if_url.c revision 1.65 1 1.65 msaitoh /* $NetBSD: if_url.c,v 1.65 2019/05/28 07:41:50 msaitoh Exp $ */
2 1.43 mrg
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 2001, 2002
5 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
16 1.1 ichiro * may be used to endorse or promote products derived from this software
17 1.1 ichiro * without specific prior written permission.
18 1.1 ichiro *
19 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 ichiro * SUCH DAMAGE.
30 1.1 ichiro *
31 1.1 ichiro */
32 1.1 ichiro
33 1.1 ichiro /*
34 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
35 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
37 1.1 ichiro */
38 1.1 ichiro
39 1.1 ichiro /*
40 1.1 ichiro * TODO:
41 1.1 ichiro * Interrupt Endpoint support
42 1.1 ichiro * External PHYs
43 1.1 ichiro * powerhook() support?
44 1.1 ichiro */
45 1.1 ichiro
46 1.1 ichiro #include <sys/cdefs.h>
47 1.65 msaitoh __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.65 2019/05/28 07:41:50 msaitoh Exp $");
48 1.1 ichiro
49 1.46 christos #ifdef _KERNEL_OPT
50 1.1 ichiro #include "opt_inet.h"
51 1.54 skrll #include "opt_usb.h"
52 1.46 christos #endif
53 1.1 ichiro
54 1.1 ichiro #include <sys/param.h>
55 1.1 ichiro #include <sys/systm.h>
56 1.27 xtraeme #include <sys/rwlock.h>
57 1.1 ichiro #include <sys/mbuf.h>
58 1.1 ichiro #include <sys/kernel.h>
59 1.1 ichiro #include <sys/socket.h>
60 1.1 ichiro
61 1.1 ichiro #include <sys/device.h>
62 1.49 riastrad #include <sys/rndsource.h>
63 1.1 ichiro
64 1.1 ichiro #include <net/if.h>
65 1.1 ichiro #include <net/if_arp.h>
66 1.1 ichiro #include <net/if_dl.h>
67 1.1 ichiro #include <net/if_media.h>
68 1.1 ichiro
69 1.1 ichiro #include <net/bpf.h>
70 1.1 ichiro
71 1.1 ichiro #include <net/if_ether.h>
72 1.1 ichiro #ifdef INET
73 1.1 ichiro #include <netinet/in.h>
74 1.1 ichiro #include <netinet/if_inarp.h>
75 1.1 ichiro #endif
76 1.1 ichiro
77 1.1 ichiro #include <dev/mii/mii.h>
78 1.1 ichiro #include <dev/mii/miivar.h>
79 1.1 ichiro #include <dev/mii/urlphyreg.h>
80 1.1 ichiro
81 1.1 ichiro #include <dev/usb/usb.h>
82 1.1 ichiro #include <dev/usb/usbdi.h>
83 1.1 ichiro #include <dev/usb/usbdi_util.h>
84 1.1 ichiro #include <dev/usb/usbdevs.h>
85 1.1 ichiro
86 1.1 ichiro #include <dev/usb/if_urlreg.h>
87 1.1 ichiro
88 1.1 ichiro
89 1.1 ichiro /* Function declarations */
90 1.53 msaitoh int url_match(device_t, cfdata_t, void *);
91 1.53 msaitoh void url_attach(device_t, device_t, void *);
92 1.53 msaitoh int url_detach(device_t, int);
93 1.53 msaitoh int url_activate(device_t, enum devact);
94 1.63 mrg
95 1.53 msaitoh CFATTACH_DECL_NEW(url, sizeof(struct url_softc), url_match, url_attach,
96 1.53 msaitoh url_detach, url_activate);
97 1.1 ichiro
98 1.1 ichiro Static int url_openpipes(struct url_softc *);
99 1.1 ichiro Static int url_rx_list_init(struct url_softc *);
100 1.1 ichiro Static int url_tx_list_init(struct url_softc *);
101 1.1 ichiro Static int url_newbuf(struct url_softc *, struct url_chain *, struct mbuf *);
102 1.1 ichiro Static void url_start(struct ifnet *);
103 1.1 ichiro Static int url_send(struct url_softc *, struct mbuf *, int);
104 1.51 skrll Static void url_txeof(struct usbd_xfer *, void *, usbd_status);
105 1.51 skrll Static void url_rxeof(struct usbd_xfer *, void *, usbd_status);
106 1.1 ichiro Static void url_tick(void *);
107 1.1 ichiro Static void url_tick_task(void *);
108 1.25 christos Static int url_ioctl(struct ifnet *, u_long, void *);
109 1.1 ichiro Static void url_stop_task(struct url_softc *);
110 1.1 ichiro Static void url_stop(struct ifnet *, int);
111 1.1 ichiro Static void url_watchdog(struct ifnet *);
112 1.1 ichiro Static int url_ifmedia_change(struct ifnet *);
113 1.1 ichiro Static void url_ifmedia_status(struct ifnet *, struct ifmediareq *);
114 1.1 ichiro Static void url_lock_mii(struct url_softc *);
115 1.1 ichiro Static void url_unlock_mii(struct url_softc *);
116 1.61 msaitoh Static int url_int_miibus_readreg(device_t, int, int, uint16_t *);
117 1.61 msaitoh Static int url_int_miibus_writereg(device_t, int, int, uint16_t);
118 1.44 matt Static void url_miibus_statchg(struct ifnet *);
119 1.1 ichiro Static int url_init(struct ifnet *);
120 1.1 ichiro Static void url_setmulti(struct url_softc *);
121 1.1 ichiro Static void url_reset(struct url_softc *);
122 1.1 ichiro
123 1.1 ichiro Static int url_csr_read_1(struct url_softc *, int);
124 1.1 ichiro Static int url_csr_read_2(struct url_softc *, int);
125 1.1 ichiro Static int url_csr_write_1(struct url_softc *, int, int);
126 1.1 ichiro Static int url_csr_write_2(struct url_softc *, int, int);
127 1.1 ichiro Static int url_csr_write_4(struct url_softc *, int, int);
128 1.1 ichiro Static int url_mem(struct url_softc *, int, int, void *, int);
129 1.1 ichiro
130 1.1 ichiro /* Macros */
131 1.1 ichiro #ifdef URL_DEBUG
132 1.38 dyoung #define DPRINTF(x) if (urldebug) printf x
133 1.64 msaitoh #define DPRINTFN(n, x) if (urldebug >= (n)) printf x
134 1.2 ichiro int urldebug = 0;
135 1.1 ichiro #else
136 1.1 ichiro #define DPRINTF(x)
137 1.64 msaitoh #define DPRINTFN(n, x)
138 1.1 ichiro #endif
139 1.1 ichiro
140 1.1 ichiro #define URL_SETBIT(sc, reg, x) \
141 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
142 1.1 ichiro
143 1.1 ichiro #define URL_SETBIT2(sc, reg, x) \
144 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
145 1.1 ichiro
146 1.1 ichiro #define URL_CLRBIT(sc, reg, x) \
147 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
148 1.1 ichiro
149 1.1 ichiro #define URL_CLRBIT2(sc, reg, x) \
150 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
151 1.1 ichiro
152 1.1 ichiro static const struct url_type {
153 1.1 ichiro struct usb_devno url_dev;
154 1.51 skrll uint16_t url_flags;
155 1.1 ichiro #define URL_EXT_PHY 0x0001
156 1.1 ichiro } url_devs [] = {
157 1.1 ichiro /* MELCO LUA-KTX */
158 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
159 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
160 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
161 1.11 augustss /* Longshine LCS-8138TX */
162 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
163 1.11 augustss /* Micronet SP128AR */
164 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
165 1.13 itojun /* OQO model 01 */
166 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
167 1.1 ichiro };
168 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
169 1.1 ichiro
170 1.1 ichiro
171 1.1 ichiro /* Probe */
172 1.46 christos int
173 1.38 dyoung url_match(device_t parent, cfdata_t match, void *aux)
174 1.1 ichiro {
175 1.38 dyoung struct usb_attach_arg *uaa = aux;
176 1.1 ichiro
177 1.51 skrll return url_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ?
178 1.51 skrll UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
179 1.1 ichiro }
180 1.1 ichiro /* Attach */
181 1.46 christos void
182 1.38 dyoung url_attach(device_t parent, device_t self, void *aux)
183 1.1 ichiro {
184 1.38 dyoung struct url_softc *sc = device_private(self);
185 1.38 dyoung struct usb_attach_arg *uaa = aux;
186 1.51 skrll struct usbd_device *dev = uaa->uaa_device;
187 1.51 skrll struct usbd_interface *iface;
188 1.1 ichiro usbd_status err;
189 1.1 ichiro usb_interface_descriptor_t *id;
190 1.1 ichiro usb_endpoint_descriptor_t *ed;
191 1.16 augustss char *devinfop;
192 1.1 ichiro struct ifnet *ifp;
193 1.1 ichiro struct mii_data *mii;
194 1.1 ichiro u_char eaddr[ETHER_ADDR_LEN];
195 1.1 ichiro int i, s;
196 1.1 ichiro
197 1.32 cube sc->sc_dev = self;
198 1.32 cube
199 1.34 plunky aprint_naive("\n");
200 1.34 plunky aprint_normal("\n");
201 1.34 plunky
202 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
203 1.32 cube aprint_normal_dev(self, "%s\n", devinfop);
204 1.16 augustss usbd_devinfo_free(devinfop);
205 1.1 ichiro
206 1.1 ichiro /* Move the device into the configured state. */
207 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
208 1.1 ichiro if (err) {
209 1.45 skrll aprint_error_dev(self, "failed to set configuration"
210 1.45 skrll ", err=%s\n", usbd_errstr(err));
211 1.1 ichiro goto bad;
212 1.1 ichiro }
213 1.1 ichiro
214 1.47 jmcneill usb_init_task(&sc->sc_tick_task, url_tick_task, sc, 0);
215 1.27 xtraeme rw_init(&sc->sc_mii_rwlock);
216 1.47 jmcneill usb_init_task(&sc->sc_stop_task, (void (*)(void *))url_stop_task, sc, 0);
217 1.1 ichiro
218 1.1 ichiro /* get control interface */
219 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
220 1.1 ichiro if (err) {
221 1.32 cube aprint_error_dev(self, "failed to get interface, err=%s\n",
222 1.1 ichiro usbd_errstr(err));
223 1.1 ichiro goto bad;
224 1.1 ichiro }
225 1.1 ichiro
226 1.1 ichiro sc->sc_udev = dev;
227 1.1 ichiro sc->sc_ctl_iface = iface;
228 1.51 skrll sc->sc_flags = url_lookup(uaa->uaa_vendor, uaa->uaa_product)->url_flags;
229 1.1 ichiro
230 1.1 ichiro /* get interface descriptor */
231 1.1 ichiro id = usbd_get_interface_descriptor(sc->sc_ctl_iface);
232 1.1 ichiro
233 1.1 ichiro /* find endpoints */
234 1.1 ichiro sc->sc_bulkin_no = sc->sc_bulkout_no = sc->sc_intrin_no = -1;
235 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
236 1.1 ichiro ed = usbd_interface2endpoint_descriptor(sc->sc_ctl_iface, i);
237 1.1 ichiro if (ed == NULL) {
238 1.32 cube aprint_error_dev(self,
239 1.32 cube "couldn't get endpoint %d\n", i);
240 1.1 ichiro goto bad;
241 1.1 ichiro }
242 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
243 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
244 1.1 ichiro sc->sc_bulkin_no = ed->bEndpointAddress; /* RX */
245 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
246 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
247 1.1 ichiro sc->sc_bulkout_no = ed->bEndpointAddress; /* TX */
248 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
249 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
250 1.1 ichiro sc->sc_intrin_no = ed->bEndpointAddress; /* Status */
251 1.1 ichiro }
252 1.1 ichiro
253 1.1 ichiro if (sc->sc_bulkin_no == -1 || sc->sc_bulkout_no == -1 ||
254 1.1 ichiro sc->sc_intrin_no == -1) {
255 1.32 cube aprint_error_dev(self, "missing endpoint\n");
256 1.1 ichiro goto bad;
257 1.1 ichiro }
258 1.1 ichiro
259 1.1 ichiro s = splnet();
260 1.1 ichiro
261 1.1 ichiro /* reset the adapter */
262 1.1 ichiro url_reset(sc);
263 1.1 ichiro
264 1.1 ichiro /* Get Ethernet Address */
265 1.1 ichiro err = url_mem(sc, URL_CMD_READMEM, URL_IDR0, (void *)eaddr,
266 1.1 ichiro ETHER_ADDR_LEN);
267 1.1 ichiro if (err) {
268 1.32 cube aprint_error_dev(self, "read MAC address failed\n");
269 1.1 ichiro splx(s);
270 1.1 ichiro goto bad;
271 1.1 ichiro }
272 1.1 ichiro
273 1.1 ichiro /* Print Ethernet Address */
274 1.32 cube aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
275 1.1 ichiro
276 1.19 wiz /* initialize interface information */
277 1.1 ichiro ifp = GET_IFP(sc);
278 1.1 ichiro ifp->if_softc = sc;
279 1.3 augustss ifp->if_mtu = ETHERMTU;
280 1.56 maya strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
281 1.1 ichiro ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
282 1.1 ichiro ifp->if_start = url_start;
283 1.1 ichiro ifp->if_ioctl = url_ioctl;
284 1.1 ichiro ifp->if_watchdog = url_watchdog;
285 1.1 ichiro ifp->if_init = url_init;
286 1.1 ichiro ifp->if_stop = url_stop;
287 1.1 ichiro
288 1.1 ichiro IFQ_SET_READY(&ifp->if_snd);
289 1.1 ichiro
290 1.1 ichiro /*
291 1.1 ichiro * Do ifmedia setup.
292 1.1 ichiro */
293 1.1 ichiro mii = &sc->sc_mii;
294 1.1 ichiro mii->mii_ifp = ifp;
295 1.1 ichiro mii->mii_readreg = url_int_miibus_readreg;
296 1.1 ichiro mii->mii_writereg = url_int_miibus_writereg;
297 1.1 ichiro #if 0
298 1.1 ichiro if (sc->sc_flags & URL_EXT_PHY) {
299 1.1 ichiro mii->mii_readreg = url_ext_miibus_readreg;
300 1.1 ichiro mii->mii_writereg = url_ext_miibus_writereg;
301 1.1 ichiro }
302 1.1 ichiro #endif
303 1.1 ichiro mii->mii_statchg = url_miibus_statchg;
304 1.1 ichiro mii->mii_flags = MIIF_AUTOTSLEEP;
305 1.30 dyoung sc->sc_ec.ec_mii = mii;
306 1.1 ichiro ifmedia_init(&mii->mii_media, 0,
307 1.1 ichiro url_ifmedia_change, url_ifmedia_status);
308 1.1 ichiro mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
309 1.1 ichiro if (LIST_FIRST(&mii->mii_phys) == NULL) {
310 1.1 ichiro ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
311 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
312 1.1 ichiro } else
313 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
314 1.1 ichiro
315 1.1 ichiro /* attach the interface */
316 1.1 ichiro if_attach(ifp);
317 1.38 dyoung ether_ifattach(ifp, eaddr);
318 1.1 ichiro
319 1.32 cube rnd_attach_source(&sc->rnd_source, device_xname(self),
320 1.48 tls RND_TYPE_NET, RND_FLAG_DEFAULT);
321 1.1 ichiro
322 1.38 dyoung callout_init(&sc->sc_stat_ch, 0);
323 1.1 ichiro sc->sc_attached = 1;
324 1.1 ichiro splx(s);
325 1.1 ichiro
326 1.38 dyoung usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, dev, sc->sc_dev);
327 1.1 ichiro
328 1.62 msaitoh if (!pmf_device_register(self, NULL, NULL))
329 1.62 msaitoh aprint_error_dev(self, "couldn't establish power handler\n");
330 1.62 msaitoh
331 1.38 dyoung return;
332 1.1 ichiro
333 1.1 ichiro bad:
334 1.1 ichiro sc->sc_dying = 1;
335 1.38 dyoung return;
336 1.1 ichiro }
337 1.1 ichiro
338 1.1 ichiro /* detach */
339 1.46 christos int
340 1.38 dyoung url_detach(device_t self, int flags)
341 1.1 ichiro {
342 1.38 dyoung struct url_softc *sc = device_private(self);
343 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
344 1.1 ichiro int s;
345 1.1 ichiro
346 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
347 1.1 ichiro
348 1.1 ichiro /* Detached before attached finished */
349 1.1 ichiro if (!sc->sc_attached)
350 1.51 skrll return 0;
351 1.1 ichiro
352 1.62 msaitoh pmf_device_deregister(self);
353 1.62 msaitoh
354 1.59 riastrad /*
355 1.59 riastrad * XXX Halting callout guarantees no more tick tasks. What
356 1.59 riastrad * guarantees no more stop tasks? What guarantees no more
357 1.59 riastrad * calls to url_send? Don't we need to wait for if_detach or
358 1.59 riastrad * something? Should set sc->sc_dying here? Is device
359 1.59 riastrad * deactivation guaranteed to have already happened?
360 1.59 riastrad */
361 1.59 riastrad callout_halt(&sc->sc_stat_ch, NULL);
362 1.1 ichiro
363 1.1 ichiro /* Remove any pending tasks */
364 1.60 riastrad usb_rem_task_wait(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER,
365 1.60 riastrad NULL);
366 1.60 riastrad usb_rem_task_wait(sc->sc_udev, &sc->sc_stop_task, USB_TASKQ_DRIVER,
367 1.60 riastrad NULL);
368 1.1 ichiro
369 1.1 ichiro s = splusb();
370 1.1 ichiro
371 1.1 ichiro if (--sc->sc_refcnt >= 0) {
372 1.1 ichiro /* Wait for processes to go away */
373 1.42 mrg usb_detach_waitold(sc->sc_dev);
374 1.1 ichiro }
375 1.1 ichiro
376 1.1 ichiro if (ifp->if_flags & IFF_RUNNING)
377 1.1 ichiro url_stop(GET_IFP(sc), 1);
378 1.1 ichiro
379 1.1 ichiro rnd_detach_source(&sc->rnd_source);
380 1.1 ichiro mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
381 1.1 ichiro ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
382 1.1 ichiro ether_ifdetach(ifp);
383 1.1 ichiro if_detach(ifp);
384 1.1 ichiro
385 1.1 ichiro #ifdef DIAGNOSTIC
386 1.1 ichiro if (sc->sc_pipe_tx != NULL)
387 1.32 cube aprint_debug_dev(self, "detach has active tx endpoint.\n");
388 1.1 ichiro if (sc->sc_pipe_rx != NULL)
389 1.32 cube aprint_debug_dev(self, "detach has active rx endpoint.\n");
390 1.1 ichiro if (sc->sc_pipe_intr != NULL)
391 1.32 cube aprint_debug_dev(self, "detach has active intr endpoint.\n");
392 1.1 ichiro #endif
393 1.1 ichiro
394 1.1 ichiro sc->sc_attached = 0;
395 1.1 ichiro
396 1.1 ichiro splx(s);
397 1.1 ichiro
398 1.28 xtraeme rw_destroy(&sc->sc_mii_rwlock);
399 1.53 msaitoh usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev);
400 1.1 ichiro
401 1.51 skrll return 0;
402 1.1 ichiro }
403 1.1 ichiro
404 1.1 ichiro /* read/write memory */
405 1.1 ichiro Static int
406 1.1 ichiro url_mem(struct url_softc *sc, int cmd, int offset, void *buf, int len)
407 1.1 ichiro {
408 1.1 ichiro usb_device_request_t req;
409 1.1 ichiro usbd_status err;
410 1.1 ichiro
411 1.1 ichiro if (sc == NULL)
412 1.51 skrll return 0;
413 1.1 ichiro
414 1.1 ichiro DPRINTFN(0x200,
415 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
416 1.1 ichiro
417 1.1 ichiro if (sc->sc_dying)
418 1.51 skrll return 0;
419 1.1 ichiro
420 1.1 ichiro if (cmd == URL_CMD_READMEM)
421 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
422 1.1 ichiro else
423 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
424 1.1 ichiro req.bRequest = URL_REQ_MEM;
425 1.1 ichiro USETW(req.wValue, offset);
426 1.1 ichiro USETW(req.wIndex, 0x0000);
427 1.1 ichiro USETW(req.wLength, len);
428 1.1 ichiro
429 1.1 ichiro sc->sc_refcnt++;
430 1.1 ichiro err = usbd_do_request(sc->sc_udev, &req, buf);
431 1.1 ichiro if (--sc->sc_refcnt < 0)
432 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
433 1.1 ichiro if (err) {
434 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
435 1.38 dyoung device_xname(sc->sc_dev),
436 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
437 1.1 ichiro offset, err));
438 1.5 augustss }
439 1.1 ichiro
440 1.51 skrll return err;
441 1.1 ichiro }
442 1.1 ichiro
443 1.1 ichiro /* read 1byte from register */
444 1.1 ichiro Static int
445 1.1 ichiro url_csr_read_1(struct url_softc *sc, int reg)
446 1.1 ichiro {
447 1.51 skrll uint8_t val = 0;
448 1.1 ichiro
449 1.1 ichiro DPRINTFN(0x100,
450 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
451 1.1 ichiro
452 1.1 ichiro if (sc->sc_dying)
453 1.51 skrll return 0;
454 1.5 augustss
455 1.51 skrll return url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val;
456 1.1 ichiro }
457 1.1 ichiro
458 1.1 ichiro /* read 2bytes from register */
459 1.1 ichiro Static int
460 1.1 ichiro url_csr_read_2(struct url_softc *sc, int reg)
461 1.1 ichiro {
462 1.1 ichiro uWord val;
463 1.1 ichiro
464 1.1 ichiro DPRINTFN(0x100,
465 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
466 1.1 ichiro
467 1.1 ichiro if (sc->sc_dying)
468 1.51 skrll return 0;
469 1.5 augustss
470 1.1 ichiro USETW(val, 0);
471 1.51 skrll return url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val);
472 1.1 ichiro }
473 1.1 ichiro
474 1.1 ichiro /* write 1byte to register */
475 1.1 ichiro Static int
476 1.1 ichiro url_csr_write_1(struct url_softc *sc, int reg, int aval)
477 1.1 ichiro {
478 1.51 skrll uint8_t val = aval;
479 1.1 ichiro
480 1.1 ichiro DPRINTFN(0x100,
481 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
482 1.1 ichiro
483 1.1 ichiro if (sc->sc_dying)
484 1.51 skrll return 0;
485 1.5 augustss
486 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0;
487 1.1 ichiro }
488 1.1 ichiro
489 1.1 ichiro /* write 2bytes to register */
490 1.1 ichiro Static int
491 1.1 ichiro url_csr_write_2(struct url_softc *sc, int reg, int aval)
492 1.1 ichiro {
493 1.1 ichiro uWord val;
494 1.1 ichiro
495 1.1 ichiro DPRINTFN(0x100,
496 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
497 1.1 ichiro
498 1.1 ichiro USETW(val, aval);
499 1.1 ichiro
500 1.1 ichiro if (sc->sc_dying)
501 1.51 skrll return 0;
502 1.5 augustss
503 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0;
504 1.1 ichiro }
505 1.1 ichiro
506 1.1 ichiro /* write 4bytes to register */
507 1.1 ichiro Static int
508 1.1 ichiro url_csr_write_4(struct url_softc *sc, int reg, int aval)
509 1.1 ichiro {
510 1.1 ichiro uDWord val;
511 1.1 ichiro
512 1.1 ichiro DPRINTFN(0x100,
513 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
514 1.1 ichiro
515 1.1 ichiro USETDW(val, aval);
516 1.1 ichiro
517 1.1 ichiro if (sc->sc_dying)
518 1.51 skrll return 0;
519 1.5 augustss
520 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0;
521 1.1 ichiro }
522 1.1 ichiro
523 1.1 ichiro Static int
524 1.1 ichiro url_init(struct ifnet *ifp)
525 1.1 ichiro {
526 1.1 ichiro struct url_softc *sc = ifp->if_softc;
527 1.1 ichiro struct mii_data *mii = GET_MII(sc);
528 1.29 dyoung const u_char *eaddr;
529 1.30 dyoung int i, rc, s;
530 1.1 ichiro
531 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
532 1.5 augustss
533 1.1 ichiro if (sc->sc_dying)
534 1.51 skrll return EIO;
535 1.1 ichiro
536 1.1 ichiro s = splnet();
537 1.1 ichiro
538 1.1 ichiro /* Cancel pending I/O and free all TX/RX buffers */
539 1.1 ichiro url_stop(ifp, 1);
540 1.1 ichiro
541 1.29 dyoung eaddr = CLLADDR(ifp->if_sadl);
542 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
543 1.1 ichiro url_csr_write_1(sc, URL_IDR0 + i, eaddr[i]);
544 1.1 ichiro
545 1.1 ichiro /* Init transmission control register */
546 1.1 ichiro URL_CLRBIT(sc, URL_TCR,
547 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
548 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
549 1.1 ichiro URL_TCR_NOCRC);
550 1.1 ichiro
551 1.1 ichiro /* Init receive control register */
552 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
553 1.1 ichiro if (ifp->if_flags & IFF_BROADCAST)
554 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AB);
555 1.1 ichiro else
556 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AB);
557 1.1 ichiro
558 1.1 ichiro /* If we want promiscuous mode, accept all physical frames. */
559 1.1 ichiro if (ifp->if_flags & IFF_PROMISC)
560 1.64 msaitoh URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
561 1.1 ichiro else
562 1.64 msaitoh URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
563 1.1 ichiro
564 1.5 augustss
565 1.1 ichiro /* Load the multicast filter */
566 1.1 ichiro url_setmulti(sc);
567 1.1 ichiro
568 1.1 ichiro /* Enable RX and TX */
569 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_TE | URL_CR_RE);
570 1.1 ichiro
571 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
572 1.30 dyoung rc = 0;
573 1.30 dyoung else if (rc != 0)
574 1.30 dyoung goto out;
575 1.1 ichiro
576 1.1 ichiro if (sc->sc_pipe_tx == NULL || sc->sc_pipe_rx == NULL) {
577 1.1 ichiro if (url_openpipes(sc)) {
578 1.1 ichiro splx(s);
579 1.51 skrll return EIO;
580 1.1 ichiro }
581 1.1 ichiro }
582 1.51 skrll /* Initialize transmit ring */
583 1.51 skrll if (url_tx_list_init(sc)) {
584 1.51 skrll printf("%s: tx list init failed\n", device_xname(sc->sc_dev));
585 1.51 skrll splx(s);
586 1.51 skrll return EIO;
587 1.51 skrll }
588 1.51 skrll
589 1.51 skrll /* Initialize receive ring */
590 1.51 skrll if (url_rx_list_init(sc)) {
591 1.51 skrll printf("%s: rx list init failed\n", device_xname(sc->sc_dev));
592 1.51 skrll splx(s);
593 1.51 skrll return EIO;
594 1.51 skrll }
595 1.51 skrll /* Start up the receive pipe. */
596 1.51 skrll for (i = 0; i < URL_RX_LIST_CNT; i++) {
597 1.51 skrll struct url_chain *c = &sc->sc_cdata.url_rx_chain[i];
598 1.51 skrll
599 1.51 skrll usbd_setup_xfer(c->url_xfer, c, c->url_buf, URL_BUFSZ,
600 1.51 skrll USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, url_rxeof);
601 1.51 skrll (void)usbd_transfer(c->url_xfer);
602 1.51 skrll DPRINTF(("%s: %s: start read\n", device_xname(sc->sc_dev),
603 1.51 skrll __func__));
604 1.51 skrll }
605 1.1 ichiro
606 1.1 ichiro ifp->if_flags |= IFF_RUNNING;
607 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
608 1.1 ichiro
609 1.38 dyoung callout_reset(&sc->sc_stat_ch, hz, url_tick, sc);
610 1.1 ichiro
611 1.30 dyoung out:
612 1.30 dyoung splx(s);
613 1.30 dyoung return rc;
614 1.1 ichiro }
615 1.1 ichiro
616 1.1 ichiro Static void
617 1.1 ichiro url_reset(struct url_softc *sc)
618 1.1 ichiro {
619 1.1 ichiro int i;
620 1.5 augustss
621 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
622 1.1 ichiro
623 1.1 ichiro if (sc->sc_dying)
624 1.1 ichiro return;
625 1.1 ichiro
626 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_SOFT_RST);
627 1.1 ichiro
628 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
629 1.1 ichiro if (!(url_csr_read_1(sc, URL_CR) & URL_CR_SOFT_RST))
630 1.1 ichiro break;
631 1.1 ichiro delay(10); /* XXX */
632 1.1 ichiro }
633 1.1 ichiro
634 1.1 ichiro delay(10000); /* XXX */
635 1.1 ichiro }
636 1.1 ichiro
637 1.1 ichiro int
638 1.38 dyoung url_activate(device_t self, enum devact act)
639 1.1 ichiro {
640 1.32 cube struct url_softc *sc = device_private(self);
641 1.1 ichiro
642 1.38 dyoung DPRINTF(("%s: %s: enter, act=%d\n", device_xname(sc->sc_dev),
643 1.4 augustss __func__, act));
644 1.1 ichiro
645 1.1 ichiro switch (act) {
646 1.1 ichiro case DVACT_DEACTIVATE:
647 1.1 ichiro if_deactivate(&sc->sc_ec.ec_if);
648 1.1 ichiro sc->sc_dying = 1;
649 1.35 dyoung return 0;
650 1.35 dyoung default:
651 1.35 dyoung return EOPNOTSUPP;
652 1.1 ichiro }
653 1.1 ichiro }
654 1.1 ichiro
655 1.1 ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
656 1.1 ichiro
657 1.1 ichiro
658 1.1 ichiro Static void
659 1.1 ichiro url_setmulti(struct url_softc *sc)
660 1.1 ichiro {
661 1.65 msaitoh struct ethercom *ec = &sc->sc_ec;
662 1.1 ichiro struct ifnet *ifp;
663 1.1 ichiro struct ether_multi *enm;
664 1.1 ichiro struct ether_multistep step;
665 1.51 skrll uint32_t hashes[2] = { 0, 0 };
666 1.1 ichiro int h = 0;
667 1.1 ichiro int mcnt = 0;
668 1.1 ichiro
669 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
670 1.1 ichiro
671 1.1 ichiro if (sc->sc_dying)
672 1.1 ichiro return;
673 1.1 ichiro
674 1.1 ichiro ifp = GET_IFP(sc);
675 1.1 ichiro
676 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
677 1.64 msaitoh URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
678 1.1 ichiro return;
679 1.1 ichiro } else if (ifp->if_flags & IFF_ALLMULTI) {
680 1.65 msaitoh allmulti:
681 1.1 ichiro ifp->if_flags |= IFF_ALLMULTI;
682 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM);
683 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAP);
684 1.1 ichiro return;
685 1.1 ichiro }
686 1.1 ichiro
687 1.1 ichiro /* first, zot all the existing hash bits */
688 1.1 ichiro url_csr_write_4(sc, URL_MAR0, 0);
689 1.1 ichiro url_csr_write_4(sc, URL_MAR4, 0);
690 1.1 ichiro
691 1.1 ichiro /* now program new ones */
692 1.65 msaitoh ETHER_LOCK(ec);
693 1.65 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
694 1.1 ichiro while (enm != NULL) {
695 1.1 ichiro if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
696 1.65 msaitoh ETHER_ADDR_LEN) != 0) {
697 1.65 msaitoh ETHER_UNLOCK(ec);
698 1.1 ichiro goto allmulti;
699 1.65 msaitoh }
700 1.1 ichiro
701 1.1 ichiro h = url_calchash(enm->enm_addrlo);
702 1.1 ichiro if (h < 32)
703 1.1 ichiro hashes[0] |= (1 << h);
704 1.1 ichiro else
705 1.1 ichiro hashes[1] |= (1 << (h -32));
706 1.1 ichiro mcnt++;
707 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
708 1.1 ichiro }
709 1.65 msaitoh ETHER_UNLOCK(ec);
710 1.1 ichiro
711 1.1 ichiro ifp->if_flags &= ~IFF_ALLMULTI;
712 1.1 ichiro
713 1.64 msaitoh URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
714 1.1 ichiro
715 1.64 msaitoh if (mcnt) {
716 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AM);
717 1.1 ichiro } else {
718 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AM);
719 1.1 ichiro }
720 1.1 ichiro url_csr_write_4(sc, URL_MAR0, hashes[0]);
721 1.1 ichiro url_csr_write_4(sc, URL_MAR4, hashes[1]);
722 1.1 ichiro }
723 1.1 ichiro
724 1.1 ichiro Static int
725 1.1 ichiro url_openpipes(struct url_softc *sc)
726 1.1 ichiro {
727 1.1 ichiro usbd_status err;
728 1.1 ichiro int error = 0;
729 1.1 ichiro
730 1.1 ichiro if (sc->sc_dying)
731 1.51 skrll return EIO;
732 1.5 augustss
733 1.1 ichiro sc->sc_refcnt++;
734 1.1 ichiro
735 1.1 ichiro /* Open RX pipe */
736 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkin_no,
737 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_rx);
738 1.1 ichiro if (err) {
739 1.1 ichiro printf("%s: open rx pipe failed: %s\n",
740 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
741 1.1 ichiro error = EIO;
742 1.1 ichiro goto done;
743 1.1 ichiro }
744 1.5 augustss
745 1.1 ichiro /* Open TX pipe */
746 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkout_no,
747 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_tx);
748 1.1 ichiro if (err) {
749 1.1 ichiro printf("%s: open tx pipe failed: %s\n",
750 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
751 1.1 ichiro error = EIO;
752 1.1 ichiro goto done;
753 1.1 ichiro }
754 1.1 ichiro
755 1.1 ichiro #if 0
756 1.1 ichiro /* XXX: interrupt endpoint is not yet supported */
757 1.1 ichiro /* Open Interrupt pipe */
758 1.1 ichiro err = usbd_open_pipe_intr(sc->sc_ctl_iface, sc->sc_intrin_no,
759 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_intr, sc,
760 1.1 ichiro &sc->sc_cdata.url_ibuf, URL_INTR_PKGLEN,
761 1.24 drochner url_intr, USBD_DEFAULT_INTERVAL);
762 1.1 ichiro if (err) {
763 1.1 ichiro printf("%s: open intr pipe failed: %s\n",
764 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
765 1.1 ichiro error = EIO;
766 1.1 ichiro goto done;
767 1.1 ichiro }
768 1.1 ichiro #endif
769 1.1 ichiro
770 1.1 ichiro done:
771 1.1 ichiro if (--sc->sc_refcnt < 0)
772 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
773 1.5 augustss
774 1.51 skrll return error;
775 1.1 ichiro }
776 1.1 ichiro
777 1.1 ichiro Static int
778 1.1 ichiro url_newbuf(struct url_softc *sc, struct url_chain *c, struct mbuf *m)
779 1.1 ichiro {
780 1.1 ichiro struct mbuf *m_new = NULL;
781 1.1 ichiro
782 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
783 1.1 ichiro
784 1.1 ichiro if (m == NULL) {
785 1.1 ichiro MGETHDR(m_new, M_DONTWAIT, MT_DATA);
786 1.1 ichiro if (m_new == NULL) {
787 1.1 ichiro printf("%s: no memory for rx list "
788 1.38 dyoung "-- packet dropped!\n", device_xname(sc->sc_dev));
789 1.51 skrll return ENOBUFS;
790 1.1 ichiro }
791 1.1 ichiro MCLGET(m_new, M_DONTWAIT);
792 1.1 ichiro if (!(m_new->m_flags & M_EXT)) {
793 1.1 ichiro printf("%s: no memory for rx list "
794 1.38 dyoung "-- packet dropped!\n", device_xname(sc->sc_dev));
795 1.1 ichiro m_freem(m_new);
796 1.51 skrll return ENOBUFS;
797 1.1 ichiro }
798 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
799 1.1 ichiro } else {
800 1.1 ichiro m_new = m;
801 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
802 1.1 ichiro m_new->m_data = m_new->m_ext.ext_buf;
803 1.1 ichiro }
804 1.1 ichiro
805 1.1 ichiro m_adj(m_new, ETHER_ALIGN);
806 1.1 ichiro c->url_mbuf = m_new;
807 1.1 ichiro
808 1.51 skrll return 0;
809 1.1 ichiro }
810 1.5 augustss
811 1.1 ichiro
812 1.1 ichiro Static int
813 1.1 ichiro url_rx_list_init(struct url_softc *sc)
814 1.1 ichiro {
815 1.1 ichiro struct url_cdata *cd;
816 1.1 ichiro struct url_chain *c;
817 1.1 ichiro int i;
818 1.1 ichiro
819 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
820 1.1 ichiro
821 1.1 ichiro cd = &sc->sc_cdata;
822 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
823 1.1 ichiro c = &cd->url_rx_chain[i];
824 1.1 ichiro c->url_sc = sc;
825 1.1 ichiro c->url_idx = i;
826 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS)
827 1.51 skrll return ENOBUFS;
828 1.1 ichiro if (c->url_xfer == NULL) {
829 1.51 skrll int error = usbd_create_xfer(sc->sc_pipe_rx, URL_BUFSZ,
830 1.57 skrll 0, 0, &c->url_xfer);
831 1.51 skrll if (error)
832 1.51 skrll return error;
833 1.51 skrll c->url_buf = usbd_get_buffer(c->url_xfer);
834 1.1 ichiro }
835 1.1 ichiro }
836 1.5 augustss
837 1.51 skrll return 0;
838 1.1 ichiro }
839 1.1 ichiro
840 1.1 ichiro Static int
841 1.1 ichiro url_tx_list_init(struct url_softc *sc)
842 1.1 ichiro {
843 1.1 ichiro struct url_cdata *cd;
844 1.1 ichiro struct url_chain *c;
845 1.1 ichiro int i;
846 1.1 ichiro
847 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
848 1.1 ichiro
849 1.1 ichiro cd = &sc->sc_cdata;
850 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
851 1.1 ichiro c = &cd->url_tx_chain[i];
852 1.1 ichiro c->url_sc = sc;
853 1.1 ichiro c->url_idx = i;
854 1.1 ichiro c->url_mbuf = NULL;
855 1.1 ichiro if (c->url_xfer == NULL) {
856 1.51 skrll int error = usbd_create_xfer(sc->sc_pipe_tx, URL_BUFSZ,
857 1.51 skrll USBD_FORCE_SHORT_XFER, 0, &c->url_xfer);
858 1.51 skrll if (error)
859 1.51 skrll return error;
860 1.51 skrll c->url_buf = usbd_get_buffer(c->url_xfer);
861 1.1 ichiro }
862 1.1 ichiro }
863 1.5 augustss
864 1.51 skrll return 0;
865 1.1 ichiro }
866 1.1 ichiro
867 1.1 ichiro Static void
868 1.1 ichiro url_start(struct ifnet *ifp)
869 1.1 ichiro {
870 1.1 ichiro struct url_softc *sc = ifp->if_softc;
871 1.1 ichiro struct mbuf *m_head = NULL;
872 1.5 augustss
873 1.38 dyoung DPRINTF(("%s: %s: enter, link=%d\n", device_xname(sc->sc_dev),
874 1.4 augustss __func__, sc->sc_link));
875 1.1 ichiro
876 1.1 ichiro if (sc->sc_dying)
877 1.1 ichiro return;
878 1.1 ichiro
879 1.1 ichiro if (!sc->sc_link)
880 1.1 ichiro return;
881 1.1 ichiro
882 1.1 ichiro if (ifp->if_flags & IFF_OACTIVE)
883 1.1 ichiro return;
884 1.1 ichiro
885 1.1 ichiro IFQ_POLL(&ifp->if_snd, m_head);
886 1.1 ichiro if (m_head == NULL)
887 1.1 ichiro return;
888 1.1 ichiro
889 1.1 ichiro if (url_send(sc, m_head, 0)) {
890 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
891 1.1 ichiro return;
892 1.1 ichiro }
893 1.1 ichiro
894 1.1 ichiro IFQ_DEQUEUE(&ifp->if_snd, m_head);
895 1.1 ichiro
896 1.58 msaitoh bpf_mtap(ifp, m_head, BPF_D_OUT);
897 1.1 ichiro
898 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
899 1.1 ichiro
900 1.1 ichiro /* Set a timeout in case the chip goes out to lunch. */
901 1.1 ichiro ifp->if_timer = 5;
902 1.1 ichiro }
903 1.1 ichiro
904 1.1 ichiro Static int
905 1.1 ichiro url_send(struct url_softc *sc, struct mbuf *m, int idx)
906 1.1 ichiro {
907 1.1 ichiro int total_len;
908 1.1 ichiro struct url_chain *c;
909 1.1 ichiro usbd_status err;
910 1.1 ichiro
911 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev),__func__));
912 1.1 ichiro
913 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[idx];
914 1.1 ichiro
915 1.1 ichiro /* Copy the mbuf data into a contiguous buffer */
916 1.1 ichiro m_copydata(m, 0, m->m_pkthdr.len, c->url_buf);
917 1.1 ichiro c->url_mbuf = m;
918 1.1 ichiro total_len = m->m_pkthdr.len;
919 1.1 ichiro
920 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
921 1.7 bouyer memset(c->url_buf + total_len, 0,
922 1.7 bouyer URL_MIN_FRAME_LEN - total_len);
923 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
924 1.7 bouyer }
925 1.64 msaitoh usbd_setup_xfer(c->url_xfer, c, c->url_buf, total_len,
926 1.51 skrll USBD_FORCE_SHORT_XFER, URL_TX_TIMEOUT, url_txeof);
927 1.1 ichiro
928 1.1 ichiro /* Transmit */
929 1.1 ichiro sc->sc_refcnt++;
930 1.1 ichiro err = usbd_transfer(c->url_xfer);
931 1.1 ichiro if (--sc->sc_refcnt < 0)
932 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
933 1.1 ichiro if (err != USBD_IN_PROGRESS) {
934 1.38 dyoung printf("%s: url_send error=%s\n", device_xname(sc->sc_dev),
935 1.1 ichiro usbd_errstr(err));
936 1.1 ichiro /* Stop the interface */
937 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_stop_task,
938 1.22 joerg USB_TASKQ_DRIVER);
939 1.51 skrll return EIO;
940 1.1 ichiro }
941 1.1 ichiro
942 1.38 dyoung DPRINTF(("%s: %s: send %d bytes\n", device_xname(sc->sc_dev),
943 1.4 augustss __func__, total_len));
944 1.1 ichiro
945 1.1 ichiro sc->sc_cdata.url_tx_cnt++;
946 1.1 ichiro
947 1.51 skrll return 0;
948 1.1 ichiro }
949 1.1 ichiro
950 1.1 ichiro Static void
951 1.51 skrll url_txeof(struct usbd_xfer *xfer, void *priv,
952 1.21 christos usbd_status status)
953 1.1 ichiro {
954 1.1 ichiro struct url_chain *c = priv;
955 1.1 ichiro struct url_softc *sc = c->url_sc;
956 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
957 1.1 ichiro int s;
958 1.1 ichiro
959 1.1 ichiro if (sc->sc_dying)
960 1.1 ichiro return;
961 1.1 ichiro
962 1.1 ichiro s = splnet();
963 1.1 ichiro
964 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
965 1.1 ichiro
966 1.1 ichiro ifp->if_timer = 0;
967 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
968 1.1 ichiro
969 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
970 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
971 1.1 ichiro splx(s);
972 1.1 ichiro return;
973 1.1 ichiro }
974 1.1 ichiro ifp->if_oerrors++;
975 1.38 dyoung printf("%s: usb error on tx: %s\n", device_xname(sc->sc_dev),
976 1.1 ichiro usbd_errstr(status));
977 1.1 ichiro if (status == USBD_STALLED) {
978 1.1 ichiro sc->sc_refcnt++;
979 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_tx);
980 1.1 ichiro if (--sc->sc_refcnt < 0)
981 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
982 1.1 ichiro }
983 1.1 ichiro splx(s);
984 1.1 ichiro return;
985 1.1 ichiro }
986 1.1 ichiro
987 1.1 ichiro ifp->if_opackets++;
988 1.1 ichiro
989 1.6 martin m_freem(c->url_mbuf);
990 1.1 ichiro c->url_mbuf = NULL;
991 1.1 ichiro
992 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
993 1.1 ichiro url_start(ifp);
994 1.1 ichiro
995 1.1 ichiro splx(s);
996 1.1 ichiro }
997 1.1 ichiro
998 1.1 ichiro Static void
999 1.51 skrll url_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1000 1.1 ichiro {
1001 1.1 ichiro struct url_chain *c = priv;
1002 1.1 ichiro struct url_softc *sc = c->url_sc;
1003 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
1004 1.1 ichiro struct mbuf *m;
1005 1.51 skrll uint32_t total_len;
1006 1.1 ichiro url_rxhdr_t rxhdr;
1007 1.1 ichiro int s;
1008 1.1 ichiro
1009 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev),__func__));
1010 1.1 ichiro
1011 1.1 ichiro if (sc->sc_dying)
1012 1.1 ichiro return;
1013 1.1 ichiro
1014 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
1015 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1016 1.1 ichiro return;
1017 1.1 ichiro sc->sc_rx_errs++;
1018 1.1 ichiro if (usbd_ratecheck(&sc->sc_rx_notice)) {
1019 1.1 ichiro printf("%s: %u usb errors on rx: %s\n",
1020 1.38 dyoung device_xname(sc->sc_dev), sc->sc_rx_errs,
1021 1.1 ichiro usbd_errstr(status));
1022 1.1 ichiro sc->sc_rx_errs = 0;
1023 1.1 ichiro }
1024 1.1 ichiro if (status == USBD_STALLED) {
1025 1.1 ichiro sc->sc_refcnt++;
1026 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_rx);
1027 1.1 ichiro if (--sc->sc_refcnt < 0)
1028 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1029 1.1 ichiro }
1030 1.1 ichiro goto done;
1031 1.1 ichiro }
1032 1.1 ichiro
1033 1.1 ichiro usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1034 1.1 ichiro
1035 1.1 ichiro memcpy(mtod(c->url_mbuf, char *), c->url_buf, total_len);
1036 1.1 ichiro
1037 1.1 ichiro if (total_len <= ETHER_CRC_LEN) {
1038 1.1 ichiro ifp->if_ierrors++;
1039 1.1 ichiro goto done;
1040 1.1 ichiro }
1041 1.1 ichiro
1042 1.1 ichiro memcpy(&rxhdr, c->url_buf + total_len - ETHER_CRC_LEN, sizeof(rxhdr));
1043 1.1 ichiro
1044 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
1045 1.38 dyoung device_xname(sc->sc_dev),
1046 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
1047 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
1048 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
1049 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
1050 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
1051 1.1 ichiro
1052 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
1053 1.1 ichiro ifp->if_ierrors++;
1054 1.1 ichiro goto done;
1055 1.1 ichiro }
1056 1.1 ichiro
1057 1.1 ichiro total_len -= ETHER_CRC_LEN;
1058 1.1 ichiro
1059 1.1 ichiro m = c->url_mbuf;
1060 1.1 ichiro m->m_pkthdr.len = m->m_len = total_len;
1061 1.52 ozaki m_set_rcvif(m, ifp);
1062 1.1 ichiro
1063 1.1 ichiro s = splnet();
1064 1.1 ichiro
1065 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS) {
1066 1.1 ichiro ifp->if_ierrors++;
1067 1.1 ichiro goto done1;
1068 1.1 ichiro }
1069 1.1 ichiro
1070 1.38 dyoung DPRINTF(("%s: %s: deliver %d\n", device_xname(sc->sc_dev),
1071 1.4 augustss __func__, m->m_len));
1072 1.50 ozaki if_percpuq_enqueue((ifp)->if_percpuq, (m));
1073 1.1 ichiro
1074 1.1 ichiro done1:
1075 1.1 ichiro splx(s);
1076 1.1 ichiro
1077 1.1 ichiro done:
1078 1.1 ichiro /* Setup new transfer */
1079 1.51 skrll usbd_setup_xfer(xfer, c, c->url_buf, URL_BUFSZ, USBD_SHORT_XFER_OK,
1080 1.51 skrll USBD_NO_TIMEOUT, url_rxeof);
1081 1.1 ichiro sc->sc_refcnt++;
1082 1.1 ichiro usbd_transfer(xfer);
1083 1.1 ichiro if (--sc->sc_refcnt < 0)
1084 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1085 1.1 ichiro
1086 1.38 dyoung DPRINTF(("%s: %s: start rx\n", device_xname(sc->sc_dev), __func__));
1087 1.1 ichiro }
1088 1.1 ichiro
1089 1.1 ichiro #if 0
1090 1.33 cegger Static void url_intr(void)
1091 1.1 ichiro {
1092 1.1 ichiro }
1093 1.1 ichiro #endif
1094 1.1 ichiro
1095 1.1 ichiro Static int
1096 1.25 christos url_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1097 1.1 ichiro {
1098 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1099 1.1 ichiro int s, error = 0;
1100 1.1 ichiro
1101 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1102 1.1 ichiro
1103 1.1 ichiro if (sc->sc_dying)
1104 1.51 skrll return EIO;
1105 1.1 ichiro
1106 1.1 ichiro s = splnet();
1107 1.1 ichiro
1108 1.30 dyoung error = ether_ioctl(ifp, cmd, data);
1109 1.30 dyoung if (error == ENETRESET) {
1110 1.30 dyoung if (ifp->if_flags & IFF_RUNNING)
1111 1.30 dyoung url_setmulti(sc);
1112 1.30 dyoung error = 0;
1113 1.1 ichiro }
1114 1.1 ichiro
1115 1.1 ichiro splx(s);
1116 1.1 ichiro
1117 1.51 skrll return error;
1118 1.1 ichiro }
1119 1.1 ichiro
1120 1.1 ichiro Static void
1121 1.1 ichiro url_watchdog(struct ifnet *ifp)
1122 1.1 ichiro {
1123 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1124 1.1 ichiro struct url_chain *c;
1125 1.1 ichiro usbd_status stat;
1126 1.1 ichiro int s;
1127 1.5 augustss
1128 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1129 1.1 ichiro
1130 1.1 ichiro ifp->if_oerrors++;
1131 1.38 dyoung printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1132 1.1 ichiro
1133 1.1 ichiro s = splusb();
1134 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[0];
1135 1.1 ichiro usbd_get_xfer_status(c->url_xfer, NULL, NULL, NULL, &stat);
1136 1.1 ichiro url_txeof(c->url_xfer, c, stat);
1137 1.1 ichiro
1138 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1139 1.1 ichiro url_start(ifp);
1140 1.1 ichiro splx(s);
1141 1.1 ichiro }
1142 1.1 ichiro
1143 1.1 ichiro Static void
1144 1.1 ichiro url_stop_task(struct url_softc *sc)
1145 1.1 ichiro {
1146 1.1 ichiro url_stop(GET_IFP(sc), 1);
1147 1.1 ichiro }
1148 1.1 ichiro
1149 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
1150 1.1 ichiro Static void
1151 1.23 christos url_stop(struct ifnet *ifp, int disable)
1152 1.1 ichiro {
1153 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1154 1.1 ichiro usbd_status err;
1155 1.1 ichiro int i;
1156 1.5 augustss
1157 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1158 1.1 ichiro
1159 1.1 ichiro ifp->if_timer = 0;
1160 1.1 ichiro
1161 1.1 ichiro url_reset(sc);
1162 1.1 ichiro
1163 1.38 dyoung callout_stop(&sc->sc_stat_ch);
1164 1.1 ichiro
1165 1.1 ichiro /* Stop transfers */
1166 1.1 ichiro /* RX endpoint */
1167 1.1 ichiro if (sc->sc_pipe_rx != NULL) {
1168 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_rx);
1169 1.1 ichiro if (err)
1170 1.1 ichiro printf("%s: abort rx pipe failed: %s\n",
1171 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1172 1.1 ichiro }
1173 1.1 ichiro
1174 1.1 ichiro /* TX endpoint */
1175 1.1 ichiro if (sc->sc_pipe_tx != NULL) {
1176 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_tx);
1177 1.1 ichiro if (err)
1178 1.1 ichiro printf("%s: abort tx pipe failed: %s\n",
1179 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1180 1.1 ichiro }
1181 1.1 ichiro
1182 1.1 ichiro #if 0
1183 1.1 ichiro /* XXX: Interrupt endpoint is not yet supported!! */
1184 1.1 ichiro /* Interrupt endpoint */
1185 1.1 ichiro if (sc->sc_pipe_intr != NULL) {
1186 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_intr);
1187 1.1 ichiro if (err)
1188 1.1 ichiro printf("%s: abort intr pipe failed: %s\n",
1189 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1190 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_intr);
1191 1.1 ichiro if (err)
1192 1.1 ichiro printf("%s: close intr pipe failed: %s\n",
1193 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1194 1.1 ichiro sc->sc_pipe_intr = NULL;
1195 1.1 ichiro }
1196 1.1 ichiro #endif
1197 1.1 ichiro
1198 1.1 ichiro /* Free RX resources. */
1199 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
1200 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_mbuf != NULL) {
1201 1.1 ichiro m_freem(sc->sc_cdata.url_rx_chain[i].url_mbuf);
1202 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_mbuf = NULL;
1203 1.1 ichiro }
1204 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_xfer != NULL) {
1205 1.51 skrll usbd_destroy_xfer(sc->sc_cdata.url_rx_chain[i].url_xfer);
1206 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_xfer = NULL;
1207 1.1 ichiro }
1208 1.1 ichiro }
1209 1.1 ichiro
1210 1.1 ichiro /* Free TX resources. */
1211 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
1212 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_mbuf != NULL) {
1213 1.1 ichiro m_freem(sc->sc_cdata.url_tx_chain[i].url_mbuf);
1214 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_mbuf = NULL;
1215 1.1 ichiro }
1216 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_xfer != NULL) {
1217 1.51 skrll usbd_destroy_xfer(sc->sc_cdata.url_tx_chain[i].url_xfer);
1218 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_xfer = NULL;
1219 1.1 ichiro }
1220 1.1 ichiro }
1221 1.1 ichiro
1222 1.51 skrll /* Close pipes */
1223 1.51 skrll /* RX endpoint */
1224 1.51 skrll if (sc->sc_pipe_rx != NULL) {
1225 1.51 skrll err = usbd_close_pipe(sc->sc_pipe_rx);
1226 1.51 skrll if (err)
1227 1.51 skrll printf("%s: close rx pipe failed: %s\n",
1228 1.51 skrll device_xname(sc->sc_dev), usbd_errstr(err));
1229 1.51 skrll sc->sc_pipe_rx = NULL;
1230 1.51 skrll }
1231 1.51 skrll
1232 1.51 skrll /* TX endpoint */
1233 1.51 skrll if (sc->sc_pipe_tx != NULL) {
1234 1.51 skrll err = usbd_close_pipe(sc->sc_pipe_tx);
1235 1.51 skrll if (err)
1236 1.51 skrll printf("%s: close tx pipe failed: %s\n",
1237 1.51 skrll device_xname(sc->sc_dev), usbd_errstr(err));
1238 1.51 skrll sc->sc_pipe_tx = NULL;
1239 1.51 skrll }
1240 1.51 skrll
1241 1.1 ichiro sc->sc_link = 0;
1242 1.1 ichiro ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1243 1.1 ichiro }
1244 1.1 ichiro
1245 1.1 ichiro /* Set media options */
1246 1.1 ichiro Static int
1247 1.1 ichiro url_ifmedia_change(struct ifnet *ifp)
1248 1.1 ichiro {
1249 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1250 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1251 1.30 dyoung int rc;
1252 1.1 ichiro
1253 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1254 1.1 ichiro
1255 1.1 ichiro if (sc->sc_dying)
1256 1.51 skrll return 0;
1257 1.1 ichiro
1258 1.1 ichiro sc->sc_link = 0;
1259 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
1260 1.30 dyoung return 0;
1261 1.30 dyoung return rc;
1262 1.1 ichiro }
1263 1.1 ichiro
1264 1.1 ichiro /* Report current media status. */
1265 1.1 ichiro Static void
1266 1.1 ichiro url_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1267 1.1 ichiro {
1268 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1269 1.1 ichiro
1270 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1271 1.1 ichiro
1272 1.1 ichiro if (sc->sc_dying)
1273 1.1 ichiro return;
1274 1.1 ichiro
1275 1.30 dyoung ether_mediastatus(ifp, ifmr);
1276 1.1 ichiro }
1277 1.1 ichiro
1278 1.1 ichiro Static void
1279 1.1 ichiro url_tick(void *xsc)
1280 1.1 ichiro {
1281 1.1 ichiro struct url_softc *sc = xsc;
1282 1.1 ichiro
1283 1.1 ichiro if (sc == NULL)
1284 1.1 ichiro return;
1285 1.1 ichiro
1286 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1287 1.4 augustss __func__));
1288 1.1 ichiro
1289 1.1 ichiro if (sc->sc_dying)
1290 1.1 ichiro return;
1291 1.1 ichiro
1292 1.1 ichiro /* Perform periodic stuff in process context */
1293 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER);
1294 1.1 ichiro }
1295 1.1 ichiro
1296 1.1 ichiro Static void
1297 1.1 ichiro url_tick_task(void *xsc)
1298 1.1 ichiro {
1299 1.1 ichiro struct url_softc *sc = xsc;
1300 1.1 ichiro struct ifnet *ifp;
1301 1.1 ichiro struct mii_data *mii;
1302 1.1 ichiro int s;
1303 1.1 ichiro
1304 1.1 ichiro if (sc == NULL)
1305 1.1 ichiro return;
1306 1.1 ichiro
1307 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1308 1.4 augustss __func__));
1309 1.1 ichiro
1310 1.1 ichiro if (sc->sc_dying)
1311 1.1 ichiro return;
1312 1.1 ichiro
1313 1.1 ichiro ifp = GET_IFP(sc);
1314 1.1 ichiro mii = GET_MII(sc);
1315 1.1 ichiro
1316 1.1 ichiro if (mii == NULL)
1317 1.1 ichiro return;
1318 1.1 ichiro
1319 1.1 ichiro s = splnet();
1320 1.1 ichiro
1321 1.1 ichiro mii_tick(mii);
1322 1.1 ichiro if (!sc->sc_link) {
1323 1.1 ichiro mii_pollstat(mii);
1324 1.1 ichiro if (mii->mii_media_status & IFM_ACTIVE &&
1325 1.1 ichiro IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1326 1.1 ichiro DPRINTF(("%s: %s: got link\n",
1327 1.38 dyoung device_xname(sc->sc_dev), __func__));
1328 1.1 ichiro sc->sc_link++;
1329 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1330 1.1 ichiro url_start(ifp);
1331 1.1 ichiro }
1332 1.1 ichiro }
1333 1.1 ichiro
1334 1.38 dyoung callout_reset(&sc->sc_stat_ch, hz, url_tick, sc);
1335 1.1 ichiro
1336 1.1 ichiro splx(s);
1337 1.1 ichiro }
1338 1.1 ichiro
1339 1.1 ichiro /* Get exclusive access to the MII registers */
1340 1.1 ichiro Static void
1341 1.1 ichiro url_lock_mii(struct url_softc *sc)
1342 1.1 ichiro {
1343 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1344 1.4 augustss __func__));
1345 1.1 ichiro
1346 1.1 ichiro sc->sc_refcnt++;
1347 1.27 xtraeme rw_enter(&sc->sc_mii_rwlock, RW_WRITER);
1348 1.1 ichiro }
1349 1.1 ichiro
1350 1.1 ichiro Static void
1351 1.1 ichiro url_unlock_mii(struct url_softc *sc)
1352 1.1 ichiro {
1353 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1354 1.4 augustss __func__));
1355 1.1 ichiro
1356 1.27 xtraeme rw_exit(&sc->sc_mii_rwlock);
1357 1.1 ichiro if (--sc->sc_refcnt < 0)
1358 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1359 1.1 ichiro }
1360 1.1 ichiro
1361 1.1 ichiro Static int
1362 1.61 msaitoh url_int_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
1363 1.1 ichiro {
1364 1.1 ichiro struct url_softc *sc;
1365 1.61 msaitoh uint16_t data;
1366 1.61 msaitoh int rv = 0;
1367 1.1 ichiro
1368 1.1 ichiro if (dev == NULL)
1369 1.51 skrll return 0;
1370 1.1 ichiro
1371 1.38 dyoung sc = device_private(dev);
1372 1.1 ichiro
1373 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
1374 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg));
1375 1.1 ichiro
1376 1.1 ichiro if (sc->sc_dying) {
1377 1.1 ichiro #ifdef DIAGNOSTIC
1378 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1379 1.4 augustss __func__);
1380 1.1 ichiro #endif
1381 1.61 msaitoh return -1;
1382 1.1 ichiro }
1383 1.1 ichiro
1384 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1385 1.1 ichiro if (phy != 0) {
1386 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1387 1.38 dyoung device_xname(sc->sc_dev), __func__, phy));
1388 1.61 msaitoh return -1;
1389 1.1 ichiro }
1390 1.1 ichiro
1391 1.1 ichiro url_lock_mii(sc);
1392 1.1 ichiro
1393 1.1 ichiro switch (reg) {
1394 1.1 ichiro case MII_BMCR: /* Control Register */
1395 1.1 ichiro reg = URL_BMCR;
1396 1.1 ichiro break;
1397 1.1 ichiro case MII_BMSR: /* Status Register */
1398 1.1 ichiro reg = URL_BMSR;
1399 1.1 ichiro break;
1400 1.1 ichiro case MII_PHYIDR1:
1401 1.1 ichiro case MII_PHYIDR2:
1402 1.61 msaitoh *val = 0;
1403 1.1 ichiro goto R_DONE;
1404 1.1 ichiro break;
1405 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1406 1.1 ichiro reg = URL_ANAR;
1407 1.1 ichiro break;
1408 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1409 1.1 ichiro reg = URL_ANLP;
1410 1.1 ichiro break;
1411 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1412 1.1 ichiro reg = URL_MSR;
1413 1.1 ichiro break;
1414 1.1 ichiro default:
1415 1.1 ichiro printf("%s: %s: bad register %04x\n",
1416 1.38 dyoung device_xname(sc->sc_dev), __func__, reg);
1417 1.61 msaitoh rv = -1;
1418 1.1 ichiro goto R_DONE;
1419 1.1 ichiro break;
1420 1.1 ichiro }
1421 1.1 ichiro
1422 1.1 ichiro if (reg == URL_MSR)
1423 1.61 msaitoh data = url_csr_read_1(sc, reg);
1424 1.1 ichiro else
1425 1.61 msaitoh data = url_csr_read_2(sc, reg);
1426 1.61 msaitoh *val = data;
1427 1.1 ichiro
1428 1.1 ichiro R_DONE:
1429 1.61 msaitoh DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04hx\n",
1430 1.61 msaitoh device_xname(sc->sc_dev), __func__, phy, reg, *val));
1431 1.1 ichiro
1432 1.1 ichiro url_unlock_mii(sc);
1433 1.61 msaitoh return rv;
1434 1.1 ichiro }
1435 1.1 ichiro
1436 1.61 msaitoh Static int
1437 1.61 msaitoh url_int_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
1438 1.1 ichiro {
1439 1.1 ichiro struct url_softc *sc;
1440 1.61 msaitoh int rv = 0;
1441 1.1 ichiro
1442 1.1 ichiro if (dev == NULL)
1443 1.61 msaitoh return -1;
1444 1.1 ichiro
1445 1.38 dyoung sc = device_private(dev);
1446 1.1 ichiro
1447 1.61 msaitoh DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x val=0x%04hx\n",
1448 1.61 msaitoh device_xname(sc->sc_dev), __func__, phy, reg, val));
1449 1.1 ichiro
1450 1.1 ichiro if (sc->sc_dying) {
1451 1.1 ichiro #ifdef DIAGNOSTIC
1452 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1453 1.4 augustss __func__);
1454 1.1 ichiro #endif
1455 1.61 msaitoh return -1;
1456 1.1 ichiro }
1457 1.1 ichiro
1458 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1459 1.1 ichiro if (phy != 0) {
1460 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1461 1.38 dyoung device_xname(sc->sc_dev), __func__, phy));
1462 1.61 msaitoh return -1;
1463 1.1 ichiro }
1464 1.1 ichiro
1465 1.1 ichiro url_lock_mii(sc);
1466 1.1 ichiro
1467 1.1 ichiro switch (reg) {
1468 1.1 ichiro case MII_BMCR: /* Control Register */
1469 1.1 ichiro reg = URL_BMCR;
1470 1.1 ichiro break;
1471 1.1 ichiro case MII_BMSR: /* Status Register */
1472 1.1 ichiro reg = URL_BMSR;
1473 1.1 ichiro break;
1474 1.1 ichiro case MII_PHYIDR1:
1475 1.1 ichiro case MII_PHYIDR2:
1476 1.1 ichiro goto W_DONE;
1477 1.1 ichiro break;
1478 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1479 1.1 ichiro reg = URL_ANAR;
1480 1.1 ichiro break;
1481 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1482 1.1 ichiro reg = URL_ANLP;
1483 1.1 ichiro break;
1484 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1485 1.1 ichiro reg = URL_MSR;
1486 1.1 ichiro break;
1487 1.1 ichiro default:
1488 1.1 ichiro printf("%s: %s: bad register %04x\n",
1489 1.38 dyoung device_xname(sc->sc_dev), __func__, reg);
1490 1.61 msaitoh rv = -1;
1491 1.1 ichiro goto W_DONE;
1492 1.1 ichiro break;
1493 1.1 ichiro }
1494 1.1 ichiro
1495 1.1 ichiro if (reg == URL_MSR)
1496 1.61 msaitoh url_csr_write_1(sc, reg, val);
1497 1.1 ichiro else
1498 1.61 msaitoh url_csr_write_2(sc, reg, val);
1499 1.1 ichiro W_DONE:
1500 1.1 ichiro
1501 1.1 ichiro url_unlock_mii(sc);
1502 1.61 msaitoh return rv;
1503 1.1 ichiro }
1504 1.1 ichiro
1505 1.1 ichiro Static void
1506 1.44 matt url_miibus_statchg(struct ifnet *ifp)
1507 1.1 ichiro {
1508 1.1 ichiro #ifdef URL_DEBUG
1509 1.44 matt if (ifp == NULL)
1510 1.1 ichiro return;
1511 1.1 ichiro
1512 1.44 matt DPRINTF(("%s: %s: enter\n", ifp->if_xname, __func__));
1513 1.1 ichiro #endif
1514 1.1 ichiro /* Nothing to do */
1515 1.1 ichiro }
1516 1.1 ichiro
1517 1.1 ichiro #if 0
1518 1.1 ichiro /*
1519 1.1 ichiro * external PHYs support, but not test.
1520 1.1 ichiro */
1521 1.1 ichiro Static int
1522 1.38 dyoung url_ext_miibus_redreg(device_t dev, int phy, int reg)
1523 1.1 ichiro {
1524 1.38 dyoung struct url_softc *sc = device_private(dev);
1525 1.51 skrll uint16_t val;
1526 1.1 ichiro
1527 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
1528 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg));
1529 1.1 ichiro
1530 1.1 ichiro if (sc->sc_dying) {
1531 1.1 ichiro #ifdef DIAGNOSTIC
1532 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1533 1.4 augustss __func__);
1534 1.1 ichiro #endif
1535 1.51 skrll return 0;
1536 1.1 ichiro }
1537 1.1 ichiro
1538 1.1 ichiro url_lock_mii(sc);
1539 1.1 ichiro
1540 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
1541 1.1 ichiro /*
1542 1.1 ichiro * RTL8150L will initiate a MII management data transaction
1543 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
1544 1.1 ichiro * this bit is auto cleared by TRL8150L.
1545 1.1 ichiro */
1546 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT,
1547 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
1548 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
1549 1.1 ichiro if ((url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
1550 1.1 ichiro break;
1551 1.1 ichiro }
1552 1.1 ichiro if (i == URL_TIMEOUT) {
1553 1.38 dyoung printf("%s: MII read timed out\n", device_xname(sc->sc_dev));
1554 1.1 ichiro }
1555 1.5 augustss
1556 1.1 ichiro val = url_csr_read_2(sc, URL_PHYDAT);
1557 1.1 ichiro
1558 1.1 ichiro DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1559 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, val));
1560 1.1 ichiro
1561 1.1 ichiro url_unlock_mii(sc);
1562 1.51 skrll return val;
1563 1.1 ichiro }
1564 1.1 ichiro
1565 1.1 ichiro Static void
1566 1.38 dyoung url_ext_miibus_writereg(device_t dev, int phy, int reg, int data)
1567 1.1 ichiro {
1568 1.38 dyoung struct url_softc *sc = device_private(dev);
1569 1.1 ichiro
1570 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1571 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, data));
1572 1.1 ichiro
1573 1.1 ichiro if (sc->sc_dying) {
1574 1.1 ichiro #ifdef DIAGNOSTIC
1575 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1576 1.4 augustss __func__);
1577 1.1 ichiro #endif
1578 1.1 ichiro return;
1579 1.1 ichiro }
1580 1.1 ichiro
1581 1.1 ichiro url_lock_mii(sc);
1582 1.1 ichiro
1583 1.1 ichiro url_csr_write_2(sc, URL_PHYDAT, data);
1584 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy);
1585 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
1586 1.1 ichiro
1587 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
1588 1.1 ichiro if (url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
1589 1.1 ichiro break;
1590 1.1 ichiro }
1591 1.1 ichiro
1592 1.1 ichiro if (i == URL_TIMEOUT) {
1593 1.1 ichiro printf("%s: MII write timed out\n",
1594 1.38 dyoung device_xname(sc->sc_dev));
1595 1.1 ichiro }
1596 1.1 ichiro
1597 1.1 ichiro url_unlock_mii(sc);
1598 1.1 ichiro return;
1599 1.1 ichiro }
1600 1.1 ichiro #endif
1601