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if_url.c revision 1.68
      1  1.68       mrg /*	$NetBSD: if_url.c,v 1.68 2019/08/15 08:02:32 mrg Exp $	*/
      2  1.43       mrg 
      3   1.1    ichiro /*
      4   1.1    ichiro  * Copyright (c) 2001, 2002
      5   1.1    ichiro  *     Shingo WATANABE <nabe (at) nabechan.org>.  All rights reserved.
      6   1.1    ichiro  *
      7   1.1    ichiro  * Redistribution and use in source and binary forms, with or without
      8   1.1    ichiro  * modification, are permitted provided that the following conditions
      9   1.1    ichiro  * are met:
     10   1.1    ichiro  * 1. Redistributions of source code must retain the above copyright
     11   1.1    ichiro  *    notice, this list of conditions and the following disclaimer.
     12   1.1    ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1    ichiro  *    notice, this list of conditions and the following disclaimer in the
     14   1.1    ichiro  *    documentation and/or other materials provided with the distribution.
     15   1.8   tsutsui  * 3. Neither the name of the author nor the names of any co-contributors
     16   1.1    ichiro  *    may be used to endorse or promote products derived from this software
     17   1.1    ichiro  *    without specific prior written permission.
     18   1.1    ichiro  *
     19   1.1    ichiro  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     20   1.1    ichiro  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21   1.1    ichiro  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22   1.1    ichiro  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     23   1.1    ichiro  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     24   1.1    ichiro  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     25   1.1    ichiro  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26   1.1    ichiro  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27   1.1    ichiro  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28   1.1    ichiro  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29   1.1    ichiro  * SUCH DAMAGE.
     30   1.1    ichiro  *
     31   1.1    ichiro  */
     32   1.1    ichiro 
     33   1.1    ichiro /*
     34   1.1    ichiro  * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
     35   1.1    ichiro  *   ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
     36   1.1    ichiro  *   ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
     37   1.1    ichiro  */
     38   1.1    ichiro 
     39   1.1    ichiro /*
     40   1.1    ichiro  * TODO:
     41   1.1    ichiro  *	Interrupt Endpoint support
     42   1.1    ichiro  *	External PHYs
     43   1.1    ichiro  *	powerhook() support?
     44   1.1    ichiro  */
     45   1.1    ichiro 
     46   1.1    ichiro #include <sys/cdefs.h>
     47  1.68       mrg __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.68 2019/08/15 08:02:32 mrg Exp $");
     48   1.1    ichiro 
     49  1.46  christos #ifdef _KERNEL_OPT
     50   1.1    ichiro #include "opt_inet.h"
     51  1.54     skrll #include "opt_usb.h"
     52  1.46  christos #endif
     53   1.1    ichiro 
     54   1.1    ichiro #include <sys/param.h>
     55   1.1    ichiro 
     56   1.1    ichiro #include <net/if_ether.h>
     57   1.1    ichiro #ifdef INET
     58   1.1    ichiro #include <netinet/in.h>
     59   1.1    ichiro #include <netinet/if_inarp.h>
     60   1.1    ichiro #endif
     61   1.1    ichiro 
     62   1.1    ichiro #include <dev/mii/urlphyreg.h>
     63   1.1    ichiro 
     64  1.68       mrg #include <dev/usb/usbnet.h>
     65   1.1    ichiro 
     66   1.1    ichiro #include <dev/usb/if_urlreg.h>
     67   1.1    ichiro 
     68   1.1    ichiro /* Function declarations */
     69  1.53   msaitoh int	url_match(device_t, cfdata_t, void *);
     70  1.53   msaitoh void	url_attach(device_t, device_t, void *);
     71  1.63       mrg 
     72  1.68       mrg CFATTACH_DECL_NEW(url, sizeof(struct usbnet), url_match, url_attach,
     73  1.68       mrg     usbnet_detach, usbnet_activate);
     74   1.1    ichiro 
     75  1.68       mrg static unsigned	url_tx_prepare(struct usbnet *, struct mbuf *,
     76  1.68       mrg 			       struct usbnet_chain *);
     77  1.68       mrg static void url_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t);
     78  1.68       mrg static usbd_status url_int_mii_read_reg(struct usbnet *, int, int, uint16_t *);
     79  1.68       mrg static usbd_status url_int_mii_write_reg(struct usbnet *, int, int, uint16_t);
     80  1.68       mrg static int url_ioctl_cb(struct ifnet *, u_long, void *);
     81  1.68       mrg static void url_stop_cb(struct ifnet *, int);
     82  1.68       mrg static void url_mii_statchg_cb(struct ifnet *);
     83  1.68       mrg static int url_init(struct ifnet *);
     84  1.68       mrg static void url_setiff_locked(struct usbnet *);
     85  1.68       mrg static void url_setiff(struct usbnet *);
     86  1.68       mrg static void url_reset(struct usbnet *);
     87  1.68       mrg 
     88  1.68       mrg static int url_csr_read_1(struct usbnet *, int);
     89  1.68       mrg static int url_csr_read_2(struct usbnet *, int);
     90  1.68       mrg static int url_csr_write_1(struct usbnet *, int, int);
     91  1.68       mrg static int url_csr_write_2(struct usbnet *, int, int);
     92  1.68       mrg static int url_csr_write_4(struct usbnet *, int, int);
     93  1.68       mrg static int url_mem(struct usbnet *, int, int, void *, int);
     94  1.68       mrg 
     95  1.68       mrg static struct usbnet_ops url_ops = {
     96  1.68       mrg 	.uno_stop = url_stop_cb,
     97  1.68       mrg 	.uno_ioctl = url_ioctl_cb,
     98  1.68       mrg 	.uno_read_reg = url_int_mii_read_reg,
     99  1.68       mrg 	.uno_write_reg = url_int_mii_write_reg,
    100  1.68       mrg 	.uno_statchg = url_mii_statchg_cb,
    101  1.68       mrg 	.uno_tx_prepare = url_tx_prepare,
    102  1.68       mrg 	.uno_rx_loop = url_rx_loop,
    103  1.68       mrg 	.uno_init = url_init,
    104  1.68       mrg };
    105   1.1    ichiro 
    106   1.1    ichiro /* Macros */
    107   1.1    ichiro #ifdef URL_DEBUG
    108  1.38    dyoung #define DPRINTF(x)	if (urldebug) printf x
    109  1.64   msaitoh #define DPRINTFN(n, x)	if (urldebug >= (n)) printf x
    110   1.2    ichiro int urldebug = 0;
    111   1.1    ichiro #else
    112   1.1    ichiro #define DPRINTF(x)
    113  1.64   msaitoh #define DPRINTFN(n, x)
    114   1.1    ichiro #endif
    115   1.1    ichiro 
    116  1.68       mrg #define	URL_SETBIT(un, reg, x)	\
    117  1.68       mrg 	url_csr_write_1(un, reg, url_csr_read_1(un, reg) | (x))
    118   1.1    ichiro 
    119  1.68       mrg #define	URL_SETBIT2(un, reg, x)	\
    120  1.68       mrg 	url_csr_write_2(un, reg, url_csr_read_2(un, reg) | (x))
    121   1.1    ichiro 
    122  1.68       mrg #define	URL_CLRBIT(un, reg, x)	\
    123  1.68       mrg 	url_csr_write_1(un, reg, url_csr_read_1(un, reg) & ~(x))
    124   1.1    ichiro 
    125  1.68       mrg #define	URL_CLRBIT2(un, reg, x)	\
    126  1.68       mrg 	url_csr_write_2(un, reg, url_csr_read_2(un, reg) & ~(x))
    127   1.1    ichiro 
    128   1.1    ichiro static const struct url_type {
    129   1.1    ichiro 	struct usb_devno url_dev;
    130  1.51     skrll 	uint16_t url_flags;
    131   1.1    ichiro #define URL_EXT_PHY	0x0001
    132   1.1    ichiro } url_devs [] = {
    133   1.1    ichiro 	/* MELCO LUA-KTX */
    134   1.1    ichiro 	{{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
    135  1.10   mycroft 	/* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
    136  1.11  augustss 	{{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
    137  1.11  augustss 	/* Longshine LCS-8138TX */
    138  1.11  augustss 	{{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
    139  1.11  augustss 	/* Micronet SP128AR */
    140  1.11  augustss 	{{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
    141  1.13    itojun 	/* OQO model 01 */
    142  1.13    itojun 	{{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
    143   1.1    ichiro };
    144  1.17  christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
    145   1.1    ichiro 
    146   1.1    ichiro 
    147   1.1    ichiro /* Probe */
    148  1.46  christos int
    149  1.38    dyoung url_match(device_t parent, cfdata_t match, void *aux)
    150   1.1    ichiro {
    151  1.38    dyoung 	struct usb_attach_arg *uaa = aux;
    152   1.1    ichiro 
    153  1.51     skrll 	return url_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ?
    154  1.51     skrll 		UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
    155   1.1    ichiro }
    156   1.1    ichiro /* Attach */
    157  1.46  christos void
    158  1.38    dyoung url_attach(device_t parent, device_t self, void *aux)
    159   1.1    ichiro {
    160  1.68       mrg 	struct usbnet * const un = device_private(self);
    161  1.38    dyoung 	struct usb_attach_arg *uaa = aux;
    162  1.51     skrll 	struct usbd_device *dev = uaa->uaa_device;
    163  1.51     skrll 	struct usbd_interface *iface;
    164   1.1    ichiro 	usbd_status err;
    165   1.1    ichiro 	usb_interface_descriptor_t *id;
    166   1.1    ichiro 	usb_endpoint_descriptor_t *ed;
    167  1.16  augustss 	char *devinfop;
    168  1.68       mrg 	int i;
    169  1.32      cube 
    170  1.34    plunky 	aprint_naive("\n");
    171  1.34    plunky 	aprint_normal("\n");
    172  1.16  augustss 	devinfop = usbd_devinfo_alloc(dev, 0);
    173  1.32      cube 	aprint_normal_dev(self, "%s\n", devinfop);
    174  1.16  augustss 	usbd_devinfo_free(devinfop);
    175   1.1    ichiro 
    176  1.68       mrg 	un->un_dev = self;
    177  1.68       mrg 	un->un_udev = dev;
    178  1.68       mrg 	un->un_sc = un;
    179  1.68       mrg 	un->un_ops = &url_ops;
    180  1.68       mrg 	un->un_rx_xfer_flags = USBD_SHORT_XFER_OK;
    181  1.68       mrg 	un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER;
    182  1.68       mrg 	un->un_rx_list_cnt = URL_RX_LIST_CNT;
    183  1.68       mrg 	un->un_tx_list_cnt = URL_TX_LIST_CNT;
    184  1.68       mrg 	un->un_rx_bufsz = URL_BUFSZ;
    185  1.68       mrg 	un->un_tx_bufsz = URL_BUFSZ;
    186  1.68       mrg 
    187   1.1    ichiro 	/* Move the device into the configured state. */
    188   1.1    ichiro 	err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
    189   1.1    ichiro 	if (err) {
    190  1.45     skrll 		aprint_error_dev(self, "failed to set configuration"
    191  1.45     skrll 		    ", err=%s\n", usbd_errstr(err));
    192   1.1    ichiro 		goto bad;
    193   1.1    ichiro 	}
    194   1.1    ichiro 
    195   1.1    ichiro 	/* get control interface */
    196   1.1    ichiro 	err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
    197   1.1    ichiro 	if (err) {
    198  1.32      cube 		aprint_error_dev(self, "failed to get interface, err=%s\n",
    199   1.1    ichiro 		       usbd_errstr(err));
    200   1.1    ichiro 		goto bad;
    201   1.1    ichiro 	}
    202   1.1    ichiro 
    203  1.68       mrg 	un->un_iface = iface;
    204  1.68       mrg 	un->un_flags = url_lookup(uaa->uaa_vendor, uaa->uaa_product)->url_flags;
    205  1.68       mrg #if 0
    206  1.68       mrg 	if (un->un_flags & URL_EXT_PHY) {
    207  1.68       mrg 		un->un_read_reg_cb = url_ext_mii_read_reg;
    208  1.68       mrg 		un->un_write_reg_cb = url_ext_mii_write_reg;
    209  1.68       mrg 	}
    210  1.68       mrg #endif
    211   1.1    ichiro 
    212   1.1    ichiro 	/* get interface descriptor */
    213  1.68       mrg 	id = usbd_get_interface_descriptor(un->un_iface);
    214   1.1    ichiro 
    215   1.1    ichiro 	/* find endpoints */
    216  1.68       mrg 	un->un_ed[USBNET_ENDPT_RX] = un->un_ed[USBNET_ENDPT_TX] =
    217  1.68       mrg 	    un->un_ed[USBNET_ENDPT_INTR] = 0;
    218   1.1    ichiro 	for (i = 0; i < id->bNumEndpoints; i++) {
    219  1.68       mrg 		ed = usbd_interface2endpoint_descriptor(un->un_iface, i);
    220   1.1    ichiro 		if (ed == NULL) {
    221  1.32      cube 			aprint_error_dev(self,
    222  1.32      cube 			    "couldn't get endpoint %d\n", i);
    223   1.1    ichiro 			goto bad;
    224   1.1    ichiro 		}
    225   1.1    ichiro 		if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
    226   1.1    ichiro 		    UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
    227  1.68       mrg 			un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress;
    228   1.1    ichiro 		else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
    229   1.1    ichiro 			 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
    230  1.68       mrg 			un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress;
    231   1.1    ichiro 		else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
    232   1.1    ichiro 			 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
    233  1.68       mrg 			un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress;
    234   1.1    ichiro 	}
    235   1.1    ichiro 
    236  1.68       mrg 	if (un->un_ed[USBNET_ENDPT_RX] == 0 ||
    237  1.68       mrg 	    un->un_ed[USBNET_ENDPT_TX] == 0 ||
    238  1.68       mrg 	    un->un_ed[USBNET_ENDPT_INTR] == 0) {
    239  1.32      cube 		aprint_error_dev(self, "missing endpoint\n");
    240   1.1    ichiro 		goto bad;
    241   1.1    ichiro 	}
    242   1.1    ichiro 
    243  1.68       mrg 	/* Set these up now for url_mem().  */
    244  1.68       mrg 	usbnet_attach(un, "urldet");
    245   1.1    ichiro 
    246   1.1    ichiro 	/* reset the adapter */
    247  1.68       mrg 	usbnet_lock(un);
    248  1.68       mrg 	url_reset(un);
    249  1.68       mrg 	usbnet_unlock(un);
    250   1.1    ichiro 
    251   1.1    ichiro 	/* Get Ethernet Address */
    252  1.68       mrg 	usbnet_lock_mii(un);
    253  1.68       mrg 	err = url_mem(un, URL_CMD_READMEM, URL_IDR0, (void *)un->un_eaddr,
    254   1.1    ichiro 		      ETHER_ADDR_LEN);
    255  1.68       mrg 	usbnet_unlock_mii(un);
    256   1.1    ichiro 	if (err) {
    257  1.32      cube 		aprint_error_dev(self, "read MAC address failed\n");
    258   1.1    ichiro 		goto bad;
    259   1.1    ichiro 	}
    260   1.1    ichiro 
    261  1.19       wiz 	/* initialize interface information */
    262  1.68       mrg 	usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST,
    263  1.68       mrg 	    0, 0);
    264  1.62   msaitoh 
    265  1.38    dyoung 	return;
    266   1.1    ichiro 
    267   1.1    ichiro  bad:
    268  1.68       mrg 	usbnet_set_dying(un, true);
    269  1.38    dyoung 	return;
    270   1.1    ichiro }
    271   1.1    ichiro 
    272   1.1    ichiro /* read/write memory */
    273  1.68       mrg static int
    274  1.68       mrg url_mem(struct usbnet *un, int cmd, int offset, void *buf, int len)
    275   1.1    ichiro {
    276   1.1    ichiro 	usb_device_request_t req;
    277   1.1    ichiro 	usbd_status err;
    278   1.1    ichiro 
    279  1.68       mrg 	usbnet_isowned_mii(un);
    280   1.1    ichiro 
    281   1.1    ichiro 	DPRINTFN(0x200,
    282  1.68       mrg 		("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    283   1.1    ichiro 
    284  1.68       mrg 	if (usbnet_isdying(un))
    285  1.51     skrll 		return 0;
    286   1.1    ichiro 
    287   1.1    ichiro 	if (cmd == URL_CMD_READMEM)
    288   1.1    ichiro 		req.bmRequestType = UT_READ_VENDOR_DEVICE;
    289   1.1    ichiro 	else
    290   1.1    ichiro 		req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
    291   1.1    ichiro 	req.bRequest = URL_REQ_MEM;
    292   1.1    ichiro 	USETW(req.wValue, offset);
    293   1.1    ichiro 	USETW(req.wIndex, 0x0000);
    294   1.1    ichiro 	USETW(req.wLength, len);
    295   1.1    ichiro 
    296  1.68       mrg 	err = usbd_do_request(un->un_udev, &req, buf);
    297   1.1    ichiro 	if (err) {
    298   1.1    ichiro 		DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
    299  1.68       mrg 			 device_xname(un->un_dev),
    300   1.1    ichiro 			 cmd == URL_CMD_READMEM ? "read" : "write",
    301   1.1    ichiro 			 offset, err));
    302   1.5  augustss 	}
    303   1.1    ichiro 
    304  1.51     skrll 	return err;
    305   1.1    ichiro }
    306   1.1    ichiro 
    307   1.1    ichiro /* read 1byte from register */
    308  1.68       mrg static int
    309  1.68       mrg url_csr_read_1(struct usbnet *un, int reg)
    310   1.1    ichiro {
    311  1.51     skrll 	uint8_t val = 0;
    312   1.1    ichiro 
    313   1.1    ichiro 	DPRINTFN(0x100,
    314  1.68       mrg 		 ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    315   1.5  augustss 
    316  1.68       mrg 	return url_mem(un, URL_CMD_READMEM, reg, &val, 1) ? 0 : val;
    317   1.1    ichiro }
    318   1.1    ichiro 
    319   1.1    ichiro /* read 2bytes from register */
    320  1.68       mrg static int
    321  1.68       mrg url_csr_read_2(struct usbnet *un, int reg)
    322   1.1    ichiro {
    323   1.1    ichiro 	uWord val;
    324   1.1    ichiro 
    325   1.1    ichiro 	DPRINTFN(0x100,
    326  1.68       mrg 		 ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    327   1.5  augustss 
    328   1.1    ichiro 	USETW(val, 0);
    329  1.68       mrg 	return url_mem(un, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val);
    330   1.1    ichiro }
    331   1.1    ichiro 
    332   1.1    ichiro /* write 1byte to register */
    333  1.68       mrg static int
    334  1.68       mrg url_csr_write_1(struct usbnet *un, int reg, int aval)
    335   1.1    ichiro {
    336  1.51     skrll 	uint8_t val = aval;
    337   1.1    ichiro 
    338   1.1    ichiro 	DPRINTFN(0x100,
    339  1.68       mrg 		 ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    340   1.1    ichiro 
    341  1.68       mrg 	return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0;
    342   1.1    ichiro }
    343   1.1    ichiro 
    344   1.1    ichiro /* write 2bytes to register */
    345  1.68       mrg static int
    346  1.68       mrg url_csr_write_2(struct usbnet *un, int reg, int aval)
    347   1.1    ichiro {
    348   1.1    ichiro 	uWord val;
    349   1.1    ichiro 
    350   1.1    ichiro 	DPRINTFN(0x100,
    351  1.68       mrg 		 ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    352   1.1    ichiro 
    353   1.1    ichiro 	USETW(val, aval);
    354   1.1    ichiro 
    355  1.68       mrg 	return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0;
    356   1.1    ichiro }
    357   1.1    ichiro 
    358   1.1    ichiro /* write 4bytes to register */
    359  1.68       mrg static int
    360  1.68       mrg url_csr_write_4(struct usbnet *un, int reg, int aval)
    361   1.1    ichiro {
    362   1.1    ichiro 	uDWord val;
    363   1.1    ichiro 
    364   1.1    ichiro 	DPRINTFN(0x100,
    365  1.68       mrg 		 ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    366   1.1    ichiro 
    367   1.1    ichiro 	USETDW(val, aval);
    368   1.1    ichiro 
    369  1.68       mrg 	return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0;
    370   1.1    ichiro }
    371   1.1    ichiro 
    372  1.68       mrg static int
    373  1.68       mrg url_init_locked(struct ifnet *ifp)
    374   1.1    ichiro {
    375  1.68       mrg 	struct usbnet * const un = ifp->if_softc;
    376  1.29    dyoung 	const u_char *eaddr;
    377  1.68       mrg 	int i;
    378   1.1    ichiro 
    379  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    380   1.5  augustss 
    381  1.68       mrg 	usbnet_isowned(un);
    382  1.68       mrg 
    383  1.68       mrg 	if (usbnet_isdying(un))
    384  1.51     skrll 		return EIO;
    385   1.1    ichiro 
    386  1.68       mrg 	/* Cancel pending I/O and free all TX/RX buffers */
    387  1.68       mrg 	usbnet_stop(un, ifp, 1);
    388   1.1    ichiro 
    389  1.68       mrg 	usbnet_lock_mii_un_locked(un);
    390   1.1    ichiro 
    391  1.29    dyoung 	eaddr = CLLADDR(ifp->if_sadl);
    392   1.1    ichiro 	for (i = 0; i < ETHER_ADDR_LEN; i++)
    393  1.68       mrg 		url_csr_write_1(un, URL_IDR0 + i, eaddr[i]);
    394   1.1    ichiro 
    395   1.1    ichiro 	/* Init transmission control register */
    396  1.68       mrg 	URL_CLRBIT(un, URL_TCR,
    397   1.1    ichiro 		   URL_TCR_TXRR1 | URL_TCR_TXRR0 |
    398   1.1    ichiro 		   URL_TCR_IFG1 | URL_TCR_IFG0 |
    399   1.1    ichiro 		   URL_TCR_NOCRC);
    400   1.1    ichiro 
    401   1.1    ichiro 	/* Init receive control register */
    402  1.68       mrg 	URL_SETBIT2(un, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
    403   1.1    ichiro 	if (ifp->if_flags & IFF_BROADCAST)
    404  1.68       mrg 		URL_SETBIT2(un, URL_RCR, URL_RCR_AB);
    405   1.1    ichiro 	else
    406  1.68       mrg 		URL_CLRBIT2(un, URL_RCR, URL_RCR_AB);
    407   1.1    ichiro 
    408   1.1    ichiro 	/* If we want promiscuous mode, accept all physical frames. */
    409   1.1    ichiro 	if (ifp->if_flags & IFF_PROMISC)
    410  1.68       mrg 		URL_SETBIT2(un, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
    411   1.1    ichiro 	else
    412  1.68       mrg 		URL_CLRBIT2(un, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
    413   1.5  augustss 
    414   1.1    ichiro 	/* Load the multicast filter */
    415  1.68       mrg 	url_setiff_locked(un);
    416   1.1    ichiro 
    417   1.1    ichiro 	/* Enable RX and TX */
    418  1.68       mrg 	URL_SETBIT(un, URL_CR, URL_CR_TE | URL_CR_RE);
    419  1.51     skrll 
    420  1.68       mrg 	usbnet_unlock_mii_un_locked(un);
    421  1.51     skrll 
    422  1.68       mrg 	return usbnet_init_rx_tx(un);
    423  1.68       mrg }
    424   1.1    ichiro 
    425  1.68       mrg static int
    426  1.68       mrg url_init(struct ifnet *ifp)
    427  1.68       mrg {
    428  1.68       mrg 	struct usbnet * const un = ifp->if_softc;
    429   1.1    ichiro 
    430  1.68       mrg 	usbnet_lock(un);
    431  1.68       mrg 	int ret = url_init_locked(ifp);
    432  1.68       mrg 	usbnet_unlock(un);
    433   1.1    ichiro 
    434  1.68       mrg 	return ret;
    435   1.1    ichiro }
    436   1.1    ichiro 
    437  1.68       mrg static void
    438  1.68       mrg url_reset(struct usbnet *un)
    439   1.1    ichiro {
    440   1.1    ichiro 	int i;
    441   1.5  augustss 
    442  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    443   1.1    ichiro 
    444  1.68       mrg 	if (usbnet_isdying(un))
    445   1.1    ichiro 		return;
    446   1.1    ichiro 
    447  1.68       mrg 	usbnet_lock_mii_un_locked(un);
    448  1.68       mrg 	URL_SETBIT(un, URL_CR, URL_CR_SOFT_RST);
    449   1.1    ichiro 
    450   1.1    ichiro 	for (i = 0; i < URL_TX_TIMEOUT; i++) {
    451  1.68       mrg 		if (!(url_csr_read_1(un, URL_CR) & URL_CR_SOFT_RST))
    452   1.1    ichiro 			break;
    453   1.1    ichiro 		delay(10);	/* XXX */
    454   1.1    ichiro 	}
    455   1.1    ichiro 
    456   1.1    ichiro 	delay(10000);		/* XXX */
    457  1.68       mrg 	usbnet_unlock_mii_un_locked(un);
    458   1.1    ichiro }
    459   1.1    ichiro 
    460   1.1    ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
    461   1.1    ichiro 
    462  1.68       mrg static void
    463  1.68       mrg url_setiff_locked(struct usbnet *un)
    464   1.1    ichiro {
    465  1.68       mrg 	struct ifnet * const ifp = usbnet_ifp(un);
    466  1.68       mrg 	struct ethercom *ec = usbnet_ec(un);
    467   1.1    ichiro 	struct ether_multi *enm;
    468   1.1    ichiro 	struct ether_multistep step;
    469  1.51     skrll 	uint32_t hashes[2] = { 0, 0 };
    470   1.1    ichiro 	int h = 0;
    471   1.1    ichiro 	int mcnt = 0;
    472   1.1    ichiro 
    473  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    474   1.1    ichiro 
    475  1.68       mrg 	usbnet_isowned_mii(un);
    476  1.68       mrg 
    477  1.68       mrg 	if (usbnet_isdying(un))
    478   1.1    ichiro 		return;
    479   1.1    ichiro 
    480   1.1    ichiro 	if (ifp->if_flags & IFF_PROMISC) {
    481  1.68       mrg 		URL_SETBIT2(un, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
    482   1.1    ichiro 		return;
    483   1.1    ichiro 	} else if (ifp->if_flags & IFF_ALLMULTI) {
    484  1.65   msaitoh allmulti:
    485   1.1    ichiro 		ifp->if_flags |= IFF_ALLMULTI;
    486  1.68       mrg 		URL_SETBIT2(un, URL_RCR, URL_RCR_AAM);
    487  1.68       mrg 		URL_CLRBIT2(un, URL_RCR, URL_RCR_AAP);
    488   1.1    ichiro 		return;
    489   1.1    ichiro 	}
    490   1.1    ichiro 
    491   1.1    ichiro 	/* first, zot all the existing hash bits */
    492  1.68       mrg 	url_csr_write_4(un, URL_MAR0, 0);
    493  1.68       mrg 	url_csr_write_4(un, URL_MAR4, 0);
    494   1.1    ichiro 
    495   1.1    ichiro 	/* now program new ones */
    496  1.65   msaitoh 	ETHER_LOCK(ec);
    497  1.65   msaitoh 	ETHER_FIRST_MULTI(step, ec, enm);
    498   1.1    ichiro 	while (enm != NULL) {
    499   1.1    ichiro 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
    500  1.65   msaitoh 		    ETHER_ADDR_LEN) != 0) {
    501  1.65   msaitoh 			ETHER_UNLOCK(ec);
    502   1.1    ichiro 			goto allmulti;
    503  1.65   msaitoh 		}
    504   1.1    ichiro 
    505   1.1    ichiro 		h = url_calchash(enm->enm_addrlo);
    506   1.1    ichiro 		if (h < 32)
    507   1.1    ichiro 			hashes[0] |= (1 << h);
    508   1.1    ichiro 		else
    509   1.1    ichiro 			hashes[1] |= (1 << (h -32));
    510   1.1    ichiro 		mcnt++;
    511   1.1    ichiro 		ETHER_NEXT_MULTI(step, enm);
    512   1.1    ichiro 	}
    513  1.65   msaitoh 	ETHER_UNLOCK(ec);
    514   1.1    ichiro 
    515   1.1    ichiro 	ifp->if_flags &= ~IFF_ALLMULTI;
    516   1.1    ichiro 
    517  1.68       mrg 	URL_CLRBIT2(un, URL_RCR, URL_RCR_AAM | URL_RCR_AAP);
    518   1.1    ichiro 
    519  1.64   msaitoh 	if (mcnt) {
    520  1.68       mrg 		URL_SETBIT2(un, URL_RCR, URL_RCR_AM);
    521   1.1    ichiro 	} else {
    522  1.68       mrg 		URL_CLRBIT2(un, URL_RCR, URL_RCR_AM);
    523   1.1    ichiro 	}
    524  1.68       mrg 	url_csr_write_4(un, URL_MAR0, hashes[0]);
    525  1.68       mrg 	url_csr_write_4(un, URL_MAR4, hashes[1]);
    526   1.1    ichiro }
    527   1.1    ichiro 
    528  1.68       mrg static void
    529  1.68       mrg url_setiff(struct usbnet *un)
    530   1.1    ichiro {
    531  1.68       mrg 	usbnet_lock(un);
    532  1.68       mrg 	usbnet_lock_mii_un_locked(un);
    533  1.68       mrg 	url_setiff_locked(un);
    534  1.68       mrg 	usbnet_unlock_mii_un_locked(un);
    535  1.68       mrg 	usbnet_unlock(un);
    536   1.1    ichiro }
    537   1.5  augustss 
    538  1.68       mrg static unsigned
    539  1.68       mrg url_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c)
    540   1.1    ichiro {
    541  1.68       mrg 	int total_len;
    542   1.1    ichiro 
    543  1.68       mrg 	usbnet_isowned_tx(un);
    544   1.1    ichiro 
    545  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev),__func__));
    546   1.5  augustss 
    547  1.68       mrg 	KASSERT(un->un_tx_bufsz >= URL_MIN_FRAME_LEN);
    548  1.68       mrg 	if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz)
    549  1.68       mrg 		return 0;
    550   1.1    ichiro 
    551   1.1    ichiro 	/* Copy the mbuf data into a contiguous buffer */
    552  1.68       mrg 	m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf);
    553   1.1    ichiro 	total_len = m->m_pkthdr.len;
    554   1.1    ichiro 
    555   1.7    bouyer 	if (total_len < URL_MIN_FRAME_LEN) {
    556  1.68       mrg 		memset(c->unc_buf + total_len, 0,
    557   1.7    bouyer 		    URL_MIN_FRAME_LEN - total_len);
    558   1.1    ichiro 		total_len = URL_MIN_FRAME_LEN;
    559   1.7    bouyer 	}
    560   1.1    ichiro 
    561  1.68       mrg 	DPRINTF(("%s: %s: send %d bytes\n", device_xname(un->un_dev),
    562   1.4  augustss 		 __func__, total_len));
    563   1.1    ichiro 
    564  1.68       mrg 	return total_len;
    565   1.1    ichiro }
    566   1.1    ichiro 
    567  1.68       mrg static void
    568  1.68       mrg url_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len)
    569   1.1    ichiro {
    570  1.68       mrg 	struct ifnet *ifp = usbnet_ifp(un);
    571   1.1    ichiro 	url_rxhdr_t rxhdr;
    572   1.1    ichiro 
    573  1.68       mrg 	usbnet_isowned_rx(un);
    574   1.1    ichiro 
    575  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev),__func__));
    576   1.1    ichiro 
    577  1.68       mrg 	if (total_len <= ETHER_CRC_LEN || total_len <= sizeof(rxhdr)) {
    578   1.1    ichiro 		ifp->if_ierrors++;
    579  1.68       mrg 		return;
    580   1.1    ichiro 	}
    581   1.1    ichiro 
    582  1.68       mrg 	memcpy(&rxhdr, c->unc_buf + total_len - ETHER_CRC_LEN, sizeof(rxhdr));
    583   1.1    ichiro 
    584   1.1    ichiro 	DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
    585  1.68       mrg 		 device_xname(un->un_dev),
    586   1.1    ichiro 		 UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
    587   1.1    ichiro 		 UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
    588   1.1    ichiro 		 UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
    589   1.1    ichiro 		 UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
    590   1.1    ichiro 		 UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
    591   1.1    ichiro 
    592   1.1    ichiro 	if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
    593   1.1    ichiro 		ifp->if_ierrors++;
    594  1.68       mrg 		return;
    595   1.1    ichiro 	}
    596   1.1    ichiro 
    597   1.1    ichiro 	total_len -= ETHER_CRC_LEN;
    598   1.1    ichiro 
    599  1.68       mrg 	DPRINTF(("%s: %s: deliver %d\n", device_xname(un->un_dev),
    600  1.68       mrg 		 __func__, total_len));
    601  1.68       mrg 	usbnet_enqueue(un, c->unc_buf, total_len, 0, 0, 0);
    602   1.1    ichiro }
    603   1.1    ichiro 
    604   1.1    ichiro #if 0
    605  1.68       mrg static void url_intr(void)
    606   1.1    ichiro {
    607   1.1    ichiro }
    608   1.1    ichiro #endif
    609   1.1    ichiro 
    610  1.68       mrg static int
    611  1.68       mrg url_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data)
    612   1.1    ichiro {
    613  1.68       mrg 	struct usbnet * const un = ifp->if_softc;
    614   1.1    ichiro 
    615  1.68       mrg 	switch (cmd) {
    616  1.68       mrg 	case SIOCADDMULTI:
    617  1.68       mrg 	case SIOCDELMULTI:
    618  1.68       mrg 		url_setiff(un);
    619  1.68       mrg 		break;
    620  1.68       mrg 	default:
    621  1.68       mrg 		break;
    622   1.1    ichiro 	}
    623   1.1    ichiro 
    624  1.68       mrg 	return 0;
    625   1.1    ichiro }
    626   1.1    ichiro 
    627   1.1    ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
    628  1.68       mrg static void
    629  1.68       mrg url_stop_cb(struct ifnet *ifp, int disable)
    630   1.1    ichiro {
    631  1.68       mrg 	struct usbnet * const un = ifp->if_softc;
    632   1.1    ichiro 
    633  1.68       mrg 	usbnet_isowned(un);
    634   1.1    ichiro 
    635  1.68       mrg 	DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
    636   1.1    ichiro 
    637  1.68       mrg 	url_reset(un);
    638   1.1    ichiro }
    639   1.1    ichiro 
    640  1.68       mrg static usbd_status
    641  1.68       mrg url_int_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)
    642   1.1    ichiro {
    643  1.61   msaitoh 	uint16_t data;
    644  1.68       mrg 	usbd_status err = USBD_NORMAL_COMPLETION;
    645   1.1    ichiro 
    646  1.68       mrg 	usbnet_isowned_mii(un);
    647   1.1    ichiro 
    648   1.1    ichiro 	DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
    649  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg));
    650   1.1    ichiro 
    651   1.1    ichiro 	/* XXX: one PHY only for the RTL8150 internal PHY */
    652   1.1    ichiro 	if (phy != 0) {
    653   1.1    ichiro 		DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
    654  1.68       mrg 			 device_xname(un->un_dev), __func__, phy));
    655  1.68       mrg 		return USBD_INVAL;
    656   1.1    ichiro 	}
    657   1.1    ichiro 
    658   1.1    ichiro 	switch (reg) {
    659   1.1    ichiro 	case MII_BMCR:		/* Control Register */
    660   1.1    ichiro 		reg = URL_BMCR;
    661   1.1    ichiro 		break;
    662   1.1    ichiro 	case MII_BMSR:		/* Status Register */
    663   1.1    ichiro 		reg = URL_BMSR;
    664   1.1    ichiro 		break;
    665   1.1    ichiro 	case MII_PHYIDR1:
    666   1.1    ichiro 	case MII_PHYIDR2:
    667  1.61   msaitoh 		*val = 0;
    668   1.1    ichiro 		goto R_DONE;
    669   1.1    ichiro 		break;
    670   1.1    ichiro 	case MII_ANAR:		/* Autonegotiation advertisement */
    671   1.1    ichiro 		reg = URL_ANAR;
    672   1.1    ichiro 		break;
    673   1.1    ichiro 	case MII_ANLPAR:	/* Autonegotiation link partner abilities */
    674   1.1    ichiro 		reg = URL_ANLP;
    675   1.1    ichiro 		break;
    676   1.1    ichiro 	case URLPHY_MSR:	/* Media Status Register */
    677   1.1    ichiro 		reg = URL_MSR;
    678   1.1    ichiro 		break;
    679   1.1    ichiro 	default:
    680   1.1    ichiro 		printf("%s: %s: bad register %04x\n",
    681  1.68       mrg 		       device_xname(un->un_dev), __func__, reg);
    682  1.68       mrg 		err = USBD_INVAL;
    683   1.1    ichiro 		goto R_DONE;
    684   1.1    ichiro 		break;
    685   1.1    ichiro 	}
    686   1.1    ichiro 
    687   1.1    ichiro 	if (reg == URL_MSR)
    688  1.68       mrg 		data = url_csr_read_1(un, reg);
    689   1.1    ichiro 	else
    690  1.68       mrg 		data = url_csr_read_2(un, reg);
    691  1.61   msaitoh 	*val = data;
    692   1.1    ichiro 
    693   1.1    ichiro  R_DONE:
    694  1.61   msaitoh 	DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04hx\n",
    695  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg, *val));
    696   1.1    ichiro 
    697  1.68       mrg 	return err;
    698   1.1    ichiro }
    699   1.1    ichiro 
    700  1.68       mrg static usbd_status
    701  1.68       mrg url_int_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)
    702   1.1    ichiro {
    703  1.68       mrg 	usbd_status err = USBD_NORMAL_COMPLETION;
    704   1.1    ichiro 
    705  1.68       mrg 	usbnet_isowned_mii(un);
    706   1.1    ichiro 
    707  1.61   msaitoh 	DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x val=0x%04hx\n",
    708  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg, val));
    709   1.1    ichiro 
    710   1.1    ichiro 	/* XXX: one PHY only for the RTL8150 internal PHY */
    711   1.1    ichiro 	if (phy != 0) {
    712   1.1    ichiro 		DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
    713  1.68       mrg 			 device_xname(un->un_dev), __func__, phy));
    714  1.68       mrg 		return USBD_INVAL;
    715   1.1    ichiro 	}
    716   1.1    ichiro 
    717   1.1    ichiro 	switch (reg) {
    718   1.1    ichiro 	case MII_BMCR:		/* Control Register */
    719   1.1    ichiro 		reg = URL_BMCR;
    720   1.1    ichiro 		break;
    721   1.1    ichiro 	case MII_BMSR:		/* Status Register */
    722   1.1    ichiro 		reg = URL_BMSR;
    723   1.1    ichiro 		break;
    724   1.1    ichiro 	case MII_PHYIDR1:
    725   1.1    ichiro 	case MII_PHYIDR2:
    726   1.1    ichiro 		goto W_DONE;
    727   1.1    ichiro 		break;
    728   1.1    ichiro 	case MII_ANAR:		/* Autonegotiation advertisement */
    729   1.1    ichiro 		reg = URL_ANAR;
    730   1.1    ichiro 		break;
    731   1.1    ichiro 	case MII_ANLPAR:	/* Autonegotiation link partner abilities */
    732   1.1    ichiro 		reg = URL_ANLP;
    733   1.1    ichiro 		break;
    734   1.1    ichiro 	case URLPHY_MSR:	/* Media Status Register */
    735   1.1    ichiro 		reg = URL_MSR;
    736   1.1    ichiro 		break;
    737   1.1    ichiro 	default:
    738   1.1    ichiro 		printf("%s: %s: bad register %04x\n",
    739  1.68       mrg 		       device_xname(un->un_dev), __func__, reg);
    740  1.68       mrg 		err = USBD_INVAL;
    741   1.1    ichiro 		goto W_DONE;
    742   1.1    ichiro 		break;
    743   1.1    ichiro 	}
    744   1.1    ichiro 
    745   1.1    ichiro 	if (reg == URL_MSR)
    746  1.68       mrg 		url_csr_write_1(un, reg, val);
    747   1.1    ichiro 	else
    748  1.68       mrg 		url_csr_write_2(un, reg, val);
    749   1.1    ichiro  W_DONE:
    750   1.1    ichiro 
    751  1.68       mrg 	return err;
    752   1.1    ichiro }
    753   1.1    ichiro 
    754  1.68       mrg static void
    755  1.68       mrg url_mii_statchg_cb(struct ifnet *ifp)
    756   1.1    ichiro {
    757  1.68       mrg 	struct usbnet * const un = ifp->if_softc;
    758   1.1    ichiro 
    759  1.44      matt 	DPRINTF(("%s: %s: enter\n", ifp->if_xname, __func__));
    760  1.68       mrg 
    761  1.68       mrg 	/* XXX */
    762  1.68       mrg 	usbnet_set_link(un, true);
    763   1.1    ichiro }
    764   1.1    ichiro 
    765   1.1    ichiro #if 0
    766   1.1    ichiro /*
    767   1.1    ichiro  * external PHYs support, but not test.
    768   1.1    ichiro  */
    769  1.68       mrg static usbd_status
    770  1.68       mrg url_ext_mii_read_reg(struct usbnet *un, int phy, int reg)
    771   1.1    ichiro {
    772  1.51     skrll 	uint16_t val;
    773   1.1    ichiro 
    774   1.1    ichiro 	DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
    775  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg));
    776   1.1    ichiro 
    777  1.68       mrg 	url_csr_write_1(un, URL_PHYADD, phy & URL_PHYADD_MASK);
    778   1.1    ichiro 	/*
    779   1.1    ichiro 	 * RTL8150L will initiate a MII management data transaction
    780   1.1    ichiro 	 * if PHYCNT_OWN bit is set 1 by software. After transaction,
    781   1.1    ichiro 	 * this bit is auto cleared by TRL8150L.
    782   1.1    ichiro 	 */
    783  1.68       mrg 	url_csr_write_1(un, URL_PHYCNT,
    784   1.1    ichiro 			(reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
    785   1.1    ichiro 	for (i = 0; i < URL_TIMEOUT; i++) {
    786  1.68       mrg 		if ((url_csr_read_1(un, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
    787   1.1    ichiro 			break;
    788   1.1    ichiro 	}
    789   1.1    ichiro 	if (i == URL_TIMEOUT) {
    790  1.68       mrg 		printf("%s: MII read timed out\n", device_xname(un->un_dev));
    791   1.1    ichiro 	}
    792   1.5  augustss 
    793  1.68       mrg 	val = url_csr_read_2(un, URL_PHYDAT);
    794   1.1    ichiro 
    795   1.1    ichiro 	DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
    796  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg, val));
    797   1.1    ichiro 
    798  1.68       mrg 	return USBD_NORMAL_COMPLETION;
    799   1.1    ichiro }
    800   1.1    ichiro 
    801  1.68       mrg static usbd_status
    802  1.68       mrg url_ext_mii_write_reg(struct usbnet *un, int phy, int reg, int data)
    803   1.1    ichiro {
    804   1.1    ichiro 
    805   1.1    ichiro 	DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
    806  1.68       mrg 		 device_xname(un->un_dev), __func__, phy, reg, data));
    807   1.1    ichiro 
    808  1.68       mrg 	url_csr_write_2(un, URL_PHYDAT, data);
    809  1.68       mrg 	url_csr_write_1(un, URL_PHYADD, phy);
    810  1.68       mrg 	url_csr_write_1(un, URL_PHYCNT, reg | URL_PHYCNT_RWCR);	/* Write */
    811   1.1    ichiro 
    812   1.1    ichiro 	for (i=0; i < URL_TIMEOUT; i++) {
    813  1.68       mrg 		if (url_csr_read_1(un, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
    814   1.1    ichiro 			break;
    815   1.1    ichiro 	}
    816   1.1    ichiro 
    817   1.1    ichiro 	if (i == URL_TIMEOUT) {
    818   1.1    ichiro 		printf("%s: MII write timed out\n",
    819  1.68       mrg 		       device_xname(un->un_dev));
    820  1.68       mrg 		return USBD_TIMEOUT;
    821   1.1    ichiro 	}
    822   1.1    ichiro 
    823  1.68       mrg 	return USBD_NORMAL_COMPLETION;
    824   1.1    ichiro }
    825   1.1    ichiro #endif
    826  1.68       mrg 
    827  1.68       mrg #ifdef _MODULE
    828  1.68       mrg #include "ioconf.c"
    829  1.68       mrg #endif
    830  1.68       mrg 
    831  1.68       mrg USBNET_MODULE(url)
    832