if_url.c revision 1.80 1 1.80 riastrad /* $NetBSD: if_url.c,v 1.80 2022/03/03 05:50:57 riastradh Exp $ */
2 1.43 mrg
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 2001, 2002
5 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
16 1.1 ichiro * may be used to endorse or promote products derived from this software
17 1.1 ichiro * without specific prior written permission.
18 1.1 ichiro *
19 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 ichiro * SUCH DAMAGE.
30 1.1 ichiro *
31 1.1 ichiro */
32 1.1 ichiro
33 1.1 ichiro /*
34 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
35 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
37 1.1 ichiro */
38 1.1 ichiro
39 1.1 ichiro /*
40 1.1 ichiro * TODO:
41 1.1 ichiro * Interrupt Endpoint support
42 1.1 ichiro * External PHYs
43 1.1 ichiro * powerhook() support?
44 1.1 ichiro */
45 1.1 ichiro
46 1.1 ichiro #include <sys/cdefs.h>
47 1.80 riastrad __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.80 2022/03/03 05:50:57 riastradh Exp $");
48 1.1 ichiro
49 1.46 christos #ifdef _KERNEL_OPT
50 1.1 ichiro #include "opt_inet.h"
51 1.54 skrll #include "opt_usb.h"
52 1.46 christos #endif
53 1.1 ichiro
54 1.1 ichiro #include <sys/param.h>
55 1.1 ichiro
56 1.1 ichiro #include <net/if_ether.h>
57 1.1 ichiro #ifdef INET
58 1.1 ichiro #include <netinet/in.h>
59 1.1 ichiro #include <netinet/if_inarp.h>
60 1.1 ichiro #endif
61 1.1 ichiro
62 1.1 ichiro #include <dev/mii/urlphyreg.h>
63 1.1 ichiro
64 1.68 mrg #include <dev/usb/usbnet.h>
65 1.1 ichiro
66 1.1 ichiro #include <dev/usb/if_urlreg.h>
67 1.1 ichiro
68 1.1 ichiro /* Function declarations */
69 1.72 maxv static int url_match(device_t, cfdata_t, void *);
70 1.72 maxv static void url_attach(device_t, device_t, void *);
71 1.63 mrg
72 1.68 mrg CFATTACH_DECL_NEW(url, sizeof(struct usbnet), url_match, url_attach,
73 1.68 mrg usbnet_detach, usbnet_activate);
74 1.1 ichiro
75 1.76 thorpej static unsigned url_uno_tx_prepare(struct usbnet *, struct mbuf *,
76 1.76 thorpej struct usbnet_chain *);
77 1.76 thorpej static void url_uno_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t);
78 1.76 thorpej static int url_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *);
79 1.76 thorpej static int url_uno_mii_write_reg(struct usbnet *, int, int, uint16_t);
80 1.76 thorpej static int url_uno_ioctl(struct ifnet *, u_long, void *);
81 1.76 thorpej static void url_uno_stop(struct ifnet *, int);
82 1.76 thorpej static void url_uno_mii_statchg(struct ifnet *);
83 1.76 thorpej static int url_uno_init(struct ifnet *);
84 1.77 nisimura static void url_rcvfilt_locked(struct usbnet *);
85 1.68 mrg static void url_reset(struct usbnet *);
86 1.68 mrg
87 1.68 mrg static int url_csr_read_1(struct usbnet *, int);
88 1.68 mrg static int url_csr_read_2(struct usbnet *, int);
89 1.68 mrg static int url_csr_write_1(struct usbnet *, int, int);
90 1.68 mrg static int url_csr_write_2(struct usbnet *, int, int);
91 1.68 mrg static int url_csr_write_4(struct usbnet *, int, int);
92 1.68 mrg static int url_mem(struct usbnet *, int, int, void *, int);
93 1.68 mrg
94 1.72 maxv static const struct usbnet_ops url_ops = {
95 1.76 thorpej .uno_stop = url_uno_stop,
96 1.76 thorpej .uno_ioctl = url_uno_ioctl,
97 1.76 thorpej .uno_read_reg = url_uno_mii_read_reg,
98 1.76 thorpej .uno_write_reg = url_uno_mii_write_reg,
99 1.76 thorpej .uno_statchg = url_uno_mii_statchg,
100 1.76 thorpej .uno_tx_prepare = url_uno_tx_prepare,
101 1.76 thorpej .uno_rx_loop = url_uno_rx_loop,
102 1.76 thorpej .uno_init = url_uno_init,
103 1.68 mrg };
104 1.1 ichiro
105 1.1 ichiro /* Macros */
106 1.1 ichiro #ifdef URL_DEBUG
107 1.38 dyoung #define DPRINTF(x) if (urldebug) printf x
108 1.64 msaitoh #define DPRINTFN(n, x) if (urldebug >= (n)) printf x
109 1.2 ichiro int urldebug = 0;
110 1.1 ichiro #else
111 1.1 ichiro #define DPRINTF(x)
112 1.64 msaitoh #define DPRINTFN(n, x)
113 1.1 ichiro #endif
114 1.1 ichiro
115 1.68 mrg #define URL_SETBIT(un, reg, x) \
116 1.68 mrg url_csr_write_1(un, reg, url_csr_read_1(un, reg) | (x))
117 1.1 ichiro
118 1.68 mrg #define URL_SETBIT2(un, reg, x) \
119 1.68 mrg url_csr_write_2(un, reg, url_csr_read_2(un, reg) | (x))
120 1.1 ichiro
121 1.68 mrg #define URL_CLRBIT(un, reg, x) \
122 1.68 mrg url_csr_write_1(un, reg, url_csr_read_1(un, reg) & ~(x))
123 1.1 ichiro
124 1.68 mrg #define URL_CLRBIT2(un, reg, x) \
125 1.68 mrg url_csr_write_2(un, reg, url_csr_read_2(un, reg) & ~(x))
126 1.1 ichiro
127 1.1 ichiro static const struct url_type {
128 1.1 ichiro struct usb_devno url_dev;
129 1.51 skrll uint16_t url_flags;
130 1.1 ichiro #define URL_EXT_PHY 0x0001
131 1.1 ichiro } url_devs [] = {
132 1.1 ichiro /* MELCO LUA-KTX */
133 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
134 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
135 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
136 1.11 augustss /* Longshine LCS-8138TX */
137 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
138 1.11 augustss /* Micronet SP128AR */
139 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
140 1.13 itojun /* OQO model 01 */
141 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
142 1.1 ichiro };
143 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
144 1.1 ichiro
145 1.1 ichiro
146 1.1 ichiro /* Probe */
147 1.72 maxv static int
148 1.38 dyoung url_match(device_t parent, cfdata_t match, void *aux)
149 1.1 ichiro {
150 1.38 dyoung struct usb_attach_arg *uaa = aux;
151 1.1 ichiro
152 1.51 skrll return url_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ?
153 1.51 skrll UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
154 1.1 ichiro }
155 1.1 ichiro /* Attach */
156 1.72 maxv static void
157 1.38 dyoung url_attach(device_t parent, device_t self, void *aux)
158 1.1 ichiro {
159 1.70 mrg USBNET_MII_DECL_DEFAULT(unm);
160 1.68 mrg struct usbnet * const un = device_private(self);
161 1.38 dyoung struct usb_attach_arg *uaa = aux;
162 1.51 skrll struct usbd_device *dev = uaa->uaa_device;
163 1.51 skrll struct usbd_interface *iface;
164 1.1 ichiro usbd_status err;
165 1.1 ichiro usb_interface_descriptor_t *id;
166 1.1 ichiro usb_endpoint_descriptor_t *ed;
167 1.16 augustss char *devinfop;
168 1.68 mrg int i;
169 1.32 cube
170 1.34 plunky aprint_naive("\n");
171 1.34 plunky aprint_normal("\n");
172 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
173 1.32 cube aprint_normal_dev(self, "%s\n", devinfop);
174 1.16 augustss usbd_devinfo_free(devinfop);
175 1.1 ichiro
176 1.68 mrg un->un_dev = self;
177 1.68 mrg un->un_udev = dev;
178 1.68 mrg un->un_sc = un;
179 1.68 mrg un->un_ops = &url_ops;
180 1.68 mrg un->un_rx_xfer_flags = USBD_SHORT_XFER_OK;
181 1.68 mrg un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER;
182 1.68 mrg un->un_rx_list_cnt = URL_RX_LIST_CNT;
183 1.68 mrg un->un_tx_list_cnt = URL_TX_LIST_CNT;
184 1.68 mrg un->un_rx_bufsz = URL_BUFSZ;
185 1.68 mrg un->un_tx_bufsz = URL_BUFSZ;
186 1.68 mrg
187 1.1 ichiro /* Move the device into the configured state. */
188 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
189 1.1 ichiro if (err) {
190 1.45 skrll aprint_error_dev(self, "failed to set configuration"
191 1.45 skrll ", err=%s\n", usbd_errstr(err));
192 1.71 mrg return;
193 1.1 ichiro }
194 1.1 ichiro
195 1.1 ichiro /* get control interface */
196 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
197 1.1 ichiro if (err) {
198 1.32 cube aprint_error_dev(self, "failed to get interface, err=%s\n",
199 1.1 ichiro usbd_errstr(err));
200 1.71 mrg return;
201 1.1 ichiro }
202 1.1 ichiro
203 1.68 mrg un->un_iface = iface;
204 1.68 mrg un->un_flags = url_lookup(uaa->uaa_vendor, uaa->uaa_product)->url_flags;
205 1.68 mrg #if 0
206 1.68 mrg if (un->un_flags & URL_EXT_PHY) {
207 1.68 mrg un->un_read_reg_cb = url_ext_mii_read_reg;
208 1.68 mrg un->un_write_reg_cb = url_ext_mii_write_reg;
209 1.68 mrg }
210 1.68 mrg #endif
211 1.1 ichiro
212 1.1 ichiro /* get interface descriptor */
213 1.68 mrg id = usbd_get_interface_descriptor(un->un_iface);
214 1.1 ichiro
215 1.1 ichiro /* find endpoints */
216 1.68 mrg un->un_ed[USBNET_ENDPT_RX] = un->un_ed[USBNET_ENDPT_TX] =
217 1.68 mrg un->un_ed[USBNET_ENDPT_INTR] = 0;
218 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
219 1.68 mrg ed = usbd_interface2endpoint_descriptor(un->un_iface, i);
220 1.1 ichiro if (ed == NULL) {
221 1.32 cube aprint_error_dev(self,
222 1.32 cube "couldn't get endpoint %d\n", i);
223 1.71 mrg return;
224 1.1 ichiro }
225 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
226 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
227 1.68 mrg un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress;
228 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
229 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
230 1.68 mrg un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress;
231 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
232 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
233 1.68 mrg un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress;
234 1.1 ichiro }
235 1.1 ichiro
236 1.68 mrg if (un->un_ed[USBNET_ENDPT_RX] == 0 ||
237 1.68 mrg un->un_ed[USBNET_ENDPT_TX] == 0 ||
238 1.68 mrg un->un_ed[USBNET_ENDPT_INTR] == 0) {
239 1.32 cube aprint_error_dev(self, "missing endpoint\n");
240 1.71 mrg return;
241 1.1 ichiro }
242 1.1 ichiro
243 1.68 mrg /* Set these up now for url_mem(). */
244 1.68 mrg usbnet_attach(un, "urldet");
245 1.1 ichiro
246 1.76 thorpej usbnet_lock_core(un);
247 1.76 thorpej usbnet_busy(un);
248 1.76 thorpej
249 1.1 ichiro /* reset the adapter */
250 1.68 mrg url_reset(un);
251 1.1 ichiro
252 1.1 ichiro /* Get Ethernet Address */
253 1.68 mrg err = url_mem(un, URL_CMD_READMEM, URL_IDR0, (void *)un->un_eaddr,
254 1.1 ichiro ETHER_ADDR_LEN);
255 1.76 thorpej usbnet_unbusy(un);
256 1.76 thorpej usbnet_unlock_core(un);
257 1.1 ichiro if (err) {
258 1.32 cube aprint_error_dev(self, "read MAC address failed\n");
259 1.78 riastrad return;
260 1.1 ichiro }
261 1.1 ichiro
262 1.19 wiz /* initialize interface information */
263 1.69 mrg usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST,
264 1.69 mrg 0, &unm);
265 1.1 ichiro }
266 1.1 ichiro
267 1.1 ichiro /* read/write memory */
268 1.68 mrg static int
269 1.68 mrg url_mem(struct usbnet *un, int cmd, int offset, void *buf, int len)
270 1.1 ichiro {
271 1.1 ichiro usb_device_request_t req;
272 1.1 ichiro usbd_status err;
273 1.1 ichiro
274 1.76 thorpej usbnet_isowned_core(un);
275 1.1 ichiro
276 1.1 ichiro DPRINTFN(0x200,
277 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
278 1.1 ichiro
279 1.68 mrg if (usbnet_isdying(un))
280 1.51 skrll return 0;
281 1.1 ichiro
282 1.1 ichiro if (cmd == URL_CMD_READMEM)
283 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
284 1.1 ichiro else
285 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
286 1.1 ichiro req.bRequest = URL_REQ_MEM;
287 1.1 ichiro USETW(req.wValue, offset);
288 1.1 ichiro USETW(req.wIndex, 0x0000);
289 1.1 ichiro USETW(req.wLength, len);
290 1.1 ichiro
291 1.68 mrg err = usbd_do_request(un->un_udev, &req, buf);
292 1.1 ichiro if (err) {
293 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
294 1.68 mrg device_xname(un->un_dev),
295 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
296 1.1 ichiro offset, err));
297 1.5 augustss }
298 1.1 ichiro
299 1.51 skrll return err;
300 1.1 ichiro }
301 1.1 ichiro
302 1.1 ichiro /* read 1byte from register */
303 1.68 mrg static int
304 1.68 mrg url_csr_read_1(struct usbnet *un, int reg)
305 1.1 ichiro {
306 1.51 skrll uint8_t val = 0;
307 1.1 ichiro
308 1.1 ichiro DPRINTFN(0x100,
309 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
310 1.5 augustss
311 1.68 mrg return url_mem(un, URL_CMD_READMEM, reg, &val, 1) ? 0 : val;
312 1.1 ichiro }
313 1.1 ichiro
314 1.1 ichiro /* read 2bytes from register */
315 1.68 mrg static int
316 1.68 mrg url_csr_read_2(struct usbnet *un, int reg)
317 1.1 ichiro {
318 1.1 ichiro uWord val;
319 1.1 ichiro
320 1.1 ichiro DPRINTFN(0x100,
321 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
322 1.5 augustss
323 1.1 ichiro USETW(val, 0);
324 1.68 mrg return url_mem(un, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val);
325 1.1 ichiro }
326 1.1 ichiro
327 1.1 ichiro /* write 1byte to register */
328 1.68 mrg static int
329 1.68 mrg url_csr_write_1(struct usbnet *un, int reg, int aval)
330 1.1 ichiro {
331 1.51 skrll uint8_t val = aval;
332 1.1 ichiro
333 1.1 ichiro DPRINTFN(0x100,
334 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
335 1.1 ichiro
336 1.68 mrg return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0;
337 1.1 ichiro }
338 1.1 ichiro
339 1.1 ichiro /* write 2bytes to register */
340 1.68 mrg static int
341 1.68 mrg url_csr_write_2(struct usbnet *un, int reg, int aval)
342 1.1 ichiro {
343 1.1 ichiro uWord val;
344 1.1 ichiro
345 1.1 ichiro DPRINTFN(0x100,
346 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
347 1.1 ichiro
348 1.1 ichiro USETW(val, aval);
349 1.1 ichiro
350 1.68 mrg return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0;
351 1.1 ichiro }
352 1.1 ichiro
353 1.1 ichiro /* write 4bytes to register */
354 1.68 mrg static int
355 1.68 mrg url_csr_write_4(struct usbnet *un, int reg, int aval)
356 1.1 ichiro {
357 1.1 ichiro uDWord val;
358 1.1 ichiro
359 1.1 ichiro DPRINTFN(0x100,
360 1.68 mrg ("%s: %s: enter\n", device_xname(un->un_dev), __func__));
361 1.1 ichiro
362 1.1 ichiro USETDW(val, aval);
363 1.1 ichiro
364 1.68 mrg return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0;
365 1.1 ichiro }
366 1.1 ichiro
367 1.68 mrg static int
368 1.68 mrg url_init_locked(struct ifnet *ifp)
369 1.1 ichiro {
370 1.68 mrg struct usbnet * const un = ifp->if_softc;
371 1.29 dyoung const u_char *eaddr;
372 1.68 mrg int i;
373 1.1 ichiro
374 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
375 1.5 augustss
376 1.76 thorpej usbnet_isowned_core(un);
377 1.68 mrg
378 1.68 mrg if (usbnet_isdying(un))
379 1.51 skrll return EIO;
380 1.1 ichiro
381 1.68 mrg /* Cancel pending I/O and free all TX/RX buffers */
382 1.68 mrg usbnet_stop(un, ifp, 1);
383 1.1 ichiro
384 1.29 dyoung eaddr = CLLADDR(ifp->if_sadl);
385 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
386 1.68 mrg url_csr_write_1(un, URL_IDR0 + i, eaddr[i]);
387 1.1 ichiro
388 1.1 ichiro /* Init transmission control register */
389 1.68 mrg URL_CLRBIT(un, URL_TCR,
390 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
391 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
392 1.1 ichiro URL_TCR_NOCRC);
393 1.1 ichiro
394 1.1 ichiro /* Init receive control register */
395 1.77 nisimura URL_SETBIT2(un, URL_RCR, URL_RCR_TAIL | URL_RCR_AD | URL_RCR_AB);
396 1.5 augustss
397 1.77 nisimura /* Accept multicast frame or run promisc. mode */
398 1.77 nisimura url_rcvfilt_locked(un);
399 1.1 ichiro
400 1.1 ichiro /* Enable RX and TX */
401 1.68 mrg URL_SETBIT(un, URL_CR, URL_CR_TE | URL_CR_RE);
402 1.51 skrll
403 1.68 mrg return usbnet_init_rx_tx(un);
404 1.68 mrg }
405 1.1 ichiro
406 1.68 mrg static int
407 1.76 thorpej url_uno_init(struct ifnet *ifp)
408 1.68 mrg {
409 1.68 mrg struct usbnet * const un = ifp->if_softc;
410 1.1 ichiro
411 1.76 thorpej usbnet_busy(un);
412 1.68 mrg int ret = url_init_locked(ifp);
413 1.76 thorpej usbnet_unbusy(un);
414 1.1 ichiro
415 1.68 mrg return ret;
416 1.1 ichiro }
417 1.1 ichiro
418 1.68 mrg static void
419 1.68 mrg url_reset(struct usbnet *un)
420 1.1 ichiro {
421 1.1 ichiro int i;
422 1.5 augustss
423 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
424 1.1 ichiro
425 1.68 mrg if (usbnet_isdying(un))
426 1.1 ichiro return;
427 1.1 ichiro
428 1.68 mrg URL_SETBIT(un, URL_CR, URL_CR_SOFT_RST);
429 1.1 ichiro
430 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
431 1.80 riastrad if (usbnet_isdying(un))
432 1.80 riastrad return;
433 1.68 mrg if (!(url_csr_read_1(un, URL_CR) & URL_CR_SOFT_RST))
434 1.1 ichiro break;
435 1.1 ichiro delay(10); /* XXX */
436 1.1 ichiro }
437 1.1 ichiro
438 1.1 ichiro delay(10000); /* XXX */
439 1.1 ichiro }
440 1.1 ichiro
441 1.68 mrg static void
442 1.77 nisimura url_rcvfilt_locked(struct usbnet *un)
443 1.1 ichiro {
444 1.68 mrg struct ifnet * const ifp = usbnet_ifp(un);
445 1.68 mrg struct ethercom *ec = usbnet_ec(un);
446 1.1 ichiro struct ether_multi *enm;
447 1.1 ichiro struct ether_multistep step;
448 1.77 nisimura uint32_t mchash[2] = { 0, 0 };
449 1.77 nisimura int h = 0, rcr;
450 1.1 ichiro
451 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
452 1.1 ichiro
453 1.76 thorpej usbnet_isowned_core(un);
454 1.68 mrg
455 1.68 mrg if (usbnet_isdying(un))
456 1.1 ichiro return;
457 1.1 ichiro
458 1.77 nisimura rcr = url_csr_read_2(un, URL_RCR);
459 1.77 nisimura rcr &= ~(URL_RCR_AAP | URL_RCR_AAM | URL_RCR_AM);
460 1.77 nisimura
461 1.77 nisimura ETHER_LOCK(ec);
462 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
463 1.77 nisimura ec->ec_flags |= ETHER_F_ALLMULTI;
464 1.77 nisimura ETHER_UNLOCK(ec);
465 1.77 nisimura /* run promisc. mode */
466 1.77 nisimura rcr |= URL_RCR_AAM; /* ??? */
467 1.77 nisimura rcr |= URL_RCR_AAP;
468 1.77 nisimura goto update;
469 1.1 ichiro }
470 1.77 nisimura ec->ec_flags &= ~ETHER_F_ALLMULTI;
471 1.65 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
472 1.1 ichiro while (enm != NULL) {
473 1.77 nisimura if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
474 1.77 nisimura ec->ec_flags |= ETHER_F_ALLMULTI;
475 1.65 msaitoh ETHER_UNLOCK(ec);
476 1.77 nisimura /* accept all multicast frames */
477 1.77 nisimura rcr |= URL_RCR_AAM;
478 1.77 nisimura goto update;
479 1.65 msaitoh }
480 1.77 nisimura h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
481 1.77 nisimura /* 1(31) and 5(30:26) bit sampling */
482 1.77 nisimura mchash[h >> 31] |= 1 << ((h >> 26) & 0x1f);
483 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
484 1.1 ichiro }
485 1.65 msaitoh ETHER_UNLOCK(ec);
486 1.77 nisimura if (h != 0)
487 1.77 nisimura rcr |= URL_RCR_AM; /* activate mcast hash filter */
488 1.77 nisimura url_csr_write_4(un, URL_MAR0, mchash[0]);
489 1.77 nisimura url_csr_write_4(un, URL_MAR4, mchash[1]);
490 1.77 nisimura update:
491 1.77 nisimura url_csr_write_2(un, URL_RCR, rcr);
492 1.1 ichiro }
493 1.1 ichiro
494 1.68 mrg static unsigned
495 1.76 thorpej url_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c)
496 1.1 ichiro {
497 1.68 mrg int total_len;
498 1.1 ichiro
499 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev),__func__));
500 1.5 augustss
501 1.68 mrg KASSERT(un->un_tx_bufsz >= URL_MIN_FRAME_LEN);
502 1.68 mrg if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz)
503 1.68 mrg return 0;
504 1.1 ichiro
505 1.1 ichiro /* Copy the mbuf data into a contiguous buffer */
506 1.68 mrg m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf);
507 1.1 ichiro total_len = m->m_pkthdr.len;
508 1.1 ichiro
509 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
510 1.68 mrg memset(c->unc_buf + total_len, 0,
511 1.7 bouyer URL_MIN_FRAME_LEN - total_len);
512 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
513 1.7 bouyer }
514 1.1 ichiro
515 1.68 mrg DPRINTF(("%s: %s: send %d bytes\n", device_xname(un->un_dev),
516 1.4 augustss __func__, total_len));
517 1.1 ichiro
518 1.68 mrg return total_len;
519 1.1 ichiro }
520 1.1 ichiro
521 1.68 mrg static void
522 1.76 thorpej url_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len)
523 1.1 ichiro {
524 1.68 mrg struct ifnet *ifp = usbnet_ifp(un);
525 1.1 ichiro url_rxhdr_t rxhdr;
526 1.1 ichiro
527 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev),__func__));
528 1.1 ichiro
529 1.68 mrg if (total_len <= ETHER_CRC_LEN || total_len <= sizeof(rxhdr)) {
530 1.73 thorpej if_statinc(ifp, if_ierrors);
531 1.68 mrg return;
532 1.1 ichiro }
533 1.1 ichiro
534 1.68 mrg memcpy(&rxhdr, c->unc_buf + total_len - ETHER_CRC_LEN, sizeof(rxhdr));
535 1.1 ichiro
536 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
537 1.68 mrg device_xname(un->un_dev),
538 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
539 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
540 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
541 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
542 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
543 1.1 ichiro
544 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
545 1.73 thorpej if_statinc(ifp, if_ierrors);
546 1.68 mrg return;
547 1.1 ichiro }
548 1.1 ichiro
549 1.1 ichiro total_len -= ETHER_CRC_LEN;
550 1.1 ichiro
551 1.68 mrg DPRINTF(("%s: %s: deliver %d\n", device_xname(un->un_dev),
552 1.68 mrg __func__, total_len));
553 1.68 mrg usbnet_enqueue(un, c->unc_buf, total_len, 0, 0, 0);
554 1.1 ichiro }
555 1.1 ichiro
556 1.1 ichiro #if 0
557 1.68 mrg static void url_intr(void)
558 1.1 ichiro {
559 1.1 ichiro }
560 1.1 ichiro #endif
561 1.1 ichiro
562 1.68 mrg static int
563 1.76 thorpej url_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data)
564 1.1 ichiro {
565 1.68 mrg struct usbnet * const un = ifp->if_softc;
566 1.1 ichiro
567 1.76 thorpej usbnet_lock_core(un);
568 1.76 thorpej usbnet_busy(un);
569 1.76 thorpej
570 1.68 mrg switch (cmd) {
571 1.68 mrg case SIOCADDMULTI:
572 1.68 mrg case SIOCDELMULTI:
573 1.77 nisimura url_rcvfilt_locked(un);
574 1.68 mrg break;
575 1.68 mrg default:
576 1.68 mrg break;
577 1.1 ichiro }
578 1.1 ichiro
579 1.76 thorpej usbnet_unbusy(un);
580 1.76 thorpej usbnet_unlock_core(un);
581 1.76 thorpej
582 1.68 mrg return 0;
583 1.1 ichiro }
584 1.1 ichiro
585 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
586 1.68 mrg static void
587 1.76 thorpej url_uno_stop(struct ifnet *ifp, int disable)
588 1.1 ichiro {
589 1.68 mrg struct usbnet * const un = ifp->if_softc;
590 1.1 ichiro
591 1.68 mrg DPRINTF(("%s: %s: enter\n", device_xname(un->un_dev), __func__));
592 1.1 ichiro
593 1.68 mrg url_reset(un);
594 1.1 ichiro }
595 1.1 ichiro
596 1.69 mrg static int
597 1.76 thorpej url_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)
598 1.1 ichiro {
599 1.61 msaitoh uint16_t data;
600 1.68 mrg usbd_status err = USBD_NORMAL_COMPLETION;
601 1.1 ichiro
602 1.75 christos DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
603 1.68 mrg device_xname(un->un_dev), __func__, phy, reg));
604 1.1 ichiro
605 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
606 1.1 ichiro if (phy != 0) {
607 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
608 1.68 mrg device_xname(un->un_dev), __func__, phy));
609 1.69 mrg return EINVAL;
610 1.1 ichiro }
611 1.1 ichiro
612 1.1 ichiro switch (reg) {
613 1.1 ichiro case MII_BMCR: /* Control Register */
614 1.1 ichiro reg = URL_BMCR;
615 1.1 ichiro break;
616 1.1 ichiro case MII_BMSR: /* Status Register */
617 1.1 ichiro reg = URL_BMSR;
618 1.1 ichiro break;
619 1.1 ichiro case MII_PHYIDR1:
620 1.1 ichiro case MII_PHYIDR2:
621 1.61 msaitoh *val = 0;
622 1.1 ichiro goto R_DONE;
623 1.1 ichiro break;
624 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
625 1.1 ichiro reg = URL_ANAR;
626 1.1 ichiro break;
627 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
628 1.1 ichiro reg = URL_ANLP;
629 1.1 ichiro break;
630 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
631 1.1 ichiro reg = URL_MSR;
632 1.1 ichiro break;
633 1.1 ichiro default:
634 1.1 ichiro printf("%s: %s: bad register %04x\n",
635 1.68 mrg device_xname(un->un_dev), __func__, reg);
636 1.69 mrg return EINVAL;
637 1.1 ichiro }
638 1.1 ichiro
639 1.1 ichiro if (reg == URL_MSR)
640 1.68 mrg data = url_csr_read_1(un, reg);
641 1.1 ichiro else
642 1.68 mrg data = url_csr_read_2(un, reg);
643 1.61 msaitoh *val = data;
644 1.1 ichiro
645 1.1 ichiro R_DONE:
646 1.75 christos DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04hx\n",
647 1.68 mrg device_xname(un->un_dev), __func__, phy, reg, *val));
648 1.1 ichiro
649 1.68 mrg return err;
650 1.1 ichiro }
651 1.1 ichiro
652 1.69 mrg static int
653 1.76 thorpej url_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)
654 1.1 ichiro {
655 1.1 ichiro
656 1.75 christos DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x val=0x%04hx\n",
657 1.68 mrg device_xname(un->un_dev), __func__, phy, reg, val));
658 1.1 ichiro
659 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
660 1.1 ichiro if (phy != 0) {
661 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
662 1.68 mrg device_xname(un->un_dev), __func__, phy));
663 1.69 mrg return EINVAL;
664 1.1 ichiro }
665 1.1 ichiro
666 1.1 ichiro switch (reg) {
667 1.1 ichiro case MII_BMCR: /* Control Register */
668 1.1 ichiro reg = URL_BMCR;
669 1.1 ichiro break;
670 1.1 ichiro case MII_BMSR: /* Status Register */
671 1.1 ichiro reg = URL_BMSR;
672 1.1 ichiro break;
673 1.1 ichiro case MII_PHYIDR1:
674 1.1 ichiro case MII_PHYIDR2:
675 1.69 mrg return 0;
676 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
677 1.1 ichiro reg = URL_ANAR;
678 1.1 ichiro break;
679 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
680 1.1 ichiro reg = URL_ANLP;
681 1.1 ichiro break;
682 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
683 1.1 ichiro reg = URL_MSR;
684 1.1 ichiro break;
685 1.1 ichiro default:
686 1.1 ichiro printf("%s: %s: bad register %04x\n",
687 1.68 mrg device_xname(un->un_dev), __func__, reg);
688 1.69 mrg return EINVAL;
689 1.1 ichiro }
690 1.1 ichiro
691 1.1 ichiro if (reg == URL_MSR)
692 1.68 mrg url_csr_write_1(un, reg, val);
693 1.1 ichiro else
694 1.68 mrg url_csr_write_2(un, reg, val);
695 1.1 ichiro
696 1.69 mrg return 0;
697 1.1 ichiro }
698 1.1 ichiro
699 1.68 mrg static void
700 1.76 thorpej url_uno_mii_statchg(struct ifnet *ifp)
701 1.1 ichiro {
702 1.68 mrg struct usbnet * const un = ifp->if_softc;
703 1.1 ichiro
704 1.44 matt DPRINTF(("%s: %s: enter\n", ifp->if_xname, __func__));
705 1.68 mrg
706 1.68 mrg /* XXX */
707 1.68 mrg usbnet_set_link(un, true);
708 1.1 ichiro }
709 1.1 ichiro
710 1.1 ichiro #if 0
711 1.1 ichiro /*
712 1.1 ichiro * external PHYs support, but not test.
713 1.1 ichiro */
714 1.68 mrg static usbd_status
715 1.68 mrg url_ext_mii_read_reg(struct usbnet *un, int phy, int reg)
716 1.1 ichiro {
717 1.51 skrll uint16_t val;
718 1.1 ichiro
719 1.75 christos DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
720 1.68 mrg device_xname(un->un_dev), __func__, phy, reg));
721 1.1 ichiro
722 1.68 mrg url_csr_write_1(un, URL_PHYADD, phy & URL_PHYADD_MASK);
723 1.1 ichiro /*
724 1.1 ichiro * RTL8150L will initiate a MII management data transaction
725 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
726 1.1 ichiro * this bit is auto cleared by TRL8150L.
727 1.1 ichiro */
728 1.68 mrg url_csr_write_1(un, URL_PHYCNT,
729 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
730 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
731 1.68 mrg if ((url_csr_read_1(un, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
732 1.1 ichiro break;
733 1.1 ichiro }
734 1.1 ichiro if (i == URL_TIMEOUT) {
735 1.68 mrg printf("%s: MII read timed out\n", device_xname(un->un_dev));
736 1.1 ichiro }
737 1.5 augustss
738 1.68 mrg val = url_csr_read_2(un, URL_PHYDAT);
739 1.1 ichiro
740 1.75 christos DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
741 1.68 mrg device_xname(un->un_dev), __func__, phy, reg, val));
742 1.1 ichiro
743 1.68 mrg return USBD_NORMAL_COMPLETION;
744 1.1 ichiro }
745 1.1 ichiro
746 1.68 mrg static usbd_status
747 1.68 mrg url_ext_mii_write_reg(struct usbnet *un, int phy, int reg, int data)
748 1.1 ichiro {
749 1.1 ichiro
750 1.75 christos DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
751 1.68 mrg device_xname(un->un_dev), __func__, phy, reg, data));
752 1.1 ichiro
753 1.68 mrg url_csr_write_2(un, URL_PHYDAT, data);
754 1.68 mrg url_csr_write_1(un, URL_PHYADD, phy);
755 1.68 mrg url_csr_write_1(un, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
756 1.1 ichiro
757 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
758 1.68 mrg if (url_csr_read_1(un, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
759 1.1 ichiro break;
760 1.1 ichiro }
761 1.1 ichiro
762 1.1 ichiro if (i == URL_TIMEOUT) {
763 1.1 ichiro printf("%s: MII write timed out\n",
764 1.68 mrg device_xname(un->un_dev));
765 1.68 mrg return USBD_TIMEOUT;
766 1.1 ichiro }
767 1.1 ichiro
768 1.68 mrg return USBD_NORMAL_COMPLETION;
769 1.1 ichiro }
770 1.1 ichiro #endif
771 1.68 mrg
772 1.68 mrg #ifdef _MODULE
773 1.68 mrg #include "ioconf.c"
774 1.68 mrg #endif
775 1.68 mrg
776 1.68 mrg USBNET_MODULE(url)
777