if_urtw.c revision 1.1.2.2
1 /* $NetBSD: if_urtw.c,v 1.1.2.2 2012/06/02 11:09:29 mrg Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.1.2.2 2012/06/02 11:09:29 mrg Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/sockio.h> 26 #include <sys/proc.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 38 #include <machine/endian.h> 39 #include <net/bpf.h> 40 #include <net/if.h> 41 #include <net/if_arp.h> 42 #include <net/if_dl.h> 43 #include <net/if_ether.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_inarp.h> 51 #include <netinet/ip.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include "if_urtwreg.h" 63 64 #ifdef USB_DEBUG 65 #define URTW_DEBUG 66 #endif 67 68 #ifdef URTW_DEBUG 69 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 70 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 71 int urtw_debug = 0; 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 /* 78 * Recognized device vendors/products. 79 */ 80 static const struct urtw_type { 81 struct usb_devno dev; 82 uint8_t rev; 83 } urtw_devs[] = { 84 #define URTW_DEV_RTL8187(v, p) \ 85 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 86 #define URTW_DEV_RTL8187B(v, p) \ 87 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 88 /* Realtek RTL8187 devices. */ 89 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 90 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 91 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 92 URTW_DEV_RTL8187(LOGITEC, RTL8187), 93 URTW_DEV_RTL8187(NETGEAR, WG111V2), 94 URTW_DEV_RTL8187(REALTEK, RTL8187), 95 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 96 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 97 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 98 /* Realtek RTL8187B devices. */ 99 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 100 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 101 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 102 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 103 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 104 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 105 #undef URTW_DEV_RTL8187 106 #undef URTW_DEV_RTL8187B 107 }; 108 #define urtw_lookup(v, p) \ 109 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 110 111 /* 112 * Helper read/write macros. 113 */ 114 #define urtw_read8_m(sc, val, data) do { \ 115 error = urtw_read8_c(sc, val, data, 0); \ 116 if (error != 0) \ 117 goto fail; \ 118 } while (0) 119 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 120 error = urtw_read8_c(sc, val, data, idx); \ 121 if (error != 0) \ 122 goto fail; \ 123 } while (0) 124 #define urtw_write8_m(sc, val, data) do { \ 125 error = urtw_write8_c(sc, val, data, 0); \ 126 if (error != 0) \ 127 goto fail; \ 128 } while (0) 129 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 130 error = urtw_write8_c(sc, val, data, idx); \ 131 if (error != 0) \ 132 goto fail; \ 133 } while (0) 134 #define urtw_read16_m(sc, val, data) do { \ 135 error = urtw_read16_c(sc, val, data, 0); \ 136 if (error != 0) \ 137 goto fail; \ 138 } while (0) 139 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 140 error = urtw_read16_c(sc, val, data, idx); \ 141 if (error != 0) \ 142 goto fail; \ 143 } while (0) 144 #define urtw_write16_m(sc, val, data) do { \ 145 error = urtw_write16_c(sc, val, data, 0); \ 146 if (error != 0) \ 147 goto fail; \ 148 } while (0) 149 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 150 error = urtw_write16_c(sc, val, data, idx); \ 151 if (error != 0) \ 152 goto fail; \ 153 } while (0) 154 #define urtw_read32_m(sc, val, data) do { \ 155 error = urtw_read32_c(sc, val, data, 0); \ 156 if (error != 0) \ 157 goto fail; \ 158 } while (0) 159 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 160 error = urtw_read32_c(sc, val, data, idx); \ 161 if (error != 0) \ 162 goto fail; \ 163 } while (0) 164 #define urtw_write32_m(sc, val, data) do { \ 165 error = urtw_write32_c(sc, val, data, 0); \ 166 if (error != 0) \ 167 goto fail; \ 168 } while (0) 169 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 170 error = urtw_write32_c(sc, val, data, idx); \ 171 if (error != 0) \ 172 goto fail; \ 173 } while (0) 174 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 175 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 176 if (error != 0) \ 177 goto fail; \ 178 } while (0) 179 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 180 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 181 if (error != 0) \ 182 goto fail; \ 183 } while (0) 184 #define urtw_8225_write(sc, val, data) do { \ 185 error = urtw_8225_write_c(sc, val, data); \ 186 if (error != 0) \ 187 goto fail; \ 188 } while (0) 189 190 struct urtw_pair { 191 uint32_t reg; 192 uint32_t val; 193 }; 194 195 struct urtw_pair_idx { 196 uint8_t reg; 197 uint8_t val; 198 uint8_t idx; 199 }; 200 201 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 202 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 203 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 204 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 205 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 206 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 207 { 0xff, 0x00, 0 }, 208 209 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 210 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 211 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 212 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 213 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 214 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 215 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 216 { 0xf8, 0x08, 1 }, 217 218 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 219 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 220 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 221 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 222 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 223 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 224 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 225 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 226 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 227 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 228 229 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 230 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 231 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 232 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 233 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 234 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 235 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 236 237 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 238 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 239 }; 240 241 static uint8_t urtw_8225_agc[] = { 242 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 243 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 244 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 245 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 246 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 247 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 248 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 249 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 250 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 251 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 252 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 253 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 254 }; 255 256 static uint32_t urtw_8225_channel[] = { 257 0x0000, /* dummy channel 0 */ 258 0x085c, /* 1 */ 259 0x08dc, /* 2 */ 260 0x095c, /* 3 */ 261 0x09dc, /* 4 */ 262 0x0a5c, /* 5 */ 263 0x0adc, /* 6 */ 264 0x0b5c, /* 7 */ 265 0x0bdc, /* 8 */ 266 0x0c5c, /* 9 */ 267 0x0cdc, /* 10 */ 268 0x0d5c, /* 11 */ 269 0x0ddc, /* 12 */ 270 0x0e5c, /* 13 */ 271 0x0f72, /* 14 */ 272 }; 273 274 static uint8_t urtw_8225_gain[] = { 275 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 276 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 277 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 278 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 279 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 280 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 281 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 282 }; 283 284 static struct urtw_pair urtw_8225_rf_part1[] = { 285 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 286 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 287 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 288 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 289 }; 290 291 static struct urtw_pair urtw_8225_rf_part2[] = { 292 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 293 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 294 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 295 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 296 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 297 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 298 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 299 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 300 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 301 { 0x27, 0x88 } 302 }; 303 304 static struct urtw_pair urtw_8225_rf_part3[] = { 305 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 306 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 307 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 308 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 309 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 310 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 311 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 312 }; 313 314 static uint16_t urtw_8225_rxgain[] = { 315 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 316 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 317 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 318 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 319 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 320 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 321 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 322 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 323 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 324 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 325 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 326 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 327 }; 328 329 static uint8_t urtw_8225_threshold[] = { 330 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 331 }; 332 333 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 334 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 335 }; 336 337 static uint8_t urtw_8225_txpwr_cck[] = { 338 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 339 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 340 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 341 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 342 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 343 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 344 }; 345 346 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 347 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 348 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 349 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 350 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 351 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 352 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 353 }; 354 355 static uint8_t urtw_8225_txpwr_ofdm[] = { 356 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 357 }; 358 359 static uint8_t urtw_8225v2_agc[] = { 360 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 361 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 362 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 363 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 364 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 365 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 366 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 367 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 368 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 369 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 370 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 371 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 372 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 373 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 374 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 375 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 376 }; 377 378 static uint8_t urtw_8225v2_ofdm[] = { 379 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 380 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 381 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 382 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 383 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 384 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 385 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 386 0x6d, 0x3c, 0xfb, 0x07 387 }; 388 389 static uint8_t urtw_8225v2_gain_bg[] = { 390 0x23, 0x15, 0xa5, /* -82-1dbm */ 391 0x23, 0x15, 0xb5, /* -82-2dbm */ 392 0x23, 0x15, 0xc5, /* -82-3dbm */ 393 0x33, 0x15, 0xc5, /* -78dbm */ 394 0x43, 0x15, 0xc5, /* -74dbm */ 395 0x53, 0x15, 0xc5, /* -70dbm */ 396 0x63, 0x15, 0xc5, /* -66dbm */ 397 }; 398 399 static struct urtw_pair urtw_8225v2_rf_part1[] = { 400 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 401 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 402 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 403 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 404 }; 405 406 static struct urtw_pair urtw_8225v2_rf_part2[] = { 407 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 408 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 409 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 410 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 411 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 412 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 413 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 414 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 415 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 416 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 417 }; 418 419 static struct urtw_pair urtw_8225v2_rf_part3[] = { 420 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 421 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 422 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 423 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 424 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 425 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 426 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 427 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 428 }; 429 430 static uint16_t urtw_8225v2_rxgain[] = { 431 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 432 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 433 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 434 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 435 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 436 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 437 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 438 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 439 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 440 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 441 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 442 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 443 }; 444 445 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 446 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 447 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 448 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 449 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 450 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 451 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 452 }; 453 454 static uint8_t urtw_8225v2_txpwr_cck[] = { 455 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 456 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 457 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 458 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 459 }; 460 461 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 462 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 463 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 464 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 465 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 466 }; 467 468 static struct urtw_pair urtw_8225v2_b_rf[] = { 469 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 470 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 471 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 472 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 473 { 0x00, 0x01b7 } 474 }; 475 476 static struct urtw_pair urtw_ratetable[] = { 477 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 478 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 479 { 96, 10 }, { 108, 11 } 480 }; 481 482 int urtw_init(struct ifnet *); 483 void urtw_stop(struct ifnet *, int); 484 int urtw_ioctl(struct ifnet *, u_long, void *); 485 void urtw_start(struct ifnet *); 486 int urtw_alloc_rx_data_list(struct urtw_softc *); 487 void urtw_free_rx_data_list(struct urtw_softc *); 488 int urtw_alloc_tx_data_list(struct urtw_softc *); 489 void urtw_free_tx_data_list(struct urtw_softc *); 490 void urtw_rxeof(usbd_xfer_handle, usbd_private_handle, 491 usbd_status); 492 int urtw_tx_start(struct urtw_softc *, 493 struct ieee80211_node *, struct mbuf *, int); 494 void urtw_txeof_low(usbd_xfer_handle, usbd_private_handle, 495 usbd_status); 496 void urtw_txeof_normal(usbd_xfer_handle, usbd_private_handle, 497 usbd_status); 498 void urtw_next_scan(void *); 499 void urtw_task(void *); 500 void urtw_ledusbtask(void *); 501 void urtw_ledtask(void *); 502 int urtw_media_change(struct ifnet *); 503 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 504 void urtw_watchdog(struct ifnet *); 505 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 506 int urtw_isbmode(uint16_t); 507 uint16_t urtw_rate2rtl(int rate); 508 uint16_t urtw_rtl2rate(int); 509 usbd_status urtw_set_rate(struct urtw_softc *); 510 usbd_status urtw_update_msr(struct urtw_softc *); 511 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 512 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 513 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 514 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 515 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 516 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 517 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 518 usbd_status urtw_eprom_ck(struct urtw_softc *); 519 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 520 int); 521 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 522 uint32_t *); 523 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 524 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 525 usbd_status urtw_get_macaddr(struct urtw_softc *); 526 usbd_status urtw_get_txpwr(struct urtw_softc *); 527 usbd_status urtw_get_rfchip(struct urtw_softc *); 528 usbd_status urtw_led_init(struct urtw_softc *); 529 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 530 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 531 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 532 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 533 uint32_t); 534 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 535 uint32_t); 536 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 537 usbd_status urtw_8225_usb_init(struct urtw_softc *); 538 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 539 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 540 uint16_t); 541 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 542 usbd_status urtw_8225_rf_init(struct urtw_rf *); 543 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 544 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 545 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 546 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 547 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 548 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 549 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 550 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 551 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 552 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 553 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 554 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 555 usbd_status urtw_open_pipes(struct urtw_softc *); 556 usbd_status urtw_close_pipes(struct urtw_softc *); 557 usbd_status urtw_intr_enable(struct urtw_softc *); 558 usbd_status urtw_intr_disable(struct urtw_softc *); 559 usbd_status urtw_reset(struct urtw_softc *); 560 usbd_status urtw_led_on(struct urtw_softc *, int); 561 usbd_status urtw_led_ctl(struct urtw_softc *, int); 562 usbd_status urtw_led_blink(struct urtw_softc *); 563 usbd_status urtw_led_mode0(struct urtw_softc *, int); 564 usbd_status urtw_led_mode1(struct urtw_softc *, int); 565 usbd_status urtw_led_mode2(struct urtw_softc *, int); 566 usbd_status urtw_led_mode3(struct urtw_softc *, int); 567 usbd_status urtw_rx_setconf(struct urtw_softc *); 568 usbd_status urtw_rx_enable(struct urtw_softc *); 569 usbd_status urtw_tx_enable(struct urtw_softc *); 570 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 571 usbd_status urtw_8187b_reset(struct urtw_softc *); 572 int urtw_8187b_init(struct ifnet *); 573 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 574 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 575 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 576 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 577 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 578 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 579 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 580 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 581 582 int urtw_match(device_t, cfdata_t, void *); 583 void urtw_attach(device_t, device_t, void *); 584 int urtw_detach(device_t, int); 585 int urtw_activate(device_t, enum devact); 586 587 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 588 urtw_match, 589 urtw_attach, 590 urtw_detach, 591 urtw_activate 592 ); 593 594 int 595 urtw_match(device_t parent, cfdata_t match, void *aux) 596 { 597 struct usb_attach_arg *uaa = aux; 598 599 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 600 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 601 } 602 603 void 604 urtw_attach(device_t parent, device_t self, void *aux) 605 { 606 struct urtw_softc *sc = device_private(self); 607 struct usb_attach_arg *uaa = aux; 608 struct ieee80211com *ic = &sc->sc_ic; 609 struct ifnet *ifp = &sc->sc_if; 610 usbd_status error; 611 uint8_t data8; 612 uint32_t data; 613 int i; 614 615 sc->sc_dev = self; 616 sc->sc_udev = uaa->device; 617 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 618 619 printf(": "); 620 621 if (sc->sc_hwrev & URTW_HWREV_8187) { 622 urtw_read32_m(sc, URTW_TX_CONF, &data); 623 data &= URTW_TX_HWREV_MASK; 624 switch (data) { 625 case URTW_TX_HWREV_8187_D: 626 sc->sc_hwrev |= URTW_HWREV_8187_D; 627 printf("RTL8187 rev D"); 628 break; 629 case URTW_TX_HWREV_8187B_D: 630 /* 631 * Detect Realtek RTL8187B devices that use 632 * USB IDs of RTL8187. 633 */ 634 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 635 printf("RTL8187B rev B (early)"); 636 break; 637 default: 638 sc->sc_hwrev |= URTW_HWREV_8187_B; 639 printf("RTL8187 rev 0x%02x", data >> 25); 640 break; 641 } 642 } else { 643 /* RTL8187B hwrev register. */ 644 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 645 switch (data8) { 646 case URTW_8187B_HWREV_8187B_B: 647 sc->sc_hwrev |= URTW_HWREV_8187B_B; 648 printf("RTL8187B rev B"); 649 break; 650 case URTW_8187B_HWREV_8187B_D: 651 sc->sc_hwrev |= URTW_HWREV_8187B_D; 652 printf("RTL8187B rev D"); 653 break; 654 case URTW_8187B_HWREV_8187B_E: 655 sc->sc_hwrev |= URTW_HWREV_8187B_E; 656 printf("RTL8187B rev E"); 657 break; 658 default: 659 sc->sc_hwrev |= URTW_HWREV_8187B_B; 660 printf("RTL8187B rev 0x%02x", data8); 661 break; 662 } 663 } 664 665 urtw_read32_m(sc, URTW_RX, &data); 666 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 667 URTW_EEPROM_93C46; 668 669 error = urtw_get_rfchip(sc); 670 if (error != 0) 671 goto fail; 672 error = urtw_get_macaddr(sc); 673 if (error != 0) 674 goto fail; 675 error = urtw_get_txpwr(sc); 676 if (error != 0) 677 goto fail; 678 error = urtw_led_init(sc); /* XXX incompleted */ 679 if (error != 0) 680 goto fail; 681 682 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 683 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 684 sc->sc_currate = 3; 685 /* XXX for what? */ 686 sc->sc_preamble_mode = 2; 687 688 usb_init_task(&sc->sc_task, urtw_task, sc); 689 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc); 690 callout_init(&sc->scan_to, 0); 691 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 692 callout_init(&sc->sc_led_ch, 0); 693 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 694 695 ic->ic_ifp = ifp; 696 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 697 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 698 ic->ic_state = IEEE80211_S_INIT; 699 700 /* set device capabilities */ 701 ic->ic_caps = 702 IEEE80211_C_MONITOR | /* monitor mode supported */ 703 IEEE80211_C_TXPMGT | /* tx power management */ 704 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 705 IEEE80211_C_SHSLOT | /* short slot time supported */ 706 IEEE80211_C_WEP | /* s/w WEP */ 707 IEEE80211_C_WPA; /* WPA/RSN */ 708 709 /* set supported .11b and .11g rates */ 710 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 711 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 712 713 /* set supported .11b and .11g channels (1 through 14) */ 714 for (i = 1; i <= 14; i++) { 715 ic->ic_channels[i].ic_freq = 716 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 717 ic->ic_channels[i].ic_flags = 718 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 719 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 720 } 721 722 ifp->if_softc = sc; 723 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 724 if (sc->sc_hwrev & URTW_HWREV_8187) { 725 ifp->if_init = urtw_init; 726 } else { 727 ifp->if_init = urtw_8187b_init; 728 } 729 ifp->if_ioctl = urtw_ioctl; 730 ifp->if_start = urtw_start; 731 ifp->if_watchdog = urtw_watchdog; 732 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 733 IFQ_SET_READY(&ifp->if_snd); 734 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 735 736 if_attach(ifp); 737 ieee80211_ifattach(ic); 738 739 /* override state transition machine */ 740 sc->sc_newstate = ic->ic_newstate; 741 ic->ic_newstate = urtw_newstate; 742 ieee80211_media_init(ic, urtw_media_change, ieee80211_media_status); 743 744 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 745 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 746 &sc->sc_drvbpf); 747 748 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 749 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 750 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 751 752 sc->sc_txtap_len = sizeof sc->sc_txtapu; 753 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 754 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 755 756 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 757 758 ieee80211_announce(ic); 759 760 return; 761 fail: 762 printf(": %s failed!\n", __func__); 763 sc->sc_dying = true; 764 } 765 766 int 767 urtw_detach(device_t self, int flags) 768 { 769 struct urtw_softc *sc = device_private(self); 770 struct ifnet *ifp = &sc->sc_if; 771 int s; 772 773 s = splusb(); 774 775 sc->sc_dying = true; 776 777 callout_destroy(&sc->scan_to); 778 callout_destroy(&sc->sc_led_ch); 779 780 usb_rem_task(sc->sc_udev, &sc->sc_task); 781 usb_rem_task(sc->sc_udev, &sc->sc_ledtask); 782 783 if (ifp->if_softc != NULL) { 784 bpf_detach(ifp); 785 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 786 if_detach(ifp); 787 } 788 789 /* abort and free xfers */ 790 urtw_free_tx_data_list(sc); 791 urtw_free_rx_data_list(sc); 792 urtw_close_pipes(sc); 793 794 splx(s); 795 796 return (0); 797 } 798 799 int 800 urtw_activate(device_t self, enum devact act) 801 { 802 struct urtw_softc *sc = device_private(self); 803 804 switch (act) { 805 case DVACT_DEACTIVATE: 806 sc->sc_dying = true; 807 break; 808 } 809 810 return (0); 811 } 812 813 usbd_status 814 urtw_close_pipes(struct urtw_softc *sc) 815 { 816 usbd_status error = 0; 817 818 if (sc->sc_rxpipe != NULL) { 819 error = usbd_close_pipe(sc->sc_rxpipe); 820 if (error != 0) 821 goto fail; 822 sc->sc_rxpipe = NULL; 823 } 824 if (sc->sc_txpipe_low != NULL) { 825 error = usbd_close_pipe(sc->sc_txpipe_low); 826 if (error != 0) 827 goto fail; 828 sc->sc_txpipe_low = NULL; 829 } 830 if (sc->sc_txpipe_normal != NULL) { 831 error = usbd_close_pipe(sc->sc_txpipe_normal); 832 if (error != 0) 833 goto fail; 834 sc->sc_txpipe_normal = NULL; 835 } 836 fail: 837 return (error); 838 } 839 840 usbd_status 841 urtw_open_pipes(struct urtw_softc *sc) 842 { 843 usbd_status error; 844 845 /* 846 * NB: there is no way to distinguish each pipes so we need to hardcode 847 * pipe numbers 848 */ 849 850 /* tx pipe - low priority packets */ 851 if (sc->sc_hwrev & URTW_HWREV_8187) 852 error = usbd_open_pipe(sc->sc_iface, 0x2, 853 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 854 else 855 error = usbd_open_pipe(sc->sc_iface, 0x6, 856 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 857 if (error != 0) { 858 printf("%s: could not open Tx low pipe: %s\n", 859 device_xname(sc->sc_dev), usbd_errstr(error)); 860 goto fail; 861 } 862 /* tx pipe - normal priority packets */ 863 if (sc->sc_hwrev & URTW_HWREV_8187) 864 error = usbd_open_pipe(sc->sc_iface, 0x3, 865 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 866 else 867 error = usbd_open_pipe(sc->sc_iface, 0x7, 868 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 869 if (error != 0) { 870 printf("%s: could not open Tx normal pipe: %s\n", 871 device_xname(sc->sc_dev), usbd_errstr(error)); 872 goto fail; 873 } 874 /* rx pipe */ 875 if (sc->sc_hwrev & URTW_HWREV_8187) 876 error = usbd_open_pipe(sc->sc_iface, 0x81, 877 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 878 else 879 error = usbd_open_pipe(sc->sc_iface, 0x83, 880 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 881 if (error != 0) { 882 printf("%s: could not open Rx pipe: %s\n", 883 device_xname(sc->sc_dev), usbd_errstr(error)); 884 goto fail; 885 } 886 887 return (0); 888 fail: 889 (void)urtw_close_pipes(sc); 890 return (error); 891 } 892 893 int 894 urtw_alloc_rx_data_list(struct urtw_softc *sc) 895 { 896 int i, error; 897 898 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 899 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 900 901 data->sc = sc; 902 903 data->xfer = usbd_alloc_xfer(sc->sc_udev); 904 if (data->xfer == NULL) { 905 printf("%s: could not allocate rx xfer\n", 906 device_xname(sc->sc_dev)); 907 error = ENOMEM; 908 goto fail; 909 } 910 911 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 912 printf("%s: could not allocate rx buffer\n", 913 device_xname(sc->sc_dev)); 914 error = ENOMEM; 915 goto fail; 916 } 917 918 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 919 if (data->m == NULL) { 920 printf("%s: could not allocate rx mbuf\n", 921 device_xname(sc->sc_dev)); 922 error = ENOMEM; 923 goto fail; 924 } 925 MCLGET(data->m, M_DONTWAIT); 926 if (!(data->m->m_flags & M_EXT)) { 927 printf("%s: could not allocate rx mbuf cluster\n", 928 device_xname(sc->sc_dev)); 929 error = ENOMEM; 930 goto fail; 931 } 932 data->buf = mtod(data->m, uint8_t *); 933 } 934 935 return (0); 936 937 fail: 938 urtw_free_rx_data_list(sc); 939 return (error); 940 } 941 942 void 943 urtw_free_rx_data_list(struct urtw_softc *sc) 944 { 945 int i; 946 947 /* Make sure no transfers are pending. */ 948 if (sc->sc_rxpipe != NULL) 949 usbd_abort_pipe(sc->sc_rxpipe); 950 951 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 952 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 953 954 if (data->xfer != NULL) { 955 usbd_free_xfer(data->xfer); 956 data->xfer = NULL; 957 } 958 if (data->m != NULL) { 959 m_freem(data->m); 960 data->m = NULL; 961 } 962 } 963 } 964 965 int 966 urtw_alloc_tx_data_list(struct urtw_softc *sc) 967 { 968 int i, error; 969 970 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 971 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 972 973 data->sc = sc; 974 data->ni = NULL; 975 976 data->xfer = usbd_alloc_xfer(sc->sc_udev); 977 if (data->xfer == NULL) { 978 printf("%s: could not allocate tx xfer\n", 979 device_xname(sc->sc_dev)); 980 error = ENOMEM; 981 goto fail; 982 } 983 984 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 985 if (data->buf == NULL) { 986 printf("%s: could not allocate tx buffer\n", 987 device_xname(sc->sc_dev)); 988 error = ENOMEM; 989 goto fail; 990 } 991 992 if (((unsigned long)data->buf) % 4) 993 printf("%s: warn: unaligned buffer %p\n", 994 device_xname(sc->sc_dev), data->buf); 995 } 996 997 return (0); 998 999 fail: 1000 urtw_free_tx_data_list(sc); 1001 return (error); 1002 } 1003 1004 void 1005 urtw_free_tx_data_list(struct urtw_softc *sc) 1006 { 1007 int i; 1008 1009 /* Make sure no transfers are pending. */ 1010 if (sc->sc_txpipe_low != NULL) 1011 usbd_abort_pipe(sc->sc_txpipe_low); 1012 if (sc->sc_txpipe_normal != NULL) 1013 usbd_abort_pipe(sc->sc_txpipe_normal); 1014 1015 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1016 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 1017 1018 if (data->xfer != NULL) { 1019 usbd_free_xfer(data->xfer); 1020 data->xfer = NULL; 1021 } 1022 if (data->ni != NULL) { 1023 ieee80211_free_node(data->ni); 1024 data->ni = NULL; 1025 } 1026 } 1027 } 1028 1029 int 1030 urtw_media_change(struct ifnet *ifp) 1031 { 1032 int error; 1033 1034 error = ieee80211_media_change(ifp); 1035 if (error != ENETRESET) 1036 return (error); 1037 1038 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1039 (IFF_UP | IFF_RUNNING)) 1040 ifp->if_init(ifp); 1041 1042 return (0); 1043 } 1044 1045 int 1046 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1047 { 1048 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1049 1050 usb_rem_task(sc->sc_udev, &sc->sc_task); 1051 callout_stop(&sc->scan_to); 1052 1053 /* do it in a process context */ 1054 sc->sc_state = nstate; 1055 sc->sc_arg = arg; 1056 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1057 1058 return (0); 1059 } 1060 1061 usbd_status 1062 urtw_led_init(struct urtw_softc *sc) 1063 { 1064 uint32_t rev; 1065 usbd_status error; 1066 1067 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1068 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1069 if (error != 0) 1070 goto fail; 1071 1072 switch (rev & URTW_EPROM_CID_MASK) { 1073 case URTW_EPROM_CID_ALPHA0: 1074 sc->sc_strategy = URTW_SW_LED_MODE1; 1075 break; 1076 case URTW_EPROM_CID_SERCOMM_PS: 1077 sc->sc_strategy = URTW_SW_LED_MODE3; 1078 break; 1079 case URTW_EPROM_CID_HW_LED: 1080 sc->sc_strategy = URTW_HW_LED; 1081 break; 1082 case URTW_EPROM_CID_RSVD0: 1083 case URTW_EPROM_CID_RSVD1: 1084 default: 1085 sc->sc_strategy = URTW_SW_LED_MODE0; 1086 break; 1087 } 1088 1089 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1090 1091 fail: 1092 return (error); 1093 } 1094 1095 usbd_status 1096 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1097 uint16_t data) 1098 { 1099 usb_device_request_t req; 1100 1101 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1102 req.bRequest = URTW_8187_SETREGS_REQ; 1103 USETW(req.wValue, addr); 1104 USETW(req.wIndex, index); 1105 USETW(req.wLength, sizeof(uint16_t)); 1106 1107 return (usbd_do_request(sc->sc_udev, &req, &data)); 1108 } 1109 1110 usbd_status 1111 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1112 { 1113 int i; 1114 int16_t bit; 1115 uint8_t rlen = 12, wlen = 6; 1116 uint16_t o1, o2, o3, tmp; 1117 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1118 uint32_t mask = 0x80000000, value = 0; 1119 usbd_status error; 1120 1121 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1122 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1123 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1124 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1125 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1126 o1 &= ~0xf; 1127 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1128 DELAY(5); 1129 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1130 DELAY(5); 1131 1132 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1133 bit = ((d2w & mask) != 0) ? 1 : 0; 1134 1135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1136 DELAY(2); 1137 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1138 URTW_BB_HOST_BANG_CLK); 1139 DELAY(2); 1140 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1141 URTW_BB_HOST_BANG_CLK); 1142 DELAY(2); 1143 mask = mask >> 1; 1144 if (i == 2) 1145 break; 1146 bit = ((d2w & mask) != 0) ? 1 : 0; 1147 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1148 URTW_BB_HOST_BANG_CLK); 1149 DELAY(2); 1150 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1151 URTW_BB_HOST_BANG_CLK); 1152 DELAY(2); 1153 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1154 DELAY(1); 1155 } 1156 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1157 URTW_BB_HOST_BANG_CLK); 1158 DELAY(2); 1159 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1160 DELAY(2); 1161 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1162 DELAY(2); 1163 1164 mask = 0x800; 1165 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1166 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1167 o1 | URTW_BB_HOST_BANG_RW); 1168 DELAY(2); 1169 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1170 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1171 DELAY(2); 1172 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1173 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1174 DELAY(2); 1175 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1176 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1177 DELAY(2); 1178 1179 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1180 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1181 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1182 o1 | URTW_BB_HOST_BANG_RW); 1183 DELAY(2); 1184 } 1185 1186 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1187 URTW_BB_HOST_BANG_RW); 1188 DELAY(2); 1189 1190 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1191 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1192 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1193 1194 if (data != NULL) 1195 *data = value; 1196 fail: 1197 return (error); 1198 } 1199 1200 usbd_status 1201 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1202 { 1203 uint16_t d80, d82, d84; 1204 usbd_status error; 1205 1206 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1207 d80 &= 0xfff3; 1208 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1209 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1210 d84 &= 0xfff0; 1211 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1212 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1213 DELAY(10); 1214 1215 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1216 DELAY(2); 1217 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1218 DELAY(10); 1219 1220 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1221 if (error != 0) 1222 goto fail; 1223 1224 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1225 DELAY(10); 1226 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1227 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1228 usbd_delay_ms(sc->sc_udev, 2); 1229 fail: 1230 return (error); 1231 } 1232 1233 usbd_status 1234 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1235 { 1236 uint32_t data; 1237 usbd_status error; 1238 1239 *ret = 1; 1240 1241 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1242 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1243 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1244 usbd_delay_ms(sc->sc_udev, 500); 1245 1246 urtw_8225_write(sc, 0x0, 0x1b7); 1247 1248 error = urtw_8225_read(sc, 0x8, &data); 1249 if (error != 0) 1250 goto fail; 1251 if (data != 0x588) 1252 *ret = 0; 1253 else { 1254 error = urtw_8225_read(sc, 0x9, &data); 1255 if (error != 0) 1256 goto fail; 1257 if (data != 0x700) 1258 *ret = 0; 1259 } 1260 1261 urtw_8225_write(sc, 0x0, 0xb7); 1262 fail: 1263 return (error); 1264 } 1265 1266 usbd_status 1267 urtw_get_rfchip(struct urtw_softc *sc) 1268 { 1269 struct urtw_rf *rf = &sc->sc_rf; 1270 int ret; 1271 uint32_t data; 1272 usbd_status error; 1273 1274 rf->rf_sc = sc; 1275 1276 if (sc->sc_hwrev & URTW_HWREV_8187) { 1277 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1278 if (error != 0) 1279 panic("unsupported RF chip"); 1280 /* NOTREACHED */ 1281 switch (data & 0xff) { 1282 case URTW_EPROM_RFCHIPID_RTL8225U: 1283 error = urtw_8225_isv2(sc, &ret); 1284 if (error != 0) 1285 goto fail; 1286 if (ret == 0) { 1287 rf->init = urtw_8225_rf_init; 1288 rf->set_chan = urtw_8225_rf_set_chan; 1289 rf->set_sens = urtw_8225_rf_set_sens; 1290 printf(", RFv1"); 1291 } else { 1292 rf->init = urtw_8225v2_rf_init; 1293 rf->set_chan = urtw_8225v2_rf_set_chan; 1294 rf->set_sens = NULL; 1295 printf(", RFv2"); 1296 } 1297 break; 1298 default: 1299 goto fail; 1300 } 1301 } else { 1302 rf->init = urtw_8225v2_b_rf_init; 1303 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1304 rf->set_sens = NULL; 1305 } 1306 1307 rf->max_sens = URTW_8225_RF_MAX_SENS; 1308 rf->sens = URTW_8225_RF_DEF_SENS; 1309 1310 return (0); 1311 1312 fail: 1313 panic("unsupported RF chip %d", data & 0xff); 1314 /* NOTREACHED */ 1315 } 1316 1317 usbd_status 1318 urtw_get_txpwr(struct urtw_softc *sc) 1319 { 1320 int i, j; 1321 uint32_t data; 1322 usbd_status error; 1323 1324 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1325 if (error != 0) 1326 goto fail; 1327 sc->sc_txpwr_cck_base = data & 0xf; 1328 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1329 1330 for (i = 1, j = 0; i < 6; i += 2, j++) { 1331 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1332 if (error != 0) 1333 goto fail; 1334 sc->sc_txpwr_cck[i] = data & 0xf; 1335 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1336 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1337 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1338 } 1339 for (i = 1, j = 0; i < 4; i += 2, j++) { 1340 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1341 if (error != 0) 1342 goto fail; 1343 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1344 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1345 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1346 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1347 } 1348 if (sc->sc_hwrev & URTW_HWREV_8187) { 1349 for (i = 1, j = 0; i < 4; i += 2, j++) { 1350 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1351 &data); 1352 if (error != 0) 1353 goto fail; 1354 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1355 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1356 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1357 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1358 (data & 0xf000) >> 12; 1359 } 1360 } else { 1361 /* Channel 11. */ 1362 error = urtw_eprom_read32(sc, 0x1b, &data); 1363 if (error != 0) 1364 goto fail; 1365 sc->sc_txpwr_cck[11] = data & 0xf; 1366 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1367 1368 /* Channel 12. */ 1369 error = urtw_eprom_read32(sc, 0xa, &data); 1370 if (error != 0) 1371 goto fail; 1372 sc->sc_txpwr_cck[12] = data & 0xf; 1373 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1374 1375 /* Channel 13, 14. */ 1376 error = urtw_eprom_read32(sc, 0x1c, &data); 1377 if (error != 0) 1378 goto fail; 1379 sc->sc_txpwr_cck[13] = data & 0xf; 1380 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1381 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1382 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1383 } 1384 fail: 1385 return (error); 1386 } 1387 1388 usbd_status 1389 urtw_get_macaddr(struct urtw_softc *sc) 1390 { 1391 struct ieee80211com *ic = &sc->sc_ic; 1392 usbd_status error; 1393 uint32_t data; 1394 1395 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1396 if (error != 0) 1397 goto fail; 1398 ic->ic_myaddr[0] = data & 0xff; 1399 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1400 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1401 if (error != 0) 1402 goto fail; 1403 ic->ic_myaddr[2] = data & 0xff; 1404 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1405 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1406 if (error != 0) 1407 goto fail; 1408 ic->ic_myaddr[4] = data & 0xff; 1409 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1410 fail: 1411 return (error); 1412 } 1413 1414 usbd_status 1415 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1416 { 1417 #define URTW_READCMD_LEN 3 1418 int addrlen, i; 1419 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1420 usbd_status error; 1421 1422 /* NB: make sure the buffer is initialized */ 1423 *data = 0; 1424 1425 /* enable EPROM programming */ 1426 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1427 DELAY(URTW_EPROM_DELAY); 1428 1429 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1430 if (error != 0) 1431 goto fail; 1432 error = urtw_eprom_ck(sc); 1433 if (error != 0) 1434 goto fail; 1435 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1436 if (error != 0) 1437 goto fail; 1438 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1439 addrlen = 8; 1440 addrstr[0] = addr & (1 << 7); 1441 addrstr[1] = addr & (1 << 6); 1442 addrstr[2] = addr & (1 << 5); 1443 addrstr[3] = addr & (1 << 4); 1444 addrstr[4] = addr & (1 << 3); 1445 addrstr[5] = addr & (1 << 2); 1446 addrstr[6] = addr & (1 << 1); 1447 addrstr[7] = addr & (1 << 0); 1448 } else { 1449 addrlen=6; 1450 addrstr[0] = addr & (1 << 5); 1451 addrstr[1] = addr & (1 << 4); 1452 addrstr[2] = addr & (1 << 3); 1453 addrstr[3] = addr & (1 << 2); 1454 addrstr[4] = addr & (1 << 1); 1455 addrstr[5] = addr & (1 << 0); 1456 } 1457 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1458 if (error != 0) 1459 goto fail; 1460 1461 error = urtw_eprom_writebit(sc, 0); 1462 if (error != 0) 1463 goto fail; 1464 1465 for (i = 0; i < 16; i++) { 1466 error = urtw_eprom_ck(sc); 1467 if (error != 0) 1468 goto fail; 1469 error = urtw_eprom_readbit(sc, &data16); 1470 if (error != 0) 1471 goto fail; 1472 1473 (*data) |= (data16 << (15 - i)); 1474 } 1475 1476 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1477 if (error != 0) 1478 goto fail; 1479 error = urtw_eprom_ck(sc); 1480 if (error != 0) 1481 goto fail; 1482 1483 /* now disable EPROM programming */ 1484 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1485 fail: 1486 return (error); 1487 #undef URTW_READCMD_LEN 1488 } 1489 1490 usbd_status 1491 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1492 { 1493 uint8_t data8; 1494 usbd_status error; 1495 1496 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1497 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1498 DELAY(URTW_EPROM_DELAY); 1499 1500 fail: 1501 return (error); 1502 } 1503 1504 usbd_status 1505 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1506 { 1507 int i = 0; 1508 usbd_status error = 0; 1509 1510 for (i = 0; i < buflen; i++) { 1511 error = urtw_eprom_writebit(sc, buf[i]); 1512 if (error != 0) 1513 goto fail; 1514 error = urtw_eprom_ck(sc); 1515 if (error != 0) 1516 goto fail; 1517 } 1518 fail: 1519 return (error); 1520 } 1521 1522 usbd_status 1523 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1524 { 1525 uint8_t data; 1526 usbd_status error; 1527 1528 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1529 if (bit != 0) 1530 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1531 else 1532 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1533 DELAY(URTW_EPROM_DELAY); 1534 fail: 1535 return (error); 1536 } 1537 1538 usbd_status 1539 urtw_eprom_ck(struct urtw_softc *sc) 1540 { 1541 uint8_t data; 1542 usbd_status error; 1543 1544 /* masking */ 1545 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1546 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1547 DELAY(URTW_EPROM_DELAY); 1548 /* unmasking */ 1549 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1550 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1551 DELAY(URTW_EPROM_DELAY); 1552 fail: 1553 return (error); 1554 } 1555 1556 usbd_status 1557 urtw_eprom_cs(struct urtw_softc *sc, int able) 1558 { 1559 uint8_t data; 1560 usbd_status error; 1561 1562 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1563 if (able == URTW_EPROM_ENABLE) 1564 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1565 else 1566 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1567 DELAY(URTW_EPROM_DELAY); 1568 fail: 1569 return (error); 1570 } 1571 1572 usbd_status 1573 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1574 { 1575 usb_device_request_t req; 1576 usbd_status error; 1577 1578 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1579 req.bRequest = URTW_8187_GETREGS_REQ; 1580 USETW(req.wValue, val | 0xff00); 1581 USETW(req.wIndex, idx & 0x03); 1582 USETW(req.wLength, sizeof(uint8_t)); 1583 1584 error = usbd_do_request(sc->sc_udev, &req, data); 1585 return (error); 1586 } 1587 1588 usbd_status 1589 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1590 { 1591 usb_device_request_t req; 1592 usbd_status error; 1593 1594 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1595 req.bRequest = URTW_8187_GETREGS_REQ; 1596 USETW(req.wValue, val | 0xfe00); 1597 USETW(req.wIndex, 0); 1598 USETW(req.wLength, sizeof(uint8_t)); 1599 1600 error = usbd_do_request(sc->sc_udev, &req, data); 1601 return (error); 1602 } 1603 1604 usbd_status 1605 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1606 { 1607 usb_device_request_t req; 1608 usbd_status error; 1609 1610 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1611 req.bRequest = URTW_8187_GETREGS_REQ; 1612 USETW(req.wValue, val | 0xff00); 1613 USETW(req.wIndex, idx & 0x03); 1614 USETW(req.wLength, sizeof(uint16_t)); 1615 1616 error = usbd_do_request(sc->sc_udev, &req, data); 1617 return (error); 1618 } 1619 1620 usbd_status 1621 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1622 { 1623 usb_device_request_t req; 1624 usbd_status error; 1625 1626 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1627 req.bRequest = URTW_8187_GETREGS_REQ; 1628 USETW(req.wValue, val | 0xff00); 1629 USETW(req.wIndex, idx & 0x03); 1630 USETW(req.wLength, sizeof(uint32_t)); 1631 1632 error = usbd_do_request(sc->sc_udev, &req, data); 1633 return (error); 1634 } 1635 1636 usbd_status 1637 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1638 { 1639 usb_device_request_t req; 1640 1641 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1642 req.bRequest = URTW_8187_SETREGS_REQ; 1643 USETW(req.wValue, val | 0xff00); 1644 USETW(req.wIndex, idx & 0x03); 1645 USETW(req.wLength, sizeof(uint8_t)); 1646 1647 return (usbd_do_request(sc->sc_udev, &req, &data)); 1648 } 1649 1650 usbd_status 1651 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1652 { 1653 usb_device_request_t req; 1654 1655 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1656 req.bRequest = URTW_8187_SETREGS_REQ; 1657 USETW(req.wValue, val | 0xfe00); 1658 USETW(req.wIndex, 0); 1659 USETW(req.wLength, sizeof(uint8_t)); 1660 1661 return (usbd_do_request(sc->sc_udev, &req, &data)); 1662 } 1663 1664 usbd_status 1665 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1666 { 1667 usb_device_request_t req; 1668 1669 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1670 req.bRequest = URTW_8187_SETREGS_REQ; 1671 USETW(req.wValue, val | 0xff00); 1672 USETW(req.wIndex, idx & 0x03); 1673 USETW(req.wLength, sizeof(uint16_t)); 1674 1675 return (usbd_do_request(sc->sc_udev, &req, &data)); 1676 } 1677 1678 usbd_status 1679 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1680 { 1681 usb_device_request_t req; 1682 1683 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1684 req.bRequest = URTW_8187_SETREGS_REQ; 1685 USETW(req.wValue, val | 0xff00); 1686 USETW(req.wIndex, idx & 0x03); 1687 USETW(req.wLength, sizeof(uint32_t)); 1688 1689 return (usbd_do_request(sc->sc_udev, &req, &data)); 1690 } 1691 1692 static usbd_status 1693 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1694 { 1695 uint8_t data; 1696 usbd_status error; 1697 1698 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1699 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1700 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1701 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1702 fail: 1703 return (error); 1704 } 1705 1706 usbd_status 1707 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1708 { 1709 uint8_t data; 1710 usbd_status error; 1711 1712 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1713 if (error) 1714 goto fail; 1715 1716 urtw_read8_m(sc, URTW_CONFIG3, &data); 1717 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1718 urtw_write32_m(sc, URTW_ANAPARAM, val); 1719 urtw_read8_m(sc, URTW_CONFIG3, &data); 1720 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1721 1722 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1723 if (error) 1724 goto fail; 1725 fail: 1726 return (error); 1727 } 1728 1729 usbd_status 1730 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1731 { 1732 uint8_t data; 1733 usbd_status error; 1734 1735 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1736 if (error) 1737 goto fail; 1738 1739 urtw_read8_m(sc, URTW_CONFIG3, &data); 1740 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1741 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1742 urtw_read8_m(sc, URTW_CONFIG3, &data); 1743 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1744 1745 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1746 if (error) 1747 goto fail; 1748 fail: 1749 return (error); 1750 } 1751 1752 usbd_status 1753 urtw_intr_disable(struct urtw_softc *sc) 1754 { 1755 usbd_status error; 1756 1757 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1758 1759 fail: 1760 return (error); 1761 } 1762 1763 usbd_status 1764 urtw_reset(struct urtw_softc *sc) 1765 { 1766 uint8_t data; 1767 usbd_status error; 1768 1769 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1770 if (error) 1771 goto fail; 1772 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1773 if (error) 1774 goto fail; 1775 1776 error = urtw_intr_disable(sc); 1777 if (error) 1778 goto fail; 1779 usbd_delay_ms(sc->sc_udev, 100); 1780 1781 error = urtw_write8e(sc, 0x18, 0x10); 1782 if (error != 0) 1783 goto fail; 1784 error = urtw_write8e(sc, 0x18, 0x11); 1785 if (error != 0) 1786 goto fail; 1787 error = urtw_write8e(sc, 0x18, 0x00); 1788 if (error != 0) 1789 goto fail; 1790 usbd_delay_ms(sc->sc_udev, 100); 1791 1792 urtw_read8_m(sc, URTW_CMD, &data); 1793 data = (data & 2) | URTW_CMD_RST; 1794 urtw_write8_m(sc, URTW_CMD, data); 1795 usbd_delay_ms(sc->sc_udev, 100); 1796 1797 urtw_read8_m(sc, URTW_CMD, &data); 1798 if (data & URTW_CMD_RST) { 1799 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1800 goto fail; 1801 } 1802 1803 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1804 if (error) 1805 goto fail; 1806 usbd_delay_ms(sc->sc_udev, 100); 1807 1808 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1809 if (error) 1810 goto fail; 1811 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1812 if (error) 1813 goto fail; 1814 fail: 1815 return (error); 1816 } 1817 1818 usbd_status 1819 urtw_led_on(struct urtw_softc *sc, int type) 1820 { 1821 usbd_status error; 1822 1823 if (type == URTW_LED_GPIO) { 1824 switch (sc->sc_gpio_ledpin) { 1825 case URTW_LED_PIN_GPIO0: 1826 urtw_write8_m(sc, URTW_GPIO, 0x01); 1827 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1828 break; 1829 default: 1830 panic("unsupported LED PIN type 0x%x", 1831 sc->sc_gpio_ledpin); 1832 /* NOTREACHED */ 1833 } 1834 } else { 1835 panic("unsupported LED type 0x%x", type); 1836 /* NOTREACHED */ 1837 } 1838 1839 sc->sc_gpio_ledon = 1; 1840 fail: 1841 return (error); 1842 } 1843 1844 static usbd_status 1845 urtw_led_off(struct urtw_softc *sc, int type) 1846 { 1847 usbd_status error; 1848 1849 if (type == URTW_LED_GPIO) { 1850 switch (sc->sc_gpio_ledpin) { 1851 case URTW_LED_PIN_GPIO0: 1852 urtw_write8_m(sc, URTW_GPIO, 0x01); 1853 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1854 break; 1855 default: 1856 panic("unsupported LED PIN type 0x%x", 1857 sc->sc_gpio_ledpin); 1858 /* NOTREACHED */ 1859 } 1860 } else { 1861 panic("unsupported LED type 0x%x", type); 1862 /* NOTREACHED */ 1863 } 1864 1865 sc->sc_gpio_ledon = 0; 1866 1867 fail: 1868 return (error); 1869 } 1870 1871 usbd_status 1872 urtw_led_mode0(struct urtw_softc *sc, int mode) 1873 { 1874 switch (mode) { 1875 case URTW_LED_CTL_POWER_ON: 1876 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1877 break; 1878 case URTW_LED_CTL_TX: 1879 if (sc->sc_gpio_ledinprogress == 1) 1880 return (0); 1881 1882 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1883 sc->sc_gpio_blinktime = 2; 1884 break; 1885 case URTW_LED_CTL_LINK: 1886 sc->sc_gpio_ledstate = URTW_LED_ON; 1887 break; 1888 default: 1889 panic("unsupported LED mode 0x%x", mode); 1890 /* NOTREACHED */ 1891 } 1892 1893 switch (sc->sc_gpio_ledstate) { 1894 case URTW_LED_ON: 1895 if (sc->sc_gpio_ledinprogress != 0) 1896 break; 1897 urtw_led_on(sc, URTW_LED_GPIO); 1898 break; 1899 case URTW_LED_BLINK_NORMAL: 1900 if (sc->sc_gpio_ledinprogress != 0) 1901 break; 1902 sc->sc_gpio_ledinprogress = 1; 1903 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1904 URTW_LED_OFF : URTW_LED_ON; 1905 if (!sc->sc_dying) 1906 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1907 break; 1908 case URTW_LED_POWER_ON_BLINK: 1909 urtw_led_on(sc, URTW_LED_GPIO); 1910 usbd_delay_ms(sc->sc_udev, 100); 1911 urtw_led_off(sc, URTW_LED_GPIO); 1912 break; 1913 default: 1914 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 1915 /* NOTREACHED */ 1916 } 1917 return (0); 1918 } 1919 1920 usbd_status 1921 urtw_led_mode1(struct urtw_softc *sc, int mode) 1922 { 1923 return (USBD_INVAL); 1924 } 1925 1926 usbd_status 1927 urtw_led_mode2(struct urtw_softc *sc, int mode) 1928 { 1929 return (USBD_INVAL); 1930 } 1931 1932 usbd_status 1933 urtw_led_mode3(struct urtw_softc *sc, int mode) 1934 { 1935 return (USBD_INVAL); 1936 } 1937 1938 void 1939 urtw_ledusbtask(void *arg) 1940 { 1941 struct urtw_softc *sc = arg; 1942 1943 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1944 panic("could not process a LED strategy 0x%x", sc->sc_strategy); 1945 1946 urtw_led_blink(sc); 1947 } 1948 1949 void 1950 urtw_ledtask(void *arg) 1951 { 1952 struct urtw_softc *sc = arg; 1953 1954 /* 1955 * NB: to change a status of the led we need at least a sleep so we 1956 * can't do it here 1957 */ 1958 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1959 } 1960 1961 usbd_status 1962 urtw_led_ctl(struct urtw_softc *sc, int mode) 1963 { 1964 usbd_status error = 0; 1965 1966 switch (sc->sc_strategy) { 1967 case URTW_SW_LED_MODE0: 1968 error = urtw_led_mode0(sc, mode); 1969 break; 1970 case URTW_SW_LED_MODE1: 1971 error = urtw_led_mode1(sc, mode); 1972 break; 1973 case URTW_SW_LED_MODE2: 1974 error = urtw_led_mode2(sc, mode); 1975 break; 1976 case URTW_SW_LED_MODE3: 1977 error = urtw_led_mode3(sc, mode); 1978 break; 1979 default: 1980 panic("unsupported LED mode %d", sc->sc_strategy); 1981 /* NOTREACHED */ 1982 } 1983 1984 return (error); 1985 } 1986 1987 usbd_status 1988 urtw_led_blink(struct urtw_softc *sc) 1989 { 1990 uint8_t ing = 0; 1991 usbd_status error; 1992 1993 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1994 error = urtw_led_on(sc, URTW_LED_GPIO); 1995 else 1996 error = urtw_led_off(sc, URTW_LED_GPIO); 1997 sc->sc_gpio_blinktime--; 1998 if (sc->sc_gpio_blinktime == 0) 1999 ing = 1; 2000 else { 2001 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 2002 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 2003 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 2004 ing = 1; 2005 } 2006 if (ing == 1) { 2007 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2008 sc->sc_gpio_ledon == 0) 2009 error = urtw_led_on(sc, URTW_LED_GPIO); 2010 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2011 sc->sc_gpio_ledon == 1) 2012 error = urtw_led_off(sc, URTW_LED_GPIO); 2013 2014 sc->sc_gpio_blinktime = 0; 2015 sc->sc_gpio_ledinprogress = 0; 2016 return (0); 2017 } 2018 2019 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2020 URTW_LED_ON : URTW_LED_OFF; 2021 2022 switch (sc->sc_gpio_ledstate) { 2023 case URTW_LED_BLINK_NORMAL: 2024 if (!sc->sc_dying) 2025 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2026 break; 2027 default: 2028 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 2029 /* NOTREACHED */ 2030 } 2031 return (0); 2032 } 2033 2034 usbd_status 2035 urtw_update_msr(struct urtw_softc *sc) 2036 { 2037 struct ieee80211com *ic = &sc->sc_ic; 2038 uint8_t data; 2039 usbd_status error; 2040 2041 urtw_read8_m(sc, URTW_MSR, &data); 2042 data &= ~URTW_MSR_LINK_MASK; 2043 2044 /* Should always be set. */ 2045 if (sc->sc_hwrev & URTW_HWREV_8187B) 2046 data |= URTW_MSR_LINK_ENEDCA; 2047 2048 if (sc->sc_state == IEEE80211_S_RUN) { 2049 switch (ic->ic_opmode) { 2050 case IEEE80211_M_STA: 2051 case IEEE80211_M_MONITOR: 2052 data |= URTW_MSR_LINK_STA; 2053 break; 2054 default: 2055 panic("unsupported operation mode 0x%x", 2056 ic->ic_opmode); 2057 /* NOTREACHED */ 2058 } 2059 } else 2060 data |= URTW_MSR_LINK_NONE; 2061 2062 urtw_write8_m(sc, URTW_MSR, data); 2063 fail: 2064 return (error); 2065 } 2066 2067 uint16_t 2068 urtw_rate2rtl(int rate) 2069 { 2070 unsigned int i; 2071 2072 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2073 if (rate == urtw_ratetable[i].reg) 2074 return (urtw_ratetable[i].val); 2075 } 2076 2077 return (3); 2078 } 2079 2080 uint16_t 2081 urtw_rtl2rate(int rate) 2082 { 2083 unsigned int i; 2084 2085 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2086 if (rate == urtw_ratetable[i].val) 2087 return (urtw_ratetable[i].reg); 2088 } 2089 2090 return (0); 2091 } 2092 2093 usbd_status 2094 urtw_set_rate(struct urtw_softc *sc) 2095 { 2096 int i, basic_rate, min_rr_rate, max_rr_rate; 2097 uint16_t data; 2098 usbd_status error; 2099 2100 basic_rate = urtw_rate2rtl(48); 2101 min_rr_rate = urtw_rate2rtl(12); 2102 max_rr_rate = urtw_rate2rtl(48); 2103 2104 urtw_write8_m(sc, URTW_RESP_RATE, 2105 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2106 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2107 2108 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2109 data &= ~URTW_BRSR_MBR_8185; 2110 2111 for (i = 0; i <= basic_rate; i++) 2112 data |= (1 << i); 2113 2114 urtw_write16_m(sc, URTW_8187_BRSR, data); 2115 fail: 2116 return (error); 2117 } 2118 2119 usbd_status 2120 urtw_intr_enable(struct urtw_softc *sc) 2121 { 2122 usbd_status error; 2123 2124 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2125 fail: 2126 return (error); 2127 } 2128 2129 usbd_status 2130 urtw_rx_setconf(struct urtw_softc *sc) 2131 { 2132 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2133 struct ieee80211com *ic = &sc->sc_ic; 2134 uint32_t data; 2135 usbd_status error; 2136 2137 urtw_read32_m(sc, URTW_RX, &data); 2138 data = data &~ URTW_RX_FILTER_MASK; 2139 #if 0 2140 data = data | URTW_RX_FILTER_CTL; 2141 #endif 2142 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2143 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2144 2145 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2146 data = data | URTW_RX_FILTER_ICVERR; 2147 data = data | URTW_RX_FILTER_PWR; 2148 } 2149 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2150 data = data | URTW_RX_FILTER_CRCERR; 2151 2152 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2153 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2154 data = data | URTW_RX_FILTER_ALLMAC; 2155 } else { 2156 data = data | URTW_RX_FILTER_NICMAC; 2157 data = data | URTW_RX_CHECK_BSSID; 2158 } 2159 2160 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2161 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2162 data = data &~ URTW_MAX_RX_DMA_MASK; 2163 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2164 2165 urtw_write32_m(sc, URTW_RX, data); 2166 fail: 2167 return (error); 2168 } 2169 2170 usbd_status 2171 urtw_rx_enable(struct urtw_softc *sc) 2172 { 2173 int i; 2174 struct urtw_rx_data *rx_data; 2175 uint8_t data; 2176 usbd_status error; 2177 2178 /* 2179 * Start up the receive pipe. 2180 */ 2181 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2182 rx_data = &sc->sc_rx_data[i]; 2183 2184 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2185 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2186 USBD_NO_TIMEOUT, urtw_rxeof); 2187 error = usbd_transfer(rx_data->xfer); 2188 if (error != USBD_IN_PROGRESS && error != 0) { 2189 printf("%s: could not queue Rx transfer\n", 2190 device_xname(sc->sc_dev)); 2191 goto fail; 2192 } 2193 } 2194 2195 error = urtw_rx_setconf(sc); 2196 if (error != 0) 2197 goto fail; 2198 2199 urtw_read8_m(sc, URTW_CMD, &data); 2200 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2201 fail: 2202 return (error); 2203 } 2204 2205 usbd_status 2206 urtw_tx_enable(struct urtw_softc *sc) 2207 { 2208 uint8_t data8; 2209 uint32_t data; 2210 usbd_status error; 2211 2212 if (sc->sc_hwrev & URTW_HWREV_8187) { 2213 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2214 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2215 URTW_CW_CONF_PERPACKET_RETRY); 2216 urtw_write8_m(sc, URTW_CW_CONF, data8); 2217 2218 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2219 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2220 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2221 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2222 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2223 2224 urtw_read32_m(sc, URTW_TX_CONF, &data); 2225 data &= ~URTW_TX_LOOPBACK_MASK; 2226 data |= URTW_TX_LOOPBACK_NONE; 2227 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2228 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2229 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2230 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2231 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2232 data &= ~URTW_TX_SWPLCPLEN; 2233 data |= URTW_TX_NOICV; 2234 urtw_write32_m(sc, URTW_TX_CONF, data); 2235 } else { 2236 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2237 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2238 URTW_TX_LONGRETRY; 2239 urtw_write32_m(sc, URTW_TX_CONF, data); 2240 } 2241 2242 urtw_read8_m(sc, URTW_CMD, &data8); 2243 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2244 fail: 2245 return (error); 2246 } 2247 2248 int 2249 urtw_init(struct ifnet *ifp) 2250 { 2251 struct urtw_softc *sc = ifp->if_softc; 2252 struct urtw_rf *rf = &sc->sc_rf; 2253 struct ieee80211com *ic = &sc->sc_ic; 2254 usbd_status error; 2255 int ret; 2256 2257 urtw_stop(ifp, 0); 2258 2259 error = urtw_reset(sc); 2260 if (error) 2261 goto fail; 2262 2263 urtw_write8_m(sc, 0x85, 0); 2264 urtw_write8_m(sc, URTW_GPIO, 0); 2265 2266 /* for led */ 2267 urtw_write8_m(sc, 0x85, 4); 2268 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2269 if (error != 0) 2270 goto fail; 2271 2272 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2273 if (error) 2274 goto fail; 2275 2276 /* applying MAC address again. */ 2277 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2278 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2279 if (error) 2280 goto fail; 2281 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2282 if (error) 2283 goto fail; 2284 2285 error = urtw_update_msr(sc); 2286 if (error) 2287 goto fail; 2288 2289 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2290 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2291 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2292 error = urtw_set_rate(sc); 2293 if (error != 0) 2294 goto fail; 2295 2296 error = rf->init(rf); 2297 if (error != 0) 2298 goto fail; 2299 if (rf->set_sens != NULL) 2300 rf->set_sens(rf); 2301 2302 urtw_write16_m(sc, 0x5e, 1); 2303 urtw_write16_m(sc, 0xfe, 0x10); 2304 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2305 urtw_write8_m(sc, 0xff, 0x60); 2306 urtw_write16_m(sc, 0x5e, 0); 2307 urtw_write8_m(sc, 0x85, 4); 2308 2309 error = urtw_intr_enable(sc); 2310 if (error != 0) 2311 goto fail; 2312 2313 /* reset softc variables */ 2314 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2315 sc->sc_txtimer = 0; 2316 2317 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2318 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2319 if (error != 0) { 2320 printf("%s: could not set configuration no\n", 2321 device_xname(sc->sc_dev)); 2322 goto fail; 2323 } 2324 /* get the first interface handle */ 2325 error = usbd_device2interface_handle(sc->sc_udev, 2326 URTW_IFACE_INDEX, &sc->sc_iface); 2327 if (error != 0) { 2328 printf("%s: could not get interface handle\n", 2329 device_xname(sc->sc_dev)); 2330 goto fail; 2331 } 2332 error = urtw_open_pipes(sc); 2333 if (error != 0) 2334 goto fail; 2335 ret = urtw_alloc_rx_data_list(sc); 2336 if (error != 0) 2337 goto fail; 2338 ret = urtw_alloc_tx_data_list(sc); 2339 if (error != 0) 2340 goto fail; 2341 sc->sc_flags |= URTW_INIT_ONCE; 2342 } 2343 2344 error = urtw_rx_enable(sc); 2345 if (error != 0) 2346 goto fail; 2347 error = urtw_tx_enable(sc); 2348 if (error != 0) 2349 goto fail; 2350 2351 ifp->if_flags &= ~IFF_OACTIVE; 2352 ifp->if_flags |= IFF_RUNNING; 2353 2354 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2355 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2356 else 2357 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2358 2359 return (0); 2360 fail: 2361 return (error); 2362 } 2363 2364 int 2365 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2366 { 2367 #define IS_RUNNING(ifp) \ 2368 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2369 2370 struct urtw_softc *sc = ifp->if_softc; 2371 struct ieee80211com *ic = &sc->sc_ic; 2372 int s, error = 0; 2373 2374 if (sc->sc_dying) 2375 return (ENXIO); 2376 2377 s = splnet(); 2378 2379 switch (cmd) { 2380 case SIOCSIFFLAGS: 2381 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2382 break; 2383 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2384 case IFF_UP|IFF_RUNNING: 2385 break; 2386 case IFF_UP: 2387 ifp->if_init(ifp); 2388 break; 2389 case IFF_RUNNING: 2390 urtw_stop(ifp, 1); 2391 break; 2392 case 0: 2393 break; 2394 } 2395 break; 2396 2397 case SIOCADDMULTI: 2398 case SIOCDELMULTI: 2399 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2400 error = 0; 2401 break; 2402 2403 default: 2404 error = ieee80211_ioctl(ic, cmd, data); 2405 break; 2406 } 2407 2408 if (error == ENETRESET) { 2409 if (IS_RUNNING(ifp) && 2410 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2411 ifp->if_init(ifp); 2412 error = 0; 2413 } 2414 2415 splx(s); 2416 2417 return (error); 2418 #undef IS_RUNNING 2419 } 2420 2421 void 2422 urtw_start(struct ifnet *ifp) 2423 { 2424 struct urtw_softc *sc = ifp->if_softc; 2425 struct ieee80211com *ic = &sc->sc_ic; 2426 struct ieee80211_node *ni; 2427 struct ether_header *eh; 2428 struct mbuf *m0; 2429 2430 /* 2431 * net80211 may still try to send management frames even if the 2432 * IFF_RUNNING flag is not set... 2433 */ 2434 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2435 return; 2436 2437 for (;;) { 2438 IF_POLL(&ic->ic_mgtq, m0); 2439 if (m0 != NULL) { 2440 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2441 sc->sc_tx_normal_queued >= 2442 URTW_TX_DATA_LIST_COUNT) { 2443 ifp->if_flags |= IFF_OACTIVE; 2444 break; 2445 } 2446 IF_DEQUEUE(&ic->ic_mgtq, m0); 2447 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2448 m0->m_pkthdr.rcvif = NULL; 2449 bpf_mtap3(ic->ic_rawbpf, m0); 2450 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2451 != 0) 2452 break; 2453 } else { 2454 if (ic->ic_state != IEEE80211_S_RUN) 2455 break; 2456 IFQ_POLL(&ifp->if_snd, m0); 2457 if (m0 == NULL) 2458 break; 2459 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2460 sc->sc_tx_normal_queued >= 2461 URTW_TX_DATA_LIST_COUNT) { 2462 ifp->if_flags |= IFF_OACTIVE; 2463 break; 2464 } 2465 IFQ_DEQUEUE(&ifp->if_snd, m0); 2466 if (m0->m_len < sizeof(struct ether_header) && 2467 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2468 continue; 2469 2470 eh = mtod(m0, struct ether_header *); 2471 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2472 if (ni == NULL) { 2473 m_freem(m0); 2474 continue; 2475 } 2476 bpf_mtap(ifp, m0); 2477 m0 = ieee80211_encap(ic, m0, ni); 2478 if (m0 == NULL) { 2479 ieee80211_free_node(ni); 2480 continue; 2481 } 2482 bpf_mtap3(ic->ic_rawbpf, m0); 2483 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2484 != 0) { 2485 ieee80211_free_node(ni); 2486 ifp->if_oerrors++; 2487 break; 2488 } 2489 } 2490 sc->sc_txtimer = 5; 2491 ifp->if_timer = 1; 2492 } 2493 } 2494 2495 void 2496 urtw_watchdog(struct ifnet *ifp) 2497 { 2498 struct urtw_softc *sc = ifp->if_softc; 2499 2500 ifp->if_timer = 0; 2501 2502 if (sc->sc_txtimer > 0) { 2503 if (--sc->sc_txtimer == 0) { 2504 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2505 ifp->if_oerrors++; 2506 return; 2507 } 2508 ifp->if_timer = 1; 2509 } 2510 2511 ieee80211_watchdog(&sc->sc_ic); 2512 } 2513 2514 void 2515 urtw_txeof_low(usbd_xfer_handle xfer, usbd_private_handle priv, 2516 usbd_status status) 2517 { 2518 struct urtw_tx_data *data = priv; 2519 struct urtw_softc *sc = data->sc; 2520 struct ieee80211com *ic = &sc->sc_ic; 2521 struct ifnet *ifp = ic->ic_ifp; 2522 int s; 2523 2524 if (status != USBD_NORMAL_COMPLETION) { 2525 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2526 return; 2527 2528 printf("%s: could not transmit buffer: %s\n", 2529 device_xname(sc->sc_dev), usbd_errstr(status)); 2530 2531 if (status == USBD_STALLED) 2532 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2533 2534 ifp->if_oerrors++; 2535 return; 2536 } 2537 2538 s = splnet(); 2539 2540 ieee80211_free_node(data->ni); 2541 data->ni = NULL; 2542 2543 sc->sc_txtimer = 0; 2544 ifp->if_opackets++; 2545 2546 sc->sc_tx_low_queued--; 2547 ifp->if_flags &= ~IFF_OACTIVE; 2548 urtw_start(ifp); 2549 2550 splx(s); 2551 } 2552 2553 void 2554 urtw_txeof_normal(usbd_xfer_handle xfer, usbd_private_handle priv, 2555 usbd_status status) 2556 { 2557 struct urtw_tx_data *data = priv; 2558 struct urtw_softc *sc = data->sc; 2559 struct ieee80211com *ic = &sc->sc_ic; 2560 struct ifnet *ifp = ic->ic_ifp; 2561 int s; 2562 2563 if (status != USBD_NORMAL_COMPLETION) { 2564 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2565 return; 2566 2567 printf("%s: could not transmit buffer: %s\n", 2568 device_xname(sc->sc_dev), usbd_errstr(status)); 2569 2570 if (status == USBD_STALLED) 2571 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2572 2573 ifp->if_oerrors++; 2574 return; 2575 } 2576 2577 s = splnet(); 2578 2579 ieee80211_free_node(data->ni); 2580 data->ni = NULL; 2581 2582 sc->sc_txtimer = 0; 2583 ifp->if_opackets++; 2584 2585 sc->sc_tx_normal_queued--; 2586 ifp->if_flags &= ~IFF_OACTIVE; 2587 urtw_start(ifp); 2588 2589 splx(s); 2590 } 2591 2592 int 2593 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2594 int prior) 2595 { 2596 struct ieee80211com *ic = &sc->sc_ic; 2597 struct urtw_tx_data *data; 2598 struct ieee80211_frame *wh; 2599 struct ieee80211_key *k; 2600 usbd_status error; 2601 int xferlen; 2602 2603 wh = mtod(m0, struct ieee80211_frame *); 2604 2605 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2606 k = ieee80211_crypto_encap(ic, ni, m0); 2607 if (k == NULL) { 2608 m_freem(m0); 2609 return (ENOBUFS); 2610 } 2611 /* packet header may have moved, reset our local pointer */ 2612 wh = mtod(m0, struct ieee80211_frame *); 2613 } 2614 2615 if (sc->sc_drvbpf != NULL) { 2616 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2617 2618 tap->wt_flags = 0; 2619 tap->wt_rate = 0; 2620 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2621 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2622 2623 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 2624 } 2625 2626 if (sc->sc_hwrev & URTW_HWREV_8187) 2627 xferlen = m0->m_pkthdr.len + 4 * 3; 2628 else 2629 xferlen = m0->m_pkthdr.len + 4 * 8; 2630 2631 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2632 xferlen += 1; 2633 2634 data = &sc->sc_tx_data[sc->sc_txidx]; 2635 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2636 2637 bzero(data->buf, URTW_TX_MAXSIZE); 2638 data->buf[0] = m0->m_pkthdr.len & 0xff; 2639 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2640 data->buf[1] |= (1 << 7); 2641 2642 /* XXX sc_preamble_mode is always 2. */ 2643 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2644 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2645 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2646 data->buf[2] |= 1; 2647 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2648 prior == URTW_PRIORITY_LOW) 2649 panic("TODO tx."); 2650 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2651 data->buf[2] |= (1 << 1); 2652 /* RTS rate - 10 means we use a basic rate. */ 2653 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2654 /* 2655 * XXX currently TX rate control depends on the rate value of 2656 * RX descriptor because I don't know how to we can control TX rate 2657 * in more smart way. Please fix me you find a thing. 2658 */ 2659 data->buf[3] = sc->sc_currate; 2660 if (prior == URTW_PRIORITY_NORMAL) { 2661 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2662 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2663 else if (ic->ic_fixed_rate != -1) 2664 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2665 } 2666 2667 if (sc->sc_hwrev & URTW_HWREV_8187) { 2668 data->buf[8] = 3; /* CW minimum */ 2669 data->buf[8] |= (7 << 4); /* CW maximum */ 2670 data->buf[9] |= 11; /* retry limitation */ 2671 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2672 } else { 2673 data->buf[21] |= 11; /* retry limitation */ 2674 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2675 } 2676 2677 data->ni = ni; 2678 2679 /* mbuf is no longer needed. */ 2680 m_freem(m0); 2681 2682 usbd_setup_xfer(data->xfer, 2683 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2684 sc->sc_txpipe_normal, data, data->buf, xferlen, 2685 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2686 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2687 error = usbd_transfer(data->xfer); 2688 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2689 printf("%s: could not send frame: %s\n", 2690 device_xname(sc->sc_dev), usbd_errstr(error)); 2691 return (EIO); 2692 } 2693 2694 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2695 if (error != 0) 2696 printf("%s: could not control LED (%d)\n", 2697 device_xname(sc->sc_dev), error); 2698 2699 if (prior == URTW_PRIORITY_LOW) 2700 sc->sc_tx_low_queued++; 2701 else 2702 sc->sc_tx_normal_queued++; 2703 2704 return (0); 2705 } 2706 2707 usbd_status 2708 urtw_8225_usb_init(struct urtw_softc *sc) 2709 { 2710 uint8_t data; 2711 usbd_status error; 2712 2713 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2714 urtw_write8_m(sc, URTW_GPIO, 0); 2715 error = urtw_read8e(sc, 0x53, &data); 2716 if (error) 2717 goto fail; 2718 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2719 if (error) 2720 goto fail; 2721 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2722 urtw_write8_m(sc, URTW_GPIO, 0x20); 2723 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2724 2725 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2726 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2727 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2728 2729 usbd_delay_ms(sc->sc_udev, 500); 2730 fail: 2731 return (error); 2732 } 2733 2734 usbd_status 2735 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2736 { 2737 usbd_status error = 0; 2738 2739 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2740 fail: 2741 return (error); 2742 } 2743 2744 usbd_status 2745 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2746 { 2747 uint32_t phyw; 2748 usbd_status error; 2749 2750 phyw = ((data << 8) | (addr | 0x80)); 2751 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2752 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2753 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2754 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2755 /* 2756 * Delay removed from 8185 to 8187. 2757 * usbd_delay_ms(sc->sc_udev, 1); 2758 */ 2759 fail: 2760 return (error); 2761 } 2762 2763 usbd_status 2764 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2765 { 2766 data = data & 0xff; 2767 return (urtw_8187_write_phy(sc, addr, data)); 2768 } 2769 2770 usbd_status 2771 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2772 { 2773 data = data & 0xff; 2774 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2775 } 2776 2777 usbd_status 2778 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2779 { 2780 usbd_status error; 2781 2782 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2783 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2784 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2785 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2786 fail: 2787 return (error); 2788 } 2789 2790 usbd_status 2791 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2792 { 2793 int i, idx, set; 2794 uint8_t *cck_pwltable; 2795 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2796 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2797 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2798 usbd_status error; 2799 2800 cck_pwrlvl_max = 11; 2801 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2802 ofdm_pwrlvl_min = 10; 2803 2804 /* CCK power setting */ 2805 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2806 idx = cck_pwrlvl % 6; 2807 set = cck_pwrlvl / 6; 2808 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2809 urtw_8225_txpwr_cck; 2810 2811 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2812 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2813 for (i = 0; i < 8; i++) { 2814 urtw_8187_write_phy_cck(sc, 0x44 + i, 2815 cck_pwltable[idx * 8 + i]); 2816 } 2817 usbd_delay_ms(sc->sc_udev, 1); 2818 2819 /* OFDM power setting */ 2820 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2821 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2822 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2823 2824 idx = ofdm_pwrlvl % 6; 2825 set = ofdm_pwrlvl / 6; 2826 2827 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2828 if (error) 2829 goto fail; 2830 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2831 urtw_8187_write_phy_ofdm(sc, 6, 0); 2832 urtw_8187_write_phy_ofdm(sc, 8, 0); 2833 2834 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2835 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2836 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2837 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2838 usbd_delay_ms(sc->sc_udev, 1); 2839 fail: 2840 return (error); 2841 } 2842 2843 usbd_status 2844 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2845 { 2846 usbd_status error; 2847 2848 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2849 usbd_delay_ms(sc->sc_udev, 1); 2850 fail: 2851 return (error); 2852 } 2853 2854 usbd_status 2855 urtw_8225_rf_init(struct urtw_rf *rf) 2856 { 2857 struct urtw_softc *sc = rf->rf_sc; 2858 unsigned int i; 2859 uint16_t data; 2860 usbd_status error; 2861 2862 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2863 if (error) 2864 goto fail; 2865 2866 error = urtw_8225_usb_init(sc); 2867 if (error) 2868 goto fail; 2869 2870 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2871 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2872 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2873 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2874 2875 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2876 if (error) 2877 goto fail; 2878 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2879 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2880 if (error) 2881 goto fail; 2882 2883 error = urtw_8185_rf_pins_enable(sc); 2884 if (error) 2885 goto fail; 2886 2887 usbd_delay_ms(sc->sc_udev, 500); 2888 2889 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2890 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2891 urtw_8225_rf_part1[i].val); 2892 } 2893 usbd_delay_ms(sc->sc_udev, 50); 2894 urtw_8225_write(sc, 0x2, 0xc4d); 2895 usbd_delay_ms(sc->sc_udev, 200); 2896 urtw_8225_write(sc, 0x2, 0x44d); 2897 usbd_delay_ms(sc->sc_udev, 200); 2898 urtw_8225_write(sc, 0x0, 0x127); 2899 2900 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2901 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2902 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2903 } 2904 2905 urtw_8225_write(sc, 0x0, 0x27); 2906 urtw_8225_write(sc, 0x0, 0x22f); 2907 2908 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2909 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2910 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2911 } 2912 2913 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2914 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2915 urtw_8225_rf_part2[i].val); 2916 usbd_delay_ms(sc->sc_udev, 1); 2917 } 2918 2919 error = urtw_8225_setgain(sc, 4); 2920 if (error) 2921 goto fail; 2922 2923 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2924 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2925 urtw_8225_rf_part3[i].val); 2926 usbd_delay_ms(sc->sc_udev, 1); 2927 } 2928 2929 urtw_write8_m(sc, 0x5b, 0x0d); 2930 2931 error = urtw_8225_set_txpwrlvl(sc, 1); 2932 if (error) 2933 goto fail; 2934 2935 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2936 usbd_delay_ms(sc->sc_udev, 1); 2937 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2938 usbd_delay_ms(sc->sc_udev, 1); 2939 2940 /* TX ant A, 0x0 for B */ 2941 error = urtw_8185_tx_antenna(sc, 0x3); 2942 if (error) 2943 goto fail; 2944 urtw_write32_m(sc, 0x94, 0x3dc00002); 2945 2946 error = urtw_8225_rf_set_chan(rf, 1); 2947 fail: 2948 return (error); 2949 } 2950 2951 usbd_status 2952 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2953 { 2954 struct urtw_softc *sc = rf->rf_sc; 2955 struct ieee80211com *ic = &sc->sc_ic; 2956 struct ieee80211_channel *c = ic->ic_ibss_chan; 2957 usbd_status error; 2958 2959 error = urtw_8225_set_txpwrlvl(sc, chan); 2960 if (error) 2961 goto fail; 2962 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2963 usbd_delay_ms(sc->sc_udev, 10); 2964 2965 urtw_write8_m(sc, URTW_SIFS, 0x22); 2966 2967 if (sc->sc_state == IEEE80211_S_ASSOC && 2968 ic->ic_flags & IEEE80211_F_SHSLOT) 2969 urtw_write8_m(sc, URTW_SLOT, 0x9); 2970 else 2971 urtw_write8_m(sc, URTW_SLOT, 0x14); 2972 2973 if (IEEE80211_IS_CHAN_G(c)) { 2974 urtw_write8_m(sc, URTW_DIFS, 0x14); 2975 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2976 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2977 } else { 2978 urtw_write8_m(sc, URTW_DIFS, 0x24); 2979 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2980 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2981 } 2982 2983 fail: 2984 return (error); 2985 } 2986 2987 usbd_status 2988 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2989 { 2990 struct urtw_softc *sc = rf->rf_sc; 2991 usbd_status error; 2992 2993 if (rf->sens > 6) 2994 return (-1); 2995 2996 if (rf->sens > 4) 2997 urtw_8225_write(sc, 0x0c, 0x850); 2998 else 2999 urtw_8225_write(sc, 0x0c, 0x50); 3000 3001 rf->sens = 6 - rf->sens; 3002 error = urtw_8225_setgain(sc, rf->sens); 3003 if (error) 3004 goto fail; 3005 3006 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3007 3008 fail: 3009 return (error); 3010 } 3011 3012 void 3013 urtw_stop(struct ifnet *ifp, int disable) 3014 { 3015 struct urtw_softc *sc = ifp->if_softc; 3016 struct ieee80211com *ic = &sc->sc_ic; 3017 uint8_t data; 3018 usbd_status error; 3019 3020 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3021 3022 sc->sc_txtimer = 0; 3023 ifp->if_timer = 0; 3024 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3025 3026 callout_stop(&sc->scan_to); 3027 callout_stop(&sc->sc_led_ch); 3028 3029 urtw_intr_disable(sc); 3030 urtw_read8_m(sc, URTW_CMD, &data); 3031 data &= ~URTW_CMD_TX_ENABLE; 3032 data &= ~URTW_CMD_RX_ENABLE; 3033 urtw_write8_m(sc, URTW_CMD, data); 3034 3035 if (sc->sc_rxpipe != NULL) 3036 usbd_abort_pipe(sc->sc_rxpipe); 3037 if (sc->sc_txpipe_low != NULL) 3038 usbd_abort_pipe(sc->sc_txpipe_low); 3039 if (sc->sc_txpipe_normal != NULL) 3040 usbd_abort_pipe(sc->sc_txpipe_normal); 3041 3042 fail: 3043 return; 3044 } 3045 3046 int 3047 urtw_isbmode(uint16_t rate) 3048 { 3049 rate = urtw_rtl2rate(rate); 3050 3051 return (((rate <= 22 && rate != 12 && rate != 18) || 3052 rate == 44) ? (1) : (0)); 3053 } 3054 3055 void 3056 urtw_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 3057 { 3058 struct urtw_rx_data *data = priv; 3059 struct urtw_softc *sc = data->sc; 3060 struct ieee80211com *ic = &sc->sc_ic; 3061 struct ifnet *ifp = ic->ic_ifp; 3062 struct ieee80211_frame *wh; 3063 struct ieee80211_node *ni; 3064 struct mbuf *m, *mnew; 3065 uint8_t *desc, quality, rate; 3066 int actlen, flen, len, nf, rssi, s; 3067 3068 if (status != USBD_NORMAL_COMPLETION) { 3069 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3070 return; 3071 3072 if (status == USBD_STALLED) 3073 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3074 ifp->if_ierrors++; 3075 goto skip; 3076 } 3077 3078 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3079 if (actlen < URTW_MIN_RXBUFSZ) { 3080 ifp->if_ierrors++; 3081 goto skip; 3082 } 3083 3084 if (sc->sc_hwrev & URTW_HWREV_8187) 3085 /* 4 dword and 4 byte CRC */ 3086 len = actlen - (4 * 4); 3087 else 3088 /* 5 dword and 4 byte CRC */ 3089 len = actlen - (4 * 5); 3090 3091 desc = data->buf + len; 3092 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3093 if (flen > actlen) { 3094 ifp->if_ierrors++; 3095 goto skip; 3096 } 3097 3098 rate = (desc[2] & 0xf0) >> 4; 3099 if (sc->sc_hwrev & URTW_HWREV_8187) { 3100 quality = desc[4] & 0xff; 3101 rssi = (desc[6] & 0xfe) >> 1; 3102 3103 /* XXX correct? */ 3104 if (!urtw_isbmode(rate)) { 3105 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3106 rssi = ((90 - rssi) * 100) / 65; 3107 } else { 3108 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3109 rssi = ((95 - rssi) * 100) / 65; 3110 } 3111 } else { 3112 quality = desc[12]; 3113 rssi = 14 - desc[14] / 2; 3114 } 3115 3116 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3117 if (mnew == NULL) { 3118 printf("%s: could not allocate rx mbuf\n", 3119 device_xname(sc->sc_dev)); 3120 ifp->if_ierrors++; 3121 goto skip; 3122 } 3123 MCLGET(mnew, M_DONTWAIT); 3124 if (!(mnew->m_flags & M_EXT)) { 3125 printf("%s: could not allocate rx mbuf cluster\n", 3126 device_xname(sc->sc_dev)); 3127 m_freem(mnew); 3128 ifp->if_ierrors++; 3129 goto skip; 3130 } 3131 3132 m = data->m; 3133 data->m = mnew; 3134 data->buf = mtod(mnew, uint8_t *); 3135 3136 /* finalize mbuf */ 3137 m->m_pkthdr.rcvif = ifp; 3138 m->m_pkthdr.len = m->m_len = flen - 4; 3139 3140 s = splnet(); 3141 3142 if (sc->sc_drvbpf != NULL) { 3143 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3144 3145 /* XXX Are variables correct? */ 3146 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3147 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3148 tap->wr_dbm_antsignal = (int8_t)rssi; 3149 3150 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 3151 } 3152 wh = mtod(m, struct ieee80211_frame *); 3153 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3154 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3155 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3156 3157 /* XXX correct? */ 3158 if (!urtw_isbmode(rate)) { 3159 if (quality > 127) 3160 quality = 0; 3161 else if (quality < 27) 3162 quality = 100; 3163 else 3164 quality = 127 - quality; 3165 } else 3166 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3167 3168 nf = quality; 3169 3170 /* send the frame to the 802.11 layer */ 3171 ieee80211_input(ic, m, ni, rssi, 0); 3172 3173 /* node is no longer needed */ 3174 ieee80211_free_node(ni); 3175 3176 splx(s); 3177 3178 skip: /* setup a new transfer */ 3179 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3180 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3181 (void)usbd_transfer(xfer); 3182 } 3183 3184 usbd_status 3185 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3186 { 3187 uint8_t *gainp; 3188 usbd_status error; 3189 3190 /* XXX for A? */ 3191 gainp = urtw_8225v2_gain_bg; 3192 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3193 usbd_delay_ms(sc->sc_udev, 1); 3194 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3195 usbd_delay_ms(sc->sc_udev, 1); 3196 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3197 usbd_delay_ms(sc->sc_udev, 1); 3198 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3199 usbd_delay_ms(sc->sc_udev, 1); 3200 fail: 3201 return (error); 3202 } 3203 3204 usbd_status 3205 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3206 { 3207 int i; 3208 uint8_t *cck_pwrtable; 3209 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3210 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3211 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3212 usbd_status error; 3213 3214 /* CCK power setting */ 3215 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3216 cck_pwrlvl += sc->sc_txpwr_cck_base; 3217 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3218 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3219 urtw_8225v2_txpwr_cck; 3220 3221 for (i = 0; i < 8; i++) { 3222 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3223 } 3224 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3225 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3226 usbd_delay_ms(sc->sc_udev, 1); 3227 3228 /* OFDM power setting */ 3229 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3230 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3231 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3232 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3233 3234 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3235 if (error) 3236 goto fail; 3237 3238 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3239 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3240 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3241 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3242 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3243 3244 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3245 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3246 usbd_delay_ms(sc->sc_udev, 1); 3247 fail: 3248 return (error); 3249 } 3250 3251 usbd_status 3252 urtw_8225v2_rf_init(struct urtw_rf *rf) 3253 { 3254 struct urtw_softc *sc = rf->rf_sc; 3255 int i; 3256 uint16_t data; 3257 uint32_t data32; 3258 usbd_status error; 3259 3260 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3261 if (error) 3262 goto fail; 3263 3264 error = urtw_8225_usb_init(sc); 3265 if (error) 3266 goto fail; 3267 3268 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3269 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3270 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3271 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3272 3273 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3274 if (error) 3275 goto fail; 3276 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3277 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3278 if (error) 3279 goto fail; 3280 3281 error = urtw_8185_rf_pins_enable(sc); 3282 if (error) 3283 goto fail; 3284 3285 usbd_delay_ms(sc->sc_udev, 1000); 3286 3287 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3288 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3289 urtw_8225v2_rf_part1[i].val); 3290 usbd_delay_ms(sc->sc_udev, 1); 3291 } 3292 usbd_delay_ms(sc->sc_udev, 50); 3293 3294 urtw_8225_write(sc, 0x0, 0x1b7); 3295 3296 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3297 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3298 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3299 } 3300 3301 urtw_8225_write(sc, 0x3, 0x2); 3302 urtw_8225_write(sc, 0x5, 0x4); 3303 urtw_8225_write(sc, 0x0, 0xb7); 3304 urtw_8225_write(sc, 0x2, 0xc4d); 3305 usbd_delay_ms(sc->sc_udev, 100); 3306 urtw_8225_write(sc, 0x2, 0x44d); 3307 usbd_delay_ms(sc->sc_udev, 100); 3308 3309 error = urtw_8225_read(sc, 0x6, &data32); 3310 if (error != 0) 3311 goto fail; 3312 if (data32 != 0xe6) 3313 printf("%s: expect 0xe6!! (0x%x)\n", device_xname(sc->sc_dev), 3314 data32); 3315 if (!(data32 & 0x80)) { 3316 urtw_8225_write(sc, 0x02, 0x0c4d); 3317 usbd_delay_ms(sc->sc_udev, 200); 3318 urtw_8225_write(sc, 0x02, 0x044d); 3319 usbd_delay_ms(sc->sc_udev, 100); 3320 error = urtw_8225_read(sc, 0x6, &data32); 3321 if (error != 0) 3322 goto fail; 3323 if (!(data32 & 0x80)) 3324 printf("%s: RF calibration failed\n", 3325 device_xname(sc->sc_dev)); 3326 } 3327 usbd_delay_ms(sc->sc_udev, 100); 3328 3329 urtw_8225_write(sc, 0x0, 0x2bf); 3330 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3331 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3332 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3333 } 3334 3335 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3336 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3337 urtw_8225v2_rf_part2[i].val); 3338 } 3339 3340 error = urtw_8225v2_setgain(sc, 4); 3341 if (error) 3342 goto fail; 3343 3344 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3345 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3346 urtw_8225v2_rf_part3[i].val); 3347 } 3348 3349 urtw_write8_m(sc, 0x5b, 0x0d); 3350 3351 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3352 if (error) 3353 goto fail; 3354 3355 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3356 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3357 3358 /* TX ant A, 0x0 for B */ 3359 error = urtw_8185_tx_antenna(sc, 0x3); 3360 if (error) 3361 goto fail; 3362 urtw_write32_m(sc, 0x94, 0x3dc00002); 3363 3364 error = urtw_8225_rf_set_chan(rf, 1); 3365 fail: 3366 return (error); 3367 } 3368 3369 usbd_status 3370 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3371 { 3372 struct urtw_softc *sc = rf->rf_sc; 3373 struct ieee80211com *ic = &sc->sc_ic; 3374 struct ieee80211_channel *c = ic->ic_ibss_chan; 3375 usbd_status error; 3376 3377 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3378 if (error) 3379 goto fail; 3380 3381 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3382 usbd_delay_ms(sc->sc_udev, 10); 3383 3384 urtw_write8_m(sc, URTW_SIFS, 0x22); 3385 3386 if(sc->sc_state == IEEE80211_S_ASSOC && 3387 ic->ic_flags & IEEE80211_F_SHSLOT) 3388 urtw_write8_m(sc, URTW_SLOT, 0x9); 3389 else 3390 urtw_write8_m(sc, URTW_SLOT, 0x14); 3391 3392 if (IEEE80211_IS_CHAN_G(c)) { 3393 urtw_write8_m(sc, URTW_DIFS, 0x14); 3394 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3395 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3396 } else { 3397 urtw_write8_m(sc, URTW_DIFS, 0x24); 3398 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3399 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3400 } 3401 3402 fail: 3403 return (error); 3404 } 3405 3406 void 3407 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3408 { 3409 struct urtw_rf *rf = &sc->sc_rf; 3410 struct ieee80211com *ic = &sc->sc_ic; 3411 usbd_status error = 0; 3412 uint32_t data; 3413 u_int chan; 3414 3415 chan = ieee80211_chan2ieee(ic, c); 3416 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3417 return; 3418 /* 3419 * During changing the channel we need to temporary disable 3420 * TX. 3421 */ 3422 urtw_read32_m(sc, URTW_TX_CONF, &data); 3423 data &= ~URTW_TX_LOOPBACK_MASK; 3424 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3425 error = rf->set_chan(rf, chan); 3426 if (error != 0) { 3427 printf("%s could not change the channel\n", 3428 device_xname(sc->sc_dev)); 3429 return; 3430 } 3431 usbd_delay_ms(sc->sc_udev, 10); 3432 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3433 3434 fail: return; 3435 3436 } 3437 3438 void 3439 urtw_next_scan(void *arg) 3440 { 3441 struct urtw_softc *sc = arg; 3442 struct ieee80211com *ic = &sc->sc_ic; 3443 int s; 3444 3445 if (sc->sc_dying) 3446 return; 3447 3448 s = splnet(); 3449 if (ic->ic_state == IEEE80211_S_SCAN) 3450 ieee80211_next_scan(ic); 3451 splx(s); 3452 } 3453 3454 void 3455 urtw_task(void *arg) 3456 { 3457 struct urtw_softc *sc = arg; 3458 struct ieee80211com *ic = &sc->sc_ic; 3459 struct ieee80211_node *ni; 3460 enum ieee80211_state ostate; 3461 usbd_status error = 0; 3462 3463 if (sc->sc_dying) 3464 return; 3465 3466 ostate = ic->ic_state; 3467 3468 switch (sc->sc_state) { 3469 case IEEE80211_S_INIT: 3470 if (ostate == IEEE80211_S_RUN) { 3471 /* turn link LED off */ 3472 (void)urtw_led_off(sc, URTW_LED_GPIO); 3473 } 3474 break; 3475 3476 case IEEE80211_S_SCAN: 3477 urtw_set_chan(sc, ic->ic_curchan); 3478 if (!sc->sc_dying) 3479 callout_schedule(&sc->scan_to, mstohz(200)); 3480 break; 3481 3482 case IEEE80211_S_AUTH: 3483 case IEEE80211_S_ASSOC: 3484 urtw_set_chan(sc, ic->ic_curchan); 3485 break; 3486 3487 case IEEE80211_S_RUN: 3488 ni = ic->ic_bss; 3489 3490 urtw_set_chan(sc, ic->ic_curchan); 3491 3492 /* setting bssid. */ 3493 error = urtw_set_bssid(sc, ni->ni_bssid); 3494 if (error != 0) 3495 goto fail; 3496 urtw_update_msr(sc); 3497 /* XXX maybe the below would be incorrect. */ 3498 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3499 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3500 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3501 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3502 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3503 if (error != 0) 3504 printf("%s: could not control LED (%d)\n", 3505 device_xname(sc->sc_dev), error); 3506 break; 3507 } 3508 3509 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3510 3511 fail: 3512 if (error != 0) { 3513 DPRINTF(("%s: error duing processing RUN state.", 3514 device_xname(sc->sc_dev))); 3515 } 3516 } 3517 3518 usbd_status 3519 urtw_8187b_update_wmm(struct urtw_softc *sc) 3520 { 3521 struct ieee80211com *ic = &sc->sc_ic; 3522 struct ieee80211_channel *c = ic->ic_ibss_chan; 3523 uint32_t data; 3524 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3525 usbd_status error; 3526 3527 sifs = 0xa; 3528 if (IEEE80211_IS_CHAN_G(c)) 3529 slot = 0x9; 3530 else 3531 slot = 0x14; 3532 3533 aifs = (2 * slot) + sifs; 3534 ecwmin = 3; 3535 ecwmax = 7; 3536 3537 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3538 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3539 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3540 3541 urtw_write32_m(sc, URTW_AC_VO, data); 3542 urtw_write32_m(sc, URTW_AC_VI, data); 3543 urtw_write32_m(sc, URTW_AC_BE, data); 3544 urtw_write32_m(sc, URTW_AC_BK, data); 3545 3546 fail: 3547 return (error); 3548 } 3549 3550 usbd_status 3551 urtw_8187b_reset(struct urtw_softc *sc) 3552 { 3553 uint8_t data; 3554 usbd_status error; 3555 3556 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3557 if (error) 3558 goto fail; 3559 3560 urtw_read8_m(sc, URTW_CONFIG3, &data); 3561 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3562 URTW_CONFIG3_GNT_SELECT); 3563 3564 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3565 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3566 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3567 3568 urtw_write8_m(sc, 0x61, 0x10); 3569 urtw_read8_m(sc, 0x62, &data); 3570 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3571 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3572 3573 urtw_read8_m(sc, URTW_CONFIG3, &data); 3574 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3575 3576 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3577 if (error) 3578 goto fail; 3579 3580 urtw_read8_m(sc, URTW_CMD, &data); 3581 data = (data & 2) | URTW_CMD_RST; 3582 urtw_write8_m(sc, URTW_CMD, data); 3583 usbd_delay_ms(sc->sc_udev, 100); 3584 3585 urtw_read8_m(sc, URTW_CMD, &data); 3586 if (data & URTW_CMD_RST) { 3587 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3588 goto fail; 3589 } 3590 3591 fail: 3592 return (error); 3593 } 3594 3595 int 3596 urtw_8187b_init(struct ifnet *ifp) 3597 { 3598 struct urtw_softc *sc = ifp->if_softc; 3599 struct urtw_rf *rf = &sc->sc_rf; 3600 struct ieee80211com *ic = &sc->sc_ic; 3601 int ret; 3602 uint8_t data; 3603 usbd_status error; 3604 3605 urtw_stop(ifp, 0); 3606 3607 error = urtw_8187b_update_wmm(sc); 3608 if (error != 0) 3609 goto fail; 3610 error = urtw_8187b_reset(sc); 3611 if (error) 3612 goto fail; 3613 3614 /* Applying MAC address again. */ 3615 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3616 if (error) 3617 goto fail; 3618 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3619 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3620 if (error) 3621 goto fail; 3622 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3623 if (error) 3624 goto fail; 3625 3626 error = urtw_update_msr(sc); 3627 if (error) 3628 goto fail; 3629 3630 error = rf->init(rf); 3631 if (error != 0) 3632 goto fail; 3633 3634 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3635 URTW_CMD_RX_ENABLE); 3636 error = urtw_intr_enable(sc); 3637 if (error != 0) 3638 goto fail; 3639 3640 error = urtw_write8e(sc, 0x41, 0xf4); 3641 if (error != 0) 3642 goto fail; 3643 error = urtw_write8e(sc, 0x40, 0x00); 3644 if (error != 0) 3645 goto fail; 3646 error = urtw_write8e(sc, 0x42, 0x00); 3647 if (error != 0) 3648 goto fail; 3649 error = urtw_write8e(sc, 0x42, 0x01); 3650 if (error != 0) 3651 goto fail; 3652 error = urtw_write8e(sc, 0x40, 0x0f); 3653 if (error != 0) 3654 goto fail; 3655 error = urtw_write8e(sc, 0x42, 0x00); 3656 if (error != 0) 3657 goto fail; 3658 error = urtw_write8e(sc, 0x42, 0x01); 3659 if (error != 0) 3660 goto fail; 3661 3662 urtw_read8_m(sc, 0xdb, &data); 3663 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3664 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3665 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3666 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3667 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3668 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3669 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3670 urtw_write8_m(sc, 0x61, 0); 3671 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3672 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3673 urtw_write8_m(sc, 0xda, 0x10); 3674 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3675 3676 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3677 3678 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3679 3680 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3681 3682 /* Reset softc variables. */ 3683 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3684 sc->sc_txtimer = 0; 3685 3686 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3687 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3688 if (error != 0) { 3689 printf("%s: could not set configuration no\n", 3690 device_xname(sc->sc_dev)); 3691 goto fail; 3692 } 3693 /* Get the first interface handle. */ 3694 error = usbd_device2interface_handle(sc->sc_udev, 3695 URTW_IFACE_INDEX, &sc->sc_iface); 3696 if (error != 0) { 3697 printf("%s: could not get interface handle\n", 3698 device_xname(sc->sc_dev)); 3699 goto fail; 3700 } 3701 error = urtw_open_pipes(sc); 3702 if (error != 0) 3703 goto fail; 3704 ret = urtw_alloc_rx_data_list(sc); 3705 if (error != 0) 3706 goto fail; 3707 ret = urtw_alloc_tx_data_list(sc); 3708 if (error != 0) 3709 goto fail; 3710 sc->sc_flags |= URTW_INIT_ONCE; 3711 } 3712 3713 error = urtw_rx_enable(sc); 3714 if (error != 0) 3715 goto fail; 3716 error = urtw_tx_enable(sc); 3717 if (error != 0) 3718 goto fail; 3719 3720 ifp->if_flags &= ~IFF_OACTIVE; 3721 ifp->if_flags |= IFF_RUNNING; 3722 3723 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3724 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3725 else 3726 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3727 3728 fail: 3729 return (error); 3730 } 3731 3732 usbd_status 3733 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3734 { 3735 int i; 3736 usbd_status error; 3737 3738 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3739 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3740 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3741 } 3742 3743 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3744 urtw_write16_m(sc, URTW_INT_MIG, 0); 3745 3746 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3747 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3748 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3749 3750 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3751 3752 fail: 3753 return (error); 3754 } 3755 3756 usbd_status 3757 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3758 { 3759 usbd_status error; 3760 3761 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3762 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3763 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3764 usbd_delay_ms(sc->sc_udev, 100); 3765 3766 fail: 3767 return (error); 3768 } 3769 3770 usbd_status 3771 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3772 { 3773 struct ieee80211com *ic = &sc->sc_ic; 3774 struct ieee80211_channel *c = ic->ic_ibss_chan; 3775 uint8_t aifs, difs, eifs, sifs, slot; 3776 usbd_status error; 3777 3778 urtw_write8_m(sc, URTW_SIFS, 0x22); 3779 3780 sifs = 0xa; 3781 if (IEEE80211_IS_CHAN_G(c)) { 3782 slot = 0x9; 3783 difs = 0x1c; 3784 eifs = 0x5b; 3785 } else { 3786 slot = 0x14; 3787 difs = 0x32; 3788 eifs = 0x5b; 3789 } 3790 aifs = (2 * slot) + sifs; 3791 3792 urtw_write8_m(sc, URTW_SLOT, slot); 3793 3794 urtw_write8_m(sc, URTW_AC_VO, aifs); 3795 urtw_write8_m(sc, URTW_AC_VI, aifs); 3796 urtw_write8_m(sc, URTW_AC_BE, aifs); 3797 urtw_write8_m(sc, URTW_AC_BK, aifs); 3798 3799 urtw_write8_m(sc, URTW_DIFS, difs); 3800 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3801 3802 fail: 3803 return (error); 3804 } 3805 3806 usbd_status 3807 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3808 { 3809 struct urtw_softc *sc = rf->rf_sc; 3810 unsigned int i; 3811 uint8_t data; 3812 usbd_status error; 3813 3814 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3815 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3816 urtw_read8_m(sc, URTW_CW_CONF, &data); 3817 urtw_write8_m(sc, URTW_CW_CONF, data | 3818 URTW_CW_CONF_PERPACKET_RETRY); 3819 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3820 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3821 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3822 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3823 3824 /* Auto rate fallback control. */ 3825 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3826 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3827 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3828 URTW_RATE_FALLBACK_ENABLE); 3829 3830 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3831 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3832 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3833 3834 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3835 if (error) 3836 goto fail; 3837 urtw_read8_m(sc, URTW_CONFIG1, &data); 3838 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3839 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3840 if (error) 3841 goto fail; 3842 3843 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3844 urtw_8225v2_b_config_mac(sc); 3845 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3846 3847 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3848 if (error) 3849 goto fail; 3850 urtw_read8_m(sc, URTW_CONFIG3, &data); 3851 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3852 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3853 if (error) 3854 goto fail; 3855 3856 urtw_8225v2_b_init_rfe(sc); 3857 3858 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3859 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3860 urtw_8225v2_b_rf[i].val); 3861 } 3862 3863 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3864 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3865 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3866 } 3867 3868 urtw_8225_write(sc, 0x03, 0x080); 3869 urtw_8225_write(sc, 0x05, 0x004); 3870 urtw_8225_write(sc, 0x00, 0x0b7); 3871 urtw_8225_write(sc, 0x02, 0xc4d); 3872 urtw_8225_write(sc, 0x02, 0x44d); 3873 urtw_8225_write(sc, 0x00, 0x2bf); 3874 3875 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3876 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3877 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3878 3879 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3880 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3881 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3882 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3883 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3884 } 3885 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3886 3887 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3888 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3889 3890 urtw_8225v2_b_update_chan(sc); 3891 3892 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3893 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3894 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3895 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3896 3897 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3898 fail: 3899 return (error); 3900 } 3901 3902 usbd_status 3903 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3904 { 3905 struct urtw_softc *sc = rf->rf_sc; 3906 usbd_status error; 3907 3908 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3909 if (error) 3910 goto fail; 3911 3912 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3913 /* 3914 * Delay removed from 8185 to 8187. 3915 * usbd_delay_ms(sc->sc_udev, 10); 3916 */ 3917 3918 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3919 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3920 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3921 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3922 3923 fail: 3924 return (error); 3925 } 3926 3927 usbd_status 3928 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3929 { 3930 int i; 3931 uint8_t *cck_pwrtable; 3932 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3933 ofdm_pwrlvl_max; 3934 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3935 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3936 usbd_status error; 3937 3938 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3939 cck_pwrlvl_min = 0; 3940 cck_pwrlvl_max = 15; 3941 ofdm_pwrlvl_min = 2; 3942 ofdm_pwrlvl_max = 17; 3943 } else { 3944 cck_pwrlvl_min = 7; 3945 cck_pwrlvl_max = 22; 3946 ofdm_pwrlvl_min = 10; 3947 ofdm_pwrlvl_max = 25; 3948 } 3949 3950 /* CCK power setting */ 3951 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3952 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3953 3954 cck_pwrlvl += sc->sc_txpwr_cck_base; 3955 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3956 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3957 3958 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3959 urtw_8225v2_txpwr_cck; 3960 3961 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3962 if (cck_pwrlvl <= 6) 3963 ; /* do nothing */ 3964 else if (cck_pwrlvl <= 11) 3965 cck_pwrtable += 8; 3966 else 3967 cck_pwrtable += 16; 3968 } else { 3969 if (cck_pwrlvl <= 5) 3970 ; /* do nothing */ 3971 else if (cck_pwrlvl <= 11) 3972 cck_pwrtable += 8; 3973 else if (cck_pwrlvl <= 17) 3974 cck_pwrtable += 16; 3975 else 3976 cck_pwrtable += 24; 3977 } 3978 3979 for (i = 0; i < 8; i++) { 3980 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3981 } 3982 3983 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3984 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3985 /* 3986 * Delay removed from 8185 to 8187. 3987 * usbd_delay_ms(sc->sc_udev, 1); 3988 */ 3989 3990 /* OFDM power setting */ 3991 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3992 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3993 3994 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3995 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3996 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3997 3998 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3999 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 4000 4001 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 4002 if (ofdm_pwrlvl <= 11) { 4003 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 4004 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 4005 } else { 4006 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4007 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4008 } 4009 } else { 4010 if (ofdm_pwrlvl <= 11) { 4011 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4012 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4013 } else if (ofdm_pwrlvl <= 17) { 4014 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4015 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4016 } else { 4017 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4018 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4019 } 4020 } 4021 4022 /* 4023 * Delay removed from 8185 to 8187. 4024 * usbd_delay_ms(sc->sc_udev, 1); 4025 */ 4026 fail: 4027 return (error); 4028 } 4029 4030 int 4031 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4032 { 4033 int error; 4034 4035 urtw_write32_m(sc, URTW_BSSID, 4036 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4037 urtw_write16_m(sc, URTW_BSSID + 4, 4038 bssid[4] | bssid[5] << 8); 4039 4040 return 0; 4041 4042 fail: 4043 return error; 4044 } 4045 4046 int 4047 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4048 { 4049 int error; 4050 4051 urtw_write32_m(sc, URTW_MAC0, 4052 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4053 urtw_write16_m(sc, URTW_MAC4, 4054 addr[4] | addr[5] << 8); 4055 4056 return 0; 4057 4058 fail: 4059 return error; 4060 } 4061 4062 MODULE(MODULE_CLASS_DRIVER, if_urtw, "bpf"); 4063 4064 #ifdef _MODULE 4065 #include "ioconf.c" 4066 #endif 4067 4068 static int 4069 if_urtw_modcmd(modcmd_t cmd, void *aux) 4070 { 4071 int error = 0; 4072 4073 switch (cmd) { 4074 case MODULE_CMD_INIT: 4075 #ifdef _MODULE 4076 error = config_init_component(cfdriver_ioconf_urtw, 4077 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4078 #endif 4079 return error; 4080 case MODULE_CMD_FINI: 4081 #ifdef _MODULE 4082 error = config_fini_component(cfdriver_ioconf_urtw, 4083 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4084 #endif 4085 return error; 4086 default: 4087 return ENOTTY; 4088 } 4089 } 4090
Indexes created Fri Oct 03 02:09:57 GMT 2025