if_urtw.c revision 1.1.8.3
1 /* $NetBSD: if_urtw.c,v 1.1.8.3 2013/01/23 00:06:12 yamt Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.1.8.3 2013/01/23 00:06:12 yamt Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/sockio.h> 26 #include <sys/proc.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 38 #include <machine/endian.h> 39 #include <net/bpf.h> 40 #include <net/if.h> 41 #include <net/if_arp.h> 42 #include <net/if_dl.h> 43 #include <net/if_ether.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_inarp.h> 51 #include <netinet/ip.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include "if_urtwreg.h" 63 64 #ifdef URTW_DEBUG 65 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 67 int urtw_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * Recognized device vendors/products. 75 */ 76 static const struct urtw_type { 77 struct usb_devno dev; 78 uint8_t rev; 79 } urtw_devs[] = { 80 #define URTW_DEV_RTL8187(v, p) \ 81 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 82 #define URTW_DEV_RTL8187B(v, p) \ 83 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 84 /* Realtek RTL8187 devices. */ 85 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 86 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 87 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 88 URTW_DEV_RTL8187(LOGITEC, RTL8187), 89 URTW_DEV_RTL8187(NETGEAR, WG111V2), 90 URTW_DEV_RTL8187(REALTEK, RTL8187), 91 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 92 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 93 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 94 /* Realtek RTL8187B devices. */ 95 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 96 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 97 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 98 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 99 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 100 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 101 #undef URTW_DEV_RTL8187 102 #undef URTW_DEV_RTL8187B 103 }; 104 #define urtw_lookup(v, p) \ 105 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 106 107 /* 108 * Helper read/write macros. 109 */ 110 #define urtw_read8_m(sc, val, data) do { \ 111 error = urtw_read8_c(sc, val, data, 0); \ 112 if (error != 0) \ 113 goto fail; \ 114 } while (0) 115 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 116 error = urtw_read8_c(sc, val, data, idx); \ 117 if (error != 0) \ 118 goto fail; \ 119 } while (0) 120 #define urtw_write8_m(sc, val, data) do { \ 121 error = urtw_write8_c(sc, val, data, 0); \ 122 if (error != 0) \ 123 goto fail; \ 124 } while (0) 125 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 126 error = urtw_write8_c(sc, val, data, idx); \ 127 if (error != 0) \ 128 goto fail; \ 129 } while (0) 130 #define urtw_read16_m(sc, val, data) do { \ 131 error = urtw_read16_c(sc, val, data, 0); \ 132 if (error != 0) \ 133 goto fail; \ 134 } while (0) 135 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 136 error = urtw_read16_c(sc, val, data, idx); \ 137 if (error != 0) \ 138 goto fail; \ 139 } while (0) 140 #define urtw_write16_m(sc, val, data) do { \ 141 error = urtw_write16_c(sc, val, data, 0); \ 142 if (error != 0) \ 143 goto fail; \ 144 } while (0) 145 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 146 error = urtw_write16_c(sc, val, data, idx); \ 147 if (error != 0) \ 148 goto fail; \ 149 } while (0) 150 #define urtw_read32_m(sc, val, data) do { \ 151 error = urtw_read32_c(sc, val, data, 0); \ 152 if (error != 0) \ 153 goto fail; \ 154 } while (0) 155 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 156 error = urtw_read32_c(sc, val, data, idx); \ 157 if (error != 0) \ 158 goto fail; \ 159 } while (0) 160 #define urtw_write32_m(sc, val, data) do { \ 161 error = urtw_write32_c(sc, val, data, 0); \ 162 if (error != 0) \ 163 goto fail; \ 164 } while (0) 165 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 166 error = urtw_write32_c(sc, val, data, idx); \ 167 if (error != 0) \ 168 goto fail; \ 169 } while (0) 170 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 171 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 172 if (error != 0) \ 173 goto fail; \ 174 } while (0) 175 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 176 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 177 if (error != 0) \ 178 goto fail; \ 179 } while (0) 180 #define urtw_8225_write(sc, val, data) do { \ 181 error = urtw_8225_write_c(sc, val, data); \ 182 if (error != 0) \ 183 goto fail; \ 184 } while (0) 185 186 struct urtw_pair { 187 uint32_t reg; 188 uint32_t val; 189 }; 190 191 struct urtw_pair_idx { 192 uint8_t reg; 193 uint8_t val; 194 uint8_t idx; 195 }; 196 197 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 198 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 199 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 200 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 201 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 202 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 203 { 0xff, 0x00, 0 }, 204 205 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 206 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 207 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 208 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 209 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 210 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 211 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 212 { 0xf8, 0x08, 1 }, 213 214 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 215 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 216 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 217 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 218 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 219 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 220 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 221 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 222 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 223 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 224 225 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 226 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 227 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 228 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 229 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 230 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 231 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 232 233 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 234 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 235 }; 236 237 static uint8_t urtw_8225_agc[] = { 238 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 239 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 240 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 241 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 242 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 243 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 244 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 245 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 246 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 247 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 248 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 249 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 250 }; 251 252 static uint32_t urtw_8225_channel[] = { 253 0x0000, /* dummy channel 0 */ 254 0x085c, /* 1 */ 255 0x08dc, /* 2 */ 256 0x095c, /* 3 */ 257 0x09dc, /* 4 */ 258 0x0a5c, /* 5 */ 259 0x0adc, /* 6 */ 260 0x0b5c, /* 7 */ 261 0x0bdc, /* 8 */ 262 0x0c5c, /* 9 */ 263 0x0cdc, /* 10 */ 264 0x0d5c, /* 11 */ 265 0x0ddc, /* 12 */ 266 0x0e5c, /* 13 */ 267 0x0f72, /* 14 */ 268 }; 269 270 static uint8_t urtw_8225_gain[] = { 271 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 272 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 273 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 274 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 275 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 276 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 277 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 278 }; 279 280 static struct urtw_pair urtw_8225_rf_part1[] = { 281 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 282 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 283 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 284 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 285 }; 286 287 static struct urtw_pair urtw_8225_rf_part2[] = { 288 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 289 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 290 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 291 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 292 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 293 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 294 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 295 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 296 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 297 { 0x27, 0x88 } 298 }; 299 300 static struct urtw_pair urtw_8225_rf_part3[] = { 301 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 302 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 303 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 304 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 305 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 306 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 307 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 308 }; 309 310 static uint16_t urtw_8225_rxgain[] = { 311 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 312 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 313 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 314 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 315 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 316 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 317 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 318 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 319 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 320 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 321 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 322 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 323 }; 324 325 static uint8_t urtw_8225_threshold[] = { 326 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 327 }; 328 329 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 330 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 331 }; 332 333 static uint8_t urtw_8225_txpwr_cck[] = { 334 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 335 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 336 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 337 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 338 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 339 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 340 }; 341 342 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 343 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 344 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 345 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 346 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 347 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 348 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 349 }; 350 351 static uint8_t urtw_8225_txpwr_ofdm[] = { 352 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 353 }; 354 355 static uint8_t urtw_8225v2_agc[] = { 356 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 357 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 358 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 359 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 360 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 361 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 362 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 363 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 364 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 365 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 366 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 367 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 368 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 369 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 370 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 371 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 372 }; 373 374 static uint8_t urtw_8225v2_ofdm[] = { 375 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 376 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 377 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 378 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 379 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 380 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 381 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 382 0x6d, 0x3c, 0xfb, 0x07 383 }; 384 385 static uint8_t urtw_8225v2_gain_bg[] = { 386 0x23, 0x15, 0xa5, /* -82-1dbm */ 387 0x23, 0x15, 0xb5, /* -82-2dbm */ 388 0x23, 0x15, 0xc5, /* -82-3dbm */ 389 0x33, 0x15, 0xc5, /* -78dbm */ 390 0x43, 0x15, 0xc5, /* -74dbm */ 391 0x53, 0x15, 0xc5, /* -70dbm */ 392 0x63, 0x15, 0xc5, /* -66dbm */ 393 }; 394 395 static struct urtw_pair urtw_8225v2_rf_part1[] = { 396 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 397 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 398 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 399 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 400 }; 401 402 static struct urtw_pair urtw_8225v2_rf_part2[] = { 403 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 404 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 405 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 406 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 407 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 408 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 409 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 410 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 411 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 412 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 413 }; 414 415 static struct urtw_pair urtw_8225v2_rf_part3[] = { 416 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 417 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 418 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 419 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 420 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 421 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 422 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 423 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 424 }; 425 426 static uint16_t urtw_8225v2_rxgain[] = { 427 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 428 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 429 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 430 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 431 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 432 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 433 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 434 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 435 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 436 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 437 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 438 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 439 }; 440 441 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 442 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 443 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 444 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 445 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 446 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 447 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 448 }; 449 450 static uint8_t urtw_8225v2_txpwr_cck[] = { 451 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 452 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 453 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 454 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 455 }; 456 457 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 458 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 459 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 460 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 461 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 462 }; 463 464 static struct urtw_pair urtw_8225v2_b_rf[] = { 465 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 466 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 467 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 468 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 469 { 0x00, 0x01b7 } 470 }; 471 472 static struct urtw_pair urtw_ratetable[] = { 473 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 474 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 475 { 96, 10 }, { 108, 11 } 476 }; 477 478 int urtw_init(struct ifnet *); 479 void urtw_stop(struct ifnet *, int); 480 int urtw_ioctl(struct ifnet *, u_long, void *); 481 void urtw_start(struct ifnet *); 482 int urtw_alloc_rx_data_list(struct urtw_softc *); 483 void urtw_free_rx_data_list(struct urtw_softc *); 484 int urtw_alloc_tx_data_list(struct urtw_softc *); 485 void urtw_free_tx_data_list(struct urtw_softc *); 486 void urtw_rxeof(usbd_xfer_handle, usbd_private_handle, 487 usbd_status); 488 int urtw_tx_start(struct urtw_softc *, 489 struct ieee80211_node *, struct mbuf *, int); 490 void urtw_txeof_low(usbd_xfer_handle, usbd_private_handle, 491 usbd_status); 492 void urtw_txeof_normal(usbd_xfer_handle, usbd_private_handle, 493 usbd_status); 494 void urtw_next_scan(void *); 495 void urtw_task(void *); 496 void urtw_ledusbtask(void *); 497 void urtw_ledtask(void *); 498 int urtw_media_change(struct ifnet *); 499 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 500 void urtw_watchdog(struct ifnet *); 501 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 502 int urtw_isbmode(uint16_t); 503 uint16_t urtw_rate2rtl(int rate); 504 uint16_t urtw_rtl2rate(int); 505 usbd_status urtw_set_rate(struct urtw_softc *); 506 usbd_status urtw_update_msr(struct urtw_softc *); 507 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 508 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 509 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 510 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 511 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 512 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 513 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 514 usbd_status urtw_eprom_ck(struct urtw_softc *); 515 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 516 int); 517 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 518 uint32_t *); 519 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 520 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 521 usbd_status urtw_get_macaddr(struct urtw_softc *); 522 usbd_status urtw_get_txpwr(struct urtw_softc *); 523 usbd_status urtw_get_rfchip(struct urtw_softc *); 524 usbd_status urtw_led_init(struct urtw_softc *); 525 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 526 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 527 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 528 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 529 uint32_t); 530 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 531 uint32_t); 532 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 533 usbd_status urtw_8225_usb_init(struct urtw_softc *); 534 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 535 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 536 uint16_t); 537 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 538 usbd_status urtw_8225_rf_init(struct urtw_rf *); 539 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 540 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 541 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 542 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 543 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 544 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 545 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 546 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 547 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 548 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 549 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 550 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 551 usbd_status urtw_open_pipes(struct urtw_softc *); 552 usbd_status urtw_close_pipes(struct urtw_softc *); 553 usbd_status urtw_intr_enable(struct urtw_softc *); 554 usbd_status urtw_intr_disable(struct urtw_softc *); 555 usbd_status urtw_reset(struct urtw_softc *); 556 usbd_status urtw_led_on(struct urtw_softc *, int); 557 usbd_status urtw_led_ctl(struct urtw_softc *, int); 558 usbd_status urtw_led_blink(struct urtw_softc *); 559 usbd_status urtw_led_mode0(struct urtw_softc *, int); 560 usbd_status urtw_led_mode1(struct urtw_softc *, int); 561 usbd_status urtw_led_mode2(struct urtw_softc *, int); 562 usbd_status urtw_led_mode3(struct urtw_softc *, int); 563 usbd_status urtw_rx_setconf(struct urtw_softc *); 564 usbd_status urtw_rx_enable(struct urtw_softc *); 565 usbd_status urtw_tx_enable(struct urtw_softc *); 566 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 567 usbd_status urtw_8187b_reset(struct urtw_softc *); 568 int urtw_8187b_init(struct ifnet *); 569 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 570 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 571 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 572 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 573 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 574 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 575 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 576 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 577 578 int urtw_match(device_t, cfdata_t, void *); 579 void urtw_attach(device_t, device_t, void *); 580 int urtw_detach(device_t, int); 581 int urtw_activate(device_t, enum devact); 582 583 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 584 urtw_match, 585 urtw_attach, 586 urtw_detach, 587 urtw_activate 588 ); 589 590 int 591 urtw_match(device_t parent, cfdata_t match, void *aux) 592 { 593 struct usb_attach_arg *uaa = aux; 594 595 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 596 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 597 } 598 599 void 600 urtw_attach(device_t parent, device_t self, void *aux) 601 { 602 struct urtw_softc *sc = device_private(self); 603 struct usb_attach_arg *uaa = aux; 604 struct ieee80211com *ic = &sc->sc_ic; 605 struct ifnet *ifp = &sc->sc_if; 606 usbd_status error; 607 uint8_t data8; 608 uint32_t data; 609 int i; 610 611 sc->sc_dev = self; 612 sc->sc_udev = uaa->device; 613 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 614 615 printf(": "); 616 617 if (sc->sc_hwrev & URTW_HWREV_8187) { 618 urtw_read32_m(sc, URTW_TX_CONF, &data); 619 data &= URTW_TX_HWREV_MASK; 620 switch (data) { 621 case URTW_TX_HWREV_8187_D: 622 sc->sc_hwrev |= URTW_HWREV_8187_D; 623 printf("RTL8187 rev D"); 624 break; 625 case URTW_TX_HWREV_8187B_D: 626 /* 627 * Detect Realtek RTL8187B devices that use 628 * USB IDs of RTL8187. 629 */ 630 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 631 printf("RTL8187B rev B (early)"); 632 break; 633 default: 634 sc->sc_hwrev |= URTW_HWREV_8187_B; 635 printf("RTL8187 rev 0x%02x", data >> 25); 636 break; 637 } 638 } else { 639 /* RTL8187B hwrev register. */ 640 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 641 switch (data8) { 642 case URTW_8187B_HWREV_8187B_B: 643 sc->sc_hwrev |= URTW_HWREV_8187B_B; 644 printf("RTL8187B rev B"); 645 break; 646 case URTW_8187B_HWREV_8187B_D: 647 sc->sc_hwrev |= URTW_HWREV_8187B_D; 648 printf("RTL8187B rev D"); 649 break; 650 case URTW_8187B_HWREV_8187B_E: 651 sc->sc_hwrev |= URTW_HWREV_8187B_E; 652 printf("RTL8187B rev E"); 653 break; 654 default: 655 sc->sc_hwrev |= URTW_HWREV_8187B_B; 656 printf("RTL8187B rev 0x%02x", data8); 657 break; 658 } 659 } 660 661 urtw_read32_m(sc, URTW_RX, &data); 662 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 663 URTW_EEPROM_93C46; 664 665 error = urtw_get_rfchip(sc); 666 if (error != 0) 667 goto fail; 668 error = urtw_get_macaddr(sc); 669 if (error != 0) 670 goto fail; 671 error = urtw_get_txpwr(sc); 672 if (error != 0) 673 goto fail; 674 error = urtw_led_init(sc); /* XXX incompleted */ 675 if (error != 0) 676 goto fail; 677 678 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 679 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 680 sc->sc_currate = 3; 681 /* XXX for what? */ 682 sc->sc_preamble_mode = 2; 683 684 usb_init_task(&sc->sc_task, urtw_task, sc, 0); 685 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 0); 686 callout_init(&sc->scan_to, 0); 687 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 688 callout_init(&sc->sc_led_ch, 0); 689 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 690 691 ic->ic_ifp = ifp; 692 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 693 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 694 ic->ic_state = IEEE80211_S_INIT; 695 696 /* set device capabilities */ 697 ic->ic_caps = 698 IEEE80211_C_MONITOR | /* monitor mode supported */ 699 IEEE80211_C_TXPMGT | /* tx power management */ 700 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 701 IEEE80211_C_SHSLOT | /* short slot time supported */ 702 IEEE80211_C_WEP | /* s/w WEP */ 703 IEEE80211_C_WPA; /* WPA/RSN */ 704 705 /* set supported .11b and .11g rates */ 706 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 707 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 708 709 /* set supported .11b and .11g channels (1 through 14) */ 710 for (i = 1; i <= 14; i++) { 711 ic->ic_channels[i].ic_freq = 712 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 713 ic->ic_channels[i].ic_flags = 714 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 715 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 716 } 717 718 ifp->if_softc = sc; 719 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 720 if (sc->sc_hwrev & URTW_HWREV_8187) { 721 ifp->if_init = urtw_init; 722 } else { 723 ifp->if_init = urtw_8187b_init; 724 } 725 ifp->if_ioctl = urtw_ioctl; 726 ifp->if_start = urtw_start; 727 ifp->if_watchdog = urtw_watchdog; 728 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 729 IFQ_SET_READY(&ifp->if_snd); 730 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 731 732 if_attach(ifp); 733 ieee80211_ifattach(ic); 734 735 /* override state transition machine */ 736 sc->sc_newstate = ic->ic_newstate; 737 ic->ic_newstate = urtw_newstate; 738 ieee80211_media_init(ic, urtw_media_change, ieee80211_media_status); 739 740 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 741 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 742 &sc->sc_drvbpf); 743 744 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 745 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 746 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 747 748 sc->sc_txtap_len = sizeof sc->sc_txtapu; 749 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 750 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 751 752 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 753 754 ieee80211_announce(ic); 755 756 return; 757 fail: 758 printf(": %s failed!\n", __func__); 759 sc->sc_dying = true; 760 } 761 762 int 763 urtw_detach(device_t self, int flags) 764 { 765 struct urtw_softc *sc = device_private(self); 766 struct ifnet *ifp = &sc->sc_if; 767 int s; 768 769 s = splusb(); 770 771 sc->sc_dying = true; 772 773 callout_destroy(&sc->scan_to); 774 callout_destroy(&sc->sc_led_ch); 775 776 usb_rem_task(sc->sc_udev, &sc->sc_task); 777 usb_rem_task(sc->sc_udev, &sc->sc_ledtask); 778 779 if (ifp->if_softc != NULL) { 780 bpf_detach(ifp); 781 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 782 if_detach(ifp); 783 } 784 785 /* abort and free xfers */ 786 urtw_free_tx_data_list(sc); 787 urtw_free_rx_data_list(sc); 788 urtw_close_pipes(sc); 789 790 splx(s); 791 792 return (0); 793 } 794 795 int 796 urtw_activate(device_t self, enum devact act) 797 { 798 struct urtw_softc *sc = device_private(self); 799 800 switch (act) { 801 case DVACT_DEACTIVATE: 802 sc->sc_dying = true; 803 break; 804 } 805 806 return (0); 807 } 808 809 usbd_status 810 urtw_close_pipes(struct urtw_softc *sc) 811 { 812 usbd_status error = 0; 813 814 if (sc->sc_rxpipe != NULL) { 815 error = usbd_close_pipe(sc->sc_rxpipe); 816 if (error != 0) 817 goto fail; 818 sc->sc_rxpipe = NULL; 819 } 820 if (sc->sc_txpipe_low != NULL) { 821 error = usbd_close_pipe(sc->sc_txpipe_low); 822 if (error != 0) 823 goto fail; 824 sc->sc_txpipe_low = NULL; 825 } 826 if (sc->sc_txpipe_normal != NULL) { 827 error = usbd_close_pipe(sc->sc_txpipe_normal); 828 if (error != 0) 829 goto fail; 830 sc->sc_txpipe_normal = NULL; 831 } 832 fail: 833 return (error); 834 } 835 836 usbd_status 837 urtw_open_pipes(struct urtw_softc *sc) 838 { 839 usbd_status error; 840 841 /* 842 * NB: there is no way to distinguish each pipes so we need to hardcode 843 * pipe numbers 844 */ 845 846 /* tx pipe - low priority packets */ 847 if (sc->sc_hwrev & URTW_HWREV_8187) 848 error = usbd_open_pipe(sc->sc_iface, 0x2, 849 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 850 else 851 error = usbd_open_pipe(sc->sc_iface, 0x6, 852 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 853 if (error != 0) { 854 printf("%s: could not open Tx low pipe: %s\n", 855 device_xname(sc->sc_dev), usbd_errstr(error)); 856 goto fail; 857 } 858 /* tx pipe - normal priority packets */ 859 if (sc->sc_hwrev & URTW_HWREV_8187) 860 error = usbd_open_pipe(sc->sc_iface, 0x3, 861 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 862 else 863 error = usbd_open_pipe(sc->sc_iface, 0x7, 864 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 865 if (error != 0) { 866 printf("%s: could not open Tx normal pipe: %s\n", 867 device_xname(sc->sc_dev), usbd_errstr(error)); 868 goto fail; 869 } 870 /* rx pipe */ 871 if (sc->sc_hwrev & URTW_HWREV_8187) 872 error = usbd_open_pipe(sc->sc_iface, 0x81, 873 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 874 else 875 error = usbd_open_pipe(sc->sc_iface, 0x83, 876 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 877 if (error != 0) { 878 printf("%s: could not open Rx pipe: %s\n", 879 device_xname(sc->sc_dev), usbd_errstr(error)); 880 goto fail; 881 } 882 883 return (0); 884 fail: 885 (void)urtw_close_pipes(sc); 886 return (error); 887 } 888 889 int 890 urtw_alloc_rx_data_list(struct urtw_softc *sc) 891 { 892 int i, error; 893 894 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 895 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 896 897 data->sc = sc; 898 899 data->xfer = usbd_alloc_xfer(sc->sc_udev); 900 if (data->xfer == NULL) { 901 printf("%s: could not allocate rx xfer\n", 902 device_xname(sc->sc_dev)); 903 error = ENOMEM; 904 goto fail; 905 } 906 907 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 908 printf("%s: could not allocate rx buffer\n", 909 device_xname(sc->sc_dev)); 910 error = ENOMEM; 911 goto fail; 912 } 913 914 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 915 if (data->m == NULL) { 916 printf("%s: could not allocate rx mbuf\n", 917 device_xname(sc->sc_dev)); 918 error = ENOMEM; 919 goto fail; 920 } 921 MCLGET(data->m, M_DONTWAIT); 922 if (!(data->m->m_flags & M_EXT)) { 923 printf("%s: could not allocate rx mbuf cluster\n", 924 device_xname(sc->sc_dev)); 925 error = ENOMEM; 926 goto fail; 927 } 928 data->buf = mtod(data->m, uint8_t *); 929 } 930 931 return (0); 932 933 fail: 934 urtw_free_rx_data_list(sc); 935 return (error); 936 } 937 938 void 939 urtw_free_rx_data_list(struct urtw_softc *sc) 940 { 941 int i; 942 943 /* Make sure no transfers are pending. */ 944 if (sc->sc_rxpipe != NULL) 945 usbd_abort_pipe(sc->sc_rxpipe); 946 947 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 948 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 949 950 if (data->xfer != NULL) { 951 usbd_free_xfer(data->xfer); 952 data->xfer = NULL; 953 } 954 if (data->m != NULL) { 955 m_freem(data->m); 956 data->m = NULL; 957 } 958 } 959 } 960 961 int 962 urtw_alloc_tx_data_list(struct urtw_softc *sc) 963 { 964 int i, error; 965 966 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 967 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 968 969 data->sc = sc; 970 data->ni = NULL; 971 972 data->xfer = usbd_alloc_xfer(sc->sc_udev); 973 if (data->xfer == NULL) { 974 printf("%s: could not allocate tx xfer\n", 975 device_xname(sc->sc_dev)); 976 error = ENOMEM; 977 goto fail; 978 } 979 980 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 981 if (data->buf == NULL) { 982 printf("%s: could not allocate tx buffer\n", 983 device_xname(sc->sc_dev)); 984 error = ENOMEM; 985 goto fail; 986 } 987 988 if (((unsigned long)data->buf) % 4) 989 printf("%s: warn: unaligned buffer %p\n", 990 device_xname(sc->sc_dev), data->buf); 991 } 992 993 return (0); 994 995 fail: 996 urtw_free_tx_data_list(sc); 997 return (error); 998 } 999 1000 void 1001 urtw_free_tx_data_list(struct urtw_softc *sc) 1002 { 1003 int i; 1004 1005 /* Make sure no transfers are pending. */ 1006 if (sc->sc_txpipe_low != NULL) 1007 usbd_abort_pipe(sc->sc_txpipe_low); 1008 if (sc->sc_txpipe_normal != NULL) 1009 usbd_abort_pipe(sc->sc_txpipe_normal); 1010 1011 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1012 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 1013 1014 if (data->xfer != NULL) { 1015 usbd_free_xfer(data->xfer); 1016 data->xfer = NULL; 1017 } 1018 if (data->ni != NULL) { 1019 ieee80211_free_node(data->ni); 1020 data->ni = NULL; 1021 } 1022 } 1023 } 1024 1025 int 1026 urtw_media_change(struct ifnet *ifp) 1027 { 1028 int error; 1029 1030 error = ieee80211_media_change(ifp); 1031 if (error != ENETRESET) 1032 return (error); 1033 1034 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1035 (IFF_UP | IFF_RUNNING)) 1036 ifp->if_init(ifp); 1037 1038 return (0); 1039 } 1040 1041 int 1042 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1043 { 1044 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1045 1046 usb_rem_task(sc->sc_udev, &sc->sc_task); 1047 callout_stop(&sc->scan_to); 1048 1049 /* do it in a process context */ 1050 sc->sc_state = nstate; 1051 sc->sc_arg = arg; 1052 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1053 1054 return (0); 1055 } 1056 1057 usbd_status 1058 urtw_led_init(struct urtw_softc *sc) 1059 { 1060 uint32_t rev; 1061 usbd_status error; 1062 1063 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1064 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1065 if (error != 0) 1066 goto fail; 1067 1068 switch (rev & URTW_EPROM_CID_MASK) { 1069 case URTW_EPROM_CID_ALPHA0: 1070 sc->sc_strategy = URTW_SW_LED_MODE1; 1071 break; 1072 case URTW_EPROM_CID_SERCOMM_PS: 1073 sc->sc_strategy = URTW_SW_LED_MODE3; 1074 break; 1075 case URTW_EPROM_CID_HW_LED: 1076 sc->sc_strategy = URTW_HW_LED; 1077 break; 1078 case URTW_EPROM_CID_RSVD0: 1079 case URTW_EPROM_CID_RSVD1: 1080 default: 1081 sc->sc_strategy = URTW_SW_LED_MODE0; 1082 break; 1083 } 1084 1085 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1086 1087 fail: 1088 return (error); 1089 } 1090 1091 usbd_status 1092 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1093 uint16_t data) 1094 { 1095 usb_device_request_t req; 1096 1097 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1098 req.bRequest = URTW_8187_SETREGS_REQ; 1099 USETW(req.wValue, addr); 1100 USETW(req.wIndex, index); 1101 USETW(req.wLength, sizeof(uint16_t)); 1102 1103 return (usbd_do_request(sc->sc_udev, &req, &data)); 1104 } 1105 1106 usbd_status 1107 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1108 { 1109 int i; 1110 int16_t bit; 1111 uint8_t rlen = 12, wlen = 6; 1112 uint16_t o1, o2, o3, tmp; 1113 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1114 uint32_t mask = 0x80000000, value = 0; 1115 usbd_status error; 1116 1117 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1118 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1119 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1120 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1121 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1122 o1 &= ~0xf; 1123 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1124 DELAY(5); 1125 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1126 DELAY(5); 1127 1128 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1129 bit = ((d2w & mask) != 0) ? 1 : 0; 1130 1131 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1132 DELAY(2); 1133 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1134 URTW_BB_HOST_BANG_CLK); 1135 DELAY(2); 1136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1137 URTW_BB_HOST_BANG_CLK); 1138 DELAY(2); 1139 mask = mask >> 1; 1140 if (i == 2) 1141 break; 1142 bit = ((d2w & mask) != 0) ? 1 : 0; 1143 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1144 URTW_BB_HOST_BANG_CLK); 1145 DELAY(2); 1146 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1147 URTW_BB_HOST_BANG_CLK); 1148 DELAY(2); 1149 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1150 DELAY(1); 1151 } 1152 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1153 URTW_BB_HOST_BANG_CLK); 1154 DELAY(2); 1155 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1156 DELAY(2); 1157 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1158 DELAY(2); 1159 1160 mask = 0x800; 1161 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1162 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1163 o1 | URTW_BB_HOST_BANG_RW); 1164 DELAY(2); 1165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1166 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1167 DELAY(2); 1168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1169 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1170 DELAY(2); 1171 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1172 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1173 DELAY(2); 1174 1175 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1176 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1177 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1178 o1 | URTW_BB_HOST_BANG_RW); 1179 DELAY(2); 1180 } 1181 1182 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1183 URTW_BB_HOST_BANG_RW); 1184 DELAY(2); 1185 1186 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1187 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1188 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1189 1190 if (data != NULL) 1191 *data = value; 1192 fail: 1193 return (error); 1194 } 1195 1196 usbd_status 1197 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1198 { 1199 uint16_t d80, d82, d84; 1200 usbd_status error; 1201 1202 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1203 d80 &= 0xfff3; 1204 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1205 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1206 d84 &= 0xfff0; 1207 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1208 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1209 DELAY(10); 1210 1211 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1212 DELAY(2); 1213 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1214 DELAY(10); 1215 1216 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1217 if (error != 0) 1218 goto fail; 1219 1220 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1221 DELAY(10); 1222 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1223 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1224 usbd_delay_ms(sc->sc_udev, 2); 1225 fail: 1226 return (error); 1227 } 1228 1229 usbd_status 1230 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1231 { 1232 uint32_t data; 1233 usbd_status error; 1234 1235 *ret = 1; 1236 1237 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1238 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1239 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1240 usbd_delay_ms(sc->sc_udev, 500); 1241 1242 urtw_8225_write(sc, 0x0, 0x1b7); 1243 1244 error = urtw_8225_read(sc, 0x8, &data); 1245 if (error != 0) 1246 goto fail; 1247 if (data != 0x588) 1248 *ret = 0; 1249 else { 1250 error = urtw_8225_read(sc, 0x9, &data); 1251 if (error != 0) 1252 goto fail; 1253 if (data != 0x700) 1254 *ret = 0; 1255 } 1256 1257 urtw_8225_write(sc, 0x0, 0xb7); 1258 fail: 1259 return (error); 1260 } 1261 1262 usbd_status 1263 urtw_get_rfchip(struct urtw_softc *sc) 1264 { 1265 struct urtw_rf *rf = &sc->sc_rf; 1266 int ret; 1267 uint32_t data; 1268 usbd_status error; 1269 1270 rf->rf_sc = sc; 1271 1272 if (sc->sc_hwrev & URTW_HWREV_8187) { 1273 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1274 if (error != 0) 1275 panic("unsupported RF chip"); 1276 /* NOTREACHED */ 1277 switch (data & 0xff) { 1278 case URTW_EPROM_RFCHIPID_RTL8225U: 1279 error = urtw_8225_isv2(sc, &ret); 1280 if (error != 0) 1281 goto fail; 1282 if (ret == 0) { 1283 rf->init = urtw_8225_rf_init; 1284 rf->set_chan = urtw_8225_rf_set_chan; 1285 rf->set_sens = urtw_8225_rf_set_sens; 1286 printf(", RFv1"); 1287 } else { 1288 rf->init = urtw_8225v2_rf_init; 1289 rf->set_chan = urtw_8225v2_rf_set_chan; 1290 rf->set_sens = NULL; 1291 printf(", RFv2"); 1292 } 1293 break; 1294 default: 1295 goto fail; 1296 } 1297 } else { 1298 rf->init = urtw_8225v2_b_rf_init; 1299 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1300 rf->set_sens = NULL; 1301 } 1302 1303 rf->max_sens = URTW_8225_RF_MAX_SENS; 1304 rf->sens = URTW_8225_RF_DEF_SENS; 1305 1306 return (0); 1307 1308 fail: 1309 panic("unsupported RF chip %d", data & 0xff); 1310 /* NOTREACHED */ 1311 } 1312 1313 usbd_status 1314 urtw_get_txpwr(struct urtw_softc *sc) 1315 { 1316 int i, j; 1317 uint32_t data; 1318 usbd_status error; 1319 1320 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1321 if (error != 0) 1322 goto fail; 1323 sc->sc_txpwr_cck_base = data & 0xf; 1324 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1325 1326 for (i = 1, j = 0; i < 6; i += 2, j++) { 1327 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1328 if (error != 0) 1329 goto fail; 1330 sc->sc_txpwr_cck[i] = data & 0xf; 1331 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1332 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1333 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1334 } 1335 for (i = 1, j = 0; i < 4; i += 2, j++) { 1336 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1337 if (error != 0) 1338 goto fail; 1339 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1340 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1341 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1342 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1343 } 1344 if (sc->sc_hwrev & URTW_HWREV_8187) { 1345 for (i = 1, j = 0; i < 4; i += 2, j++) { 1346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1347 &data); 1348 if (error != 0) 1349 goto fail; 1350 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1351 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1352 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1353 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1354 (data & 0xf000) >> 12; 1355 } 1356 } else { 1357 /* Channel 11. */ 1358 error = urtw_eprom_read32(sc, 0x1b, &data); 1359 if (error != 0) 1360 goto fail; 1361 sc->sc_txpwr_cck[11] = data & 0xf; 1362 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1363 1364 /* Channel 12. */ 1365 error = urtw_eprom_read32(sc, 0xa, &data); 1366 if (error != 0) 1367 goto fail; 1368 sc->sc_txpwr_cck[12] = data & 0xf; 1369 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1370 1371 /* Channel 13, 14. */ 1372 error = urtw_eprom_read32(sc, 0x1c, &data); 1373 if (error != 0) 1374 goto fail; 1375 sc->sc_txpwr_cck[13] = data & 0xf; 1376 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1377 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1378 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1379 } 1380 fail: 1381 return (error); 1382 } 1383 1384 usbd_status 1385 urtw_get_macaddr(struct urtw_softc *sc) 1386 { 1387 struct ieee80211com *ic = &sc->sc_ic; 1388 usbd_status error; 1389 uint32_t data; 1390 1391 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1392 if (error != 0) 1393 goto fail; 1394 ic->ic_myaddr[0] = data & 0xff; 1395 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1396 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1397 if (error != 0) 1398 goto fail; 1399 ic->ic_myaddr[2] = data & 0xff; 1400 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1401 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1402 if (error != 0) 1403 goto fail; 1404 ic->ic_myaddr[4] = data & 0xff; 1405 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1406 fail: 1407 return (error); 1408 } 1409 1410 usbd_status 1411 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1412 { 1413 #define URTW_READCMD_LEN 3 1414 int addrlen, i; 1415 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1416 usbd_status error; 1417 1418 /* NB: make sure the buffer is initialized */ 1419 *data = 0; 1420 1421 /* enable EPROM programming */ 1422 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1423 DELAY(URTW_EPROM_DELAY); 1424 1425 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1426 if (error != 0) 1427 goto fail; 1428 error = urtw_eprom_ck(sc); 1429 if (error != 0) 1430 goto fail; 1431 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1432 if (error != 0) 1433 goto fail; 1434 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1435 addrlen = 8; 1436 addrstr[0] = addr & (1 << 7); 1437 addrstr[1] = addr & (1 << 6); 1438 addrstr[2] = addr & (1 << 5); 1439 addrstr[3] = addr & (1 << 4); 1440 addrstr[4] = addr & (1 << 3); 1441 addrstr[5] = addr & (1 << 2); 1442 addrstr[6] = addr & (1 << 1); 1443 addrstr[7] = addr & (1 << 0); 1444 } else { 1445 addrlen=6; 1446 addrstr[0] = addr & (1 << 5); 1447 addrstr[1] = addr & (1 << 4); 1448 addrstr[2] = addr & (1 << 3); 1449 addrstr[3] = addr & (1 << 2); 1450 addrstr[4] = addr & (1 << 1); 1451 addrstr[5] = addr & (1 << 0); 1452 } 1453 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1454 if (error != 0) 1455 goto fail; 1456 1457 error = urtw_eprom_writebit(sc, 0); 1458 if (error != 0) 1459 goto fail; 1460 1461 for (i = 0; i < 16; i++) { 1462 error = urtw_eprom_ck(sc); 1463 if (error != 0) 1464 goto fail; 1465 error = urtw_eprom_readbit(sc, &data16); 1466 if (error != 0) 1467 goto fail; 1468 1469 (*data) |= (data16 << (15 - i)); 1470 } 1471 1472 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1473 if (error != 0) 1474 goto fail; 1475 error = urtw_eprom_ck(sc); 1476 if (error != 0) 1477 goto fail; 1478 1479 /* now disable EPROM programming */ 1480 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1481 fail: 1482 return (error); 1483 #undef URTW_READCMD_LEN 1484 } 1485 1486 usbd_status 1487 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1488 { 1489 uint8_t data8; 1490 usbd_status error; 1491 1492 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1493 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1494 DELAY(URTW_EPROM_DELAY); 1495 1496 fail: 1497 return (error); 1498 } 1499 1500 usbd_status 1501 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1502 { 1503 int i = 0; 1504 usbd_status error = 0; 1505 1506 for (i = 0; i < buflen; i++) { 1507 error = urtw_eprom_writebit(sc, buf[i]); 1508 if (error != 0) 1509 goto fail; 1510 error = urtw_eprom_ck(sc); 1511 if (error != 0) 1512 goto fail; 1513 } 1514 fail: 1515 return (error); 1516 } 1517 1518 usbd_status 1519 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1520 { 1521 uint8_t data; 1522 usbd_status error; 1523 1524 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1525 if (bit != 0) 1526 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1527 else 1528 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1529 DELAY(URTW_EPROM_DELAY); 1530 fail: 1531 return (error); 1532 } 1533 1534 usbd_status 1535 urtw_eprom_ck(struct urtw_softc *sc) 1536 { 1537 uint8_t data; 1538 usbd_status error; 1539 1540 /* masking */ 1541 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1542 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1543 DELAY(URTW_EPROM_DELAY); 1544 /* unmasking */ 1545 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1546 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1547 DELAY(URTW_EPROM_DELAY); 1548 fail: 1549 return (error); 1550 } 1551 1552 usbd_status 1553 urtw_eprom_cs(struct urtw_softc *sc, int able) 1554 { 1555 uint8_t data; 1556 usbd_status error; 1557 1558 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1559 if (able == URTW_EPROM_ENABLE) 1560 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1561 else 1562 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1563 DELAY(URTW_EPROM_DELAY); 1564 fail: 1565 return (error); 1566 } 1567 1568 usbd_status 1569 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1570 { 1571 usb_device_request_t req; 1572 usbd_status error; 1573 1574 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1575 req.bRequest = URTW_8187_GETREGS_REQ; 1576 USETW(req.wValue, val | 0xff00); 1577 USETW(req.wIndex, idx & 0x03); 1578 USETW(req.wLength, sizeof(uint8_t)); 1579 1580 error = usbd_do_request(sc->sc_udev, &req, data); 1581 return (error); 1582 } 1583 1584 usbd_status 1585 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1586 { 1587 usb_device_request_t req; 1588 usbd_status error; 1589 1590 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1591 req.bRequest = URTW_8187_GETREGS_REQ; 1592 USETW(req.wValue, val | 0xfe00); 1593 USETW(req.wIndex, 0); 1594 USETW(req.wLength, sizeof(uint8_t)); 1595 1596 error = usbd_do_request(sc->sc_udev, &req, data); 1597 return (error); 1598 } 1599 1600 usbd_status 1601 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1602 { 1603 usb_device_request_t req; 1604 usbd_status error; 1605 1606 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1607 req.bRequest = URTW_8187_GETREGS_REQ; 1608 USETW(req.wValue, val | 0xff00); 1609 USETW(req.wIndex, idx & 0x03); 1610 USETW(req.wLength, sizeof(uint16_t)); 1611 1612 error = usbd_do_request(sc->sc_udev, &req, data); 1613 return (error); 1614 } 1615 1616 usbd_status 1617 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1618 { 1619 usb_device_request_t req; 1620 usbd_status error; 1621 1622 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1623 req.bRequest = URTW_8187_GETREGS_REQ; 1624 USETW(req.wValue, val | 0xff00); 1625 USETW(req.wIndex, idx & 0x03); 1626 USETW(req.wLength, sizeof(uint32_t)); 1627 1628 error = usbd_do_request(sc->sc_udev, &req, data); 1629 return (error); 1630 } 1631 1632 usbd_status 1633 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1634 { 1635 usb_device_request_t req; 1636 1637 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1638 req.bRequest = URTW_8187_SETREGS_REQ; 1639 USETW(req.wValue, val | 0xff00); 1640 USETW(req.wIndex, idx & 0x03); 1641 USETW(req.wLength, sizeof(uint8_t)); 1642 1643 return (usbd_do_request(sc->sc_udev, &req, &data)); 1644 } 1645 1646 usbd_status 1647 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1648 { 1649 usb_device_request_t req; 1650 1651 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1652 req.bRequest = URTW_8187_SETREGS_REQ; 1653 USETW(req.wValue, val | 0xfe00); 1654 USETW(req.wIndex, 0); 1655 USETW(req.wLength, sizeof(uint8_t)); 1656 1657 return (usbd_do_request(sc->sc_udev, &req, &data)); 1658 } 1659 1660 usbd_status 1661 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1662 { 1663 usb_device_request_t req; 1664 1665 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1666 req.bRequest = URTW_8187_SETREGS_REQ; 1667 USETW(req.wValue, val | 0xff00); 1668 USETW(req.wIndex, idx & 0x03); 1669 USETW(req.wLength, sizeof(uint16_t)); 1670 1671 return (usbd_do_request(sc->sc_udev, &req, &data)); 1672 } 1673 1674 usbd_status 1675 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1676 { 1677 usb_device_request_t req; 1678 1679 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1680 req.bRequest = URTW_8187_SETREGS_REQ; 1681 USETW(req.wValue, val | 0xff00); 1682 USETW(req.wIndex, idx & 0x03); 1683 USETW(req.wLength, sizeof(uint32_t)); 1684 1685 return (usbd_do_request(sc->sc_udev, &req, &data)); 1686 } 1687 1688 static usbd_status 1689 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1690 { 1691 uint8_t data; 1692 usbd_status error; 1693 1694 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1695 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1696 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1697 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1698 fail: 1699 return (error); 1700 } 1701 1702 usbd_status 1703 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1704 { 1705 uint8_t data; 1706 usbd_status error; 1707 1708 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1709 if (error) 1710 goto fail; 1711 1712 urtw_read8_m(sc, URTW_CONFIG3, &data); 1713 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1714 urtw_write32_m(sc, URTW_ANAPARAM, val); 1715 urtw_read8_m(sc, URTW_CONFIG3, &data); 1716 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1717 1718 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1719 if (error) 1720 goto fail; 1721 fail: 1722 return (error); 1723 } 1724 1725 usbd_status 1726 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1727 { 1728 uint8_t data; 1729 usbd_status error; 1730 1731 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1732 if (error) 1733 goto fail; 1734 1735 urtw_read8_m(sc, URTW_CONFIG3, &data); 1736 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1737 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1738 urtw_read8_m(sc, URTW_CONFIG3, &data); 1739 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1740 1741 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1742 if (error) 1743 goto fail; 1744 fail: 1745 return (error); 1746 } 1747 1748 usbd_status 1749 urtw_intr_disable(struct urtw_softc *sc) 1750 { 1751 usbd_status error; 1752 1753 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1754 1755 fail: 1756 return (error); 1757 } 1758 1759 usbd_status 1760 urtw_reset(struct urtw_softc *sc) 1761 { 1762 uint8_t data; 1763 usbd_status error; 1764 1765 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1766 if (error) 1767 goto fail; 1768 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1769 if (error) 1770 goto fail; 1771 1772 error = urtw_intr_disable(sc); 1773 if (error) 1774 goto fail; 1775 usbd_delay_ms(sc->sc_udev, 100); 1776 1777 error = urtw_write8e(sc, 0x18, 0x10); 1778 if (error != 0) 1779 goto fail; 1780 error = urtw_write8e(sc, 0x18, 0x11); 1781 if (error != 0) 1782 goto fail; 1783 error = urtw_write8e(sc, 0x18, 0x00); 1784 if (error != 0) 1785 goto fail; 1786 usbd_delay_ms(sc->sc_udev, 100); 1787 1788 urtw_read8_m(sc, URTW_CMD, &data); 1789 data = (data & 2) | URTW_CMD_RST; 1790 urtw_write8_m(sc, URTW_CMD, data); 1791 usbd_delay_ms(sc->sc_udev, 100); 1792 1793 urtw_read8_m(sc, URTW_CMD, &data); 1794 if (data & URTW_CMD_RST) { 1795 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1796 goto fail; 1797 } 1798 1799 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1800 if (error) 1801 goto fail; 1802 usbd_delay_ms(sc->sc_udev, 100); 1803 1804 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1805 if (error) 1806 goto fail; 1807 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1808 if (error) 1809 goto fail; 1810 fail: 1811 return (error); 1812 } 1813 1814 usbd_status 1815 urtw_led_on(struct urtw_softc *sc, int type) 1816 { 1817 usbd_status error; 1818 1819 if (type == URTW_LED_GPIO) { 1820 switch (sc->sc_gpio_ledpin) { 1821 case URTW_LED_PIN_GPIO0: 1822 urtw_write8_m(sc, URTW_GPIO, 0x01); 1823 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1824 break; 1825 default: 1826 panic("unsupported LED PIN type 0x%x", 1827 sc->sc_gpio_ledpin); 1828 /* NOTREACHED */ 1829 } 1830 } else { 1831 panic("unsupported LED type 0x%x", type); 1832 /* NOTREACHED */ 1833 } 1834 1835 sc->sc_gpio_ledon = 1; 1836 fail: 1837 return (error); 1838 } 1839 1840 static usbd_status 1841 urtw_led_off(struct urtw_softc *sc, int type) 1842 { 1843 usbd_status error; 1844 1845 if (type == URTW_LED_GPIO) { 1846 switch (sc->sc_gpio_ledpin) { 1847 case URTW_LED_PIN_GPIO0: 1848 urtw_write8_m(sc, URTW_GPIO, 0x01); 1849 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1850 break; 1851 default: 1852 panic("unsupported LED PIN type 0x%x", 1853 sc->sc_gpio_ledpin); 1854 /* NOTREACHED */ 1855 } 1856 } else { 1857 panic("unsupported LED type 0x%x", type); 1858 /* NOTREACHED */ 1859 } 1860 1861 sc->sc_gpio_ledon = 0; 1862 1863 fail: 1864 return (error); 1865 } 1866 1867 usbd_status 1868 urtw_led_mode0(struct urtw_softc *sc, int mode) 1869 { 1870 switch (mode) { 1871 case URTW_LED_CTL_POWER_ON: 1872 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1873 break; 1874 case URTW_LED_CTL_TX: 1875 if (sc->sc_gpio_ledinprogress == 1) 1876 return (0); 1877 1878 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1879 sc->sc_gpio_blinktime = 2; 1880 break; 1881 case URTW_LED_CTL_LINK: 1882 sc->sc_gpio_ledstate = URTW_LED_ON; 1883 break; 1884 default: 1885 panic("unsupported LED mode 0x%x", mode); 1886 /* NOTREACHED */ 1887 } 1888 1889 switch (sc->sc_gpio_ledstate) { 1890 case URTW_LED_ON: 1891 if (sc->sc_gpio_ledinprogress != 0) 1892 break; 1893 urtw_led_on(sc, URTW_LED_GPIO); 1894 break; 1895 case URTW_LED_BLINK_NORMAL: 1896 if (sc->sc_gpio_ledinprogress != 0) 1897 break; 1898 sc->sc_gpio_ledinprogress = 1; 1899 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1900 URTW_LED_OFF : URTW_LED_ON; 1901 if (!sc->sc_dying) 1902 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1903 break; 1904 case URTW_LED_POWER_ON_BLINK: 1905 urtw_led_on(sc, URTW_LED_GPIO); 1906 usbd_delay_ms(sc->sc_udev, 100); 1907 urtw_led_off(sc, URTW_LED_GPIO); 1908 break; 1909 default: 1910 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 1911 /* NOTREACHED */ 1912 } 1913 return (0); 1914 } 1915 1916 usbd_status 1917 urtw_led_mode1(struct urtw_softc *sc, int mode) 1918 { 1919 return (USBD_INVAL); 1920 } 1921 1922 usbd_status 1923 urtw_led_mode2(struct urtw_softc *sc, int mode) 1924 { 1925 return (USBD_INVAL); 1926 } 1927 1928 usbd_status 1929 urtw_led_mode3(struct urtw_softc *sc, int mode) 1930 { 1931 return (USBD_INVAL); 1932 } 1933 1934 void 1935 urtw_ledusbtask(void *arg) 1936 { 1937 struct urtw_softc *sc = arg; 1938 1939 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1940 panic("could not process a LED strategy 0x%x", sc->sc_strategy); 1941 1942 urtw_led_blink(sc); 1943 } 1944 1945 void 1946 urtw_ledtask(void *arg) 1947 { 1948 struct urtw_softc *sc = arg; 1949 1950 /* 1951 * NB: to change a status of the led we need at least a sleep so we 1952 * can't do it here 1953 */ 1954 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1955 } 1956 1957 usbd_status 1958 urtw_led_ctl(struct urtw_softc *sc, int mode) 1959 { 1960 usbd_status error = 0; 1961 1962 switch (sc->sc_strategy) { 1963 case URTW_SW_LED_MODE0: 1964 error = urtw_led_mode0(sc, mode); 1965 break; 1966 case URTW_SW_LED_MODE1: 1967 error = urtw_led_mode1(sc, mode); 1968 break; 1969 case URTW_SW_LED_MODE2: 1970 error = urtw_led_mode2(sc, mode); 1971 break; 1972 case URTW_SW_LED_MODE3: 1973 error = urtw_led_mode3(sc, mode); 1974 break; 1975 default: 1976 panic("unsupported LED mode %d", sc->sc_strategy); 1977 /* NOTREACHED */ 1978 } 1979 1980 return (error); 1981 } 1982 1983 usbd_status 1984 urtw_led_blink(struct urtw_softc *sc) 1985 { 1986 uint8_t ing = 0; 1987 usbd_status error; 1988 1989 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1990 error = urtw_led_on(sc, URTW_LED_GPIO); 1991 else 1992 error = urtw_led_off(sc, URTW_LED_GPIO); 1993 sc->sc_gpio_blinktime--; 1994 if (sc->sc_gpio_blinktime == 0) 1995 ing = 1; 1996 else { 1997 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1998 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1999 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 2000 ing = 1; 2001 } 2002 if (ing == 1) { 2003 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2004 sc->sc_gpio_ledon == 0) 2005 error = urtw_led_on(sc, URTW_LED_GPIO); 2006 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2007 sc->sc_gpio_ledon == 1) 2008 error = urtw_led_off(sc, URTW_LED_GPIO); 2009 2010 sc->sc_gpio_blinktime = 0; 2011 sc->sc_gpio_ledinprogress = 0; 2012 return (0); 2013 } 2014 2015 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2016 URTW_LED_ON : URTW_LED_OFF; 2017 2018 switch (sc->sc_gpio_ledstate) { 2019 case URTW_LED_BLINK_NORMAL: 2020 if (!sc->sc_dying) 2021 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2022 break; 2023 default: 2024 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 2025 /* NOTREACHED */ 2026 } 2027 return (0); 2028 } 2029 2030 usbd_status 2031 urtw_update_msr(struct urtw_softc *sc) 2032 { 2033 struct ieee80211com *ic = &sc->sc_ic; 2034 uint8_t data; 2035 usbd_status error; 2036 2037 urtw_read8_m(sc, URTW_MSR, &data); 2038 data &= ~URTW_MSR_LINK_MASK; 2039 2040 /* Should always be set. */ 2041 if (sc->sc_hwrev & URTW_HWREV_8187B) 2042 data |= URTW_MSR_LINK_ENEDCA; 2043 2044 if (sc->sc_state == IEEE80211_S_RUN) { 2045 switch (ic->ic_opmode) { 2046 case IEEE80211_M_STA: 2047 case IEEE80211_M_MONITOR: 2048 data |= URTW_MSR_LINK_STA; 2049 break; 2050 default: 2051 panic("unsupported operation mode 0x%x", 2052 ic->ic_opmode); 2053 /* NOTREACHED */ 2054 } 2055 } else 2056 data |= URTW_MSR_LINK_NONE; 2057 2058 urtw_write8_m(sc, URTW_MSR, data); 2059 fail: 2060 return (error); 2061 } 2062 2063 uint16_t 2064 urtw_rate2rtl(int rate) 2065 { 2066 unsigned int i; 2067 2068 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2069 if (rate == urtw_ratetable[i].reg) 2070 return (urtw_ratetable[i].val); 2071 } 2072 2073 return (3); 2074 } 2075 2076 uint16_t 2077 urtw_rtl2rate(int rate) 2078 { 2079 unsigned int i; 2080 2081 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2082 if (rate == urtw_ratetable[i].val) 2083 return (urtw_ratetable[i].reg); 2084 } 2085 2086 return (0); 2087 } 2088 2089 usbd_status 2090 urtw_set_rate(struct urtw_softc *sc) 2091 { 2092 int i, basic_rate, min_rr_rate, max_rr_rate; 2093 uint16_t data; 2094 usbd_status error; 2095 2096 basic_rate = urtw_rate2rtl(48); 2097 min_rr_rate = urtw_rate2rtl(12); 2098 max_rr_rate = urtw_rate2rtl(48); 2099 2100 urtw_write8_m(sc, URTW_RESP_RATE, 2101 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2102 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2103 2104 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2105 data &= ~URTW_BRSR_MBR_8185; 2106 2107 for (i = 0; i <= basic_rate; i++) 2108 data |= (1 << i); 2109 2110 urtw_write16_m(sc, URTW_8187_BRSR, data); 2111 fail: 2112 return (error); 2113 } 2114 2115 usbd_status 2116 urtw_intr_enable(struct urtw_softc *sc) 2117 { 2118 usbd_status error; 2119 2120 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2121 fail: 2122 return (error); 2123 } 2124 2125 usbd_status 2126 urtw_rx_setconf(struct urtw_softc *sc) 2127 { 2128 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2129 struct ieee80211com *ic = &sc->sc_ic; 2130 uint32_t data; 2131 usbd_status error; 2132 2133 urtw_read32_m(sc, URTW_RX, &data); 2134 data = data &~ URTW_RX_FILTER_MASK; 2135 #if 0 2136 data = data | URTW_RX_FILTER_CTL; 2137 #endif 2138 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2139 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2140 2141 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2142 data = data | URTW_RX_FILTER_ICVERR; 2143 data = data | URTW_RX_FILTER_PWR; 2144 } 2145 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2146 data = data | URTW_RX_FILTER_CRCERR; 2147 2148 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2149 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2150 data = data | URTW_RX_FILTER_ALLMAC; 2151 } else { 2152 data = data | URTW_RX_FILTER_NICMAC; 2153 data = data | URTW_RX_CHECK_BSSID; 2154 } 2155 2156 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2157 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2158 data = data &~ URTW_MAX_RX_DMA_MASK; 2159 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2160 2161 urtw_write32_m(sc, URTW_RX, data); 2162 fail: 2163 return (error); 2164 } 2165 2166 usbd_status 2167 urtw_rx_enable(struct urtw_softc *sc) 2168 { 2169 int i; 2170 struct urtw_rx_data *rx_data; 2171 uint8_t data; 2172 usbd_status error; 2173 2174 /* 2175 * Start up the receive pipe. 2176 */ 2177 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2178 rx_data = &sc->sc_rx_data[i]; 2179 2180 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2181 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2182 USBD_NO_TIMEOUT, urtw_rxeof); 2183 error = usbd_transfer(rx_data->xfer); 2184 if (error != USBD_IN_PROGRESS && error != 0) { 2185 printf("%s: could not queue Rx transfer\n", 2186 device_xname(sc->sc_dev)); 2187 goto fail; 2188 } 2189 } 2190 2191 error = urtw_rx_setconf(sc); 2192 if (error != 0) 2193 goto fail; 2194 2195 urtw_read8_m(sc, URTW_CMD, &data); 2196 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2197 fail: 2198 return (error); 2199 } 2200 2201 usbd_status 2202 urtw_tx_enable(struct urtw_softc *sc) 2203 { 2204 uint8_t data8; 2205 uint32_t data; 2206 usbd_status error; 2207 2208 if (sc->sc_hwrev & URTW_HWREV_8187) { 2209 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2210 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2211 URTW_CW_CONF_PERPACKET_RETRY); 2212 urtw_write8_m(sc, URTW_CW_CONF, data8); 2213 2214 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2215 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2216 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2217 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2218 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2219 2220 urtw_read32_m(sc, URTW_TX_CONF, &data); 2221 data &= ~URTW_TX_LOOPBACK_MASK; 2222 data |= URTW_TX_LOOPBACK_NONE; 2223 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2224 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2225 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2226 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2227 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2228 data &= ~URTW_TX_SWPLCPLEN; 2229 data |= URTW_TX_NOICV; 2230 urtw_write32_m(sc, URTW_TX_CONF, data); 2231 } else { 2232 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2233 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2234 URTW_TX_LONGRETRY; 2235 urtw_write32_m(sc, URTW_TX_CONF, data); 2236 } 2237 2238 urtw_read8_m(sc, URTW_CMD, &data8); 2239 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2240 fail: 2241 return (error); 2242 } 2243 2244 int 2245 urtw_init(struct ifnet *ifp) 2246 { 2247 struct urtw_softc *sc = ifp->if_softc; 2248 struct urtw_rf *rf = &sc->sc_rf; 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 usbd_status error; 2251 int ret; 2252 2253 urtw_stop(ifp, 0); 2254 2255 error = urtw_reset(sc); 2256 if (error) 2257 goto fail; 2258 2259 urtw_write8_m(sc, 0x85, 0); 2260 urtw_write8_m(sc, URTW_GPIO, 0); 2261 2262 /* for led */ 2263 urtw_write8_m(sc, 0x85, 4); 2264 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2265 if (error != 0) 2266 goto fail; 2267 2268 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2269 if (error) 2270 goto fail; 2271 2272 /* applying MAC address again. */ 2273 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2274 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2275 if (error) 2276 goto fail; 2277 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2278 if (error) 2279 goto fail; 2280 2281 error = urtw_update_msr(sc); 2282 if (error) 2283 goto fail; 2284 2285 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2286 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2287 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2288 error = urtw_set_rate(sc); 2289 if (error != 0) 2290 goto fail; 2291 2292 error = rf->init(rf); 2293 if (error != 0) 2294 goto fail; 2295 if (rf->set_sens != NULL) 2296 rf->set_sens(rf); 2297 2298 urtw_write16_m(sc, 0x5e, 1); 2299 urtw_write16_m(sc, 0xfe, 0x10); 2300 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2301 urtw_write8_m(sc, 0xff, 0x60); 2302 urtw_write16_m(sc, 0x5e, 0); 2303 urtw_write8_m(sc, 0x85, 4); 2304 2305 error = urtw_intr_enable(sc); 2306 if (error != 0) 2307 goto fail; 2308 2309 /* reset softc variables */ 2310 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2311 sc->sc_txtimer = 0; 2312 2313 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2314 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2315 if (error != 0) { 2316 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2317 ", err=%s\n", usbd_errstr(error)); 2318 goto fail; 2319 } 2320 /* get the first interface handle */ 2321 error = usbd_device2interface_handle(sc->sc_udev, 2322 URTW_IFACE_INDEX, &sc->sc_iface); 2323 if (error != 0) { 2324 printf("%s: could not get interface handle\n", 2325 device_xname(sc->sc_dev)); 2326 goto fail; 2327 } 2328 error = urtw_open_pipes(sc); 2329 if (error != 0) 2330 goto fail; 2331 ret = urtw_alloc_rx_data_list(sc); 2332 if (error != 0) 2333 goto fail; 2334 ret = urtw_alloc_tx_data_list(sc); 2335 if (error != 0) 2336 goto fail; 2337 sc->sc_flags |= URTW_INIT_ONCE; 2338 } 2339 2340 error = urtw_rx_enable(sc); 2341 if (error != 0) 2342 goto fail; 2343 error = urtw_tx_enable(sc); 2344 if (error != 0) 2345 goto fail; 2346 2347 ifp->if_flags &= ~IFF_OACTIVE; 2348 ifp->if_flags |= IFF_RUNNING; 2349 2350 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2351 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2352 else 2353 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2354 2355 return (0); 2356 fail: 2357 return (error); 2358 } 2359 2360 int 2361 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2362 { 2363 #define IS_RUNNING(ifp) \ 2364 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2365 2366 struct urtw_softc *sc = ifp->if_softc; 2367 struct ieee80211com *ic = &sc->sc_ic; 2368 int s, error = 0; 2369 2370 if (sc->sc_dying) 2371 return (ENXIO); 2372 2373 s = splnet(); 2374 2375 switch (cmd) { 2376 case SIOCSIFFLAGS: 2377 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2378 break; 2379 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2380 case IFF_UP|IFF_RUNNING: 2381 break; 2382 case IFF_UP: 2383 ifp->if_init(ifp); 2384 break; 2385 case IFF_RUNNING: 2386 urtw_stop(ifp, 1); 2387 break; 2388 case 0: 2389 break; 2390 } 2391 break; 2392 2393 case SIOCADDMULTI: 2394 case SIOCDELMULTI: 2395 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2396 error = 0; 2397 break; 2398 2399 default: 2400 error = ieee80211_ioctl(ic, cmd, data); 2401 break; 2402 } 2403 2404 if (error == ENETRESET) { 2405 if (IS_RUNNING(ifp) && 2406 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2407 ifp->if_init(ifp); 2408 error = 0; 2409 } 2410 2411 splx(s); 2412 2413 return (error); 2414 #undef IS_RUNNING 2415 } 2416 2417 void 2418 urtw_start(struct ifnet *ifp) 2419 { 2420 struct urtw_softc *sc = ifp->if_softc; 2421 struct ieee80211com *ic = &sc->sc_ic; 2422 struct ieee80211_node *ni; 2423 struct ether_header *eh; 2424 struct mbuf *m0; 2425 2426 /* 2427 * net80211 may still try to send management frames even if the 2428 * IFF_RUNNING flag is not set... 2429 */ 2430 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2431 return; 2432 2433 for (;;) { 2434 IF_POLL(&ic->ic_mgtq, m0); 2435 if (m0 != NULL) { 2436 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2437 sc->sc_tx_normal_queued >= 2438 URTW_TX_DATA_LIST_COUNT) { 2439 ifp->if_flags |= IFF_OACTIVE; 2440 break; 2441 } 2442 IF_DEQUEUE(&ic->ic_mgtq, m0); 2443 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2444 m0->m_pkthdr.rcvif = NULL; 2445 bpf_mtap3(ic->ic_rawbpf, m0); 2446 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2447 != 0) 2448 break; 2449 } else { 2450 if (ic->ic_state != IEEE80211_S_RUN) 2451 break; 2452 IFQ_POLL(&ifp->if_snd, m0); 2453 if (m0 == NULL) 2454 break; 2455 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2456 sc->sc_tx_normal_queued >= 2457 URTW_TX_DATA_LIST_COUNT) { 2458 ifp->if_flags |= IFF_OACTIVE; 2459 break; 2460 } 2461 IFQ_DEQUEUE(&ifp->if_snd, m0); 2462 if (m0->m_len < sizeof(struct ether_header) && 2463 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2464 continue; 2465 2466 eh = mtod(m0, struct ether_header *); 2467 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2468 if (ni == NULL) { 2469 m_freem(m0); 2470 continue; 2471 } 2472 bpf_mtap(ifp, m0); 2473 m0 = ieee80211_encap(ic, m0, ni); 2474 if (m0 == NULL) { 2475 ieee80211_free_node(ni); 2476 continue; 2477 } 2478 bpf_mtap3(ic->ic_rawbpf, m0); 2479 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2480 != 0) { 2481 ieee80211_free_node(ni); 2482 ifp->if_oerrors++; 2483 break; 2484 } 2485 } 2486 sc->sc_txtimer = 5; 2487 ifp->if_timer = 1; 2488 } 2489 } 2490 2491 void 2492 urtw_watchdog(struct ifnet *ifp) 2493 { 2494 struct urtw_softc *sc = ifp->if_softc; 2495 2496 ifp->if_timer = 0; 2497 2498 if (sc->sc_txtimer > 0) { 2499 if (--sc->sc_txtimer == 0) { 2500 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2501 ifp->if_oerrors++; 2502 return; 2503 } 2504 ifp->if_timer = 1; 2505 } 2506 2507 ieee80211_watchdog(&sc->sc_ic); 2508 } 2509 2510 void 2511 urtw_txeof_low(usbd_xfer_handle xfer, usbd_private_handle priv, 2512 usbd_status status) 2513 { 2514 struct urtw_tx_data *data = priv; 2515 struct urtw_softc *sc = data->sc; 2516 struct ieee80211com *ic = &sc->sc_ic; 2517 struct ifnet *ifp = ic->ic_ifp; 2518 int s; 2519 2520 if (status != USBD_NORMAL_COMPLETION) { 2521 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2522 return; 2523 2524 printf("%s: could not transmit buffer: %s\n", 2525 device_xname(sc->sc_dev), usbd_errstr(status)); 2526 2527 if (status == USBD_STALLED) 2528 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2529 2530 ifp->if_oerrors++; 2531 return; 2532 } 2533 2534 s = splnet(); 2535 2536 ieee80211_free_node(data->ni); 2537 data->ni = NULL; 2538 2539 sc->sc_txtimer = 0; 2540 ifp->if_opackets++; 2541 2542 sc->sc_tx_low_queued--; 2543 ifp->if_flags &= ~IFF_OACTIVE; 2544 urtw_start(ifp); 2545 2546 splx(s); 2547 } 2548 2549 void 2550 urtw_txeof_normal(usbd_xfer_handle xfer, usbd_private_handle priv, 2551 usbd_status status) 2552 { 2553 struct urtw_tx_data *data = priv; 2554 struct urtw_softc *sc = data->sc; 2555 struct ieee80211com *ic = &sc->sc_ic; 2556 struct ifnet *ifp = ic->ic_ifp; 2557 int s; 2558 2559 if (status != USBD_NORMAL_COMPLETION) { 2560 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2561 return; 2562 2563 printf("%s: could not transmit buffer: %s\n", 2564 device_xname(sc->sc_dev), usbd_errstr(status)); 2565 2566 if (status == USBD_STALLED) 2567 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2568 2569 ifp->if_oerrors++; 2570 return; 2571 } 2572 2573 s = splnet(); 2574 2575 ieee80211_free_node(data->ni); 2576 data->ni = NULL; 2577 2578 sc->sc_txtimer = 0; 2579 ifp->if_opackets++; 2580 2581 sc->sc_tx_normal_queued--; 2582 ifp->if_flags &= ~IFF_OACTIVE; 2583 urtw_start(ifp); 2584 2585 splx(s); 2586 } 2587 2588 int 2589 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2590 int prior) 2591 { 2592 struct ieee80211com *ic = &sc->sc_ic; 2593 struct urtw_tx_data *data; 2594 struct ieee80211_frame *wh; 2595 struct ieee80211_key *k; 2596 usbd_status error; 2597 int xferlen; 2598 2599 wh = mtod(m0, struct ieee80211_frame *); 2600 2601 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2602 k = ieee80211_crypto_encap(ic, ni, m0); 2603 if (k == NULL) { 2604 m_freem(m0); 2605 return (ENOBUFS); 2606 } 2607 /* packet header may have moved, reset our local pointer */ 2608 wh = mtod(m0, struct ieee80211_frame *); 2609 } 2610 2611 if (sc->sc_drvbpf != NULL) { 2612 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2613 2614 tap->wt_flags = 0; 2615 tap->wt_rate = 0; 2616 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2617 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2618 2619 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 2620 } 2621 2622 if (sc->sc_hwrev & URTW_HWREV_8187) 2623 xferlen = m0->m_pkthdr.len + 4 * 3; 2624 else 2625 xferlen = m0->m_pkthdr.len + 4 * 8; 2626 2627 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2628 xferlen += 1; 2629 2630 data = &sc->sc_tx_data[sc->sc_txidx]; 2631 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2632 2633 bzero(data->buf, URTW_TX_MAXSIZE); 2634 data->buf[0] = m0->m_pkthdr.len & 0xff; 2635 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2636 data->buf[1] |= (1 << 7); 2637 2638 /* XXX sc_preamble_mode is always 2. */ 2639 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2640 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2641 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2642 data->buf[2] |= 1; 2643 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2644 prior == URTW_PRIORITY_LOW) 2645 panic("TODO tx."); 2646 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2647 data->buf[2] |= (1 << 1); 2648 /* RTS rate - 10 means we use a basic rate. */ 2649 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2650 /* 2651 * XXX currently TX rate control depends on the rate value of 2652 * RX descriptor because I don't know how to we can control TX rate 2653 * in more smart way. Please fix me you find a thing. 2654 */ 2655 data->buf[3] = sc->sc_currate; 2656 if (prior == URTW_PRIORITY_NORMAL) { 2657 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2658 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2659 else if (ic->ic_fixed_rate != -1) 2660 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2661 } 2662 2663 if (sc->sc_hwrev & URTW_HWREV_8187) { 2664 data->buf[8] = 3; /* CW minimum */ 2665 data->buf[8] |= (7 << 4); /* CW maximum */ 2666 data->buf[9] |= 11; /* retry limitation */ 2667 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2668 } else { 2669 data->buf[21] |= 11; /* retry limitation */ 2670 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2671 } 2672 2673 data->ni = ni; 2674 2675 /* mbuf is no longer needed. */ 2676 m_freem(m0); 2677 2678 usbd_setup_xfer(data->xfer, 2679 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2680 sc->sc_txpipe_normal, data, data->buf, xferlen, 2681 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2682 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2683 error = usbd_transfer(data->xfer); 2684 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2685 printf("%s: could not send frame: %s\n", 2686 device_xname(sc->sc_dev), usbd_errstr(error)); 2687 return (EIO); 2688 } 2689 2690 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2691 if (error != 0) 2692 printf("%s: could not control LED (%d)\n", 2693 device_xname(sc->sc_dev), error); 2694 2695 if (prior == URTW_PRIORITY_LOW) 2696 sc->sc_tx_low_queued++; 2697 else 2698 sc->sc_tx_normal_queued++; 2699 2700 return (0); 2701 } 2702 2703 usbd_status 2704 urtw_8225_usb_init(struct urtw_softc *sc) 2705 { 2706 uint8_t data; 2707 usbd_status error; 2708 2709 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2710 urtw_write8_m(sc, URTW_GPIO, 0); 2711 error = urtw_read8e(sc, 0x53, &data); 2712 if (error) 2713 goto fail; 2714 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2715 if (error) 2716 goto fail; 2717 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2718 urtw_write8_m(sc, URTW_GPIO, 0x20); 2719 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2720 2721 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2722 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2723 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2724 2725 usbd_delay_ms(sc->sc_udev, 500); 2726 fail: 2727 return (error); 2728 } 2729 2730 usbd_status 2731 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2732 { 2733 usbd_status error = 0; 2734 2735 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2736 fail: 2737 return (error); 2738 } 2739 2740 usbd_status 2741 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2742 { 2743 uint32_t phyw; 2744 usbd_status error; 2745 2746 phyw = ((data << 8) | (addr | 0x80)); 2747 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2748 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2749 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2750 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2751 /* 2752 * Delay removed from 8185 to 8187. 2753 * usbd_delay_ms(sc->sc_udev, 1); 2754 */ 2755 fail: 2756 return (error); 2757 } 2758 2759 usbd_status 2760 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2761 { 2762 data = data & 0xff; 2763 return (urtw_8187_write_phy(sc, addr, data)); 2764 } 2765 2766 usbd_status 2767 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2768 { 2769 data = data & 0xff; 2770 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2771 } 2772 2773 usbd_status 2774 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2775 { 2776 usbd_status error; 2777 2778 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2779 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2780 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2781 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2782 fail: 2783 return (error); 2784 } 2785 2786 usbd_status 2787 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2788 { 2789 int i, idx, set; 2790 uint8_t *cck_pwltable; 2791 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2792 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2793 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2794 usbd_status error; 2795 2796 cck_pwrlvl_max = 11; 2797 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2798 ofdm_pwrlvl_min = 10; 2799 2800 /* CCK power setting */ 2801 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2802 idx = cck_pwrlvl % 6; 2803 set = cck_pwrlvl / 6; 2804 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2805 urtw_8225_txpwr_cck; 2806 2807 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2808 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2809 for (i = 0; i < 8; i++) { 2810 urtw_8187_write_phy_cck(sc, 0x44 + i, 2811 cck_pwltable[idx * 8 + i]); 2812 } 2813 usbd_delay_ms(sc->sc_udev, 1); 2814 2815 /* OFDM power setting */ 2816 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2817 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2818 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2819 2820 idx = ofdm_pwrlvl % 6; 2821 set = ofdm_pwrlvl / 6; 2822 2823 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2824 if (error) 2825 goto fail; 2826 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2827 urtw_8187_write_phy_ofdm(sc, 6, 0); 2828 urtw_8187_write_phy_ofdm(sc, 8, 0); 2829 2830 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2831 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2832 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2833 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2834 usbd_delay_ms(sc->sc_udev, 1); 2835 fail: 2836 return (error); 2837 } 2838 2839 usbd_status 2840 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2841 { 2842 usbd_status error; 2843 2844 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2845 usbd_delay_ms(sc->sc_udev, 1); 2846 fail: 2847 return (error); 2848 } 2849 2850 usbd_status 2851 urtw_8225_rf_init(struct urtw_rf *rf) 2852 { 2853 struct urtw_softc *sc = rf->rf_sc; 2854 unsigned int i; 2855 uint16_t data; 2856 usbd_status error; 2857 2858 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2859 if (error) 2860 goto fail; 2861 2862 error = urtw_8225_usb_init(sc); 2863 if (error) 2864 goto fail; 2865 2866 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2867 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2868 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2869 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2870 2871 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2872 if (error) 2873 goto fail; 2874 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2875 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2876 if (error) 2877 goto fail; 2878 2879 error = urtw_8185_rf_pins_enable(sc); 2880 if (error) 2881 goto fail; 2882 2883 usbd_delay_ms(sc->sc_udev, 500); 2884 2885 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2886 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2887 urtw_8225_rf_part1[i].val); 2888 } 2889 usbd_delay_ms(sc->sc_udev, 50); 2890 urtw_8225_write(sc, 0x2, 0xc4d); 2891 usbd_delay_ms(sc->sc_udev, 200); 2892 urtw_8225_write(sc, 0x2, 0x44d); 2893 usbd_delay_ms(sc->sc_udev, 200); 2894 urtw_8225_write(sc, 0x0, 0x127); 2895 2896 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2897 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2898 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2899 } 2900 2901 urtw_8225_write(sc, 0x0, 0x27); 2902 urtw_8225_write(sc, 0x0, 0x22f); 2903 2904 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2905 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2906 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2907 } 2908 2909 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2910 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2911 urtw_8225_rf_part2[i].val); 2912 usbd_delay_ms(sc->sc_udev, 1); 2913 } 2914 2915 error = urtw_8225_setgain(sc, 4); 2916 if (error) 2917 goto fail; 2918 2919 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2920 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2921 urtw_8225_rf_part3[i].val); 2922 usbd_delay_ms(sc->sc_udev, 1); 2923 } 2924 2925 urtw_write8_m(sc, 0x5b, 0x0d); 2926 2927 error = urtw_8225_set_txpwrlvl(sc, 1); 2928 if (error) 2929 goto fail; 2930 2931 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2932 usbd_delay_ms(sc->sc_udev, 1); 2933 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2934 usbd_delay_ms(sc->sc_udev, 1); 2935 2936 /* TX ant A, 0x0 for B */ 2937 error = urtw_8185_tx_antenna(sc, 0x3); 2938 if (error) 2939 goto fail; 2940 urtw_write32_m(sc, 0x94, 0x3dc00002); 2941 2942 error = urtw_8225_rf_set_chan(rf, 1); 2943 fail: 2944 return (error); 2945 } 2946 2947 usbd_status 2948 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2949 { 2950 struct urtw_softc *sc = rf->rf_sc; 2951 struct ieee80211com *ic = &sc->sc_ic; 2952 struct ieee80211_channel *c = ic->ic_ibss_chan; 2953 usbd_status error; 2954 2955 error = urtw_8225_set_txpwrlvl(sc, chan); 2956 if (error) 2957 goto fail; 2958 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2959 usbd_delay_ms(sc->sc_udev, 10); 2960 2961 urtw_write8_m(sc, URTW_SIFS, 0x22); 2962 2963 if (sc->sc_state == IEEE80211_S_ASSOC && 2964 ic->ic_flags & IEEE80211_F_SHSLOT) 2965 urtw_write8_m(sc, URTW_SLOT, 0x9); 2966 else 2967 urtw_write8_m(sc, URTW_SLOT, 0x14); 2968 2969 if (IEEE80211_IS_CHAN_G(c)) { 2970 urtw_write8_m(sc, URTW_DIFS, 0x14); 2971 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2972 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2973 } else { 2974 urtw_write8_m(sc, URTW_DIFS, 0x24); 2975 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2976 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2977 } 2978 2979 fail: 2980 return (error); 2981 } 2982 2983 usbd_status 2984 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2985 { 2986 struct urtw_softc *sc = rf->rf_sc; 2987 usbd_status error; 2988 2989 if (rf->sens > 6) 2990 return (-1); 2991 2992 if (rf->sens > 4) 2993 urtw_8225_write(sc, 0x0c, 0x850); 2994 else 2995 urtw_8225_write(sc, 0x0c, 0x50); 2996 2997 rf->sens = 6 - rf->sens; 2998 error = urtw_8225_setgain(sc, rf->sens); 2999 if (error) 3000 goto fail; 3001 3002 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3003 3004 fail: 3005 return (error); 3006 } 3007 3008 void 3009 urtw_stop(struct ifnet *ifp, int disable) 3010 { 3011 struct urtw_softc *sc = ifp->if_softc; 3012 struct ieee80211com *ic = &sc->sc_ic; 3013 uint8_t data; 3014 usbd_status error; 3015 3016 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3017 3018 sc->sc_txtimer = 0; 3019 ifp->if_timer = 0; 3020 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3021 3022 callout_stop(&sc->scan_to); 3023 callout_stop(&sc->sc_led_ch); 3024 3025 urtw_intr_disable(sc); 3026 urtw_read8_m(sc, URTW_CMD, &data); 3027 data &= ~URTW_CMD_TX_ENABLE; 3028 data &= ~URTW_CMD_RX_ENABLE; 3029 urtw_write8_m(sc, URTW_CMD, data); 3030 3031 if (sc->sc_rxpipe != NULL) 3032 usbd_abort_pipe(sc->sc_rxpipe); 3033 if (sc->sc_txpipe_low != NULL) 3034 usbd_abort_pipe(sc->sc_txpipe_low); 3035 if (sc->sc_txpipe_normal != NULL) 3036 usbd_abort_pipe(sc->sc_txpipe_normal); 3037 3038 fail: 3039 return; 3040 } 3041 3042 int 3043 urtw_isbmode(uint16_t rate) 3044 { 3045 rate = urtw_rtl2rate(rate); 3046 3047 return (((rate <= 22 && rate != 12 && rate != 18) || 3048 rate == 44) ? (1) : (0)); 3049 } 3050 3051 void 3052 urtw_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 3053 { 3054 struct urtw_rx_data *data = priv; 3055 struct urtw_softc *sc = data->sc; 3056 struct ieee80211com *ic = &sc->sc_ic; 3057 struct ifnet *ifp = ic->ic_ifp; 3058 struct ieee80211_frame *wh; 3059 struct ieee80211_node *ni; 3060 struct mbuf *m, *mnew; 3061 uint8_t *desc, quality, rate; 3062 int actlen, flen, len, nf, rssi, s; 3063 3064 if (status != USBD_NORMAL_COMPLETION) { 3065 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3066 return; 3067 3068 if (status == USBD_STALLED) 3069 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3070 ifp->if_ierrors++; 3071 goto skip; 3072 } 3073 3074 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3075 if (actlen < URTW_MIN_RXBUFSZ) { 3076 ifp->if_ierrors++; 3077 goto skip; 3078 } 3079 3080 if (sc->sc_hwrev & URTW_HWREV_8187) 3081 /* 4 dword and 4 byte CRC */ 3082 len = actlen - (4 * 4); 3083 else 3084 /* 5 dword and 4 byte CRC */ 3085 len = actlen - (4 * 5); 3086 3087 desc = data->buf + len; 3088 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3089 if (flen > actlen) { 3090 ifp->if_ierrors++; 3091 goto skip; 3092 } 3093 3094 rate = (desc[2] & 0xf0) >> 4; 3095 if (sc->sc_hwrev & URTW_HWREV_8187) { 3096 quality = desc[4] & 0xff; 3097 rssi = (desc[6] & 0xfe) >> 1; 3098 3099 /* XXX correct? */ 3100 if (!urtw_isbmode(rate)) { 3101 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3102 rssi = ((90 - rssi) * 100) / 65; 3103 } else { 3104 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3105 rssi = ((95 - rssi) * 100) / 65; 3106 } 3107 } else { 3108 quality = desc[12]; 3109 rssi = 14 - desc[14] / 2; 3110 } 3111 3112 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3113 if (mnew == NULL) { 3114 printf("%s: could not allocate rx mbuf\n", 3115 device_xname(sc->sc_dev)); 3116 ifp->if_ierrors++; 3117 goto skip; 3118 } 3119 MCLGET(mnew, M_DONTWAIT); 3120 if (!(mnew->m_flags & M_EXT)) { 3121 printf("%s: could not allocate rx mbuf cluster\n", 3122 device_xname(sc->sc_dev)); 3123 m_freem(mnew); 3124 ifp->if_ierrors++; 3125 goto skip; 3126 } 3127 3128 m = data->m; 3129 data->m = mnew; 3130 data->buf = mtod(mnew, uint8_t *); 3131 3132 /* finalize mbuf */ 3133 m->m_pkthdr.rcvif = ifp; 3134 m->m_pkthdr.len = m->m_len = flen - 4; 3135 3136 s = splnet(); 3137 3138 if (sc->sc_drvbpf != NULL) { 3139 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3140 3141 /* XXX Are variables correct? */ 3142 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3143 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3144 tap->wr_dbm_antsignal = (int8_t)rssi; 3145 3146 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 3147 } 3148 wh = mtod(m, struct ieee80211_frame *); 3149 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3150 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3151 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3152 3153 /* XXX correct? */ 3154 if (!urtw_isbmode(rate)) { 3155 if (quality > 127) 3156 quality = 0; 3157 else if (quality < 27) 3158 quality = 100; 3159 else 3160 quality = 127 - quality; 3161 } else 3162 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3163 3164 nf = quality; 3165 3166 /* send the frame to the 802.11 layer */ 3167 ieee80211_input(ic, m, ni, rssi, 0); 3168 3169 /* node is no longer needed */ 3170 ieee80211_free_node(ni); 3171 3172 splx(s); 3173 3174 skip: /* setup a new transfer */ 3175 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3176 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3177 (void)usbd_transfer(xfer); 3178 } 3179 3180 usbd_status 3181 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3182 { 3183 uint8_t *gainp; 3184 usbd_status error; 3185 3186 /* XXX for A? */ 3187 gainp = urtw_8225v2_gain_bg; 3188 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3189 usbd_delay_ms(sc->sc_udev, 1); 3190 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3191 usbd_delay_ms(sc->sc_udev, 1); 3192 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3193 usbd_delay_ms(sc->sc_udev, 1); 3194 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3195 usbd_delay_ms(sc->sc_udev, 1); 3196 fail: 3197 return (error); 3198 } 3199 3200 usbd_status 3201 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3202 { 3203 int i; 3204 uint8_t *cck_pwrtable; 3205 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3206 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3207 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3208 usbd_status error; 3209 3210 /* CCK power setting */ 3211 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3212 cck_pwrlvl += sc->sc_txpwr_cck_base; 3213 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3214 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3215 urtw_8225v2_txpwr_cck; 3216 3217 for (i = 0; i < 8; i++) { 3218 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3219 } 3220 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3221 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3222 usbd_delay_ms(sc->sc_udev, 1); 3223 3224 /* OFDM power setting */ 3225 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3226 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3227 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3228 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3229 3230 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3231 if (error) 3232 goto fail; 3233 3234 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3235 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3236 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3237 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3238 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3239 3240 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3241 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3242 usbd_delay_ms(sc->sc_udev, 1); 3243 fail: 3244 return (error); 3245 } 3246 3247 usbd_status 3248 urtw_8225v2_rf_init(struct urtw_rf *rf) 3249 { 3250 struct urtw_softc *sc = rf->rf_sc; 3251 int i; 3252 uint16_t data; 3253 uint32_t data32; 3254 usbd_status error; 3255 3256 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3257 if (error) 3258 goto fail; 3259 3260 error = urtw_8225_usb_init(sc); 3261 if (error) 3262 goto fail; 3263 3264 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3265 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3266 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3267 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3268 3269 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3270 if (error) 3271 goto fail; 3272 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3273 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3274 if (error) 3275 goto fail; 3276 3277 error = urtw_8185_rf_pins_enable(sc); 3278 if (error) 3279 goto fail; 3280 3281 usbd_delay_ms(sc->sc_udev, 1000); 3282 3283 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3284 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3285 urtw_8225v2_rf_part1[i].val); 3286 usbd_delay_ms(sc->sc_udev, 1); 3287 } 3288 usbd_delay_ms(sc->sc_udev, 50); 3289 3290 urtw_8225_write(sc, 0x0, 0x1b7); 3291 3292 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3293 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3294 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3295 } 3296 3297 urtw_8225_write(sc, 0x3, 0x2); 3298 urtw_8225_write(sc, 0x5, 0x4); 3299 urtw_8225_write(sc, 0x0, 0xb7); 3300 urtw_8225_write(sc, 0x2, 0xc4d); 3301 usbd_delay_ms(sc->sc_udev, 100); 3302 urtw_8225_write(sc, 0x2, 0x44d); 3303 usbd_delay_ms(sc->sc_udev, 100); 3304 3305 error = urtw_8225_read(sc, 0x6, &data32); 3306 if (error != 0) 3307 goto fail; 3308 if (data32 != 0xe6) 3309 printf("%s: expect 0xe6!! (0x%x)\n", device_xname(sc->sc_dev), 3310 data32); 3311 if (!(data32 & 0x80)) { 3312 urtw_8225_write(sc, 0x02, 0x0c4d); 3313 usbd_delay_ms(sc->sc_udev, 200); 3314 urtw_8225_write(sc, 0x02, 0x044d); 3315 usbd_delay_ms(sc->sc_udev, 100); 3316 error = urtw_8225_read(sc, 0x6, &data32); 3317 if (error != 0) 3318 goto fail; 3319 if (!(data32 & 0x80)) 3320 printf("%s: RF calibration failed\n", 3321 device_xname(sc->sc_dev)); 3322 } 3323 usbd_delay_ms(sc->sc_udev, 100); 3324 3325 urtw_8225_write(sc, 0x0, 0x2bf); 3326 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3327 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3328 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3329 } 3330 3331 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3332 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3333 urtw_8225v2_rf_part2[i].val); 3334 } 3335 3336 error = urtw_8225v2_setgain(sc, 4); 3337 if (error) 3338 goto fail; 3339 3340 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3341 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3342 urtw_8225v2_rf_part3[i].val); 3343 } 3344 3345 urtw_write8_m(sc, 0x5b, 0x0d); 3346 3347 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3348 if (error) 3349 goto fail; 3350 3351 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3352 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3353 3354 /* TX ant A, 0x0 for B */ 3355 error = urtw_8185_tx_antenna(sc, 0x3); 3356 if (error) 3357 goto fail; 3358 urtw_write32_m(sc, 0x94, 0x3dc00002); 3359 3360 error = urtw_8225_rf_set_chan(rf, 1); 3361 fail: 3362 return (error); 3363 } 3364 3365 usbd_status 3366 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3367 { 3368 struct urtw_softc *sc = rf->rf_sc; 3369 struct ieee80211com *ic = &sc->sc_ic; 3370 struct ieee80211_channel *c = ic->ic_ibss_chan; 3371 usbd_status error; 3372 3373 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3374 if (error) 3375 goto fail; 3376 3377 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3378 usbd_delay_ms(sc->sc_udev, 10); 3379 3380 urtw_write8_m(sc, URTW_SIFS, 0x22); 3381 3382 if(sc->sc_state == IEEE80211_S_ASSOC && 3383 ic->ic_flags & IEEE80211_F_SHSLOT) 3384 urtw_write8_m(sc, URTW_SLOT, 0x9); 3385 else 3386 urtw_write8_m(sc, URTW_SLOT, 0x14); 3387 3388 if (IEEE80211_IS_CHAN_G(c)) { 3389 urtw_write8_m(sc, URTW_DIFS, 0x14); 3390 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3391 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3392 } else { 3393 urtw_write8_m(sc, URTW_DIFS, 0x24); 3394 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3395 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3396 } 3397 3398 fail: 3399 return (error); 3400 } 3401 3402 void 3403 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3404 { 3405 struct urtw_rf *rf = &sc->sc_rf; 3406 struct ieee80211com *ic = &sc->sc_ic; 3407 usbd_status error = 0; 3408 uint32_t data; 3409 u_int chan; 3410 3411 chan = ieee80211_chan2ieee(ic, c); 3412 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3413 return; 3414 /* 3415 * During changing the channel we need to temporary disable 3416 * TX. 3417 */ 3418 urtw_read32_m(sc, URTW_TX_CONF, &data); 3419 data &= ~URTW_TX_LOOPBACK_MASK; 3420 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3421 error = rf->set_chan(rf, chan); 3422 if (error != 0) { 3423 printf("%s could not change the channel\n", 3424 device_xname(sc->sc_dev)); 3425 return; 3426 } 3427 usbd_delay_ms(sc->sc_udev, 10); 3428 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3429 3430 fail: return; 3431 3432 } 3433 3434 void 3435 urtw_next_scan(void *arg) 3436 { 3437 struct urtw_softc *sc = arg; 3438 struct ieee80211com *ic = &sc->sc_ic; 3439 int s; 3440 3441 if (sc->sc_dying) 3442 return; 3443 3444 s = splnet(); 3445 if (ic->ic_state == IEEE80211_S_SCAN) 3446 ieee80211_next_scan(ic); 3447 splx(s); 3448 } 3449 3450 void 3451 urtw_task(void *arg) 3452 { 3453 struct urtw_softc *sc = arg; 3454 struct ieee80211com *ic = &sc->sc_ic; 3455 struct ieee80211_node *ni; 3456 enum ieee80211_state ostate; 3457 usbd_status error = 0; 3458 3459 if (sc->sc_dying) 3460 return; 3461 3462 ostate = ic->ic_state; 3463 3464 switch (sc->sc_state) { 3465 case IEEE80211_S_INIT: 3466 if (ostate == IEEE80211_S_RUN) { 3467 /* turn link LED off */ 3468 (void)urtw_led_off(sc, URTW_LED_GPIO); 3469 } 3470 break; 3471 3472 case IEEE80211_S_SCAN: 3473 urtw_set_chan(sc, ic->ic_curchan); 3474 if (!sc->sc_dying) 3475 callout_schedule(&sc->scan_to, mstohz(200)); 3476 break; 3477 3478 case IEEE80211_S_AUTH: 3479 case IEEE80211_S_ASSOC: 3480 urtw_set_chan(sc, ic->ic_curchan); 3481 break; 3482 3483 case IEEE80211_S_RUN: 3484 ni = ic->ic_bss; 3485 3486 urtw_set_chan(sc, ic->ic_curchan); 3487 3488 /* setting bssid. */ 3489 error = urtw_set_bssid(sc, ni->ni_bssid); 3490 if (error != 0) 3491 goto fail; 3492 urtw_update_msr(sc); 3493 /* XXX maybe the below would be incorrect. */ 3494 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3495 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3496 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3497 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3498 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3499 if (error != 0) 3500 printf("%s: could not control LED (%d)\n", 3501 device_xname(sc->sc_dev), error); 3502 break; 3503 } 3504 3505 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3506 3507 fail: 3508 if (error != 0) { 3509 DPRINTF(("%s: error duing processing RUN state.", 3510 device_xname(sc->sc_dev))); 3511 } 3512 } 3513 3514 usbd_status 3515 urtw_8187b_update_wmm(struct urtw_softc *sc) 3516 { 3517 struct ieee80211com *ic = &sc->sc_ic; 3518 struct ieee80211_channel *c = ic->ic_ibss_chan; 3519 uint32_t data; 3520 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3521 usbd_status error; 3522 3523 sifs = 0xa; 3524 if (IEEE80211_IS_CHAN_G(c)) 3525 slot = 0x9; 3526 else 3527 slot = 0x14; 3528 3529 aifs = (2 * slot) + sifs; 3530 ecwmin = 3; 3531 ecwmax = 7; 3532 3533 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3534 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3535 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3536 3537 urtw_write32_m(sc, URTW_AC_VO, data); 3538 urtw_write32_m(sc, URTW_AC_VI, data); 3539 urtw_write32_m(sc, URTW_AC_BE, data); 3540 urtw_write32_m(sc, URTW_AC_BK, data); 3541 3542 fail: 3543 return (error); 3544 } 3545 3546 usbd_status 3547 urtw_8187b_reset(struct urtw_softc *sc) 3548 { 3549 uint8_t data; 3550 usbd_status error; 3551 3552 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3553 if (error) 3554 goto fail; 3555 3556 urtw_read8_m(sc, URTW_CONFIG3, &data); 3557 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3558 URTW_CONFIG3_GNT_SELECT); 3559 3560 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3561 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3562 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3563 3564 urtw_write8_m(sc, 0x61, 0x10); 3565 urtw_read8_m(sc, 0x62, &data); 3566 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3567 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3568 3569 urtw_read8_m(sc, URTW_CONFIG3, &data); 3570 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3571 3572 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3573 if (error) 3574 goto fail; 3575 3576 urtw_read8_m(sc, URTW_CMD, &data); 3577 data = (data & 2) | URTW_CMD_RST; 3578 urtw_write8_m(sc, URTW_CMD, data); 3579 usbd_delay_ms(sc->sc_udev, 100); 3580 3581 urtw_read8_m(sc, URTW_CMD, &data); 3582 if (data & URTW_CMD_RST) { 3583 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3584 goto fail; 3585 } 3586 3587 fail: 3588 return (error); 3589 } 3590 3591 int 3592 urtw_8187b_init(struct ifnet *ifp) 3593 { 3594 struct urtw_softc *sc = ifp->if_softc; 3595 struct urtw_rf *rf = &sc->sc_rf; 3596 struct ieee80211com *ic = &sc->sc_ic; 3597 int ret; 3598 uint8_t data; 3599 usbd_status error; 3600 3601 urtw_stop(ifp, 0); 3602 3603 error = urtw_8187b_update_wmm(sc); 3604 if (error != 0) 3605 goto fail; 3606 error = urtw_8187b_reset(sc); 3607 if (error) 3608 goto fail; 3609 3610 /* Applying MAC address again. */ 3611 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3612 if (error) 3613 goto fail; 3614 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3615 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3616 if (error) 3617 goto fail; 3618 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3619 if (error) 3620 goto fail; 3621 3622 error = urtw_update_msr(sc); 3623 if (error) 3624 goto fail; 3625 3626 error = rf->init(rf); 3627 if (error != 0) 3628 goto fail; 3629 3630 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3631 URTW_CMD_RX_ENABLE); 3632 error = urtw_intr_enable(sc); 3633 if (error != 0) 3634 goto fail; 3635 3636 error = urtw_write8e(sc, 0x41, 0xf4); 3637 if (error != 0) 3638 goto fail; 3639 error = urtw_write8e(sc, 0x40, 0x00); 3640 if (error != 0) 3641 goto fail; 3642 error = urtw_write8e(sc, 0x42, 0x00); 3643 if (error != 0) 3644 goto fail; 3645 error = urtw_write8e(sc, 0x42, 0x01); 3646 if (error != 0) 3647 goto fail; 3648 error = urtw_write8e(sc, 0x40, 0x0f); 3649 if (error != 0) 3650 goto fail; 3651 error = urtw_write8e(sc, 0x42, 0x00); 3652 if (error != 0) 3653 goto fail; 3654 error = urtw_write8e(sc, 0x42, 0x01); 3655 if (error != 0) 3656 goto fail; 3657 3658 urtw_read8_m(sc, 0xdb, &data); 3659 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3660 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3661 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3662 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3663 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3664 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3665 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3666 urtw_write8_m(sc, 0x61, 0); 3667 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3668 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3669 urtw_write8_m(sc, 0xda, 0x10); 3670 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3671 3672 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3673 3674 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3675 3676 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3677 3678 /* Reset softc variables. */ 3679 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3680 sc->sc_txtimer = 0; 3681 3682 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3683 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3684 if (error != 0) { 3685 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3686 ", err=%s\n", usbd_errstr(error)); 3687 3688 goto fail; 3689 } 3690 /* Get the first interface handle. */ 3691 error = usbd_device2interface_handle(sc->sc_udev, 3692 URTW_IFACE_INDEX, &sc->sc_iface); 3693 if (error != 0) { 3694 printf("%s: could not get interface handle\n", 3695 device_xname(sc->sc_dev)); 3696 goto fail; 3697 } 3698 error = urtw_open_pipes(sc); 3699 if (error != 0) 3700 goto fail; 3701 ret = urtw_alloc_rx_data_list(sc); 3702 if (error != 0) 3703 goto fail; 3704 ret = urtw_alloc_tx_data_list(sc); 3705 if (error != 0) 3706 goto fail; 3707 sc->sc_flags |= URTW_INIT_ONCE; 3708 } 3709 3710 error = urtw_rx_enable(sc); 3711 if (error != 0) 3712 goto fail; 3713 error = urtw_tx_enable(sc); 3714 if (error != 0) 3715 goto fail; 3716 3717 ifp->if_flags &= ~IFF_OACTIVE; 3718 ifp->if_flags |= IFF_RUNNING; 3719 3720 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3721 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3722 else 3723 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3724 3725 fail: 3726 return (error); 3727 } 3728 3729 usbd_status 3730 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3731 { 3732 int i; 3733 usbd_status error; 3734 3735 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3736 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3737 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3738 } 3739 3740 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3741 urtw_write16_m(sc, URTW_INT_MIG, 0); 3742 3743 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3744 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3745 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3746 3747 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3748 3749 fail: 3750 return (error); 3751 } 3752 3753 usbd_status 3754 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3755 { 3756 usbd_status error; 3757 3758 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3759 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3760 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3761 usbd_delay_ms(sc->sc_udev, 100); 3762 3763 fail: 3764 return (error); 3765 } 3766 3767 usbd_status 3768 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3769 { 3770 struct ieee80211com *ic = &sc->sc_ic; 3771 struct ieee80211_channel *c = ic->ic_ibss_chan; 3772 uint8_t aifs, difs, eifs, sifs, slot; 3773 usbd_status error; 3774 3775 urtw_write8_m(sc, URTW_SIFS, 0x22); 3776 3777 sifs = 0xa; 3778 if (IEEE80211_IS_CHAN_G(c)) { 3779 slot = 0x9; 3780 difs = 0x1c; 3781 eifs = 0x5b; 3782 } else { 3783 slot = 0x14; 3784 difs = 0x32; 3785 eifs = 0x5b; 3786 } 3787 aifs = (2 * slot) + sifs; 3788 3789 urtw_write8_m(sc, URTW_SLOT, slot); 3790 3791 urtw_write8_m(sc, URTW_AC_VO, aifs); 3792 urtw_write8_m(sc, URTW_AC_VI, aifs); 3793 urtw_write8_m(sc, URTW_AC_BE, aifs); 3794 urtw_write8_m(sc, URTW_AC_BK, aifs); 3795 3796 urtw_write8_m(sc, URTW_DIFS, difs); 3797 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3798 3799 fail: 3800 return (error); 3801 } 3802 3803 usbd_status 3804 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3805 { 3806 struct urtw_softc *sc = rf->rf_sc; 3807 unsigned int i; 3808 uint8_t data; 3809 usbd_status error; 3810 3811 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3812 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3813 urtw_read8_m(sc, URTW_CW_CONF, &data); 3814 urtw_write8_m(sc, URTW_CW_CONF, data | 3815 URTW_CW_CONF_PERPACKET_RETRY); 3816 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3817 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3818 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3819 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3820 3821 /* Auto rate fallback control. */ 3822 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3823 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3824 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3825 URTW_RATE_FALLBACK_ENABLE); 3826 3827 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3828 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3829 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3830 3831 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3832 if (error) 3833 goto fail; 3834 urtw_read8_m(sc, URTW_CONFIG1, &data); 3835 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3836 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3837 if (error) 3838 goto fail; 3839 3840 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3841 urtw_8225v2_b_config_mac(sc); 3842 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3843 3844 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3845 if (error) 3846 goto fail; 3847 urtw_read8_m(sc, URTW_CONFIG3, &data); 3848 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3849 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3850 if (error) 3851 goto fail; 3852 3853 urtw_8225v2_b_init_rfe(sc); 3854 3855 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3856 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3857 urtw_8225v2_b_rf[i].val); 3858 } 3859 3860 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3861 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3862 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3863 } 3864 3865 urtw_8225_write(sc, 0x03, 0x080); 3866 urtw_8225_write(sc, 0x05, 0x004); 3867 urtw_8225_write(sc, 0x00, 0x0b7); 3868 urtw_8225_write(sc, 0x02, 0xc4d); 3869 urtw_8225_write(sc, 0x02, 0x44d); 3870 urtw_8225_write(sc, 0x00, 0x2bf); 3871 3872 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3873 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3874 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3875 3876 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3877 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3878 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3879 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3880 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3881 } 3882 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3883 3884 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3885 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3886 3887 urtw_8225v2_b_update_chan(sc); 3888 3889 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3890 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3891 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3892 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3893 3894 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3895 fail: 3896 return (error); 3897 } 3898 3899 usbd_status 3900 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3901 { 3902 struct urtw_softc *sc = rf->rf_sc; 3903 usbd_status error; 3904 3905 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3906 if (error) 3907 goto fail; 3908 3909 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3910 /* 3911 * Delay removed from 8185 to 8187. 3912 * usbd_delay_ms(sc->sc_udev, 10); 3913 */ 3914 3915 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3916 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3917 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3918 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3919 3920 fail: 3921 return (error); 3922 } 3923 3924 usbd_status 3925 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3926 { 3927 int i; 3928 uint8_t *cck_pwrtable; 3929 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3930 ofdm_pwrlvl_max; 3931 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3932 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3933 usbd_status error; 3934 3935 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3936 cck_pwrlvl_min = 0; 3937 cck_pwrlvl_max = 15; 3938 ofdm_pwrlvl_min = 2; 3939 ofdm_pwrlvl_max = 17; 3940 } else { 3941 cck_pwrlvl_min = 7; 3942 cck_pwrlvl_max = 22; 3943 ofdm_pwrlvl_min = 10; 3944 ofdm_pwrlvl_max = 25; 3945 } 3946 3947 /* CCK power setting */ 3948 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3949 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3950 3951 cck_pwrlvl += sc->sc_txpwr_cck_base; 3952 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3953 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3954 3955 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3956 urtw_8225v2_txpwr_cck; 3957 3958 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3959 if (cck_pwrlvl <= 6) 3960 ; /* do nothing */ 3961 else if (cck_pwrlvl <= 11) 3962 cck_pwrtable += 8; 3963 else 3964 cck_pwrtable += 16; 3965 } else { 3966 if (cck_pwrlvl <= 5) 3967 ; /* do nothing */ 3968 else if (cck_pwrlvl <= 11) 3969 cck_pwrtable += 8; 3970 else if (cck_pwrlvl <= 17) 3971 cck_pwrtable += 16; 3972 else 3973 cck_pwrtable += 24; 3974 } 3975 3976 for (i = 0; i < 8; i++) { 3977 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3978 } 3979 3980 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3981 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3982 /* 3983 * Delay removed from 8185 to 8187. 3984 * usbd_delay_ms(sc->sc_udev, 1); 3985 */ 3986 3987 /* OFDM power setting */ 3988 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3989 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3990 3991 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3992 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3993 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3994 3995 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3996 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3997 3998 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3999 if (ofdm_pwrlvl <= 11) { 4000 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 4001 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 4002 } else { 4003 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4004 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4005 } 4006 } else { 4007 if (ofdm_pwrlvl <= 11) { 4008 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4009 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4010 } else if (ofdm_pwrlvl <= 17) { 4011 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4012 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4013 } else { 4014 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4015 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4016 } 4017 } 4018 4019 /* 4020 * Delay removed from 8185 to 8187. 4021 * usbd_delay_ms(sc->sc_udev, 1); 4022 */ 4023 fail: 4024 return (error); 4025 } 4026 4027 int 4028 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4029 { 4030 int error; 4031 4032 urtw_write32_m(sc, URTW_BSSID, 4033 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4034 urtw_write16_m(sc, URTW_BSSID + 4, 4035 bssid[4] | bssid[5] << 8); 4036 4037 return 0; 4038 4039 fail: 4040 return error; 4041 } 4042 4043 int 4044 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4045 { 4046 int error; 4047 4048 urtw_write32_m(sc, URTW_MAC0, 4049 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4050 urtw_write16_m(sc, URTW_MAC4, 4051 addr[4] | addr[5] << 8); 4052 4053 return 0; 4054 4055 fail: 4056 return error; 4057 } 4058 4059 MODULE(MODULE_CLASS_DRIVER, if_urtw, "bpf"); 4060 4061 #ifdef _MODULE 4062 #include "ioconf.c" 4063 #endif 4064 4065 static int 4066 if_urtw_modcmd(modcmd_t cmd, void *aux) 4067 { 4068 int error = 0; 4069 4070 switch (cmd) { 4071 case MODULE_CMD_INIT: 4072 #ifdef _MODULE 4073 error = config_init_component(cfdriver_ioconf_urtw, 4074 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4075 #endif 4076 return error; 4077 case MODULE_CMD_FINI: 4078 #ifdef _MODULE 4079 error = config_fini_component(cfdriver_ioconf_urtw, 4080 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4081 #endif 4082 return error; 4083 default: 4084 return ENOTTY; 4085 } 4086 } 4087
Indexes created Fri Oct 03 02:09:57 GMT 2025