if_urtw.c revision 1.1.8.4
1 /* $NetBSD: if_urtw.c,v 1.1.8.4 2014/05/22 11:40:36 yamt Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.1.8.4 2014/05/22 11:40:36 yamt Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/sockio.h> 26 #include <sys/proc.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 38 #include <machine/endian.h> 39 #include <net/bpf.h> 40 #include <net/if.h> 41 #include <net/if_arp.h> 42 #include <net/if_dl.h> 43 #include <net/if_ether.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_inarp.h> 51 #include <netinet/ip.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include "if_urtwreg.h" 63 64 #ifdef URTW_DEBUG 65 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 67 int urtw_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * Recognized device vendors/products. 75 */ 76 static const struct urtw_type { 77 struct usb_devno dev; 78 uint8_t rev; 79 } urtw_devs[] = { 80 #define URTW_DEV_RTL8187(v, p) \ 81 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 82 #define URTW_DEV_RTL8187B(v, p) \ 83 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 84 /* Realtek RTL8187 devices. */ 85 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 86 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 87 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 88 URTW_DEV_RTL8187(LOGITEC, RTL8187), 89 URTW_DEV_RTL8187(NETGEAR, WG111V2), 90 URTW_DEV_RTL8187(REALTEK, RTL8187), 91 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 92 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 93 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 94 /* Realtek RTL8187B devices. */ 95 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 96 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 97 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 98 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 99 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 100 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 101 #undef URTW_DEV_RTL8187 102 #undef URTW_DEV_RTL8187B 103 }; 104 #define urtw_lookup(v, p) \ 105 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 106 107 /* 108 * Helper read/write macros. 109 */ 110 #define urtw_read8_m(sc, val, data) do { \ 111 error = urtw_read8_c(sc, val, data, 0); \ 112 if (error != 0) \ 113 goto fail; \ 114 } while (0) 115 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 116 error = urtw_read8_c(sc, val, data, idx); \ 117 if (error != 0) \ 118 goto fail; \ 119 } while (0) 120 #define urtw_write8_m(sc, val, data) do { \ 121 error = urtw_write8_c(sc, val, data, 0); \ 122 if (error != 0) \ 123 goto fail; \ 124 } while (0) 125 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 126 error = urtw_write8_c(sc, val, data, idx); \ 127 if (error != 0) \ 128 goto fail; \ 129 } while (0) 130 #define urtw_read16_m(sc, val, data) do { \ 131 error = urtw_read16_c(sc, val, data, 0); \ 132 if (error != 0) \ 133 goto fail; \ 134 } while (0) 135 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 136 error = urtw_read16_c(sc, val, data, idx); \ 137 if (error != 0) \ 138 goto fail; \ 139 } while (0) 140 #define urtw_write16_m(sc, val, data) do { \ 141 error = urtw_write16_c(sc, val, data, 0); \ 142 if (error != 0) \ 143 goto fail; \ 144 } while (0) 145 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 146 error = urtw_write16_c(sc, val, data, idx); \ 147 if (error != 0) \ 148 goto fail; \ 149 } while (0) 150 #define urtw_read32_m(sc, val, data) do { \ 151 error = urtw_read32_c(sc, val, data, 0); \ 152 if (error != 0) \ 153 goto fail; \ 154 } while (0) 155 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 156 error = urtw_read32_c(sc, val, data, idx); \ 157 if (error != 0) \ 158 goto fail; \ 159 } while (0) 160 #define urtw_write32_m(sc, val, data) do { \ 161 error = urtw_write32_c(sc, val, data, 0); \ 162 if (error != 0) \ 163 goto fail; \ 164 } while (0) 165 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 166 error = urtw_write32_c(sc, val, data, idx); \ 167 if (error != 0) \ 168 goto fail; \ 169 } while (0) 170 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 171 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 172 if (error != 0) \ 173 goto fail; \ 174 } while (0) 175 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 176 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 177 if (error != 0) \ 178 goto fail; \ 179 } while (0) 180 #define urtw_8225_write(sc, val, data) do { \ 181 error = urtw_8225_write_c(sc, val, data); \ 182 if (error != 0) \ 183 goto fail; \ 184 } while (0) 185 186 struct urtw_pair { 187 uint32_t reg; 188 uint32_t val; 189 }; 190 191 struct urtw_pair_idx { 192 uint8_t reg; 193 uint8_t val; 194 uint8_t idx; 195 }; 196 197 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 198 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 199 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 200 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 201 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 202 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 203 { 0xff, 0x00, 0 }, 204 205 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 206 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 207 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 208 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 209 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 210 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 211 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 212 { 0xf8, 0x08, 1 }, 213 214 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 215 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 216 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 217 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 218 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 219 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 220 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 221 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 222 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 223 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 224 225 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 226 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 227 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 228 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 229 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 230 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 231 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 232 233 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 234 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 235 }; 236 237 static uint8_t urtw_8225_agc[] = { 238 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 239 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 240 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 241 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 242 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 243 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 244 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 245 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 246 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 247 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 248 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 249 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 250 }; 251 252 static uint32_t urtw_8225_channel[] = { 253 0x0000, /* dummy channel 0 */ 254 0x085c, /* 1 */ 255 0x08dc, /* 2 */ 256 0x095c, /* 3 */ 257 0x09dc, /* 4 */ 258 0x0a5c, /* 5 */ 259 0x0adc, /* 6 */ 260 0x0b5c, /* 7 */ 261 0x0bdc, /* 8 */ 262 0x0c5c, /* 9 */ 263 0x0cdc, /* 10 */ 264 0x0d5c, /* 11 */ 265 0x0ddc, /* 12 */ 266 0x0e5c, /* 13 */ 267 0x0f72, /* 14 */ 268 }; 269 270 static uint8_t urtw_8225_gain[] = { 271 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 272 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 273 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 274 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 275 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 276 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 277 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 278 }; 279 280 static struct urtw_pair urtw_8225_rf_part1[] = { 281 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 282 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 283 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 284 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 285 }; 286 287 static struct urtw_pair urtw_8225_rf_part2[] = { 288 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 289 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 290 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 291 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 292 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 293 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 294 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 295 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 296 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 297 { 0x27, 0x88 } 298 }; 299 300 static struct urtw_pair urtw_8225_rf_part3[] = { 301 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 302 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 303 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 304 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 305 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 306 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 307 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 308 }; 309 310 static uint16_t urtw_8225_rxgain[] = { 311 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 312 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 313 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 314 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 315 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 316 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 317 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 318 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 319 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 320 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 321 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 322 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 323 }; 324 325 static uint8_t urtw_8225_threshold[] = { 326 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 327 }; 328 329 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 330 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 331 }; 332 333 static uint8_t urtw_8225_txpwr_cck[] = { 334 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 335 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 336 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 337 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 338 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 339 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 340 }; 341 342 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 343 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 344 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 345 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 346 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 347 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 348 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 349 }; 350 351 static uint8_t urtw_8225_txpwr_ofdm[] = { 352 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 353 }; 354 355 static uint8_t urtw_8225v2_agc[] = { 356 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 357 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 358 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 359 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 360 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 361 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 362 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 363 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 364 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 365 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 366 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 367 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 368 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 369 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 370 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 371 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 372 }; 373 374 static uint8_t urtw_8225v2_ofdm[] = { 375 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 376 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 377 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 378 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 379 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 380 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 381 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 382 0x6d, 0x3c, 0xfb, 0x07 383 }; 384 385 static uint8_t urtw_8225v2_gain_bg[] = { 386 0x23, 0x15, 0xa5, /* -82-1dbm */ 387 0x23, 0x15, 0xb5, /* -82-2dbm */ 388 0x23, 0x15, 0xc5, /* -82-3dbm */ 389 0x33, 0x15, 0xc5, /* -78dbm */ 390 0x43, 0x15, 0xc5, /* -74dbm */ 391 0x53, 0x15, 0xc5, /* -70dbm */ 392 0x63, 0x15, 0xc5, /* -66dbm */ 393 }; 394 395 static struct urtw_pair urtw_8225v2_rf_part1[] = { 396 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 397 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 398 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 399 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 400 }; 401 402 static struct urtw_pair urtw_8225v2_rf_part2[] = { 403 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 404 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 405 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 406 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 407 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 408 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 409 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 410 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 411 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 412 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 413 }; 414 415 static struct urtw_pair urtw_8225v2_rf_part3[] = { 416 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 417 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 418 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 419 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 420 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 421 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 422 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 423 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 424 }; 425 426 static uint16_t urtw_8225v2_rxgain[] = { 427 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 428 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 429 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 430 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 431 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 432 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 433 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 434 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 435 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 436 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 437 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 438 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 439 }; 440 441 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 442 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 443 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 444 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 445 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 446 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 447 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 448 }; 449 450 static uint8_t urtw_8225v2_txpwr_cck[] = { 451 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 452 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 453 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 454 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 455 }; 456 457 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 458 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 459 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 460 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 461 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 462 }; 463 464 static struct urtw_pair urtw_8225v2_b_rf[] = { 465 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 466 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 467 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 468 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 469 { 0x00, 0x01b7 } 470 }; 471 472 static struct urtw_pair urtw_ratetable[] = { 473 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 474 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 475 { 96, 10 }, { 108, 11 } 476 }; 477 478 int urtw_init(struct ifnet *); 479 void urtw_stop(struct ifnet *, int); 480 int urtw_ioctl(struct ifnet *, u_long, void *); 481 void urtw_start(struct ifnet *); 482 int urtw_alloc_rx_data_list(struct urtw_softc *); 483 void urtw_free_rx_data_list(struct urtw_softc *); 484 int urtw_alloc_tx_data_list(struct urtw_softc *); 485 void urtw_free_tx_data_list(struct urtw_softc *); 486 void urtw_rxeof(usbd_xfer_handle, usbd_private_handle, 487 usbd_status); 488 int urtw_tx_start(struct urtw_softc *, 489 struct ieee80211_node *, struct mbuf *, int); 490 void urtw_txeof_low(usbd_xfer_handle, usbd_private_handle, 491 usbd_status); 492 void urtw_txeof_normal(usbd_xfer_handle, usbd_private_handle, 493 usbd_status); 494 void urtw_next_scan(void *); 495 void urtw_task(void *); 496 void urtw_ledusbtask(void *); 497 void urtw_ledtask(void *); 498 int urtw_media_change(struct ifnet *); 499 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 500 void urtw_watchdog(struct ifnet *); 501 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 502 int urtw_isbmode(uint16_t); 503 uint16_t urtw_rate2rtl(int rate); 504 uint16_t urtw_rtl2rate(int); 505 usbd_status urtw_set_rate(struct urtw_softc *); 506 usbd_status urtw_update_msr(struct urtw_softc *); 507 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 508 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 509 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 510 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 511 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 512 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 513 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 514 usbd_status urtw_eprom_ck(struct urtw_softc *); 515 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 516 int); 517 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 518 uint32_t *); 519 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 520 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 521 usbd_status urtw_get_macaddr(struct urtw_softc *); 522 usbd_status urtw_get_txpwr(struct urtw_softc *); 523 usbd_status urtw_get_rfchip(struct urtw_softc *); 524 usbd_status urtw_led_init(struct urtw_softc *); 525 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 526 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 527 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 528 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 529 uint32_t); 530 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 531 uint32_t); 532 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 533 usbd_status urtw_8225_usb_init(struct urtw_softc *); 534 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 535 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 536 uint16_t); 537 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 538 usbd_status urtw_8225_rf_init(struct urtw_rf *); 539 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 540 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 541 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 542 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 543 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 544 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 545 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 546 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 547 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 548 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 549 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 550 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 551 usbd_status urtw_open_pipes(struct urtw_softc *); 552 usbd_status urtw_close_pipes(struct urtw_softc *); 553 usbd_status urtw_intr_enable(struct urtw_softc *); 554 usbd_status urtw_intr_disable(struct urtw_softc *); 555 usbd_status urtw_reset(struct urtw_softc *); 556 usbd_status urtw_led_on(struct urtw_softc *, int); 557 usbd_status urtw_led_ctl(struct urtw_softc *, int); 558 usbd_status urtw_led_blink(struct urtw_softc *); 559 usbd_status urtw_led_mode0(struct urtw_softc *, int); 560 usbd_status urtw_led_mode1(struct urtw_softc *, int); 561 usbd_status urtw_led_mode2(struct urtw_softc *, int); 562 usbd_status urtw_led_mode3(struct urtw_softc *, int); 563 usbd_status urtw_rx_setconf(struct urtw_softc *); 564 usbd_status urtw_rx_enable(struct urtw_softc *); 565 usbd_status urtw_tx_enable(struct urtw_softc *); 566 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 567 usbd_status urtw_8187b_reset(struct urtw_softc *); 568 int urtw_8187b_init(struct ifnet *); 569 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 570 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 571 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 572 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 573 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 574 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 575 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 576 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 577 578 int urtw_match(device_t, cfdata_t, void *); 579 void urtw_attach(device_t, device_t, void *); 580 int urtw_detach(device_t, int); 581 int urtw_activate(device_t, enum devact); 582 583 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 584 urtw_match, 585 urtw_attach, 586 urtw_detach, 587 urtw_activate 588 ); 589 590 int 591 urtw_match(device_t parent, cfdata_t match, void *aux) 592 { 593 struct usb_attach_arg *uaa = aux; 594 595 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 596 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 597 } 598 599 void 600 urtw_attach(device_t parent, device_t self, void *aux) 601 { 602 struct urtw_softc *sc = device_private(self); 603 struct usb_attach_arg *uaa = aux; 604 struct ieee80211com *ic = &sc->sc_ic; 605 struct ifnet *ifp = &sc->sc_if; 606 usbd_status error; 607 uint8_t data8; 608 uint32_t data; 609 int i; 610 611 sc->sc_dev = self; 612 sc->sc_udev = uaa->device; 613 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 614 615 printf(": "); 616 617 if (sc->sc_hwrev & URTW_HWREV_8187) { 618 urtw_read32_m(sc, URTW_TX_CONF, &data); 619 data &= URTW_TX_HWREV_MASK; 620 switch (data) { 621 case URTW_TX_HWREV_8187_D: 622 sc->sc_hwrev |= URTW_HWREV_8187_D; 623 printf("RTL8187 rev D"); 624 break; 625 case URTW_TX_HWREV_8187B_D: 626 /* 627 * Detect Realtek RTL8187B devices that use 628 * USB IDs of RTL8187. 629 */ 630 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 631 printf("RTL8187B rev B (early)"); 632 break; 633 default: 634 sc->sc_hwrev |= URTW_HWREV_8187_B; 635 printf("RTL8187 rev 0x%02x", data >> 25); 636 break; 637 } 638 } else { 639 /* RTL8187B hwrev register. */ 640 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 641 switch (data8) { 642 case URTW_8187B_HWREV_8187B_B: 643 sc->sc_hwrev |= URTW_HWREV_8187B_B; 644 printf("RTL8187B rev B"); 645 break; 646 case URTW_8187B_HWREV_8187B_D: 647 sc->sc_hwrev |= URTW_HWREV_8187B_D; 648 printf("RTL8187B rev D"); 649 break; 650 case URTW_8187B_HWREV_8187B_E: 651 sc->sc_hwrev |= URTW_HWREV_8187B_E; 652 printf("RTL8187B rev E"); 653 break; 654 default: 655 sc->sc_hwrev |= URTW_HWREV_8187B_B; 656 printf("RTL8187B rev 0x%02x", data8); 657 break; 658 } 659 } 660 661 urtw_read32_m(sc, URTW_RX, &data); 662 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 663 URTW_EEPROM_93C46; 664 665 error = urtw_get_rfchip(sc); 666 if (error != 0) 667 goto fail; 668 error = urtw_get_macaddr(sc); 669 if (error != 0) 670 goto fail; 671 error = urtw_get_txpwr(sc); 672 if (error != 0) 673 goto fail; 674 error = urtw_led_init(sc); /* XXX incompleted */ 675 if (error != 0) 676 goto fail; 677 678 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 679 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 680 sc->sc_currate = 3; 681 /* XXX for what? */ 682 sc->sc_preamble_mode = 2; 683 684 usb_init_task(&sc->sc_task, urtw_task, sc, 0); 685 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 0); 686 callout_init(&sc->scan_to, 0); 687 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 688 callout_init(&sc->sc_led_ch, 0); 689 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 690 691 ic->ic_ifp = ifp; 692 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 693 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 694 ic->ic_state = IEEE80211_S_INIT; 695 696 /* set device capabilities */ 697 ic->ic_caps = 698 IEEE80211_C_MONITOR | /* monitor mode supported */ 699 IEEE80211_C_TXPMGT | /* tx power management */ 700 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 701 IEEE80211_C_SHSLOT | /* short slot time supported */ 702 IEEE80211_C_WEP | /* s/w WEP */ 703 IEEE80211_C_WPA; /* WPA/RSN */ 704 705 /* set supported .11b and .11g rates */ 706 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 707 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 708 709 /* set supported .11b and .11g channels (1 through 14) */ 710 for (i = 1; i <= 14; i++) { 711 ic->ic_channels[i].ic_freq = 712 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 713 ic->ic_channels[i].ic_flags = 714 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 715 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 716 } 717 718 ifp->if_softc = sc; 719 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 720 if (sc->sc_hwrev & URTW_HWREV_8187) { 721 ifp->if_init = urtw_init; 722 } else { 723 ifp->if_init = urtw_8187b_init; 724 } 725 ifp->if_ioctl = urtw_ioctl; 726 ifp->if_start = urtw_start; 727 ifp->if_watchdog = urtw_watchdog; 728 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 729 IFQ_SET_READY(&ifp->if_snd); 730 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 731 732 if_attach(ifp); 733 ieee80211_ifattach(ic); 734 735 /* override state transition machine */ 736 sc->sc_newstate = ic->ic_newstate; 737 ic->ic_newstate = urtw_newstate; 738 ieee80211_media_init(ic, urtw_media_change, ieee80211_media_status); 739 740 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 741 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 742 &sc->sc_drvbpf); 743 744 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 745 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 746 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 747 748 sc->sc_txtap_len = sizeof sc->sc_txtapu; 749 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 750 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 751 752 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 753 754 ieee80211_announce(ic); 755 756 return; 757 fail: 758 printf(": %s failed!\n", __func__); 759 sc->sc_dying = true; 760 } 761 762 int 763 urtw_detach(device_t self, int flags) 764 { 765 struct urtw_softc *sc = device_private(self); 766 struct ifnet *ifp = &sc->sc_if; 767 int s; 768 769 s = splusb(); 770 771 sc->sc_dying = true; 772 773 callout_destroy(&sc->scan_to); 774 callout_destroy(&sc->sc_led_ch); 775 776 usb_rem_task(sc->sc_udev, &sc->sc_task); 777 usb_rem_task(sc->sc_udev, &sc->sc_ledtask); 778 779 if (ifp->if_softc != NULL) { 780 bpf_detach(ifp); 781 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 782 if_detach(ifp); 783 } 784 785 /* abort and free xfers */ 786 urtw_free_tx_data_list(sc); 787 urtw_free_rx_data_list(sc); 788 urtw_close_pipes(sc); 789 790 splx(s); 791 792 return (0); 793 } 794 795 int 796 urtw_activate(device_t self, enum devact act) 797 { 798 struct urtw_softc *sc = device_private(self); 799 800 switch (act) { 801 case DVACT_DEACTIVATE: 802 sc->sc_dying = true; 803 break; 804 } 805 806 return (0); 807 } 808 809 usbd_status 810 urtw_close_pipes(struct urtw_softc *sc) 811 { 812 usbd_status error = 0; 813 814 if (sc->sc_rxpipe != NULL) { 815 error = usbd_close_pipe(sc->sc_rxpipe); 816 if (error != 0) 817 goto fail; 818 sc->sc_rxpipe = NULL; 819 } 820 if (sc->sc_txpipe_low != NULL) { 821 error = usbd_close_pipe(sc->sc_txpipe_low); 822 if (error != 0) 823 goto fail; 824 sc->sc_txpipe_low = NULL; 825 } 826 if (sc->sc_txpipe_normal != NULL) { 827 error = usbd_close_pipe(sc->sc_txpipe_normal); 828 if (error != 0) 829 goto fail; 830 sc->sc_txpipe_normal = NULL; 831 } 832 fail: 833 return (error); 834 } 835 836 usbd_status 837 urtw_open_pipes(struct urtw_softc *sc) 838 { 839 usbd_status error; 840 841 /* 842 * NB: there is no way to distinguish each pipes so we need to hardcode 843 * pipe numbers 844 */ 845 846 /* tx pipe - low priority packets */ 847 if (sc->sc_hwrev & URTW_HWREV_8187) 848 error = usbd_open_pipe(sc->sc_iface, 0x2, 849 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 850 else 851 error = usbd_open_pipe(sc->sc_iface, 0x6, 852 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 853 if (error != 0) { 854 printf("%s: could not open Tx low pipe: %s\n", 855 device_xname(sc->sc_dev), usbd_errstr(error)); 856 goto fail; 857 } 858 /* tx pipe - normal priority packets */ 859 if (sc->sc_hwrev & URTW_HWREV_8187) 860 error = usbd_open_pipe(sc->sc_iface, 0x3, 861 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 862 else 863 error = usbd_open_pipe(sc->sc_iface, 0x7, 864 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 865 if (error != 0) { 866 printf("%s: could not open Tx normal pipe: %s\n", 867 device_xname(sc->sc_dev), usbd_errstr(error)); 868 goto fail; 869 } 870 /* rx pipe */ 871 if (sc->sc_hwrev & URTW_HWREV_8187) 872 error = usbd_open_pipe(sc->sc_iface, 0x81, 873 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 874 else 875 error = usbd_open_pipe(sc->sc_iface, 0x83, 876 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 877 if (error != 0) { 878 printf("%s: could not open Rx pipe: %s\n", 879 device_xname(sc->sc_dev), usbd_errstr(error)); 880 goto fail; 881 } 882 883 return (0); 884 fail: 885 (void)urtw_close_pipes(sc); 886 return (error); 887 } 888 889 int 890 urtw_alloc_rx_data_list(struct urtw_softc *sc) 891 { 892 int i, error; 893 894 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 895 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 896 897 data->sc = sc; 898 899 data->xfer = usbd_alloc_xfer(sc->sc_udev); 900 if (data->xfer == NULL) { 901 printf("%s: could not allocate rx xfer\n", 902 device_xname(sc->sc_dev)); 903 error = ENOMEM; 904 goto fail; 905 } 906 907 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 908 printf("%s: could not allocate rx buffer\n", 909 device_xname(sc->sc_dev)); 910 error = ENOMEM; 911 goto fail; 912 } 913 914 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 915 if (data->m == NULL) { 916 printf("%s: could not allocate rx mbuf\n", 917 device_xname(sc->sc_dev)); 918 error = ENOMEM; 919 goto fail; 920 } 921 MCLGET(data->m, M_DONTWAIT); 922 if (!(data->m->m_flags & M_EXT)) { 923 printf("%s: could not allocate rx mbuf cluster\n", 924 device_xname(sc->sc_dev)); 925 error = ENOMEM; 926 goto fail; 927 } 928 data->buf = mtod(data->m, uint8_t *); 929 } 930 931 return (0); 932 933 fail: 934 urtw_free_rx_data_list(sc); 935 return (error); 936 } 937 938 void 939 urtw_free_rx_data_list(struct urtw_softc *sc) 940 { 941 int i; 942 943 /* Make sure no transfers are pending. */ 944 if (sc->sc_rxpipe != NULL) 945 usbd_abort_pipe(sc->sc_rxpipe); 946 947 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 948 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 949 950 if (data->xfer != NULL) { 951 usbd_free_xfer(data->xfer); 952 data->xfer = NULL; 953 } 954 if (data->m != NULL) { 955 m_freem(data->m); 956 data->m = NULL; 957 } 958 } 959 } 960 961 int 962 urtw_alloc_tx_data_list(struct urtw_softc *sc) 963 { 964 int i, error; 965 966 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 967 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 968 969 data->sc = sc; 970 data->ni = NULL; 971 972 data->xfer = usbd_alloc_xfer(sc->sc_udev); 973 if (data->xfer == NULL) { 974 printf("%s: could not allocate tx xfer\n", 975 device_xname(sc->sc_dev)); 976 error = ENOMEM; 977 goto fail; 978 } 979 980 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 981 if (data->buf == NULL) { 982 printf("%s: could not allocate tx buffer\n", 983 device_xname(sc->sc_dev)); 984 error = ENOMEM; 985 goto fail; 986 } 987 988 if (((unsigned long)data->buf) % 4) 989 printf("%s: warn: unaligned buffer %p\n", 990 device_xname(sc->sc_dev), data->buf); 991 } 992 993 return (0); 994 995 fail: 996 urtw_free_tx_data_list(sc); 997 return (error); 998 } 999 1000 void 1001 urtw_free_tx_data_list(struct urtw_softc *sc) 1002 { 1003 int i; 1004 1005 /* Make sure no transfers are pending. */ 1006 if (sc->sc_txpipe_low != NULL) 1007 usbd_abort_pipe(sc->sc_txpipe_low); 1008 if (sc->sc_txpipe_normal != NULL) 1009 usbd_abort_pipe(sc->sc_txpipe_normal); 1010 1011 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1012 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 1013 1014 if (data->xfer != NULL) { 1015 usbd_free_xfer(data->xfer); 1016 data->xfer = NULL; 1017 } 1018 if (data->ni != NULL) { 1019 ieee80211_free_node(data->ni); 1020 data->ni = NULL; 1021 } 1022 } 1023 } 1024 1025 int 1026 urtw_media_change(struct ifnet *ifp) 1027 { 1028 int error; 1029 1030 error = ieee80211_media_change(ifp); 1031 if (error != ENETRESET) 1032 return (error); 1033 1034 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1035 (IFF_UP | IFF_RUNNING)) 1036 ifp->if_init(ifp); 1037 1038 return (0); 1039 } 1040 1041 int 1042 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1043 { 1044 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1045 1046 usb_rem_task(sc->sc_udev, &sc->sc_task); 1047 callout_stop(&sc->scan_to); 1048 1049 /* do it in a process context */ 1050 sc->sc_state = nstate; 1051 sc->sc_arg = arg; 1052 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1053 1054 return (0); 1055 } 1056 1057 usbd_status 1058 urtw_led_init(struct urtw_softc *sc) 1059 { 1060 uint32_t rev; 1061 usbd_status error; 1062 1063 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1064 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1065 if (error != 0) 1066 goto fail; 1067 1068 switch (rev & URTW_EPROM_CID_MASK) { 1069 case URTW_EPROM_CID_ALPHA0: 1070 sc->sc_strategy = URTW_SW_LED_MODE1; 1071 break; 1072 case URTW_EPROM_CID_SERCOMM_PS: 1073 sc->sc_strategy = URTW_SW_LED_MODE3; 1074 break; 1075 case URTW_EPROM_CID_HW_LED: 1076 sc->sc_strategy = URTW_HW_LED; 1077 break; 1078 case URTW_EPROM_CID_RSVD0: 1079 case URTW_EPROM_CID_RSVD1: 1080 default: 1081 sc->sc_strategy = URTW_SW_LED_MODE0; 1082 break; 1083 } 1084 1085 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1086 1087 fail: 1088 return (error); 1089 } 1090 1091 usbd_status 1092 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1093 uint16_t data) 1094 { 1095 usb_device_request_t req; 1096 1097 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1098 req.bRequest = URTW_8187_SETREGS_REQ; 1099 USETW(req.wValue, addr); 1100 USETW(req.wIndex, index); 1101 USETW(req.wLength, sizeof(uint16_t)); 1102 1103 return (usbd_do_request(sc->sc_udev, &req, &data)); 1104 } 1105 1106 usbd_status 1107 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1108 { 1109 int i; 1110 int16_t bit; 1111 uint8_t rlen = 12, wlen = 6; 1112 uint16_t o1, o2, o3, tmp; 1113 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1114 uint32_t mask = 0x80000000, value = 0; 1115 usbd_status error; 1116 1117 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1118 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1119 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1120 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1121 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1122 o1 &= ~0xf; 1123 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1124 DELAY(5); 1125 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1126 DELAY(5); 1127 1128 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1129 bit = ((d2w & mask) != 0) ? 1 : 0; 1130 1131 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1132 DELAY(2); 1133 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1134 URTW_BB_HOST_BANG_CLK); 1135 DELAY(2); 1136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1137 URTW_BB_HOST_BANG_CLK); 1138 DELAY(2); 1139 mask = mask >> 1; 1140 if (i == 2) 1141 break; 1142 bit = ((d2w & mask) != 0) ? 1 : 0; 1143 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1144 URTW_BB_HOST_BANG_CLK); 1145 DELAY(2); 1146 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1147 URTW_BB_HOST_BANG_CLK); 1148 DELAY(2); 1149 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1150 DELAY(1); 1151 } 1152 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1153 URTW_BB_HOST_BANG_CLK); 1154 DELAY(2); 1155 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1156 DELAY(2); 1157 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1158 DELAY(2); 1159 1160 mask = 0x800; 1161 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1162 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1163 o1 | URTW_BB_HOST_BANG_RW); 1164 DELAY(2); 1165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1166 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1167 DELAY(2); 1168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1169 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1170 DELAY(2); 1171 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1172 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1173 DELAY(2); 1174 1175 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1176 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1177 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1178 o1 | URTW_BB_HOST_BANG_RW); 1179 DELAY(2); 1180 } 1181 1182 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1183 URTW_BB_HOST_BANG_RW); 1184 DELAY(2); 1185 1186 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1187 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1188 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1189 1190 if (data != NULL) 1191 *data = value; 1192 fail: 1193 return (error); 1194 } 1195 1196 usbd_status 1197 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1198 { 1199 uint16_t d80, d82, d84; 1200 usbd_status error; 1201 1202 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1203 d80 &= 0xfff3; 1204 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1205 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1206 d84 &= 0xfff0; 1207 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1208 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1209 DELAY(10); 1210 1211 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1212 DELAY(2); 1213 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1214 DELAY(10); 1215 1216 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1217 if (error != 0) 1218 goto fail; 1219 1220 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1221 DELAY(10); 1222 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1223 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1224 usbd_delay_ms(sc->sc_udev, 2); 1225 fail: 1226 return (error); 1227 } 1228 1229 usbd_status 1230 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1231 { 1232 uint32_t data; 1233 usbd_status error; 1234 1235 *ret = 1; 1236 1237 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1238 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1239 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1240 usbd_delay_ms(sc->sc_udev, 500); 1241 1242 urtw_8225_write(sc, 0x0, 0x1b7); 1243 1244 error = urtw_8225_read(sc, 0x8, &data); 1245 if (error != 0) 1246 goto fail; 1247 if (data != 0x588) 1248 *ret = 0; 1249 else { 1250 error = urtw_8225_read(sc, 0x9, &data); 1251 if (error != 0) 1252 goto fail; 1253 if (data != 0x700) 1254 *ret = 0; 1255 } 1256 1257 urtw_8225_write(sc, 0x0, 0xb7); 1258 fail: 1259 return (error); 1260 } 1261 1262 usbd_status 1263 urtw_get_rfchip(struct urtw_softc *sc) 1264 { 1265 struct urtw_rf *rf = &sc->sc_rf; 1266 int ret; 1267 uint32_t data; 1268 usbd_status error; 1269 1270 rf->rf_sc = sc; 1271 1272 if (sc->sc_hwrev & URTW_HWREV_8187) { 1273 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1274 if (error != 0) 1275 panic("unsupported RF chip"); 1276 /* NOTREACHED */ 1277 switch (data & 0xff) { 1278 case URTW_EPROM_RFCHIPID_RTL8225U: 1279 error = urtw_8225_isv2(sc, &ret); 1280 if (error != 0) 1281 goto fail; 1282 if (ret == 0) { 1283 rf->init = urtw_8225_rf_init; 1284 rf->set_chan = urtw_8225_rf_set_chan; 1285 rf->set_sens = urtw_8225_rf_set_sens; 1286 printf(", RFv1"); 1287 } else { 1288 rf->init = urtw_8225v2_rf_init; 1289 rf->set_chan = urtw_8225v2_rf_set_chan; 1290 rf->set_sens = NULL; 1291 printf(", RFv2"); 1292 } 1293 break; 1294 default: 1295 goto fail; 1296 } 1297 } else { 1298 rf->init = urtw_8225v2_b_rf_init; 1299 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1300 rf->set_sens = NULL; 1301 } 1302 1303 rf->max_sens = URTW_8225_RF_MAX_SENS; 1304 rf->sens = URTW_8225_RF_DEF_SENS; 1305 1306 return (0); 1307 1308 fail: 1309 panic("unsupported RF chip %d", data & 0xff); 1310 /* NOTREACHED */ 1311 } 1312 1313 usbd_status 1314 urtw_get_txpwr(struct urtw_softc *sc) 1315 { 1316 int i, j; 1317 uint32_t data; 1318 usbd_status error; 1319 1320 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1321 if (error != 0) 1322 goto fail; 1323 sc->sc_txpwr_cck_base = data & 0xf; 1324 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1325 1326 for (i = 1, j = 0; i < 6; i += 2, j++) { 1327 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1328 if (error != 0) 1329 goto fail; 1330 sc->sc_txpwr_cck[i] = data & 0xf; 1331 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1332 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1333 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1334 } 1335 for (i = 1, j = 0; i < 4; i += 2, j++) { 1336 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1337 if (error != 0) 1338 goto fail; 1339 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1340 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1341 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1342 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1343 } 1344 if (sc->sc_hwrev & URTW_HWREV_8187) { 1345 for (i = 1, j = 0; i < 4; i += 2, j++) { 1346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1347 &data); 1348 if (error != 0) 1349 goto fail; 1350 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1351 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1352 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1353 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1354 (data & 0xf000) >> 12; 1355 } 1356 } else { 1357 /* Channel 11. */ 1358 error = urtw_eprom_read32(sc, 0x1b, &data); 1359 if (error != 0) 1360 goto fail; 1361 sc->sc_txpwr_cck[11] = data & 0xf; 1362 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1363 1364 /* Channel 12. */ 1365 error = urtw_eprom_read32(sc, 0xa, &data); 1366 if (error != 0) 1367 goto fail; 1368 sc->sc_txpwr_cck[12] = data & 0xf; 1369 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1370 1371 /* Channel 13, 14. */ 1372 error = urtw_eprom_read32(sc, 0x1c, &data); 1373 if (error != 0) 1374 goto fail; 1375 sc->sc_txpwr_cck[13] = data & 0xf; 1376 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1377 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1378 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1379 } 1380 fail: 1381 return (error); 1382 } 1383 1384 usbd_status 1385 urtw_get_macaddr(struct urtw_softc *sc) 1386 { 1387 struct ieee80211com *ic = &sc->sc_ic; 1388 usbd_status error; 1389 uint32_t data; 1390 1391 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1392 if (error != 0) 1393 goto fail; 1394 ic->ic_myaddr[0] = data & 0xff; 1395 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1396 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1397 if (error != 0) 1398 goto fail; 1399 ic->ic_myaddr[2] = data & 0xff; 1400 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1401 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1402 if (error != 0) 1403 goto fail; 1404 ic->ic_myaddr[4] = data & 0xff; 1405 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1406 fail: 1407 return (error); 1408 } 1409 1410 usbd_status 1411 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1412 { 1413 #define URTW_READCMD_LEN 3 1414 int addrlen, i; 1415 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1416 usbd_status error; 1417 1418 /* NB: make sure the buffer is initialized */ 1419 *data = 0; 1420 1421 /* enable EPROM programming */ 1422 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1423 DELAY(URTW_EPROM_DELAY); 1424 1425 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1426 if (error != 0) 1427 goto fail; 1428 error = urtw_eprom_ck(sc); 1429 if (error != 0) 1430 goto fail; 1431 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1432 if (error != 0) 1433 goto fail; 1434 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1435 addrlen = 8; 1436 addrstr[0] = addr & (1 << 7); 1437 addrstr[1] = addr & (1 << 6); 1438 addrstr[2] = addr & (1 << 5); 1439 addrstr[3] = addr & (1 << 4); 1440 addrstr[4] = addr & (1 << 3); 1441 addrstr[5] = addr & (1 << 2); 1442 addrstr[6] = addr & (1 << 1); 1443 addrstr[7] = addr & (1 << 0); 1444 } else { 1445 addrlen=6; 1446 addrstr[0] = addr & (1 << 5); 1447 addrstr[1] = addr & (1 << 4); 1448 addrstr[2] = addr & (1 << 3); 1449 addrstr[3] = addr & (1 << 2); 1450 addrstr[4] = addr & (1 << 1); 1451 addrstr[5] = addr & (1 << 0); 1452 } 1453 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1454 if (error != 0) 1455 goto fail; 1456 1457 error = urtw_eprom_writebit(sc, 0); 1458 if (error != 0) 1459 goto fail; 1460 1461 for (i = 0; i < 16; i++) { 1462 error = urtw_eprom_ck(sc); 1463 if (error != 0) 1464 goto fail; 1465 error = urtw_eprom_readbit(sc, &data16); 1466 if (error != 0) 1467 goto fail; 1468 1469 (*data) |= (data16 << (15 - i)); 1470 } 1471 1472 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1473 if (error != 0) 1474 goto fail; 1475 error = urtw_eprom_ck(sc); 1476 if (error != 0) 1477 goto fail; 1478 1479 /* now disable EPROM programming */ 1480 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1481 fail: 1482 return (error); 1483 #undef URTW_READCMD_LEN 1484 } 1485 1486 usbd_status 1487 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1488 { 1489 uint8_t data8; 1490 usbd_status error; 1491 1492 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1493 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1494 DELAY(URTW_EPROM_DELAY); 1495 1496 fail: 1497 return (error); 1498 } 1499 1500 usbd_status 1501 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1502 { 1503 int i = 0; 1504 usbd_status error = 0; 1505 1506 for (i = 0; i < buflen; i++) { 1507 error = urtw_eprom_writebit(sc, buf[i]); 1508 if (error != 0) 1509 goto fail; 1510 error = urtw_eprom_ck(sc); 1511 if (error != 0) 1512 goto fail; 1513 } 1514 fail: 1515 return (error); 1516 } 1517 1518 usbd_status 1519 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1520 { 1521 uint8_t data; 1522 usbd_status error; 1523 1524 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1525 if (bit != 0) 1526 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1527 else 1528 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1529 DELAY(URTW_EPROM_DELAY); 1530 fail: 1531 return (error); 1532 } 1533 1534 usbd_status 1535 urtw_eprom_ck(struct urtw_softc *sc) 1536 { 1537 uint8_t data; 1538 usbd_status error; 1539 1540 /* masking */ 1541 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1542 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1543 DELAY(URTW_EPROM_DELAY); 1544 /* unmasking */ 1545 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1546 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1547 DELAY(URTW_EPROM_DELAY); 1548 fail: 1549 return (error); 1550 } 1551 1552 usbd_status 1553 urtw_eprom_cs(struct urtw_softc *sc, int able) 1554 { 1555 uint8_t data; 1556 usbd_status error; 1557 1558 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1559 if (able == URTW_EPROM_ENABLE) 1560 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1561 else 1562 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1563 DELAY(URTW_EPROM_DELAY); 1564 fail: 1565 return (error); 1566 } 1567 1568 usbd_status 1569 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1570 { 1571 usb_device_request_t req; 1572 usbd_status error; 1573 1574 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1575 req.bRequest = URTW_8187_GETREGS_REQ; 1576 USETW(req.wValue, val | 0xff00); 1577 USETW(req.wIndex, idx & 0x03); 1578 USETW(req.wLength, sizeof(uint8_t)); 1579 1580 error = usbd_do_request(sc->sc_udev, &req, data); 1581 return (error); 1582 } 1583 1584 usbd_status 1585 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1586 { 1587 usb_device_request_t req; 1588 usbd_status error; 1589 1590 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1591 req.bRequest = URTW_8187_GETREGS_REQ; 1592 USETW(req.wValue, val | 0xfe00); 1593 USETW(req.wIndex, 0); 1594 USETW(req.wLength, sizeof(uint8_t)); 1595 1596 error = usbd_do_request(sc->sc_udev, &req, data); 1597 return (error); 1598 } 1599 1600 usbd_status 1601 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1602 { 1603 usb_device_request_t req; 1604 usbd_status error; 1605 1606 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1607 req.bRequest = URTW_8187_GETREGS_REQ; 1608 USETW(req.wValue, val | 0xff00); 1609 USETW(req.wIndex, idx & 0x03); 1610 USETW(req.wLength, sizeof(uint16_t)); 1611 1612 error = usbd_do_request(sc->sc_udev, &req, data); 1613 return (error); 1614 } 1615 1616 usbd_status 1617 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1618 { 1619 usb_device_request_t req; 1620 usbd_status error; 1621 1622 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1623 req.bRequest = URTW_8187_GETREGS_REQ; 1624 USETW(req.wValue, val | 0xff00); 1625 USETW(req.wIndex, idx & 0x03); 1626 USETW(req.wLength, sizeof(uint32_t)); 1627 1628 error = usbd_do_request(sc->sc_udev, &req, data); 1629 return (error); 1630 } 1631 1632 usbd_status 1633 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1634 { 1635 usb_device_request_t req; 1636 1637 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1638 req.bRequest = URTW_8187_SETREGS_REQ; 1639 USETW(req.wValue, val | 0xff00); 1640 USETW(req.wIndex, idx & 0x03); 1641 USETW(req.wLength, sizeof(uint8_t)); 1642 1643 return (usbd_do_request(sc->sc_udev, &req, &data)); 1644 } 1645 1646 usbd_status 1647 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1648 { 1649 usb_device_request_t req; 1650 1651 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1652 req.bRequest = URTW_8187_SETREGS_REQ; 1653 USETW(req.wValue, val | 0xfe00); 1654 USETW(req.wIndex, 0); 1655 USETW(req.wLength, sizeof(uint8_t)); 1656 1657 return (usbd_do_request(sc->sc_udev, &req, &data)); 1658 } 1659 1660 usbd_status 1661 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1662 { 1663 usb_device_request_t req; 1664 1665 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1666 req.bRequest = URTW_8187_SETREGS_REQ; 1667 USETW(req.wValue, val | 0xff00); 1668 USETW(req.wIndex, idx & 0x03); 1669 USETW(req.wLength, sizeof(uint16_t)); 1670 1671 return (usbd_do_request(sc->sc_udev, &req, &data)); 1672 } 1673 1674 usbd_status 1675 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1676 { 1677 usb_device_request_t req; 1678 1679 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1680 req.bRequest = URTW_8187_SETREGS_REQ; 1681 USETW(req.wValue, val | 0xff00); 1682 USETW(req.wIndex, idx & 0x03); 1683 USETW(req.wLength, sizeof(uint32_t)); 1684 1685 return (usbd_do_request(sc->sc_udev, &req, &data)); 1686 } 1687 1688 static usbd_status 1689 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1690 { 1691 uint8_t data; 1692 usbd_status error; 1693 1694 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1695 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1696 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1697 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1698 fail: 1699 return (error); 1700 } 1701 1702 usbd_status 1703 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1704 { 1705 uint8_t data; 1706 usbd_status error; 1707 1708 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1709 if (error) 1710 goto fail; 1711 1712 urtw_read8_m(sc, URTW_CONFIG3, &data); 1713 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1714 urtw_write32_m(sc, URTW_ANAPARAM, val); 1715 urtw_read8_m(sc, URTW_CONFIG3, &data); 1716 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1717 1718 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1719 if (error) 1720 goto fail; 1721 fail: 1722 return (error); 1723 } 1724 1725 usbd_status 1726 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1727 { 1728 uint8_t data; 1729 usbd_status error; 1730 1731 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1732 if (error) 1733 goto fail; 1734 1735 urtw_read8_m(sc, URTW_CONFIG3, &data); 1736 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1737 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1738 urtw_read8_m(sc, URTW_CONFIG3, &data); 1739 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1740 1741 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1742 if (error) 1743 goto fail; 1744 fail: 1745 return (error); 1746 } 1747 1748 usbd_status 1749 urtw_intr_disable(struct urtw_softc *sc) 1750 { 1751 usbd_status error; 1752 1753 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1754 1755 fail: 1756 return (error); 1757 } 1758 1759 usbd_status 1760 urtw_reset(struct urtw_softc *sc) 1761 { 1762 uint8_t data; 1763 usbd_status error; 1764 1765 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1766 if (error) 1767 goto fail; 1768 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1769 if (error) 1770 goto fail; 1771 1772 error = urtw_intr_disable(sc); 1773 if (error) 1774 goto fail; 1775 usbd_delay_ms(sc->sc_udev, 100); 1776 1777 error = urtw_write8e(sc, 0x18, 0x10); 1778 if (error != 0) 1779 goto fail; 1780 error = urtw_write8e(sc, 0x18, 0x11); 1781 if (error != 0) 1782 goto fail; 1783 error = urtw_write8e(sc, 0x18, 0x00); 1784 if (error != 0) 1785 goto fail; 1786 usbd_delay_ms(sc->sc_udev, 100); 1787 1788 urtw_read8_m(sc, URTW_CMD, &data); 1789 data = (data & 2) | URTW_CMD_RST; 1790 urtw_write8_m(sc, URTW_CMD, data); 1791 usbd_delay_ms(sc->sc_udev, 100); 1792 1793 urtw_read8_m(sc, URTW_CMD, &data); 1794 if (data & URTW_CMD_RST) { 1795 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1796 goto fail; 1797 } 1798 1799 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1800 if (error) 1801 goto fail; 1802 usbd_delay_ms(sc->sc_udev, 100); 1803 1804 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1805 if (error) 1806 goto fail; 1807 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1808 if (error) 1809 goto fail; 1810 fail: 1811 return (error); 1812 } 1813 1814 usbd_status 1815 urtw_led_on(struct urtw_softc *sc, int type) 1816 { 1817 usbd_status error; 1818 1819 if (type == URTW_LED_GPIO) { 1820 switch (sc->sc_gpio_ledpin) { 1821 case URTW_LED_PIN_GPIO0: 1822 urtw_write8_m(sc, URTW_GPIO, 0x01); 1823 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1824 break; 1825 default: 1826 panic("unsupported LED PIN type 0x%x", 1827 sc->sc_gpio_ledpin); 1828 /* NOTREACHED */ 1829 } 1830 } else { 1831 panic("unsupported LED type 0x%x", type); 1832 /* NOTREACHED */ 1833 } 1834 1835 sc->sc_gpio_ledon = 1; 1836 fail: 1837 return (error); 1838 } 1839 1840 static usbd_status 1841 urtw_led_off(struct urtw_softc *sc, int type) 1842 { 1843 usbd_status error; 1844 1845 if (type == URTW_LED_GPIO) { 1846 switch (sc->sc_gpio_ledpin) { 1847 case URTW_LED_PIN_GPIO0: 1848 urtw_write8_m(sc, URTW_GPIO, 0x01); 1849 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1850 break; 1851 default: 1852 panic("unsupported LED PIN type 0x%x", 1853 sc->sc_gpio_ledpin); 1854 /* NOTREACHED */ 1855 } 1856 } else { 1857 panic("unsupported LED type 0x%x", type); 1858 /* NOTREACHED */ 1859 } 1860 1861 sc->sc_gpio_ledon = 0; 1862 1863 fail: 1864 return (error); 1865 } 1866 1867 usbd_status 1868 urtw_led_mode0(struct urtw_softc *sc, int mode) 1869 { 1870 switch (mode) { 1871 case URTW_LED_CTL_POWER_ON: 1872 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1873 break; 1874 case URTW_LED_CTL_TX: 1875 if (sc->sc_gpio_ledinprogress == 1) 1876 return (0); 1877 1878 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1879 sc->sc_gpio_blinktime = 2; 1880 break; 1881 case URTW_LED_CTL_LINK: 1882 sc->sc_gpio_ledstate = URTW_LED_ON; 1883 break; 1884 default: 1885 panic("unsupported LED mode 0x%x", mode); 1886 /* NOTREACHED */ 1887 } 1888 1889 switch (sc->sc_gpio_ledstate) { 1890 case URTW_LED_ON: 1891 if (sc->sc_gpio_ledinprogress != 0) 1892 break; 1893 urtw_led_on(sc, URTW_LED_GPIO); 1894 break; 1895 case URTW_LED_BLINK_NORMAL: 1896 if (sc->sc_gpio_ledinprogress != 0) 1897 break; 1898 sc->sc_gpio_ledinprogress = 1; 1899 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1900 URTW_LED_OFF : URTW_LED_ON; 1901 if (!sc->sc_dying) 1902 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1903 break; 1904 case URTW_LED_POWER_ON_BLINK: 1905 urtw_led_on(sc, URTW_LED_GPIO); 1906 usbd_delay_ms(sc->sc_udev, 100); 1907 urtw_led_off(sc, URTW_LED_GPIO); 1908 break; 1909 default: 1910 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 1911 /* NOTREACHED */ 1912 } 1913 return (0); 1914 } 1915 1916 usbd_status 1917 urtw_led_mode1(struct urtw_softc *sc, int mode) 1918 { 1919 return (USBD_INVAL); 1920 } 1921 1922 usbd_status 1923 urtw_led_mode2(struct urtw_softc *sc, int mode) 1924 { 1925 return (USBD_INVAL); 1926 } 1927 1928 usbd_status 1929 urtw_led_mode3(struct urtw_softc *sc, int mode) 1930 { 1931 return (USBD_INVAL); 1932 } 1933 1934 void 1935 urtw_ledusbtask(void *arg) 1936 { 1937 struct urtw_softc *sc = arg; 1938 1939 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1940 panic("could not process a LED strategy 0x%x", sc->sc_strategy); 1941 1942 urtw_led_blink(sc); 1943 } 1944 1945 void 1946 urtw_ledtask(void *arg) 1947 { 1948 struct urtw_softc *sc = arg; 1949 1950 /* 1951 * NB: to change a status of the led we need at least a sleep so we 1952 * can't do it here 1953 */ 1954 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1955 } 1956 1957 usbd_status 1958 urtw_led_ctl(struct urtw_softc *sc, int mode) 1959 { 1960 usbd_status error = 0; 1961 1962 switch (sc->sc_strategy) { 1963 case URTW_SW_LED_MODE0: 1964 error = urtw_led_mode0(sc, mode); 1965 break; 1966 case URTW_SW_LED_MODE1: 1967 error = urtw_led_mode1(sc, mode); 1968 break; 1969 case URTW_SW_LED_MODE2: 1970 error = urtw_led_mode2(sc, mode); 1971 break; 1972 case URTW_SW_LED_MODE3: 1973 error = urtw_led_mode3(sc, mode); 1974 break; 1975 default: 1976 panic("unsupported LED mode %d", sc->sc_strategy); 1977 /* NOTREACHED */ 1978 } 1979 1980 return (error); 1981 } 1982 1983 usbd_status 1984 urtw_led_blink(struct urtw_softc *sc) 1985 { 1986 uint8_t ing = 0; 1987 1988 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1989 (void)urtw_led_on(sc, URTW_LED_GPIO); 1990 else 1991 (void)urtw_led_off(sc, URTW_LED_GPIO); 1992 sc->sc_gpio_blinktime--; 1993 if (sc->sc_gpio_blinktime == 0) 1994 ing = 1; 1995 else { 1996 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1997 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1998 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 1999 ing = 1; 2000 } 2001 if (ing == 1) { 2002 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2003 sc->sc_gpio_ledon == 0) 2004 (void)urtw_led_on(sc, URTW_LED_GPIO); 2005 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2006 sc->sc_gpio_ledon == 1) 2007 (void)urtw_led_off(sc, URTW_LED_GPIO); 2008 2009 sc->sc_gpio_blinktime = 0; 2010 sc->sc_gpio_ledinprogress = 0; 2011 return (0); 2012 } 2013 2014 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2015 URTW_LED_ON : URTW_LED_OFF; 2016 2017 switch (sc->sc_gpio_ledstate) { 2018 case URTW_LED_BLINK_NORMAL: 2019 if (!sc->sc_dying) 2020 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2021 break; 2022 default: 2023 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 2024 /* NOTREACHED */ 2025 } 2026 return (0); 2027 } 2028 2029 usbd_status 2030 urtw_update_msr(struct urtw_softc *sc) 2031 { 2032 struct ieee80211com *ic = &sc->sc_ic; 2033 uint8_t data; 2034 usbd_status error; 2035 2036 urtw_read8_m(sc, URTW_MSR, &data); 2037 data &= ~URTW_MSR_LINK_MASK; 2038 2039 /* Should always be set. */ 2040 if (sc->sc_hwrev & URTW_HWREV_8187B) 2041 data |= URTW_MSR_LINK_ENEDCA; 2042 2043 if (sc->sc_state == IEEE80211_S_RUN) { 2044 switch (ic->ic_opmode) { 2045 case IEEE80211_M_STA: 2046 case IEEE80211_M_MONITOR: 2047 data |= URTW_MSR_LINK_STA; 2048 break; 2049 default: 2050 panic("unsupported operation mode 0x%x", 2051 ic->ic_opmode); 2052 /* NOTREACHED */ 2053 } 2054 } else 2055 data |= URTW_MSR_LINK_NONE; 2056 2057 urtw_write8_m(sc, URTW_MSR, data); 2058 fail: 2059 return (error); 2060 } 2061 2062 uint16_t 2063 urtw_rate2rtl(int rate) 2064 { 2065 unsigned int i; 2066 2067 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2068 if (rate == urtw_ratetable[i].reg) 2069 return (urtw_ratetable[i].val); 2070 } 2071 2072 return (3); 2073 } 2074 2075 uint16_t 2076 urtw_rtl2rate(int rate) 2077 { 2078 unsigned int i; 2079 2080 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2081 if (rate == urtw_ratetable[i].val) 2082 return (urtw_ratetable[i].reg); 2083 } 2084 2085 return (0); 2086 } 2087 2088 usbd_status 2089 urtw_set_rate(struct urtw_softc *sc) 2090 { 2091 int i, basic_rate, min_rr_rate, max_rr_rate; 2092 uint16_t data; 2093 usbd_status error; 2094 2095 basic_rate = urtw_rate2rtl(48); 2096 min_rr_rate = urtw_rate2rtl(12); 2097 max_rr_rate = urtw_rate2rtl(48); 2098 2099 urtw_write8_m(sc, URTW_RESP_RATE, 2100 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2101 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2102 2103 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2104 data &= ~URTW_BRSR_MBR_8185; 2105 2106 for (i = 0; i <= basic_rate; i++) 2107 data |= (1 << i); 2108 2109 urtw_write16_m(sc, URTW_8187_BRSR, data); 2110 fail: 2111 return (error); 2112 } 2113 2114 usbd_status 2115 urtw_intr_enable(struct urtw_softc *sc) 2116 { 2117 usbd_status error; 2118 2119 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2120 fail: 2121 return (error); 2122 } 2123 2124 usbd_status 2125 urtw_rx_setconf(struct urtw_softc *sc) 2126 { 2127 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2128 struct ieee80211com *ic = &sc->sc_ic; 2129 uint32_t data; 2130 usbd_status error; 2131 2132 urtw_read32_m(sc, URTW_RX, &data); 2133 data = data &~ URTW_RX_FILTER_MASK; 2134 #if 0 2135 data = data | URTW_RX_FILTER_CTL; 2136 #endif 2137 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2138 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2139 2140 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2141 data = data | URTW_RX_FILTER_ICVERR; 2142 data = data | URTW_RX_FILTER_PWR; 2143 } 2144 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2145 data = data | URTW_RX_FILTER_CRCERR; 2146 2147 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2148 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2149 data = data | URTW_RX_FILTER_ALLMAC; 2150 } else { 2151 data = data | URTW_RX_FILTER_NICMAC; 2152 data = data | URTW_RX_CHECK_BSSID; 2153 } 2154 2155 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2156 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2157 data = data &~ URTW_MAX_RX_DMA_MASK; 2158 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2159 2160 urtw_write32_m(sc, URTW_RX, data); 2161 fail: 2162 return (error); 2163 } 2164 2165 usbd_status 2166 urtw_rx_enable(struct urtw_softc *sc) 2167 { 2168 int i; 2169 struct urtw_rx_data *rx_data; 2170 uint8_t data; 2171 usbd_status error; 2172 2173 /* 2174 * Start up the receive pipe. 2175 */ 2176 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2177 rx_data = &sc->sc_rx_data[i]; 2178 2179 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2180 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2181 USBD_NO_TIMEOUT, urtw_rxeof); 2182 error = usbd_transfer(rx_data->xfer); 2183 if (error != USBD_IN_PROGRESS && error != 0) { 2184 printf("%s: could not queue Rx transfer\n", 2185 device_xname(sc->sc_dev)); 2186 goto fail; 2187 } 2188 } 2189 2190 error = urtw_rx_setconf(sc); 2191 if (error != 0) 2192 goto fail; 2193 2194 urtw_read8_m(sc, URTW_CMD, &data); 2195 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2196 fail: 2197 return (error); 2198 } 2199 2200 usbd_status 2201 urtw_tx_enable(struct urtw_softc *sc) 2202 { 2203 uint8_t data8; 2204 uint32_t data; 2205 usbd_status error; 2206 2207 if (sc->sc_hwrev & URTW_HWREV_8187) { 2208 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2209 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2210 URTW_CW_CONF_PERPACKET_RETRY); 2211 urtw_write8_m(sc, URTW_CW_CONF, data8); 2212 2213 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2214 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2215 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2216 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2217 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2218 2219 urtw_read32_m(sc, URTW_TX_CONF, &data); 2220 data &= ~URTW_TX_LOOPBACK_MASK; 2221 data |= URTW_TX_LOOPBACK_NONE; 2222 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2223 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2224 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2225 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2226 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2227 data &= ~URTW_TX_SWPLCPLEN; 2228 data |= URTW_TX_NOICV; 2229 urtw_write32_m(sc, URTW_TX_CONF, data); 2230 } else { 2231 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2232 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2233 URTW_TX_LONGRETRY; 2234 urtw_write32_m(sc, URTW_TX_CONF, data); 2235 } 2236 2237 urtw_read8_m(sc, URTW_CMD, &data8); 2238 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2239 fail: 2240 return (error); 2241 } 2242 2243 int 2244 urtw_init(struct ifnet *ifp) 2245 { 2246 struct urtw_softc *sc = ifp->if_softc; 2247 struct urtw_rf *rf = &sc->sc_rf; 2248 struct ieee80211com *ic = &sc->sc_ic; 2249 usbd_status error; 2250 2251 urtw_stop(ifp, 0); 2252 2253 error = urtw_reset(sc); 2254 if (error) 2255 goto fail; 2256 2257 urtw_write8_m(sc, 0x85, 0); 2258 urtw_write8_m(sc, URTW_GPIO, 0); 2259 2260 /* for led */ 2261 urtw_write8_m(sc, 0x85, 4); 2262 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2263 if (error != 0) 2264 goto fail; 2265 2266 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2267 if (error) 2268 goto fail; 2269 2270 /* applying MAC address again. */ 2271 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2272 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2273 if (error) 2274 goto fail; 2275 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2276 if (error) 2277 goto fail; 2278 2279 error = urtw_update_msr(sc); 2280 if (error) 2281 goto fail; 2282 2283 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2284 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2285 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2286 error = urtw_set_rate(sc); 2287 if (error != 0) 2288 goto fail; 2289 2290 error = rf->init(rf); 2291 if (error != 0) 2292 goto fail; 2293 if (rf->set_sens != NULL) 2294 rf->set_sens(rf); 2295 2296 urtw_write16_m(sc, 0x5e, 1); 2297 urtw_write16_m(sc, 0xfe, 0x10); 2298 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2299 urtw_write8_m(sc, 0xff, 0x60); 2300 urtw_write16_m(sc, 0x5e, 0); 2301 urtw_write8_m(sc, 0x85, 4); 2302 2303 error = urtw_intr_enable(sc); 2304 if (error != 0) 2305 goto fail; 2306 2307 /* reset softc variables */ 2308 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2309 sc->sc_txtimer = 0; 2310 2311 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2312 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2313 if (error != 0) { 2314 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2315 ", err=%s\n", usbd_errstr(error)); 2316 goto fail; 2317 } 2318 /* get the first interface handle */ 2319 error = usbd_device2interface_handle(sc->sc_udev, 2320 URTW_IFACE_INDEX, &sc->sc_iface); 2321 if (error != 0) { 2322 printf("%s: could not get interface handle\n", 2323 device_xname(sc->sc_dev)); 2324 goto fail; 2325 } 2326 error = urtw_open_pipes(sc); 2327 if (error != 0) 2328 goto fail; 2329 error = urtw_alloc_rx_data_list(sc); 2330 if (error != 0) 2331 goto fail; 2332 error = urtw_alloc_tx_data_list(sc); 2333 if (error != 0) 2334 goto fail; 2335 sc->sc_flags |= URTW_INIT_ONCE; 2336 } 2337 2338 error = urtw_rx_enable(sc); 2339 if (error != 0) 2340 goto fail; 2341 error = urtw_tx_enable(sc); 2342 if (error != 0) 2343 goto fail; 2344 2345 ifp->if_flags &= ~IFF_OACTIVE; 2346 ifp->if_flags |= IFF_RUNNING; 2347 2348 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2349 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2350 else 2351 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2352 2353 return (0); 2354 fail: 2355 return (error); 2356 } 2357 2358 int 2359 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2360 { 2361 #define IS_RUNNING(ifp) \ 2362 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2363 2364 struct urtw_softc *sc = ifp->if_softc; 2365 struct ieee80211com *ic = &sc->sc_ic; 2366 int s, error = 0; 2367 2368 if (sc->sc_dying) 2369 return (ENXIO); 2370 2371 s = splnet(); 2372 2373 switch (cmd) { 2374 case SIOCSIFFLAGS: 2375 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2376 break; 2377 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2378 case IFF_UP|IFF_RUNNING: 2379 break; 2380 case IFF_UP: 2381 ifp->if_init(ifp); 2382 break; 2383 case IFF_RUNNING: 2384 urtw_stop(ifp, 1); 2385 break; 2386 case 0: 2387 break; 2388 } 2389 break; 2390 2391 case SIOCADDMULTI: 2392 case SIOCDELMULTI: 2393 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2394 error = 0; 2395 break; 2396 2397 default: 2398 error = ieee80211_ioctl(ic, cmd, data); 2399 break; 2400 } 2401 2402 if (error == ENETRESET) { 2403 if (IS_RUNNING(ifp) && 2404 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2405 ifp->if_init(ifp); 2406 error = 0; 2407 } 2408 2409 splx(s); 2410 2411 return (error); 2412 #undef IS_RUNNING 2413 } 2414 2415 void 2416 urtw_start(struct ifnet *ifp) 2417 { 2418 struct urtw_softc *sc = ifp->if_softc; 2419 struct ieee80211com *ic = &sc->sc_ic; 2420 struct ieee80211_node *ni; 2421 struct ether_header *eh; 2422 struct mbuf *m0; 2423 2424 /* 2425 * net80211 may still try to send management frames even if the 2426 * IFF_RUNNING flag is not set... 2427 */ 2428 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2429 return; 2430 2431 for (;;) { 2432 IF_POLL(&ic->ic_mgtq, m0); 2433 if (m0 != NULL) { 2434 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2435 sc->sc_tx_normal_queued >= 2436 URTW_TX_DATA_LIST_COUNT) { 2437 ifp->if_flags |= IFF_OACTIVE; 2438 break; 2439 } 2440 IF_DEQUEUE(&ic->ic_mgtq, m0); 2441 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2442 m0->m_pkthdr.rcvif = NULL; 2443 bpf_mtap3(ic->ic_rawbpf, m0); 2444 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2445 != 0) 2446 break; 2447 } else { 2448 if (ic->ic_state != IEEE80211_S_RUN) 2449 break; 2450 IFQ_POLL(&ifp->if_snd, m0); 2451 if (m0 == NULL) 2452 break; 2453 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2454 sc->sc_tx_normal_queued >= 2455 URTW_TX_DATA_LIST_COUNT) { 2456 ifp->if_flags |= IFF_OACTIVE; 2457 break; 2458 } 2459 IFQ_DEQUEUE(&ifp->if_snd, m0); 2460 if (m0->m_len < sizeof(struct ether_header) && 2461 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2462 continue; 2463 2464 eh = mtod(m0, struct ether_header *); 2465 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2466 if (ni == NULL) { 2467 m_freem(m0); 2468 continue; 2469 } 2470 bpf_mtap(ifp, m0); 2471 m0 = ieee80211_encap(ic, m0, ni); 2472 if (m0 == NULL) { 2473 ieee80211_free_node(ni); 2474 continue; 2475 } 2476 bpf_mtap3(ic->ic_rawbpf, m0); 2477 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2478 != 0) { 2479 ieee80211_free_node(ni); 2480 ifp->if_oerrors++; 2481 break; 2482 } 2483 } 2484 sc->sc_txtimer = 5; 2485 ifp->if_timer = 1; 2486 } 2487 } 2488 2489 void 2490 urtw_watchdog(struct ifnet *ifp) 2491 { 2492 struct urtw_softc *sc = ifp->if_softc; 2493 2494 ifp->if_timer = 0; 2495 2496 if (sc->sc_txtimer > 0) { 2497 if (--sc->sc_txtimer == 0) { 2498 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2499 ifp->if_oerrors++; 2500 return; 2501 } 2502 ifp->if_timer = 1; 2503 } 2504 2505 ieee80211_watchdog(&sc->sc_ic); 2506 } 2507 2508 void 2509 urtw_txeof_low(usbd_xfer_handle xfer, usbd_private_handle priv, 2510 usbd_status status) 2511 { 2512 struct urtw_tx_data *data = priv; 2513 struct urtw_softc *sc = data->sc; 2514 struct ieee80211com *ic = &sc->sc_ic; 2515 struct ifnet *ifp = ic->ic_ifp; 2516 int s; 2517 2518 if (status != USBD_NORMAL_COMPLETION) { 2519 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2520 return; 2521 2522 printf("%s: could not transmit buffer: %s\n", 2523 device_xname(sc->sc_dev), usbd_errstr(status)); 2524 2525 if (status == USBD_STALLED) 2526 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2527 2528 ifp->if_oerrors++; 2529 return; 2530 } 2531 2532 s = splnet(); 2533 2534 ieee80211_free_node(data->ni); 2535 data->ni = NULL; 2536 2537 sc->sc_txtimer = 0; 2538 ifp->if_opackets++; 2539 2540 sc->sc_tx_low_queued--; 2541 ifp->if_flags &= ~IFF_OACTIVE; 2542 urtw_start(ifp); 2543 2544 splx(s); 2545 } 2546 2547 void 2548 urtw_txeof_normal(usbd_xfer_handle xfer, usbd_private_handle priv, 2549 usbd_status status) 2550 { 2551 struct urtw_tx_data *data = priv; 2552 struct urtw_softc *sc = data->sc; 2553 struct ieee80211com *ic = &sc->sc_ic; 2554 struct ifnet *ifp = ic->ic_ifp; 2555 int s; 2556 2557 if (status != USBD_NORMAL_COMPLETION) { 2558 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2559 return; 2560 2561 printf("%s: could not transmit buffer: %s\n", 2562 device_xname(sc->sc_dev), usbd_errstr(status)); 2563 2564 if (status == USBD_STALLED) 2565 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2566 2567 ifp->if_oerrors++; 2568 return; 2569 } 2570 2571 s = splnet(); 2572 2573 ieee80211_free_node(data->ni); 2574 data->ni = NULL; 2575 2576 sc->sc_txtimer = 0; 2577 ifp->if_opackets++; 2578 2579 sc->sc_tx_normal_queued--; 2580 ifp->if_flags &= ~IFF_OACTIVE; 2581 urtw_start(ifp); 2582 2583 splx(s); 2584 } 2585 2586 int 2587 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2588 int prior) 2589 { 2590 struct ieee80211com *ic = &sc->sc_ic; 2591 struct urtw_tx_data *data; 2592 struct ieee80211_frame *wh; 2593 struct ieee80211_key *k; 2594 usbd_status error; 2595 int xferlen; 2596 2597 wh = mtod(m0, struct ieee80211_frame *); 2598 2599 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2600 k = ieee80211_crypto_encap(ic, ni, m0); 2601 if (k == NULL) { 2602 m_freem(m0); 2603 return (ENOBUFS); 2604 } 2605 /* packet header may have moved, reset our local pointer */ 2606 wh = mtod(m0, struct ieee80211_frame *); 2607 } 2608 2609 if (sc->sc_drvbpf != NULL) { 2610 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2611 2612 tap->wt_flags = 0; 2613 tap->wt_rate = 0; 2614 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2615 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2616 2617 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 2618 } 2619 2620 if (sc->sc_hwrev & URTW_HWREV_8187) 2621 xferlen = m0->m_pkthdr.len + 4 * 3; 2622 else 2623 xferlen = m0->m_pkthdr.len + 4 * 8; 2624 2625 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2626 xferlen += 1; 2627 2628 data = &sc->sc_tx_data[sc->sc_txidx]; 2629 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2630 2631 bzero(data->buf, URTW_TX_MAXSIZE); 2632 data->buf[0] = m0->m_pkthdr.len & 0xff; 2633 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2634 data->buf[1] |= (1 << 7); 2635 2636 /* XXX sc_preamble_mode is always 2. */ 2637 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2638 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2639 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2640 data->buf[2] |= 1; 2641 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2642 prior == URTW_PRIORITY_LOW) 2643 panic("TODO tx."); 2644 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2645 data->buf[2] |= (1 << 1); 2646 /* RTS rate - 10 means we use a basic rate. */ 2647 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2648 /* 2649 * XXX currently TX rate control depends on the rate value of 2650 * RX descriptor because I don't know how to we can control TX rate 2651 * in more smart way. Please fix me you find a thing. 2652 */ 2653 data->buf[3] = sc->sc_currate; 2654 if (prior == URTW_PRIORITY_NORMAL) { 2655 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2656 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2657 else if (ic->ic_fixed_rate != -1) 2658 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2659 } 2660 2661 if (sc->sc_hwrev & URTW_HWREV_8187) { 2662 data->buf[8] = 3; /* CW minimum */ 2663 data->buf[8] |= (7 << 4); /* CW maximum */ 2664 data->buf[9] |= 11; /* retry limitation */ 2665 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2666 } else { 2667 data->buf[21] |= 11; /* retry limitation */ 2668 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2669 } 2670 2671 data->ni = ni; 2672 2673 /* mbuf is no longer needed. */ 2674 m_freem(m0); 2675 2676 usbd_setup_xfer(data->xfer, 2677 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2678 sc->sc_txpipe_normal, data, data->buf, xferlen, 2679 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2680 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2681 error = usbd_transfer(data->xfer); 2682 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2683 printf("%s: could not send frame: %s\n", 2684 device_xname(sc->sc_dev), usbd_errstr(error)); 2685 return (EIO); 2686 } 2687 2688 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2689 if (error != 0) 2690 printf("%s: could not control LED (%d)\n", 2691 device_xname(sc->sc_dev), error); 2692 2693 if (prior == URTW_PRIORITY_LOW) 2694 sc->sc_tx_low_queued++; 2695 else 2696 sc->sc_tx_normal_queued++; 2697 2698 return (0); 2699 } 2700 2701 usbd_status 2702 urtw_8225_usb_init(struct urtw_softc *sc) 2703 { 2704 uint8_t data; 2705 usbd_status error; 2706 2707 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2708 urtw_write8_m(sc, URTW_GPIO, 0); 2709 error = urtw_read8e(sc, 0x53, &data); 2710 if (error) 2711 goto fail; 2712 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2713 if (error) 2714 goto fail; 2715 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2716 urtw_write8_m(sc, URTW_GPIO, 0x20); 2717 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2718 2719 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2720 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2721 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2722 2723 usbd_delay_ms(sc->sc_udev, 500); 2724 fail: 2725 return (error); 2726 } 2727 2728 usbd_status 2729 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2730 { 2731 usbd_status error = 0; 2732 2733 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2734 fail: 2735 return (error); 2736 } 2737 2738 usbd_status 2739 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2740 { 2741 uint32_t phyw; 2742 usbd_status error; 2743 2744 phyw = ((data << 8) | (addr | 0x80)); 2745 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2746 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2747 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2748 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2749 /* 2750 * Delay removed from 8185 to 8187. 2751 * usbd_delay_ms(sc->sc_udev, 1); 2752 */ 2753 fail: 2754 return (error); 2755 } 2756 2757 usbd_status 2758 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2759 { 2760 data = data & 0xff; 2761 return (urtw_8187_write_phy(sc, addr, data)); 2762 } 2763 2764 usbd_status 2765 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2766 { 2767 data = data & 0xff; 2768 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2769 } 2770 2771 usbd_status 2772 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2773 { 2774 usbd_status error; 2775 2776 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2777 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2778 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2779 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2780 fail: 2781 return (error); 2782 } 2783 2784 usbd_status 2785 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2786 { 2787 int i, idx, set; 2788 uint8_t *cck_pwltable; 2789 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2790 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2791 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2792 usbd_status error; 2793 2794 cck_pwrlvl_max = 11; 2795 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2796 ofdm_pwrlvl_min = 10; 2797 2798 /* CCK power setting */ 2799 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2800 idx = cck_pwrlvl % 6; 2801 set = cck_pwrlvl / 6; 2802 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2803 urtw_8225_txpwr_cck; 2804 2805 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2806 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2807 for (i = 0; i < 8; i++) { 2808 urtw_8187_write_phy_cck(sc, 0x44 + i, 2809 cck_pwltable[idx * 8 + i]); 2810 } 2811 usbd_delay_ms(sc->sc_udev, 1); 2812 2813 /* OFDM power setting */ 2814 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2815 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2816 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2817 2818 idx = ofdm_pwrlvl % 6; 2819 set = ofdm_pwrlvl / 6; 2820 2821 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2822 if (error) 2823 goto fail; 2824 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2825 urtw_8187_write_phy_ofdm(sc, 6, 0); 2826 urtw_8187_write_phy_ofdm(sc, 8, 0); 2827 2828 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2829 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2830 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2831 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2832 usbd_delay_ms(sc->sc_udev, 1); 2833 fail: 2834 return (error); 2835 } 2836 2837 usbd_status 2838 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2839 { 2840 usbd_status error; 2841 2842 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2843 usbd_delay_ms(sc->sc_udev, 1); 2844 fail: 2845 return (error); 2846 } 2847 2848 usbd_status 2849 urtw_8225_rf_init(struct urtw_rf *rf) 2850 { 2851 struct urtw_softc *sc = rf->rf_sc; 2852 unsigned int i; 2853 uint16_t data; 2854 usbd_status error; 2855 2856 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2857 if (error) 2858 goto fail; 2859 2860 error = urtw_8225_usb_init(sc); 2861 if (error) 2862 goto fail; 2863 2864 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2865 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2866 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2867 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2868 2869 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2870 if (error) 2871 goto fail; 2872 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2873 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2874 if (error) 2875 goto fail; 2876 2877 error = urtw_8185_rf_pins_enable(sc); 2878 if (error) 2879 goto fail; 2880 2881 usbd_delay_ms(sc->sc_udev, 500); 2882 2883 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2884 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2885 urtw_8225_rf_part1[i].val); 2886 } 2887 usbd_delay_ms(sc->sc_udev, 50); 2888 urtw_8225_write(sc, 0x2, 0xc4d); 2889 usbd_delay_ms(sc->sc_udev, 200); 2890 urtw_8225_write(sc, 0x2, 0x44d); 2891 usbd_delay_ms(sc->sc_udev, 200); 2892 urtw_8225_write(sc, 0x0, 0x127); 2893 2894 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2895 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2896 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2897 } 2898 2899 urtw_8225_write(sc, 0x0, 0x27); 2900 urtw_8225_write(sc, 0x0, 0x22f); 2901 2902 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2903 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2904 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2905 } 2906 2907 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2908 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2909 urtw_8225_rf_part2[i].val); 2910 usbd_delay_ms(sc->sc_udev, 1); 2911 } 2912 2913 error = urtw_8225_setgain(sc, 4); 2914 if (error) 2915 goto fail; 2916 2917 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2918 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2919 urtw_8225_rf_part3[i].val); 2920 usbd_delay_ms(sc->sc_udev, 1); 2921 } 2922 2923 urtw_write8_m(sc, 0x5b, 0x0d); 2924 2925 error = urtw_8225_set_txpwrlvl(sc, 1); 2926 if (error) 2927 goto fail; 2928 2929 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2930 usbd_delay_ms(sc->sc_udev, 1); 2931 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2932 usbd_delay_ms(sc->sc_udev, 1); 2933 2934 /* TX ant A, 0x0 for B */ 2935 error = urtw_8185_tx_antenna(sc, 0x3); 2936 if (error) 2937 goto fail; 2938 urtw_write32_m(sc, 0x94, 0x3dc00002); 2939 2940 error = urtw_8225_rf_set_chan(rf, 1); 2941 fail: 2942 return (error); 2943 } 2944 2945 usbd_status 2946 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2947 { 2948 struct urtw_softc *sc = rf->rf_sc; 2949 struct ieee80211com *ic = &sc->sc_ic; 2950 struct ieee80211_channel *c = ic->ic_ibss_chan; 2951 usbd_status error; 2952 2953 error = urtw_8225_set_txpwrlvl(sc, chan); 2954 if (error) 2955 goto fail; 2956 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2957 usbd_delay_ms(sc->sc_udev, 10); 2958 2959 urtw_write8_m(sc, URTW_SIFS, 0x22); 2960 2961 if (sc->sc_state == IEEE80211_S_ASSOC && 2962 ic->ic_flags & IEEE80211_F_SHSLOT) 2963 urtw_write8_m(sc, URTW_SLOT, 0x9); 2964 else 2965 urtw_write8_m(sc, URTW_SLOT, 0x14); 2966 2967 if (IEEE80211_IS_CHAN_G(c)) { 2968 urtw_write8_m(sc, URTW_DIFS, 0x14); 2969 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2970 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2971 } else { 2972 urtw_write8_m(sc, URTW_DIFS, 0x24); 2973 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2974 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2975 } 2976 2977 fail: 2978 return (error); 2979 } 2980 2981 usbd_status 2982 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2983 { 2984 struct urtw_softc *sc = rf->rf_sc; 2985 usbd_status error; 2986 2987 if (rf->sens > 6) 2988 return (-1); 2989 2990 if (rf->sens > 4) 2991 urtw_8225_write(sc, 0x0c, 0x850); 2992 else 2993 urtw_8225_write(sc, 0x0c, 0x50); 2994 2995 rf->sens = 6 - rf->sens; 2996 error = urtw_8225_setgain(sc, rf->sens); 2997 if (error) 2998 goto fail; 2999 3000 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3001 3002 fail: 3003 return (error); 3004 } 3005 3006 void 3007 urtw_stop(struct ifnet *ifp, int disable) 3008 { 3009 struct urtw_softc *sc = ifp->if_softc; 3010 struct ieee80211com *ic = &sc->sc_ic; 3011 uint8_t data; 3012 usbd_status error; 3013 3014 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3015 3016 sc->sc_txtimer = 0; 3017 ifp->if_timer = 0; 3018 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3019 3020 callout_stop(&sc->scan_to); 3021 callout_stop(&sc->sc_led_ch); 3022 3023 urtw_intr_disable(sc); 3024 urtw_read8_m(sc, URTW_CMD, &data); 3025 data &= ~URTW_CMD_TX_ENABLE; 3026 data &= ~URTW_CMD_RX_ENABLE; 3027 urtw_write8_m(sc, URTW_CMD, data); 3028 3029 if (sc->sc_rxpipe != NULL) 3030 usbd_abort_pipe(sc->sc_rxpipe); 3031 if (sc->sc_txpipe_low != NULL) 3032 usbd_abort_pipe(sc->sc_txpipe_low); 3033 if (sc->sc_txpipe_normal != NULL) 3034 usbd_abort_pipe(sc->sc_txpipe_normal); 3035 3036 fail: 3037 return; 3038 } 3039 3040 int 3041 urtw_isbmode(uint16_t rate) 3042 { 3043 rate = urtw_rtl2rate(rate); 3044 3045 return (((rate <= 22 && rate != 12 && rate != 18) || 3046 rate == 44) ? (1) : (0)); 3047 } 3048 3049 void 3050 urtw_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 3051 { 3052 struct urtw_rx_data *data = priv; 3053 struct urtw_softc *sc = data->sc; 3054 struct ieee80211com *ic = &sc->sc_ic; 3055 struct ifnet *ifp = ic->ic_ifp; 3056 struct ieee80211_frame *wh; 3057 struct ieee80211_node *ni; 3058 struct mbuf *m, *mnew; 3059 uint8_t *desc, quality, rate; 3060 int actlen, flen, len, rssi, s; 3061 3062 if (status != USBD_NORMAL_COMPLETION) { 3063 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3064 return; 3065 3066 if (status == USBD_STALLED) 3067 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3068 ifp->if_ierrors++; 3069 goto skip; 3070 } 3071 3072 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3073 if (actlen < URTW_MIN_RXBUFSZ) { 3074 ifp->if_ierrors++; 3075 goto skip; 3076 } 3077 3078 if (sc->sc_hwrev & URTW_HWREV_8187) 3079 /* 4 dword and 4 byte CRC */ 3080 len = actlen - (4 * 4); 3081 else 3082 /* 5 dword and 4 byte CRC */ 3083 len = actlen - (4 * 5); 3084 3085 desc = data->buf + len; 3086 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3087 if (flen > actlen) { 3088 ifp->if_ierrors++; 3089 goto skip; 3090 } 3091 3092 rate = (desc[2] & 0xf0) >> 4; 3093 if (sc->sc_hwrev & URTW_HWREV_8187) { 3094 quality = desc[4] & 0xff; 3095 rssi = (desc[6] & 0xfe) >> 1; 3096 3097 /* XXX correct? */ 3098 if (!urtw_isbmode(rate)) { 3099 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3100 rssi = ((90 - rssi) * 100) / 65; 3101 } else { 3102 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3103 rssi = ((95 - rssi) * 100) / 65; 3104 } 3105 } else { 3106 quality = desc[12]; 3107 rssi = 14 - desc[14] / 2; 3108 } 3109 3110 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3111 if (mnew == NULL) { 3112 printf("%s: could not allocate rx mbuf\n", 3113 device_xname(sc->sc_dev)); 3114 ifp->if_ierrors++; 3115 goto skip; 3116 } 3117 MCLGET(mnew, M_DONTWAIT); 3118 if (!(mnew->m_flags & M_EXT)) { 3119 printf("%s: could not allocate rx mbuf cluster\n", 3120 device_xname(sc->sc_dev)); 3121 m_freem(mnew); 3122 ifp->if_ierrors++; 3123 goto skip; 3124 } 3125 3126 m = data->m; 3127 data->m = mnew; 3128 data->buf = mtod(mnew, uint8_t *); 3129 3130 /* finalize mbuf */ 3131 m->m_pkthdr.rcvif = ifp; 3132 m->m_pkthdr.len = m->m_len = flen - 4; 3133 3134 s = splnet(); 3135 3136 if (sc->sc_drvbpf != NULL) { 3137 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3138 3139 /* XXX Are variables correct? */ 3140 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3141 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3142 tap->wr_dbm_antsignal = (int8_t)rssi; 3143 3144 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 3145 } 3146 wh = mtod(m, struct ieee80211_frame *); 3147 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3148 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3149 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3150 3151 /* XXX correct? */ 3152 if (!urtw_isbmode(rate)) { 3153 if (quality > 127) 3154 quality = 0; 3155 else if (quality < 27) 3156 quality = 100; 3157 else 3158 quality = 127 - quality; 3159 } else 3160 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3161 3162 /* send the frame to the 802.11 layer */ 3163 ieee80211_input(ic, m, ni, rssi, 0); 3164 3165 /* node is no longer needed */ 3166 ieee80211_free_node(ni); 3167 3168 splx(s); 3169 3170 skip: /* setup a new transfer */ 3171 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3172 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3173 (void)usbd_transfer(xfer); 3174 } 3175 3176 usbd_status 3177 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3178 { 3179 uint8_t *gainp; 3180 usbd_status error; 3181 3182 /* XXX for A? */ 3183 gainp = urtw_8225v2_gain_bg; 3184 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3185 usbd_delay_ms(sc->sc_udev, 1); 3186 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3187 usbd_delay_ms(sc->sc_udev, 1); 3188 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3189 usbd_delay_ms(sc->sc_udev, 1); 3190 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3191 usbd_delay_ms(sc->sc_udev, 1); 3192 fail: 3193 return (error); 3194 } 3195 3196 usbd_status 3197 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3198 { 3199 int i; 3200 uint8_t *cck_pwrtable; 3201 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3202 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3203 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3204 usbd_status error; 3205 3206 /* CCK power setting */ 3207 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3208 cck_pwrlvl += sc->sc_txpwr_cck_base; 3209 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3210 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3211 urtw_8225v2_txpwr_cck; 3212 3213 for (i = 0; i < 8; i++) { 3214 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3215 } 3216 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3217 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3218 usbd_delay_ms(sc->sc_udev, 1); 3219 3220 /* OFDM power setting */ 3221 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3222 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3223 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3224 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3225 3226 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3227 if (error) 3228 goto fail; 3229 3230 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3231 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3232 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3233 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3234 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3235 3236 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3237 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3238 usbd_delay_ms(sc->sc_udev, 1); 3239 fail: 3240 return (error); 3241 } 3242 3243 usbd_status 3244 urtw_8225v2_rf_init(struct urtw_rf *rf) 3245 { 3246 struct urtw_softc *sc = rf->rf_sc; 3247 int i; 3248 uint16_t data; 3249 uint32_t data32; 3250 usbd_status error; 3251 3252 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3253 if (error) 3254 goto fail; 3255 3256 error = urtw_8225_usb_init(sc); 3257 if (error) 3258 goto fail; 3259 3260 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3261 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3262 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3263 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3264 3265 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3266 if (error) 3267 goto fail; 3268 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3269 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3270 if (error) 3271 goto fail; 3272 3273 error = urtw_8185_rf_pins_enable(sc); 3274 if (error) 3275 goto fail; 3276 3277 usbd_delay_ms(sc->sc_udev, 1000); 3278 3279 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3280 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3281 urtw_8225v2_rf_part1[i].val); 3282 usbd_delay_ms(sc->sc_udev, 1); 3283 } 3284 usbd_delay_ms(sc->sc_udev, 50); 3285 3286 urtw_8225_write(sc, 0x0, 0x1b7); 3287 3288 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3289 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3290 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3291 } 3292 3293 urtw_8225_write(sc, 0x3, 0x2); 3294 urtw_8225_write(sc, 0x5, 0x4); 3295 urtw_8225_write(sc, 0x0, 0xb7); 3296 urtw_8225_write(sc, 0x2, 0xc4d); 3297 usbd_delay_ms(sc->sc_udev, 100); 3298 urtw_8225_write(sc, 0x2, 0x44d); 3299 usbd_delay_ms(sc->sc_udev, 100); 3300 3301 error = urtw_8225_read(sc, 0x6, &data32); 3302 if (error != 0) 3303 goto fail; 3304 if (data32 != 0xe6) 3305 printf("%s: expect 0xe6!! (0x%x)\n", device_xname(sc->sc_dev), 3306 data32); 3307 if (!(data32 & 0x80)) { 3308 urtw_8225_write(sc, 0x02, 0x0c4d); 3309 usbd_delay_ms(sc->sc_udev, 200); 3310 urtw_8225_write(sc, 0x02, 0x044d); 3311 usbd_delay_ms(sc->sc_udev, 100); 3312 error = urtw_8225_read(sc, 0x6, &data32); 3313 if (error != 0) 3314 goto fail; 3315 if (!(data32 & 0x80)) 3316 printf("%s: RF calibration failed\n", 3317 device_xname(sc->sc_dev)); 3318 } 3319 usbd_delay_ms(sc->sc_udev, 100); 3320 3321 urtw_8225_write(sc, 0x0, 0x2bf); 3322 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3323 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3324 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3325 } 3326 3327 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3328 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3329 urtw_8225v2_rf_part2[i].val); 3330 } 3331 3332 error = urtw_8225v2_setgain(sc, 4); 3333 if (error) 3334 goto fail; 3335 3336 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3337 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3338 urtw_8225v2_rf_part3[i].val); 3339 } 3340 3341 urtw_write8_m(sc, 0x5b, 0x0d); 3342 3343 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3344 if (error) 3345 goto fail; 3346 3347 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3348 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3349 3350 /* TX ant A, 0x0 for B */ 3351 error = urtw_8185_tx_antenna(sc, 0x3); 3352 if (error) 3353 goto fail; 3354 urtw_write32_m(sc, 0x94, 0x3dc00002); 3355 3356 error = urtw_8225_rf_set_chan(rf, 1); 3357 fail: 3358 return (error); 3359 } 3360 3361 usbd_status 3362 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3363 { 3364 struct urtw_softc *sc = rf->rf_sc; 3365 struct ieee80211com *ic = &sc->sc_ic; 3366 struct ieee80211_channel *c = ic->ic_ibss_chan; 3367 usbd_status error; 3368 3369 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3370 if (error) 3371 goto fail; 3372 3373 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3374 usbd_delay_ms(sc->sc_udev, 10); 3375 3376 urtw_write8_m(sc, URTW_SIFS, 0x22); 3377 3378 if(sc->sc_state == IEEE80211_S_ASSOC && 3379 ic->ic_flags & IEEE80211_F_SHSLOT) 3380 urtw_write8_m(sc, URTW_SLOT, 0x9); 3381 else 3382 urtw_write8_m(sc, URTW_SLOT, 0x14); 3383 3384 if (IEEE80211_IS_CHAN_G(c)) { 3385 urtw_write8_m(sc, URTW_DIFS, 0x14); 3386 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3387 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3388 } else { 3389 urtw_write8_m(sc, URTW_DIFS, 0x24); 3390 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3391 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3392 } 3393 3394 fail: 3395 return (error); 3396 } 3397 3398 void 3399 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3400 { 3401 struct urtw_rf *rf = &sc->sc_rf; 3402 struct ieee80211com *ic = &sc->sc_ic; 3403 usbd_status error = 0; 3404 uint32_t data; 3405 u_int chan; 3406 3407 chan = ieee80211_chan2ieee(ic, c); 3408 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3409 return; 3410 /* 3411 * During changing the channel we need to temporary disable 3412 * TX. 3413 */ 3414 urtw_read32_m(sc, URTW_TX_CONF, &data); 3415 data &= ~URTW_TX_LOOPBACK_MASK; 3416 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3417 error = rf->set_chan(rf, chan); 3418 if (error != 0) { 3419 printf("%s could not change the channel\n", 3420 device_xname(sc->sc_dev)); 3421 return; 3422 } 3423 usbd_delay_ms(sc->sc_udev, 10); 3424 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3425 3426 fail: return; 3427 3428 } 3429 3430 void 3431 urtw_next_scan(void *arg) 3432 { 3433 struct urtw_softc *sc = arg; 3434 struct ieee80211com *ic = &sc->sc_ic; 3435 int s; 3436 3437 if (sc->sc_dying) 3438 return; 3439 3440 s = splnet(); 3441 if (ic->ic_state == IEEE80211_S_SCAN) 3442 ieee80211_next_scan(ic); 3443 splx(s); 3444 } 3445 3446 void 3447 urtw_task(void *arg) 3448 { 3449 struct urtw_softc *sc = arg; 3450 struct ieee80211com *ic = &sc->sc_ic; 3451 struct ieee80211_node *ni; 3452 enum ieee80211_state ostate; 3453 usbd_status error = 0; 3454 3455 if (sc->sc_dying) 3456 return; 3457 3458 ostate = ic->ic_state; 3459 3460 switch (sc->sc_state) { 3461 case IEEE80211_S_INIT: 3462 if (ostate == IEEE80211_S_RUN) { 3463 /* turn link LED off */ 3464 (void)urtw_led_off(sc, URTW_LED_GPIO); 3465 } 3466 break; 3467 3468 case IEEE80211_S_SCAN: 3469 urtw_set_chan(sc, ic->ic_curchan); 3470 if (!sc->sc_dying) 3471 callout_schedule(&sc->scan_to, mstohz(200)); 3472 break; 3473 3474 case IEEE80211_S_AUTH: 3475 case IEEE80211_S_ASSOC: 3476 urtw_set_chan(sc, ic->ic_curchan); 3477 break; 3478 3479 case IEEE80211_S_RUN: 3480 ni = ic->ic_bss; 3481 3482 urtw_set_chan(sc, ic->ic_curchan); 3483 3484 /* setting bssid. */ 3485 error = urtw_set_bssid(sc, ni->ni_bssid); 3486 if (error != 0) 3487 goto fail; 3488 urtw_update_msr(sc); 3489 /* XXX maybe the below would be incorrect. */ 3490 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3491 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3492 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3493 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3494 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3495 if (error != 0) 3496 printf("%s: could not control LED (%d)\n", 3497 device_xname(sc->sc_dev), error); 3498 break; 3499 } 3500 3501 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3502 3503 fail: 3504 if (error != 0) { 3505 DPRINTF(("%s: error duing processing RUN state.", 3506 device_xname(sc->sc_dev))); 3507 } 3508 } 3509 3510 usbd_status 3511 urtw_8187b_update_wmm(struct urtw_softc *sc) 3512 { 3513 struct ieee80211com *ic = &sc->sc_ic; 3514 struct ieee80211_channel *c = ic->ic_ibss_chan; 3515 uint32_t data; 3516 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3517 usbd_status error; 3518 3519 sifs = 0xa; 3520 if (IEEE80211_IS_CHAN_G(c)) 3521 slot = 0x9; 3522 else 3523 slot = 0x14; 3524 3525 aifs = (2 * slot) + sifs; 3526 ecwmin = 3; 3527 ecwmax = 7; 3528 3529 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3530 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3531 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3532 3533 urtw_write32_m(sc, URTW_AC_VO, data); 3534 urtw_write32_m(sc, URTW_AC_VI, data); 3535 urtw_write32_m(sc, URTW_AC_BE, data); 3536 urtw_write32_m(sc, URTW_AC_BK, data); 3537 3538 fail: 3539 return (error); 3540 } 3541 3542 usbd_status 3543 urtw_8187b_reset(struct urtw_softc *sc) 3544 { 3545 uint8_t data; 3546 usbd_status error; 3547 3548 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3549 if (error) 3550 goto fail; 3551 3552 urtw_read8_m(sc, URTW_CONFIG3, &data); 3553 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3554 URTW_CONFIG3_GNT_SELECT); 3555 3556 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3557 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3558 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3559 3560 urtw_write8_m(sc, 0x61, 0x10); 3561 urtw_read8_m(sc, 0x62, &data); 3562 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3563 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3564 3565 urtw_read8_m(sc, URTW_CONFIG3, &data); 3566 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3567 3568 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3569 if (error) 3570 goto fail; 3571 3572 urtw_read8_m(sc, URTW_CMD, &data); 3573 data = (data & 2) | URTW_CMD_RST; 3574 urtw_write8_m(sc, URTW_CMD, data); 3575 usbd_delay_ms(sc->sc_udev, 100); 3576 3577 urtw_read8_m(sc, URTW_CMD, &data); 3578 if (data & URTW_CMD_RST) { 3579 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3580 goto fail; 3581 } 3582 3583 fail: 3584 return (error); 3585 } 3586 3587 int 3588 urtw_8187b_init(struct ifnet *ifp) 3589 { 3590 struct urtw_softc *sc = ifp->if_softc; 3591 struct urtw_rf *rf = &sc->sc_rf; 3592 struct ieee80211com *ic = &sc->sc_ic; 3593 uint8_t data; 3594 usbd_status error; 3595 3596 urtw_stop(ifp, 0); 3597 3598 error = urtw_8187b_update_wmm(sc); 3599 if (error != 0) 3600 goto fail; 3601 error = urtw_8187b_reset(sc); 3602 if (error) 3603 goto fail; 3604 3605 /* Applying MAC address again. */ 3606 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3607 if (error) 3608 goto fail; 3609 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3610 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3611 if (error) 3612 goto fail; 3613 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3614 if (error) 3615 goto fail; 3616 3617 error = urtw_update_msr(sc); 3618 if (error) 3619 goto fail; 3620 3621 error = rf->init(rf); 3622 if (error != 0) 3623 goto fail; 3624 3625 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3626 URTW_CMD_RX_ENABLE); 3627 error = urtw_intr_enable(sc); 3628 if (error != 0) 3629 goto fail; 3630 3631 error = urtw_write8e(sc, 0x41, 0xf4); 3632 if (error != 0) 3633 goto fail; 3634 error = urtw_write8e(sc, 0x40, 0x00); 3635 if (error != 0) 3636 goto fail; 3637 error = urtw_write8e(sc, 0x42, 0x00); 3638 if (error != 0) 3639 goto fail; 3640 error = urtw_write8e(sc, 0x42, 0x01); 3641 if (error != 0) 3642 goto fail; 3643 error = urtw_write8e(sc, 0x40, 0x0f); 3644 if (error != 0) 3645 goto fail; 3646 error = urtw_write8e(sc, 0x42, 0x00); 3647 if (error != 0) 3648 goto fail; 3649 error = urtw_write8e(sc, 0x42, 0x01); 3650 if (error != 0) 3651 goto fail; 3652 3653 urtw_read8_m(sc, 0xdb, &data); 3654 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3655 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3656 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3657 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3658 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3659 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3660 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3661 urtw_write8_m(sc, 0x61, 0); 3662 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3663 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3664 urtw_write8_m(sc, 0xda, 0x10); 3665 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3666 3667 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3668 3669 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3670 3671 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3672 3673 /* Reset softc variables. */ 3674 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3675 sc->sc_txtimer = 0; 3676 3677 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3678 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3679 if (error != 0) { 3680 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3681 ", err=%s\n", usbd_errstr(error)); 3682 3683 goto fail; 3684 } 3685 /* Get the first interface handle. */ 3686 error = usbd_device2interface_handle(sc->sc_udev, 3687 URTW_IFACE_INDEX, &sc->sc_iface); 3688 if (error != 0) { 3689 printf("%s: could not get interface handle\n", 3690 device_xname(sc->sc_dev)); 3691 goto fail; 3692 } 3693 error = urtw_open_pipes(sc); 3694 if (error != 0) 3695 goto fail; 3696 error = urtw_alloc_rx_data_list(sc); 3697 if (error != 0) 3698 goto fail; 3699 error = urtw_alloc_tx_data_list(sc); 3700 if (error != 0) 3701 goto fail; 3702 sc->sc_flags |= URTW_INIT_ONCE; 3703 } 3704 3705 error = urtw_rx_enable(sc); 3706 if (error != 0) 3707 goto fail; 3708 error = urtw_tx_enable(sc); 3709 if (error != 0) 3710 goto fail; 3711 3712 ifp->if_flags &= ~IFF_OACTIVE; 3713 ifp->if_flags |= IFF_RUNNING; 3714 3715 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3716 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3717 else 3718 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3719 3720 fail: 3721 return (error); 3722 } 3723 3724 usbd_status 3725 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3726 { 3727 int i; 3728 usbd_status error; 3729 3730 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3731 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3732 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3733 } 3734 3735 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3736 urtw_write16_m(sc, URTW_INT_MIG, 0); 3737 3738 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3739 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3740 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3741 3742 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3743 3744 fail: 3745 return (error); 3746 } 3747 3748 usbd_status 3749 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3750 { 3751 usbd_status error; 3752 3753 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3754 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3755 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3756 usbd_delay_ms(sc->sc_udev, 100); 3757 3758 fail: 3759 return (error); 3760 } 3761 3762 usbd_status 3763 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3764 { 3765 struct ieee80211com *ic = &sc->sc_ic; 3766 struct ieee80211_channel *c = ic->ic_ibss_chan; 3767 uint8_t aifs, difs, eifs, sifs, slot; 3768 usbd_status error; 3769 3770 urtw_write8_m(sc, URTW_SIFS, 0x22); 3771 3772 sifs = 0xa; 3773 if (IEEE80211_IS_CHAN_G(c)) { 3774 slot = 0x9; 3775 difs = 0x1c; 3776 eifs = 0x5b; 3777 } else { 3778 slot = 0x14; 3779 difs = 0x32; 3780 eifs = 0x5b; 3781 } 3782 aifs = (2 * slot) + sifs; 3783 3784 urtw_write8_m(sc, URTW_SLOT, slot); 3785 3786 urtw_write8_m(sc, URTW_AC_VO, aifs); 3787 urtw_write8_m(sc, URTW_AC_VI, aifs); 3788 urtw_write8_m(sc, URTW_AC_BE, aifs); 3789 urtw_write8_m(sc, URTW_AC_BK, aifs); 3790 3791 urtw_write8_m(sc, URTW_DIFS, difs); 3792 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3793 3794 fail: 3795 return (error); 3796 } 3797 3798 usbd_status 3799 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3800 { 3801 struct urtw_softc *sc = rf->rf_sc; 3802 unsigned int i; 3803 uint8_t data; 3804 usbd_status error; 3805 3806 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3807 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3808 urtw_read8_m(sc, URTW_CW_CONF, &data); 3809 urtw_write8_m(sc, URTW_CW_CONF, data | 3810 URTW_CW_CONF_PERPACKET_RETRY); 3811 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3812 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3813 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3814 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3815 3816 /* Auto rate fallback control. */ 3817 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3818 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3819 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3820 URTW_RATE_FALLBACK_ENABLE); 3821 3822 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3823 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3824 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3825 3826 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3827 if (error) 3828 goto fail; 3829 urtw_read8_m(sc, URTW_CONFIG1, &data); 3830 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3831 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3832 if (error) 3833 goto fail; 3834 3835 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3836 urtw_8225v2_b_config_mac(sc); 3837 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3838 3839 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3840 if (error) 3841 goto fail; 3842 urtw_read8_m(sc, URTW_CONFIG3, &data); 3843 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3844 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3845 if (error) 3846 goto fail; 3847 3848 urtw_8225v2_b_init_rfe(sc); 3849 3850 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3851 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3852 urtw_8225v2_b_rf[i].val); 3853 } 3854 3855 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3856 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3857 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3858 } 3859 3860 urtw_8225_write(sc, 0x03, 0x080); 3861 urtw_8225_write(sc, 0x05, 0x004); 3862 urtw_8225_write(sc, 0x00, 0x0b7); 3863 urtw_8225_write(sc, 0x02, 0xc4d); 3864 urtw_8225_write(sc, 0x02, 0x44d); 3865 urtw_8225_write(sc, 0x00, 0x2bf); 3866 3867 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3868 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3869 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3870 3871 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3872 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3873 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3874 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3875 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3876 } 3877 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3878 3879 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3880 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3881 3882 urtw_8225v2_b_update_chan(sc); 3883 3884 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3885 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3886 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3887 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3888 3889 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3890 fail: 3891 return (error); 3892 } 3893 3894 usbd_status 3895 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3896 { 3897 struct urtw_softc *sc = rf->rf_sc; 3898 usbd_status error; 3899 3900 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3901 if (error) 3902 goto fail; 3903 3904 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3905 /* 3906 * Delay removed from 8185 to 8187. 3907 * usbd_delay_ms(sc->sc_udev, 10); 3908 */ 3909 3910 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3911 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3912 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3913 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3914 3915 fail: 3916 return (error); 3917 } 3918 3919 usbd_status 3920 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3921 { 3922 int i; 3923 uint8_t *cck_pwrtable; 3924 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3925 ofdm_pwrlvl_max; 3926 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3927 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3928 usbd_status error; 3929 3930 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3931 cck_pwrlvl_min = 0; 3932 cck_pwrlvl_max = 15; 3933 ofdm_pwrlvl_min = 2; 3934 ofdm_pwrlvl_max = 17; 3935 } else { 3936 cck_pwrlvl_min = 7; 3937 cck_pwrlvl_max = 22; 3938 ofdm_pwrlvl_min = 10; 3939 ofdm_pwrlvl_max = 25; 3940 } 3941 3942 /* CCK power setting */ 3943 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3944 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3945 3946 cck_pwrlvl += sc->sc_txpwr_cck_base; 3947 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3948 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3949 3950 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3951 urtw_8225v2_txpwr_cck; 3952 3953 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3954 if (cck_pwrlvl <= 6) 3955 ; /* do nothing */ 3956 else if (cck_pwrlvl <= 11) 3957 cck_pwrtable += 8; 3958 else 3959 cck_pwrtable += 16; 3960 } else { 3961 if (cck_pwrlvl <= 5) 3962 ; /* do nothing */ 3963 else if (cck_pwrlvl <= 11) 3964 cck_pwrtable += 8; 3965 else if (cck_pwrlvl <= 17) 3966 cck_pwrtable += 16; 3967 else 3968 cck_pwrtable += 24; 3969 } 3970 3971 for (i = 0; i < 8; i++) { 3972 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3973 } 3974 3975 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3976 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3977 /* 3978 * Delay removed from 8185 to 8187. 3979 * usbd_delay_ms(sc->sc_udev, 1); 3980 */ 3981 3982 /* OFDM power setting */ 3983 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3984 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3985 3986 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3987 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3988 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3989 3990 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3991 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3992 3993 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3994 if (ofdm_pwrlvl <= 11) { 3995 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3996 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3997 } else { 3998 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3999 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4000 } 4001 } else { 4002 if (ofdm_pwrlvl <= 11) { 4003 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4004 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4005 } else if (ofdm_pwrlvl <= 17) { 4006 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4007 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4008 } else { 4009 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4010 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4011 } 4012 } 4013 4014 /* 4015 * Delay removed from 8185 to 8187. 4016 * usbd_delay_ms(sc->sc_udev, 1); 4017 */ 4018 fail: 4019 return (error); 4020 } 4021 4022 int 4023 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4024 { 4025 int error; 4026 4027 urtw_write32_m(sc, URTW_BSSID, 4028 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4029 urtw_write16_m(sc, URTW_BSSID + 4, 4030 bssid[4] | bssid[5] << 8); 4031 4032 return 0; 4033 4034 fail: 4035 return error; 4036 } 4037 4038 int 4039 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4040 { 4041 int error; 4042 4043 urtw_write32_m(sc, URTW_MAC0, 4044 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4045 urtw_write16_m(sc, URTW_MAC4, 4046 addr[4] | addr[5] << 8); 4047 4048 return 0; 4049 4050 fail: 4051 return error; 4052 } 4053 4054 MODULE(MODULE_CLASS_DRIVER, if_urtw, "bpf"); 4055 4056 #ifdef _MODULE 4057 #include "ioconf.c" 4058 #endif 4059 4060 static int 4061 if_urtw_modcmd(modcmd_t cmd, void *aux) 4062 { 4063 int error = 0; 4064 4065 switch (cmd) { 4066 case MODULE_CMD_INIT: 4067 #ifdef _MODULE 4068 error = config_init_component(cfdriver_ioconf_urtw, 4069 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4070 #endif 4071 return error; 4072 case MODULE_CMD_FINI: 4073 #ifdef _MODULE 4074 error = config_fini_component(cfdriver_ioconf_urtw, 4075 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4076 #endif 4077 return error; 4078 default: 4079 return ENOTTY; 4080 } 4081 } 4082
Indexes created Fri Oct 03 02:09:57 GMT 2025