if_urtw.c revision 1.15.2.2
1 /* $NetBSD: if_urtw.c,v 1.15.2.2 2020/04/08 14:08:13 martin Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.15.2.2 2020/04/08 14:08:13 martin Exp $"); 23 24 #ifdef _KERNEL_OPT 25 #include "opt_usb.h" 26 #endif 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/proc.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <machine/endian.h> 42 #include <net/bpf.h> 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/if_dl.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 50 #include <netinet/in.h> 51 #include <netinet/in_systm.h> 52 #include <netinet/in_var.h> 53 #include <netinet/if_inarp.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdi_util.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usbdevs.h> 64 65 #include "if_urtwreg.h" 66 67 #ifdef URTW_DEBUG 68 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 69 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 70 int urtw_debug = 0; 71 #else 72 #define DPRINTF(x) 73 #define DPRINTFN(n, x) 74 #endif 75 76 /* 77 * Recognized device vendors/products. 78 */ 79 static const struct urtw_type { 80 struct usb_devno dev; 81 uint8_t rev; 82 } urtw_devs[] = { 83 #define URTW_DEV_RTL8187(v, p) \ 84 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 85 #define URTW_DEV_RTL8187B(v, p) \ 86 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 87 /* Realtek RTL8187 devices. */ 88 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 89 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 90 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 91 URTW_DEV_RTL8187(LOGITEC, RTL8187), 92 URTW_DEV_RTL8187(NETGEAR, WG111V2), 93 URTW_DEV_RTL8187(REALTEK, RTL8187), 94 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 95 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 96 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 97 /* Realtek RTL8187B devices. */ 98 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 99 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 100 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 101 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 102 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 103 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 104 #undef URTW_DEV_RTL8187 105 #undef URTW_DEV_RTL8187B 106 }; 107 #define urtw_lookup(v, p) \ 108 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 109 110 /* 111 * Helper read/write macros. 112 */ 113 #define urtw_read8_m(sc, val, data) do { \ 114 error = urtw_read8_c(sc, val, data, 0); \ 115 if (error != 0) \ 116 goto fail; \ 117 } while (0) 118 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 119 error = urtw_read8_c(sc, val, data, idx); \ 120 if (error != 0) \ 121 goto fail; \ 122 } while (0) 123 #define urtw_write8_m(sc, val, data) do { \ 124 error = urtw_write8_c(sc, val, data, 0); \ 125 if (error != 0) \ 126 goto fail; \ 127 } while (0) 128 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 129 error = urtw_write8_c(sc, val, data, idx); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_read16_m(sc, val, data) do { \ 134 error = urtw_read16_c(sc, val, data, 0); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 139 error = urtw_read16_c(sc, val, data, idx); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data, 0); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 149 error = urtw_write16_c(sc, val, data, idx); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_read32_m(sc, val, data) do { \ 154 error = urtw_read32_c(sc, val, data, 0); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 159 error = urtw_read32_c(sc, val, data, idx); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_write32_m(sc, val, data) do { \ 164 error = urtw_write32_c(sc, val, data, 0); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 169 error = urtw_write32_c(sc, val, data, idx); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 174 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 175 if (error != 0) \ 176 goto fail; \ 177 } while (0) 178 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 179 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 180 if (error != 0) \ 181 goto fail; \ 182 } while (0) 183 #define urtw_8225_write(sc, val, data) do { \ 184 error = urtw_8225_write_c(sc, val, data); \ 185 if (error != 0) \ 186 goto fail; \ 187 } while (0) 188 189 struct urtw_pair { 190 uint32_t reg; 191 uint32_t val; 192 }; 193 194 struct urtw_pair_idx { 195 uint8_t reg; 196 uint8_t val; 197 uint8_t idx; 198 }; 199 200 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 201 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 202 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 203 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 204 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 205 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 206 { 0xff, 0x00, 0 }, 207 208 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 209 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 210 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 211 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 212 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 213 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 214 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 215 { 0xf8, 0x08, 1 }, 216 217 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 218 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 219 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 220 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 221 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 222 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 223 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 224 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 225 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 226 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 227 228 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 229 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 230 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 231 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 232 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 233 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 234 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 235 236 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 237 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 238 }; 239 240 static uint8_t urtw_8225_agc[] = { 241 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 242 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 243 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 244 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 245 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 246 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 247 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 248 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 249 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 250 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 251 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 252 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 253 }; 254 255 static uint32_t urtw_8225_channel[] = { 256 0x0000, /* dummy channel 0 */ 257 0x085c, /* 1 */ 258 0x08dc, /* 2 */ 259 0x095c, /* 3 */ 260 0x09dc, /* 4 */ 261 0x0a5c, /* 5 */ 262 0x0adc, /* 6 */ 263 0x0b5c, /* 7 */ 264 0x0bdc, /* 8 */ 265 0x0c5c, /* 9 */ 266 0x0cdc, /* 10 */ 267 0x0d5c, /* 11 */ 268 0x0ddc, /* 12 */ 269 0x0e5c, /* 13 */ 270 0x0f72, /* 14 */ 271 }; 272 273 static uint8_t urtw_8225_gain[] = { 274 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 275 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 276 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 277 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 278 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 279 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 280 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 281 }; 282 283 static struct urtw_pair urtw_8225_rf_part1[] = { 284 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 285 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 286 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 287 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 288 }; 289 290 static struct urtw_pair urtw_8225_rf_part2[] = { 291 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 292 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 293 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 294 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 295 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 296 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 297 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 298 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 299 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 300 { 0x27, 0x88 } 301 }; 302 303 static struct urtw_pair urtw_8225_rf_part3[] = { 304 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 305 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 306 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 307 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 308 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 309 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 310 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 311 }; 312 313 static uint16_t urtw_8225_rxgain[] = { 314 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 315 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 316 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 317 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 318 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 319 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 320 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 321 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 322 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 323 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 324 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 325 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 326 }; 327 328 static uint8_t urtw_8225_threshold[] = { 329 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 330 }; 331 332 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 333 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 334 }; 335 336 static uint8_t urtw_8225_txpwr_cck[] = { 337 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 338 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 339 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 340 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 341 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 342 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 343 }; 344 345 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 346 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 347 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 348 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 349 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 350 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 351 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 352 }; 353 354 static uint8_t urtw_8225_txpwr_ofdm[] = { 355 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 356 }; 357 358 static uint8_t urtw_8225v2_agc[] = { 359 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 360 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 361 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 362 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 363 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 364 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 365 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 366 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 367 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 368 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 369 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 370 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 371 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 372 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 373 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 374 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 375 }; 376 377 static uint8_t urtw_8225v2_ofdm[] = { 378 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 379 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 380 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 381 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 382 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 383 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 384 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 385 0x6d, 0x3c, 0xfb, 0x07 386 }; 387 388 static uint8_t urtw_8225v2_gain_bg[] = { 389 0x23, 0x15, 0xa5, /* -82-1dbm */ 390 0x23, 0x15, 0xb5, /* -82-2dbm */ 391 0x23, 0x15, 0xc5, /* -82-3dbm */ 392 0x33, 0x15, 0xc5, /* -78dbm */ 393 0x43, 0x15, 0xc5, /* -74dbm */ 394 0x53, 0x15, 0xc5, /* -70dbm */ 395 0x63, 0x15, 0xc5, /* -66dbm */ 396 }; 397 398 static struct urtw_pair urtw_8225v2_rf_part1[] = { 399 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 400 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 401 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 402 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 403 }; 404 405 static struct urtw_pair urtw_8225v2_rf_part2[] = { 406 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 407 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 408 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 409 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 410 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 411 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 412 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 413 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 414 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 415 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 416 }; 417 418 static struct urtw_pair urtw_8225v2_rf_part3[] = { 419 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 420 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 421 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 422 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 423 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 424 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 425 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 426 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 427 }; 428 429 static uint16_t urtw_8225v2_rxgain[] = { 430 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 431 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 432 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 433 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 434 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 435 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 436 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 437 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 438 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 439 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 440 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 441 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 442 }; 443 444 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 445 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 446 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 447 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 448 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 449 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 450 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 451 }; 452 453 static uint8_t urtw_8225v2_txpwr_cck[] = { 454 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 455 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 456 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 457 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 458 }; 459 460 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 461 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 462 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 463 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 464 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 465 }; 466 467 static struct urtw_pair urtw_8225v2_b_rf[] = { 468 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 469 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 470 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 471 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 472 { 0x00, 0x01b7 } 473 }; 474 475 static struct urtw_pair urtw_ratetable[] = { 476 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 477 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 478 { 96, 10 }, { 108, 11 } 479 }; 480 481 static int urtw_init(struct ifnet *); 482 static void urtw_stop(struct ifnet *, int); 483 static int urtw_ioctl(struct ifnet *, u_long, void *); 484 static void urtw_start(struct ifnet *); 485 static int urtw_alloc_rx_data_list(struct urtw_softc *); 486 static void urtw_free_rx_data_list(struct urtw_softc *); 487 static int urtw_alloc_tx_data_list(struct urtw_softc *); 488 static void urtw_free_tx_data_list(struct urtw_softc *); 489 static void urtw_rxeof(struct usbd_xfer *, void *, 490 usbd_status); 491 static int urtw_tx_start(struct urtw_softc *, 492 struct ieee80211_node *, struct mbuf *, int); 493 static void urtw_txeof_low(struct usbd_xfer *, void *, 494 usbd_status); 495 static void urtw_txeof_normal(struct usbd_xfer *, void *, 496 usbd_status); 497 static void urtw_next_scan(void *); 498 static void urtw_task(void *); 499 static void urtw_ledusbtask(void *); 500 static void urtw_ledtask(void *); 501 static int urtw_media_change(struct ifnet *); 502 static int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 503 static void urtw_watchdog(struct ifnet *); 504 static void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 505 static int urtw_isbmode(uint16_t); 506 static uint16_t urtw_rate2rtl(int); 507 static uint16_t urtw_rtl2rate(int); 508 static usbd_status urtw_set_rate(struct urtw_softc *); 509 static usbd_status urtw_update_msr(struct urtw_softc *); 510 static usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 511 static usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 512 static usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 513 static usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 514 static usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 515 static usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 516 static usbd_status urtw_eprom_cs(struct urtw_softc *, int); 517 static usbd_status urtw_eprom_ck(struct urtw_softc *); 518 static usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 519 int); 520 static usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 521 uint32_t *); 522 static usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 523 static usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 524 static usbd_status urtw_get_macaddr(struct urtw_softc *); 525 static usbd_status urtw_get_txpwr(struct urtw_softc *); 526 static usbd_status urtw_get_rfchip(struct urtw_softc *); 527 static usbd_status urtw_led_init(struct urtw_softc *); 528 static usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 529 static usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 530 static usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 531 static usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 532 uint32_t); 533 static usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 534 uint32_t); 535 static usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 536 static usbd_status urtw_8225_usb_init(struct urtw_softc *); 537 static usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 538 static usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 539 uint16_t); 540 static usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 541 static usbd_status urtw_8225_rf_init(struct urtw_rf *); 542 static usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 543 static usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 544 static usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 545 static usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 546 static usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 547 static usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 548 static usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 549 static usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 550 static usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 551 static usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 552 static usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 553 static usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 554 static usbd_status urtw_open_pipes(struct urtw_softc *); 555 static usbd_status urtw_close_pipes(struct urtw_softc *); 556 static usbd_status urtw_intr_enable(struct urtw_softc *); 557 static usbd_status urtw_intr_disable(struct urtw_softc *); 558 static usbd_status urtw_reset(struct urtw_softc *); 559 static usbd_status urtw_led_on(struct urtw_softc *, int); 560 static usbd_status urtw_led_ctl(struct urtw_softc *, int); 561 static usbd_status urtw_led_blink(struct urtw_softc *); 562 static usbd_status urtw_led_mode0(struct urtw_softc *, int); 563 static usbd_status urtw_led_mode1(struct urtw_softc *, int); 564 static usbd_status urtw_led_mode2(struct urtw_softc *, int); 565 static usbd_status urtw_led_mode3(struct urtw_softc *, int); 566 static usbd_status urtw_rx_setconf(struct urtw_softc *); 567 static usbd_status urtw_rx_enable(struct urtw_softc *); 568 static usbd_status urtw_tx_enable(struct urtw_softc *); 569 static usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 570 static usbd_status urtw_8187b_reset(struct urtw_softc *); 571 static int urtw_8187b_init(struct ifnet *); 572 static usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 573 static usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 574 static usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 575 static usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 576 static usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 577 static usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 578 static int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 579 static int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 580 581 static int urtw_match(device_t, cfdata_t, void *); 582 static void urtw_attach(device_t, device_t, void *); 583 static int urtw_detach(device_t, int); 584 static int urtw_activate(device_t, enum devact); 585 586 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 587 urtw_match, 588 urtw_attach, 589 urtw_detach, 590 urtw_activate 591 ); 592 593 static int 594 urtw_match(device_t parent, cfdata_t match, void *aux) 595 { 596 struct usb_attach_arg *uaa = aux; 597 598 return urtw_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 599 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 600 } 601 602 static void 603 urtw_attach(device_t parent, device_t self, void *aux) 604 { 605 struct urtw_softc *sc = device_private(self); 606 struct usb_attach_arg *uaa = aux; 607 struct ieee80211com *ic = &sc->sc_ic; 608 struct ifnet *ifp = &sc->sc_if; 609 usbd_status error; 610 uint8_t data8; 611 uint32_t data; 612 int i; 613 614 sc->sc_dev = self; 615 sc->sc_udev = uaa->uaa_device; 616 sc->sc_hwrev = urtw_lookup(uaa->uaa_vendor, uaa->uaa_product)->rev; 617 618 aprint_naive("\n"); 619 aprint_normal(": "); 620 621 if (sc->sc_hwrev & URTW_HWREV_8187) { 622 urtw_read32_m(sc, URTW_TX_CONF, &data); 623 data &= URTW_TX_HWREV_MASK; 624 switch (data) { 625 case URTW_TX_HWREV_8187_D: 626 sc->sc_hwrev |= URTW_HWREV_8187_D; 627 aprint_normal("RTL8187 rev D"); 628 break; 629 case URTW_TX_HWREV_8187B_D: 630 /* 631 * Detect Realtek RTL8187B devices that use 632 * USB IDs of RTL8187. 633 */ 634 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 635 aprint_normal("RTL8187B rev B (early)"); 636 break; 637 default: 638 sc->sc_hwrev |= URTW_HWREV_8187_B; 639 aprint_normal("RTL8187 rev 0x%02x", data >> 25); 640 break; 641 } 642 } else { 643 /* RTL8187B hwrev register. */ 644 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 645 switch (data8) { 646 case URTW_8187B_HWREV_8187B_B: 647 sc->sc_hwrev |= URTW_HWREV_8187B_B; 648 aprint_normal("RTL8187B rev B"); 649 break; 650 case URTW_8187B_HWREV_8187B_D: 651 sc->sc_hwrev |= URTW_HWREV_8187B_D; 652 aprint_normal("RTL8187B rev D"); 653 break; 654 case URTW_8187B_HWREV_8187B_E: 655 sc->sc_hwrev |= URTW_HWREV_8187B_E; 656 aprint_normal("RTL8187B rev E"); 657 break; 658 default: 659 sc->sc_hwrev |= URTW_HWREV_8187B_B; 660 aprint_normal("RTL8187B rev 0x%02x", data8); 661 break; 662 } 663 } 664 665 urtw_read32_m(sc, URTW_RX, &data); 666 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 667 URTW_EEPROM_93C46; 668 669 error = urtw_get_rfchip(sc); 670 if (error != 0) 671 goto fail; 672 error = urtw_get_macaddr(sc); 673 if (error != 0) 674 goto fail; 675 error = urtw_get_txpwr(sc); 676 if (error != 0) 677 goto fail; 678 error = urtw_led_init(sc); /* XXX incompleted */ 679 if (error != 0) 680 goto fail; 681 682 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 683 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 684 sc->sc_currate = 3; 685 /* XXX for what? */ 686 sc->sc_preamble_mode = 2; 687 688 usb_init_task(&sc->sc_task, urtw_task, sc, 0); 689 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 0); 690 callout_init(&sc->scan_to, 0); 691 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 692 callout_init(&sc->sc_led_ch, 0); 693 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 694 695 ic->ic_ifp = ifp; 696 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 697 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 698 ic->ic_state = IEEE80211_S_INIT; 699 700 /* set device capabilities */ 701 ic->ic_caps = 702 IEEE80211_C_MONITOR | /* monitor mode supported */ 703 IEEE80211_C_TXPMGT | /* tx power management */ 704 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 705 IEEE80211_C_SHSLOT | /* short slot time supported */ 706 IEEE80211_C_WEP | /* s/w WEP */ 707 IEEE80211_C_WPA; /* WPA/RSN */ 708 709 /* set supported .11b and .11g rates */ 710 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 711 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 712 713 /* set supported .11b and .11g channels (1 through 14) */ 714 for (i = 1; i <= 14; i++) { 715 ic->ic_channels[i].ic_freq = 716 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 717 ic->ic_channels[i].ic_flags = 718 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 719 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 720 } 721 722 ifp->if_softc = sc; 723 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 724 if (sc->sc_hwrev & URTW_HWREV_8187) { 725 ifp->if_init = urtw_init; 726 } else { 727 ifp->if_init = urtw_8187b_init; 728 } 729 ifp->if_ioctl = urtw_ioctl; 730 ifp->if_start = urtw_start; 731 ifp->if_watchdog = urtw_watchdog; 732 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 733 IFQ_SET_READY(&ifp->if_snd); 734 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 735 736 if_attach(ifp); 737 ieee80211_ifattach(ic); 738 739 /* override state transition machine */ 740 sc->sc_newstate = ic->ic_newstate; 741 ic->ic_newstate = urtw_newstate; 742 743 /* XXX media locking needs revisiting */ 744 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 745 ieee80211_media_init_with_lock(ic, 746 urtw_media_change, ieee80211_media_status, &sc->sc_media_mtx); 747 748 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 749 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 750 &sc->sc_drvbpf); 751 752 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 753 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 754 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 755 756 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 757 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 758 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 759 760 aprint_normal(", address %s\n", ether_sprintf(ic->ic_myaddr)); 761 762 ieee80211_announce(ic); 763 764 return; 765 fail: 766 aprint_error(": %s failed!\n", __func__); 767 sc->sc_dying = true; 768 } 769 770 static int 771 urtw_detach(device_t self, int flags) 772 { 773 struct urtw_softc *sc = device_private(self); 774 struct ifnet *ifp = &sc->sc_if; 775 int s; 776 777 s = splusb(); 778 779 sc->sc_dying = true; 780 781 callout_halt(&sc->scan_to, NULL); 782 callout_halt(&sc->sc_led_ch, NULL); 783 callout_destroy(&sc->scan_to); 784 callout_destroy(&sc->sc_led_ch); 785 786 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, NULL); 787 usb_rem_task_wait(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER, 788 NULL); 789 790 if (ifp->if_softc != NULL) { 791 bpf_detach(ifp); 792 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 793 if_detach(ifp); 794 } 795 796 /* abort and free xfers */ 797 urtw_free_tx_data_list(sc); 798 urtw_free_rx_data_list(sc); 799 urtw_close_pipes(sc); 800 801 splx(s); 802 803 return 0; 804 } 805 806 static int 807 urtw_activate(device_t self, enum devact act) 808 { 809 struct urtw_softc *sc = device_private(self); 810 811 switch (act) { 812 case DVACT_DEACTIVATE: 813 sc->sc_dying = true; 814 break; 815 } 816 817 return 0; 818 } 819 820 static usbd_status 821 urtw_close_pipes(struct urtw_softc *sc) 822 { 823 usbd_status error = 0; 824 825 if (sc->sc_rxpipe != NULL) { 826 error = usbd_close_pipe(sc->sc_rxpipe); 827 if (error != 0) 828 goto fail; 829 sc->sc_rxpipe = NULL; 830 } 831 if (sc->sc_txpipe_low != NULL) { 832 error = usbd_close_pipe(sc->sc_txpipe_low); 833 if (error != 0) 834 goto fail; 835 sc->sc_txpipe_low = NULL; 836 } 837 if (sc->sc_txpipe_normal != NULL) { 838 error = usbd_close_pipe(sc->sc_txpipe_normal); 839 if (error != 0) 840 goto fail; 841 sc->sc_txpipe_normal = NULL; 842 } 843 fail: 844 return error; 845 } 846 847 static usbd_status 848 urtw_open_pipes(struct urtw_softc *sc) 849 { 850 usbd_status error; 851 852 /* 853 * NB: there is no way to distinguish each pipes so we need to hardcode 854 * pipe numbers 855 */ 856 857 /* tx pipe - low priority packets */ 858 if (sc->sc_hwrev & URTW_HWREV_8187) 859 error = usbd_open_pipe(sc->sc_iface, 0x2, 860 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 861 else 862 error = usbd_open_pipe(sc->sc_iface, 0x6, 863 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 864 if (error != 0) { 865 printf("%s: could not open Tx low pipe: %s\n", 866 device_xname(sc->sc_dev), usbd_errstr(error)); 867 goto fail; 868 } 869 /* tx pipe - normal priority packets */ 870 if (sc->sc_hwrev & URTW_HWREV_8187) 871 error = usbd_open_pipe(sc->sc_iface, 0x3, 872 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 873 else 874 error = usbd_open_pipe(sc->sc_iface, 0x7, 875 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 876 if (error != 0) { 877 printf("%s: could not open Tx normal pipe: %s\n", 878 device_xname(sc->sc_dev), usbd_errstr(error)); 879 goto fail; 880 } 881 /* rx pipe */ 882 if (sc->sc_hwrev & URTW_HWREV_8187) 883 error = usbd_open_pipe(sc->sc_iface, 0x81, 884 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 885 else 886 error = usbd_open_pipe(sc->sc_iface, 0x83, 887 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 888 if (error != 0) { 889 printf("%s: could not open Rx pipe: %s\n", 890 device_xname(sc->sc_dev), usbd_errstr(error)); 891 goto fail; 892 } 893 894 return 0; 895 fail: 896 (void)urtw_close_pipes(sc); 897 return error; 898 } 899 900 static int 901 urtw_alloc_rx_data_list(struct urtw_softc *sc) 902 { 903 int i, error; 904 905 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 906 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 907 908 data->sc = sc; 909 910 error = usbd_create_xfer(sc->sc_rxpipe, MCLBYTES, 911 0, 0, &data->xfer); 912 if (error) { 913 914 printf("%s: could not allocate rx xfer\n", 915 device_xname(sc->sc_dev)); 916 error = ENOMEM; 917 goto fail; 918 } 919 920 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 921 if (data->m == NULL) { 922 printf("%s: could not allocate rx mbuf\n", 923 device_xname(sc->sc_dev)); 924 error = ENOMEM; 925 goto fail; 926 } 927 MCLGET(data->m, M_DONTWAIT); 928 if (!(data->m->m_flags & M_EXT)) { 929 printf("%s: could not allocate rx mbuf cluster\n", 930 device_xname(sc->sc_dev)); 931 error = ENOMEM; 932 goto fail; 933 } 934 data->buf = mtod(data->m, uint8_t *); 935 } 936 937 return 0; 938 939 fail: 940 urtw_free_rx_data_list(sc); 941 return error; 942 } 943 944 static void 945 urtw_free_rx_data_list(struct urtw_softc *sc) 946 { 947 int i; 948 949 /* Make sure no transfers are pending. */ 950 if (sc->sc_rxpipe != NULL) 951 usbd_abort_pipe(sc->sc_rxpipe); 952 953 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 954 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 955 956 if (data->xfer != NULL) { 957 usbd_destroy_xfer(data->xfer); 958 data->xfer = NULL; 959 } 960 if (data->m != NULL) { 961 m_freem(data->m); 962 data->m = NULL; 963 } 964 } 965 } 966 967 static int 968 urtw_alloc_tx_data_list(struct urtw_softc *sc) 969 { 970 int i, error; 971 972 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 973 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 974 struct urtw_tx_data *data = &sc->sc_tx_data[j][i]; 975 976 data->sc = sc; 977 data->ni = NULL; 978 979 error = usbd_create_xfer((j == URTW_PRIORITY_LOW) ? 980 sc->sc_txpipe_low : sc->sc_txpipe_normal, 981 URTW_TX_MAXSIZE, USBD_FORCE_SHORT_XFER, 0, 982 &data->xfer); 983 if (error) { 984 printf("%s: could not allocate tx xfer\n", 985 device_xname(sc->sc_dev)); 986 goto fail; 987 } 988 989 data->buf = usbd_get_buffer(data->xfer); 990 991 if (((unsigned long)data->buf) % 4) 992 printf("%s: warn: unaligned buffer %p\n", 993 device_xname(sc->sc_dev), data->buf); 994 } 995 } 996 997 return 0; 998 999 fail: 1000 urtw_free_tx_data_list(sc); 1001 return error; 1002 } 1003 1004 static void 1005 urtw_free_tx_data_list(struct urtw_softc *sc) 1006 { 1007 int i; 1008 1009 /* Make sure no transfers are pending. */ 1010 if (sc->sc_txpipe_low != NULL) 1011 usbd_abort_pipe(sc->sc_txpipe_low); 1012 if (sc->sc_txpipe_normal != NULL) 1013 usbd_abort_pipe(sc->sc_txpipe_normal); 1014 1015 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 1016 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1017 struct urtw_tx_data *data = &sc->sc_tx_data[j][i]; 1018 1019 if (data->xfer != NULL) { 1020 usbd_destroy_xfer(data->xfer); 1021 data->xfer = NULL; 1022 } 1023 if (data->ni != NULL) { 1024 ieee80211_free_node(data->ni); 1025 data->ni = NULL; 1026 } 1027 } 1028 } 1029 } 1030 1031 static int 1032 urtw_media_change(struct ifnet *ifp) 1033 { 1034 int error; 1035 1036 error = ieee80211_media_change(ifp); 1037 if (error != ENETRESET) 1038 return error; 1039 1040 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1041 (IFF_UP | IFF_RUNNING)) 1042 ifp->if_init(ifp); 1043 1044 return 0; 1045 } 1046 1047 static int 1048 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1049 { 1050 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1051 1052 /* 1053 * XXXSMP: This does not wait for the task, if it is in flight, 1054 * to complete. If this code works at all, it must rely on the 1055 * kernel lock to serialize with the USB task thread. 1056 */ 1057 usb_rem_task(sc->sc_udev, &sc->sc_task); 1058 callout_stop(&sc->scan_to); 1059 1060 /* do it in a process context */ 1061 sc->sc_state = nstate; 1062 sc->sc_arg = arg; 1063 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1064 1065 return 0; 1066 } 1067 1068 static usbd_status 1069 urtw_led_init(struct urtw_softc *sc) 1070 { 1071 uint32_t rev; 1072 usbd_status error; 1073 1074 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1075 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1076 if (error != 0) 1077 goto fail; 1078 1079 switch (rev & URTW_EPROM_CID_MASK) { 1080 case URTW_EPROM_CID_ALPHA0: 1081 sc->sc_strategy = URTW_SW_LED_MODE1; 1082 break; 1083 case URTW_EPROM_CID_SERCOMM_PS: 1084 sc->sc_strategy = URTW_SW_LED_MODE3; 1085 break; 1086 case URTW_EPROM_CID_HW_LED: 1087 sc->sc_strategy = URTW_HW_LED; 1088 break; 1089 case URTW_EPROM_CID_RSVD0: 1090 case URTW_EPROM_CID_RSVD1: 1091 default: 1092 sc->sc_strategy = URTW_SW_LED_MODE0; 1093 break; 1094 } 1095 1096 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1097 1098 fail: 1099 return error; 1100 } 1101 1102 static usbd_status 1103 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1104 uint16_t data) 1105 { 1106 usb_device_request_t req; 1107 1108 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1109 req.bRequest = URTW_8187_SETREGS_REQ; 1110 USETW(req.wValue, addr); 1111 USETW(req.wIndex, index); 1112 USETW(req.wLength, sizeof(uint16_t)); 1113 1114 return usbd_do_request(sc->sc_udev, &req, &data); 1115 } 1116 1117 static usbd_status 1118 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1119 { 1120 int i; 1121 int16_t bit; 1122 uint8_t rlen = 12, wlen = 6; 1123 uint16_t o1, o2, o3, tmp; 1124 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1125 uint32_t mask = 0x80000000, value = 0; 1126 usbd_status error; 1127 1128 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1129 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1130 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1131 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1132 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1133 o1 &= ~0xf; 1134 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1135 DELAY(5); 1136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1137 DELAY(5); 1138 1139 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1140 bit = ((d2w & mask) != 0) ? 1 : 0; 1141 1142 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1143 DELAY(2); 1144 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1145 URTW_BB_HOST_BANG_CLK); 1146 DELAY(2); 1147 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1148 URTW_BB_HOST_BANG_CLK); 1149 DELAY(2); 1150 mask = mask >> 1; 1151 if (i == 2) 1152 break; 1153 bit = ((d2w & mask) != 0) ? 1 : 0; 1154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1155 URTW_BB_HOST_BANG_CLK); 1156 DELAY(2); 1157 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1158 URTW_BB_HOST_BANG_CLK); 1159 DELAY(2); 1160 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1161 DELAY(1); 1162 } 1163 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1164 URTW_BB_HOST_BANG_CLK); 1165 DELAY(2); 1166 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1167 DELAY(2); 1168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1169 DELAY(2); 1170 1171 mask = 0x800; 1172 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1173 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1174 o1 | URTW_BB_HOST_BANG_RW); 1175 DELAY(2); 1176 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1177 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1178 DELAY(2); 1179 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1180 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1181 DELAY(2); 1182 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1183 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1184 DELAY(2); 1185 1186 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1187 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1188 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1189 o1 | URTW_BB_HOST_BANG_RW); 1190 DELAY(2); 1191 } 1192 1193 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1194 URTW_BB_HOST_BANG_RW); 1195 DELAY(2); 1196 1197 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1198 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1199 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1200 1201 if (data != NULL) 1202 *data = value; 1203 fail: 1204 return error; 1205 } 1206 1207 static usbd_status 1208 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1209 { 1210 uint16_t d80, d82, d84; 1211 usbd_status error; 1212 1213 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1214 d80 &= 0xfff3; 1215 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1216 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1217 d84 &= 0xfff0; 1218 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1219 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1220 DELAY(10); 1221 1222 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1223 DELAY(2); 1224 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1225 DELAY(10); 1226 1227 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1228 if (error != 0) 1229 goto fail; 1230 1231 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1232 DELAY(10); 1233 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1234 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1235 usbd_delay_ms(sc->sc_udev, 2); 1236 fail: 1237 return error; 1238 } 1239 1240 static usbd_status 1241 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1242 { 1243 uint32_t data; 1244 usbd_status error; 1245 1246 *ret = 1; 1247 1248 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1249 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1250 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1251 usbd_delay_ms(sc->sc_udev, 500); 1252 1253 urtw_8225_write(sc, 0x0, 0x1b7); 1254 1255 error = urtw_8225_read(sc, 0x8, &data); 1256 if (error != 0) 1257 goto fail; 1258 if (data != 0x588) 1259 *ret = 0; 1260 else { 1261 error = urtw_8225_read(sc, 0x9, &data); 1262 if (error != 0) 1263 goto fail; 1264 if (data != 0x700) 1265 *ret = 0; 1266 } 1267 1268 urtw_8225_write(sc, 0x0, 0xb7); 1269 fail: 1270 return error; 1271 } 1272 1273 static usbd_status 1274 urtw_get_rfchip(struct urtw_softc *sc) 1275 { 1276 struct urtw_rf *rf = &sc->sc_rf; 1277 int ret; 1278 uint32_t data; 1279 usbd_status error; 1280 1281 rf->rf_sc = sc; 1282 1283 if (sc->sc_hwrev & URTW_HWREV_8187) { 1284 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1285 if (error != 0) 1286 panic("unsupported RF chip"); 1287 /* NOTREACHED */ 1288 switch (data & 0xff) { 1289 case URTW_EPROM_RFCHIPID_RTL8225U: 1290 error = urtw_8225_isv2(sc, &ret); 1291 if (error != 0) 1292 goto fail; 1293 if (ret == 0) { 1294 rf->init = urtw_8225_rf_init; 1295 rf->set_chan = urtw_8225_rf_set_chan; 1296 rf->set_sens = urtw_8225_rf_set_sens; 1297 printf(", RFv1"); 1298 } else { 1299 rf->init = urtw_8225v2_rf_init; 1300 rf->set_chan = urtw_8225v2_rf_set_chan; 1301 rf->set_sens = NULL; 1302 printf(", RFv2"); 1303 } 1304 break; 1305 default: 1306 goto fail; 1307 } 1308 } else { 1309 rf->init = urtw_8225v2_b_rf_init; 1310 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1311 rf->set_sens = NULL; 1312 } 1313 1314 rf->max_sens = URTW_8225_RF_MAX_SENS; 1315 rf->sens = URTW_8225_RF_DEF_SENS; 1316 1317 return 0; 1318 1319 fail: 1320 panic("unsupported RF chip %d", data & 0xff); 1321 /* NOTREACHED */ 1322 } 1323 1324 static usbd_status 1325 urtw_get_txpwr(struct urtw_softc *sc) 1326 { 1327 int i, j; 1328 uint32_t data; 1329 usbd_status error; 1330 1331 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1332 if (error != 0) 1333 goto fail; 1334 sc->sc_txpwr_cck_base = data & 0xf; 1335 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1336 1337 for (i = 1, j = 0; i < 6; i += 2, j++) { 1338 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1339 if (error != 0) 1340 goto fail; 1341 sc->sc_txpwr_cck[i] = data & 0xf; 1342 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1343 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1344 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1345 } 1346 for (i = 1, j = 0; i < 4; i += 2, j++) { 1347 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1348 if (error != 0) 1349 goto fail; 1350 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1351 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1352 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1353 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1354 } 1355 if (sc->sc_hwrev & URTW_HWREV_8187) { 1356 for (i = 1, j = 0; i < 4; i += 2, j++) { 1357 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1358 &data); 1359 if (error != 0) 1360 goto fail; 1361 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1362 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1363 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1364 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1365 (data & 0xf000) >> 12; 1366 } 1367 } else { 1368 /* Channel 11. */ 1369 error = urtw_eprom_read32(sc, 0x1b, &data); 1370 if (error != 0) 1371 goto fail; 1372 sc->sc_txpwr_cck[11] = data & 0xf; 1373 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1374 1375 /* Channel 12. */ 1376 error = urtw_eprom_read32(sc, 0xa, &data); 1377 if (error != 0) 1378 goto fail; 1379 sc->sc_txpwr_cck[12] = data & 0xf; 1380 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1381 1382 /* Channel 13, 14. */ 1383 error = urtw_eprom_read32(sc, 0x1c, &data); 1384 if (error != 0) 1385 goto fail; 1386 sc->sc_txpwr_cck[13] = data & 0xf; 1387 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1388 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1389 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1390 } 1391 fail: 1392 return error; 1393 } 1394 1395 static usbd_status 1396 urtw_get_macaddr(struct urtw_softc *sc) 1397 { 1398 struct ieee80211com *ic = &sc->sc_ic; 1399 usbd_status error; 1400 uint32_t data; 1401 1402 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1403 if (error != 0) 1404 goto fail; 1405 ic->ic_myaddr[0] = data & 0xff; 1406 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1407 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1408 if (error != 0) 1409 goto fail; 1410 ic->ic_myaddr[2] = data & 0xff; 1411 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1412 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1413 if (error != 0) 1414 goto fail; 1415 ic->ic_myaddr[4] = data & 0xff; 1416 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1417 fail: 1418 return error; 1419 } 1420 1421 static usbd_status 1422 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1423 { 1424 #define URTW_READCMD_LEN 3 1425 int addrlen, i; 1426 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1427 usbd_status error; 1428 1429 /* NB: make sure the buffer is initialized */ 1430 *data = 0; 1431 1432 /* enable EPROM programming */ 1433 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1434 DELAY(URTW_EPROM_DELAY); 1435 1436 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1437 if (error != 0) 1438 goto fail; 1439 error = urtw_eprom_ck(sc); 1440 if (error != 0) 1441 goto fail; 1442 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1443 if (error != 0) 1444 goto fail; 1445 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1446 addrlen = 8; 1447 addrstr[0] = addr & (1 << 7); 1448 addrstr[1] = addr & (1 << 6); 1449 addrstr[2] = addr & (1 << 5); 1450 addrstr[3] = addr & (1 << 4); 1451 addrstr[4] = addr & (1 << 3); 1452 addrstr[5] = addr & (1 << 2); 1453 addrstr[6] = addr & (1 << 1); 1454 addrstr[7] = addr & (1 << 0); 1455 } else { 1456 addrlen=6; 1457 addrstr[0] = addr & (1 << 5); 1458 addrstr[1] = addr & (1 << 4); 1459 addrstr[2] = addr & (1 << 3); 1460 addrstr[3] = addr & (1 << 2); 1461 addrstr[4] = addr & (1 << 1); 1462 addrstr[5] = addr & (1 << 0); 1463 } 1464 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1465 if (error != 0) 1466 goto fail; 1467 1468 error = urtw_eprom_writebit(sc, 0); 1469 if (error != 0) 1470 goto fail; 1471 1472 for (i = 0; i < 16; i++) { 1473 error = urtw_eprom_ck(sc); 1474 if (error != 0) 1475 goto fail; 1476 error = urtw_eprom_readbit(sc, &data16); 1477 if (error != 0) 1478 goto fail; 1479 1480 (*data) |= (data16 << (15 - i)); 1481 } 1482 1483 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1484 if (error != 0) 1485 goto fail; 1486 error = urtw_eprom_ck(sc); 1487 if (error != 0) 1488 goto fail; 1489 1490 /* now disable EPROM programming */ 1491 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1492 fail: 1493 return error; 1494 #undef URTW_READCMD_LEN 1495 } 1496 1497 static usbd_status 1498 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1499 { 1500 uint8_t data8; 1501 usbd_status error; 1502 1503 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1504 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1505 DELAY(URTW_EPROM_DELAY); 1506 1507 fail: 1508 return error; 1509 } 1510 1511 static usbd_status 1512 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1513 { 1514 int i = 0; 1515 usbd_status error = 0; 1516 1517 for (i = 0; i < buflen; i++) { 1518 error = urtw_eprom_writebit(sc, buf[i]); 1519 if (error != 0) 1520 goto fail; 1521 error = urtw_eprom_ck(sc); 1522 if (error != 0) 1523 goto fail; 1524 } 1525 fail: 1526 return error; 1527 } 1528 1529 static usbd_status 1530 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1531 { 1532 uint8_t data; 1533 usbd_status error; 1534 1535 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1536 if (bit != 0) 1537 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1538 else 1539 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1540 DELAY(URTW_EPROM_DELAY); 1541 fail: 1542 return error; 1543 } 1544 1545 static usbd_status 1546 urtw_eprom_ck(struct urtw_softc *sc) 1547 { 1548 uint8_t data; 1549 usbd_status error; 1550 1551 /* masking */ 1552 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1553 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1554 DELAY(URTW_EPROM_DELAY); 1555 /* unmasking */ 1556 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1557 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1558 DELAY(URTW_EPROM_DELAY); 1559 fail: 1560 return error; 1561 } 1562 1563 static usbd_status 1564 urtw_eprom_cs(struct urtw_softc *sc, int able) 1565 { 1566 uint8_t data; 1567 usbd_status error; 1568 1569 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1570 if (able == URTW_EPROM_ENABLE) 1571 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1572 else 1573 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1574 DELAY(URTW_EPROM_DELAY); 1575 fail: 1576 return error; 1577 } 1578 1579 static usbd_status 1580 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1581 { 1582 usb_device_request_t req; 1583 usbd_status error; 1584 1585 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1586 req.bRequest = URTW_8187_GETREGS_REQ; 1587 USETW(req.wValue, val | 0xff00); 1588 USETW(req.wIndex, idx & 0x03); 1589 USETW(req.wLength, sizeof(uint8_t)); 1590 1591 error = usbd_do_request(sc->sc_udev, &req, data); 1592 return error; 1593 } 1594 1595 static usbd_status 1596 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1597 { 1598 usb_device_request_t req; 1599 usbd_status error; 1600 1601 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1602 req.bRequest = URTW_8187_GETREGS_REQ; 1603 USETW(req.wValue, val | 0xfe00); 1604 USETW(req.wIndex, 0); 1605 USETW(req.wLength, sizeof(uint8_t)); 1606 1607 error = usbd_do_request(sc->sc_udev, &req, data); 1608 return error; 1609 } 1610 1611 static usbd_status 1612 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1613 { 1614 usb_device_request_t req; 1615 usbd_status error; 1616 1617 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1618 req.bRequest = URTW_8187_GETREGS_REQ; 1619 USETW(req.wValue, val | 0xff00); 1620 USETW(req.wIndex, idx & 0x03); 1621 USETW(req.wLength, sizeof(uint16_t)); 1622 1623 error = usbd_do_request(sc->sc_udev, &req, data); 1624 return error; 1625 } 1626 1627 static usbd_status 1628 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1629 { 1630 usb_device_request_t req; 1631 usbd_status error; 1632 1633 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1634 req.bRequest = URTW_8187_GETREGS_REQ; 1635 USETW(req.wValue, val | 0xff00); 1636 USETW(req.wIndex, idx & 0x03); 1637 USETW(req.wLength, sizeof(uint32_t)); 1638 1639 error = usbd_do_request(sc->sc_udev, &req, data); 1640 return error; 1641 } 1642 1643 static usbd_status 1644 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1645 { 1646 usb_device_request_t req; 1647 1648 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1649 req.bRequest = URTW_8187_SETREGS_REQ; 1650 USETW(req.wValue, val | 0xff00); 1651 USETW(req.wIndex, idx & 0x03); 1652 USETW(req.wLength, sizeof(uint8_t)); 1653 1654 return usbd_do_request(sc->sc_udev, &req, &data); 1655 } 1656 1657 static usbd_status 1658 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1659 { 1660 usb_device_request_t req; 1661 1662 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1663 req.bRequest = URTW_8187_SETREGS_REQ; 1664 USETW(req.wValue, val | 0xfe00); 1665 USETW(req.wIndex, 0); 1666 USETW(req.wLength, sizeof(uint8_t)); 1667 1668 return usbd_do_request(sc->sc_udev, &req, &data); 1669 } 1670 1671 static usbd_status 1672 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1673 { 1674 usb_device_request_t req; 1675 1676 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1677 req.bRequest = URTW_8187_SETREGS_REQ; 1678 USETW(req.wValue, val | 0xff00); 1679 USETW(req.wIndex, idx & 0x03); 1680 USETW(req.wLength, sizeof(uint16_t)); 1681 1682 return usbd_do_request(sc->sc_udev, &req, &data); 1683 } 1684 1685 static usbd_status 1686 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1687 { 1688 usb_device_request_t req; 1689 1690 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1691 req.bRequest = URTW_8187_SETREGS_REQ; 1692 USETW(req.wValue, val | 0xff00); 1693 USETW(req.wIndex, idx & 0x03); 1694 USETW(req.wLength, sizeof(uint32_t)); 1695 1696 return usbd_do_request(sc->sc_udev, &req, &data); 1697 } 1698 1699 static usbd_status 1700 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1701 { 1702 uint8_t data; 1703 usbd_status error; 1704 1705 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1706 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1707 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1708 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1709 fail: 1710 return error; 1711 } 1712 1713 static usbd_status 1714 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1715 { 1716 uint8_t data; 1717 usbd_status error; 1718 1719 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1720 if (error) 1721 goto fail; 1722 1723 urtw_read8_m(sc, URTW_CONFIG3, &data); 1724 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1725 urtw_write32_m(sc, URTW_ANAPARAM, val); 1726 urtw_read8_m(sc, URTW_CONFIG3, &data); 1727 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1728 1729 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1730 if (error) 1731 goto fail; 1732 fail: 1733 return error; 1734 } 1735 1736 static usbd_status 1737 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1738 { 1739 uint8_t data; 1740 usbd_status error; 1741 1742 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1743 if (error) 1744 goto fail; 1745 1746 urtw_read8_m(sc, URTW_CONFIG3, &data); 1747 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1748 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1749 urtw_read8_m(sc, URTW_CONFIG3, &data); 1750 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1751 1752 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1753 if (error) 1754 goto fail; 1755 fail: 1756 return error; 1757 } 1758 1759 static usbd_status 1760 urtw_intr_disable(struct urtw_softc *sc) 1761 { 1762 usbd_status error; 1763 1764 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1765 1766 fail: 1767 return error; 1768 } 1769 1770 static usbd_status 1771 urtw_reset(struct urtw_softc *sc) 1772 { 1773 uint8_t data; 1774 usbd_status error; 1775 1776 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1777 if (error) 1778 goto fail; 1779 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1780 if (error) 1781 goto fail; 1782 1783 error = urtw_intr_disable(sc); 1784 if (error) 1785 goto fail; 1786 usbd_delay_ms(sc->sc_udev, 100); 1787 1788 error = urtw_write8e(sc, 0x18, 0x10); 1789 if (error != 0) 1790 goto fail; 1791 error = urtw_write8e(sc, 0x18, 0x11); 1792 if (error != 0) 1793 goto fail; 1794 error = urtw_write8e(sc, 0x18, 0x00); 1795 if (error != 0) 1796 goto fail; 1797 usbd_delay_ms(sc->sc_udev, 100); 1798 1799 urtw_read8_m(sc, URTW_CMD, &data); 1800 data = (data & 2) | URTW_CMD_RST; 1801 urtw_write8_m(sc, URTW_CMD, data); 1802 usbd_delay_ms(sc->sc_udev, 100); 1803 1804 urtw_read8_m(sc, URTW_CMD, &data); 1805 if (data & URTW_CMD_RST) { 1806 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1807 goto fail; 1808 } 1809 1810 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1811 if (error) 1812 goto fail; 1813 usbd_delay_ms(sc->sc_udev, 100); 1814 1815 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1816 if (error) 1817 goto fail; 1818 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1819 if (error) 1820 goto fail; 1821 fail: 1822 return error; 1823 } 1824 1825 static usbd_status 1826 urtw_led_on(struct urtw_softc *sc, int type) 1827 { 1828 usbd_status error; 1829 1830 if (type == URTW_LED_GPIO) { 1831 switch (sc->sc_gpio_ledpin) { 1832 case URTW_LED_PIN_GPIO0: 1833 urtw_write8_m(sc, URTW_GPIO, 0x01); 1834 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1835 break; 1836 default: 1837 panic("unsupported LED PIN type %#x", 1838 sc->sc_gpio_ledpin); 1839 /* NOTREACHED */ 1840 } 1841 } else { 1842 panic("unsupported LED type %#x", type); 1843 /* NOTREACHED */ 1844 } 1845 1846 sc->sc_gpio_ledon = 1; 1847 fail: 1848 return error; 1849 } 1850 1851 static usbd_status 1852 urtw_led_off(struct urtw_softc *sc, int type) 1853 { 1854 usbd_status error; 1855 1856 if (type == URTW_LED_GPIO) { 1857 switch (sc->sc_gpio_ledpin) { 1858 case URTW_LED_PIN_GPIO0: 1859 urtw_write8_m(sc, URTW_GPIO, 0x01); 1860 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1861 break; 1862 default: 1863 panic("unsupported LED PIN type %#x", 1864 sc->sc_gpio_ledpin); 1865 /* NOTREACHED */ 1866 } 1867 } else { 1868 panic("unsupported LED type %#x", type); 1869 /* NOTREACHED */ 1870 } 1871 1872 sc->sc_gpio_ledon = 0; 1873 1874 fail: 1875 return error; 1876 } 1877 1878 static usbd_status 1879 urtw_led_mode0(struct urtw_softc *sc, int mode) 1880 { 1881 switch (mode) { 1882 case URTW_LED_CTL_POWER_ON: 1883 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1884 break; 1885 case URTW_LED_CTL_TX: 1886 if (sc->sc_gpio_ledinprogress == 1) 1887 return 0; 1888 1889 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1890 sc->sc_gpio_blinktime = 2; 1891 break; 1892 case URTW_LED_CTL_LINK: 1893 sc->sc_gpio_ledstate = URTW_LED_ON; 1894 break; 1895 default: 1896 panic("unsupported LED mode %#x", mode); 1897 /* NOTREACHED */ 1898 } 1899 1900 switch (sc->sc_gpio_ledstate) { 1901 case URTW_LED_ON: 1902 if (sc->sc_gpio_ledinprogress != 0) 1903 break; 1904 urtw_led_on(sc, URTW_LED_GPIO); 1905 break; 1906 case URTW_LED_BLINK_NORMAL: 1907 if (sc->sc_gpio_ledinprogress != 0) 1908 break; 1909 sc->sc_gpio_ledinprogress = 1; 1910 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1911 URTW_LED_OFF : URTW_LED_ON; 1912 if (!sc->sc_dying) 1913 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1914 break; 1915 case URTW_LED_POWER_ON_BLINK: 1916 urtw_led_on(sc, URTW_LED_GPIO); 1917 usbd_delay_ms(sc->sc_udev, 100); 1918 urtw_led_off(sc, URTW_LED_GPIO); 1919 break; 1920 default: 1921 panic("unknown LED status %#x", sc->sc_gpio_ledstate); 1922 /* NOTREACHED */ 1923 } 1924 return 0; 1925 } 1926 1927 static usbd_status 1928 urtw_led_mode1(struct urtw_softc *sc, int mode) 1929 { 1930 return USBD_INVAL; 1931 } 1932 1933 static usbd_status 1934 urtw_led_mode2(struct urtw_softc *sc, int mode) 1935 { 1936 return USBD_INVAL; 1937 } 1938 1939 static usbd_status 1940 urtw_led_mode3(struct urtw_softc *sc, int mode) 1941 { 1942 return USBD_INVAL; 1943 } 1944 1945 static void 1946 urtw_ledusbtask(void *arg) 1947 { 1948 struct urtw_softc *sc = arg; 1949 1950 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1951 panic("could not process a LED strategy %#x", sc->sc_strategy); 1952 1953 urtw_led_blink(sc); 1954 } 1955 1956 static void 1957 urtw_ledtask(void *arg) 1958 { 1959 struct urtw_softc *sc = arg; 1960 1961 /* 1962 * NB: to change a status of the led we need at least a sleep so we 1963 * can't do it here 1964 */ 1965 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1966 } 1967 1968 static usbd_status 1969 urtw_led_ctl(struct urtw_softc *sc, int mode) 1970 { 1971 usbd_status error = 0; 1972 1973 switch (sc->sc_strategy) { 1974 case URTW_SW_LED_MODE0: 1975 error = urtw_led_mode0(sc, mode); 1976 break; 1977 case URTW_SW_LED_MODE1: 1978 error = urtw_led_mode1(sc, mode); 1979 break; 1980 case URTW_SW_LED_MODE2: 1981 error = urtw_led_mode2(sc, mode); 1982 break; 1983 case URTW_SW_LED_MODE3: 1984 error = urtw_led_mode3(sc, mode); 1985 break; 1986 default: 1987 panic("unsupported LED mode %d", sc->sc_strategy); 1988 /* NOTREACHED */ 1989 } 1990 1991 return error; 1992 } 1993 1994 static usbd_status 1995 urtw_led_blink(struct urtw_softc *sc) 1996 { 1997 uint8_t ing = 0; 1998 1999 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 2000 (void)urtw_led_on(sc, URTW_LED_GPIO); 2001 else 2002 (void)urtw_led_off(sc, URTW_LED_GPIO); 2003 sc->sc_gpio_blinktime--; 2004 if (sc->sc_gpio_blinktime == 0) 2005 ing = 1; 2006 else { 2007 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 2008 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 2009 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 2010 ing = 1; 2011 } 2012 if (ing == 1) { 2013 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2014 sc->sc_gpio_ledon == 0) 2015 (void)urtw_led_on(sc, URTW_LED_GPIO); 2016 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2017 sc->sc_gpio_ledon == 1) 2018 (void)urtw_led_off(sc, URTW_LED_GPIO); 2019 2020 sc->sc_gpio_blinktime = 0; 2021 sc->sc_gpio_ledinprogress = 0; 2022 return 0; 2023 } 2024 2025 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2026 URTW_LED_ON : URTW_LED_OFF; 2027 2028 switch (sc->sc_gpio_ledstate) { 2029 case URTW_LED_BLINK_NORMAL: 2030 if (!sc->sc_dying) 2031 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2032 break; 2033 default: 2034 panic("unknown LED status %#x", sc->sc_gpio_ledstate); 2035 /* NOTREACHED */ 2036 } 2037 return 0; 2038 } 2039 2040 static usbd_status 2041 urtw_update_msr(struct urtw_softc *sc) 2042 { 2043 struct ieee80211com *ic = &sc->sc_ic; 2044 uint8_t data; 2045 usbd_status error; 2046 2047 urtw_read8_m(sc, URTW_MSR, &data); 2048 data &= ~URTW_MSR_LINK_MASK; 2049 2050 /* Should always be set. */ 2051 if (sc->sc_hwrev & URTW_HWREV_8187B) 2052 data |= URTW_MSR_LINK_ENEDCA; 2053 2054 if (sc->sc_state == IEEE80211_S_RUN) { 2055 switch (ic->ic_opmode) { 2056 case IEEE80211_M_STA: 2057 case IEEE80211_M_MONITOR: 2058 data |= URTW_MSR_LINK_STA; 2059 break; 2060 default: 2061 panic("unsupported operation mode %#x", 2062 ic->ic_opmode); 2063 /* NOTREACHED */ 2064 } 2065 } else 2066 data |= URTW_MSR_LINK_NONE; 2067 2068 urtw_write8_m(sc, URTW_MSR, data); 2069 fail: 2070 return error; 2071 } 2072 2073 static uint16_t 2074 urtw_rate2rtl(int rate) 2075 { 2076 unsigned int i; 2077 2078 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2079 if (rate == urtw_ratetable[i].reg) 2080 return urtw_ratetable[i].val; 2081 } 2082 2083 return 3; 2084 } 2085 2086 static uint16_t 2087 urtw_rtl2rate(int rate) 2088 { 2089 unsigned int i; 2090 2091 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2092 if (rate == urtw_ratetable[i].val) 2093 return urtw_ratetable[i].reg; 2094 } 2095 2096 return 0; 2097 } 2098 2099 static usbd_status 2100 urtw_set_rate(struct urtw_softc *sc) 2101 { 2102 int i, basic_rate, min_rr_rate, max_rr_rate; 2103 uint16_t data; 2104 usbd_status error; 2105 2106 basic_rate = urtw_rate2rtl(48); 2107 min_rr_rate = urtw_rate2rtl(12); 2108 max_rr_rate = urtw_rate2rtl(48); 2109 2110 urtw_write8_m(sc, URTW_RESP_RATE, 2111 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2112 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2113 2114 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2115 data &= ~URTW_BRSR_MBR_8185; 2116 2117 for (i = 0; i <= basic_rate; i++) 2118 data |= (1 << i); 2119 2120 urtw_write16_m(sc, URTW_8187_BRSR, data); 2121 fail: 2122 return error; 2123 } 2124 2125 static usbd_status 2126 urtw_intr_enable(struct urtw_softc *sc) 2127 { 2128 usbd_status error; 2129 2130 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2131 fail: 2132 return error; 2133 } 2134 2135 static usbd_status 2136 urtw_rx_setconf(struct urtw_softc *sc) 2137 { 2138 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2139 struct ieee80211com *ic = &sc->sc_ic; 2140 uint32_t data; 2141 usbd_status error; 2142 2143 urtw_read32_m(sc, URTW_RX, &data); 2144 data = data &~ URTW_RX_FILTER_MASK; 2145 #if 0 2146 data = data | URTW_RX_FILTER_CTL; 2147 #endif 2148 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2149 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2150 2151 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2152 data = data | URTW_RX_FILTER_ICVERR; 2153 data = data | URTW_RX_FILTER_PWR; 2154 } 2155 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2156 data = data | URTW_RX_FILTER_CRCERR; 2157 2158 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2159 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2160 data = data | URTW_RX_FILTER_ALLMAC; 2161 } else { 2162 data = data | URTW_RX_FILTER_NICMAC; 2163 data = data | URTW_RX_CHECK_BSSID; 2164 } 2165 2166 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2167 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2168 data = data &~ URTW_MAX_RX_DMA_MASK; 2169 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2170 2171 urtw_write32_m(sc, URTW_RX, data); 2172 fail: 2173 return error; 2174 } 2175 2176 static usbd_status 2177 urtw_rx_enable(struct urtw_softc *sc) 2178 { 2179 int i; 2180 struct urtw_rx_data *rx_data; 2181 uint8_t data; 2182 usbd_status error; 2183 2184 /* 2185 * Start up the receive pipe. 2186 */ 2187 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2188 rx_data = &sc->sc_rx_data[i]; 2189 2190 usbd_setup_xfer(rx_data->xfer, rx_data, rx_data->buf, MCLBYTES, 2191 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 2192 error = usbd_transfer(rx_data->xfer); 2193 if (error != USBD_IN_PROGRESS && error != 0) { 2194 printf("%s: could not queue Rx transfer\n", 2195 device_xname(sc->sc_dev)); 2196 goto fail; 2197 } 2198 } 2199 2200 error = urtw_rx_setconf(sc); 2201 if (error != 0) 2202 goto fail; 2203 2204 urtw_read8_m(sc, URTW_CMD, &data); 2205 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2206 fail: 2207 return error; 2208 } 2209 2210 static usbd_status 2211 urtw_tx_enable(struct urtw_softc *sc) 2212 { 2213 uint8_t data8; 2214 uint32_t data; 2215 usbd_status error; 2216 2217 if (sc->sc_hwrev & URTW_HWREV_8187) { 2218 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2219 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2220 URTW_CW_CONF_PERPACKET_RETRY); 2221 urtw_write8_m(sc, URTW_CW_CONF, data8); 2222 2223 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2224 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2225 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2226 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2227 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2228 2229 urtw_read32_m(sc, URTW_TX_CONF, &data); 2230 data &= ~URTW_TX_LOOPBACK_MASK; 2231 data |= URTW_TX_LOOPBACK_NONE; 2232 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2233 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2234 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2235 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2236 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2237 data &= ~URTW_TX_SWPLCPLEN; 2238 data |= URTW_TX_NOICV; 2239 urtw_write32_m(sc, URTW_TX_CONF, data); 2240 } else { 2241 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2242 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2243 URTW_TX_LONGRETRY; 2244 urtw_write32_m(sc, URTW_TX_CONF, data); 2245 } 2246 2247 urtw_read8_m(sc, URTW_CMD, &data8); 2248 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2249 fail: 2250 return error; 2251 } 2252 2253 static int 2254 urtw_init(struct ifnet *ifp) 2255 { 2256 struct urtw_softc *sc = ifp->if_softc; 2257 struct urtw_rf *rf = &sc->sc_rf; 2258 struct ieee80211com *ic = &sc->sc_ic; 2259 usbd_status error; 2260 2261 urtw_stop(ifp, 0); 2262 2263 error = urtw_reset(sc); 2264 if (error) 2265 goto fail; 2266 2267 urtw_write8_m(sc, 0x85, 0); 2268 urtw_write8_m(sc, URTW_GPIO, 0); 2269 2270 /* for led */ 2271 urtw_write8_m(sc, 0x85, 4); 2272 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2273 if (error != 0) 2274 goto fail; 2275 2276 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2277 if (error) 2278 goto fail; 2279 2280 /* applying MAC address again. */ 2281 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2282 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2283 if (error) 2284 goto fail; 2285 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2286 if (error) 2287 goto fail; 2288 2289 error = urtw_update_msr(sc); 2290 if (error) 2291 goto fail; 2292 2293 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2294 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2295 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2296 error = urtw_set_rate(sc); 2297 if (error != 0) 2298 goto fail; 2299 2300 error = rf->init(rf); 2301 if (error != 0) 2302 goto fail; 2303 if (rf->set_sens != NULL) 2304 rf->set_sens(rf); 2305 2306 urtw_write16_m(sc, 0x5e, 1); 2307 urtw_write16_m(sc, 0xfe, 0x10); 2308 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2309 urtw_write8_m(sc, 0xff, 0x60); 2310 urtw_write16_m(sc, 0x5e, 0); 2311 urtw_write8_m(sc, 0x85, 4); 2312 2313 error = urtw_intr_enable(sc); 2314 if (error != 0) 2315 goto fail; 2316 2317 /* reset softc variables */ 2318 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 2319 sc->sc_txidx[j] = sc->sc_tx_queued[j] = 0; 2320 } 2321 sc->sc_txtimer = 0; 2322 2323 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2324 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2325 if (error != 0) { 2326 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2327 ", err=%s\n", usbd_errstr(error)); 2328 goto fail; 2329 } 2330 /* get the first interface handle */ 2331 error = usbd_device2interface_handle(sc->sc_udev, 2332 URTW_IFACE_INDEX, &sc->sc_iface); 2333 if (error != 0) { 2334 printf("%s: could not get interface handle\n", 2335 device_xname(sc->sc_dev)); 2336 goto fail; 2337 } 2338 error = urtw_open_pipes(sc); 2339 if (error != 0) 2340 goto fail; 2341 error = urtw_alloc_rx_data_list(sc); 2342 if (error != 0) 2343 goto fail; 2344 error = urtw_alloc_tx_data_list(sc); 2345 if (error != 0) 2346 goto fail; 2347 sc->sc_flags |= URTW_INIT_ONCE; 2348 } 2349 2350 error = urtw_rx_enable(sc); 2351 if (error != 0) 2352 goto fail; 2353 error = urtw_tx_enable(sc); 2354 if (error != 0) 2355 goto fail; 2356 2357 ifp->if_flags &= ~IFF_OACTIVE; 2358 ifp->if_flags |= IFF_RUNNING; 2359 2360 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2361 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2362 else 2363 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2364 2365 return 0; 2366 fail: 2367 return error; 2368 } 2369 2370 static int 2371 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2372 { 2373 #define IS_RUNNING(ifp) \ 2374 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2375 2376 struct urtw_softc *sc = ifp->if_softc; 2377 struct ieee80211com *ic = &sc->sc_ic; 2378 int s, error = 0; 2379 2380 if (sc->sc_dying) 2381 return ENXIO; 2382 2383 s = splnet(); 2384 2385 switch (cmd) { 2386 case SIOCSIFFLAGS: 2387 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2388 break; 2389 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2390 case IFF_UP|IFF_RUNNING: 2391 break; 2392 case IFF_UP: 2393 ifp->if_init(ifp); 2394 break; 2395 case IFF_RUNNING: 2396 urtw_stop(ifp, 1); 2397 break; 2398 case 0: 2399 break; 2400 } 2401 break; 2402 2403 case SIOCADDMULTI: 2404 case SIOCDELMULTI: 2405 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2406 error = 0; 2407 break; 2408 2409 default: 2410 error = ieee80211_ioctl(ic, cmd, data); 2411 break; 2412 } 2413 2414 if (error == ENETRESET) { 2415 if (IS_RUNNING(ifp) && 2416 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2417 ifp->if_init(ifp); 2418 error = 0; 2419 } 2420 2421 splx(s); 2422 2423 return error; 2424 #undef IS_RUNNING 2425 } 2426 2427 static void 2428 urtw_start(struct ifnet *ifp) 2429 { 2430 struct urtw_softc *sc = ifp->if_softc; 2431 struct ieee80211com *ic = &sc->sc_ic; 2432 struct ieee80211_node *ni; 2433 struct ether_header *eh; 2434 struct mbuf *m0; 2435 2436 /* 2437 * net80211 may still try to send management frames even if the 2438 * IFF_RUNNING flag is not set... 2439 */ 2440 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2441 return; 2442 2443 for (;;) { 2444 IF_POLL(&ic->ic_mgtq, m0); 2445 if (m0 != NULL) { 2446 2447 if (sc->sc_tx_queued[URTW_PRIORITY_NORMAL] >= 2448 URTW_TX_DATA_LIST_COUNT) { 2449 ifp->if_flags |= IFF_OACTIVE; 2450 break; 2451 } 2452 IF_DEQUEUE(&ic->ic_mgtq, m0); 2453 ni = M_GETCTX(m0, struct ieee80211_node *); 2454 M_CLEARCTX(m0); 2455 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 2456 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2457 != 0) 2458 break; 2459 } else { 2460 if (ic->ic_state != IEEE80211_S_RUN) 2461 break; 2462 IFQ_POLL(&ifp->if_snd, m0); 2463 if (m0 == NULL) 2464 break; 2465 if (sc->sc_tx_queued[URTW_PRIORITY_NORMAL] >= 2466 URTW_TX_DATA_LIST_COUNT) { 2467 ifp->if_flags |= IFF_OACTIVE; 2468 break; 2469 } 2470 IFQ_DEQUEUE(&ifp->if_snd, m0); 2471 if (m0->m_len < sizeof(struct ether_header) && 2472 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2473 continue; 2474 2475 eh = mtod(m0, struct ether_header *); 2476 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2477 if (ni == NULL) { 2478 m_freem(m0); 2479 continue; 2480 } 2481 bpf_mtap(ifp, m0, BPF_D_OUT); 2482 m0 = ieee80211_encap(ic, m0, ni); 2483 if (m0 == NULL) { 2484 ieee80211_free_node(ni); 2485 continue; 2486 } 2487 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 2488 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2489 != 0) { 2490 ieee80211_free_node(ni); 2491 if_statinc(ifp, if_oerrors); 2492 break; 2493 } 2494 } 2495 sc->sc_txtimer = 5; 2496 ifp->if_timer = 1; 2497 } 2498 } 2499 2500 static void 2501 urtw_watchdog(struct ifnet *ifp) 2502 { 2503 struct urtw_softc *sc = ifp->if_softc; 2504 2505 ifp->if_timer = 0; 2506 2507 if (sc->sc_txtimer > 0) { 2508 if (--sc->sc_txtimer == 0) { 2509 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2510 if_statinc(ifp, if_oerrors); 2511 return; 2512 } 2513 ifp->if_timer = 1; 2514 } 2515 2516 ieee80211_watchdog(&sc->sc_ic); 2517 } 2518 2519 static void 2520 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2521 usbd_status status) 2522 { 2523 struct urtw_tx_data *data = priv; 2524 struct urtw_softc *sc = data->sc; 2525 struct ieee80211com *ic = &sc->sc_ic; 2526 struct ifnet *ifp = ic->ic_ifp; 2527 int s; 2528 2529 if (status != USBD_NORMAL_COMPLETION) { 2530 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2531 return; 2532 2533 printf("%s: could not transmit buffer: %s\n", 2534 device_xname(sc->sc_dev), usbd_errstr(status)); 2535 2536 if (status == USBD_STALLED) 2537 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2538 2539 if_statinc(ifp, if_oerrors); 2540 return; 2541 } 2542 2543 s = splnet(); 2544 2545 ieee80211_free_node(data->ni); 2546 data->ni = NULL; 2547 2548 sc->sc_txtimer = 0; 2549 if_statinc(ifp, if_opackets); 2550 2551 sc->sc_tx_queued[URTW_PRIORITY_LOW]--; 2552 ifp->if_flags &= ~IFF_OACTIVE; 2553 urtw_start(ifp); 2554 2555 splx(s); 2556 } 2557 2558 static void 2559 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2560 usbd_status status) 2561 { 2562 struct urtw_tx_data *data = priv; 2563 struct urtw_softc *sc = data->sc; 2564 struct ieee80211com *ic = &sc->sc_ic; 2565 struct ifnet *ifp = ic->ic_ifp; 2566 int s; 2567 2568 if (status != USBD_NORMAL_COMPLETION) { 2569 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2570 return; 2571 2572 printf("%s: could not transmit buffer: %s\n", 2573 device_xname(sc->sc_dev), usbd_errstr(status)); 2574 2575 if (status == USBD_STALLED) 2576 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2577 2578 if_statinc(ifp, if_oerrors); 2579 return; 2580 } 2581 2582 s = splnet(); 2583 2584 ieee80211_free_node(data->ni); 2585 data->ni = NULL; 2586 2587 sc->sc_txtimer = 0; 2588 if_statinc(ifp, if_opackets); 2589 2590 sc->sc_tx_queued[URTW_PRIORITY_NORMAL]--; 2591 ifp->if_flags &= ~IFF_OACTIVE; 2592 urtw_start(ifp); 2593 2594 splx(s); 2595 } 2596 2597 static int 2598 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2599 int prior) 2600 { 2601 struct ieee80211com *ic = &sc->sc_ic; 2602 struct urtw_tx_data *data; 2603 struct ieee80211_frame *wh; 2604 struct ieee80211_key *k; 2605 usbd_status error; 2606 int xferlen; 2607 2608 wh = mtod(m0, struct ieee80211_frame *); 2609 2610 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2611 k = ieee80211_crypto_encap(ic, ni, m0); 2612 if (k == NULL) { 2613 m_freem(m0); 2614 return ENOBUFS; 2615 } 2616 /* packet header may have moved, reset our local pointer */ 2617 wh = mtod(m0, struct ieee80211_frame *); 2618 } 2619 2620 if (sc->sc_drvbpf != NULL) { 2621 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2622 2623 tap->wt_flags = 0; 2624 tap->wt_rate = 0; 2625 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2626 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2627 2628 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 2629 } 2630 2631 if (sc->sc_hwrev & URTW_HWREV_8187) 2632 xferlen = m0->m_pkthdr.len + 4 * 3; 2633 else 2634 xferlen = m0->m_pkthdr.len + 4 * 8; 2635 2636 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2637 xferlen += 1; 2638 2639 data = &sc->sc_tx_data[prior][sc->sc_txidx[prior]]; 2640 sc->sc_txidx[prior] = 2641 (sc->sc_txidx[prior] + 1) % URTW_TX_DATA_LIST_COUNT; 2642 2643 memset(data->buf, 0, URTW_TX_MAXSIZE); 2644 data->buf[0] = m0->m_pkthdr.len & 0xff; 2645 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2646 data->buf[1] |= (1 << 7); 2647 2648 /* XXX sc_preamble_mode is always 2. */ 2649 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2650 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2651 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2652 data->buf[2] |= 1; 2653 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2654 prior == URTW_PRIORITY_LOW) 2655 panic("TODO tx."); 2656 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2657 data->buf[2] |= (1 << 1); 2658 /* RTS rate - 10 means we use a basic rate. */ 2659 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2660 /* 2661 * XXX currently TX rate control depends on the rate value of 2662 * RX descriptor because I don't know how to we can control TX rate 2663 * in more smart way. Please fix me you find a thing. 2664 */ 2665 data->buf[3] = sc->sc_currate; 2666 if (prior == URTW_PRIORITY_NORMAL) { 2667 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2668 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2669 else if (ic->ic_fixed_rate != -1) 2670 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2671 } 2672 2673 if (sc->sc_hwrev & URTW_HWREV_8187) { 2674 data->buf[8] = 3; /* CW minimum */ 2675 data->buf[8] |= (7 << 4); /* CW maximum */ 2676 data->buf[9] |= 11; /* retry limitation */ 2677 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2678 } else { 2679 data->buf[21] |= 11; /* retry limitation */ 2680 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2681 } 2682 2683 data->ni = ni; 2684 2685 /* mbuf is no longer needed. */ 2686 m_freem(m0); 2687 2688 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2689 USBD_FORCE_SHORT_XFER, URTW_DATA_TIMEOUT, 2690 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2691 error = usbd_transfer(data->xfer); 2692 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2693 printf("%s: could not send frame: %s\n", 2694 device_xname(sc->sc_dev), usbd_errstr(error)); 2695 return EIO; 2696 } 2697 2698 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2699 if (error != 0) 2700 printf("%s: could not control LED (%d)\n", 2701 device_xname(sc->sc_dev), error); 2702 2703 sc->sc_tx_queued[prior]++; 2704 2705 return 0; 2706 } 2707 2708 static usbd_status 2709 urtw_8225_usb_init(struct urtw_softc *sc) 2710 { 2711 uint8_t data; 2712 usbd_status error; 2713 2714 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2715 urtw_write8_m(sc, URTW_GPIO, 0); 2716 error = urtw_read8e(sc, 0x53, &data); 2717 if (error) 2718 goto fail; 2719 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2720 if (error) 2721 goto fail; 2722 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2723 urtw_write8_m(sc, URTW_GPIO, 0x20); 2724 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2725 2726 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2727 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2728 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2729 2730 usbd_delay_ms(sc->sc_udev, 500); 2731 fail: 2732 return error; 2733 } 2734 2735 static usbd_status 2736 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2737 { 2738 usbd_status error = 0; 2739 2740 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2741 fail: 2742 return error; 2743 } 2744 2745 static usbd_status 2746 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2747 { 2748 uint32_t phyw; 2749 usbd_status error; 2750 2751 phyw = ((data << 8) | (addr | 0x80)); 2752 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2753 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2754 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2755 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2756 /* 2757 * Delay removed from 8185 to 8187. 2758 * usbd_delay_ms(sc->sc_udev, 1); 2759 */ 2760 fail: 2761 return error; 2762 } 2763 2764 static usbd_status 2765 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2766 { 2767 data = data & 0xff; 2768 return urtw_8187_write_phy(sc, addr, data); 2769 } 2770 2771 static usbd_status 2772 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2773 { 2774 data = data & 0xff; 2775 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2776 } 2777 2778 static usbd_status 2779 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2780 { 2781 usbd_status error; 2782 2783 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2784 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2785 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2786 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2787 fail: 2788 return error; 2789 } 2790 2791 static usbd_status 2792 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2793 { 2794 int i, idx, set; 2795 uint8_t *cck_pwltable; 2796 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2797 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2798 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2799 usbd_status error; 2800 2801 cck_pwrlvl_max = 11; 2802 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2803 ofdm_pwrlvl_min = 10; 2804 2805 /* CCK power setting */ 2806 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2807 idx = cck_pwrlvl % 6; 2808 set = cck_pwrlvl / 6; 2809 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2810 urtw_8225_txpwr_cck; 2811 2812 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2813 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2814 for (i = 0; i < 8; i++) { 2815 urtw_8187_write_phy_cck(sc, 0x44 + i, 2816 cck_pwltable[idx * 8 + i]); 2817 } 2818 usbd_delay_ms(sc->sc_udev, 1); 2819 2820 /* OFDM power setting */ 2821 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2822 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2823 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2824 2825 idx = ofdm_pwrlvl % 6; 2826 set = ofdm_pwrlvl / 6; 2827 2828 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2829 if (error) 2830 goto fail; 2831 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2832 urtw_8187_write_phy_ofdm(sc, 6, 0); 2833 urtw_8187_write_phy_ofdm(sc, 8, 0); 2834 2835 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2836 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2837 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2838 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2839 usbd_delay_ms(sc->sc_udev, 1); 2840 fail: 2841 return error; 2842 } 2843 2844 static usbd_status 2845 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2846 { 2847 usbd_status error; 2848 2849 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2850 usbd_delay_ms(sc->sc_udev, 1); 2851 fail: 2852 return error; 2853 } 2854 2855 static usbd_status 2856 urtw_8225_rf_init(struct urtw_rf *rf) 2857 { 2858 struct urtw_softc *sc = rf->rf_sc; 2859 unsigned int i; 2860 uint16_t data; 2861 usbd_status error; 2862 2863 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2864 if (error) 2865 goto fail; 2866 2867 error = urtw_8225_usb_init(sc); 2868 if (error) 2869 goto fail; 2870 2871 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2872 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2873 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2874 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2875 2876 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2877 if (error) 2878 goto fail; 2879 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2880 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2881 if (error) 2882 goto fail; 2883 2884 error = urtw_8185_rf_pins_enable(sc); 2885 if (error) 2886 goto fail; 2887 2888 usbd_delay_ms(sc->sc_udev, 500); 2889 2890 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2891 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2892 urtw_8225_rf_part1[i].val); 2893 } 2894 usbd_delay_ms(sc->sc_udev, 50); 2895 urtw_8225_write(sc, 0x2, 0xc4d); 2896 usbd_delay_ms(sc->sc_udev, 200); 2897 urtw_8225_write(sc, 0x2, 0x44d); 2898 usbd_delay_ms(sc->sc_udev, 200); 2899 urtw_8225_write(sc, 0x0, 0x127); 2900 2901 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2902 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2903 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2904 } 2905 2906 urtw_8225_write(sc, 0x0, 0x27); 2907 urtw_8225_write(sc, 0x0, 0x22f); 2908 2909 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2910 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2911 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2912 } 2913 2914 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2915 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2916 urtw_8225_rf_part2[i].val); 2917 usbd_delay_ms(sc->sc_udev, 1); 2918 } 2919 2920 error = urtw_8225_setgain(sc, 4); 2921 if (error) 2922 goto fail; 2923 2924 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2925 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2926 urtw_8225_rf_part3[i].val); 2927 usbd_delay_ms(sc->sc_udev, 1); 2928 } 2929 2930 urtw_write8_m(sc, 0x5b, 0x0d); 2931 2932 error = urtw_8225_set_txpwrlvl(sc, 1); 2933 if (error) 2934 goto fail; 2935 2936 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2937 usbd_delay_ms(sc->sc_udev, 1); 2938 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2939 usbd_delay_ms(sc->sc_udev, 1); 2940 2941 /* TX ant A, 0x0 for B */ 2942 error = urtw_8185_tx_antenna(sc, 0x3); 2943 if (error) 2944 goto fail; 2945 urtw_write32_m(sc, 0x94, 0x3dc00002); 2946 2947 error = urtw_8225_rf_set_chan(rf, 1); 2948 fail: 2949 return error; 2950 } 2951 2952 static usbd_status 2953 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2954 { 2955 struct urtw_softc *sc = rf->rf_sc; 2956 struct ieee80211com *ic = &sc->sc_ic; 2957 struct ieee80211_channel *c = ic->ic_ibss_chan; 2958 usbd_status error; 2959 2960 error = urtw_8225_set_txpwrlvl(sc, chan); 2961 if (error) 2962 goto fail; 2963 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2964 usbd_delay_ms(sc->sc_udev, 10); 2965 2966 urtw_write8_m(sc, URTW_SIFS, 0x22); 2967 2968 if (sc->sc_state == IEEE80211_S_ASSOC && 2969 ic->ic_flags & IEEE80211_F_SHSLOT) 2970 urtw_write8_m(sc, URTW_SLOT, 0x9); 2971 else 2972 urtw_write8_m(sc, URTW_SLOT, 0x14); 2973 2974 if (IEEE80211_IS_CHAN_G(c)) { 2975 urtw_write8_m(sc, URTW_DIFS, 0x14); 2976 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2977 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2978 } else { 2979 urtw_write8_m(sc, URTW_DIFS, 0x24); 2980 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2981 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2982 } 2983 2984 fail: 2985 return error; 2986 } 2987 2988 static usbd_status 2989 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2990 { 2991 struct urtw_softc *sc = rf->rf_sc; 2992 usbd_status error; 2993 2994 if (rf->sens > 6) 2995 return -1; 2996 2997 if (rf->sens > 4) 2998 urtw_8225_write(sc, 0x0c, 0x850); 2999 else 3000 urtw_8225_write(sc, 0x0c, 0x50); 3001 3002 rf->sens = 6 - rf->sens; 3003 error = urtw_8225_setgain(sc, rf->sens); 3004 if (error) 3005 goto fail; 3006 3007 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3008 3009 fail: 3010 return error; 3011 } 3012 3013 static void 3014 urtw_stop(struct ifnet *ifp, int disable) 3015 { 3016 struct urtw_softc *sc = ifp->if_softc; 3017 struct ieee80211com *ic = &sc->sc_ic; 3018 uint8_t data; 3019 usbd_status error; 3020 3021 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3022 3023 sc->sc_txtimer = 0; 3024 ifp->if_timer = 0; 3025 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3026 3027 callout_stop(&sc->scan_to); 3028 callout_stop(&sc->sc_led_ch); 3029 3030 urtw_intr_disable(sc); 3031 urtw_read8_m(sc, URTW_CMD, &data); 3032 data &= ~URTW_CMD_TX_ENABLE; 3033 data &= ~URTW_CMD_RX_ENABLE; 3034 urtw_write8_m(sc, URTW_CMD, data); 3035 3036 if (sc->sc_rxpipe != NULL) 3037 usbd_abort_pipe(sc->sc_rxpipe); 3038 if (sc->sc_txpipe_low != NULL) 3039 usbd_abort_pipe(sc->sc_txpipe_low); 3040 if (sc->sc_txpipe_normal != NULL) 3041 usbd_abort_pipe(sc->sc_txpipe_normal); 3042 3043 fail: 3044 return; 3045 } 3046 3047 static int 3048 urtw_isbmode(uint16_t rate) 3049 { 3050 rate = urtw_rtl2rate(rate); 3051 3052 return ((rate <= 22 && rate != 12 && rate != 18) || 3053 rate == 44) ? 1 : 0; 3054 } 3055 3056 static void 3057 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3058 { 3059 struct urtw_rx_data *data = priv; 3060 struct urtw_softc *sc = data->sc; 3061 struct ieee80211com *ic = &sc->sc_ic; 3062 struct ifnet *ifp = ic->ic_ifp; 3063 struct ieee80211_frame *wh; 3064 struct ieee80211_node *ni; 3065 struct mbuf *m, *mnew; 3066 uint8_t *desc, quality, rate; 3067 int actlen, flen, len, rssi, s; 3068 3069 if (status != USBD_NORMAL_COMPLETION) { 3070 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3071 return; 3072 3073 if (status == USBD_STALLED) 3074 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3075 if_statinc(ifp, if_ierrors); 3076 goto skip; 3077 } 3078 3079 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3080 if (actlen < URTW_MIN_RXBUFSZ) { 3081 if_statinc(ifp, if_ierrors); 3082 goto skip; 3083 } 3084 3085 if (sc->sc_hwrev & URTW_HWREV_8187) 3086 /* 4 dword and 4 byte CRC */ 3087 len = actlen - (4 * 4); 3088 else 3089 /* 5 dword and 4 byte CRC */ 3090 len = actlen - (4 * 5); 3091 3092 desc = data->buf + len; 3093 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3094 if (flen > actlen) { 3095 if_statinc(ifp, if_ierrors); 3096 goto skip; 3097 } 3098 3099 rate = (desc[2] & 0xf0) >> 4; 3100 if (sc->sc_hwrev & URTW_HWREV_8187) { 3101 quality = desc[4] & 0xff; 3102 rssi = (desc[6] & 0xfe) >> 1; 3103 3104 /* XXX correct? */ 3105 if (!urtw_isbmode(rate)) { 3106 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3107 rssi = ((90 - rssi) * 100) / 65; 3108 } else { 3109 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3110 rssi = ((95 - rssi) * 100) / 65; 3111 } 3112 } else { 3113 quality = desc[12]; 3114 rssi = 14 - desc[14] / 2; 3115 } 3116 3117 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3118 if (mnew == NULL) { 3119 printf("%s: could not allocate rx mbuf\n", 3120 device_xname(sc->sc_dev)); 3121 if_statinc(ifp, if_ierrors); 3122 goto skip; 3123 } 3124 MCLGET(mnew, M_DONTWAIT); 3125 if (!(mnew->m_flags & M_EXT)) { 3126 printf("%s: could not allocate rx mbuf cluster\n", 3127 device_xname(sc->sc_dev)); 3128 m_freem(mnew); 3129 if_statinc(ifp, if_ierrors); 3130 goto skip; 3131 } 3132 3133 m = data->m; 3134 data->m = mnew; 3135 data->buf = mtod(mnew, uint8_t *); 3136 3137 /* finalize mbuf */ 3138 m_set_rcvif(m, ifp); 3139 m->m_pkthdr.len = m->m_len = flen - 4; 3140 3141 s = splnet(); 3142 3143 if (sc->sc_drvbpf != NULL) { 3144 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3145 3146 /* XXX Are variables correct? */ 3147 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3148 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3149 tap->wr_dbm_antsignal = (int8_t)rssi; 3150 3151 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 3152 } 3153 wh = mtod(m, struct ieee80211_frame *); 3154 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3155 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3156 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3157 3158 /* XXX correct? */ 3159 if (!urtw_isbmode(rate)) { 3160 if (quality > 127) 3161 quality = 0; 3162 else if (quality < 27) 3163 quality = 100; 3164 else 3165 quality = 127 - quality; 3166 } else 3167 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3168 3169 /* send the frame to the 802.11 layer */ 3170 ieee80211_input(ic, m, ni, rssi, 0); 3171 3172 /* node is no longer needed */ 3173 ieee80211_free_node(ni); 3174 3175 splx(s); 3176 3177 skip: /* setup a new transfer */ 3178 usbd_setup_xfer(xfer, data, data->buf, MCLBYTES, 3179 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3180 (void)usbd_transfer(xfer); 3181 } 3182 3183 static usbd_status 3184 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3185 { 3186 uint8_t *gainp; 3187 usbd_status error; 3188 3189 /* XXX for A? */ 3190 gainp = urtw_8225v2_gain_bg; 3191 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3192 usbd_delay_ms(sc->sc_udev, 1); 3193 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3194 usbd_delay_ms(sc->sc_udev, 1); 3195 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3196 usbd_delay_ms(sc->sc_udev, 1); 3197 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3198 usbd_delay_ms(sc->sc_udev, 1); 3199 fail: 3200 return error; 3201 } 3202 3203 static usbd_status 3204 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3205 { 3206 int i; 3207 uint8_t *cck_pwrtable; 3208 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3209 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3210 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3211 usbd_status error; 3212 3213 /* CCK power setting */ 3214 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3215 cck_pwrlvl += sc->sc_txpwr_cck_base; 3216 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3217 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3218 urtw_8225v2_txpwr_cck; 3219 3220 for (i = 0; i < 8; i++) { 3221 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3222 } 3223 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3224 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3225 usbd_delay_ms(sc->sc_udev, 1); 3226 3227 /* OFDM power setting */ 3228 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3229 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3230 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3231 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3232 3233 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3234 if (error) 3235 goto fail; 3236 3237 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3238 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3239 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3240 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3241 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3242 3243 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3244 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3245 usbd_delay_ms(sc->sc_udev, 1); 3246 fail: 3247 return error; 3248 } 3249 3250 static usbd_status 3251 urtw_8225v2_rf_init(struct urtw_rf *rf) 3252 { 3253 struct urtw_softc *sc = rf->rf_sc; 3254 int i; 3255 uint16_t data; 3256 uint32_t data32; 3257 usbd_status error; 3258 3259 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3260 if (error) 3261 goto fail; 3262 3263 error = urtw_8225_usb_init(sc); 3264 if (error) 3265 goto fail; 3266 3267 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3268 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3269 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3270 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3271 3272 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3273 if (error) 3274 goto fail; 3275 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3276 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3277 if (error) 3278 goto fail; 3279 3280 error = urtw_8185_rf_pins_enable(sc); 3281 if (error) 3282 goto fail; 3283 3284 usbd_delay_ms(sc->sc_udev, 1000); 3285 3286 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3287 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3288 urtw_8225v2_rf_part1[i].val); 3289 usbd_delay_ms(sc->sc_udev, 1); 3290 } 3291 usbd_delay_ms(sc->sc_udev, 50); 3292 3293 urtw_8225_write(sc, 0x0, 0x1b7); 3294 3295 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3296 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3297 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3298 } 3299 3300 urtw_8225_write(sc, 0x3, 0x2); 3301 urtw_8225_write(sc, 0x5, 0x4); 3302 urtw_8225_write(sc, 0x0, 0xb7); 3303 urtw_8225_write(sc, 0x2, 0xc4d); 3304 usbd_delay_ms(sc->sc_udev, 100); 3305 urtw_8225_write(sc, 0x2, 0x44d); 3306 usbd_delay_ms(sc->sc_udev, 100); 3307 3308 error = urtw_8225_read(sc, 0x6, &data32); 3309 if (error != 0) 3310 goto fail; 3311 if (data32 != 0xe6) 3312 printf("%s: expect 0xe6!! (%#x)\n", device_xname(sc->sc_dev), 3313 data32); 3314 if (!(data32 & 0x80)) { 3315 urtw_8225_write(sc, 0x02, 0x0c4d); 3316 usbd_delay_ms(sc->sc_udev, 200); 3317 urtw_8225_write(sc, 0x02, 0x044d); 3318 usbd_delay_ms(sc->sc_udev, 100); 3319 error = urtw_8225_read(sc, 0x6, &data32); 3320 if (error != 0) 3321 goto fail; 3322 if (!(data32 & 0x80)) 3323 printf("%s: RF calibration failed\n", 3324 device_xname(sc->sc_dev)); 3325 } 3326 usbd_delay_ms(sc->sc_udev, 100); 3327 3328 urtw_8225_write(sc, 0x0, 0x2bf); 3329 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3330 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3331 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3332 } 3333 3334 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3335 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3336 urtw_8225v2_rf_part2[i].val); 3337 } 3338 3339 error = urtw_8225v2_setgain(sc, 4); 3340 if (error) 3341 goto fail; 3342 3343 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3344 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3345 urtw_8225v2_rf_part3[i].val); 3346 } 3347 3348 urtw_write8_m(sc, 0x5b, 0x0d); 3349 3350 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3351 if (error) 3352 goto fail; 3353 3354 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3355 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3356 3357 /* TX ant A, 0x0 for B */ 3358 error = urtw_8185_tx_antenna(sc, 0x3); 3359 if (error) 3360 goto fail; 3361 urtw_write32_m(sc, 0x94, 0x3dc00002); 3362 3363 error = urtw_8225_rf_set_chan(rf, 1); 3364 fail: 3365 return error; 3366 } 3367 3368 static usbd_status 3369 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3370 { 3371 struct urtw_softc *sc = rf->rf_sc; 3372 struct ieee80211com *ic = &sc->sc_ic; 3373 struct ieee80211_channel *c = ic->ic_ibss_chan; 3374 usbd_status error; 3375 3376 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3377 if (error) 3378 goto fail; 3379 3380 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3381 usbd_delay_ms(sc->sc_udev, 10); 3382 3383 urtw_write8_m(sc, URTW_SIFS, 0x22); 3384 3385 if(sc->sc_state == IEEE80211_S_ASSOC && 3386 ic->ic_flags & IEEE80211_F_SHSLOT) 3387 urtw_write8_m(sc, URTW_SLOT, 0x9); 3388 else 3389 urtw_write8_m(sc, URTW_SLOT, 0x14); 3390 3391 if (IEEE80211_IS_CHAN_G(c)) { 3392 urtw_write8_m(sc, URTW_DIFS, 0x14); 3393 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3394 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3395 } else { 3396 urtw_write8_m(sc, URTW_DIFS, 0x24); 3397 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3398 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3399 } 3400 3401 fail: 3402 return error; 3403 } 3404 3405 static void 3406 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3407 { 3408 struct urtw_rf *rf = &sc->sc_rf; 3409 struct ieee80211com *ic = &sc->sc_ic; 3410 usbd_status error = 0; 3411 uint32_t data; 3412 u_int chan; 3413 3414 chan = ieee80211_chan2ieee(ic, c); 3415 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3416 return; 3417 /* 3418 * During changing the channel we need to temporary disable 3419 * TX. 3420 */ 3421 urtw_read32_m(sc, URTW_TX_CONF, &data); 3422 data &= ~URTW_TX_LOOPBACK_MASK; 3423 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3424 error = rf->set_chan(rf, chan); 3425 if (error != 0) { 3426 printf("%s could not change the channel\n", 3427 device_xname(sc->sc_dev)); 3428 return; 3429 } 3430 usbd_delay_ms(sc->sc_udev, 10); 3431 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3432 3433 fail: return; 3434 3435 } 3436 3437 static void 3438 urtw_next_scan(void *arg) 3439 { 3440 struct urtw_softc *sc = arg; 3441 struct ieee80211com *ic = &sc->sc_ic; 3442 int s; 3443 3444 if (sc->sc_dying) 3445 return; 3446 3447 s = splnet(); 3448 if (ic->ic_state == IEEE80211_S_SCAN) 3449 ieee80211_next_scan(ic); 3450 splx(s); 3451 } 3452 3453 static void 3454 urtw_task(void *arg) 3455 { 3456 struct urtw_softc *sc = arg; 3457 struct ieee80211com *ic = &sc->sc_ic; 3458 struct ieee80211_node *ni; 3459 enum ieee80211_state ostate; 3460 usbd_status error = 0; 3461 3462 if (sc->sc_dying) 3463 return; 3464 3465 ostate = ic->ic_state; 3466 3467 switch (sc->sc_state) { 3468 case IEEE80211_S_INIT: 3469 if (ostate == IEEE80211_S_RUN) { 3470 /* turn link LED off */ 3471 (void)urtw_led_off(sc, URTW_LED_GPIO); 3472 } 3473 break; 3474 3475 case IEEE80211_S_SCAN: 3476 urtw_set_chan(sc, ic->ic_curchan); 3477 if (!sc->sc_dying) 3478 callout_schedule(&sc->scan_to, mstohz(200)); 3479 break; 3480 3481 case IEEE80211_S_AUTH: 3482 case IEEE80211_S_ASSOC: 3483 urtw_set_chan(sc, ic->ic_curchan); 3484 break; 3485 3486 case IEEE80211_S_RUN: 3487 ni = ic->ic_bss; 3488 3489 urtw_set_chan(sc, ic->ic_curchan); 3490 3491 /* setting bssid. */ 3492 error = urtw_set_bssid(sc, ni->ni_bssid); 3493 if (error != 0) 3494 goto fail; 3495 urtw_update_msr(sc); 3496 /* XXX maybe the below would be incorrect. */ 3497 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3498 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3499 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3500 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3501 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3502 if (error != 0) 3503 printf("%s: could not control LED (%d)\n", 3504 device_xname(sc->sc_dev), error); 3505 break; 3506 } 3507 3508 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3509 3510 fail: 3511 if (error != 0) { 3512 DPRINTF(("%s: error duing processing RUN state.", 3513 device_xname(sc->sc_dev))); 3514 } 3515 } 3516 3517 static usbd_status 3518 urtw_8187b_update_wmm(struct urtw_softc *sc) 3519 { 3520 struct ieee80211com *ic = &sc->sc_ic; 3521 struct ieee80211_channel *c = ic->ic_ibss_chan; 3522 uint32_t data; 3523 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3524 usbd_status error; 3525 3526 sifs = 0xa; 3527 if (IEEE80211_IS_CHAN_G(c)) 3528 slot = 0x9; 3529 else 3530 slot = 0x14; 3531 3532 aifs = (2 * slot) + sifs; 3533 ecwmin = 3; 3534 ecwmax = 7; 3535 3536 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3537 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3538 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3539 3540 urtw_write32_m(sc, URTW_AC_VO, data); 3541 urtw_write32_m(sc, URTW_AC_VI, data); 3542 urtw_write32_m(sc, URTW_AC_BE, data); 3543 urtw_write32_m(sc, URTW_AC_BK, data); 3544 3545 fail: 3546 return error; 3547 } 3548 3549 static usbd_status 3550 urtw_8187b_reset(struct urtw_softc *sc) 3551 { 3552 uint8_t data; 3553 usbd_status error; 3554 3555 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3556 if (error) 3557 goto fail; 3558 3559 urtw_read8_m(sc, URTW_CONFIG3, &data); 3560 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3561 URTW_CONFIG3_GNT_SELECT); 3562 3563 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3564 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3565 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3566 3567 urtw_write8_m(sc, 0x61, 0x10); 3568 urtw_read8_m(sc, 0x62, &data); 3569 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3570 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3571 3572 urtw_read8_m(sc, URTW_CONFIG3, &data); 3573 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3574 3575 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3576 if (error) 3577 goto fail; 3578 3579 urtw_read8_m(sc, URTW_CMD, &data); 3580 data = (data & 2) | URTW_CMD_RST; 3581 urtw_write8_m(sc, URTW_CMD, data); 3582 usbd_delay_ms(sc->sc_udev, 100); 3583 3584 urtw_read8_m(sc, URTW_CMD, &data); 3585 if (data & URTW_CMD_RST) { 3586 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3587 goto fail; 3588 } 3589 3590 fail: 3591 return error; 3592 } 3593 3594 static int 3595 urtw_8187b_init(struct ifnet *ifp) 3596 { 3597 struct urtw_softc *sc = ifp->if_softc; 3598 struct urtw_rf *rf = &sc->sc_rf; 3599 struct ieee80211com *ic = &sc->sc_ic; 3600 uint8_t data; 3601 usbd_status error; 3602 3603 urtw_stop(ifp, 0); 3604 3605 error = urtw_8187b_update_wmm(sc); 3606 if (error != 0) 3607 goto fail; 3608 error = urtw_8187b_reset(sc); 3609 if (error) 3610 goto fail; 3611 3612 /* Applying MAC address again. */ 3613 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3614 if (error) 3615 goto fail; 3616 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3617 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3618 if (error) 3619 goto fail; 3620 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3621 if (error) 3622 goto fail; 3623 3624 error = urtw_update_msr(sc); 3625 if (error) 3626 goto fail; 3627 3628 error = rf->init(rf); 3629 if (error != 0) 3630 goto fail; 3631 3632 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3633 URTW_CMD_RX_ENABLE); 3634 error = urtw_intr_enable(sc); 3635 if (error != 0) 3636 goto fail; 3637 3638 error = urtw_write8e(sc, 0x41, 0xf4); 3639 if (error != 0) 3640 goto fail; 3641 error = urtw_write8e(sc, 0x40, 0x00); 3642 if (error != 0) 3643 goto fail; 3644 error = urtw_write8e(sc, 0x42, 0x00); 3645 if (error != 0) 3646 goto fail; 3647 error = urtw_write8e(sc, 0x42, 0x01); 3648 if (error != 0) 3649 goto fail; 3650 error = urtw_write8e(sc, 0x40, 0x0f); 3651 if (error != 0) 3652 goto fail; 3653 error = urtw_write8e(sc, 0x42, 0x00); 3654 if (error != 0) 3655 goto fail; 3656 error = urtw_write8e(sc, 0x42, 0x01); 3657 if (error != 0) 3658 goto fail; 3659 3660 urtw_read8_m(sc, 0xdb, &data); 3661 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3662 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3663 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3664 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3665 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3666 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3667 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3668 urtw_write8_m(sc, 0x61, 0); 3669 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3670 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3671 urtw_write8_m(sc, 0xda, 0x10); 3672 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3673 3674 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3675 3676 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3677 3678 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3679 3680 /* Reset softc variables. */ 3681 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 3682 sc->sc_txidx[j] = sc->sc_tx_queued[j] = 0; 3683 } 3684 sc->sc_txtimer = 0; 3685 3686 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3687 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3688 if (error != 0) { 3689 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3690 ", err=%s\n", usbd_errstr(error)); 3691 3692 goto fail; 3693 } 3694 /* Get the first interface handle. */ 3695 error = usbd_device2interface_handle(sc->sc_udev, 3696 URTW_IFACE_INDEX, &sc->sc_iface); 3697 if (error != 0) { 3698 printf("%s: could not get interface handle\n", 3699 device_xname(sc->sc_dev)); 3700 goto fail; 3701 } 3702 error = urtw_open_pipes(sc); 3703 if (error != 0) 3704 goto fail; 3705 error = urtw_alloc_rx_data_list(sc); 3706 if (error != 0) 3707 goto fail; 3708 error = urtw_alloc_tx_data_list(sc); 3709 if (error != 0) 3710 goto fail; 3711 sc->sc_flags |= URTW_INIT_ONCE; 3712 } 3713 3714 error = urtw_rx_enable(sc); 3715 if (error != 0) 3716 goto fail; 3717 error = urtw_tx_enable(sc); 3718 if (error != 0) 3719 goto fail; 3720 3721 ifp->if_flags &= ~IFF_OACTIVE; 3722 ifp->if_flags |= IFF_RUNNING; 3723 3724 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3725 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3726 else 3727 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3728 3729 fail: 3730 return error; 3731 } 3732 3733 static usbd_status 3734 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3735 { 3736 int i; 3737 usbd_status error; 3738 3739 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3740 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3741 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3742 } 3743 3744 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3745 urtw_write16_m(sc, URTW_INT_MIG, 0); 3746 3747 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3748 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3749 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3750 3751 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3752 3753 fail: 3754 return error; 3755 } 3756 3757 static usbd_status 3758 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3759 { 3760 usbd_status error; 3761 3762 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3763 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3764 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3765 usbd_delay_ms(sc->sc_udev, 100); 3766 3767 fail: 3768 return error; 3769 } 3770 3771 static usbd_status 3772 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3773 { 3774 struct ieee80211com *ic = &sc->sc_ic; 3775 struct ieee80211_channel *c = ic->ic_ibss_chan; 3776 uint8_t aifs, difs, eifs, sifs, slot; 3777 usbd_status error; 3778 3779 urtw_write8_m(sc, URTW_SIFS, 0x22); 3780 3781 sifs = 0xa; 3782 if (IEEE80211_IS_CHAN_G(c)) { 3783 slot = 0x9; 3784 difs = 0x1c; 3785 eifs = 0x5b; 3786 } else { 3787 slot = 0x14; 3788 difs = 0x32; 3789 eifs = 0x5b; 3790 } 3791 aifs = (2 * slot) + sifs; 3792 3793 urtw_write8_m(sc, URTW_SLOT, slot); 3794 3795 urtw_write8_m(sc, URTW_AC_VO, aifs); 3796 urtw_write8_m(sc, URTW_AC_VI, aifs); 3797 urtw_write8_m(sc, URTW_AC_BE, aifs); 3798 urtw_write8_m(sc, URTW_AC_BK, aifs); 3799 3800 urtw_write8_m(sc, URTW_DIFS, difs); 3801 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3802 3803 fail: 3804 return error; 3805 } 3806 3807 static usbd_status 3808 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3809 { 3810 struct urtw_softc *sc = rf->rf_sc; 3811 unsigned int i; 3812 uint8_t data; 3813 usbd_status error; 3814 3815 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3816 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3817 urtw_read8_m(sc, URTW_CW_CONF, &data); 3818 urtw_write8_m(sc, URTW_CW_CONF, data | 3819 URTW_CW_CONF_PERPACKET_RETRY); 3820 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3821 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3822 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3823 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3824 3825 /* Auto rate fallback control. */ 3826 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3827 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3828 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3829 URTW_RATE_FALLBACK_ENABLE); 3830 3831 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3832 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3833 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3834 3835 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3836 if (error) 3837 goto fail; 3838 urtw_read8_m(sc, URTW_CONFIG1, &data); 3839 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3840 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3841 if (error) 3842 goto fail; 3843 3844 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3845 urtw_8225v2_b_config_mac(sc); 3846 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3847 3848 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3849 if (error) 3850 goto fail; 3851 urtw_read8_m(sc, URTW_CONFIG3, &data); 3852 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3853 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3854 if (error) 3855 goto fail; 3856 3857 urtw_8225v2_b_init_rfe(sc); 3858 3859 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3860 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3861 urtw_8225v2_b_rf[i].val); 3862 } 3863 3864 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3865 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3866 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3867 } 3868 3869 urtw_8225_write(sc, 0x03, 0x080); 3870 urtw_8225_write(sc, 0x05, 0x004); 3871 urtw_8225_write(sc, 0x00, 0x0b7); 3872 urtw_8225_write(sc, 0x02, 0xc4d); 3873 urtw_8225_write(sc, 0x02, 0x44d); 3874 urtw_8225_write(sc, 0x00, 0x2bf); 3875 3876 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3877 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3878 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3879 3880 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3881 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3882 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3883 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3884 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3885 } 3886 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3887 3888 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3889 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3890 3891 urtw_8225v2_b_update_chan(sc); 3892 3893 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3894 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3895 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3896 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3897 3898 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3899 fail: 3900 return error; 3901 } 3902 3903 static usbd_status 3904 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3905 { 3906 struct urtw_softc *sc = rf->rf_sc; 3907 usbd_status error; 3908 3909 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3910 if (error) 3911 goto fail; 3912 3913 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3914 /* 3915 * Delay removed from 8185 to 8187. 3916 * usbd_delay_ms(sc->sc_udev, 10); 3917 */ 3918 3919 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3920 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3921 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3922 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3923 3924 fail: 3925 return error; 3926 } 3927 3928 static usbd_status 3929 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3930 { 3931 int i; 3932 uint8_t *cck_pwrtable; 3933 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3934 ofdm_pwrlvl_max; 3935 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3936 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3937 usbd_status error; 3938 3939 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3940 cck_pwrlvl_min = 0; 3941 cck_pwrlvl_max = 15; 3942 ofdm_pwrlvl_min = 2; 3943 ofdm_pwrlvl_max = 17; 3944 } else { 3945 cck_pwrlvl_min = 7; 3946 cck_pwrlvl_max = 22; 3947 ofdm_pwrlvl_min = 10; 3948 ofdm_pwrlvl_max = 25; 3949 } 3950 3951 /* CCK power setting */ 3952 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3953 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3954 3955 cck_pwrlvl += sc->sc_txpwr_cck_base; 3956 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3957 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3958 3959 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3960 urtw_8225v2_txpwr_cck; 3961 3962 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3963 if (cck_pwrlvl <= 6) 3964 ; /* do nothing */ 3965 else if (cck_pwrlvl <= 11) 3966 cck_pwrtable += 8; 3967 else 3968 cck_pwrtable += 16; 3969 } else { 3970 if (cck_pwrlvl <= 5) 3971 ; /* do nothing */ 3972 else if (cck_pwrlvl <= 11) 3973 cck_pwrtable += 8; 3974 else if (cck_pwrlvl <= 17) 3975 cck_pwrtable += 16; 3976 else 3977 cck_pwrtable += 24; 3978 } 3979 3980 for (i = 0; i < 8; i++) { 3981 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3982 } 3983 3984 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3985 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3986 /* 3987 * Delay removed from 8185 to 8187. 3988 * usbd_delay_ms(sc->sc_udev, 1); 3989 */ 3990 3991 /* OFDM power setting */ 3992 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3993 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3994 3995 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3996 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3997 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3998 3999 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 4000 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 4001 4002 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 4003 if (ofdm_pwrlvl <= 11) { 4004 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 4005 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 4006 } else { 4007 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4008 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4009 } 4010 } else { 4011 if (ofdm_pwrlvl <= 11) { 4012 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4013 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4014 } else if (ofdm_pwrlvl <= 17) { 4015 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4016 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4017 } else { 4018 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4019 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4020 } 4021 } 4022 4023 /* 4024 * Delay removed from 8185 to 8187. 4025 * usbd_delay_ms(sc->sc_udev, 1); 4026 */ 4027 fail: 4028 return error; 4029 } 4030 4031 static int 4032 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4033 { 4034 int error; 4035 4036 urtw_write32_m(sc, URTW_BSSID, 4037 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4038 urtw_write16_m(sc, URTW_BSSID + 4, 4039 bssid[4] | bssid[5] << 8); 4040 4041 return 0; 4042 4043 fail: 4044 return error; 4045 } 4046 4047 static int 4048 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4049 { 4050 int error; 4051 4052 urtw_write32_m(sc, URTW_MAC0, 4053 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4054 urtw_write16_m(sc, URTW_MAC4, 4055 addr[4] | addr[5] << 8); 4056 4057 return 0; 4058 4059 fail: 4060 return error; 4061 } 4062 4063 MODULE(MODULE_CLASS_DRIVER, if_urtw, NULL); 4064 4065 #ifdef _MODULE 4066 #include "ioconf.c" 4067 #endif 4068 4069 static int 4070 if_urtw_modcmd(modcmd_t cmd, void *aux) 4071 { 4072 int error = 0; 4073 4074 switch (cmd) { 4075 case MODULE_CMD_INIT: 4076 #ifdef _MODULE 4077 error = config_init_component(cfdriver_ioconf_urtw, 4078 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4079 #endif 4080 return error; 4081 case MODULE_CMD_FINI: 4082 #ifdef _MODULE 4083 error = config_fini_component(cfdriver_ioconf_urtw, 4084 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4085 #endif 4086 return error; 4087 default: 4088 return ENOTTY; 4089 } 4090 } 4091
Indexes created Fri Oct 03 02:09:57 GMT 2025