if_urtw.c revision 1.3
1 /* $NetBSD: if_urtw.c,v 1.3 2013/01/05 01:30:16 christos Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.3 2013/01/05 01:30:16 christos Exp $"); 23 24 #ifdef _KERNEL_OPT 25 #include "opt_usb.h" 26 #endif 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/proc.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/callout.h> 37 #include <sys/conf.h> 38 #include <sys/device.h> 39 #include <sys/module.h> 40 #include <sys/bus.h> 41 42 #include <machine/endian.h> 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/if_inarp.h> 55 #include <netinet/ip.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usbdevs.h> 65 66 #include "if_urtwreg.h" 67 68 #ifdef USB_DEBUG 69 #define URTW_DEBUG 70 #endif 71 72 #ifdef URTW_DEBUG 73 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 75 int urtw_debug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 /* 82 * Recognized device vendors/products. 83 */ 84 static const struct urtw_type { 85 struct usb_devno dev; 86 uint8_t rev; 87 } urtw_devs[] = { 88 #define URTW_DEV_RTL8187(v, p) \ 89 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 90 #define URTW_DEV_RTL8187B(v, p) \ 91 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 92 /* Realtek RTL8187 devices. */ 93 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 94 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 95 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 96 URTW_DEV_RTL8187(LOGITEC, RTL8187), 97 URTW_DEV_RTL8187(NETGEAR, WG111V2), 98 URTW_DEV_RTL8187(REALTEK, RTL8187), 99 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 100 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 101 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 102 /* Realtek RTL8187B devices. */ 103 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 104 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 105 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 106 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 107 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 108 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 109 #undef URTW_DEV_RTL8187 110 #undef URTW_DEV_RTL8187B 111 }; 112 #define urtw_lookup(v, p) \ 113 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 114 115 /* 116 * Helper read/write macros. 117 */ 118 #define urtw_read8_m(sc, val, data) do { \ 119 error = urtw_read8_c(sc, val, data, 0); \ 120 if (error != 0) \ 121 goto fail; \ 122 } while (0) 123 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 124 error = urtw_read8_c(sc, val, data, idx); \ 125 if (error != 0) \ 126 goto fail; \ 127 } while (0) 128 #define urtw_write8_m(sc, val, data) do { \ 129 error = urtw_write8_c(sc, val, data, 0); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 134 error = urtw_write8_c(sc, val, data, idx); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_m(sc, val, data) do { \ 139 error = urtw_read16_c(sc, val, data, 0); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 144 error = urtw_read16_c(sc, val, data, idx); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_write16_m(sc, val, data) do { \ 149 error = urtw_write16_c(sc, val, data, 0); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 154 error = urtw_write16_c(sc, val, data, idx); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_read32_m(sc, val, data) do { \ 159 error = urtw_read32_c(sc, val, data, 0); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 164 error = urtw_read32_c(sc, val, data, idx); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_write32_m(sc, val, data) do { \ 169 error = urtw_write32_c(sc, val, data, 0); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 174 error = urtw_write32_c(sc, val, data, idx); \ 175 if (error != 0) \ 176 goto fail; \ 177 } while (0) 178 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 179 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 180 if (error != 0) \ 181 goto fail; \ 182 } while (0) 183 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 184 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 185 if (error != 0) \ 186 goto fail; \ 187 } while (0) 188 #define urtw_8225_write(sc, val, data) do { \ 189 error = urtw_8225_write_c(sc, val, data); \ 190 if (error != 0) \ 191 goto fail; \ 192 } while (0) 193 194 struct urtw_pair { 195 uint32_t reg; 196 uint32_t val; 197 }; 198 199 struct urtw_pair_idx { 200 uint8_t reg; 201 uint8_t val; 202 uint8_t idx; 203 }; 204 205 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 206 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 207 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 208 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 209 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 210 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 211 { 0xff, 0x00, 0 }, 212 213 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 214 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 215 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 216 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 217 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 218 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 219 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 220 { 0xf8, 0x08, 1 }, 221 222 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 223 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 224 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 225 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 226 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 227 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 228 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 229 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 230 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 231 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 232 233 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 234 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 235 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 236 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 237 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 238 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 239 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 240 241 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 242 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 243 }; 244 245 static uint8_t urtw_8225_agc[] = { 246 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 247 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 248 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 249 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 250 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 251 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 252 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 253 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 254 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 255 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 256 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 257 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 258 }; 259 260 static uint32_t urtw_8225_channel[] = { 261 0x0000, /* dummy channel 0 */ 262 0x085c, /* 1 */ 263 0x08dc, /* 2 */ 264 0x095c, /* 3 */ 265 0x09dc, /* 4 */ 266 0x0a5c, /* 5 */ 267 0x0adc, /* 6 */ 268 0x0b5c, /* 7 */ 269 0x0bdc, /* 8 */ 270 0x0c5c, /* 9 */ 271 0x0cdc, /* 10 */ 272 0x0d5c, /* 11 */ 273 0x0ddc, /* 12 */ 274 0x0e5c, /* 13 */ 275 0x0f72, /* 14 */ 276 }; 277 278 static uint8_t urtw_8225_gain[] = { 279 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 280 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 281 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 282 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 283 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 284 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 285 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 286 }; 287 288 static struct urtw_pair urtw_8225_rf_part1[] = { 289 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 290 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 291 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 292 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 293 }; 294 295 static struct urtw_pair urtw_8225_rf_part2[] = { 296 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 297 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 298 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 299 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 300 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 301 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 302 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 303 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 304 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 305 { 0x27, 0x88 } 306 }; 307 308 static struct urtw_pair urtw_8225_rf_part3[] = { 309 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 310 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 311 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 312 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 313 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 314 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 315 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 316 }; 317 318 static uint16_t urtw_8225_rxgain[] = { 319 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 320 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 321 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 322 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 323 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 324 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 325 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 326 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 327 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 328 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 329 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 330 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 331 }; 332 333 static uint8_t urtw_8225_threshold[] = { 334 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 335 }; 336 337 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 338 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 339 }; 340 341 static uint8_t urtw_8225_txpwr_cck[] = { 342 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 343 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 344 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 345 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 346 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 347 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 348 }; 349 350 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 351 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 352 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 353 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 354 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 355 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 356 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 357 }; 358 359 static uint8_t urtw_8225_txpwr_ofdm[] = { 360 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 361 }; 362 363 static uint8_t urtw_8225v2_agc[] = { 364 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 365 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 366 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 367 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 368 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 369 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 370 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 371 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 372 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 373 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 374 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 375 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 376 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 377 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 378 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 379 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 380 }; 381 382 static uint8_t urtw_8225v2_ofdm[] = { 383 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 384 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 385 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 386 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 387 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 388 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 389 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 390 0x6d, 0x3c, 0xfb, 0x07 391 }; 392 393 static uint8_t urtw_8225v2_gain_bg[] = { 394 0x23, 0x15, 0xa5, /* -82-1dbm */ 395 0x23, 0x15, 0xb5, /* -82-2dbm */ 396 0x23, 0x15, 0xc5, /* -82-3dbm */ 397 0x33, 0x15, 0xc5, /* -78dbm */ 398 0x43, 0x15, 0xc5, /* -74dbm */ 399 0x53, 0x15, 0xc5, /* -70dbm */ 400 0x63, 0x15, 0xc5, /* -66dbm */ 401 }; 402 403 static struct urtw_pair urtw_8225v2_rf_part1[] = { 404 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 405 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 406 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 407 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 408 }; 409 410 static struct urtw_pair urtw_8225v2_rf_part2[] = { 411 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 412 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 413 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 414 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 415 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 416 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 417 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 418 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 419 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 420 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 421 }; 422 423 static struct urtw_pair urtw_8225v2_rf_part3[] = { 424 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 425 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 426 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 427 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 428 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 429 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 430 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 431 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 432 }; 433 434 static uint16_t urtw_8225v2_rxgain[] = { 435 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 436 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 437 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 438 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 439 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 440 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 441 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 442 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 443 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 444 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 445 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 446 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 447 }; 448 449 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 450 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 451 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 452 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 453 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 454 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 455 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 456 }; 457 458 static uint8_t urtw_8225v2_txpwr_cck[] = { 459 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 460 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 461 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 462 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 463 }; 464 465 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 466 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 467 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 468 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 470 }; 471 472 static struct urtw_pair urtw_8225v2_b_rf[] = { 473 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 474 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 475 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 476 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 477 { 0x00, 0x01b7 } 478 }; 479 480 static struct urtw_pair urtw_ratetable[] = { 481 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 482 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 483 { 96, 10 }, { 108, 11 } 484 }; 485 486 int urtw_init(struct ifnet *); 487 void urtw_stop(struct ifnet *, int); 488 int urtw_ioctl(struct ifnet *, u_long, void *); 489 void urtw_start(struct ifnet *); 490 int urtw_alloc_rx_data_list(struct urtw_softc *); 491 void urtw_free_rx_data_list(struct urtw_softc *); 492 int urtw_alloc_tx_data_list(struct urtw_softc *); 493 void urtw_free_tx_data_list(struct urtw_softc *); 494 void urtw_rxeof(usbd_xfer_handle, usbd_private_handle, 495 usbd_status); 496 int urtw_tx_start(struct urtw_softc *, 497 struct ieee80211_node *, struct mbuf *, int); 498 void urtw_txeof_low(usbd_xfer_handle, usbd_private_handle, 499 usbd_status); 500 void urtw_txeof_normal(usbd_xfer_handle, usbd_private_handle, 501 usbd_status); 502 void urtw_next_scan(void *); 503 void urtw_task(void *); 504 void urtw_ledusbtask(void *); 505 void urtw_ledtask(void *); 506 int urtw_media_change(struct ifnet *); 507 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 508 void urtw_watchdog(struct ifnet *); 509 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 510 int urtw_isbmode(uint16_t); 511 uint16_t urtw_rate2rtl(int rate); 512 uint16_t urtw_rtl2rate(int); 513 usbd_status urtw_set_rate(struct urtw_softc *); 514 usbd_status urtw_update_msr(struct urtw_softc *); 515 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 516 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 517 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 518 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 519 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 520 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 521 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 522 usbd_status urtw_eprom_ck(struct urtw_softc *); 523 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 524 int); 525 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 526 uint32_t *); 527 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 528 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 529 usbd_status urtw_get_macaddr(struct urtw_softc *); 530 usbd_status urtw_get_txpwr(struct urtw_softc *); 531 usbd_status urtw_get_rfchip(struct urtw_softc *); 532 usbd_status urtw_led_init(struct urtw_softc *); 533 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 534 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 535 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 536 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 537 uint32_t); 538 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 539 uint32_t); 540 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 541 usbd_status urtw_8225_usb_init(struct urtw_softc *); 542 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 543 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 544 uint16_t); 545 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 546 usbd_status urtw_8225_rf_init(struct urtw_rf *); 547 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 548 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 549 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 550 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 551 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 552 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 553 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 554 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 555 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 556 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 557 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 558 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 559 usbd_status urtw_open_pipes(struct urtw_softc *); 560 usbd_status urtw_close_pipes(struct urtw_softc *); 561 usbd_status urtw_intr_enable(struct urtw_softc *); 562 usbd_status urtw_intr_disable(struct urtw_softc *); 563 usbd_status urtw_reset(struct urtw_softc *); 564 usbd_status urtw_led_on(struct urtw_softc *, int); 565 usbd_status urtw_led_ctl(struct urtw_softc *, int); 566 usbd_status urtw_led_blink(struct urtw_softc *); 567 usbd_status urtw_led_mode0(struct urtw_softc *, int); 568 usbd_status urtw_led_mode1(struct urtw_softc *, int); 569 usbd_status urtw_led_mode2(struct urtw_softc *, int); 570 usbd_status urtw_led_mode3(struct urtw_softc *, int); 571 usbd_status urtw_rx_setconf(struct urtw_softc *); 572 usbd_status urtw_rx_enable(struct urtw_softc *); 573 usbd_status urtw_tx_enable(struct urtw_softc *); 574 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 575 usbd_status urtw_8187b_reset(struct urtw_softc *); 576 int urtw_8187b_init(struct ifnet *); 577 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 578 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 579 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 580 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 581 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 582 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 583 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 584 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 585 586 int urtw_match(device_t, cfdata_t, void *); 587 void urtw_attach(device_t, device_t, void *); 588 int urtw_detach(device_t, int); 589 int urtw_activate(device_t, enum devact); 590 591 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 592 urtw_match, 593 urtw_attach, 594 urtw_detach, 595 urtw_activate 596 ); 597 598 int 599 urtw_match(device_t parent, cfdata_t match, void *aux) 600 { 601 struct usb_attach_arg *uaa = aux; 602 603 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 604 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 605 } 606 607 void 608 urtw_attach(device_t parent, device_t self, void *aux) 609 { 610 struct urtw_softc *sc = device_private(self); 611 struct usb_attach_arg *uaa = aux; 612 struct ieee80211com *ic = &sc->sc_ic; 613 struct ifnet *ifp = &sc->sc_if; 614 usbd_status error; 615 uint8_t data8; 616 uint32_t data; 617 int i; 618 619 sc->sc_dev = self; 620 sc->sc_udev = uaa->device; 621 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 622 623 printf(": "); 624 625 if (sc->sc_hwrev & URTW_HWREV_8187) { 626 urtw_read32_m(sc, URTW_TX_CONF, &data); 627 data &= URTW_TX_HWREV_MASK; 628 switch (data) { 629 case URTW_TX_HWREV_8187_D: 630 sc->sc_hwrev |= URTW_HWREV_8187_D; 631 printf("RTL8187 rev D"); 632 break; 633 case URTW_TX_HWREV_8187B_D: 634 /* 635 * Detect Realtek RTL8187B devices that use 636 * USB IDs of RTL8187. 637 */ 638 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 639 printf("RTL8187B rev B (early)"); 640 break; 641 default: 642 sc->sc_hwrev |= URTW_HWREV_8187_B; 643 printf("RTL8187 rev 0x%02x", data >> 25); 644 break; 645 } 646 } else { 647 /* RTL8187B hwrev register. */ 648 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 649 switch (data8) { 650 case URTW_8187B_HWREV_8187B_B: 651 sc->sc_hwrev |= URTW_HWREV_8187B_B; 652 printf("RTL8187B rev B"); 653 break; 654 case URTW_8187B_HWREV_8187B_D: 655 sc->sc_hwrev |= URTW_HWREV_8187B_D; 656 printf("RTL8187B rev D"); 657 break; 658 case URTW_8187B_HWREV_8187B_E: 659 sc->sc_hwrev |= URTW_HWREV_8187B_E; 660 printf("RTL8187B rev E"); 661 break; 662 default: 663 sc->sc_hwrev |= URTW_HWREV_8187B_B; 664 printf("RTL8187B rev 0x%02x", data8); 665 break; 666 } 667 } 668 669 urtw_read32_m(sc, URTW_RX, &data); 670 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 671 URTW_EEPROM_93C46; 672 673 error = urtw_get_rfchip(sc); 674 if (error != 0) 675 goto fail; 676 error = urtw_get_macaddr(sc); 677 if (error != 0) 678 goto fail; 679 error = urtw_get_txpwr(sc); 680 if (error != 0) 681 goto fail; 682 error = urtw_led_init(sc); /* XXX incompleted */ 683 if (error != 0) 684 goto fail; 685 686 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 687 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 688 sc->sc_currate = 3; 689 /* XXX for what? */ 690 sc->sc_preamble_mode = 2; 691 692 usb_init_task(&sc->sc_task, urtw_task, sc); 693 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc); 694 callout_init(&sc->scan_to, 0); 695 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 696 callout_init(&sc->sc_led_ch, 0); 697 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 698 699 ic->ic_ifp = ifp; 700 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 701 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 702 ic->ic_state = IEEE80211_S_INIT; 703 704 /* set device capabilities */ 705 ic->ic_caps = 706 IEEE80211_C_MONITOR | /* monitor mode supported */ 707 IEEE80211_C_TXPMGT | /* tx power management */ 708 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 709 IEEE80211_C_SHSLOT | /* short slot time supported */ 710 IEEE80211_C_WEP | /* s/w WEP */ 711 IEEE80211_C_WPA; /* WPA/RSN */ 712 713 /* set supported .11b and .11g rates */ 714 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 715 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 716 717 /* set supported .11b and .11g channels (1 through 14) */ 718 for (i = 1; i <= 14; i++) { 719 ic->ic_channels[i].ic_freq = 720 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 721 ic->ic_channels[i].ic_flags = 722 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 723 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 724 } 725 726 ifp->if_softc = sc; 727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 728 if (sc->sc_hwrev & URTW_HWREV_8187) { 729 ifp->if_init = urtw_init; 730 } else { 731 ifp->if_init = urtw_8187b_init; 732 } 733 ifp->if_ioctl = urtw_ioctl; 734 ifp->if_start = urtw_start; 735 ifp->if_watchdog = urtw_watchdog; 736 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 737 IFQ_SET_READY(&ifp->if_snd); 738 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 739 740 if_attach(ifp); 741 ieee80211_ifattach(ic); 742 743 /* override state transition machine */ 744 sc->sc_newstate = ic->ic_newstate; 745 ic->ic_newstate = urtw_newstate; 746 ieee80211_media_init(ic, urtw_media_change, ieee80211_media_status); 747 748 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 749 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 750 &sc->sc_drvbpf); 751 752 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 753 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 754 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 755 756 sc->sc_txtap_len = sizeof sc->sc_txtapu; 757 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 758 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 759 760 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 761 762 ieee80211_announce(ic); 763 764 return; 765 fail: 766 printf(": %s failed!\n", __func__); 767 sc->sc_dying = true; 768 } 769 770 int 771 urtw_detach(device_t self, int flags) 772 { 773 struct urtw_softc *sc = device_private(self); 774 struct ifnet *ifp = &sc->sc_if; 775 int s; 776 777 s = splusb(); 778 779 sc->sc_dying = true; 780 781 callout_destroy(&sc->scan_to); 782 callout_destroy(&sc->sc_led_ch); 783 784 usb_rem_task(sc->sc_udev, &sc->sc_task); 785 usb_rem_task(sc->sc_udev, &sc->sc_ledtask); 786 787 if (ifp->if_softc != NULL) { 788 bpf_detach(ifp); 789 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 790 if_detach(ifp); 791 } 792 793 /* abort and free xfers */ 794 urtw_free_tx_data_list(sc); 795 urtw_free_rx_data_list(sc); 796 urtw_close_pipes(sc); 797 798 splx(s); 799 800 return (0); 801 } 802 803 int 804 urtw_activate(device_t self, enum devact act) 805 { 806 struct urtw_softc *sc = device_private(self); 807 808 switch (act) { 809 case DVACT_DEACTIVATE: 810 sc->sc_dying = true; 811 break; 812 } 813 814 return (0); 815 } 816 817 usbd_status 818 urtw_close_pipes(struct urtw_softc *sc) 819 { 820 usbd_status error = 0; 821 822 if (sc->sc_rxpipe != NULL) { 823 error = usbd_close_pipe(sc->sc_rxpipe); 824 if (error != 0) 825 goto fail; 826 sc->sc_rxpipe = NULL; 827 } 828 if (sc->sc_txpipe_low != NULL) { 829 error = usbd_close_pipe(sc->sc_txpipe_low); 830 if (error != 0) 831 goto fail; 832 sc->sc_txpipe_low = NULL; 833 } 834 if (sc->sc_txpipe_normal != NULL) { 835 error = usbd_close_pipe(sc->sc_txpipe_normal); 836 if (error != 0) 837 goto fail; 838 sc->sc_txpipe_normal = NULL; 839 } 840 fail: 841 return (error); 842 } 843 844 usbd_status 845 urtw_open_pipes(struct urtw_softc *sc) 846 { 847 usbd_status error; 848 849 /* 850 * NB: there is no way to distinguish each pipes so we need to hardcode 851 * pipe numbers 852 */ 853 854 /* tx pipe - low priority packets */ 855 if (sc->sc_hwrev & URTW_HWREV_8187) 856 error = usbd_open_pipe(sc->sc_iface, 0x2, 857 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 858 else 859 error = usbd_open_pipe(sc->sc_iface, 0x6, 860 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 861 if (error != 0) { 862 printf("%s: could not open Tx low pipe: %s\n", 863 device_xname(sc->sc_dev), usbd_errstr(error)); 864 goto fail; 865 } 866 /* tx pipe - normal priority packets */ 867 if (sc->sc_hwrev & URTW_HWREV_8187) 868 error = usbd_open_pipe(sc->sc_iface, 0x3, 869 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 870 else 871 error = usbd_open_pipe(sc->sc_iface, 0x7, 872 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 873 if (error != 0) { 874 printf("%s: could not open Tx normal pipe: %s\n", 875 device_xname(sc->sc_dev), usbd_errstr(error)); 876 goto fail; 877 } 878 /* rx pipe */ 879 if (sc->sc_hwrev & URTW_HWREV_8187) 880 error = usbd_open_pipe(sc->sc_iface, 0x81, 881 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 882 else 883 error = usbd_open_pipe(sc->sc_iface, 0x83, 884 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 885 if (error != 0) { 886 printf("%s: could not open Rx pipe: %s\n", 887 device_xname(sc->sc_dev), usbd_errstr(error)); 888 goto fail; 889 } 890 891 return (0); 892 fail: 893 (void)urtw_close_pipes(sc); 894 return (error); 895 } 896 897 int 898 urtw_alloc_rx_data_list(struct urtw_softc *sc) 899 { 900 int i, error; 901 902 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 903 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 904 905 data->sc = sc; 906 907 data->xfer = usbd_alloc_xfer(sc->sc_udev); 908 if (data->xfer == NULL) { 909 printf("%s: could not allocate rx xfer\n", 910 device_xname(sc->sc_dev)); 911 error = ENOMEM; 912 goto fail; 913 } 914 915 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 916 printf("%s: could not allocate rx buffer\n", 917 device_xname(sc->sc_dev)); 918 error = ENOMEM; 919 goto fail; 920 } 921 922 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 923 if (data->m == NULL) { 924 printf("%s: could not allocate rx mbuf\n", 925 device_xname(sc->sc_dev)); 926 error = ENOMEM; 927 goto fail; 928 } 929 MCLGET(data->m, M_DONTWAIT); 930 if (!(data->m->m_flags & M_EXT)) { 931 printf("%s: could not allocate rx mbuf cluster\n", 932 device_xname(sc->sc_dev)); 933 error = ENOMEM; 934 goto fail; 935 } 936 data->buf = mtod(data->m, uint8_t *); 937 } 938 939 return (0); 940 941 fail: 942 urtw_free_rx_data_list(sc); 943 return (error); 944 } 945 946 void 947 urtw_free_rx_data_list(struct urtw_softc *sc) 948 { 949 int i; 950 951 /* Make sure no transfers are pending. */ 952 if (sc->sc_rxpipe != NULL) 953 usbd_abort_pipe(sc->sc_rxpipe); 954 955 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 956 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 957 958 if (data->xfer != NULL) { 959 usbd_free_xfer(data->xfer); 960 data->xfer = NULL; 961 } 962 if (data->m != NULL) { 963 m_freem(data->m); 964 data->m = NULL; 965 } 966 } 967 } 968 969 int 970 urtw_alloc_tx_data_list(struct urtw_softc *sc) 971 { 972 int i, error; 973 974 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 975 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 976 977 data->sc = sc; 978 data->ni = NULL; 979 980 data->xfer = usbd_alloc_xfer(sc->sc_udev); 981 if (data->xfer == NULL) { 982 printf("%s: could not allocate tx xfer\n", 983 device_xname(sc->sc_dev)); 984 error = ENOMEM; 985 goto fail; 986 } 987 988 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 989 if (data->buf == NULL) { 990 printf("%s: could not allocate tx buffer\n", 991 device_xname(sc->sc_dev)); 992 error = ENOMEM; 993 goto fail; 994 } 995 996 if (((unsigned long)data->buf) % 4) 997 printf("%s: warn: unaligned buffer %p\n", 998 device_xname(sc->sc_dev), data->buf); 999 } 1000 1001 return (0); 1002 1003 fail: 1004 urtw_free_tx_data_list(sc); 1005 return (error); 1006 } 1007 1008 void 1009 urtw_free_tx_data_list(struct urtw_softc *sc) 1010 { 1011 int i; 1012 1013 /* Make sure no transfers are pending. */ 1014 if (sc->sc_txpipe_low != NULL) 1015 usbd_abort_pipe(sc->sc_txpipe_low); 1016 if (sc->sc_txpipe_normal != NULL) 1017 usbd_abort_pipe(sc->sc_txpipe_normal); 1018 1019 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1020 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 1021 1022 if (data->xfer != NULL) { 1023 usbd_free_xfer(data->xfer); 1024 data->xfer = NULL; 1025 } 1026 if (data->ni != NULL) { 1027 ieee80211_free_node(data->ni); 1028 data->ni = NULL; 1029 } 1030 } 1031 } 1032 1033 int 1034 urtw_media_change(struct ifnet *ifp) 1035 { 1036 int error; 1037 1038 error = ieee80211_media_change(ifp); 1039 if (error != ENETRESET) 1040 return (error); 1041 1042 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1043 (IFF_UP | IFF_RUNNING)) 1044 ifp->if_init(ifp); 1045 1046 return (0); 1047 } 1048 1049 int 1050 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1051 { 1052 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1053 1054 usb_rem_task(sc->sc_udev, &sc->sc_task); 1055 callout_stop(&sc->scan_to); 1056 1057 /* do it in a process context */ 1058 sc->sc_state = nstate; 1059 sc->sc_arg = arg; 1060 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1061 1062 return (0); 1063 } 1064 1065 usbd_status 1066 urtw_led_init(struct urtw_softc *sc) 1067 { 1068 uint32_t rev; 1069 usbd_status error; 1070 1071 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1072 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1073 if (error != 0) 1074 goto fail; 1075 1076 switch (rev & URTW_EPROM_CID_MASK) { 1077 case URTW_EPROM_CID_ALPHA0: 1078 sc->sc_strategy = URTW_SW_LED_MODE1; 1079 break; 1080 case URTW_EPROM_CID_SERCOMM_PS: 1081 sc->sc_strategy = URTW_SW_LED_MODE3; 1082 break; 1083 case URTW_EPROM_CID_HW_LED: 1084 sc->sc_strategy = URTW_HW_LED; 1085 break; 1086 case URTW_EPROM_CID_RSVD0: 1087 case URTW_EPROM_CID_RSVD1: 1088 default: 1089 sc->sc_strategy = URTW_SW_LED_MODE0; 1090 break; 1091 } 1092 1093 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1094 1095 fail: 1096 return (error); 1097 } 1098 1099 usbd_status 1100 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1101 uint16_t data) 1102 { 1103 usb_device_request_t req; 1104 1105 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1106 req.bRequest = URTW_8187_SETREGS_REQ; 1107 USETW(req.wValue, addr); 1108 USETW(req.wIndex, index); 1109 USETW(req.wLength, sizeof(uint16_t)); 1110 1111 return (usbd_do_request(sc->sc_udev, &req, &data)); 1112 } 1113 1114 usbd_status 1115 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1116 { 1117 int i; 1118 int16_t bit; 1119 uint8_t rlen = 12, wlen = 6; 1120 uint16_t o1, o2, o3, tmp; 1121 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1122 uint32_t mask = 0x80000000, value = 0; 1123 usbd_status error; 1124 1125 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1126 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1127 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1128 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1129 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1130 o1 &= ~0xf; 1131 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1132 DELAY(5); 1133 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1134 DELAY(5); 1135 1136 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1137 bit = ((d2w & mask) != 0) ? 1 : 0; 1138 1139 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1140 DELAY(2); 1141 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1142 URTW_BB_HOST_BANG_CLK); 1143 DELAY(2); 1144 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1145 URTW_BB_HOST_BANG_CLK); 1146 DELAY(2); 1147 mask = mask >> 1; 1148 if (i == 2) 1149 break; 1150 bit = ((d2w & mask) != 0) ? 1 : 0; 1151 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1152 URTW_BB_HOST_BANG_CLK); 1153 DELAY(2); 1154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1155 URTW_BB_HOST_BANG_CLK); 1156 DELAY(2); 1157 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1158 DELAY(1); 1159 } 1160 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1161 URTW_BB_HOST_BANG_CLK); 1162 DELAY(2); 1163 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1164 DELAY(2); 1165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1166 DELAY(2); 1167 1168 mask = 0x800; 1169 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1170 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1171 o1 | URTW_BB_HOST_BANG_RW); 1172 DELAY(2); 1173 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1174 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1175 DELAY(2); 1176 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1177 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1178 DELAY(2); 1179 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1180 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1181 DELAY(2); 1182 1183 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1184 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1185 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1186 o1 | URTW_BB_HOST_BANG_RW); 1187 DELAY(2); 1188 } 1189 1190 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1191 URTW_BB_HOST_BANG_RW); 1192 DELAY(2); 1193 1194 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1195 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1196 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1197 1198 if (data != NULL) 1199 *data = value; 1200 fail: 1201 return (error); 1202 } 1203 1204 usbd_status 1205 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1206 { 1207 uint16_t d80, d82, d84; 1208 usbd_status error; 1209 1210 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1211 d80 &= 0xfff3; 1212 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1213 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1214 d84 &= 0xfff0; 1215 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1216 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1217 DELAY(10); 1218 1219 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1220 DELAY(2); 1221 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1222 DELAY(10); 1223 1224 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1225 if (error != 0) 1226 goto fail; 1227 1228 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1229 DELAY(10); 1230 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1231 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1232 usbd_delay_ms(sc->sc_udev, 2); 1233 fail: 1234 return (error); 1235 } 1236 1237 usbd_status 1238 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1239 { 1240 uint32_t data; 1241 usbd_status error; 1242 1243 *ret = 1; 1244 1245 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1246 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1247 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1248 usbd_delay_ms(sc->sc_udev, 500); 1249 1250 urtw_8225_write(sc, 0x0, 0x1b7); 1251 1252 error = urtw_8225_read(sc, 0x8, &data); 1253 if (error != 0) 1254 goto fail; 1255 if (data != 0x588) 1256 *ret = 0; 1257 else { 1258 error = urtw_8225_read(sc, 0x9, &data); 1259 if (error != 0) 1260 goto fail; 1261 if (data != 0x700) 1262 *ret = 0; 1263 } 1264 1265 urtw_8225_write(sc, 0x0, 0xb7); 1266 fail: 1267 return (error); 1268 } 1269 1270 usbd_status 1271 urtw_get_rfchip(struct urtw_softc *sc) 1272 { 1273 struct urtw_rf *rf = &sc->sc_rf; 1274 int ret; 1275 uint32_t data; 1276 usbd_status error; 1277 1278 rf->rf_sc = sc; 1279 1280 if (sc->sc_hwrev & URTW_HWREV_8187) { 1281 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1282 if (error != 0) 1283 panic("unsupported RF chip"); 1284 /* NOTREACHED */ 1285 switch (data & 0xff) { 1286 case URTW_EPROM_RFCHIPID_RTL8225U: 1287 error = urtw_8225_isv2(sc, &ret); 1288 if (error != 0) 1289 goto fail; 1290 if (ret == 0) { 1291 rf->init = urtw_8225_rf_init; 1292 rf->set_chan = urtw_8225_rf_set_chan; 1293 rf->set_sens = urtw_8225_rf_set_sens; 1294 printf(", RFv1"); 1295 } else { 1296 rf->init = urtw_8225v2_rf_init; 1297 rf->set_chan = urtw_8225v2_rf_set_chan; 1298 rf->set_sens = NULL; 1299 printf(", RFv2"); 1300 } 1301 break; 1302 default: 1303 goto fail; 1304 } 1305 } else { 1306 rf->init = urtw_8225v2_b_rf_init; 1307 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1308 rf->set_sens = NULL; 1309 } 1310 1311 rf->max_sens = URTW_8225_RF_MAX_SENS; 1312 rf->sens = URTW_8225_RF_DEF_SENS; 1313 1314 return (0); 1315 1316 fail: 1317 panic("unsupported RF chip %d", data & 0xff); 1318 /* NOTREACHED */ 1319 } 1320 1321 usbd_status 1322 urtw_get_txpwr(struct urtw_softc *sc) 1323 { 1324 int i, j; 1325 uint32_t data; 1326 usbd_status error; 1327 1328 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1329 if (error != 0) 1330 goto fail; 1331 sc->sc_txpwr_cck_base = data & 0xf; 1332 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1333 1334 for (i = 1, j = 0; i < 6; i += 2, j++) { 1335 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1336 if (error != 0) 1337 goto fail; 1338 sc->sc_txpwr_cck[i] = data & 0xf; 1339 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1340 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1341 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1342 } 1343 for (i = 1, j = 0; i < 4; i += 2, j++) { 1344 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1345 if (error != 0) 1346 goto fail; 1347 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1348 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1349 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1350 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1351 } 1352 if (sc->sc_hwrev & URTW_HWREV_8187) { 1353 for (i = 1, j = 0; i < 4; i += 2, j++) { 1354 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1355 &data); 1356 if (error != 0) 1357 goto fail; 1358 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1359 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1360 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1361 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1362 (data & 0xf000) >> 12; 1363 } 1364 } else { 1365 /* Channel 11. */ 1366 error = urtw_eprom_read32(sc, 0x1b, &data); 1367 if (error != 0) 1368 goto fail; 1369 sc->sc_txpwr_cck[11] = data & 0xf; 1370 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1371 1372 /* Channel 12. */ 1373 error = urtw_eprom_read32(sc, 0xa, &data); 1374 if (error != 0) 1375 goto fail; 1376 sc->sc_txpwr_cck[12] = data & 0xf; 1377 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1378 1379 /* Channel 13, 14. */ 1380 error = urtw_eprom_read32(sc, 0x1c, &data); 1381 if (error != 0) 1382 goto fail; 1383 sc->sc_txpwr_cck[13] = data & 0xf; 1384 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1385 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1386 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1387 } 1388 fail: 1389 return (error); 1390 } 1391 1392 usbd_status 1393 urtw_get_macaddr(struct urtw_softc *sc) 1394 { 1395 struct ieee80211com *ic = &sc->sc_ic; 1396 usbd_status error; 1397 uint32_t data; 1398 1399 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1400 if (error != 0) 1401 goto fail; 1402 ic->ic_myaddr[0] = data & 0xff; 1403 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1404 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1405 if (error != 0) 1406 goto fail; 1407 ic->ic_myaddr[2] = data & 0xff; 1408 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1409 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1410 if (error != 0) 1411 goto fail; 1412 ic->ic_myaddr[4] = data & 0xff; 1413 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1414 fail: 1415 return (error); 1416 } 1417 1418 usbd_status 1419 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1420 { 1421 #define URTW_READCMD_LEN 3 1422 int addrlen, i; 1423 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1424 usbd_status error; 1425 1426 /* NB: make sure the buffer is initialized */ 1427 *data = 0; 1428 1429 /* enable EPROM programming */ 1430 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1431 DELAY(URTW_EPROM_DELAY); 1432 1433 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1434 if (error != 0) 1435 goto fail; 1436 error = urtw_eprom_ck(sc); 1437 if (error != 0) 1438 goto fail; 1439 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1440 if (error != 0) 1441 goto fail; 1442 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1443 addrlen = 8; 1444 addrstr[0] = addr & (1 << 7); 1445 addrstr[1] = addr & (1 << 6); 1446 addrstr[2] = addr & (1 << 5); 1447 addrstr[3] = addr & (1 << 4); 1448 addrstr[4] = addr & (1 << 3); 1449 addrstr[5] = addr & (1 << 2); 1450 addrstr[6] = addr & (1 << 1); 1451 addrstr[7] = addr & (1 << 0); 1452 } else { 1453 addrlen=6; 1454 addrstr[0] = addr & (1 << 5); 1455 addrstr[1] = addr & (1 << 4); 1456 addrstr[2] = addr & (1 << 3); 1457 addrstr[3] = addr & (1 << 2); 1458 addrstr[4] = addr & (1 << 1); 1459 addrstr[5] = addr & (1 << 0); 1460 } 1461 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1462 if (error != 0) 1463 goto fail; 1464 1465 error = urtw_eprom_writebit(sc, 0); 1466 if (error != 0) 1467 goto fail; 1468 1469 for (i = 0; i < 16; i++) { 1470 error = urtw_eprom_ck(sc); 1471 if (error != 0) 1472 goto fail; 1473 error = urtw_eprom_readbit(sc, &data16); 1474 if (error != 0) 1475 goto fail; 1476 1477 (*data) |= (data16 << (15 - i)); 1478 } 1479 1480 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1481 if (error != 0) 1482 goto fail; 1483 error = urtw_eprom_ck(sc); 1484 if (error != 0) 1485 goto fail; 1486 1487 /* now disable EPROM programming */ 1488 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1489 fail: 1490 return (error); 1491 #undef URTW_READCMD_LEN 1492 } 1493 1494 usbd_status 1495 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1496 { 1497 uint8_t data8; 1498 usbd_status error; 1499 1500 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1501 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1502 DELAY(URTW_EPROM_DELAY); 1503 1504 fail: 1505 return (error); 1506 } 1507 1508 usbd_status 1509 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1510 { 1511 int i = 0; 1512 usbd_status error = 0; 1513 1514 for (i = 0; i < buflen; i++) { 1515 error = urtw_eprom_writebit(sc, buf[i]); 1516 if (error != 0) 1517 goto fail; 1518 error = urtw_eprom_ck(sc); 1519 if (error != 0) 1520 goto fail; 1521 } 1522 fail: 1523 return (error); 1524 } 1525 1526 usbd_status 1527 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1528 { 1529 uint8_t data; 1530 usbd_status error; 1531 1532 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1533 if (bit != 0) 1534 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1535 else 1536 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1537 DELAY(URTW_EPROM_DELAY); 1538 fail: 1539 return (error); 1540 } 1541 1542 usbd_status 1543 urtw_eprom_ck(struct urtw_softc *sc) 1544 { 1545 uint8_t data; 1546 usbd_status error; 1547 1548 /* masking */ 1549 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1550 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1551 DELAY(URTW_EPROM_DELAY); 1552 /* unmasking */ 1553 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1554 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1555 DELAY(URTW_EPROM_DELAY); 1556 fail: 1557 return (error); 1558 } 1559 1560 usbd_status 1561 urtw_eprom_cs(struct urtw_softc *sc, int able) 1562 { 1563 uint8_t data; 1564 usbd_status error; 1565 1566 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1567 if (able == URTW_EPROM_ENABLE) 1568 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1569 else 1570 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1571 DELAY(URTW_EPROM_DELAY); 1572 fail: 1573 return (error); 1574 } 1575 1576 usbd_status 1577 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1578 { 1579 usb_device_request_t req; 1580 usbd_status error; 1581 1582 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1583 req.bRequest = URTW_8187_GETREGS_REQ; 1584 USETW(req.wValue, val | 0xff00); 1585 USETW(req.wIndex, idx & 0x03); 1586 USETW(req.wLength, sizeof(uint8_t)); 1587 1588 error = usbd_do_request(sc->sc_udev, &req, data); 1589 return (error); 1590 } 1591 1592 usbd_status 1593 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1594 { 1595 usb_device_request_t req; 1596 usbd_status error; 1597 1598 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1599 req.bRequest = URTW_8187_GETREGS_REQ; 1600 USETW(req.wValue, val | 0xfe00); 1601 USETW(req.wIndex, 0); 1602 USETW(req.wLength, sizeof(uint8_t)); 1603 1604 error = usbd_do_request(sc->sc_udev, &req, data); 1605 return (error); 1606 } 1607 1608 usbd_status 1609 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1610 { 1611 usb_device_request_t req; 1612 usbd_status error; 1613 1614 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1615 req.bRequest = URTW_8187_GETREGS_REQ; 1616 USETW(req.wValue, val | 0xff00); 1617 USETW(req.wIndex, idx & 0x03); 1618 USETW(req.wLength, sizeof(uint16_t)); 1619 1620 error = usbd_do_request(sc->sc_udev, &req, data); 1621 return (error); 1622 } 1623 1624 usbd_status 1625 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1626 { 1627 usb_device_request_t req; 1628 usbd_status error; 1629 1630 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1631 req.bRequest = URTW_8187_GETREGS_REQ; 1632 USETW(req.wValue, val | 0xff00); 1633 USETW(req.wIndex, idx & 0x03); 1634 USETW(req.wLength, sizeof(uint32_t)); 1635 1636 error = usbd_do_request(sc->sc_udev, &req, data); 1637 return (error); 1638 } 1639 1640 usbd_status 1641 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1642 { 1643 usb_device_request_t req; 1644 1645 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1646 req.bRequest = URTW_8187_SETREGS_REQ; 1647 USETW(req.wValue, val | 0xff00); 1648 USETW(req.wIndex, idx & 0x03); 1649 USETW(req.wLength, sizeof(uint8_t)); 1650 1651 return (usbd_do_request(sc->sc_udev, &req, &data)); 1652 } 1653 1654 usbd_status 1655 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1656 { 1657 usb_device_request_t req; 1658 1659 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1660 req.bRequest = URTW_8187_SETREGS_REQ; 1661 USETW(req.wValue, val | 0xfe00); 1662 USETW(req.wIndex, 0); 1663 USETW(req.wLength, sizeof(uint8_t)); 1664 1665 return (usbd_do_request(sc->sc_udev, &req, &data)); 1666 } 1667 1668 usbd_status 1669 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1670 { 1671 usb_device_request_t req; 1672 1673 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1674 req.bRequest = URTW_8187_SETREGS_REQ; 1675 USETW(req.wValue, val | 0xff00); 1676 USETW(req.wIndex, idx & 0x03); 1677 USETW(req.wLength, sizeof(uint16_t)); 1678 1679 return (usbd_do_request(sc->sc_udev, &req, &data)); 1680 } 1681 1682 usbd_status 1683 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1684 { 1685 usb_device_request_t req; 1686 1687 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1688 req.bRequest = URTW_8187_SETREGS_REQ; 1689 USETW(req.wValue, val | 0xff00); 1690 USETW(req.wIndex, idx & 0x03); 1691 USETW(req.wLength, sizeof(uint32_t)); 1692 1693 return (usbd_do_request(sc->sc_udev, &req, &data)); 1694 } 1695 1696 static usbd_status 1697 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1698 { 1699 uint8_t data; 1700 usbd_status error; 1701 1702 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1703 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1704 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1705 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1706 fail: 1707 return (error); 1708 } 1709 1710 usbd_status 1711 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1712 { 1713 uint8_t data; 1714 usbd_status error; 1715 1716 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1717 if (error) 1718 goto fail; 1719 1720 urtw_read8_m(sc, URTW_CONFIG3, &data); 1721 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1722 urtw_write32_m(sc, URTW_ANAPARAM, val); 1723 urtw_read8_m(sc, URTW_CONFIG3, &data); 1724 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1725 1726 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1727 if (error) 1728 goto fail; 1729 fail: 1730 return (error); 1731 } 1732 1733 usbd_status 1734 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1735 { 1736 uint8_t data; 1737 usbd_status error; 1738 1739 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1740 if (error) 1741 goto fail; 1742 1743 urtw_read8_m(sc, URTW_CONFIG3, &data); 1744 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1745 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1746 urtw_read8_m(sc, URTW_CONFIG3, &data); 1747 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1748 1749 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1750 if (error) 1751 goto fail; 1752 fail: 1753 return (error); 1754 } 1755 1756 usbd_status 1757 urtw_intr_disable(struct urtw_softc *sc) 1758 { 1759 usbd_status error; 1760 1761 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1762 1763 fail: 1764 return (error); 1765 } 1766 1767 usbd_status 1768 urtw_reset(struct urtw_softc *sc) 1769 { 1770 uint8_t data; 1771 usbd_status error; 1772 1773 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1774 if (error) 1775 goto fail; 1776 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1777 if (error) 1778 goto fail; 1779 1780 error = urtw_intr_disable(sc); 1781 if (error) 1782 goto fail; 1783 usbd_delay_ms(sc->sc_udev, 100); 1784 1785 error = urtw_write8e(sc, 0x18, 0x10); 1786 if (error != 0) 1787 goto fail; 1788 error = urtw_write8e(sc, 0x18, 0x11); 1789 if (error != 0) 1790 goto fail; 1791 error = urtw_write8e(sc, 0x18, 0x00); 1792 if (error != 0) 1793 goto fail; 1794 usbd_delay_ms(sc->sc_udev, 100); 1795 1796 urtw_read8_m(sc, URTW_CMD, &data); 1797 data = (data & 2) | URTW_CMD_RST; 1798 urtw_write8_m(sc, URTW_CMD, data); 1799 usbd_delay_ms(sc->sc_udev, 100); 1800 1801 urtw_read8_m(sc, URTW_CMD, &data); 1802 if (data & URTW_CMD_RST) { 1803 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1804 goto fail; 1805 } 1806 1807 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1808 if (error) 1809 goto fail; 1810 usbd_delay_ms(sc->sc_udev, 100); 1811 1812 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1813 if (error) 1814 goto fail; 1815 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1816 if (error) 1817 goto fail; 1818 fail: 1819 return (error); 1820 } 1821 1822 usbd_status 1823 urtw_led_on(struct urtw_softc *sc, int type) 1824 { 1825 usbd_status error; 1826 1827 if (type == URTW_LED_GPIO) { 1828 switch (sc->sc_gpio_ledpin) { 1829 case URTW_LED_PIN_GPIO0: 1830 urtw_write8_m(sc, URTW_GPIO, 0x01); 1831 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1832 break; 1833 default: 1834 panic("unsupported LED PIN type 0x%x", 1835 sc->sc_gpio_ledpin); 1836 /* NOTREACHED */ 1837 } 1838 } else { 1839 panic("unsupported LED type 0x%x", type); 1840 /* NOTREACHED */ 1841 } 1842 1843 sc->sc_gpio_ledon = 1; 1844 fail: 1845 return (error); 1846 } 1847 1848 static usbd_status 1849 urtw_led_off(struct urtw_softc *sc, int type) 1850 { 1851 usbd_status error; 1852 1853 if (type == URTW_LED_GPIO) { 1854 switch (sc->sc_gpio_ledpin) { 1855 case URTW_LED_PIN_GPIO0: 1856 urtw_write8_m(sc, URTW_GPIO, 0x01); 1857 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1858 break; 1859 default: 1860 panic("unsupported LED PIN type 0x%x", 1861 sc->sc_gpio_ledpin); 1862 /* NOTREACHED */ 1863 } 1864 } else { 1865 panic("unsupported LED type 0x%x", type); 1866 /* NOTREACHED */ 1867 } 1868 1869 sc->sc_gpio_ledon = 0; 1870 1871 fail: 1872 return (error); 1873 } 1874 1875 usbd_status 1876 urtw_led_mode0(struct urtw_softc *sc, int mode) 1877 { 1878 switch (mode) { 1879 case URTW_LED_CTL_POWER_ON: 1880 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1881 break; 1882 case URTW_LED_CTL_TX: 1883 if (sc->sc_gpio_ledinprogress == 1) 1884 return (0); 1885 1886 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1887 sc->sc_gpio_blinktime = 2; 1888 break; 1889 case URTW_LED_CTL_LINK: 1890 sc->sc_gpio_ledstate = URTW_LED_ON; 1891 break; 1892 default: 1893 panic("unsupported LED mode 0x%x", mode); 1894 /* NOTREACHED */ 1895 } 1896 1897 switch (sc->sc_gpio_ledstate) { 1898 case URTW_LED_ON: 1899 if (sc->sc_gpio_ledinprogress != 0) 1900 break; 1901 urtw_led_on(sc, URTW_LED_GPIO); 1902 break; 1903 case URTW_LED_BLINK_NORMAL: 1904 if (sc->sc_gpio_ledinprogress != 0) 1905 break; 1906 sc->sc_gpio_ledinprogress = 1; 1907 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1908 URTW_LED_OFF : URTW_LED_ON; 1909 if (!sc->sc_dying) 1910 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1911 break; 1912 case URTW_LED_POWER_ON_BLINK: 1913 urtw_led_on(sc, URTW_LED_GPIO); 1914 usbd_delay_ms(sc->sc_udev, 100); 1915 urtw_led_off(sc, URTW_LED_GPIO); 1916 break; 1917 default: 1918 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 1919 /* NOTREACHED */ 1920 } 1921 return (0); 1922 } 1923 1924 usbd_status 1925 urtw_led_mode1(struct urtw_softc *sc, int mode) 1926 { 1927 return (USBD_INVAL); 1928 } 1929 1930 usbd_status 1931 urtw_led_mode2(struct urtw_softc *sc, int mode) 1932 { 1933 return (USBD_INVAL); 1934 } 1935 1936 usbd_status 1937 urtw_led_mode3(struct urtw_softc *sc, int mode) 1938 { 1939 return (USBD_INVAL); 1940 } 1941 1942 void 1943 urtw_ledusbtask(void *arg) 1944 { 1945 struct urtw_softc *sc = arg; 1946 1947 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1948 panic("could not process a LED strategy 0x%x", sc->sc_strategy); 1949 1950 urtw_led_blink(sc); 1951 } 1952 1953 void 1954 urtw_ledtask(void *arg) 1955 { 1956 struct urtw_softc *sc = arg; 1957 1958 /* 1959 * NB: to change a status of the led we need at least a sleep so we 1960 * can't do it here 1961 */ 1962 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1963 } 1964 1965 usbd_status 1966 urtw_led_ctl(struct urtw_softc *sc, int mode) 1967 { 1968 usbd_status error = 0; 1969 1970 switch (sc->sc_strategy) { 1971 case URTW_SW_LED_MODE0: 1972 error = urtw_led_mode0(sc, mode); 1973 break; 1974 case URTW_SW_LED_MODE1: 1975 error = urtw_led_mode1(sc, mode); 1976 break; 1977 case URTW_SW_LED_MODE2: 1978 error = urtw_led_mode2(sc, mode); 1979 break; 1980 case URTW_SW_LED_MODE3: 1981 error = urtw_led_mode3(sc, mode); 1982 break; 1983 default: 1984 panic("unsupported LED mode %d", sc->sc_strategy); 1985 /* NOTREACHED */ 1986 } 1987 1988 return (error); 1989 } 1990 1991 usbd_status 1992 urtw_led_blink(struct urtw_softc *sc) 1993 { 1994 uint8_t ing = 0; 1995 usbd_status error; 1996 1997 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1998 error = urtw_led_on(sc, URTW_LED_GPIO); 1999 else 2000 error = urtw_led_off(sc, URTW_LED_GPIO); 2001 sc->sc_gpio_blinktime--; 2002 if (sc->sc_gpio_blinktime == 0) 2003 ing = 1; 2004 else { 2005 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 2006 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 2007 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 2008 ing = 1; 2009 } 2010 if (ing == 1) { 2011 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2012 sc->sc_gpio_ledon == 0) 2013 error = urtw_led_on(sc, URTW_LED_GPIO); 2014 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2015 sc->sc_gpio_ledon == 1) 2016 error = urtw_led_off(sc, URTW_LED_GPIO); 2017 2018 sc->sc_gpio_blinktime = 0; 2019 sc->sc_gpio_ledinprogress = 0; 2020 return (0); 2021 } 2022 2023 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2024 URTW_LED_ON : URTW_LED_OFF; 2025 2026 switch (sc->sc_gpio_ledstate) { 2027 case URTW_LED_BLINK_NORMAL: 2028 if (!sc->sc_dying) 2029 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2030 break; 2031 default: 2032 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 2033 /* NOTREACHED */ 2034 } 2035 return (0); 2036 } 2037 2038 usbd_status 2039 urtw_update_msr(struct urtw_softc *sc) 2040 { 2041 struct ieee80211com *ic = &sc->sc_ic; 2042 uint8_t data; 2043 usbd_status error; 2044 2045 urtw_read8_m(sc, URTW_MSR, &data); 2046 data &= ~URTW_MSR_LINK_MASK; 2047 2048 /* Should always be set. */ 2049 if (sc->sc_hwrev & URTW_HWREV_8187B) 2050 data |= URTW_MSR_LINK_ENEDCA; 2051 2052 if (sc->sc_state == IEEE80211_S_RUN) { 2053 switch (ic->ic_opmode) { 2054 case IEEE80211_M_STA: 2055 case IEEE80211_M_MONITOR: 2056 data |= URTW_MSR_LINK_STA; 2057 break; 2058 default: 2059 panic("unsupported operation mode 0x%x", 2060 ic->ic_opmode); 2061 /* NOTREACHED */ 2062 } 2063 } else 2064 data |= URTW_MSR_LINK_NONE; 2065 2066 urtw_write8_m(sc, URTW_MSR, data); 2067 fail: 2068 return (error); 2069 } 2070 2071 uint16_t 2072 urtw_rate2rtl(int rate) 2073 { 2074 unsigned int i; 2075 2076 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2077 if (rate == urtw_ratetable[i].reg) 2078 return (urtw_ratetable[i].val); 2079 } 2080 2081 return (3); 2082 } 2083 2084 uint16_t 2085 urtw_rtl2rate(int rate) 2086 { 2087 unsigned int i; 2088 2089 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2090 if (rate == urtw_ratetable[i].val) 2091 return (urtw_ratetable[i].reg); 2092 } 2093 2094 return (0); 2095 } 2096 2097 usbd_status 2098 urtw_set_rate(struct urtw_softc *sc) 2099 { 2100 int i, basic_rate, min_rr_rate, max_rr_rate; 2101 uint16_t data; 2102 usbd_status error; 2103 2104 basic_rate = urtw_rate2rtl(48); 2105 min_rr_rate = urtw_rate2rtl(12); 2106 max_rr_rate = urtw_rate2rtl(48); 2107 2108 urtw_write8_m(sc, URTW_RESP_RATE, 2109 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2110 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2111 2112 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2113 data &= ~URTW_BRSR_MBR_8185; 2114 2115 for (i = 0; i <= basic_rate; i++) 2116 data |= (1 << i); 2117 2118 urtw_write16_m(sc, URTW_8187_BRSR, data); 2119 fail: 2120 return (error); 2121 } 2122 2123 usbd_status 2124 urtw_intr_enable(struct urtw_softc *sc) 2125 { 2126 usbd_status error; 2127 2128 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2129 fail: 2130 return (error); 2131 } 2132 2133 usbd_status 2134 urtw_rx_setconf(struct urtw_softc *sc) 2135 { 2136 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2137 struct ieee80211com *ic = &sc->sc_ic; 2138 uint32_t data; 2139 usbd_status error; 2140 2141 urtw_read32_m(sc, URTW_RX, &data); 2142 data = data &~ URTW_RX_FILTER_MASK; 2143 #if 0 2144 data = data | URTW_RX_FILTER_CTL; 2145 #endif 2146 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2147 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2148 2149 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2150 data = data | URTW_RX_FILTER_ICVERR; 2151 data = data | URTW_RX_FILTER_PWR; 2152 } 2153 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2154 data = data | URTW_RX_FILTER_CRCERR; 2155 2156 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2157 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2158 data = data | URTW_RX_FILTER_ALLMAC; 2159 } else { 2160 data = data | URTW_RX_FILTER_NICMAC; 2161 data = data | URTW_RX_CHECK_BSSID; 2162 } 2163 2164 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2165 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2166 data = data &~ URTW_MAX_RX_DMA_MASK; 2167 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2168 2169 urtw_write32_m(sc, URTW_RX, data); 2170 fail: 2171 return (error); 2172 } 2173 2174 usbd_status 2175 urtw_rx_enable(struct urtw_softc *sc) 2176 { 2177 int i; 2178 struct urtw_rx_data *rx_data; 2179 uint8_t data; 2180 usbd_status error; 2181 2182 /* 2183 * Start up the receive pipe. 2184 */ 2185 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2186 rx_data = &sc->sc_rx_data[i]; 2187 2188 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2189 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2190 USBD_NO_TIMEOUT, urtw_rxeof); 2191 error = usbd_transfer(rx_data->xfer); 2192 if (error != USBD_IN_PROGRESS && error != 0) { 2193 printf("%s: could not queue Rx transfer\n", 2194 device_xname(sc->sc_dev)); 2195 goto fail; 2196 } 2197 } 2198 2199 error = urtw_rx_setconf(sc); 2200 if (error != 0) 2201 goto fail; 2202 2203 urtw_read8_m(sc, URTW_CMD, &data); 2204 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2205 fail: 2206 return (error); 2207 } 2208 2209 usbd_status 2210 urtw_tx_enable(struct urtw_softc *sc) 2211 { 2212 uint8_t data8; 2213 uint32_t data; 2214 usbd_status error; 2215 2216 if (sc->sc_hwrev & URTW_HWREV_8187) { 2217 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2218 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2219 URTW_CW_CONF_PERPACKET_RETRY); 2220 urtw_write8_m(sc, URTW_CW_CONF, data8); 2221 2222 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2223 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2224 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2225 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2226 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2227 2228 urtw_read32_m(sc, URTW_TX_CONF, &data); 2229 data &= ~URTW_TX_LOOPBACK_MASK; 2230 data |= URTW_TX_LOOPBACK_NONE; 2231 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2232 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2233 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2234 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2235 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2236 data &= ~URTW_TX_SWPLCPLEN; 2237 data |= URTW_TX_NOICV; 2238 urtw_write32_m(sc, URTW_TX_CONF, data); 2239 } else { 2240 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2241 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2242 URTW_TX_LONGRETRY; 2243 urtw_write32_m(sc, URTW_TX_CONF, data); 2244 } 2245 2246 urtw_read8_m(sc, URTW_CMD, &data8); 2247 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2248 fail: 2249 return (error); 2250 } 2251 2252 int 2253 urtw_init(struct ifnet *ifp) 2254 { 2255 struct urtw_softc *sc = ifp->if_softc; 2256 struct urtw_rf *rf = &sc->sc_rf; 2257 struct ieee80211com *ic = &sc->sc_ic; 2258 usbd_status error; 2259 int ret; 2260 2261 urtw_stop(ifp, 0); 2262 2263 error = urtw_reset(sc); 2264 if (error) 2265 goto fail; 2266 2267 urtw_write8_m(sc, 0x85, 0); 2268 urtw_write8_m(sc, URTW_GPIO, 0); 2269 2270 /* for led */ 2271 urtw_write8_m(sc, 0x85, 4); 2272 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2273 if (error != 0) 2274 goto fail; 2275 2276 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2277 if (error) 2278 goto fail; 2279 2280 /* applying MAC address again. */ 2281 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2282 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2283 if (error) 2284 goto fail; 2285 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2286 if (error) 2287 goto fail; 2288 2289 error = urtw_update_msr(sc); 2290 if (error) 2291 goto fail; 2292 2293 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2294 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2295 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2296 error = urtw_set_rate(sc); 2297 if (error != 0) 2298 goto fail; 2299 2300 error = rf->init(rf); 2301 if (error != 0) 2302 goto fail; 2303 if (rf->set_sens != NULL) 2304 rf->set_sens(rf); 2305 2306 urtw_write16_m(sc, 0x5e, 1); 2307 urtw_write16_m(sc, 0xfe, 0x10); 2308 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2309 urtw_write8_m(sc, 0xff, 0x60); 2310 urtw_write16_m(sc, 0x5e, 0); 2311 urtw_write8_m(sc, 0x85, 4); 2312 2313 error = urtw_intr_enable(sc); 2314 if (error != 0) 2315 goto fail; 2316 2317 /* reset softc variables */ 2318 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2319 sc->sc_txtimer = 0; 2320 2321 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2322 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2323 if (error != 0) { 2324 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2325 ", err=%s\n", usbd_errstr(error)); 2326 goto fail; 2327 } 2328 /* get the first interface handle */ 2329 error = usbd_device2interface_handle(sc->sc_udev, 2330 URTW_IFACE_INDEX, &sc->sc_iface); 2331 if (error != 0) { 2332 printf("%s: could not get interface handle\n", 2333 device_xname(sc->sc_dev)); 2334 goto fail; 2335 } 2336 error = urtw_open_pipes(sc); 2337 if (error != 0) 2338 goto fail; 2339 ret = urtw_alloc_rx_data_list(sc); 2340 if (error != 0) 2341 goto fail; 2342 ret = urtw_alloc_tx_data_list(sc); 2343 if (error != 0) 2344 goto fail; 2345 sc->sc_flags |= URTW_INIT_ONCE; 2346 } 2347 2348 error = urtw_rx_enable(sc); 2349 if (error != 0) 2350 goto fail; 2351 error = urtw_tx_enable(sc); 2352 if (error != 0) 2353 goto fail; 2354 2355 ifp->if_flags &= ~IFF_OACTIVE; 2356 ifp->if_flags |= IFF_RUNNING; 2357 2358 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2359 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2360 else 2361 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2362 2363 return (0); 2364 fail: 2365 return (error); 2366 } 2367 2368 int 2369 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2370 { 2371 #define IS_RUNNING(ifp) \ 2372 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2373 2374 struct urtw_softc *sc = ifp->if_softc; 2375 struct ieee80211com *ic = &sc->sc_ic; 2376 int s, error = 0; 2377 2378 if (sc->sc_dying) 2379 return (ENXIO); 2380 2381 s = splnet(); 2382 2383 switch (cmd) { 2384 case SIOCSIFFLAGS: 2385 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2386 break; 2387 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2388 case IFF_UP|IFF_RUNNING: 2389 break; 2390 case IFF_UP: 2391 ifp->if_init(ifp); 2392 break; 2393 case IFF_RUNNING: 2394 urtw_stop(ifp, 1); 2395 break; 2396 case 0: 2397 break; 2398 } 2399 break; 2400 2401 case SIOCADDMULTI: 2402 case SIOCDELMULTI: 2403 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2404 error = 0; 2405 break; 2406 2407 default: 2408 error = ieee80211_ioctl(ic, cmd, data); 2409 break; 2410 } 2411 2412 if (error == ENETRESET) { 2413 if (IS_RUNNING(ifp) && 2414 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2415 ifp->if_init(ifp); 2416 error = 0; 2417 } 2418 2419 splx(s); 2420 2421 return (error); 2422 #undef IS_RUNNING 2423 } 2424 2425 void 2426 urtw_start(struct ifnet *ifp) 2427 { 2428 struct urtw_softc *sc = ifp->if_softc; 2429 struct ieee80211com *ic = &sc->sc_ic; 2430 struct ieee80211_node *ni; 2431 struct ether_header *eh; 2432 struct mbuf *m0; 2433 2434 /* 2435 * net80211 may still try to send management frames even if the 2436 * IFF_RUNNING flag is not set... 2437 */ 2438 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2439 return; 2440 2441 for (;;) { 2442 IF_POLL(&ic->ic_mgtq, m0); 2443 if (m0 != NULL) { 2444 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2445 sc->sc_tx_normal_queued >= 2446 URTW_TX_DATA_LIST_COUNT) { 2447 ifp->if_flags |= IFF_OACTIVE; 2448 break; 2449 } 2450 IF_DEQUEUE(&ic->ic_mgtq, m0); 2451 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2452 m0->m_pkthdr.rcvif = NULL; 2453 bpf_mtap3(ic->ic_rawbpf, m0); 2454 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2455 != 0) 2456 break; 2457 } else { 2458 if (ic->ic_state != IEEE80211_S_RUN) 2459 break; 2460 IFQ_POLL(&ifp->if_snd, m0); 2461 if (m0 == NULL) 2462 break; 2463 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2464 sc->sc_tx_normal_queued >= 2465 URTW_TX_DATA_LIST_COUNT) { 2466 ifp->if_flags |= IFF_OACTIVE; 2467 break; 2468 } 2469 IFQ_DEQUEUE(&ifp->if_snd, m0); 2470 if (m0->m_len < sizeof(struct ether_header) && 2471 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2472 continue; 2473 2474 eh = mtod(m0, struct ether_header *); 2475 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2476 if (ni == NULL) { 2477 m_freem(m0); 2478 continue; 2479 } 2480 bpf_mtap(ifp, m0); 2481 m0 = ieee80211_encap(ic, m0, ni); 2482 if (m0 == NULL) { 2483 ieee80211_free_node(ni); 2484 continue; 2485 } 2486 bpf_mtap3(ic->ic_rawbpf, m0); 2487 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2488 != 0) { 2489 ieee80211_free_node(ni); 2490 ifp->if_oerrors++; 2491 break; 2492 } 2493 } 2494 sc->sc_txtimer = 5; 2495 ifp->if_timer = 1; 2496 } 2497 } 2498 2499 void 2500 urtw_watchdog(struct ifnet *ifp) 2501 { 2502 struct urtw_softc *sc = ifp->if_softc; 2503 2504 ifp->if_timer = 0; 2505 2506 if (sc->sc_txtimer > 0) { 2507 if (--sc->sc_txtimer == 0) { 2508 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2509 ifp->if_oerrors++; 2510 return; 2511 } 2512 ifp->if_timer = 1; 2513 } 2514 2515 ieee80211_watchdog(&sc->sc_ic); 2516 } 2517 2518 void 2519 urtw_txeof_low(usbd_xfer_handle xfer, usbd_private_handle priv, 2520 usbd_status status) 2521 { 2522 struct urtw_tx_data *data = priv; 2523 struct urtw_softc *sc = data->sc; 2524 struct ieee80211com *ic = &sc->sc_ic; 2525 struct ifnet *ifp = ic->ic_ifp; 2526 int s; 2527 2528 if (status != USBD_NORMAL_COMPLETION) { 2529 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2530 return; 2531 2532 printf("%s: could not transmit buffer: %s\n", 2533 device_xname(sc->sc_dev), usbd_errstr(status)); 2534 2535 if (status == USBD_STALLED) 2536 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2537 2538 ifp->if_oerrors++; 2539 return; 2540 } 2541 2542 s = splnet(); 2543 2544 ieee80211_free_node(data->ni); 2545 data->ni = NULL; 2546 2547 sc->sc_txtimer = 0; 2548 ifp->if_opackets++; 2549 2550 sc->sc_tx_low_queued--; 2551 ifp->if_flags &= ~IFF_OACTIVE; 2552 urtw_start(ifp); 2553 2554 splx(s); 2555 } 2556 2557 void 2558 urtw_txeof_normal(usbd_xfer_handle xfer, usbd_private_handle priv, 2559 usbd_status status) 2560 { 2561 struct urtw_tx_data *data = priv; 2562 struct urtw_softc *sc = data->sc; 2563 struct ieee80211com *ic = &sc->sc_ic; 2564 struct ifnet *ifp = ic->ic_ifp; 2565 int s; 2566 2567 if (status != USBD_NORMAL_COMPLETION) { 2568 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2569 return; 2570 2571 printf("%s: could not transmit buffer: %s\n", 2572 device_xname(sc->sc_dev), usbd_errstr(status)); 2573 2574 if (status == USBD_STALLED) 2575 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2576 2577 ifp->if_oerrors++; 2578 return; 2579 } 2580 2581 s = splnet(); 2582 2583 ieee80211_free_node(data->ni); 2584 data->ni = NULL; 2585 2586 sc->sc_txtimer = 0; 2587 ifp->if_opackets++; 2588 2589 sc->sc_tx_normal_queued--; 2590 ifp->if_flags &= ~IFF_OACTIVE; 2591 urtw_start(ifp); 2592 2593 splx(s); 2594 } 2595 2596 int 2597 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2598 int prior) 2599 { 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 struct urtw_tx_data *data; 2602 struct ieee80211_frame *wh; 2603 struct ieee80211_key *k; 2604 usbd_status error; 2605 int xferlen; 2606 2607 wh = mtod(m0, struct ieee80211_frame *); 2608 2609 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2610 k = ieee80211_crypto_encap(ic, ni, m0); 2611 if (k == NULL) { 2612 m_freem(m0); 2613 return (ENOBUFS); 2614 } 2615 /* packet header may have moved, reset our local pointer */ 2616 wh = mtod(m0, struct ieee80211_frame *); 2617 } 2618 2619 if (sc->sc_drvbpf != NULL) { 2620 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2621 2622 tap->wt_flags = 0; 2623 tap->wt_rate = 0; 2624 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2625 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2626 2627 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 2628 } 2629 2630 if (sc->sc_hwrev & URTW_HWREV_8187) 2631 xferlen = m0->m_pkthdr.len + 4 * 3; 2632 else 2633 xferlen = m0->m_pkthdr.len + 4 * 8; 2634 2635 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2636 xferlen += 1; 2637 2638 data = &sc->sc_tx_data[sc->sc_txidx]; 2639 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2640 2641 bzero(data->buf, URTW_TX_MAXSIZE); 2642 data->buf[0] = m0->m_pkthdr.len & 0xff; 2643 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2644 data->buf[1] |= (1 << 7); 2645 2646 /* XXX sc_preamble_mode is always 2. */ 2647 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2648 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2649 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2650 data->buf[2] |= 1; 2651 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2652 prior == URTW_PRIORITY_LOW) 2653 panic("TODO tx."); 2654 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2655 data->buf[2] |= (1 << 1); 2656 /* RTS rate - 10 means we use a basic rate. */ 2657 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2658 /* 2659 * XXX currently TX rate control depends on the rate value of 2660 * RX descriptor because I don't know how to we can control TX rate 2661 * in more smart way. Please fix me you find a thing. 2662 */ 2663 data->buf[3] = sc->sc_currate; 2664 if (prior == URTW_PRIORITY_NORMAL) { 2665 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2666 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2667 else if (ic->ic_fixed_rate != -1) 2668 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2669 } 2670 2671 if (sc->sc_hwrev & URTW_HWREV_8187) { 2672 data->buf[8] = 3; /* CW minimum */ 2673 data->buf[8] |= (7 << 4); /* CW maximum */ 2674 data->buf[9] |= 11; /* retry limitation */ 2675 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2676 } else { 2677 data->buf[21] |= 11; /* retry limitation */ 2678 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2679 } 2680 2681 data->ni = ni; 2682 2683 /* mbuf is no longer needed. */ 2684 m_freem(m0); 2685 2686 usbd_setup_xfer(data->xfer, 2687 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2688 sc->sc_txpipe_normal, data, data->buf, xferlen, 2689 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2690 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2691 error = usbd_transfer(data->xfer); 2692 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2693 printf("%s: could not send frame: %s\n", 2694 device_xname(sc->sc_dev), usbd_errstr(error)); 2695 return (EIO); 2696 } 2697 2698 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2699 if (error != 0) 2700 printf("%s: could not control LED (%d)\n", 2701 device_xname(sc->sc_dev), error); 2702 2703 if (prior == URTW_PRIORITY_LOW) 2704 sc->sc_tx_low_queued++; 2705 else 2706 sc->sc_tx_normal_queued++; 2707 2708 return (0); 2709 } 2710 2711 usbd_status 2712 urtw_8225_usb_init(struct urtw_softc *sc) 2713 { 2714 uint8_t data; 2715 usbd_status error; 2716 2717 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2718 urtw_write8_m(sc, URTW_GPIO, 0); 2719 error = urtw_read8e(sc, 0x53, &data); 2720 if (error) 2721 goto fail; 2722 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2723 if (error) 2724 goto fail; 2725 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2726 urtw_write8_m(sc, URTW_GPIO, 0x20); 2727 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2728 2729 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2730 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2731 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2732 2733 usbd_delay_ms(sc->sc_udev, 500); 2734 fail: 2735 return (error); 2736 } 2737 2738 usbd_status 2739 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2740 { 2741 usbd_status error = 0; 2742 2743 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2744 fail: 2745 return (error); 2746 } 2747 2748 usbd_status 2749 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2750 { 2751 uint32_t phyw; 2752 usbd_status error; 2753 2754 phyw = ((data << 8) | (addr | 0x80)); 2755 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2756 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2757 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2758 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2759 /* 2760 * Delay removed from 8185 to 8187. 2761 * usbd_delay_ms(sc->sc_udev, 1); 2762 */ 2763 fail: 2764 return (error); 2765 } 2766 2767 usbd_status 2768 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2769 { 2770 data = data & 0xff; 2771 return (urtw_8187_write_phy(sc, addr, data)); 2772 } 2773 2774 usbd_status 2775 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2776 { 2777 data = data & 0xff; 2778 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2779 } 2780 2781 usbd_status 2782 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2783 { 2784 usbd_status error; 2785 2786 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2787 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2788 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2789 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2790 fail: 2791 return (error); 2792 } 2793 2794 usbd_status 2795 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2796 { 2797 int i, idx, set; 2798 uint8_t *cck_pwltable; 2799 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2800 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2801 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2802 usbd_status error; 2803 2804 cck_pwrlvl_max = 11; 2805 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2806 ofdm_pwrlvl_min = 10; 2807 2808 /* CCK power setting */ 2809 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2810 idx = cck_pwrlvl % 6; 2811 set = cck_pwrlvl / 6; 2812 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2813 urtw_8225_txpwr_cck; 2814 2815 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2816 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2817 for (i = 0; i < 8; i++) { 2818 urtw_8187_write_phy_cck(sc, 0x44 + i, 2819 cck_pwltable[idx * 8 + i]); 2820 } 2821 usbd_delay_ms(sc->sc_udev, 1); 2822 2823 /* OFDM power setting */ 2824 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2825 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2826 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2827 2828 idx = ofdm_pwrlvl % 6; 2829 set = ofdm_pwrlvl / 6; 2830 2831 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2832 if (error) 2833 goto fail; 2834 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2835 urtw_8187_write_phy_ofdm(sc, 6, 0); 2836 urtw_8187_write_phy_ofdm(sc, 8, 0); 2837 2838 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2839 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2840 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2841 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2842 usbd_delay_ms(sc->sc_udev, 1); 2843 fail: 2844 return (error); 2845 } 2846 2847 usbd_status 2848 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2849 { 2850 usbd_status error; 2851 2852 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2853 usbd_delay_ms(sc->sc_udev, 1); 2854 fail: 2855 return (error); 2856 } 2857 2858 usbd_status 2859 urtw_8225_rf_init(struct urtw_rf *rf) 2860 { 2861 struct urtw_softc *sc = rf->rf_sc; 2862 unsigned int i; 2863 uint16_t data; 2864 usbd_status error; 2865 2866 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2867 if (error) 2868 goto fail; 2869 2870 error = urtw_8225_usb_init(sc); 2871 if (error) 2872 goto fail; 2873 2874 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2875 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2876 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2877 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2878 2879 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2880 if (error) 2881 goto fail; 2882 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2883 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2884 if (error) 2885 goto fail; 2886 2887 error = urtw_8185_rf_pins_enable(sc); 2888 if (error) 2889 goto fail; 2890 2891 usbd_delay_ms(sc->sc_udev, 500); 2892 2893 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2894 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2895 urtw_8225_rf_part1[i].val); 2896 } 2897 usbd_delay_ms(sc->sc_udev, 50); 2898 urtw_8225_write(sc, 0x2, 0xc4d); 2899 usbd_delay_ms(sc->sc_udev, 200); 2900 urtw_8225_write(sc, 0x2, 0x44d); 2901 usbd_delay_ms(sc->sc_udev, 200); 2902 urtw_8225_write(sc, 0x0, 0x127); 2903 2904 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2905 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2906 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2907 } 2908 2909 urtw_8225_write(sc, 0x0, 0x27); 2910 urtw_8225_write(sc, 0x0, 0x22f); 2911 2912 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2913 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2914 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2915 } 2916 2917 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2918 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2919 urtw_8225_rf_part2[i].val); 2920 usbd_delay_ms(sc->sc_udev, 1); 2921 } 2922 2923 error = urtw_8225_setgain(sc, 4); 2924 if (error) 2925 goto fail; 2926 2927 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2928 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2929 urtw_8225_rf_part3[i].val); 2930 usbd_delay_ms(sc->sc_udev, 1); 2931 } 2932 2933 urtw_write8_m(sc, 0x5b, 0x0d); 2934 2935 error = urtw_8225_set_txpwrlvl(sc, 1); 2936 if (error) 2937 goto fail; 2938 2939 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2940 usbd_delay_ms(sc->sc_udev, 1); 2941 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2942 usbd_delay_ms(sc->sc_udev, 1); 2943 2944 /* TX ant A, 0x0 for B */ 2945 error = urtw_8185_tx_antenna(sc, 0x3); 2946 if (error) 2947 goto fail; 2948 urtw_write32_m(sc, 0x94, 0x3dc00002); 2949 2950 error = urtw_8225_rf_set_chan(rf, 1); 2951 fail: 2952 return (error); 2953 } 2954 2955 usbd_status 2956 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2957 { 2958 struct urtw_softc *sc = rf->rf_sc; 2959 struct ieee80211com *ic = &sc->sc_ic; 2960 struct ieee80211_channel *c = ic->ic_ibss_chan; 2961 usbd_status error; 2962 2963 error = urtw_8225_set_txpwrlvl(sc, chan); 2964 if (error) 2965 goto fail; 2966 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2967 usbd_delay_ms(sc->sc_udev, 10); 2968 2969 urtw_write8_m(sc, URTW_SIFS, 0x22); 2970 2971 if (sc->sc_state == IEEE80211_S_ASSOC && 2972 ic->ic_flags & IEEE80211_F_SHSLOT) 2973 urtw_write8_m(sc, URTW_SLOT, 0x9); 2974 else 2975 urtw_write8_m(sc, URTW_SLOT, 0x14); 2976 2977 if (IEEE80211_IS_CHAN_G(c)) { 2978 urtw_write8_m(sc, URTW_DIFS, 0x14); 2979 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2980 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2981 } else { 2982 urtw_write8_m(sc, URTW_DIFS, 0x24); 2983 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2984 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2985 } 2986 2987 fail: 2988 return (error); 2989 } 2990 2991 usbd_status 2992 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2993 { 2994 struct urtw_softc *sc = rf->rf_sc; 2995 usbd_status error; 2996 2997 if (rf->sens > 6) 2998 return (-1); 2999 3000 if (rf->sens > 4) 3001 urtw_8225_write(sc, 0x0c, 0x850); 3002 else 3003 urtw_8225_write(sc, 0x0c, 0x50); 3004 3005 rf->sens = 6 - rf->sens; 3006 error = urtw_8225_setgain(sc, rf->sens); 3007 if (error) 3008 goto fail; 3009 3010 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3011 3012 fail: 3013 return (error); 3014 } 3015 3016 void 3017 urtw_stop(struct ifnet *ifp, int disable) 3018 { 3019 struct urtw_softc *sc = ifp->if_softc; 3020 struct ieee80211com *ic = &sc->sc_ic; 3021 uint8_t data; 3022 usbd_status error; 3023 3024 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3025 3026 sc->sc_txtimer = 0; 3027 ifp->if_timer = 0; 3028 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3029 3030 callout_stop(&sc->scan_to); 3031 callout_stop(&sc->sc_led_ch); 3032 3033 urtw_intr_disable(sc); 3034 urtw_read8_m(sc, URTW_CMD, &data); 3035 data &= ~URTW_CMD_TX_ENABLE; 3036 data &= ~URTW_CMD_RX_ENABLE; 3037 urtw_write8_m(sc, URTW_CMD, data); 3038 3039 if (sc->sc_rxpipe != NULL) 3040 usbd_abort_pipe(sc->sc_rxpipe); 3041 if (sc->sc_txpipe_low != NULL) 3042 usbd_abort_pipe(sc->sc_txpipe_low); 3043 if (sc->sc_txpipe_normal != NULL) 3044 usbd_abort_pipe(sc->sc_txpipe_normal); 3045 3046 fail: 3047 return; 3048 } 3049 3050 int 3051 urtw_isbmode(uint16_t rate) 3052 { 3053 rate = urtw_rtl2rate(rate); 3054 3055 return (((rate <= 22 && rate != 12 && rate != 18) || 3056 rate == 44) ? (1) : (0)); 3057 } 3058 3059 void 3060 urtw_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 3061 { 3062 struct urtw_rx_data *data = priv; 3063 struct urtw_softc *sc = data->sc; 3064 struct ieee80211com *ic = &sc->sc_ic; 3065 struct ifnet *ifp = ic->ic_ifp; 3066 struct ieee80211_frame *wh; 3067 struct ieee80211_node *ni; 3068 struct mbuf *m, *mnew; 3069 uint8_t *desc, quality, rate; 3070 int actlen, flen, len, nf, rssi, s; 3071 3072 if (status != USBD_NORMAL_COMPLETION) { 3073 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3074 return; 3075 3076 if (status == USBD_STALLED) 3077 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3078 ifp->if_ierrors++; 3079 goto skip; 3080 } 3081 3082 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3083 if (actlen < URTW_MIN_RXBUFSZ) { 3084 ifp->if_ierrors++; 3085 goto skip; 3086 } 3087 3088 if (sc->sc_hwrev & URTW_HWREV_8187) 3089 /* 4 dword and 4 byte CRC */ 3090 len = actlen - (4 * 4); 3091 else 3092 /* 5 dword and 4 byte CRC */ 3093 len = actlen - (4 * 5); 3094 3095 desc = data->buf + len; 3096 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3097 if (flen > actlen) { 3098 ifp->if_ierrors++; 3099 goto skip; 3100 } 3101 3102 rate = (desc[2] & 0xf0) >> 4; 3103 if (sc->sc_hwrev & URTW_HWREV_8187) { 3104 quality = desc[4] & 0xff; 3105 rssi = (desc[6] & 0xfe) >> 1; 3106 3107 /* XXX correct? */ 3108 if (!urtw_isbmode(rate)) { 3109 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3110 rssi = ((90 - rssi) * 100) / 65; 3111 } else { 3112 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3113 rssi = ((95 - rssi) * 100) / 65; 3114 } 3115 } else { 3116 quality = desc[12]; 3117 rssi = 14 - desc[14] / 2; 3118 } 3119 3120 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3121 if (mnew == NULL) { 3122 printf("%s: could not allocate rx mbuf\n", 3123 device_xname(sc->sc_dev)); 3124 ifp->if_ierrors++; 3125 goto skip; 3126 } 3127 MCLGET(mnew, M_DONTWAIT); 3128 if (!(mnew->m_flags & M_EXT)) { 3129 printf("%s: could not allocate rx mbuf cluster\n", 3130 device_xname(sc->sc_dev)); 3131 m_freem(mnew); 3132 ifp->if_ierrors++; 3133 goto skip; 3134 } 3135 3136 m = data->m; 3137 data->m = mnew; 3138 data->buf = mtod(mnew, uint8_t *); 3139 3140 /* finalize mbuf */ 3141 m->m_pkthdr.rcvif = ifp; 3142 m->m_pkthdr.len = m->m_len = flen - 4; 3143 3144 s = splnet(); 3145 3146 if (sc->sc_drvbpf != NULL) { 3147 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3148 3149 /* XXX Are variables correct? */ 3150 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3151 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3152 tap->wr_dbm_antsignal = (int8_t)rssi; 3153 3154 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 3155 } 3156 wh = mtod(m, struct ieee80211_frame *); 3157 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3158 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3159 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3160 3161 /* XXX correct? */ 3162 if (!urtw_isbmode(rate)) { 3163 if (quality > 127) 3164 quality = 0; 3165 else if (quality < 27) 3166 quality = 100; 3167 else 3168 quality = 127 - quality; 3169 } else 3170 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3171 3172 nf = quality; 3173 3174 /* send the frame to the 802.11 layer */ 3175 ieee80211_input(ic, m, ni, rssi, 0); 3176 3177 /* node is no longer needed */ 3178 ieee80211_free_node(ni); 3179 3180 splx(s); 3181 3182 skip: /* setup a new transfer */ 3183 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3184 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3185 (void)usbd_transfer(xfer); 3186 } 3187 3188 usbd_status 3189 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3190 { 3191 uint8_t *gainp; 3192 usbd_status error; 3193 3194 /* XXX for A? */ 3195 gainp = urtw_8225v2_gain_bg; 3196 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3197 usbd_delay_ms(sc->sc_udev, 1); 3198 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3199 usbd_delay_ms(sc->sc_udev, 1); 3200 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3201 usbd_delay_ms(sc->sc_udev, 1); 3202 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3203 usbd_delay_ms(sc->sc_udev, 1); 3204 fail: 3205 return (error); 3206 } 3207 3208 usbd_status 3209 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3210 { 3211 int i; 3212 uint8_t *cck_pwrtable; 3213 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3214 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3215 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3216 usbd_status error; 3217 3218 /* CCK power setting */ 3219 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3220 cck_pwrlvl += sc->sc_txpwr_cck_base; 3221 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3222 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3223 urtw_8225v2_txpwr_cck; 3224 3225 for (i = 0; i < 8; i++) { 3226 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3227 } 3228 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3229 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3230 usbd_delay_ms(sc->sc_udev, 1); 3231 3232 /* OFDM power setting */ 3233 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3234 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3235 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3236 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3237 3238 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3239 if (error) 3240 goto fail; 3241 3242 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3243 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3244 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3245 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3246 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3247 3248 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3249 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3250 usbd_delay_ms(sc->sc_udev, 1); 3251 fail: 3252 return (error); 3253 } 3254 3255 usbd_status 3256 urtw_8225v2_rf_init(struct urtw_rf *rf) 3257 { 3258 struct urtw_softc *sc = rf->rf_sc; 3259 int i; 3260 uint16_t data; 3261 uint32_t data32; 3262 usbd_status error; 3263 3264 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3265 if (error) 3266 goto fail; 3267 3268 error = urtw_8225_usb_init(sc); 3269 if (error) 3270 goto fail; 3271 3272 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3273 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3274 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3275 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3276 3277 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3278 if (error) 3279 goto fail; 3280 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3281 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3282 if (error) 3283 goto fail; 3284 3285 error = urtw_8185_rf_pins_enable(sc); 3286 if (error) 3287 goto fail; 3288 3289 usbd_delay_ms(sc->sc_udev, 1000); 3290 3291 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3292 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3293 urtw_8225v2_rf_part1[i].val); 3294 usbd_delay_ms(sc->sc_udev, 1); 3295 } 3296 usbd_delay_ms(sc->sc_udev, 50); 3297 3298 urtw_8225_write(sc, 0x0, 0x1b7); 3299 3300 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3301 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3302 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3303 } 3304 3305 urtw_8225_write(sc, 0x3, 0x2); 3306 urtw_8225_write(sc, 0x5, 0x4); 3307 urtw_8225_write(sc, 0x0, 0xb7); 3308 urtw_8225_write(sc, 0x2, 0xc4d); 3309 usbd_delay_ms(sc->sc_udev, 100); 3310 urtw_8225_write(sc, 0x2, 0x44d); 3311 usbd_delay_ms(sc->sc_udev, 100); 3312 3313 error = urtw_8225_read(sc, 0x6, &data32); 3314 if (error != 0) 3315 goto fail; 3316 if (data32 != 0xe6) 3317 printf("%s: expect 0xe6!! (0x%x)\n", device_xname(sc->sc_dev), 3318 data32); 3319 if (!(data32 & 0x80)) { 3320 urtw_8225_write(sc, 0x02, 0x0c4d); 3321 usbd_delay_ms(sc->sc_udev, 200); 3322 urtw_8225_write(sc, 0x02, 0x044d); 3323 usbd_delay_ms(sc->sc_udev, 100); 3324 error = urtw_8225_read(sc, 0x6, &data32); 3325 if (error != 0) 3326 goto fail; 3327 if (!(data32 & 0x80)) 3328 printf("%s: RF calibration failed\n", 3329 device_xname(sc->sc_dev)); 3330 } 3331 usbd_delay_ms(sc->sc_udev, 100); 3332 3333 urtw_8225_write(sc, 0x0, 0x2bf); 3334 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3335 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3336 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3337 } 3338 3339 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3340 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3341 urtw_8225v2_rf_part2[i].val); 3342 } 3343 3344 error = urtw_8225v2_setgain(sc, 4); 3345 if (error) 3346 goto fail; 3347 3348 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3349 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3350 urtw_8225v2_rf_part3[i].val); 3351 } 3352 3353 urtw_write8_m(sc, 0x5b, 0x0d); 3354 3355 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3356 if (error) 3357 goto fail; 3358 3359 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3360 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3361 3362 /* TX ant A, 0x0 for B */ 3363 error = urtw_8185_tx_antenna(sc, 0x3); 3364 if (error) 3365 goto fail; 3366 urtw_write32_m(sc, 0x94, 0x3dc00002); 3367 3368 error = urtw_8225_rf_set_chan(rf, 1); 3369 fail: 3370 return (error); 3371 } 3372 3373 usbd_status 3374 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3375 { 3376 struct urtw_softc *sc = rf->rf_sc; 3377 struct ieee80211com *ic = &sc->sc_ic; 3378 struct ieee80211_channel *c = ic->ic_ibss_chan; 3379 usbd_status error; 3380 3381 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3382 if (error) 3383 goto fail; 3384 3385 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3386 usbd_delay_ms(sc->sc_udev, 10); 3387 3388 urtw_write8_m(sc, URTW_SIFS, 0x22); 3389 3390 if(sc->sc_state == IEEE80211_S_ASSOC && 3391 ic->ic_flags & IEEE80211_F_SHSLOT) 3392 urtw_write8_m(sc, URTW_SLOT, 0x9); 3393 else 3394 urtw_write8_m(sc, URTW_SLOT, 0x14); 3395 3396 if (IEEE80211_IS_CHAN_G(c)) { 3397 urtw_write8_m(sc, URTW_DIFS, 0x14); 3398 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3399 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3400 } else { 3401 urtw_write8_m(sc, URTW_DIFS, 0x24); 3402 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3403 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3404 } 3405 3406 fail: 3407 return (error); 3408 } 3409 3410 void 3411 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3412 { 3413 struct urtw_rf *rf = &sc->sc_rf; 3414 struct ieee80211com *ic = &sc->sc_ic; 3415 usbd_status error = 0; 3416 uint32_t data; 3417 u_int chan; 3418 3419 chan = ieee80211_chan2ieee(ic, c); 3420 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3421 return; 3422 /* 3423 * During changing the channel we need to temporary disable 3424 * TX. 3425 */ 3426 urtw_read32_m(sc, URTW_TX_CONF, &data); 3427 data &= ~URTW_TX_LOOPBACK_MASK; 3428 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3429 error = rf->set_chan(rf, chan); 3430 if (error != 0) { 3431 printf("%s could not change the channel\n", 3432 device_xname(sc->sc_dev)); 3433 return; 3434 } 3435 usbd_delay_ms(sc->sc_udev, 10); 3436 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3437 3438 fail: return; 3439 3440 } 3441 3442 void 3443 urtw_next_scan(void *arg) 3444 { 3445 struct urtw_softc *sc = arg; 3446 struct ieee80211com *ic = &sc->sc_ic; 3447 int s; 3448 3449 if (sc->sc_dying) 3450 return; 3451 3452 s = splnet(); 3453 if (ic->ic_state == IEEE80211_S_SCAN) 3454 ieee80211_next_scan(ic); 3455 splx(s); 3456 } 3457 3458 void 3459 urtw_task(void *arg) 3460 { 3461 struct urtw_softc *sc = arg; 3462 struct ieee80211com *ic = &sc->sc_ic; 3463 struct ieee80211_node *ni; 3464 enum ieee80211_state ostate; 3465 usbd_status error = 0; 3466 3467 if (sc->sc_dying) 3468 return; 3469 3470 ostate = ic->ic_state; 3471 3472 switch (sc->sc_state) { 3473 case IEEE80211_S_INIT: 3474 if (ostate == IEEE80211_S_RUN) { 3475 /* turn link LED off */ 3476 (void)urtw_led_off(sc, URTW_LED_GPIO); 3477 } 3478 break; 3479 3480 case IEEE80211_S_SCAN: 3481 urtw_set_chan(sc, ic->ic_curchan); 3482 if (!sc->sc_dying) 3483 callout_schedule(&sc->scan_to, mstohz(200)); 3484 break; 3485 3486 case IEEE80211_S_AUTH: 3487 case IEEE80211_S_ASSOC: 3488 urtw_set_chan(sc, ic->ic_curchan); 3489 break; 3490 3491 case IEEE80211_S_RUN: 3492 ni = ic->ic_bss; 3493 3494 urtw_set_chan(sc, ic->ic_curchan); 3495 3496 /* setting bssid. */ 3497 error = urtw_set_bssid(sc, ni->ni_bssid); 3498 if (error != 0) 3499 goto fail; 3500 urtw_update_msr(sc); 3501 /* XXX maybe the below would be incorrect. */ 3502 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3503 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3504 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3505 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3506 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3507 if (error != 0) 3508 printf("%s: could not control LED (%d)\n", 3509 device_xname(sc->sc_dev), error); 3510 break; 3511 } 3512 3513 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3514 3515 fail: 3516 if (error != 0) { 3517 DPRINTF(("%s: error duing processing RUN state.", 3518 device_xname(sc->sc_dev))); 3519 } 3520 } 3521 3522 usbd_status 3523 urtw_8187b_update_wmm(struct urtw_softc *sc) 3524 { 3525 struct ieee80211com *ic = &sc->sc_ic; 3526 struct ieee80211_channel *c = ic->ic_ibss_chan; 3527 uint32_t data; 3528 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3529 usbd_status error; 3530 3531 sifs = 0xa; 3532 if (IEEE80211_IS_CHAN_G(c)) 3533 slot = 0x9; 3534 else 3535 slot = 0x14; 3536 3537 aifs = (2 * slot) + sifs; 3538 ecwmin = 3; 3539 ecwmax = 7; 3540 3541 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3542 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3543 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3544 3545 urtw_write32_m(sc, URTW_AC_VO, data); 3546 urtw_write32_m(sc, URTW_AC_VI, data); 3547 urtw_write32_m(sc, URTW_AC_BE, data); 3548 urtw_write32_m(sc, URTW_AC_BK, data); 3549 3550 fail: 3551 return (error); 3552 } 3553 3554 usbd_status 3555 urtw_8187b_reset(struct urtw_softc *sc) 3556 { 3557 uint8_t data; 3558 usbd_status error; 3559 3560 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3561 if (error) 3562 goto fail; 3563 3564 urtw_read8_m(sc, URTW_CONFIG3, &data); 3565 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3566 URTW_CONFIG3_GNT_SELECT); 3567 3568 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3569 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3570 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3571 3572 urtw_write8_m(sc, 0x61, 0x10); 3573 urtw_read8_m(sc, 0x62, &data); 3574 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3575 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3576 3577 urtw_read8_m(sc, URTW_CONFIG3, &data); 3578 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3579 3580 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3581 if (error) 3582 goto fail; 3583 3584 urtw_read8_m(sc, URTW_CMD, &data); 3585 data = (data & 2) | URTW_CMD_RST; 3586 urtw_write8_m(sc, URTW_CMD, data); 3587 usbd_delay_ms(sc->sc_udev, 100); 3588 3589 urtw_read8_m(sc, URTW_CMD, &data); 3590 if (data & URTW_CMD_RST) { 3591 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3592 goto fail; 3593 } 3594 3595 fail: 3596 return (error); 3597 } 3598 3599 int 3600 urtw_8187b_init(struct ifnet *ifp) 3601 { 3602 struct urtw_softc *sc = ifp->if_softc; 3603 struct urtw_rf *rf = &sc->sc_rf; 3604 struct ieee80211com *ic = &sc->sc_ic; 3605 int ret; 3606 uint8_t data; 3607 usbd_status error; 3608 3609 urtw_stop(ifp, 0); 3610 3611 error = urtw_8187b_update_wmm(sc); 3612 if (error != 0) 3613 goto fail; 3614 error = urtw_8187b_reset(sc); 3615 if (error) 3616 goto fail; 3617 3618 /* Applying MAC address again. */ 3619 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3620 if (error) 3621 goto fail; 3622 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3623 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3624 if (error) 3625 goto fail; 3626 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3627 if (error) 3628 goto fail; 3629 3630 error = urtw_update_msr(sc); 3631 if (error) 3632 goto fail; 3633 3634 error = rf->init(rf); 3635 if (error != 0) 3636 goto fail; 3637 3638 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3639 URTW_CMD_RX_ENABLE); 3640 error = urtw_intr_enable(sc); 3641 if (error != 0) 3642 goto fail; 3643 3644 error = urtw_write8e(sc, 0x41, 0xf4); 3645 if (error != 0) 3646 goto fail; 3647 error = urtw_write8e(sc, 0x40, 0x00); 3648 if (error != 0) 3649 goto fail; 3650 error = urtw_write8e(sc, 0x42, 0x00); 3651 if (error != 0) 3652 goto fail; 3653 error = urtw_write8e(sc, 0x42, 0x01); 3654 if (error != 0) 3655 goto fail; 3656 error = urtw_write8e(sc, 0x40, 0x0f); 3657 if (error != 0) 3658 goto fail; 3659 error = urtw_write8e(sc, 0x42, 0x00); 3660 if (error != 0) 3661 goto fail; 3662 error = urtw_write8e(sc, 0x42, 0x01); 3663 if (error != 0) 3664 goto fail; 3665 3666 urtw_read8_m(sc, 0xdb, &data); 3667 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3668 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3669 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3670 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3671 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3672 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3673 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3674 urtw_write8_m(sc, 0x61, 0); 3675 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3676 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3677 urtw_write8_m(sc, 0xda, 0x10); 3678 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3679 3680 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3681 3682 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3683 3684 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3685 3686 /* Reset softc variables. */ 3687 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3688 sc->sc_txtimer = 0; 3689 3690 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3691 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3692 if (error != 0) { 3693 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3694 ", err=%s\n", usbd_errstr(error)); 3695 3696 goto fail; 3697 } 3698 /* Get the first interface handle. */ 3699 error = usbd_device2interface_handle(sc->sc_udev, 3700 URTW_IFACE_INDEX, &sc->sc_iface); 3701 if (error != 0) { 3702 printf("%s: could not get interface handle\n", 3703 device_xname(sc->sc_dev)); 3704 goto fail; 3705 } 3706 error = urtw_open_pipes(sc); 3707 if (error != 0) 3708 goto fail; 3709 ret = urtw_alloc_rx_data_list(sc); 3710 if (error != 0) 3711 goto fail; 3712 ret = urtw_alloc_tx_data_list(sc); 3713 if (error != 0) 3714 goto fail; 3715 sc->sc_flags |= URTW_INIT_ONCE; 3716 } 3717 3718 error = urtw_rx_enable(sc); 3719 if (error != 0) 3720 goto fail; 3721 error = urtw_tx_enable(sc); 3722 if (error != 0) 3723 goto fail; 3724 3725 ifp->if_flags &= ~IFF_OACTIVE; 3726 ifp->if_flags |= IFF_RUNNING; 3727 3728 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3729 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3730 else 3731 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3732 3733 fail: 3734 return (error); 3735 } 3736 3737 usbd_status 3738 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3739 { 3740 int i; 3741 usbd_status error; 3742 3743 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3744 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3745 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3746 } 3747 3748 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3749 urtw_write16_m(sc, URTW_INT_MIG, 0); 3750 3751 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3752 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3753 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3754 3755 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3756 3757 fail: 3758 return (error); 3759 } 3760 3761 usbd_status 3762 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3763 { 3764 usbd_status error; 3765 3766 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3767 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3768 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3769 usbd_delay_ms(sc->sc_udev, 100); 3770 3771 fail: 3772 return (error); 3773 } 3774 3775 usbd_status 3776 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3777 { 3778 struct ieee80211com *ic = &sc->sc_ic; 3779 struct ieee80211_channel *c = ic->ic_ibss_chan; 3780 uint8_t aifs, difs, eifs, sifs, slot; 3781 usbd_status error; 3782 3783 urtw_write8_m(sc, URTW_SIFS, 0x22); 3784 3785 sifs = 0xa; 3786 if (IEEE80211_IS_CHAN_G(c)) { 3787 slot = 0x9; 3788 difs = 0x1c; 3789 eifs = 0x5b; 3790 } else { 3791 slot = 0x14; 3792 difs = 0x32; 3793 eifs = 0x5b; 3794 } 3795 aifs = (2 * slot) + sifs; 3796 3797 urtw_write8_m(sc, URTW_SLOT, slot); 3798 3799 urtw_write8_m(sc, URTW_AC_VO, aifs); 3800 urtw_write8_m(sc, URTW_AC_VI, aifs); 3801 urtw_write8_m(sc, URTW_AC_BE, aifs); 3802 urtw_write8_m(sc, URTW_AC_BK, aifs); 3803 3804 urtw_write8_m(sc, URTW_DIFS, difs); 3805 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3806 3807 fail: 3808 return (error); 3809 } 3810 3811 usbd_status 3812 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3813 { 3814 struct urtw_softc *sc = rf->rf_sc; 3815 unsigned int i; 3816 uint8_t data; 3817 usbd_status error; 3818 3819 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3820 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3821 urtw_read8_m(sc, URTW_CW_CONF, &data); 3822 urtw_write8_m(sc, URTW_CW_CONF, data | 3823 URTW_CW_CONF_PERPACKET_RETRY); 3824 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3825 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3826 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3827 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3828 3829 /* Auto rate fallback control. */ 3830 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3831 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3832 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3833 URTW_RATE_FALLBACK_ENABLE); 3834 3835 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3836 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3837 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3838 3839 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3840 if (error) 3841 goto fail; 3842 urtw_read8_m(sc, URTW_CONFIG1, &data); 3843 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3844 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3845 if (error) 3846 goto fail; 3847 3848 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3849 urtw_8225v2_b_config_mac(sc); 3850 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3851 3852 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3853 if (error) 3854 goto fail; 3855 urtw_read8_m(sc, URTW_CONFIG3, &data); 3856 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3857 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3858 if (error) 3859 goto fail; 3860 3861 urtw_8225v2_b_init_rfe(sc); 3862 3863 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3864 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3865 urtw_8225v2_b_rf[i].val); 3866 } 3867 3868 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3869 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3870 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3871 } 3872 3873 urtw_8225_write(sc, 0x03, 0x080); 3874 urtw_8225_write(sc, 0x05, 0x004); 3875 urtw_8225_write(sc, 0x00, 0x0b7); 3876 urtw_8225_write(sc, 0x02, 0xc4d); 3877 urtw_8225_write(sc, 0x02, 0x44d); 3878 urtw_8225_write(sc, 0x00, 0x2bf); 3879 3880 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3881 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3882 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3883 3884 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3885 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3886 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3887 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3888 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3889 } 3890 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3891 3892 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3893 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3894 3895 urtw_8225v2_b_update_chan(sc); 3896 3897 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3898 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3899 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3900 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3901 3902 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3903 fail: 3904 return (error); 3905 } 3906 3907 usbd_status 3908 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3909 { 3910 struct urtw_softc *sc = rf->rf_sc; 3911 usbd_status error; 3912 3913 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3914 if (error) 3915 goto fail; 3916 3917 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3918 /* 3919 * Delay removed from 8185 to 8187. 3920 * usbd_delay_ms(sc->sc_udev, 10); 3921 */ 3922 3923 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3924 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3925 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3926 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3927 3928 fail: 3929 return (error); 3930 } 3931 3932 usbd_status 3933 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3934 { 3935 int i; 3936 uint8_t *cck_pwrtable; 3937 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3938 ofdm_pwrlvl_max; 3939 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3940 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3941 usbd_status error; 3942 3943 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3944 cck_pwrlvl_min = 0; 3945 cck_pwrlvl_max = 15; 3946 ofdm_pwrlvl_min = 2; 3947 ofdm_pwrlvl_max = 17; 3948 } else { 3949 cck_pwrlvl_min = 7; 3950 cck_pwrlvl_max = 22; 3951 ofdm_pwrlvl_min = 10; 3952 ofdm_pwrlvl_max = 25; 3953 } 3954 3955 /* CCK power setting */ 3956 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3957 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3958 3959 cck_pwrlvl += sc->sc_txpwr_cck_base; 3960 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3961 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3962 3963 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3964 urtw_8225v2_txpwr_cck; 3965 3966 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3967 if (cck_pwrlvl <= 6) 3968 ; /* do nothing */ 3969 else if (cck_pwrlvl <= 11) 3970 cck_pwrtable += 8; 3971 else 3972 cck_pwrtable += 16; 3973 } else { 3974 if (cck_pwrlvl <= 5) 3975 ; /* do nothing */ 3976 else if (cck_pwrlvl <= 11) 3977 cck_pwrtable += 8; 3978 else if (cck_pwrlvl <= 17) 3979 cck_pwrtable += 16; 3980 else 3981 cck_pwrtable += 24; 3982 } 3983 3984 for (i = 0; i < 8; i++) { 3985 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3986 } 3987 3988 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3989 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3990 /* 3991 * Delay removed from 8185 to 8187. 3992 * usbd_delay_ms(sc->sc_udev, 1); 3993 */ 3994 3995 /* OFDM power setting */ 3996 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3997 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3998 3999 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 4000 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 4001 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 4002 4003 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 4004 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 4005 4006 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 4007 if (ofdm_pwrlvl <= 11) { 4008 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 4009 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 4010 } else { 4011 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4012 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4013 } 4014 } else { 4015 if (ofdm_pwrlvl <= 11) { 4016 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4017 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4018 } else if (ofdm_pwrlvl <= 17) { 4019 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4020 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4021 } else { 4022 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4023 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4024 } 4025 } 4026 4027 /* 4028 * Delay removed from 8185 to 8187. 4029 * usbd_delay_ms(sc->sc_udev, 1); 4030 */ 4031 fail: 4032 return (error); 4033 } 4034 4035 int 4036 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4037 { 4038 int error; 4039 4040 urtw_write32_m(sc, URTW_BSSID, 4041 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4042 urtw_write16_m(sc, URTW_BSSID + 4, 4043 bssid[4] | bssid[5] << 8); 4044 4045 return 0; 4046 4047 fail: 4048 return error; 4049 } 4050 4051 int 4052 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4053 { 4054 int error; 4055 4056 urtw_write32_m(sc, URTW_MAC0, 4057 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4058 urtw_write16_m(sc, URTW_MAC4, 4059 addr[4] | addr[5] << 8); 4060 4061 return 0; 4062 4063 fail: 4064 return error; 4065 } 4066 4067 MODULE(MODULE_CLASS_DRIVER, if_urtw, "bpf"); 4068 4069 #ifdef _MODULE 4070 #include "ioconf.c" 4071 #endif 4072 4073 static int 4074 if_urtw_modcmd(modcmd_t cmd, void *aux) 4075 { 4076 int error = 0; 4077 4078 switch (cmd) { 4079 case MODULE_CMD_INIT: 4080 #ifdef _MODULE 4081 error = config_init_component(cfdriver_ioconf_urtw, 4082 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4083 #endif 4084 return error; 4085 case MODULE_CMD_FINI: 4086 #ifdef _MODULE 4087 error = config_fini_component(cfdriver_ioconf_urtw, 4088 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4089 #endif 4090 return error; 4091 default: 4092 return ENOTTY; 4093 } 4094 } 4095
Indexes created Fri Oct 03 02:09:57 GMT 2025