if_urtw.c revision 1.6.6.8
1 /* $NetBSD: if_urtw.c,v 1.6.6.8 2015/03/21 11:33:37 skrll Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.6.6.8 2015/03/21 11:33:37 skrll Exp $"); 23 24 #include <sys/param.h> 25 #include <sys/sockio.h> 26 #include <sys/proc.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/callout.h> 32 #include <sys/conf.h> 33 #include <sys/device.h> 34 #include <sys/module.h> 35 #include <sys/bus.h> 36 37 #include <machine/endian.h> 38 #include <net/bpf.h> 39 #include <net/if.h> 40 #include <net/if_arp.h> 41 #include <net/if_dl.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 #include <netinet/in_var.h> 49 #include <netinet/if_inarp.h> 50 #include <netinet/ip.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdi_util.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdevs.h> 60 61 #include "if_urtwreg.h" 62 63 #ifdef URTW_DEBUG 64 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 65 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 66 int urtw_debug = 0; 67 #else 68 #define DPRINTF(x) 69 #define DPRINTFN(n, x) 70 #endif 71 72 /* 73 * Recognized device vendors/products. 74 */ 75 static const struct urtw_type { 76 struct usb_devno dev; 77 uint8_t rev; 78 } urtw_devs[] = { 79 #define URTW_DEV_RTL8187(v, p) \ 80 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 81 #define URTW_DEV_RTL8187B(v, p) \ 82 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 83 /* Realtek RTL8187 devices. */ 84 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 85 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 86 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 87 URTW_DEV_RTL8187(LOGITEC, RTL8187), 88 URTW_DEV_RTL8187(NETGEAR, WG111V2), 89 URTW_DEV_RTL8187(REALTEK, RTL8187), 90 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 91 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 92 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 93 /* Realtek RTL8187B devices. */ 94 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 95 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 96 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 97 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 98 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 99 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 100 #undef URTW_DEV_RTL8187 101 #undef URTW_DEV_RTL8187B 102 }; 103 #define urtw_lookup(v, p) \ 104 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 105 106 /* 107 * Helper read/write macros. 108 */ 109 #define urtw_read8_m(sc, val, data) do { \ 110 error = urtw_read8_c(sc, val, data, 0); \ 111 if (error != 0) \ 112 goto fail; \ 113 } while (0) 114 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 115 error = urtw_read8_c(sc, val, data, idx); \ 116 if (error != 0) \ 117 goto fail; \ 118 } while (0) 119 #define urtw_write8_m(sc, val, data) do { \ 120 error = urtw_write8_c(sc, val, data, 0); \ 121 if (error != 0) \ 122 goto fail; \ 123 } while (0) 124 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 125 error = urtw_write8_c(sc, val, data, idx); \ 126 if (error != 0) \ 127 goto fail; \ 128 } while (0) 129 #define urtw_read16_m(sc, val, data) do { \ 130 error = urtw_read16_c(sc, val, data, 0); \ 131 if (error != 0) \ 132 goto fail; \ 133 } while (0) 134 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 135 error = urtw_read16_c(sc, val, data, idx); \ 136 if (error != 0) \ 137 goto fail; \ 138 } while (0) 139 #define urtw_write16_m(sc, val, data) do { \ 140 error = urtw_write16_c(sc, val, data, 0); \ 141 if (error != 0) \ 142 goto fail; \ 143 } while (0) 144 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 145 error = urtw_write16_c(sc, val, data, idx); \ 146 if (error != 0) \ 147 goto fail; \ 148 } while (0) 149 #define urtw_read32_m(sc, val, data) do { \ 150 error = urtw_read32_c(sc, val, data, 0); \ 151 if (error != 0) \ 152 goto fail; \ 153 } while (0) 154 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 155 error = urtw_read32_c(sc, val, data, idx); \ 156 if (error != 0) \ 157 goto fail; \ 158 } while (0) 159 #define urtw_write32_m(sc, val, data) do { \ 160 error = urtw_write32_c(sc, val, data, 0); \ 161 if (error != 0) \ 162 goto fail; \ 163 } while (0) 164 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 165 error = urtw_write32_c(sc, val, data, idx); \ 166 if (error != 0) \ 167 goto fail; \ 168 } while (0) 169 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 170 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 171 if (error != 0) \ 172 goto fail; \ 173 } while (0) 174 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 175 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 176 if (error != 0) \ 177 goto fail; \ 178 } while (0) 179 #define urtw_8225_write(sc, val, data) do { \ 180 error = urtw_8225_write_c(sc, val, data); \ 181 if (error != 0) \ 182 goto fail; \ 183 } while (0) 184 185 struct urtw_pair { 186 uint32_t reg; 187 uint32_t val; 188 }; 189 190 struct urtw_pair_idx { 191 uint8_t reg; 192 uint8_t val; 193 uint8_t idx; 194 }; 195 196 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 197 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 198 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 199 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 200 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 201 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 202 { 0xff, 0x00, 0 }, 203 204 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 205 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 206 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 207 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 208 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 209 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 210 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 211 { 0xf8, 0x08, 1 }, 212 213 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 214 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 215 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 216 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 217 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 218 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 219 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 220 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 221 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 222 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 223 224 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 225 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 226 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 227 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 228 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 229 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 230 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 231 232 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 233 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 234 }; 235 236 static uint8_t urtw_8225_agc[] = { 237 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 238 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 239 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 240 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 241 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 242 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 243 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 244 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 245 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 246 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 247 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 248 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 249 }; 250 251 static uint32_t urtw_8225_channel[] = { 252 0x0000, /* dummy channel 0 */ 253 0x085c, /* 1 */ 254 0x08dc, /* 2 */ 255 0x095c, /* 3 */ 256 0x09dc, /* 4 */ 257 0x0a5c, /* 5 */ 258 0x0adc, /* 6 */ 259 0x0b5c, /* 7 */ 260 0x0bdc, /* 8 */ 261 0x0c5c, /* 9 */ 262 0x0cdc, /* 10 */ 263 0x0d5c, /* 11 */ 264 0x0ddc, /* 12 */ 265 0x0e5c, /* 13 */ 266 0x0f72, /* 14 */ 267 }; 268 269 static uint8_t urtw_8225_gain[] = { 270 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 271 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 272 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 273 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 274 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 275 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 276 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 277 }; 278 279 static struct urtw_pair urtw_8225_rf_part1[] = { 280 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 281 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 282 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 283 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 284 }; 285 286 static struct urtw_pair urtw_8225_rf_part2[] = { 287 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 288 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 289 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 290 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 291 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 292 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 293 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 294 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 295 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 296 { 0x27, 0x88 } 297 }; 298 299 static struct urtw_pair urtw_8225_rf_part3[] = { 300 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 301 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 302 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 303 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 304 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 305 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 306 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 307 }; 308 309 static uint16_t urtw_8225_rxgain[] = { 310 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 311 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 312 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 313 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 314 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 315 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 316 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 317 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 318 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 319 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 320 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 321 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 322 }; 323 324 static uint8_t urtw_8225_threshold[] = { 325 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 326 }; 327 328 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 329 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 330 }; 331 332 static uint8_t urtw_8225_txpwr_cck[] = { 333 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 334 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 335 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 336 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 337 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 338 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 339 }; 340 341 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 342 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 343 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 344 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 345 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 346 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 347 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 348 }; 349 350 static uint8_t urtw_8225_txpwr_ofdm[] = { 351 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 352 }; 353 354 static uint8_t urtw_8225v2_agc[] = { 355 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 356 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 357 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 358 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 359 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 360 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 361 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 362 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 363 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 364 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 365 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 366 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 367 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 368 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 369 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 370 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 371 }; 372 373 static uint8_t urtw_8225v2_ofdm[] = { 374 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 375 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 376 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 377 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 378 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 379 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 380 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 381 0x6d, 0x3c, 0xfb, 0x07 382 }; 383 384 static uint8_t urtw_8225v2_gain_bg[] = { 385 0x23, 0x15, 0xa5, /* -82-1dbm */ 386 0x23, 0x15, 0xb5, /* -82-2dbm */ 387 0x23, 0x15, 0xc5, /* -82-3dbm */ 388 0x33, 0x15, 0xc5, /* -78dbm */ 389 0x43, 0x15, 0xc5, /* -74dbm */ 390 0x53, 0x15, 0xc5, /* -70dbm */ 391 0x63, 0x15, 0xc5, /* -66dbm */ 392 }; 393 394 static struct urtw_pair urtw_8225v2_rf_part1[] = { 395 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 396 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 397 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 398 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 399 }; 400 401 static struct urtw_pair urtw_8225v2_rf_part2[] = { 402 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 403 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 404 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 405 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 406 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 407 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 408 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 409 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 410 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 411 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 412 }; 413 414 static struct urtw_pair urtw_8225v2_rf_part3[] = { 415 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 416 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 417 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 418 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 419 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 420 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 421 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 422 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 423 }; 424 425 static uint16_t urtw_8225v2_rxgain[] = { 426 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 427 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 428 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 429 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 430 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 431 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 432 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 433 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 434 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 435 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 436 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 437 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 438 }; 439 440 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 441 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 442 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 443 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 444 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 445 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 446 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 447 }; 448 449 static uint8_t urtw_8225v2_txpwr_cck[] = { 450 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 451 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 452 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 453 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 454 }; 455 456 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 457 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 458 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 459 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 460 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 461 }; 462 463 static struct urtw_pair urtw_8225v2_b_rf[] = { 464 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 465 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 466 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 467 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 468 { 0x00, 0x01b7 } 469 }; 470 471 static struct urtw_pair urtw_ratetable[] = { 472 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 473 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 474 { 96, 10 }, { 108, 11 } 475 }; 476 477 int urtw_init(struct ifnet *); 478 void urtw_stop(struct ifnet *, int); 479 int urtw_ioctl(struct ifnet *, u_long, void *); 480 void urtw_start(struct ifnet *); 481 int urtw_alloc_rx_data_list(struct urtw_softc *); 482 void urtw_free_rx_data_list(struct urtw_softc *); 483 int urtw_alloc_tx_data_list(struct urtw_softc *); 484 void urtw_free_tx_data_list(struct urtw_softc *); 485 void urtw_rxeof(struct usbd_xfer *, void *, 486 usbd_status); 487 int urtw_tx_start(struct urtw_softc *, 488 struct ieee80211_node *, struct mbuf *, int); 489 void urtw_txeof_low(struct usbd_xfer *, void *, 490 usbd_status); 491 void urtw_txeof_normal(struct usbd_xfer *, void *, 492 usbd_status); 493 void urtw_next_scan(void *); 494 void urtw_task(void *); 495 void urtw_ledusbtask(void *); 496 void urtw_ledtask(void *); 497 int urtw_media_change(struct ifnet *); 498 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 499 void urtw_watchdog(struct ifnet *); 500 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 501 int urtw_isbmode(uint16_t); 502 uint16_t urtw_rate2rtl(int); 503 uint16_t urtw_rtl2rate(int); 504 usbd_status urtw_set_rate(struct urtw_softc *); 505 usbd_status urtw_update_msr(struct urtw_softc *); 506 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 507 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 508 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 509 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 510 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 511 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 512 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 513 usbd_status urtw_eprom_ck(struct urtw_softc *); 514 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 515 int); 516 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 517 uint32_t *); 518 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 519 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 520 usbd_status urtw_get_macaddr(struct urtw_softc *); 521 usbd_status urtw_get_txpwr(struct urtw_softc *); 522 usbd_status urtw_get_rfchip(struct urtw_softc *); 523 usbd_status urtw_led_init(struct urtw_softc *); 524 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 525 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 526 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 527 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 528 uint32_t); 529 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 530 uint32_t); 531 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 532 usbd_status urtw_8225_usb_init(struct urtw_softc *); 533 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 534 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 535 uint16_t); 536 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 537 usbd_status urtw_8225_rf_init(struct urtw_rf *); 538 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 539 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 540 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 541 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 542 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 543 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 544 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 545 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 546 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 547 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 548 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 549 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 550 usbd_status urtw_open_pipes(struct urtw_softc *); 551 usbd_status urtw_close_pipes(struct urtw_softc *); 552 usbd_status urtw_intr_enable(struct urtw_softc *); 553 usbd_status urtw_intr_disable(struct urtw_softc *); 554 usbd_status urtw_reset(struct urtw_softc *); 555 usbd_status urtw_led_on(struct urtw_softc *, int); 556 usbd_status urtw_led_ctl(struct urtw_softc *, int); 557 usbd_status urtw_led_blink(struct urtw_softc *); 558 usbd_status urtw_led_mode0(struct urtw_softc *, int); 559 usbd_status urtw_led_mode1(struct urtw_softc *, int); 560 usbd_status urtw_led_mode2(struct urtw_softc *, int); 561 usbd_status urtw_led_mode3(struct urtw_softc *, int); 562 usbd_status urtw_rx_setconf(struct urtw_softc *); 563 usbd_status urtw_rx_enable(struct urtw_softc *); 564 usbd_status urtw_tx_enable(struct urtw_softc *); 565 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 566 usbd_status urtw_8187b_reset(struct urtw_softc *); 567 int urtw_8187b_init(struct ifnet *); 568 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 569 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 570 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 571 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 572 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 573 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 574 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 575 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 576 577 int urtw_match(device_t, cfdata_t, void *); 578 void urtw_attach(device_t, device_t, void *); 579 int urtw_detach(device_t, int); 580 int urtw_activate(device_t, enum devact); 581 582 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 583 urtw_match, 584 urtw_attach, 585 urtw_detach, 586 urtw_activate 587 ); 588 589 int 590 urtw_match(device_t parent, cfdata_t match, void *aux) 591 { 592 struct usb_attach_arg *uaa = aux; 593 594 return urtw_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 595 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 596 } 597 598 void 599 urtw_attach(device_t parent, device_t self, void *aux) 600 { 601 struct urtw_softc *sc = device_private(self); 602 struct usb_attach_arg *uaa = aux; 603 struct ieee80211com *ic = &sc->sc_ic; 604 struct ifnet *ifp = &sc->sc_if; 605 usbd_status error; 606 uint8_t data8; 607 uint32_t data; 608 int i; 609 610 sc->sc_dev = self; 611 sc->sc_udev = uaa->uaa_device; 612 sc->sc_hwrev = urtw_lookup(uaa->uaa_vendor, uaa->uaa_product)->rev; 613 614 printf(": "); 615 616 if (sc->sc_hwrev & URTW_HWREV_8187) { 617 urtw_read32_m(sc, URTW_TX_CONF, &data); 618 data &= URTW_TX_HWREV_MASK; 619 switch (data) { 620 case URTW_TX_HWREV_8187_D: 621 sc->sc_hwrev |= URTW_HWREV_8187_D; 622 printf("RTL8187 rev D"); 623 break; 624 case URTW_TX_HWREV_8187B_D: 625 /* 626 * Detect Realtek RTL8187B devices that use 627 * USB IDs of RTL8187. 628 */ 629 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 630 printf("RTL8187B rev B (early)"); 631 break; 632 default: 633 sc->sc_hwrev |= URTW_HWREV_8187_B; 634 printf("RTL8187 rev 0x%02x", data >> 25); 635 break; 636 } 637 } else { 638 /* RTL8187B hwrev register. */ 639 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 640 switch (data8) { 641 case URTW_8187B_HWREV_8187B_B: 642 sc->sc_hwrev |= URTW_HWREV_8187B_B; 643 printf("RTL8187B rev B"); 644 break; 645 case URTW_8187B_HWREV_8187B_D: 646 sc->sc_hwrev |= URTW_HWREV_8187B_D; 647 printf("RTL8187B rev D"); 648 break; 649 case URTW_8187B_HWREV_8187B_E: 650 sc->sc_hwrev |= URTW_HWREV_8187B_E; 651 printf("RTL8187B rev E"); 652 break; 653 default: 654 sc->sc_hwrev |= URTW_HWREV_8187B_B; 655 printf("RTL8187B rev 0x%02x", data8); 656 break; 657 } 658 } 659 660 urtw_read32_m(sc, URTW_RX, &data); 661 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 662 URTW_EEPROM_93C46; 663 664 error = urtw_get_rfchip(sc); 665 if (error != 0) 666 goto fail; 667 error = urtw_get_macaddr(sc); 668 if (error != 0) 669 goto fail; 670 error = urtw_get_txpwr(sc); 671 if (error != 0) 672 goto fail; 673 error = urtw_led_init(sc); /* XXX incompleted */ 674 if (error != 0) 675 goto fail; 676 677 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 678 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 679 sc->sc_currate = 3; 680 /* XXX for what? */ 681 sc->sc_preamble_mode = 2; 682 683 usb_init_task(&sc->sc_task, urtw_task, sc, 0); 684 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 0); 685 callout_init(&sc->scan_to, 0); 686 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 687 callout_init(&sc->sc_led_ch, 0); 688 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 689 690 ic->ic_ifp = ifp; 691 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 692 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 693 ic->ic_state = IEEE80211_S_INIT; 694 695 /* set device capabilities */ 696 ic->ic_caps = 697 IEEE80211_C_MONITOR | /* monitor mode supported */ 698 IEEE80211_C_TXPMGT | /* tx power management */ 699 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 700 IEEE80211_C_SHSLOT | /* short slot time supported */ 701 IEEE80211_C_WEP | /* s/w WEP */ 702 IEEE80211_C_WPA; /* WPA/RSN */ 703 704 /* set supported .11b and .11g rates */ 705 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 706 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 707 708 /* set supported .11b and .11g channels (1 through 14) */ 709 for (i = 1; i <= 14; i++) { 710 ic->ic_channels[i].ic_freq = 711 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 712 ic->ic_channels[i].ic_flags = 713 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 714 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 715 } 716 717 ifp->if_softc = sc; 718 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 719 if (sc->sc_hwrev & URTW_HWREV_8187) { 720 ifp->if_init = urtw_init; 721 } else { 722 ifp->if_init = urtw_8187b_init; 723 } 724 ifp->if_ioctl = urtw_ioctl; 725 ifp->if_start = urtw_start; 726 ifp->if_watchdog = urtw_watchdog; 727 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 728 IFQ_SET_READY(&ifp->if_snd); 729 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 730 731 if_attach(ifp); 732 ieee80211_ifattach(ic); 733 734 /* override state transition machine */ 735 sc->sc_newstate = ic->ic_newstate; 736 ic->ic_newstate = urtw_newstate; 737 ieee80211_media_init(ic, urtw_media_change, ieee80211_media_status); 738 739 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 740 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 741 &sc->sc_drvbpf); 742 743 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 744 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 745 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 746 747 sc->sc_txtap_len = sizeof sc->sc_txtapu; 748 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 749 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 750 751 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 752 753 ieee80211_announce(ic); 754 755 return; 756 fail: 757 printf(": %s failed!\n", __func__); 758 sc->sc_dying = true; 759 } 760 761 int 762 urtw_detach(device_t self, int flags) 763 { 764 struct urtw_softc *sc = device_private(self); 765 struct ifnet *ifp = &sc->sc_if; 766 int s; 767 768 s = splusb(); 769 770 sc->sc_dying = true; 771 772 callout_destroy(&sc->scan_to); 773 callout_destroy(&sc->sc_led_ch); 774 775 usb_rem_task(sc->sc_udev, &sc->sc_task); 776 usb_rem_task(sc->sc_udev, &sc->sc_ledtask); 777 778 if (ifp->if_softc != NULL) { 779 bpf_detach(ifp); 780 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 781 if_detach(ifp); 782 } 783 784 /* abort and free xfers */ 785 urtw_free_tx_data_list(sc); 786 urtw_free_rx_data_list(sc); 787 urtw_close_pipes(sc); 788 789 splx(s); 790 791 return 0; 792 } 793 794 int 795 urtw_activate(device_t self, enum devact act) 796 { 797 struct urtw_softc *sc = device_private(self); 798 799 switch (act) { 800 case DVACT_DEACTIVATE: 801 sc->sc_dying = true; 802 break; 803 } 804 805 return 0; 806 } 807 808 usbd_status 809 urtw_close_pipes(struct urtw_softc *sc) 810 { 811 usbd_status error = 0; 812 813 if (sc->sc_rxpipe != NULL) { 814 error = usbd_close_pipe(sc->sc_rxpipe); 815 if (error != 0) 816 goto fail; 817 sc->sc_rxpipe = NULL; 818 } 819 if (sc->sc_txpipe_low != NULL) { 820 error = usbd_close_pipe(sc->sc_txpipe_low); 821 if (error != 0) 822 goto fail; 823 sc->sc_txpipe_low = NULL; 824 } 825 if (sc->sc_txpipe_normal != NULL) { 826 error = usbd_close_pipe(sc->sc_txpipe_normal); 827 if (error != 0) 828 goto fail; 829 sc->sc_txpipe_normal = NULL; 830 } 831 fail: 832 return error; 833 } 834 835 usbd_status 836 urtw_open_pipes(struct urtw_softc *sc) 837 { 838 usbd_status error; 839 840 /* 841 * NB: there is no way to distinguish each pipes so we need to hardcode 842 * pipe numbers 843 */ 844 845 /* tx pipe - low priority packets */ 846 if (sc->sc_hwrev & URTW_HWREV_8187) 847 error = usbd_open_pipe(sc->sc_iface, 0x2, 848 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 849 else 850 error = usbd_open_pipe(sc->sc_iface, 0x6, 851 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 852 if (error != 0) { 853 printf("%s: could not open Tx low pipe: %s\n", 854 device_xname(sc->sc_dev), usbd_errstr(error)); 855 goto fail; 856 } 857 /* tx pipe - normal priority packets */ 858 if (sc->sc_hwrev & URTW_HWREV_8187) 859 error = usbd_open_pipe(sc->sc_iface, 0x3, 860 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 861 else 862 error = usbd_open_pipe(sc->sc_iface, 0x7, 863 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 864 if (error != 0) { 865 printf("%s: could not open Tx normal pipe: %s\n", 866 device_xname(sc->sc_dev), usbd_errstr(error)); 867 goto fail; 868 } 869 /* rx pipe */ 870 if (sc->sc_hwrev & URTW_HWREV_8187) 871 error = usbd_open_pipe(sc->sc_iface, 0x81, 872 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 873 else 874 error = usbd_open_pipe(sc->sc_iface, 0x83, 875 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 876 if (error != 0) { 877 printf("%s: could not open Rx pipe: %s\n", 878 device_xname(sc->sc_dev), usbd_errstr(error)); 879 goto fail; 880 } 881 882 return 0; 883 fail: 884 (void)urtw_close_pipes(sc); 885 return error; 886 } 887 888 int 889 urtw_alloc_rx_data_list(struct urtw_softc *sc) 890 { 891 int i, error; 892 893 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 894 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 895 896 data->sc = sc; 897 898 data->xfer = usbd_alloc_xfer(sc->sc_udev); 899 if (data->xfer == NULL) { 900 printf("%s: could not allocate rx xfer\n", 901 device_xname(sc->sc_dev)); 902 error = ENOMEM; 903 goto fail; 904 } 905 906 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 907 printf("%s: could not allocate rx buffer\n", 908 device_xname(sc->sc_dev)); 909 error = ENOMEM; 910 goto fail; 911 } 912 913 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 914 if (data->m == NULL) { 915 printf("%s: could not allocate rx mbuf\n", 916 device_xname(sc->sc_dev)); 917 error = ENOMEM; 918 goto fail; 919 } 920 MCLGET(data->m, M_DONTWAIT); 921 if (!(data->m->m_flags & M_EXT)) { 922 printf("%s: could not allocate rx mbuf cluster\n", 923 device_xname(sc->sc_dev)); 924 error = ENOMEM; 925 goto fail; 926 } 927 data->buf = mtod(data->m, uint8_t *); 928 } 929 930 return 0; 931 932 fail: 933 urtw_free_rx_data_list(sc); 934 return error; 935 } 936 937 void 938 urtw_free_rx_data_list(struct urtw_softc *sc) 939 { 940 int i; 941 942 /* Make sure no transfers are pending. */ 943 if (sc->sc_rxpipe != NULL) 944 usbd_abort_pipe(sc->sc_rxpipe); 945 946 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 947 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 948 949 if (data->xfer != NULL) { 950 usbd_free_xfer(data->xfer); 951 data->xfer = NULL; 952 } 953 if (data->m != NULL) { 954 m_freem(data->m); 955 data->m = NULL; 956 } 957 } 958 } 959 960 int 961 urtw_alloc_tx_data_list(struct urtw_softc *sc) 962 { 963 int i, error; 964 965 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 966 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 967 968 data->sc = sc; 969 data->ni = NULL; 970 971 data->xfer = usbd_alloc_xfer(sc->sc_udev); 972 if (data->xfer == NULL) { 973 printf("%s: could not allocate tx xfer\n", 974 device_xname(sc->sc_dev)); 975 error = ENOMEM; 976 goto fail; 977 } 978 979 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 980 if (data->buf == NULL) { 981 printf("%s: could not allocate tx buffer\n", 982 device_xname(sc->sc_dev)); 983 error = ENOMEM; 984 goto fail; 985 } 986 987 if (((unsigned long)data->buf) % 4) 988 printf("%s: warn: unaligned buffer %p\n", 989 device_xname(sc->sc_dev), data->buf); 990 } 991 992 return 0; 993 994 fail: 995 urtw_free_tx_data_list(sc); 996 return error; 997 } 998 999 void 1000 urtw_free_tx_data_list(struct urtw_softc *sc) 1001 { 1002 int i; 1003 1004 /* Make sure no transfers are pending. */ 1005 if (sc->sc_txpipe_low != NULL) 1006 usbd_abort_pipe(sc->sc_txpipe_low); 1007 if (sc->sc_txpipe_normal != NULL) 1008 usbd_abort_pipe(sc->sc_txpipe_normal); 1009 1010 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1011 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 1012 1013 if (data->xfer != NULL) { 1014 usbd_free_xfer(data->xfer); 1015 data->xfer = NULL; 1016 } 1017 if (data->ni != NULL) { 1018 ieee80211_free_node(data->ni); 1019 data->ni = NULL; 1020 } 1021 } 1022 } 1023 1024 int 1025 urtw_media_change(struct ifnet *ifp) 1026 { 1027 int error; 1028 1029 error = ieee80211_media_change(ifp); 1030 if (error != ENETRESET) 1031 return error; 1032 1033 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1034 (IFF_UP | IFF_RUNNING)) 1035 ifp->if_init(ifp); 1036 1037 return 0; 1038 } 1039 1040 int 1041 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1042 { 1043 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1044 1045 usb_rem_task(sc->sc_udev, &sc->sc_task); 1046 callout_stop(&sc->scan_to); 1047 1048 /* do it in a process context */ 1049 sc->sc_state = nstate; 1050 sc->sc_arg = arg; 1051 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1052 1053 return 0; 1054 } 1055 1056 usbd_status 1057 urtw_led_init(struct urtw_softc *sc) 1058 { 1059 uint32_t rev; 1060 usbd_status error; 1061 1062 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1063 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1064 if (error != 0) 1065 goto fail; 1066 1067 switch (rev & URTW_EPROM_CID_MASK) { 1068 case URTW_EPROM_CID_ALPHA0: 1069 sc->sc_strategy = URTW_SW_LED_MODE1; 1070 break; 1071 case URTW_EPROM_CID_SERCOMM_PS: 1072 sc->sc_strategy = URTW_SW_LED_MODE3; 1073 break; 1074 case URTW_EPROM_CID_HW_LED: 1075 sc->sc_strategy = URTW_HW_LED; 1076 break; 1077 case URTW_EPROM_CID_RSVD0: 1078 case URTW_EPROM_CID_RSVD1: 1079 default: 1080 sc->sc_strategy = URTW_SW_LED_MODE0; 1081 break; 1082 } 1083 1084 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1085 1086 fail: 1087 return error; 1088 } 1089 1090 usbd_status 1091 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1092 uint16_t data) 1093 { 1094 usb_device_request_t req; 1095 1096 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1097 req.bRequest = URTW_8187_SETREGS_REQ; 1098 USETW(req.wValue, addr); 1099 USETW(req.wIndex, index); 1100 USETW(req.wLength, sizeof(uint16_t)); 1101 1102 return usbd_do_request(sc->sc_udev, &req, &data); 1103 } 1104 1105 usbd_status 1106 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1107 { 1108 int i; 1109 int16_t bit; 1110 uint8_t rlen = 12, wlen = 6; 1111 uint16_t o1, o2, o3, tmp; 1112 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1113 uint32_t mask = 0x80000000, value = 0; 1114 usbd_status error; 1115 1116 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1117 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1118 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1119 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1120 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1121 o1 &= ~0xf; 1122 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1123 DELAY(5); 1124 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1125 DELAY(5); 1126 1127 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1128 bit = ((d2w & mask) != 0) ? 1 : 0; 1129 1130 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1131 DELAY(2); 1132 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1133 URTW_BB_HOST_BANG_CLK); 1134 DELAY(2); 1135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1136 URTW_BB_HOST_BANG_CLK); 1137 DELAY(2); 1138 mask = mask >> 1; 1139 if (i == 2) 1140 break; 1141 bit = ((d2w & mask) != 0) ? 1 : 0; 1142 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1143 URTW_BB_HOST_BANG_CLK); 1144 DELAY(2); 1145 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1146 URTW_BB_HOST_BANG_CLK); 1147 DELAY(2); 1148 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1149 DELAY(1); 1150 } 1151 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1152 URTW_BB_HOST_BANG_CLK); 1153 DELAY(2); 1154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1155 DELAY(2); 1156 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1157 DELAY(2); 1158 1159 mask = 0x800; 1160 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1161 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1162 o1 | URTW_BB_HOST_BANG_RW); 1163 DELAY(2); 1164 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1165 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1166 DELAY(2); 1167 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1168 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1169 DELAY(2); 1170 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1171 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1172 DELAY(2); 1173 1174 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1175 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1176 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1177 o1 | URTW_BB_HOST_BANG_RW); 1178 DELAY(2); 1179 } 1180 1181 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1182 URTW_BB_HOST_BANG_RW); 1183 DELAY(2); 1184 1185 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1186 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1187 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1188 1189 if (data != NULL) 1190 *data = value; 1191 fail: 1192 return error; 1193 } 1194 1195 usbd_status 1196 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1197 { 1198 uint16_t d80, d82, d84; 1199 usbd_status error; 1200 1201 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1202 d80 &= 0xfff3; 1203 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1204 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1205 d84 &= 0xfff0; 1206 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1207 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1208 DELAY(10); 1209 1210 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1211 DELAY(2); 1212 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1213 DELAY(10); 1214 1215 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1216 if (error != 0) 1217 goto fail; 1218 1219 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1220 DELAY(10); 1221 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1222 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1223 usbd_delay_ms(sc->sc_udev, 2); 1224 fail: 1225 return error; 1226 } 1227 1228 usbd_status 1229 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1230 { 1231 uint32_t data; 1232 usbd_status error; 1233 1234 *ret = 1; 1235 1236 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1237 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1238 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1239 usbd_delay_ms(sc->sc_udev, 500); 1240 1241 urtw_8225_write(sc, 0x0, 0x1b7); 1242 1243 error = urtw_8225_read(sc, 0x8, &data); 1244 if (error != 0) 1245 goto fail; 1246 if (data != 0x588) 1247 *ret = 0; 1248 else { 1249 error = urtw_8225_read(sc, 0x9, &data); 1250 if (error != 0) 1251 goto fail; 1252 if (data != 0x700) 1253 *ret = 0; 1254 } 1255 1256 urtw_8225_write(sc, 0x0, 0xb7); 1257 fail: 1258 return error; 1259 } 1260 1261 usbd_status 1262 urtw_get_rfchip(struct urtw_softc *sc) 1263 { 1264 struct urtw_rf *rf = &sc->sc_rf; 1265 int ret; 1266 uint32_t data; 1267 usbd_status error; 1268 1269 rf->rf_sc = sc; 1270 1271 if (sc->sc_hwrev & URTW_HWREV_8187) { 1272 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1273 if (error != 0) 1274 panic("unsupported RF chip"); 1275 /* NOTREACHED */ 1276 switch (data & 0xff) { 1277 case URTW_EPROM_RFCHIPID_RTL8225U: 1278 error = urtw_8225_isv2(sc, &ret); 1279 if (error != 0) 1280 goto fail; 1281 if (ret == 0) { 1282 rf->init = urtw_8225_rf_init; 1283 rf->set_chan = urtw_8225_rf_set_chan; 1284 rf->set_sens = urtw_8225_rf_set_sens; 1285 printf(", RFv1"); 1286 } else { 1287 rf->init = urtw_8225v2_rf_init; 1288 rf->set_chan = urtw_8225v2_rf_set_chan; 1289 rf->set_sens = NULL; 1290 printf(", RFv2"); 1291 } 1292 break; 1293 default: 1294 goto fail; 1295 } 1296 } else { 1297 rf->init = urtw_8225v2_b_rf_init; 1298 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1299 rf->set_sens = NULL; 1300 } 1301 1302 rf->max_sens = URTW_8225_RF_MAX_SENS; 1303 rf->sens = URTW_8225_RF_DEF_SENS; 1304 1305 return 0; 1306 1307 fail: 1308 panic("unsupported RF chip %d", data & 0xff); 1309 /* NOTREACHED */ 1310 } 1311 1312 usbd_status 1313 urtw_get_txpwr(struct urtw_softc *sc) 1314 { 1315 int i, j; 1316 uint32_t data; 1317 usbd_status error; 1318 1319 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1320 if (error != 0) 1321 goto fail; 1322 sc->sc_txpwr_cck_base = data & 0xf; 1323 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1324 1325 for (i = 1, j = 0; i < 6; i += 2, j++) { 1326 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1327 if (error != 0) 1328 goto fail; 1329 sc->sc_txpwr_cck[i] = data & 0xf; 1330 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1331 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1332 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1333 } 1334 for (i = 1, j = 0; i < 4; i += 2, j++) { 1335 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1336 if (error != 0) 1337 goto fail; 1338 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1339 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1340 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1341 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1342 } 1343 if (sc->sc_hwrev & URTW_HWREV_8187) { 1344 for (i = 1, j = 0; i < 4; i += 2, j++) { 1345 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1346 &data); 1347 if (error != 0) 1348 goto fail; 1349 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1350 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1351 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1352 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1353 (data & 0xf000) >> 12; 1354 } 1355 } else { 1356 /* Channel 11. */ 1357 error = urtw_eprom_read32(sc, 0x1b, &data); 1358 if (error != 0) 1359 goto fail; 1360 sc->sc_txpwr_cck[11] = data & 0xf; 1361 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1362 1363 /* Channel 12. */ 1364 error = urtw_eprom_read32(sc, 0xa, &data); 1365 if (error != 0) 1366 goto fail; 1367 sc->sc_txpwr_cck[12] = data & 0xf; 1368 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1369 1370 /* Channel 13, 14. */ 1371 error = urtw_eprom_read32(sc, 0x1c, &data); 1372 if (error != 0) 1373 goto fail; 1374 sc->sc_txpwr_cck[13] = data & 0xf; 1375 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1376 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1377 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1378 } 1379 fail: 1380 return error; 1381 } 1382 1383 usbd_status 1384 urtw_get_macaddr(struct urtw_softc *sc) 1385 { 1386 struct ieee80211com *ic = &sc->sc_ic; 1387 usbd_status error; 1388 uint32_t data; 1389 1390 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1391 if (error != 0) 1392 goto fail; 1393 ic->ic_myaddr[0] = data & 0xff; 1394 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1395 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1396 if (error != 0) 1397 goto fail; 1398 ic->ic_myaddr[2] = data & 0xff; 1399 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1400 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1401 if (error != 0) 1402 goto fail; 1403 ic->ic_myaddr[4] = data & 0xff; 1404 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1405 fail: 1406 return error; 1407 } 1408 1409 usbd_status 1410 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1411 { 1412 #define URTW_READCMD_LEN 3 1413 int addrlen, i; 1414 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1415 usbd_status error; 1416 1417 /* NB: make sure the buffer is initialized */ 1418 *data = 0; 1419 1420 /* enable EPROM programming */ 1421 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1422 DELAY(URTW_EPROM_DELAY); 1423 1424 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1425 if (error != 0) 1426 goto fail; 1427 error = urtw_eprom_ck(sc); 1428 if (error != 0) 1429 goto fail; 1430 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1431 if (error != 0) 1432 goto fail; 1433 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1434 addrlen = 8; 1435 addrstr[0] = addr & (1 << 7); 1436 addrstr[1] = addr & (1 << 6); 1437 addrstr[2] = addr & (1 << 5); 1438 addrstr[3] = addr & (1 << 4); 1439 addrstr[4] = addr & (1 << 3); 1440 addrstr[5] = addr & (1 << 2); 1441 addrstr[6] = addr & (1 << 1); 1442 addrstr[7] = addr & (1 << 0); 1443 } else { 1444 addrlen=6; 1445 addrstr[0] = addr & (1 << 5); 1446 addrstr[1] = addr & (1 << 4); 1447 addrstr[2] = addr & (1 << 3); 1448 addrstr[3] = addr & (1 << 2); 1449 addrstr[4] = addr & (1 << 1); 1450 addrstr[5] = addr & (1 << 0); 1451 } 1452 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1453 if (error != 0) 1454 goto fail; 1455 1456 error = urtw_eprom_writebit(sc, 0); 1457 if (error != 0) 1458 goto fail; 1459 1460 for (i = 0; i < 16; i++) { 1461 error = urtw_eprom_ck(sc); 1462 if (error != 0) 1463 goto fail; 1464 error = urtw_eprom_readbit(sc, &data16); 1465 if (error != 0) 1466 goto fail; 1467 1468 (*data) |= (data16 << (15 - i)); 1469 } 1470 1471 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1472 if (error != 0) 1473 goto fail; 1474 error = urtw_eprom_ck(sc); 1475 if (error != 0) 1476 goto fail; 1477 1478 /* now disable EPROM programming */ 1479 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1480 fail: 1481 return error; 1482 #undef URTW_READCMD_LEN 1483 } 1484 1485 usbd_status 1486 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1487 { 1488 uint8_t data8; 1489 usbd_status error; 1490 1491 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1492 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1493 DELAY(URTW_EPROM_DELAY); 1494 1495 fail: 1496 return error; 1497 } 1498 1499 usbd_status 1500 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1501 { 1502 int i = 0; 1503 usbd_status error = 0; 1504 1505 for (i = 0; i < buflen; i++) { 1506 error = urtw_eprom_writebit(sc, buf[i]); 1507 if (error != 0) 1508 goto fail; 1509 error = urtw_eprom_ck(sc); 1510 if (error != 0) 1511 goto fail; 1512 } 1513 fail: 1514 return error; 1515 } 1516 1517 usbd_status 1518 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1519 { 1520 uint8_t data; 1521 usbd_status error; 1522 1523 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1524 if (bit != 0) 1525 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1526 else 1527 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1528 DELAY(URTW_EPROM_DELAY); 1529 fail: 1530 return error; 1531 } 1532 1533 usbd_status 1534 urtw_eprom_ck(struct urtw_softc *sc) 1535 { 1536 uint8_t data; 1537 usbd_status error; 1538 1539 /* masking */ 1540 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1541 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1542 DELAY(URTW_EPROM_DELAY); 1543 /* unmasking */ 1544 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1545 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1546 DELAY(URTW_EPROM_DELAY); 1547 fail: 1548 return error; 1549 } 1550 1551 usbd_status 1552 urtw_eprom_cs(struct urtw_softc *sc, int able) 1553 { 1554 uint8_t data; 1555 usbd_status error; 1556 1557 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1558 if (able == URTW_EPROM_ENABLE) 1559 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1560 else 1561 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1562 DELAY(URTW_EPROM_DELAY); 1563 fail: 1564 return error; 1565 } 1566 1567 usbd_status 1568 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1569 { 1570 usb_device_request_t req; 1571 usbd_status error; 1572 1573 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1574 req.bRequest = URTW_8187_GETREGS_REQ; 1575 USETW(req.wValue, val | 0xff00); 1576 USETW(req.wIndex, idx & 0x03); 1577 USETW(req.wLength, sizeof(uint8_t)); 1578 1579 error = usbd_do_request(sc->sc_udev, &req, data); 1580 return error; 1581 } 1582 1583 usbd_status 1584 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1585 { 1586 usb_device_request_t req; 1587 usbd_status error; 1588 1589 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1590 req.bRequest = URTW_8187_GETREGS_REQ; 1591 USETW(req.wValue, val | 0xfe00); 1592 USETW(req.wIndex, 0); 1593 USETW(req.wLength, sizeof(uint8_t)); 1594 1595 error = usbd_do_request(sc->sc_udev, &req, data); 1596 return error; 1597 } 1598 1599 usbd_status 1600 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1601 { 1602 usb_device_request_t req; 1603 usbd_status error; 1604 1605 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1606 req.bRequest = URTW_8187_GETREGS_REQ; 1607 USETW(req.wValue, val | 0xff00); 1608 USETW(req.wIndex, idx & 0x03); 1609 USETW(req.wLength, sizeof(uint16_t)); 1610 1611 error = usbd_do_request(sc->sc_udev, &req, data); 1612 return error; 1613 } 1614 1615 usbd_status 1616 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1617 { 1618 usb_device_request_t req; 1619 usbd_status error; 1620 1621 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1622 req.bRequest = URTW_8187_GETREGS_REQ; 1623 USETW(req.wValue, val | 0xff00); 1624 USETW(req.wIndex, idx & 0x03); 1625 USETW(req.wLength, sizeof(uint32_t)); 1626 1627 error = usbd_do_request(sc->sc_udev, &req, data); 1628 return error; 1629 } 1630 1631 usbd_status 1632 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1633 { 1634 usb_device_request_t req; 1635 1636 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1637 req.bRequest = URTW_8187_SETREGS_REQ; 1638 USETW(req.wValue, val | 0xff00); 1639 USETW(req.wIndex, idx & 0x03); 1640 USETW(req.wLength, sizeof(uint8_t)); 1641 1642 return usbd_do_request(sc->sc_udev, &req, &data); 1643 } 1644 1645 usbd_status 1646 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1647 { 1648 usb_device_request_t req; 1649 1650 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1651 req.bRequest = URTW_8187_SETREGS_REQ; 1652 USETW(req.wValue, val | 0xfe00); 1653 USETW(req.wIndex, 0); 1654 USETW(req.wLength, sizeof(uint8_t)); 1655 1656 return usbd_do_request(sc->sc_udev, &req, &data); 1657 } 1658 1659 usbd_status 1660 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1661 { 1662 usb_device_request_t req; 1663 1664 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1665 req.bRequest = URTW_8187_SETREGS_REQ; 1666 USETW(req.wValue, val | 0xff00); 1667 USETW(req.wIndex, idx & 0x03); 1668 USETW(req.wLength, sizeof(uint16_t)); 1669 1670 return usbd_do_request(sc->sc_udev, &req, &data); 1671 } 1672 1673 usbd_status 1674 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1675 { 1676 usb_device_request_t req; 1677 1678 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1679 req.bRequest = URTW_8187_SETREGS_REQ; 1680 USETW(req.wValue, val | 0xff00); 1681 USETW(req.wIndex, idx & 0x03); 1682 USETW(req.wLength, sizeof(uint32_t)); 1683 1684 return usbd_do_request(sc->sc_udev, &req, &data); 1685 } 1686 1687 static usbd_status 1688 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1689 { 1690 uint8_t data; 1691 usbd_status error; 1692 1693 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1694 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1695 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1696 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1697 fail: 1698 return error; 1699 } 1700 1701 usbd_status 1702 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1703 { 1704 uint8_t data; 1705 usbd_status error; 1706 1707 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1708 if (error) 1709 goto fail; 1710 1711 urtw_read8_m(sc, URTW_CONFIG3, &data); 1712 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1713 urtw_write32_m(sc, URTW_ANAPARAM, val); 1714 urtw_read8_m(sc, URTW_CONFIG3, &data); 1715 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1716 1717 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1718 if (error) 1719 goto fail; 1720 fail: 1721 return error; 1722 } 1723 1724 usbd_status 1725 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1726 { 1727 uint8_t data; 1728 usbd_status error; 1729 1730 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1731 if (error) 1732 goto fail; 1733 1734 urtw_read8_m(sc, URTW_CONFIG3, &data); 1735 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1736 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1737 urtw_read8_m(sc, URTW_CONFIG3, &data); 1738 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1739 1740 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1741 if (error) 1742 goto fail; 1743 fail: 1744 return error; 1745 } 1746 1747 usbd_status 1748 urtw_intr_disable(struct urtw_softc *sc) 1749 { 1750 usbd_status error; 1751 1752 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1753 1754 fail: 1755 return error; 1756 } 1757 1758 usbd_status 1759 urtw_reset(struct urtw_softc *sc) 1760 { 1761 uint8_t data; 1762 usbd_status error; 1763 1764 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1765 if (error) 1766 goto fail; 1767 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1768 if (error) 1769 goto fail; 1770 1771 error = urtw_intr_disable(sc); 1772 if (error) 1773 goto fail; 1774 usbd_delay_ms(sc->sc_udev, 100); 1775 1776 error = urtw_write8e(sc, 0x18, 0x10); 1777 if (error != 0) 1778 goto fail; 1779 error = urtw_write8e(sc, 0x18, 0x11); 1780 if (error != 0) 1781 goto fail; 1782 error = urtw_write8e(sc, 0x18, 0x00); 1783 if (error != 0) 1784 goto fail; 1785 usbd_delay_ms(sc->sc_udev, 100); 1786 1787 urtw_read8_m(sc, URTW_CMD, &data); 1788 data = (data & 2) | URTW_CMD_RST; 1789 urtw_write8_m(sc, URTW_CMD, data); 1790 usbd_delay_ms(sc->sc_udev, 100); 1791 1792 urtw_read8_m(sc, URTW_CMD, &data); 1793 if (data & URTW_CMD_RST) { 1794 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1795 goto fail; 1796 } 1797 1798 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1799 if (error) 1800 goto fail; 1801 usbd_delay_ms(sc->sc_udev, 100); 1802 1803 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1804 if (error) 1805 goto fail; 1806 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1807 if (error) 1808 goto fail; 1809 fail: 1810 return error; 1811 } 1812 1813 usbd_status 1814 urtw_led_on(struct urtw_softc *sc, int type) 1815 { 1816 usbd_status error; 1817 1818 if (type == URTW_LED_GPIO) { 1819 switch (sc->sc_gpio_ledpin) { 1820 case URTW_LED_PIN_GPIO0: 1821 urtw_write8_m(sc, URTW_GPIO, 0x01); 1822 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1823 break; 1824 default: 1825 panic("unsupported LED PIN type 0x%x", 1826 sc->sc_gpio_ledpin); 1827 /* NOTREACHED */ 1828 } 1829 } else { 1830 panic("unsupported LED type 0x%x", type); 1831 /* NOTREACHED */ 1832 } 1833 1834 sc->sc_gpio_ledon = 1; 1835 fail: 1836 return error; 1837 } 1838 1839 static usbd_status 1840 urtw_led_off(struct urtw_softc *sc, int type) 1841 { 1842 usbd_status error; 1843 1844 if (type == URTW_LED_GPIO) { 1845 switch (sc->sc_gpio_ledpin) { 1846 case URTW_LED_PIN_GPIO0: 1847 urtw_write8_m(sc, URTW_GPIO, 0x01); 1848 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1849 break; 1850 default: 1851 panic("unsupported LED PIN type 0x%x", 1852 sc->sc_gpio_ledpin); 1853 /* NOTREACHED */ 1854 } 1855 } else { 1856 panic("unsupported LED type 0x%x", type); 1857 /* NOTREACHED */ 1858 } 1859 1860 sc->sc_gpio_ledon = 0; 1861 1862 fail: 1863 return error; 1864 } 1865 1866 usbd_status 1867 urtw_led_mode0(struct urtw_softc *sc, int mode) 1868 { 1869 switch (mode) { 1870 case URTW_LED_CTL_POWER_ON: 1871 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1872 break; 1873 case URTW_LED_CTL_TX: 1874 if (sc->sc_gpio_ledinprogress == 1) 1875 return 0; 1876 1877 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1878 sc->sc_gpio_blinktime = 2; 1879 break; 1880 case URTW_LED_CTL_LINK: 1881 sc->sc_gpio_ledstate = URTW_LED_ON; 1882 break; 1883 default: 1884 panic("unsupported LED mode 0x%x", mode); 1885 /* NOTREACHED */ 1886 } 1887 1888 switch (sc->sc_gpio_ledstate) { 1889 case URTW_LED_ON: 1890 if (sc->sc_gpio_ledinprogress != 0) 1891 break; 1892 urtw_led_on(sc, URTW_LED_GPIO); 1893 break; 1894 case URTW_LED_BLINK_NORMAL: 1895 if (sc->sc_gpio_ledinprogress != 0) 1896 break; 1897 sc->sc_gpio_ledinprogress = 1; 1898 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1899 URTW_LED_OFF : URTW_LED_ON; 1900 if (!sc->sc_dying) 1901 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1902 break; 1903 case URTW_LED_POWER_ON_BLINK: 1904 urtw_led_on(sc, URTW_LED_GPIO); 1905 usbd_delay_ms(sc->sc_udev, 100); 1906 urtw_led_off(sc, URTW_LED_GPIO); 1907 break; 1908 default: 1909 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 1910 /* NOTREACHED */ 1911 } 1912 return 0; 1913 } 1914 1915 usbd_status 1916 urtw_led_mode1(struct urtw_softc *sc, int mode) 1917 { 1918 return USBD_INVAL; 1919 } 1920 1921 usbd_status 1922 urtw_led_mode2(struct urtw_softc *sc, int mode) 1923 { 1924 return USBD_INVAL; 1925 } 1926 1927 usbd_status 1928 urtw_led_mode3(struct urtw_softc *sc, int mode) 1929 { 1930 return USBD_INVAL; 1931 } 1932 1933 void 1934 urtw_ledusbtask(void *arg) 1935 { 1936 struct urtw_softc *sc = arg; 1937 1938 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1939 panic("could not process a LED strategy 0x%x", sc->sc_strategy); 1940 1941 urtw_led_blink(sc); 1942 } 1943 1944 void 1945 urtw_ledtask(void *arg) 1946 { 1947 struct urtw_softc *sc = arg; 1948 1949 /* 1950 * NB: to change a status of the led we need at least a sleep so we 1951 * can't do it here 1952 */ 1953 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1954 } 1955 1956 usbd_status 1957 urtw_led_ctl(struct urtw_softc *sc, int mode) 1958 { 1959 usbd_status error = 0; 1960 1961 switch (sc->sc_strategy) { 1962 case URTW_SW_LED_MODE0: 1963 error = urtw_led_mode0(sc, mode); 1964 break; 1965 case URTW_SW_LED_MODE1: 1966 error = urtw_led_mode1(sc, mode); 1967 break; 1968 case URTW_SW_LED_MODE2: 1969 error = urtw_led_mode2(sc, mode); 1970 break; 1971 case URTW_SW_LED_MODE3: 1972 error = urtw_led_mode3(sc, mode); 1973 break; 1974 default: 1975 panic("unsupported LED mode %d", sc->sc_strategy); 1976 /* NOTREACHED */ 1977 } 1978 1979 return error; 1980 } 1981 1982 usbd_status 1983 urtw_led_blink(struct urtw_softc *sc) 1984 { 1985 uint8_t ing = 0; 1986 1987 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1988 (void)urtw_led_on(sc, URTW_LED_GPIO); 1989 else 1990 (void)urtw_led_off(sc, URTW_LED_GPIO); 1991 sc->sc_gpio_blinktime--; 1992 if (sc->sc_gpio_blinktime == 0) 1993 ing = 1; 1994 else { 1995 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1996 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1997 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 1998 ing = 1; 1999 } 2000 if (ing == 1) { 2001 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2002 sc->sc_gpio_ledon == 0) 2003 (void)urtw_led_on(sc, URTW_LED_GPIO); 2004 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2005 sc->sc_gpio_ledon == 1) 2006 (void)urtw_led_off(sc, URTW_LED_GPIO); 2007 2008 sc->sc_gpio_blinktime = 0; 2009 sc->sc_gpio_ledinprogress = 0; 2010 return 0; 2011 } 2012 2013 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2014 URTW_LED_ON : URTW_LED_OFF; 2015 2016 switch (sc->sc_gpio_ledstate) { 2017 case URTW_LED_BLINK_NORMAL: 2018 if (!sc->sc_dying) 2019 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2020 break; 2021 default: 2022 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate); 2023 /* NOTREACHED */ 2024 } 2025 return 0; 2026 } 2027 2028 usbd_status 2029 urtw_update_msr(struct urtw_softc *sc) 2030 { 2031 struct ieee80211com *ic = &sc->sc_ic; 2032 uint8_t data; 2033 usbd_status error; 2034 2035 urtw_read8_m(sc, URTW_MSR, &data); 2036 data &= ~URTW_MSR_LINK_MASK; 2037 2038 /* Should always be set. */ 2039 if (sc->sc_hwrev & URTW_HWREV_8187B) 2040 data |= URTW_MSR_LINK_ENEDCA; 2041 2042 if (sc->sc_state == IEEE80211_S_RUN) { 2043 switch (ic->ic_opmode) { 2044 case IEEE80211_M_STA: 2045 case IEEE80211_M_MONITOR: 2046 data |= URTW_MSR_LINK_STA; 2047 break; 2048 default: 2049 panic("unsupported operation mode 0x%x", 2050 ic->ic_opmode); 2051 /* NOTREACHED */ 2052 } 2053 } else 2054 data |= URTW_MSR_LINK_NONE; 2055 2056 urtw_write8_m(sc, URTW_MSR, data); 2057 fail: 2058 return error; 2059 } 2060 2061 uint16_t 2062 urtw_rate2rtl(int rate) 2063 { 2064 unsigned int i; 2065 2066 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2067 if (rate == urtw_ratetable[i].reg) 2068 return urtw_ratetable[i].val; 2069 } 2070 2071 return 3; 2072 } 2073 2074 uint16_t 2075 urtw_rtl2rate(int rate) 2076 { 2077 unsigned int i; 2078 2079 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2080 if (rate == urtw_ratetable[i].val) 2081 return urtw_ratetable[i].reg; 2082 } 2083 2084 return 0; 2085 } 2086 2087 usbd_status 2088 urtw_set_rate(struct urtw_softc *sc) 2089 { 2090 int i, basic_rate, min_rr_rate, max_rr_rate; 2091 uint16_t data; 2092 usbd_status error; 2093 2094 basic_rate = urtw_rate2rtl(48); 2095 min_rr_rate = urtw_rate2rtl(12); 2096 max_rr_rate = urtw_rate2rtl(48); 2097 2098 urtw_write8_m(sc, URTW_RESP_RATE, 2099 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2100 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2101 2102 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2103 data &= ~URTW_BRSR_MBR_8185; 2104 2105 for (i = 0; i <= basic_rate; i++) 2106 data |= (1 << i); 2107 2108 urtw_write16_m(sc, URTW_8187_BRSR, data); 2109 fail: 2110 return error; 2111 } 2112 2113 usbd_status 2114 urtw_intr_enable(struct urtw_softc *sc) 2115 { 2116 usbd_status error; 2117 2118 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2119 fail: 2120 return error; 2121 } 2122 2123 usbd_status 2124 urtw_rx_setconf(struct urtw_softc *sc) 2125 { 2126 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2127 struct ieee80211com *ic = &sc->sc_ic; 2128 uint32_t data; 2129 usbd_status error; 2130 2131 urtw_read32_m(sc, URTW_RX, &data); 2132 data = data &~ URTW_RX_FILTER_MASK; 2133 #if 0 2134 data = data | URTW_RX_FILTER_CTL; 2135 #endif 2136 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2137 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2138 2139 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2140 data = data | URTW_RX_FILTER_ICVERR; 2141 data = data | URTW_RX_FILTER_PWR; 2142 } 2143 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2144 data = data | URTW_RX_FILTER_CRCERR; 2145 2146 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2147 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2148 data = data | URTW_RX_FILTER_ALLMAC; 2149 } else { 2150 data = data | URTW_RX_FILTER_NICMAC; 2151 data = data | URTW_RX_CHECK_BSSID; 2152 } 2153 2154 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2155 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2156 data = data &~ URTW_MAX_RX_DMA_MASK; 2157 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2158 2159 urtw_write32_m(sc, URTW_RX, data); 2160 fail: 2161 return error; 2162 } 2163 2164 usbd_status 2165 urtw_rx_enable(struct urtw_softc *sc) 2166 { 2167 int i; 2168 struct urtw_rx_data *rx_data; 2169 uint8_t data; 2170 usbd_status error; 2171 2172 /* 2173 * Start up the receive pipe. 2174 */ 2175 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2176 rx_data = &sc->sc_rx_data[i]; 2177 2178 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2179 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2180 USBD_NO_TIMEOUT, urtw_rxeof); 2181 error = usbd_transfer(rx_data->xfer); 2182 if (error != USBD_IN_PROGRESS && error != 0) { 2183 printf("%s: could not queue Rx transfer\n", 2184 device_xname(sc->sc_dev)); 2185 goto fail; 2186 } 2187 } 2188 2189 error = urtw_rx_setconf(sc); 2190 if (error != 0) 2191 goto fail; 2192 2193 urtw_read8_m(sc, URTW_CMD, &data); 2194 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2195 fail: 2196 return error; 2197 } 2198 2199 usbd_status 2200 urtw_tx_enable(struct urtw_softc *sc) 2201 { 2202 uint8_t data8; 2203 uint32_t data; 2204 usbd_status error; 2205 2206 if (sc->sc_hwrev & URTW_HWREV_8187) { 2207 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2208 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2209 URTW_CW_CONF_PERPACKET_RETRY); 2210 urtw_write8_m(sc, URTW_CW_CONF, data8); 2211 2212 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2213 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2214 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2215 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2216 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2217 2218 urtw_read32_m(sc, URTW_TX_CONF, &data); 2219 data &= ~URTW_TX_LOOPBACK_MASK; 2220 data |= URTW_TX_LOOPBACK_NONE; 2221 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2222 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2223 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2224 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2225 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2226 data &= ~URTW_TX_SWPLCPLEN; 2227 data |= URTW_TX_NOICV; 2228 urtw_write32_m(sc, URTW_TX_CONF, data); 2229 } else { 2230 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2231 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2232 URTW_TX_LONGRETRY; 2233 urtw_write32_m(sc, URTW_TX_CONF, data); 2234 } 2235 2236 urtw_read8_m(sc, URTW_CMD, &data8); 2237 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2238 fail: 2239 return error; 2240 } 2241 2242 int 2243 urtw_init(struct ifnet *ifp) 2244 { 2245 struct urtw_softc *sc = ifp->if_softc; 2246 struct urtw_rf *rf = &sc->sc_rf; 2247 struct ieee80211com *ic = &sc->sc_ic; 2248 usbd_status error; 2249 2250 urtw_stop(ifp, 0); 2251 2252 error = urtw_reset(sc); 2253 if (error) 2254 goto fail; 2255 2256 urtw_write8_m(sc, 0x85, 0); 2257 urtw_write8_m(sc, URTW_GPIO, 0); 2258 2259 /* for led */ 2260 urtw_write8_m(sc, 0x85, 4); 2261 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2262 if (error != 0) 2263 goto fail; 2264 2265 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2266 if (error) 2267 goto fail; 2268 2269 /* applying MAC address again. */ 2270 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2271 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2272 if (error) 2273 goto fail; 2274 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2275 if (error) 2276 goto fail; 2277 2278 error = urtw_update_msr(sc); 2279 if (error) 2280 goto fail; 2281 2282 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2283 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2284 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2285 error = urtw_set_rate(sc); 2286 if (error != 0) 2287 goto fail; 2288 2289 error = rf->init(rf); 2290 if (error != 0) 2291 goto fail; 2292 if (rf->set_sens != NULL) 2293 rf->set_sens(rf); 2294 2295 urtw_write16_m(sc, 0x5e, 1); 2296 urtw_write16_m(sc, 0xfe, 0x10); 2297 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2298 urtw_write8_m(sc, 0xff, 0x60); 2299 urtw_write16_m(sc, 0x5e, 0); 2300 urtw_write8_m(sc, 0x85, 4); 2301 2302 error = urtw_intr_enable(sc); 2303 if (error != 0) 2304 goto fail; 2305 2306 /* reset softc variables */ 2307 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2308 sc->sc_txtimer = 0; 2309 2310 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2311 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2312 if (error != 0) { 2313 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2314 ", err=%s\n", usbd_errstr(error)); 2315 goto fail; 2316 } 2317 /* get the first interface handle */ 2318 error = usbd_device2interface_handle(sc->sc_udev, 2319 URTW_IFACE_INDEX, &sc->sc_iface); 2320 if (error != 0) { 2321 printf("%s: could not get interface handle\n", 2322 device_xname(sc->sc_dev)); 2323 goto fail; 2324 } 2325 error = urtw_open_pipes(sc); 2326 if (error != 0) 2327 goto fail; 2328 error = urtw_alloc_rx_data_list(sc); 2329 if (error != 0) 2330 goto fail; 2331 error = urtw_alloc_tx_data_list(sc); 2332 if (error != 0) 2333 goto fail; 2334 sc->sc_flags |= URTW_INIT_ONCE; 2335 } 2336 2337 error = urtw_rx_enable(sc); 2338 if (error != 0) 2339 goto fail; 2340 error = urtw_tx_enable(sc); 2341 if (error != 0) 2342 goto fail; 2343 2344 ifp->if_flags &= ~IFF_OACTIVE; 2345 ifp->if_flags |= IFF_RUNNING; 2346 2347 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2348 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2349 else 2350 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2351 2352 return 0; 2353 fail: 2354 return error; 2355 } 2356 2357 int 2358 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2359 { 2360 #define IS_RUNNING(ifp) \ 2361 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2362 2363 struct urtw_softc *sc = ifp->if_softc; 2364 struct ieee80211com *ic = &sc->sc_ic; 2365 int s, error = 0; 2366 2367 if (sc->sc_dying) 2368 return ENXIO; 2369 2370 s = splnet(); 2371 2372 switch (cmd) { 2373 case SIOCSIFFLAGS: 2374 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2375 break; 2376 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2377 case IFF_UP|IFF_RUNNING: 2378 break; 2379 case IFF_UP: 2380 ifp->if_init(ifp); 2381 break; 2382 case IFF_RUNNING: 2383 urtw_stop(ifp, 1); 2384 break; 2385 case 0: 2386 break; 2387 } 2388 break; 2389 2390 case SIOCADDMULTI: 2391 case SIOCDELMULTI: 2392 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2393 error = 0; 2394 break; 2395 2396 default: 2397 error = ieee80211_ioctl(ic, cmd, data); 2398 break; 2399 } 2400 2401 if (error == ENETRESET) { 2402 if (IS_RUNNING(ifp) && 2403 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2404 ifp->if_init(ifp); 2405 error = 0; 2406 } 2407 2408 splx(s); 2409 2410 return error; 2411 #undef IS_RUNNING 2412 } 2413 2414 void 2415 urtw_start(struct ifnet *ifp) 2416 { 2417 struct urtw_softc *sc = ifp->if_softc; 2418 struct ieee80211com *ic = &sc->sc_ic; 2419 struct ieee80211_node *ni; 2420 struct ether_header *eh; 2421 struct mbuf *m0; 2422 2423 /* 2424 * net80211 may still try to send management frames even if the 2425 * IFF_RUNNING flag is not set... 2426 */ 2427 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2428 return; 2429 2430 for (;;) { 2431 IF_POLL(&ic->ic_mgtq, m0); 2432 if (m0 != NULL) { 2433 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2434 sc->sc_tx_normal_queued >= 2435 URTW_TX_DATA_LIST_COUNT) { 2436 ifp->if_flags |= IFF_OACTIVE; 2437 break; 2438 } 2439 IF_DEQUEUE(&ic->ic_mgtq, m0); 2440 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2441 m0->m_pkthdr.rcvif = NULL; 2442 bpf_mtap3(ic->ic_rawbpf, m0); 2443 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2444 != 0) 2445 break; 2446 } else { 2447 if (ic->ic_state != IEEE80211_S_RUN) 2448 break; 2449 IFQ_POLL(&ifp->if_snd, m0); 2450 if (m0 == NULL) 2451 break; 2452 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2453 sc->sc_tx_normal_queued >= 2454 URTW_TX_DATA_LIST_COUNT) { 2455 ifp->if_flags |= IFF_OACTIVE; 2456 break; 2457 } 2458 IFQ_DEQUEUE(&ifp->if_snd, m0); 2459 if (m0->m_len < sizeof(struct ether_header) && 2460 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2461 continue; 2462 2463 eh = mtod(m0, struct ether_header *); 2464 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2465 if (ni == NULL) { 2466 m_freem(m0); 2467 continue; 2468 } 2469 bpf_mtap(ifp, m0); 2470 m0 = ieee80211_encap(ic, m0, ni); 2471 if (m0 == NULL) { 2472 ieee80211_free_node(ni); 2473 continue; 2474 } 2475 bpf_mtap3(ic->ic_rawbpf, m0); 2476 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2477 != 0) { 2478 ieee80211_free_node(ni); 2479 ifp->if_oerrors++; 2480 break; 2481 } 2482 } 2483 sc->sc_txtimer = 5; 2484 ifp->if_timer = 1; 2485 } 2486 } 2487 2488 void 2489 urtw_watchdog(struct ifnet *ifp) 2490 { 2491 struct urtw_softc *sc = ifp->if_softc; 2492 2493 ifp->if_timer = 0; 2494 2495 if (sc->sc_txtimer > 0) { 2496 if (--sc->sc_txtimer == 0) { 2497 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2498 ifp->if_oerrors++; 2499 return; 2500 } 2501 ifp->if_timer = 1; 2502 } 2503 2504 ieee80211_watchdog(&sc->sc_ic); 2505 } 2506 2507 void 2508 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2509 usbd_status status) 2510 { 2511 struct urtw_tx_data *data = priv; 2512 struct urtw_softc *sc = data->sc; 2513 struct ieee80211com *ic = &sc->sc_ic; 2514 struct ifnet *ifp = ic->ic_ifp; 2515 int s; 2516 2517 if (status != USBD_NORMAL_COMPLETION) { 2518 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2519 return; 2520 2521 printf("%s: could not transmit buffer: %s\n", 2522 device_xname(sc->sc_dev), usbd_errstr(status)); 2523 2524 if (status == USBD_STALLED) 2525 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2526 2527 ifp->if_oerrors++; 2528 return; 2529 } 2530 2531 s = splnet(); 2532 2533 ieee80211_free_node(data->ni); 2534 data->ni = NULL; 2535 2536 sc->sc_txtimer = 0; 2537 ifp->if_opackets++; 2538 2539 sc->sc_tx_low_queued--; 2540 ifp->if_flags &= ~IFF_OACTIVE; 2541 urtw_start(ifp); 2542 2543 splx(s); 2544 } 2545 2546 void 2547 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2548 usbd_status status) 2549 { 2550 struct urtw_tx_data *data = priv; 2551 struct urtw_softc *sc = data->sc; 2552 struct ieee80211com *ic = &sc->sc_ic; 2553 struct ifnet *ifp = ic->ic_ifp; 2554 int s; 2555 2556 if (status != USBD_NORMAL_COMPLETION) { 2557 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2558 return; 2559 2560 printf("%s: could not transmit buffer: %s\n", 2561 device_xname(sc->sc_dev), usbd_errstr(status)); 2562 2563 if (status == USBD_STALLED) 2564 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2565 2566 ifp->if_oerrors++; 2567 return; 2568 } 2569 2570 s = splnet(); 2571 2572 ieee80211_free_node(data->ni); 2573 data->ni = NULL; 2574 2575 sc->sc_txtimer = 0; 2576 ifp->if_opackets++; 2577 2578 sc->sc_tx_normal_queued--; 2579 ifp->if_flags &= ~IFF_OACTIVE; 2580 urtw_start(ifp); 2581 2582 splx(s); 2583 } 2584 2585 int 2586 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2587 int prior) 2588 { 2589 struct ieee80211com *ic = &sc->sc_ic; 2590 struct urtw_tx_data *data; 2591 struct ieee80211_frame *wh; 2592 struct ieee80211_key *k; 2593 usbd_status error; 2594 int xferlen; 2595 2596 wh = mtod(m0, struct ieee80211_frame *); 2597 2598 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2599 k = ieee80211_crypto_encap(ic, ni, m0); 2600 if (k == NULL) { 2601 m_freem(m0); 2602 return ENOBUFS; 2603 } 2604 /* packet header may have moved, reset our local pointer */ 2605 wh = mtod(m0, struct ieee80211_frame *); 2606 } 2607 2608 if (sc->sc_drvbpf != NULL) { 2609 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2610 2611 tap->wt_flags = 0; 2612 tap->wt_rate = 0; 2613 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2614 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2615 2616 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 2617 } 2618 2619 if (sc->sc_hwrev & URTW_HWREV_8187) 2620 xferlen = m0->m_pkthdr.len + 4 * 3; 2621 else 2622 xferlen = m0->m_pkthdr.len + 4 * 8; 2623 2624 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2625 xferlen += 1; 2626 2627 data = &sc->sc_tx_data[sc->sc_txidx]; 2628 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2629 2630 memset(data->buf, 0, URTW_TX_MAXSIZE); 2631 data->buf[0] = m0->m_pkthdr.len & 0xff; 2632 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2633 data->buf[1] |= (1 << 7); 2634 2635 /* XXX sc_preamble_mode is always 2. */ 2636 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2637 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2638 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2639 data->buf[2] |= 1; 2640 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2641 prior == URTW_PRIORITY_LOW) 2642 panic("TODO tx."); 2643 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2644 data->buf[2] |= (1 << 1); 2645 /* RTS rate - 10 means we use a basic rate. */ 2646 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2647 /* 2648 * XXX currently TX rate control depends on the rate value of 2649 * RX descriptor because I don't know how to we can control TX rate 2650 * in more smart way. Please fix me you find a thing. 2651 */ 2652 data->buf[3] = sc->sc_currate; 2653 if (prior == URTW_PRIORITY_NORMAL) { 2654 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2655 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2656 else if (ic->ic_fixed_rate != -1) 2657 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2658 } 2659 2660 if (sc->sc_hwrev & URTW_HWREV_8187) { 2661 data->buf[8] = 3; /* CW minimum */ 2662 data->buf[8] |= (7 << 4); /* CW maximum */ 2663 data->buf[9] |= 11; /* retry limitation */ 2664 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2665 } else { 2666 data->buf[21] |= 11; /* retry limitation */ 2667 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2668 } 2669 2670 data->ni = ni; 2671 2672 /* mbuf is no longer needed. */ 2673 m_freem(m0); 2674 2675 usbd_setup_xfer(data->xfer, 2676 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2677 sc->sc_txpipe_normal, data, data->buf, xferlen, 2678 USBD_FORCE_SHORT_XFER, URTW_DATA_TIMEOUT, 2679 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2680 error = usbd_transfer(data->xfer); 2681 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2682 printf("%s: could not send frame: %s\n", 2683 device_xname(sc->sc_dev), usbd_errstr(error)); 2684 return EIO; 2685 } 2686 2687 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2688 if (error != 0) 2689 printf("%s: could not control LED (%d)\n", 2690 device_xname(sc->sc_dev), error); 2691 2692 if (prior == URTW_PRIORITY_LOW) 2693 sc->sc_tx_low_queued++; 2694 else 2695 sc->sc_tx_normal_queued++; 2696 2697 return 0; 2698 } 2699 2700 usbd_status 2701 urtw_8225_usb_init(struct urtw_softc *sc) 2702 { 2703 uint8_t data; 2704 usbd_status error; 2705 2706 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2707 urtw_write8_m(sc, URTW_GPIO, 0); 2708 error = urtw_read8e(sc, 0x53, &data); 2709 if (error) 2710 goto fail; 2711 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2712 if (error) 2713 goto fail; 2714 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2715 urtw_write8_m(sc, URTW_GPIO, 0x20); 2716 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2717 2718 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2719 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2720 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2721 2722 usbd_delay_ms(sc->sc_udev, 500); 2723 fail: 2724 return error; 2725 } 2726 2727 usbd_status 2728 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2729 { 2730 usbd_status error = 0; 2731 2732 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2733 fail: 2734 return error; 2735 } 2736 2737 usbd_status 2738 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2739 { 2740 uint32_t phyw; 2741 usbd_status error; 2742 2743 phyw = ((data << 8) | (addr | 0x80)); 2744 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2745 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2746 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2747 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2748 /* 2749 * Delay removed from 8185 to 8187. 2750 * usbd_delay_ms(sc->sc_udev, 1); 2751 */ 2752 fail: 2753 return error; 2754 } 2755 2756 usbd_status 2757 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2758 { 2759 data = data & 0xff; 2760 return urtw_8187_write_phy(sc, addr, data); 2761 } 2762 2763 usbd_status 2764 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2765 { 2766 data = data & 0xff; 2767 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2768 } 2769 2770 usbd_status 2771 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2772 { 2773 usbd_status error; 2774 2775 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2776 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2777 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2778 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2779 fail: 2780 return error; 2781 } 2782 2783 usbd_status 2784 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2785 { 2786 int i, idx, set; 2787 uint8_t *cck_pwltable; 2788 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2789 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2790 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2791 usbd_status error; 2792 2793 cck_pwrlvl_max = 11; 2794 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2795 ofdm_pwrlvl_min = 10; 2796 2797 /* CCK power setting */ 2798 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2799 idx = cck_pwrlvl % 6; 2800 set = cck_pwrlvl / 6; 2801 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2802 urtw_8225_txpwr_cck; 2803 2804 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2805 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2806 for (i = 0; i < 8; i++) { 2807 urtw_8187_write_phy_cck(sc, 0x44 + i, 2808 cck_pwltable[idx * 8 + i]); 2809 } 2810 usbd_delay_ms(sc->sc_udev, 1); 2811 2812 /* OFDM power setting */ 2813 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2814 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2815 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2816 2817 idx = ofdm_pwrlvl % 6; 2818 set = ofdm_pwrlvl / 6; 2819 2820 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2821 if (error) 2822 goto fail; 2823 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2824 urtw_8187_write_phy_ofdm(sc, 6, 0); 2825 urtw_8187_write_phy_ofdm(sc, 8, 0); 2826 2827 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2828 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2829 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2830 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2831 usbd_delay_ms(sc->sc_udev, 1); 2832 fail: 2833 return error; 2834 } 2835 2836 usbd_status 2837 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2838 { 2839 usbd_status error; 2840 2841 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2842 usbd_delay_ms(sc->sc_udev, 1); 2843 fail: 2844 return error; 2845 } 2846 2847 usbd_status 2848 urtw_8225_rf_init(struct urtw_rf *rf) 2849 { 2850 struct urtw_softc *sc = rf->rf_sc; 2851 unsigned int i; 2852 uint16_t data; 2853 usbd_status error; 2854 2855 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2856 if (error) 2857 goto fail; 2858 2859 error = urtw_8225_usb_init(sc); 2860 if (error) 2861 goto fail; 2862 2863 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2864 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2865 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2866 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2867 2868 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2869 if (error) 2870 goto fail; 2871 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2872 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2873 if (error) 2874 goto fail; 2875 2876 error = urtw_8185_rf_pins_enable(sc); 2877 if (error) 2878 goto fail; 2879 2880 usbd_delay_ms(sc->sc_udev, 500); 2881 2882 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2883 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2884 urtw_8225_rf_part1[i].val); 2885 } 2886 usbd_delay_ms(sc->sc_udev, 50); 2887 urtw_8225_write(sc, 0x2, 0xc4d); 2888 usbd_delay_ms(sc->sc_udev, 200); 2889 urtw_8225_write(sc, 0x2, 0x44d); 2890 usbd_delay_ms(sc->sc_udev, 200); 2891 urtw_8225_write(sc, 0x0, 0x127); 2892 2893 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2894 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2895 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2896 } 2897 2898 urtw_8225_write(sc, 0x0, 0x27); 2899 urtw_8225_write(sc, 0x0, 0x22f); 2900 2901 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2902 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2903 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2904 } 2905 2906 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2907 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2908 urtw_8225_rf_part2[i].val); 2909 usbd_delay_ms(sc->sc_udev, 1); 2910 } 2911 2912 error = urtw_8225_setgain(sc, 4); 2913 if (error) 2914 goto fail; 2915 2916 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2917 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2918 urtw_8225_rf_part3[i].val); 2919 usbd_delay_ms(sc->sc_udev, 1); 2920 } 2921 2922 urtw_write8_m(sc, 0x5b, 0x0d); 2923 2924 error = urtw_8225_set_txpwrlvl(sc, 1); 2925 if (error) 2926 goto fail; 2927 2928 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2929 usbd_delay_ms(sc->sc_udev, 1); 2930 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2931 usbd_delay_ms(sc->sc_udev, 1); 2932 2933 /* TX ant A, 0x0 for B */ 2934 error = urtw_8185_tx_antenna(sc, 0x3); 2935 if (error) 2936 goto fail; 2937 urtw_write32_m(sc, 0x94, 0x3dc00002); 2938 2939 error = urtw_8225_rf_set_chan(rf, 1); 2940 fail: 2941 return error; 2942 } 2943 2944 usbd_status 2945 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2946 { 2947 struct urtw_softc *sc = rf->rf_sc; 2948 struct ieee80211com *ic = &sc->sc_ic; 2949 struct ieee80211_channel *c = ic->ic_ibss_chan; 2950 usbd_status error; 2951 2952 error = urtw_8225_set_txpwrlvl(sc, chan); 2953 if (error) 2954 goto fail; 2955 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2956 usbd_delay_ms(sc->sc_udev, 10); 2957 2958 urtw_write8_m(sc, URTW_SIFS, 0x22); 2959 2960 if (sc->sc_state == IEEE80211_S_ASSOC && 2961 ic->ic_flags & IEEE80211_F_SHSLOT) 2962 urtw_write8_m(sc, URTW_SLOT, 0x9); 2963 else 2964 urtw_write8_m(sc, URTW_SLOT, 0x14); 2965 2966 if (IEEE80211_IS_CHAN_G(c)) { 2967 urtw_write8_m(sc, URTW_DIFS, 0x14); 2968 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2969 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2970 } else { 2971 urtw_write8_m(sc, URTW_DIFS, 0x24); 2972 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2973 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2974 } 2975 2976 fail: 2977 return error; 2978 } 2979 2980 usbd_status 2981 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2982 { 2983 struct urtw_softc *sc = rf->rf_sc; 2984 usbd_status error; 2985 2986 if (rf->sens > 6) 2987 return -1; 2988 2989 if (rf->sens > 4) 2990 urtw_8225_write(sc, 0x0c, 0x850); 2991 else 2992 urtw_8225_write(sc, 0x0c, 0x50); 2993 2994 rf->sens = 6 - rf->sens; 2995 error = urtw_8225_setgain(sc, rf->sens); 2996 if (error) 2997 goto fail; 2998 2999 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3000 3001 fail: 3002 return error; 3003 } 3004 3005 void 3006 urtw_stop(struct ifnet *ifp, int disable) 3007 { 3008 struct urtw_softc *sc = ifp->if_softc; 3009 struct ieee80211com *ic = &sc->sc_ic; 3010 uint8_t data; 3011 usbd_status error; 3012 3013 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3014 3015 sc->sc_txtimer = 0; 3016 ifp->if_timer = 0; 3017 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3018 3019 callout_stop(&sc->scan_to); 3020 callout_stop(&sc->sc_led_ch); 3021 3022 urtw_intr_disable(sc); 3023 urtw_read8_m(sc, URTW_CMD, &data); 3024 data &= ~URTW_CMD_TX_ENABLE; 3025 data &= ~URTW_CMD_RX_ENABLE; 3026 urtw_write8_m(sc, URTW_CMD, data); 3027 3028 if (sc->sc_rxpipe != NULL) 3029 usbd_abort_pipe(sc->sc_rxpipe); 3030 if (sc->sc_txpipe_low != NULL) 3031 usbd_abort_pipe(sc->sc_txpipe_low); 3032 if (sc->sc_txpipe_normal != NULL) 3033 usbd_abort_pipe(sc->sc_txpipe_normal); 3034 3035 fail: 3036 return; 3037 } 3038 3039 int 3040 urtw_isbmode(uint16_t rate) 3041 { 3042 rate = urtw_rtl2rate(rate); 3043 3044 return ((rate <= 22 && rate != 12 && rate != 18) || 3045 rate == 44) ? 1 : 0; 3046 } 3047 3048 void 3049 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3050 { 3051 struct urtw_rx_data *data = priv; 3052 struct urtw_softc *sc = data->sc; 3053 struct ieee80211com *ic = &sc->sc_ic; 3054 struct ifnet *ifp = ic->ic_ifp; 3055 struct ieee80211_frame *wh; 3056 struct ieee80211_node *ni; 3057 struct mbuf *m, *mnew; 3058 uint8_t *desc, quality, rate; 3059 int actlen, flen, len, rssi, s; 3060 3061 if (status != USBD_NORMAL_COMPLETION) { 3062 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3063 return; 3064 3065 if (status == USBD_STALLED) 3066 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3067 ifp->if_ierrors++; 3068 goto skip; 3069 } 3070 3071 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3072 if (actlen < URTW_MIN_RXBUFSZ) { 3073 ifp->if_ierrors++; 3074 goto skip; 3075 } 3076 3077 if (sc->sc_hwrev & URTW_HWREV_8187) 3078 /* 4 dword and 4 byte CRC */ 3079 len = actlen - (4 * 4); 3080 else 3081 /* 5 dword and 4 byte CRC */ 3082 len = actlen - (4 * 5); 3083 3084 desc = data->buf + len; 3085 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3086 if (flen > actlen) { 3087 ifp->if_ierrors++; 3088 goto skip; 3089 } 3090 3091 rate = (desc[2] & 0xf0) >> 4; 3092 if (sc->sc_hwrev & URTW_HWREV_8187) { 3093 quality = desc[4] & 0xff; 3094 rssi = (desc[6] & 0xfe) >> 1; 3095 3096 /* XXX correct? */ 3097 if (!urtw_isbmode(rate)) { 3098 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3099 rssi = ((90 - rssi) * 100) / 65; 3100 } else { 3101 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3102 rssi = ((95 - rssi) * 100) / 65; 3103 } 3104 } else { 3105 quality = desc[12]; 3106 rssi = 14 - desc[14] / 2; 3107 } 3108 3109 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3110 if (mnew == NULL) { 3111 printf("%s: could not allocate rx mbuf\n", 3112 device_xname(sc->sc_dev)); 3113 ifp->if_ierrors++; 3114 goto skip; 3115 } 3116 MCLGET(mnew, M_DONTWAIT); 3117 if (!(mnew->m_flags & M_EXT)) { 3118 printf("%s: could not allocate rx mbuf cluster\n", 3119 device_xname(sc->sc_dev)); 3120 m_freem(mnew); 3121 ifp->if_ierrors++; 3122 goto skip; 3123 } 3124 3125 m = data->m; 3126 data->m = mnew; 3127 data->buf = mtod(mnew, uint8_t *); 3128 3129 /* finalize mbuf */ 3130 m->m_pkthdr.rcvif = ifp; 3131 m->m_pkthdr.len = m->m_len = flen - 4; 3132 3133 s = splnet(); 3134 3135 if (sc->sc_drvbpf != NULL) { 3136 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3137 3138 /* XXX Are variables correct? */ 3139 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3140 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3141 tap->wr_dbm_antsignal = (int8_t)rssi; 3142 3143 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 3144 } 3145 wh = mtod(m, struct ieee80211_frame *); 3146 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3147 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3148 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3149 3150 /* XXX correct? */ 3151 if (!urtw_isbmode(rate)) { 3152 if (quality > 127) 3153 quality = 0; 3154 else if (quality < 27) 3155 quality = 100; 3156 else 3157 quality = 127 - quality; 3158 } else 3159 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3160 3161 /* send the frame to the 802.11 layer */ 3162 ieee80211_input(ic, m, ni, rssi, 0); 3163 3164 /* node is no longer needed */ 3165 ieee80211_free_node(ni); 3166 3167 splx(s); 3168 3169 skip: /* setup a new transfer */ 3170 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3171 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3172 (void)usbd_transfer(xfer); 3173 } 3174 3175 usbd_status 3176 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3177 { 3178 uint8_t *gainp; 3179 usbd_status error; 3180 3181 /* XXX for A? */ 3182 gainp = urtw_8225v2_gain_bg; 3183 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3184 usbd_delay_ms(sc->sc_udev, 1); 3185 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3186 usbd_delay_ms(sc->sc_udev, 1); 3187 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3188 usbd_delay_ms(sc->sc_udev, 1); 3189 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3190 usbd_delay_ms(sc->sc_udev, 1); 3191 fail: 3192 return error; 3193 } 3194 3195 usbd_status 3196 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3197 { 3198 int i; 3199 uint8_t *cck_pwrtable; 3200 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3201 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3202 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3203 usbd_status error; 3204 3205 /* CCK power setting */ 3206 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3207 cck_pwrlvl += sc->sc_txpwr_cck_base; 3208 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3209 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3210 urtw_8225v2_txpwr_cck; 3211 3212 for (i = 0; i < 8; i++) { 3213 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3214 } 3215 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3216 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3217 usbd_delay_ms(sc->sc_udev, 1); 3218 3219 /* OFDM power setting */ 3220 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3221 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3222 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3223 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3224 3225 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3226 if (error) 3227 goto fail; 3228 3229 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3230 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3231 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3232 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3233 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3234 3235 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3236 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3237 usbd_delay_ms(sc->sc_udev, 1); 3238 fail: 3239 return error; 3240 } 3241 3242 usbd_status 3243 urtw_8225v2_rf_init(struct urtw_rf *rf) 3244 { 3245 struct urtw_softc *sc = rf->rf_sc; 3246 int i; 3247 uint16_t data; 3248 uint32_t data32; 3249 usbd_status error; 3250 3251 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3252 if (error) 3253 goto fail; 3254 3255 error = urtw_8225_usb_init(sc); 3256 if (error) 3257 goto fail; 3258 3259 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3260 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3261 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3262 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3263 3264 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3265 if (error) 3266 goto fail; 3267 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3268 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3269 if (error) 3270 goto fail; 3271 3272 error = urtw_8185_rf_pins_enable(sc); 3273 if (error) 3274 goto fail; 3275 3276 usbd_delay_ms(sc->sc_udev, 1000); 3277 3278 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3279 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3280 urtw_8225v2_rf_part1[i].val); 3281 usbd_delay_ms(sc->sc_udev, 1); 3282 } 3283 usbd_delay_ms(sc->sc_udev, 50); 3284 3285 urtw_8225_write(sc, 0x0, 0x1b7); 3286 3287 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3288 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3289 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3290 } 3291 3292 urtw_8225_write(sc, 0x3, 0x2); 3293 urtw_8225_write(sc, 0x5, 0x4); 3294 urtw_8225_write(sc, 0x0, 0xb7); 3295 urtw_8225_write(sc, 0x2, 0xc4d); 3296 usbd_delay_ms(sc->sc_udev, 100); 3297 urtw_8225_write(sc, 0x2, 0x44d); 3298 usbd_delay_ms(sc->sc_udev, 100); 3299 3300 error = urtw_8225_read(sc, 0x6, &data32); 3301 if (error != 0) 3302 goto fail; 3303 if (data32 != 0xe6) 3304 printf("%s: expect 0xe6!! (0x%x)\n", device_xname(sc->sc_dev), 3305 data32); 3306 if (!(data32 & 0x80)) { 3307 urtw_8225_write(sc, 0x02, 0x0c4d); 3308 usbd_delay_ms(sc->sc_udev, 200); 3309 urtw_8225_write(sc, 0x02, 0x044d); 3310 usbd_delay_ms(sc->sc_udev, 100); 3311 error = urtw_8225_read(sc, 0x6, &data32); 3312 if (error != 0) 3313 goto fail; 3314 if (!(data32 & 0x80)) 3315 printf("%s: RF calibration failed\n", 3316 device_xname(sc->sc_dev)); 3317 } 3318 usbd_delay_ms(sc->sc_udev, 100); 3319 3320 urtw_8225_write(sc, 0x0, 0x2bf); 3321 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3322 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3323 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3324 } 3325 3326 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3327 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3328 urtw_8225v2_rf_part2[i].val); 3329 } 3330 3331 error = urtw_8225v2_setgain(sc, 4); 3332 if (error) 3333 goto fail; 3334 3335 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3336 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3337 urtw_8225v2_rf_part3[i].val); 3338 } 3339 3340 urtw_write8_m(sc, 0x5b, 0x0d); 3341 3342 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3343 if (error) 3344 goto fail; 3345 3346 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3347 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3348 3349 /* TX ant A, 0x0 for B */ 3350 error = urtw_8185_tx_antenna(sc, 0x3); 3351 if (error) 3352 goto fail; 3353 urtw_write32_m(sc, 0x94, 0x3dc00002); 3354 3355 error = urtw_8225_rf_set_chan(rf, 1); 3356 fail: 3357 return error; 3358 } 3359 3360 usbd_status 3361 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3362 { 3363 struct urtw_softc *sc = rf->rf_sc; 3364 struct ieee80211com *ic = &sc->sc_ic; 3365 struct ieee80211_channel *c = ic->ic_ibss_chan; 3366 usbd_status error; 3367 3368 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3369 if (error) 3370 goto fail; 3371 3372 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3373 usbd_delay_ms(sc->sc_udev, 10); 3374 3375 urtw_write8_m(sc, URTW_SIFS, 0x22); 3376 3377 if(sc->sc_state == IEEE80211_S_ASSOC && 3378 ic->ic_flags & IEEE80211_F_SHSLOT) 3379 urtw_write8_m(sc, URTW_SLOT, 0x9); 3380 else 3381 urtw_write8_m(sc, URTW_SLOT, 0x14); 3382 3383 if (IEEE80211_IS_CHAN_G(c)) { 3384 urtw_write8_m(sc, URTW_DIFS, 0x14); 3385 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3386 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3387 } else { 3388 urtw_write8_m(sc, URTW_DIFS, 0x24); 3389 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3390 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3391 } 3392 3393 fail: 3394 return error; 3395 } 3396 3397 void 3398 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3399 { 3400 struct urtw_rf *rf = &sc->sc_rf; 3401 struct ieee80211com *ic = &sc->sc_ic; 3402 usbd_status error = 0; 3403 uint32_t data; 3404 u_int chan; 3405 3406 chan = ieee80211_chan2ieee(ic, c); 3407 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3408 return; 3409 /* 3410 * During changing the channel we need to temporary disable 3411 * TX. 3412 */ 3413 urtw_read32_m(sc, URTW_TX_CONF, &data); 3414 data &= ~URTW_TX_LOOPBACK_MASK; 3415 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3416 error = rf->set_chan(rf, chan); 3417 if (error != 0) { 3418 printf("%s could not change the channel\n", 3419 device_xname(sc->sc_dev)); 3420 return; 3421 } 3422 usbd_delay_ms(sc->sc_udev, 10); 3423 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3424 3425 fail: return; 3426 3427 } 3428 3429 void 3430 urtw_next_scan(void *arg) 3431 { 3432 struct urtw_softc *sc = arg; 3433 struct ieee80211com *ic = &sc->sc_ic; 3434 int s; 3435 3436 if (sc->sc_dying) 3437 return; 3438 3439 s = splnet(); 3440 if (ic->ic_state == IEEE80211_S_SCAN) 3441 ieee80211_next_scan(ic); 3442 splx(s); 3443 } 3444 3445 void 3446 urtw_task(void *arg) 3447 { 3448 struct urtw_softc *sc = arg; 3449 struct ieee80211com *ic = &sc->sc_ic; 3450 struct ieee80211_node *ni; 3451 enum ieee80211_state ostate; 3452 usbd_status error = 0; 3453 3454 if (sc->sc_dying) 3455 return; 3456 3457 ostate = ic->ic_state; 3458 3459 switch (sc->sc_state) { 3460 case IEEE80211_S_INIT: 3461 if (ostate == IEEE80211_S_RUN) { 3462 /* turn link LED off */ 3463 (void)urtw_led_off(sc, URTW_LED_GPIO); 3464 } 3465 break; 3466 3467 case IEEE80211_S_SCAN: 3468 urtw_set_chan(sc, ic->ic_curchan); 3469 if (!sc->sc_dying) 3470 callout_schedule(&sc->scan_to, mstohz(200)); 3471 break; 3472 3473 case IEEE80211_S_AUTH: 3474 case IEEE80211_S_ASSOC: 3475 urtw_set_chan(sc, ic->ic_curchan); 3476 break; 3477 3478 case IEEE80211_S_RUN: 3479 ni = ic->ic_bss; 3480 3481 urtw_set_chan(sc, ic->ic_curchan); 3482 3483 /* setting bssid. */ 3484 error = urtw_set_bssid(sc, ni->ni_bssid); 3485 if (error != 0) 3486 goto fail; 3487 urtw_update_msr(sc); 3488 /* XXX maybe the below would be incorrect. */ 3489 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3490 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3491 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3492 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3493 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3494 if (error != 0) 3495 printf("%s: could not control LED (%d)\n", 3496 device_xname(sc->sc_dev), error); 3497 break; 3498 } 3499 3500 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3501 3502 fail: 3503 if (error != 0) { 3504 DPRINTF(("%s: error duing processing RUN state.", 3505 device_xname(sc->sc_dev))); 3506 } 3507 } 3508 3509 usbd_status 3510 urtw_8187b_update_wmm(struct urtw_softc *sc) 3511 { 3512 struct ieee80211com *ic = &sc->sc_ic; 3513 struct ieee80211_channel *c = ic->ic_ibss_chan; 3514 uint32_t data; 3515 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3516 usbd_status error; 3517 3518 sifs = 0xa; 3519 if (IEEE80211_IS_CHAN_G(c)) 3520 slot = 0x9; 3521 else 3522 slot = 0x14; 3523 3524 aifs = (2 * slot) + sifs; 3525 ecwmin = 3; 3526 ecwmax = 7; 3527 3528 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3529 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3530 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3531 3532 urtw_write32_m(sc, URTW_AC_VO, data); 3533 urtw_write32_m(sc, URTW_AC_VI, data); 3534 urtw_write32_m(sc, URTW_AC_BE, data); 3535 urtw_write32_m(sc, URTW_AC_BK, data); 3536 3537 fail: 3538 return error; 3539 } 3540 3541 usbd_status 3542 urtw_8187b_reset(struct urtw_softc *sc) 3543 { 3544 uint8_t data; 3545 usbd_status error; 3546 3547 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3548 if (error) 3549 goto fail; 3550 3551 urtw_read8_m(sc, URTW_CONFIG3, &data); 3552 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3553 URTW_CONFIG3_GNT_SELECT); 3554 3555 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3556 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3557 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3558 3559 urtw_write8_m(sc, 0x61, 0x10); 3560 urtw_read8_m(sc, 0x62, &data); 3561 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3562 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3563 3564 urtw_read8_m(sc, URTW_CONFIG3, &data); 3565 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3566 3567 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3568 if (error) 3569 goto fail; 3570 3571 urtw_read8_m(sc, URTW_CMD, &data); 3572 data = (data & 2) | URTW_CMD_RST; 3573 urtw_write8_m(sc, URTW_CMD, data); 3574 usbd_delay_ms(sc->sc_udev, 100); 3575 3576 urtw_read8_m(sc, URTW_CMD, &data); 3577 if (data & URTW_CMD_RST) { 3578 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3579 goto fail; 3580 } 3581 3582 fail: 3583 return error; 3584 } 3585 3586 int 3587 urtw_8187b_init(struct ifnet *ifp) 3588 { 3589 struct urtw_softc *sc = ifp->if_softc; 3590 struct urtw_rf *rf = &sc->sc_rf; 3591 struct ieee80211com *ic = &sc->sc_ic; 3592 uint8_t data; 3593 usbd_status error; 3594 3595 urtw_stop(ifp, 0); 3596 3597 error = urtw_8187b_update_wmm(sc); 3598 if (error != 0) 3599 goto fail; 3600 error = urtw_8187b_reset(sc); 3601 if (error) 3602 goto fail; 3603 3604 /* Applying MAC address again. */ 3605 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3606 if (error) 3607 goto fail; 3608 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3609 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3610 if (error) 3611 goto fail; 3612 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3613 if (error) 3614 goto fail; 3615 3616 error = urtw_update_msr(sc); 3617 if (error) 3618 goto fail; 3619 3620 error = rf->init(rf); 3621 if (error != 0) 3622 goto fail; 3623 3624 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3625 URTW_CMD_RX_ENABLE); 3626 error = urtw_intr_enable(sc); 3627 if (error != 0) 3628 goto fail; 3629 3630 error = urtw_write8e(sc, 0x41, 0xf4); 3631 if (error != 0) 3632 goto fail; 3633 error = urtw_write8e(sc, 0x40, 0x00); 3634 if (error != 0) 3635 goto fail; 3636 error = urtw_write8e(sc, 0x42, 0x00); 3637 if (error != 0) 3638 goto fail; 3639 error = urtw_write8e(sc, 0x42, 0x01); 3640 if (error != 0) 3641 goto fail; 3642 error = urtw_write8e(sc, 0x40, 0x0f); 3643 if (error != 0) 3644 goto fail; 3645 error = urtw_write8e(sc, 0x42, 0x00); 3646 if (error != 0) 3647 goto fail; 3648 error = urtw_write8e(sc, 0x42, 0x01); 3649 if (error != 0) 3650 goto fail; 3651 3652 urtw_read8_m(sc, 0xdb, &data); 3653 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3654 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3655 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3656 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3657 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3658 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3659 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3660 urtw_write8_m(sc, 0x61, 0); 3661 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3662 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3663 urtw_write8_m(sc, 0xda, 0x10); 3664 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3665 3666 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3667 3668 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3669 3670 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3671 3672 /* Reset softc variables. */ 3673 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3674 sc->sc_txtimer = 0; 3675 3676 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3677 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3678 if (error != 0) { 3679 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3680 ", err=%s\n", usbd_errstr(error)); 3681 3682 goto fail; 3683 } 3684 /* Get the first interface handle. */ 3685 error = usbd_device2interface_handle(sc->sc_udev, 3686 URTW_IFACE_INDEX, &sc->sc_iface); 3687 if (error != 0) { 3688 printf("%s: could not get interface handle\n", 3689 device_xname(sc->sc_dev)); 3690 goto fail; 3691 } 3692 error = urtw_open_pipes(sc); 3693 if (error != 0) 3694 goto fail; 3695 error = urtw_alloc_rx_data_list(sc); 3696 if (error != 0) 3697 goto fail; 3698 error = urtw_alloc_tx_data_list(sc); 3699 if (error != 0) 3700 goto fail; 3701 sc->sc_flags |= URTW_INIT_ONCE; 3702 } 3703 3704 error = urtw_rx_enable(sc); 3705 if (error != 0) 3706 goto fail; 3707 error = urtw_tx_enable(sc); 3708 if (error != 0) 3709 goto fail; 3710 3711 ifp->if_flags &= ~IFF_OACTIVE; 3712 ifp->if_flags |= IFF_RUNNING; 3713 3714 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3715 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3716 else 3717 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3718 3719 fail: 3720 return error; 3721 } 3722 3723 usbd_status 3724 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3725 { 3726 int i; 3727 usbd_status error; 3728 3729 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3730 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3731 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3732 } 3733 3734 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3735 urtw_write16_m(sc, URTW_INT_MIG, 0); 3736 3737 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3738 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3739 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3740 3741 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3742 3743 fail: 3744 return error; 3745 } 3746 3747 usbd_status 3748 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3749 { 3750 usbd_status error; 3751 3752 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3753 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3754 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3755 usbd_delay_ms(sc->sc_udev, 100); 3756 3757 fail: 3758 return error; 3759 } 3760 3761 usbd_status 3762 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3763 { 3764 struct ieee80211com *ic = &sc->sc_ic; 3765 struct ieee80211_channel *c = ic->ic_ibss_chan; 3766 uint8_t aifs, difs, eifs, sifs, slot; 3767 usbd_status error; 3768 3769 urtw_write8_m(sc, URTW_SIFS, 0x22); 3770 3771 sifs = 0xa; 3772 if (IEEE80211_IS_CHAN_G(c)) { 3773 slot = 0x9; 3774 difs = 0x1c; 3775 eifs = 0x5b; 3776 } else { 3777 slot = 0x14; 3778 difs = 0x32; 3779 eifs = 0x5b; 3780 } 3781 aifs = (2 * slot) + sifs; 3782 3783 urtw_write8_m(sc, URTW_SLOT, slot); 3784 3785 urtw_write8_m(sc, URTW_AC_VO, aifs); 3786 urtw_write8_m(sc, URTW_AC_VI, aifs); 3787 urtw_write8_m(sc, URTW_AC_BE, aifs); 3788 urtw_write8_m(sc, URTW_AC_BK, aifs); 3789 3790 urtw_write8_m(sc, URTW_DIFS, difs); 3791 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3792 3793 fail: 3794 return error; 3795 } 3796 3797 usbd_status 3798 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3799 { 3800 struct urtw_softc *sc = rf->rf_sc; 3801 unsigned int i; 3802 uint8_t data; 3803 usbd_status error; 3804 3805 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3806 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3807 urtw_read8_m(sc, URTW_CW_CONF, &data); 3808 urtw_write8_m(sc, URTW_CW_CONF, data | 3809 URTW_CW_CONF_PERPACKET_RETRY); 3810 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3811 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3812 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3813 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3814 3815 /* Auto rate fallback control. */ 3816 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3817 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3818 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3819 URTW_RATE_FALLBACK_ENABLE); 3820 3821 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3822 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3823 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3824 3825 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3826 if (error) 3827 goto fail; 3828 urtw_read8_m(sc, URTW_CONFIG1, &data); 3829 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3830 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3831 if (error) 3832 goto fail; 3833 3834 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3835 urtw_8225v2_b_config_mac(sc); 3836 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3837 3838 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3839 if (error) 3840 goto fail; 3841 urtw_read8_m(sc, URTW_CONFIG3, &data); 3842 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3843 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3844 if (error) 3845 goto fail; 3846 3847 urtw_8225v2_b_init_rfe(sc); 3848 3849 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3850 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3851 urtw_8225v2_b_rf[i].val); 3852 } 3853 3854 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3855 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3856 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3857 } 3858 3859 urtw_8225_write(sc, 0x03, 0x080); 3860 urtw_8225_write(sc, 0x05, 0x004); 3861 urtw_8225_write(sc, 0x00, 0x0b7); 3862 urtw_8225_write(sc, 0x02, 0xc4d); 3863 urtw_8225_write(sc, 0x02, 0x44d); 3864 urtw_8225_write(sc, 0x00, 0x2bf); 3865 3866 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3867 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3868 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3869 3870 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3871 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3872 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3873 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3874 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3875 } 3876 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3877 3878 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3879 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3880 3881 urtw_8225v2_b_update_chan(sc); 3882 3883 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3884 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3885 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3886 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3887 3888 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3889 fail: 3890 return error; 3891 } 3892 3893 usbd_status 3894 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3895 { 3896 struct urtw_softc *sc = rf->rf_sc; 3897 usbd_status error; 3898 3899 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3900 if (error) 3901 goto fail; 3902 3903 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3904 /* 3905 * Delay removed from 8185 to 8187. 3906 * usbd_delay_ms(sc->sc_udev, 10); 3907 */ 3908 3909 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3910 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3911 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3912 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3913 3914 fail: 3915 return error; 3916 } 3917 3918 usbd_status 3919 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3920 { 3921 int i; 3922 uint8_t *cck_pwrtable; 3923 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3924 ofdm_pwrlvl_max; 3925 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3926 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3927 usbd_status error; 3928 3929 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3930 cck_pwrlvl_min = 0; 3931 cck_pwrlvl_max = 15; 3932 ofdm_pwrlvl_min = 2; 3933 ofdm_pwrlvl_max = 17; 3934 } else { 3935 cck_pwrlvl_min = 7; 3936 cck_pwrlvl_max = 22; 3937 ofdm_pwrlvl_min = 10; 3938 ofdm_pwrlvl_max = 25; 3939 } 3940 3941 /* CCK power setting */ 3942 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3943 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3944 3945 cck_pwrlvl += sc->sc_txpwr_cck_base; 3946 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3947 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3948 3949 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3950 urtw_8225v2_txpwr_cck; 3951 3952 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3953 if (cck_pwrlvl <= 6) 3954 ; /* do nothing */ 3955 else if (cck_pwrlvl <= 11) 3956 cck_pwrtable += 8; 3957 else 3958 cck_pwrtable += 16; 3959 } else { 3960 if (cck_pwrlvl <= 5) 3961 ; /* do nothing */ 3962 else if (cck_pwrlvl <= 11) 3963 cck_pwrtable += 8; 3964 else if (cck_pwrlvl <= 17) 3965 cck_pwrtable += 16; 3966 else 3967 cck_pwrtable += 24; 3968 } 3969 3970 for (i = 0; i < 8; i++) { 3971 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3972 } 3973 3974 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3975 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3976 /* 3977 * Delay removed from 8185 to 8187. 3978 * usbd_delay_ms(sc->sc_udev, 1); 3979 */ 3980 3981 /* OFDM power setting */ 3982 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3983 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3984 3985 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3986 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3987 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3988 3989 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3990 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3991 3992 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3993 if (ofdm_pwrlvl <= 11) { 3994 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3995 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3996 } else { 3997 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3998 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3999 } 4000 } else { 4001 if (ofdm_pwrlvl <= 11) { 4002 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4003 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4004 } else if (ofdm_pwrlvl <= 17) { 4005 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4006 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4007 } else { 4008 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4009 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4010 } 4011 } 4012 4013 /* 4014 * Delay removed from 8185 to 8187. 4015 * usbd_delay_ms(sc->sc_udev, 1); 4016 */ 4017 fail: 4018 return error; 4019 } 4020 4021 int 4022 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4023 { 4024 int error; 4025 4026 urtw_write32_m(sc, URTW_BSSID, 4027 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4028 urtw_write16_m(sc, URTW_BSSID + 4, 4029 bssid[4] | bssid[5] << 8); 4030 4031 return 0; 4032 4033 fail: 4034 return error; 4035 } 4036 4037 int 4038 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4039 { 4040 int error; 4041 4042 urtw_write32_m(sc, URTW_MAC0, 4043 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4044 urtw_write16_m(sc, URTW_MAC4, 4045 addr[4] | addr[5] << 8); 4046 4047 return 0; 4048 4049 fail: 4050 return error; 4051 } 4052 4053 MODULE(MODULE_CLASS_DRIVER, if_urtw, "bpf"); 4054 4055 #ifdef _MODULE 4056 #include "ioconf.c" 4057 #endif 4058 4059 static int 4060 if_urtw_modcmd(modcmd_t cmd, void *aux) 4061 { 4062 int error = 0; 4063 4064 switch (cmd) { 4065 case MODULE_CMD_INIT: 4066 #ifdef _MODULE 4067 error = config_init_component(cfdriver_ioconf_urtw, 4068 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4069 #endif 4070 return error; 4071 case MODULE_CMD_FINI: 4072 #ifdef _MODULE 4073 error = config_fini_component(cfdriver_ioconf_urtw, 4074 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4075 #endif 4076 return error; 4077 default: 4078 return ENOTTY; 4079 } 4080 } 4081
Indexes created Fri Oct 03 02:09:57 GMT 2025