if_urtwn.c revision 1.1
1 /* $NetBSD: if_urtwn.c,v 1.1 2012/03/25 00:11:16 nonaka Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.1 2012/03/25 00:11:16 nonaka Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/sysctl.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 #include <machine/endian.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_netbsd.h> 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/firmload.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usbdi_util.h> 66 #include <dev/usb/usbdevs.h> 67 68 #include <dev/usb/if_urtwnreg.h> 69 #include <dev/usb/if_urtwnvar.h> 70 #include <dev/usb/if_urtwn_data.h> 71 72 #ifdef USB_DEBUG 73 #define URTWN_DEBUG 74 #endif 75 76 #ifdef URTWN_DEBUG 77 #define DBG_INIT __BIT(0) 78 #define DBG_FN __BIT(1) 79 #define DBG_TX __BIT(2) 80 #define DBG_RX __BIT(3) 81 #define DBG_STM __BIT(4) 82 #define DBG_RF __BIT(5) 83 #define DBG_REG __BIT(6) 84 #define DBG_ALL 0xffffffffU 85 u_int urtwn_debug = DBG_TX|DBG_RX|DBG_STM; 86 #define DPRINTFN(n, s) \ 87 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 88 #else 89 #define DPRINTFN(n, s) 90 #endif 91 92 static const struct usb_devno urtwn_devs[] = { 93 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 94 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 95 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 96 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 97 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 98 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 99 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 100 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 101 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 102 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 103 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 104 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 105 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 106 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 107 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 108 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 109 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 110 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 111 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 112 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 113 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 114 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 115 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 116 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 117 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 118 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 123 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 124 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 125 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 126 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 127 }; 128 129 static int urtwn_match(device_t, cfdata_t, void *); 130 static void urtwn_attach(device_t, device_t, void *); 131 static int urtwn_detach(device_t, int); 132 static int urtwn_activate(device_t, enum devact); 133 134 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 135 urtwn_attach, urtwn_detach, urtwn_activate); 136 137 static int urtwn_open_pipes(struct urtwn_softc *); 138 static void urtwn_close_pipes(struct urtwn_softc *); 139 static int urtwn_alloc_rx_list(struct urtwn_softc *); 140 static void urtwn_free_rx_list(struct urtwn_softc *); 141 static int urtwn_alloc_tx_list(struct urtwn_softc *); 142 static void urtwn_free_tx_list(struct urtwn_softc *); 143 static void urtwn_task(void *); 144 static void urtwn_do_async(struct urtwn_softc *, 145 void (*)(struct urtwn_softc *, void *), void *, int); 146 static void urtwn_wait_async(struct urtwn_softc *); 147 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 148 int); 149 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 150 int); 151 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 152 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 153 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 154 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 155 static void urtwn_efuse_read(struct urtwn_softc *); 156 static int urtwn_read_chipid(struct urtwn_softc *); 157 static void urtwn_read_rom(struct urtwn_softc *); 158 static int urtwn_media_change(struct ifnet *); 159 static int urtwn_ra_init(struct urtwn_softc *); 160 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 161 static void urtwn_set_led(struct urtwn_softc *, int, int); 162 static void urtwn_calib_to(void *); 163 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 164 static void urtwn_next_scan(void *); 165 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 166 int); 167 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 168 static int urtwn_wme_update(struct ieee80211com *); 169 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 170 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 171 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 172 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 173 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 174 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 175 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 176 struct ieee80211_node *); 177 static void urtwn_start(struct ifnet *); 178 static void urtwn_watchdog(struct ifnet *); 179 static int urtwn_ioctl(struct ifnet *, u_long, void *); 180 static int urtwn_power_on(struct urtwn_softc *); 181 static int urtwn_llt_init(struct urtwn_softc *); 182 static void urtwn_fw_reset(struct urtwn_softc *); 183 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 184 static int urtwn_load_firmware(struct urtwn_softc *); 185 static int urtwn_dma_init(struct urtwn_softc *); 186 static void urtwn_mac_init(struct urtwn_softc *); 187 static void urtwn_bb_init(struct urtwn_softc *); 188 static void urtwn_rf_init(struct urtwn_softc *); 189 static void urtwn_cam_init(struct urtwn_softc *); 190 static void urtwn_pa_bias_init(struct urtwn_softc *); 191 static void urtwn_rxfilter_init(struct urtwn_softc *); 192 static void urtwn_edca_init(struct urtwn_softc *); 193 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 194 static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, 195 uint16_t[]); 196 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 197 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 198 u_int); 199 static void urtwn_iq_calib(struct urtwn_softc *, bool); 200 static void urtwn_lc_calib(struct urtwn_softc *); 201 static void urtwn_temp_calib(struct urtwn_softc *); 202 static int urtwn_init(struct ifnet *); 203 static void urtwn_stop(struct ifnet *, int); 204 static void urtwn_chip_stop(struct urtwn_softc *); 205 206 /* Aliases. */ 207 #define urtwn_bb_write urtwn_write_4 208 #define urtwn_bb_read urtwn_read_4 209 210 static int 211 urtwn_match(device_t parent, cfdata_t match, void *aux) 212 { 213 struct usb_attach_arg *uaa = aux; 214 215 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 216 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 217 } 218 219 static void 220 urtwn_attach(device_t parent, device_t self, void *aux) 221 { 222 struct urtwn_softc *sc = device_private(self); 223 struct ieee80211com *ic = &sc->sc_ic; 224 struct ifnet *ifp = &sc->sc_if; 225 struct usb_attach_arg *uaa = aux; 226 char *devinfop; 227 int i, error; 228 229 sc->sc_dev = self; 230 sc->sc_udev = uaa->device; 231 232 aprint_naive("\n"); 233 aprint_normal("\n"); 234 235 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 236 aprint_normal_dev(self, "%s\n", devinfop); 237 usbd_devinfo_free(devinfop); 238 239 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 240 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NET); 241 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 242 243 usb_init_task(&sc->sc_task, urtwn_task, sc); 244 245 callout_init(&sc->sc_scan_to, 0); 246 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 247 callout_init(&sc->sc_calib_to, 0); 248 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 249 250 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 251 aprint_error_dev(self, "could not set configuration no\n"); 252 goto fail; 253 } 254 255 /* Get the first interface handle. */ 256 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 257 if (error != 0) { 258 aprint_error_dev(self, "could not get interface handle\n"); 259 goto fail; 260 } 261 262 error = urtwn_read_chipid(sc); 263 if (error != 0) { 264 aprint_error_dev(self, "unsupported test chip\n"); 265 goto fail; 266 } 267 268 /* Determine number of Tx/Rx chains. */ 269 if (sc->chip & URTWN_CHIP_92C) { 270 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 271 sc->nrxchains = 2; 272 } else { 273 sc->ntxchains = 1; 274 sc->nrxchains = 1; 275 } 276 urtwn_read_rom(sc); 277 278 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 279 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 280 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 281 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 282 "8188CUS", sc->ntxchains, sc->nrxchains, 283 ether_sprintf(ic->ic_myaddr)); 284 285 error = urtwn_open_pipes(sc); 286 if (error != 0) { 287 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 288 goto fail; 289 } 290 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 291 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 292 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 293 294 /* 295 * Setup the 802.11 device. 296 */ 297 ic->ic_ifp = ifp; 298 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 299 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 300 ic->ic_state = IEEE80211_S_INIT; 301 302 /* Set device capabilities. */ 303 ic->ic_caps = 304 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 305 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 306 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 307 IEEE80211_C_WME | /* 802.11e */ 308 IEEE80211_C_WPA; /* 802.11i */ 309 310 /* Set supported .11b and .11g rates. */ 311 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 312 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 313 314 /* Set supported .11b and .11g channels (1 through 14). */ 315 for (i = 1; i <= 14; i++) { 316 ic->ic_channels[i].ic_freq = 317 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 318 ic->ic_channels[i].ic_flags = 319 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 320 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 321 } 322 323 ifp->if_softc = sc; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_init = urtwn_init; 326 ifp->if_ioctl = urtwn_ioctl; 327 ifp->if_start = urtwn_start; 328 ifp->if_watchdog = urtwn_watchdog; 329 IFQ_SET_READY(&ifp->if_snd); 330 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 331 332 if_attach(ifp); 333 ieee80211_ifattach(ic); 334 /* override default methods */ 335 ic->ic_wme.wme_update = urtwn_wme_update; 336 337 /* Override state transition machine. */ 338 sc->sc_newstate = ic->ic_newstate; 339 ic->ic_newstate = urtwn_newstate; 340 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 341 342 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 343 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 344 &sc->sc_drvbpf); 345 346 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 347 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 348 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 349 350 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 351 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 352 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 353 354 ieee80211_announce(ic); 355 356 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 357 358 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 359 return; 360 361 fail: 362 sc->sc_dying = 1; 363 aprint_error_dev(self, "attach failed\n"); 364 } 365 366 static int 367 urtwn_detach(device_t self, int flags) 368 { 369 struct urtwn_softc *sc = device_private(self); 370 struct ifnet *ifp = &sc->sc_if; 371 int s; 372 373 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 374 375 s = splusb(); 376 377 sc->sc_dying = 1; 378 379 callout_stop(&sc->sc_scan_to); 380 callout_stop(&sc->sc_calib_to); 381 382 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 383 usb_rem_task(sc->sc_udev, &sc->sc_task); 384 urtwn_stop(ifp, 0); 385 386 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 387 bpf_detach(ifp); 388 ieee80211_ifdetach(&sc->sc_ic); 389 if_detach(ifp); 390 391 /* Abort and close Tx/Rx pipes. */ 392 urtwn_close_pipes(sc); 393 } 394 395 splx(s); 396 397 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 398 399 callout_destroy(&sc->sc_scan_to); 400 callout_destroy(&sc->sc_calib_to); 401 mutex_destroy(&sc->sc_fwcmd_mtx); 402 mutex_destroy(&sc->sc_tx_mtx); 403 mutex_destroy(&sc->sc_task_mtx); 404 405 return (0); 406 } 407 408 static int 409 urtwn_activate(device_t self, enum devact act) 410 { 411 struct urtwn_softc *sc = device_private(self); 412 413 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 414 415 switch (act) { 416 case DVACT_DEACTIVATE: 417 if_deactivate(sc->sc_ic.ic_ifp); 418 return (0); 419 default: 420 return (EOPNOTSUPP); 421 } 422 } 423 424 static int 425 urtwn_open_pipes(struct urtwn_softc *sc) 426 { 427 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 428 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 429 usb_interface_descriptor_t *id; 430 usb_endpoint_descriptor_t *ed; 431 int i, ntx = 0, error; 432 433 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 434 435 /* Determine the number of bulk-out pipes. */ 436 id = usbd_get_interface_descriptor(sc->sc_iface); 437 for (i = 0; i < id->bNumEndpoints; i++) { 438 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 439 if (ed != NULL && 440 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 441 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 442 ntx++; 443 } 444 DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", 445 device_xname(sc->sc_dev), __func__, ntx)); 446 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 447 aprint_error_dev(sc->sc_dev, 448 "%d: invalid number of Tx bulk pipes\n", ntx); 449 return (EIO); 450 } 451 sc->rx_npipe = 1; 452 sc->tx_npipe = ntx; 453 454 /* Open bulk-in pipe at address 0x81. */ 455 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 456 &sc->rx_pipe); 457 if (error != 0) { 458 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe\n"); 459 goto fail; 460 } 461 462 /* Open bulk-out pipes (up to 3). */ 463 for (i = 0; i < ntx; i++) { 464 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 465 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, 468 "could not open Tx bulk pipe 0x%02x\n", epaddr[i]); 469 goto fail; 470 } 471 } 472 473 /* Map 802.11 access categories to USB pipes. */ 474 sc->ac2idx[WME_AC_BK] = 475 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 476 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 477 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 478 479 fail: 480 if (error != 0) 481 urtwn_close_pipes(sc); 482 return (error); 483 } 484 485 static void 486 urtwn_close_pipes(struct urtwn_softc *sc) 487 { 488 int i; 489 490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 491 492 /* Close Rx pipe. */ 493 if (sc->rx_pipe != NULL) { 494 usbd_abort_pipe(sc->rx_pipe); 495 usbd_close_pipe(sc->rx_pipe); 496 sc->rx_pipe = NULL; 497 } 498 /* Close Tx pipes. */ 499 for (i = 0; i < R92C_MAX_EPOUT; i++) { 500 if (sc->tx_pipe[i] == NULL) 501 continue; 502 usbd_abort_pipe(sc->tx_pipe[i]); 503 usbd_close_pipe(sc->tx_pipe[i]); 504 sc->tx_pipe[i] = NULL; 505 } 506 } 507 508 static int 509 urtwn_alloc_rx_list(struct urtwn_softc *sc) 510 { 511 struct urtwn_rx_data *data; 512 int i, error = 0; 513 514 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 515 516 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 517 data = &sc->rx_data[i]; 518 519 data->sc = sc; /* Backpointer for callbacks. */ 520 521 data->xfer = usbd_alloc_xfer(sc->sc_udev); 522 if (data->xfer == NULL) { 523 aprint_error_dev(sc->sc_dev, 524 "could not allocate xfer\n"); 525 error = ENOMEM; 526 break; 527 } 528 529 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 530 if (data->buf == NULL) { 531 aprint_error_dev(sc->sc_dev, 532 "could not allocate xfer buffer\n"); 533 error = ENOMEM; 534 break; 535 } 536 } 537 if (error != 0) 538 urtwn_free_rx_list(sc); 539 return (error); 540 } 541 542 static void 543 urtwn_free_rx_list(struct urtwn_softc *sc) 544 { 545 int i; 546 547 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 548 549 /* NB: Caller must abort pipe first. */ 550 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 551 if (sc->rx_data[i].xfer != NULL) { 552 usbd_free_xfer(sc->rx_data[i].xfer); 553 sc->rx_data[i].xfer = NULL; 554 } 555 } 556 } 557 558 static int 559 urtwn_alloc_tx_list(struct urtwn_softc *sc) 560 { 561 struct urtwn_tx_data *data; 562 int i, error = 0; 563 564 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 565 566 mutex_enter(&sc->sc_tx_mtx); 567 TAILQ_INIT(&sc->tx_free_list); 568 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 569 data = &sc->tx_data[i]; 570 571 data->sc = sc; /* Backpointer for callbacks. */ 572 573 data->xfer = usbd_alloc_xfer(sc->sc_udev); 574 if (data->xfer == NULL) { 575 aprint_error_dev(sc->sc_dev, 576 "could not allocate xfer\n"); 577 error = ENOMEM; 578 goto fail; 579 } 580 581 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 582 if (data->buf == NULL) { 583 aprint_error_dev(sc->sc_dev, 584 "could not allocate xfer buffer\n"); 585 error = ENOMEM; 586 goto fail; 587 } 588 589 /* Append this Tx buffer to our free list. */ 590 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 591 } 592 mutex_exit(&sc->sc_tx_mtx); 593 return (0); 594 595 fail: 596 urtwn_free_tx_list(sc); 597 return (error); 598 } 599 600 static void 601 urtwn_free_tx_list(struct urtwn_softc *sc) 602 { 603 struct urtwn_tx_data *data; 604 int i; 605 606 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 607 608 /* NB: Caller must abort pipe first. */ 609 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 610 data = &sc->tx_data[i]; 611 612 if (data->xfer != NULL) { 613 usbd_free_xfer(data->xfer); 614 data->xfer = NULL; 615 } 616 } 617 } 618 619 static void 620 urtwn_task(void *arg) 621 { 622 struct urtwn_softc *sc = arg; 623 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 624 struct urtwn_host_cmd *cmd; 625 int s; 626 627 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 628 629 /* Process host commands. */ 630 s = splusb(); 631 mutex_spin_enter(&sc->sc_task_mtx); 632 while (ring->next != ring->cur) { 633 cmd = &ring->cmd[ring->next]; 634 mutex_spin_exit(&sc->sc_task_mtx); 635 splx(s); 636 /* Invoke callback. */ 637 cmd->cb(sc, cmd->data); 638 s = splusb(); 639 mutex_spin_enter(&sc->sc_task_mtx); 640 ring->queued--; 641 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 642 } 643 mutex_spin_exit(&sc->sc_task_mtx); 644 wakeup(&sc->cmdq); 645 splx(s); 646 } 647 648 static void 649 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 650 void *arg, int len) 651 { 652 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 653 struct urtwn_host_cmd *cmd; 654 int s; 655 656 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 657 device_xname(sc->sc_dev), __func__, cb, arg, len)); 658 659 s = splusb(); 660 mutex_spin_enter(&sc->sc_task_mtx); 661 cmd = &ring->cmd[ring->cur]; 662 cmd->cb = cb; 663 KASSERT(len <= sizeof(cmd->data)); 664 memcpy(cmd->data, arg, len); 665 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 666 667 /* If there is no pending command already, schedule a task. */ 668 if (!sc->sc_dying && ++ring->queued == 1) { 669 mutex_spin_exit(&sc->sc_task_mtx); 670 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 671 } else 672 mutex_spin_exit(&sc->sc_task_mtx); 673 splx(s); 674 } 675 676 static void 677 urtwn_wait_async(struct urtwn_softc *sc) 678 { 679 680 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 681 682 /* Wait for all queued asynchronous commands to complete. */ 683 while (sc->cmdq.queued > 0) 684 tsleep(&sc->cmdq, 0, "endtask", 0); 685 } 686 687 static int 688 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 689 int len) 690 { 691 usb_device_request_t req; 692 usbd_status error; 693 694 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 695 req.bRequest = R92C_REQ_REGS; 696 USETW(req.wValue, addr); 697 USETW(req.wIndex, 0); 698 USETW(req.wLength, len); 699 error = usbd_do_request(sc->sc_udev, &req, buf); 700 if (error != USBD_NORMAL_COMPLETION) { 701 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 702 device_xname(sc->sc_dev), __func__, error, addr, len)); 703 } 704 return (error); 705 } 706 707 static void 708 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 709 { 710 711 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 712 device_xname(sc->sc_dev), __func__, addr, val)); 713 714 urtwn_write_region_1(sc, addr, &val, 1); 715 } 716 717 static void 718 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 719 { 720 uint8_t buf[2]; 721 722 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 723 device_xname(sc->sc_dev), __func__, addr, val)); 724 725 buf[0] = (uint8_t)val; 726 buf[1] = (uint8_t)(val >> 8); 727 urtwn_write_region_1(sc, addr, buf, 2); 728 } 729 730 static void 731 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 732 { 733 uint8_t buf[4]; 734 735 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 736 device_xname(sc->sc_dev), __func__, addr, val)); 737 738 buf[0] = (uint8_t)val; 739 buf[1] = (uint8_t)(val >> 8); 740 buf[2] = (uint8_t)(val >> 16); 741 buf[3] = (uint8_t)(val >> 24); 742 urtwn_write_region_1(sc, addr, buf, 4); 743 } 744 745 static int 746 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 747 { 748 749 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 750 device_xname(sc->sc_dev), __func__, addr, len)); 751 752 return urtwn_write_region_1(sc, addr, buf, len); 753 } 754 755 static int 756 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 757 int len) 758 { 759 usb_device_request_t req; 760 usbd_status error; 761 762 req.bmRequestType = UT_READ_VENDOR_DEVICE; 763 req.bRequest = R92C_REQ_REGS; 764 USETW(req.wValue, addr); 765 USETW(req.wIndex, 0); 766 USETW(req.wLength, len); 767 error = usbd_do_request(sc->sc_udev, &req, buf); 768 if (error != USBD_NORMAL_COMPLETION) { 769 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 770 device_xname(sc->sc_dev), __func__, error, addr, len)); 771 } 772 return (error); 773 } 774 775 static uint8_t 776 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 777 { 778 uint8_t val; 779 780 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 781 return (0xff); 782 783 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 784 device_xname(sc->sc_dev), __func__, addr, val)); 785 return (val); 786 } 787 788 static uint16_t 789 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 790 { 791 uint8_t buf[2]; 792 uint16_t val; 793 794 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 795 return (0xffff); 796 797 val = LE_READ_2(&buf[0]); 798 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 799 device_xname(sc->sc_dev), __func__, addr, val)); 800 return (val); 801 } 802 803 static uint32_t 804 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 805 { 806 uint8_t buf[4]; 807 uint32_t val; 808 809 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 810 return (0xffffffff); 811 812 val = LE_READ_4(&buf[0]); 813 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 814 device_xname(sc->sc_dev), __func__, addr, val)); 815 return (val); 816 } 817 818 static int 819 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 820 { 821 struct r92c_fw_cmd cmd; 822 uint8_t *cp; 823 int fwcur; 824 int ntries; 825 826 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 827 device_xname(sc->sc_dev), __func__, id, buf, len)); 828 829 mutex_enter(&sc->sc_fwcmd_mtx); 830 fwcur = sc->fwcur; 831 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 832 mutex_exit(&sc->sc_fwcmd_mtx); 833 834 /* Wait for current FW box to be empty. */ 835 for (ntries = 0; ntries < 100; ntries++) { 836 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 837 break; 838 DELAY(1); 839 } 840 if (ntries == 100) { 841 aprint_error_dev(sc->sc_dev, 842 "could not send firmware command %d\n", id); 843 return (ETIMEDOUT); 844 } 845 846 memset(&cmd, 0, sizeof(cmd)); 847 KASSERT(len <= sizeof(cmd.msg)); 848 memcpy(cmd.msg, buf, len); 849 850 /* Write the first word last since that will trigger the FW. */ 851 cp = (uint8_t *)&cmd; 852 if (len >= 4) { 853 cmd.id = id | R92C_CMD_FLAG_EXT; 854 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 855 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 856 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 857 } else { 858 cmd.id = id; 859 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 860 } 861 862 return (0); 863 } 864 865 static void 866 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 867 { 868 869 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 870 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 871 } 872 873 static uint32_t 874 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 875 { 876 uint32_t reg[R92C_MAX_CHAINS], val; 877 878 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 879 if (chain != 0) { 880 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 881 } 882 883 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 884 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 885 DELAY(1000); 886 887 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 888 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 889 R92C_HSSI_PARAM2_READ_EDGE); 890 DELAY(1000); 891 892 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 893 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 894 DELAY(1000); 895 896 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 897 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 898 } else { 899 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 900 } 901 return (MS(val, R92C_LSSI_READBACK_DATA)); 902 } 903 904 static int 905 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 906 { 907 int ntries; 908 909 urtwn_write_4(sc, R92C_LLT_INIT, 910 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 911 SM(R92C_LLT_INIT_ADDR, addr) | 912 SM(R92C_LLT_INIT_DATA, data)); 913 /* Wait for write operation to complete. */ 914 for (ntries = 0; ntries < 20; ntries++) { 915 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 916 R92C_LLT_INIT_OP_NO_ACTIVE) { 917 /* Done */ 918 return (0); 919 } 920 DELAY(5); 921 } 922 return (ETIMEDOUT); 923 } 924 925 static uint8_t 926 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 927 { 928 uint32_t reg; 929 int ntries; 930 931 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 932 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 933 reg &= ~R92C_EFUSE_CTRL_VALID; 934 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 935 936 /* Wait for read operation to complete. */ 937 for (ntries = 0; ntries < 100; ntries++) { 938 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 939 if (reg & R92C_EFUSE_CTRL_VALID) { 940 /* Done */ 941 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 942 } 943 DELAY(5); 944 } 945 aprint_error_dev(sc->sc_dev, 946 "could not read efuse byte at address 0x%04x\n", addr); 947 return (0xff); 948 } 949 950 static void 951 urtwn_efuse_read(struct urtwn_softc *sc) 952 { 953 uint8_t *rom = (uint8_t *)&sc->rom; 954 uint32_t reg; 955 uint16_t addr = 0; 956 uint8_t off, msk; 957 int i; 958 959 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 960 961 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 962 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 963 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 964 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 965 } 966 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 967 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 968 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 969 reg | R92C_SYS_FUNC_EN_ELDR); 970 } 971 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 972 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 973 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 974 urtwn_write_2(sc, R92C_SYS_CLKR, 975 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 976 } 977 memset(&sc->rom, 0xff, sizeof(sc->rom)); 978 while (addr < 512) { 979 reg = urtwn_efuse_read_1(sc, addr); 980 if (reg == 0xff) 981 break; 982 addr++; 983 off = reg >> 4; 984 msk = reg & 0xf; 985 for (i = 0; i < 4; i++) { 986 if (msk & (1U << i)) 987 continue; 988 989 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 990 addr++; 991 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 992 addr++; 993 } 994 } 995 #ifdef URTWN_DEBUG 996 if (urtwn_debug & DBG_INIT) { 997 /* Dump ROM content. */ 998 printf("%s: %s", device_xname(sc->sc_dev), __func__); 999 for (i = 0; i < (int)sizeof(sc->rom); i++) 1000 printf(":%02x", rom[i]); 1001 printf("\n"); 1002 } 1003 #endif 1004 } 1005 1006 static int 1007 urtwn_read_chipid(struct urtwn_softc *sc) 1008 { 1009 uint32_t reg; 1010 1011 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1012 1013 sc->chip = 0; 1014 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1015 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1016 /* test chip, not supported */ 1017 return (EIO); 1018 } 1019 if (reg & R92C_SYS_CFG_TYPE_92C) { 1020 sc->chip |= URTWN_CHIP_92C; 1021 /* Check if it is a castrated 8192C. */ 1022 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1023 R92C_HPON_FSM_CHIP_BONDING_ID) == 1024 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1025 sc->chip |= URTWN_CHIP_92C_1T2R; 1026 } 1027 } 1028 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1029 sc->chip |= URTWN_CHIP_UMC; 1030 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1031 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1032 } 1033 } 1034 return (0); 1035 } 1036 1037 #ifdef URTWN_DEBUG 1038 static void 1039 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1040 { 1041 1042 aprint_normal_dev(sc->sc_dev, 1043 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1044 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1045 1046 aprint_normal_dev(sc->sc_dev, 1047 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1048 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1049 1050 aprint_normal_dev(sc->sc_dev, 1051 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1052 rp->macaddr[0], rp->macaddr[1], 1053 rp->macaddr[2], rp->macaddr[3], 1054 rp->macaddr[4], rp->macaddr[5]); 1055 1056 aprint_normal_dev(sc->sc_dev, 1057 "string %s, subcustomer_id 0x%x\n", 1058 rp->string, rp->subcustomer_id); 1059 1060 aprint_normal_dev(sc->sc_dev, 1061 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1062 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1063 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1064 1065 aprint_normal_dev(sc->sc_dev, 1066 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1067 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1068 rp->ht40_1s_tx_pwr[0][2], 1069 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1070 rp->ht40_1s_tx_pwr[1][2]); 1071 1072 aprint_normal_dev(sc->sc_dev, 1073 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1074 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1075 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1076 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1077 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1078 1079 aprint_normal_dev(sc->sc_dev, 1080 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1081 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1082 rp->ht20_tx_pwr_diff[2] & 0xf, 1083 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1084 rp->ht20_tx_pwr_diff[2] >> 4); 1085 1086 aprint_normal_dev(sc->sc_dev, 1087 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1088 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1089 rp->ofdm_tx_pwr_diff[2] & 0xf, 1090 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1091 rp->ofdm_tx_pwr_diff[2] >> 4); 1092 1093 aprint_normal_dev(sc->sc_dev, 1094 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1095 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1096 rp->ht40_max_pwr[2] & 0xf, 1097 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1098 rp->ht40_max_pwr[2] >> 4); 1099 1100 aprint_normal_dev(sc->sc_dev, 1101 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1102 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1103 rp->ht20_max_pwr[2] & 0xf, 1104 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1105 rp->ht20_max_pwr[2] >> 4); 1106 1107 aprint_normal_dev(sc->sc_dev, 1108 "xtal_calib %d, tssi %d %d, thermal %d\n", 1109 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1110 1111 aprint_normal_dev(sc->sc_dev, 1112 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1113 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1114 1115 aprint_normal_dev(sc->sc_dev, 1116 "channnel_plan %d, version %d customer_id 0x%x\n", 1117 rp->channel_plan, rp->version, rp->curstomer_id); 1118 } 1119 #endif 1120 1121 static void 1122 urtwn_read_rom(struct urtwn_softc *sc) 1123 { 1124 struct ieee80211com *ic = &sc->sc_ic; 1125 struct r92c_rom *rom = &sc->rom; 1126 1127 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1128 1129 /* Read full ROM image. */ 1130 urtwn_efuse_read(sc); 1131 #ifdef URTWN_DEBUG 1132 if (urtwn_debug & DBG_REG) 1133 urtwn_dump_rom(sc, rom); 1134 #endif 1135 1136 /* XXX Weird but this is what the vendor driver does. */ 1137 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1138 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1139 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1140 1141 DPRINTFN(DBG_INIT, 1142 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1143 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1144 sc->board_type, sc->regulatory)); 1145 1146 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1147 } 1148 1149 static int 1150 urtwn_media_change(struct ifnet *ifp) 1151 { 1152 #ifdef URTWN_DEBUG 1153 struct urtwn_softc *sc = ifp->if_softc; 1154 #endif 1155 int error; 1156 1157 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1158 1159 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1160 return (error); 1161 1162 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1163 (IFF_UP | IFF_RUNNING)) { 1164 urtwn_init(ifp); 1165 } 1166 return (0); 1167 } 1168 1169 /* 1170 * Initialize rate adaptation in firmware. 1171 */ 1172 static int 1173 urtwn_ra_init(struct urtwn_softc *sc) 1174 { 1175 static const uint8_t map[] = { 1176 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1177 }; 1178 struct ieee80211com *ic = &sc->sc_ic; 1179 struct ieee80211_node *ni = ic->ic_bss; 1180 struct ieee80211_rateset *rs = &ni->ni_rates; 1181 struct r92c_fw_cmd_macid_cfg cmd; 1182 uint32_t rates, basicrates; 1183 uint32_t mask; 1184 uint8_t mode; 1185 int maxrate, maxbasicrate, error, i, j; 1186 1187 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1188 1189 /* Get normal and basic rates mask. */ 1190 rates = basicrates = 0; 1191 maxrate = maxbasicrate = 0; 1192 for (i = 0; i < rs->rs_nrates; i++) { 1193 /* Convert 802.11 rate to HW rate index. */ 1194 for (j = 0; j < (int)__arraycount(map); j++) { 1195 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1196 break; 1197 } 1198 } 1199 if (j == __arraycount(map)) { 1200 /* Unknown rate, skip. */ 1201 continue; 1202 } 1203 1204 rates |= 1U << j; 1205 if (j > maxrate) { 1206 maxrate = j; 1207 } 1208 1209 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1210 basicrates |= 1U << j; 1211 if (j > maxbasicrate) { 1212 maxbasicrate = j; 1213 } 1214 } 1215 } 1216 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1217 mode = R92C_RAID_11B; 1218 } else { 1219 mode = R92C_RAID_11BG; 1220 } 1221 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1222 "maxrate=%x, maxbasicrate=%x\n", 1223 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1224 maxrate, maxbasicrate)); 1225 if (basicrates == 0) { 1226 basicrates |= 1; /* add 1Mbps */ 1227 } 1228 1229 /* Set rates mask for group addressed frames. */ 1230 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1231 mask = (mode << 28) | basicrates; 1232 cmd.mask[0] = (uint8_t)mask; 1233 cmd.mask[1] = (uint8_t)(mask >> 8); 1234 cmd.mask[2] = (uint8_t)(mask >> 16); 1235 cmd.mask[3] = (uint8_t)(mask >> 24); 1236 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1237 if (error != 0) { 1238 aprint_error_dev(sc->sc_dev, 1239 "could not add broadcast station\n"); 1240 return (error); 1241 } 1242 /* Set initial MRR rate. */ 1243 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", 1244 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1245 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1246 1247 /* Set rates mask for unicast frames. */ 1248 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1249 mask = (mode << 28) | rates; 1250 cmd.mask[0] = (uint8_t)mask; 1251 cmd.mask[1] = (uint8_t)(mask >> 8); 1252 cmd.mask[2] = (uint8_t)(mask >> 16); 1253 cmd.mask[3] = (uint8_t)(mask >> 24); 1254 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1255 if (error != 0) { 1256 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1257 return (error); 1258 } 1259 /* Set initial MRR rate. */ 1260 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), 1261 __func__, maxrate)); 1262 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1263 1264 /* Indicate highest supported rate. */ 1265 ni->ni_txrate = rs->rs_nrates - 1; 1266 1267 return (0); 1268 } 1269 1270 static int 1271 urtwn_get_nettype(struct urtwn_softc *sc) 1272 { 1273 struct ieee80211com *ic = &sc->sc_ic; 1274 int type; 1275 1276 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1277 1278 switch (ic->ic_opmode) { 1279 case IEEE80211_M_STA: 1280 type = R92C_CR_NETTYPE_INFRA; 1281 break; 1282 1283 case IEEE80211_M_IBSS: 1284 type = R92C_CR_NETTYPE_ADHOC; 1285 break; 1286 1287 default: 1288 type = R92C_CR_NETTYPE_NOLINK; 1289 break; 1290 } 1291 1292 return (type); 1293 } 1294 1295 static void 1296 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1297 { 1298 uint8_t reg; 1299 1300 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1301 __func__, type)); 1302 1303 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1304 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1305 } 1306 1307 static void 1308 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1309 { 1310 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1311 uint64_t tsf; 1312 1313 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1314 1315 /* Enable TSF synchronization. */ 1316 urtwn_write_1(sc, R92C_BCN_CTRL, 1317 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1318 1319 /* Correct TSF */ 1320 urtwn_write_1(sc, R92C_BCN_CTRL, 1321 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1322 1323 /* Set initial TSF. */ 1324 tsf = ni->ni_tstamp.tsf; 1325 tsf = le64toh(tsf); 1326 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1327 tsf -= IEEE80211_DUR_TU; 1328 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1329 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1330 1331 urtwn_write_1(sc, R92C_BCN_CTRL, 1332 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1333 } 1334 1335 static void 1336 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1337 { 1338 uint8_t reg; 1339 1340 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1341 __func__, led, on)); 1342 1343 if (led == URTWN_LED_LINK) { 1344 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1345 if (!on) { 1346 reg |= R92C_LEDCFG0_DIS; 1347 } 1348 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1349 sc->ledlink = on; /* Save LED state. */ 1350 } 1351 } 1352 1353 static void 1354 urtwn_calib_to(void *arg) 1355 { 1356 struct urtwn_softc *sc = arg; 1357 1358 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1359 1360 if (sc->sc_dying) 1361 return; 1362 1363 /* Do it in a process context. */ 1364 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1365 } 1366 1367 /* ARGSUSED */ 1368 static void 1369 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1370 { 1371 struct r92c_fw_cmd_rssi cmd; 1372 1373 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1374 1375 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1376 goto restart_timer; 1377 1378 if (sc->avg_pwdb != -1) { 1379 /* Indicate Rx signal strength to FW for rate adaptation. */ 1380 memset(&cmd, 0, sizeof(cmd)); 1381 cmd.macid = 0; /* BSS. */ 1382 cmd.pwdb = sc->avg_pwdb; 1383 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1384 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1385 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1386 } 1387 1388 /* Do temperature compensation. */ 1389 urtwn_temp_calib(sc); 1390 1391 restart_timer: 1392 if (!sc->sc_dying) { 1393 /* Restart calibration timer. */ 1394 callout_schedule(&sc->sc_calib_to, hz); 1395 } 1396 } 1397 1398 static void 1399 urtwn_next_scan(void *arg) 1400 { 1401 struct urtwn_softc *sc = arg; 1402 1403 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1404 1405 if (sc->sc_dying) 1406 return; 1407 1408 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1409 ieee80211_next_scan(&sc->sc_ic); 1410 } 1411 1412 static int 1413 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1414 { 1415 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1416 struct urtwn_cmd_newstate cmd; 1417 1418 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1419 device_xname(sc->sc_dev), __func__, 1420 ieee80211_state_name[nstate], nstate, arg)); 1421 1422 callout_stop(&sc->sc_scan_to); 1423 callout_stop(&sc->sc_calib_to); 1424 1425 /* Do it in a process context. */ 1426 cmd.state = nstate; 1427 cmd.arg = arg; 1428 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1429 return (0); 1430 } 1431 1432 static void 1433 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1434 { 1435 struct urtwn_cmd_newstate *cmd = arg; 1436 struct ieee80211com *ic = &sc->sc_ic; 1437 struct ieee80211_node *ni; 1438 enum ieee80211_state ostate = ic->ic_state; 1439 enum ieee80211_state nstate = cmd->state; 1440 uint32_t reg; 1441 uint8_t sifs_time; 1442 int s; 1443 1444 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1445 device_xname(sc->sc_dev), __func__, 1446 ieee80211_state_name[ostate], ostate, 1447 ieee80211_state_name[nstate], nstate)); 1448 1449 s = splnet(); 1450 1451 switch (ostate) { 1452 case IEEE80211_S_INIT: 1453 break; 1454 1455 case IEEE80211_S_SCAN: 1456 if (nstate != IEEE80211_S_SCAN) { 1457 /* 1458 * End of scanning 1459 */ 1460 /* flush 4-AC Queue after site_survey */ 1461 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1462 1463 /* Allow Rx from our BSSID only. */ 1464 urtwn_write_4(sc, R92C_RCR, 1465 urtwn_read_4(sc, R92C_RCR) | 1466 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1467 } 1468 break; 1469 1470 case IEEE80211_S_AUTH: 1471 case IEEE80211_S_ASSOC: 1472 break; 1473 1474 case IEEE80211_S_RUN: 1475 /* Turn link LED off. */ 1476 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1477 1478 /* Set media status to 'No Link'. */ 1479 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1480 1481 /* Stop Rx of data frames. */ 1482 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1483 1484 /* Reset TSF. */ 1485 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1486 1487 /* Disable TSF synchronization. */ 1488 urtwn_write_1(sc, R92C_BCN_CTRL, 1489 urtwn_read_1(sc, R92C_BCN_CTRL) | 1490 R92C_BCN_CTRL_DIS_TSF_UDT0); 1491 1492 /* Back to 20MHz mode */ 1493 urtwn_set_chan(sc, ic->ic_bss->ni_chan, 1494 IEEE80211_HTINFO_2NDCHAN_NONE); 1495 1496 if (ic->ic_opmode == IEEE80211_M_IBSS || 1497 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1498 /* Stop BCN */ 1499 urtwn_write_1(sc, R92C_BCN_CTRL, 1500 urtwn_read_1(sc, R92C_BCN_CTRL) & 1501 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1502 } 1503 1504 /* Reset EDCA parameters. */ 1505 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1506 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1507 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1508 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1509 1510 /* flush all cam entries */ 1511 urtwn_cam_init(sc); 1512 break; 1513 } 1514 1515 switch (nstate) { 1516 case IEEE80211_S_INIT: 1517 /* Turn link LED off. */ 1518 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1519 break; 1520 1521 case IEEE80211_S_SCAN: 1522 if (ostate != IEEE80211_S_SCAN) { 1523 /* 1524 * Begin of scanning 1525 */ 1526 1527 /* Set gain for scanning. */ 1528 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1529 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1530 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1531 1532 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1533 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1534 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1535 1536 /* Set media status to 'No Link'. */ 1537 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1538 1539 /* Allow Rx from any BSSID. */ 1540 urtwn_write_4(sc, R92C_RCR, 1541 urtwn_read_4(sc, R92C_RCR) & 1542 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1543 1544 /* Stop Rx of data frames. */ 1545 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1546 1547 /* Disable update TSF */ 1548 urtwn_write_1(sc, R92C_BCN_CTRL, 1549 urtwn_read_1(sc, R92C_BCN_CTRL) | 1550 R92C_BCN_CTRL_DIS_TSF_UDT0); 1551 } 1552 1553 /* Make link LED blink during scan. */ 1554 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1555 1556 /* Pause AC Tx queues. */ 1557 urtwn_write_1(sc, R92C_TXPAUSE, 1558 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1559 1560 urtwn_set_chan(sc, ic->ic_curchan, 1561 IEEE80211_HTINFO_2NDCHAN_NONE); 1562 1563 /* Start periodic scan. */ 1564 if (!sc->sc_dying) 1565 callout_schedule(&sc->sc_scan_to, hz / 5); 1566 break; 1567 1568 case IEEE80211_S_AUTH: 1569 /* Set initial gain under link. */ 1570 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1571 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1572 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1573 1574 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1575 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1576 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1577 1578 /* Set media status to 'No Link'. */ 1579 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1580 1581 /* Allow Rx from any BSSID. */ 1582 urtwn_write_4(sc, R92C_RCR, 1583 urtwn_read_4(sc, R92C_RCR) & 1584 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1585 1586 urtwn_set_chan(sc, ic->ic_curchan, 1587 IEEE80211_HTINFO_2NDCHAN_NONE); 1588 break; 1589 1590 case IEEE80211_S_ASSOC: 1591 break; 1592 1593 case IEEE80211_S_RUN: 1594 ni = ic->ic_bss; 1595 1596 /* XXX: Set 20MHz mode */ 1597 urtwn_set_chan(sc, ic->ic_curchan, 1598 IEEE80211_HTINFO_2NDCHAN_NONE); 1599 1600 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1601 /* Back to 20MHz mode */ 1602 urtwn_set_chan(sc, ic->ic_ibss_chan, 1603 IEEE80211_HTINFO_2NDCHAN_NONE); 1604 1605 /* Enable Rx of data frames. */ 1606 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1607 1608 /* Turn link LED on. */ 1609 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1610 break; 1611 } 1612 1613 /* Set media status to 'Associated'. */ 1614 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1615 1616 /* Set BSSID. */ 1617 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1618 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1619 1620 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1621 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1622 } else { 1623 /* 802.11b/g */ 1624 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1625 } 1626 1627 /* Enable Rx of data frames. */ 1628 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1629 1630 /* Set beacon interval. */ 1631 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1632 1633 if (ic->ic_opmode == IEEE80211_M_STA) { 1634 /* Allow Rx from our BSSID only. */ 1635 urtwn_write_4(sc, R92C_RCR, 1636 urtwn_read_4(sc, R92C_RCR) | 1637 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1638 1639 /* Enable TSF synchronization. */ 1640 urtwn_tsf_sync_enable(sc); 1641 } 1642 1643 sifs_time = 10; 1644 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1645 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1646 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1647 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1648 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1649 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1650 1651 /* Intialize rate adaptation. */ 1652 urtwn_ra_init(sc); 1653 1654 /* Turn link LED on. */ 1655 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1656 1657 /* Reset average RSSI. */ 1658 sc->avg_pwdb = -1; 1659 1660 /* Reset temperature calibration state machine. */ 1661 sc->thcal_state = 0; 1662 sc->thcal_lctemp = 0; 1663 1664 /* Start periodic calibration. */ 1665 if (!sc->sc_dying) 1666 callout_schedule(&sc->sc_calib_to, hz); 1667 break; 1668 } 1669 1670 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1671 1672 splx(s); 1673 } 1674 1675 static int 1676 urtwn_wme_update(struct ieee80211com *ic) 1677 { 1678 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1679 1680 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1681 1682 /* don't override default WME values if WME is not actually enabled */ 1683 if (!(ic->ic_flags & IEEE80211_F_WME)) 1684 return (0); 1685 1686 /* Do it in a process context. */ 1687 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1688 return (0); 1689 } 1690 1691 static void 1692 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1693 { 1694 static const uint16_t ac2reg[WME_NUM_AC] = { 1695 R92C_EDCA_BE_PARAM, 1696 R92C_EDCA_BK_PARAM, 1697 R92C_EDCA_VI_PARAM, 1698 R92C_EDCA_VO_PARAM 1699 }; 1700 struct ieee80211com *ic = &sc->sc_ic; 1701 const struct wmeParams *wmep; 1702 int ac, aifs, slottime; 1703 int s; 1704 1705 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1706 __func__)); 1707 1708 s = splnet(); 1709 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1710 for (ac = 0; ac < WME_NUM_AC; ac++) { 1711 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1712 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1713 aifs = wmep->wmep_aifsn * slottime + 10; 1714 urtwn_write_4(sc, ac2reg[ac], 1715 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1716 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1717 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1718 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1719 } 1720 splx(s); 1721 } 1722 1723 static void 1724 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1725 { 1726 int pwdb; 1727 1728 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1729 device_xname(sc->sc_dev), __func__, rate, rssi)); 1730 1731 /* Convert antenna signal to percentage. */ 1732 if (rssi <= -100 || rssi >= 20) 1733 pwdb = 0; 1734 else if (rssi >= 0) 1735 pwdb = 100; 1736 else 1737 pwdb = 100 + rssi; 1738 if (rate <= 3) { 1739 /* CCK gain is smaller than OFDM/MCS gain. */ 1740 pwdb += 6; 1741 if (pwdb > 100) 1742 pwdb = 100; 1743 if (pwdb <= 14) 1744 pwdb -= 4; 1745 else if (pwdb <= 26) 1746 pwdb -= 8; 1747 else if (pwdb <= 34) 1748 pwdb -= 6; 1749 else if (pwdb <= 42) 1750 pwdb -= 2; 1751 } 1752 if (sc->avg_pwdb == -1) /* Init. */ 1753 sc->avg_pwdb = pwdb; 1754 else if (sc->avg_pwdb < pwdb) 1755 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1756 else 1757 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1758 1759 DPRINTFN(DBG_RF, ("%s: %s: PWDB=%d EMA=%d\n", device_xname(sc->sc_dev), 1760 __func__, pwdb, sc->avg_pwdb)); 1761 } 1762 1763 static int8_t 1764 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1765 { 1766 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1767 struct r92c_rx_phystat *phy; 1768 struct r92c_rx_cck *cck; 1769 uint8_t rpt; 1770 int8_t rssi; 1771 1772 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1773 __func__, rate)); 1774 1775 if (rate <= 3) { 1776 cck = (struct r92c_rx_cck *)physt; 1777 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1778 rpt = (cck->agc_rpt >> 5) & 0x3; 1779 rssi = (cck->agc_rpt & 0x1f) << 1; 1780 } else { 1781 rpt = (cck->agc_rpt >> 6) & 0x3; 1782 rssi = cck->agc_rpt & 0x3e; 1783 } 1784 rssi = cckoff[rpt] - rssi; 1785 } else { /* OFDM/HT. */ 1786 phy = (struct r92c_rx_phystat *)physt; 1787 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1788 } 1789 return (rssi); 1790 } 1791 1792 static void 1793 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1794 { 1795 struct ieee80211com *ic = &sc->sc_ic; 1796 struct ifnet *ifp = ic->ic_ifp; 1797 struct ieee80211_frame *wh; 1798 struct ieee80211_node *ni; 1799 struct r92c_rx_stat *stat; 1800 uint32_t rxdw0, rxdw3; 1801 struct mbuf *m; 1802 uint8_t rate; 1803 int8_t rssi = 0; 1804 int s, infosz; 1805 1806 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1807 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1808 1809 stat = (struct r92c_rx_stat *)buf; 1810 rxdw0 = le32toh(stat->rxdw0); 1811 rxdw3 = le32toh(stat->rxdw3); 1812 1813 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1814 /* 1815 * This should not happen since we setup our Rx filter 1816 * to not receive these frames. 1817 */ 1818 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1819 device_xname(sc->sc_dev), __func__)); 1820 ifp->if_ierrors++; 1821 return; 1822 } 1823 if (__predict_false(pktlen < (int)sizeof(*wh))) { 1824 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1825 device_xname(sc->sc_dev), __func__, pktlen)); 1826 ic->ic_stats.is_rx_tooshort++; 1827 ifp->if_ierrors++; 1828 return; 1829 } 1830 if (__predict_false(pktlen > MCLBYTES)) { 1831 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1832 device_xname(sc->sc_dev), __func__, pktlen)); 1833 ifp->if_ierrors++; 1834 return; 1835 } 1836 1837 rate = MS(rxdw3, R92C_RXDW3_RATE); 1838 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1839 1840 /* Get RSSI from PHY status descriptor if present. */ 1841 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1842 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1843 /* Update our average RSSI. */ 1844 urtwn_update_avgrssi(sc, rate, rssi); 1845 } 1846 1847 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1848 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1849 1850 MGETHDR(m, M_DONTWAIT, MT_DATA); 1851 if (__predict_false(m == NULL)) { 1852 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1853 ic->ic_stats.is_rx_nobuf++; 1854 ifp->if_ierrors++; 1855 return; 1856 } 1857 if (pktlen > (int)MHLEN) { 1858 MCLGET(m, M_DONTWAIT); 1859 if (__predict_false(!(m->m_flags & M_EXT))) { 1860 aprint_error_dev(sc->sc_dev, 1861 "couldn't allocate rx mbuf cluster\n"); 1862 m_freem(m); 1863 ic->ic_stats.is_rx_nobuf++; 1864 ifp->if_ierrors++; 1865 return; 1866 } 1867 } 1868 1869 /* Finalize mbuf. */ 1870 m->m_pkthdr.rcvif = ifp; 1871 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1872 memcpy(mtod(m, uint8_t *), wh, pktlen); 1873 m->m_pkthdr.len = m->m_len = pktlen; 1874 1875 s = splnet(); 1876 if (__predict_false(sc->sc_drvbpf != NULL)) { 1877 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1878 1879 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1880 if (!(rxdw3 & R92C_RXDW3_HT)) { 1881 switch (rate) { 1882 /* CCK. */ 1883 case 0: tap->wr_rate = 2; break; 1884 case 1: tap->wr_rate = 4; break; 1885 case 2: tap->wr_rate = 11; break; 1886 case 3: tap->wr_rate = 22; break; 1887 /* OFDM. */ 1888 case 4: tap->wr_rate = 12; break; 1889 case 5: tap->wr_rate = 18; break; 1890 case 6: tap->wr_rate = 24; break; 1891 case 7: tap->wr_rate = 36; break; 1892 case 8: tap->wr_rate = 48; break; 1893 case 9: tap->wr_rate = 72; break; 1894 case 10: tap->wr_rate = 96; break; 1895 case 11: tap->wr_rate = 108; break; 1896 } 1897 } else if (rate >= 12) { /* MCS0~15. */ 1898 /* Bit 7 set means HT MCS instead of rate. */ 1899 tap->wr_rate = 0x80 | (rate - 12); 1900 } 1901 tap->wr_dbm_antsignal = rssi; 1902 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1903 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1904 1905 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1906 } 1907 1908 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1909 1910 /* push the frame up to the 802.11 stack */ 1911 ieee80211_input(ic, m, ni, rssi, 0); 1912 1913 /* Node is no longer needed. */ 1914 ieee80211_free_node(ni); 1915 1916 splx(s); 1917 } 1918 1919 static void 1920 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1921 { 1922 struct urtwn_rx_data *data = priv; 1923 struct urtwn_softc *sc = data->sc; 1924 struct r92c_rx_stat *stat; 1925 uint32_t rxdw0; 1926 uint8_t *buf; 1927 int len, totlen, pktlen, infosz, npkts; 1928 1929 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 1930 device_xname(sc->sc_dev), __func__, status)); 1931 1932 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1933 if (status == USBD_STALLED) 1934 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1935 else if (status != USBD_CANCELLED) 1936 goto resubmit; 1937 return; 1938 } 1939 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1940 1941 if (__predict_false(len < (int)sizeof(*stat))) { 1942 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 1943 device_xname(sc->sc_dev), __func__, len)); 1944 goto resubmit; 1945 } 1946 buf = data->buf; 1947 1948 /* Get the number of encapsulated frames. */ 1949 stat = (struct r92c_rx_stat *)buf; 1950 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 1951 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 1952 device_xname(sc->sc_dev), __func__, npkts)); 1953 1954 /* Process all of them. */ 1955 while (npkts-- > 0) { 1956 if (__predict_false(len < (int)sizeof(*stat))) { 1957 DPRINTFN(DBG_RX, 1958 ("%s: %s: len(%d) is short than header\n", 1959 device_xname(sc->sc_dev), __func__, len)); 1960 break; 1961 } 1962 stat = (struct r92c_rx_stat *)buf; 1963 rxdw0 = le32toh(stat->rxdw0); 1964 1965 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1966 if (__predict_false(pktlen == 0)) { 1967 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 1968 device_xname(sc->sc_dev), __func__)); 1969 break; 1970 } 1971 1972 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1973 1974 /* Make sure everything fits in xfer. */ 1975 totlen = sizeof(*stat) + infosz + pktlen; 1976 if (__predict_false(totlen > len)) { 1977 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 1978 device_xname(sc->sc_dev), __func__, totlen, 1979 (int)sizeof(*stat), infosz, pktlen, len)); 1980 break; 1981 } 1982 1983 /* Process 802.11 frame. */ 1984 urtwn_rx_frame(sc, buf, pktlen); 1985 1986 /* Next chunk is 128-byte aligned. */ 1987 totlen = roundup2(totlen, 128); 1988 buf += totlen; 1989 len -= totlen; 1990 } 1991 1992 resubmit: 1993 /* Setup a new transfer. */ 1994 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1995 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1996 (void)usbd_transfer(xfer); 1997 } 1998 1999 static void 2000 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2001 { 2002 struct urtwn_tx_data *data = priv; 2003 struct urtwn_softc *sc = data->sc; 2004 struct ifnet *ifp = &sc->sc_if; 2005 int s; 2006 2007 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2008 device_xname(sc->sc_dev), __func__, status)); 2009 2010 mutex_enter(&sc->sc_tx_mtx); 2011 /* Put this Tx buffer back to our free list. */ 2012 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2013 mutex_exit(&sc->sc_tx_mtx); 2014 2015 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2016 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2017 if (status == USBD_STALLED) 2018 usbd_clear_endpoint_stall_async(data->pipe); 2019 ifp->if_oerrors++; 2020 } 2021 return; 2022 } 2023 2024 ifp->if_opackets++; 2025 2026 s = splnet(); 2027 sc->tx_timer = 0; 2028 ifp->if_flags &= ~IFF_OACTIVE; 2029 splx(s); 2030 2031 urtwn_start(ifp); 2032 } 2033 2034 static int 2035 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2036 { 2037 struct ieee80211com *ic = &sc->sc_ic; 2038 struct ieee80211_frame *wh; 2039 struct ieee80211_key *k = NULL; 2040 struct urtwn_tx_data *data; 2041 struct r92c_tx_desc *txd; 2042 usbd_pipe_handle pipe; 2043 uint16_t seq, sum; 2044 uint8_t raid, type, tid, qid; 2045 int i, s, hasqos, xferlen, padsize, error; 2046 2047 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2048 2049 wh = mtod(m, struct ieee80211_frame *); 2050 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2051 2052 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2053 k = ieee80211_crypto_encap(ic, ni, m); 2054 if (k == NULL) { 2055 m_freem(m); 2056 return (ENOBUFS); 2057 } 2058 /* packet header may have moved, reset our local pointer */ 2059 wh = mtod(m, struct ieee80211_frame *); 2060 } 2061 2062 if (__predict_false(sc->sc_drvbpf != NULL)) { 2063 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2064 2065 tap->wt_flags = 0; 2066 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2067 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2068 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2069 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2070 2071 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2072 } 2073 2074 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2075 /* data frames in 11n mode */ 2076 struct ieee80211_qosframe *qwh = (void *)wh; 2077 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2078 qid = TID_TO_WME_AC(tid); 2079 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2080 /* Use AC_VO for management frames. */ 2081 qid = WME_AC_VO; 2082 tid = 0; /* compiler happy */ 2083 } else { 2084 /* non-qos data frames */ 2085 tid = R92C_TXDW1_QSEL_BE; 2086 qid = WME_AC_BE; 2087 } 2088 2089 /* Get the USB pipe to use for this AC. */ 2090 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2091 2092 /* Grab a Tx buffer from our free list. */ 2093 mutex_enter(&sc->sc_tx_mtx); 2094 data = TAILQ_FIRST(&sc->tx_free_list); 2095 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2096 mutex_exit(&sc->sc_tx_mtx); 2097 2098 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2099 padsize = 8; 2100 else 2101 padsize = 0; 2102 2103 /* Fill Tx descriptor. */ 2104 txd = (struct r92c_tx_desc *)data->buf; 2105 memset(txd, 0, sizeof(*txd) + padsize); 2106 2107 txd->txdw0 |= htole32( 2108 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2109 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2110 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2111 2112 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2113 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2114 2115 /* fix pad field */ 2116 if (padsize > 0) { 2117 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", 2118 device_xname(sc->sc_dev), __func__, padsize)); 2119 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2120 } 2121 2122 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2123 type == IEEE80211_FC0_TYPE_DATA) { 2124 if (ic->ic_curmode == IEEE80211_MODE_11B) 2125 raid = R92C_RAID_11B; 2126 else 2127 raid = R92C_RAID_11BG; 2128 DPRINTFN(DBG_TX, 2129 ("%s: %s: data packet: tid=%d, raid=%d\n", 2130 device_xname(sc->sc_dev), __func__, tid, raid)); 2131 2132 txd->txdw1 |= htole32( 2133 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2134 SM(R92C_TXDW1_QSEL, tid) | 2135 SM(R92C_TXDW1_RAID, raid) | 2136 R92C_TXDW1_AGGBK); 2137 2138 if (hasqos) { 2139 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2140 } 2141 2142 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2143 /* for 11g */ 2144 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2145 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2146 R92C_TXDW4_HWRTSEN); 2147 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2148 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2149 R92C_TXDW4_HWRTSEN); 2150 } 2151 } 2152 /* Send RTS at OFDM24. */ 2153 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2154 txd->txdw5 |= htole32(0x0001ff00); 2155 /* Send data at OFDM54. */ 2156 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2157 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2158 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2159 device_xname(sc->sc_dev), __func__)); 2160 txd->txdw1 |= htole32( 2161 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2162 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2163 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2164 2165 /* Force CCK1. */ 2166 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2167 /* Use 1Mbps */ 2168 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2169 } else { 2170 /* broadcast or multicast packets */ 2171 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2172 device_xname(sc->sc_dev), __func__)); 2173 txd->txdw1 |= htole32( 2174 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2175 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2176 2177 /* Force CCK1. */ 2178 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2179 /* Use 1Mbps */ 2180 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2181 } 2182 2183 /* Set sequence number */ 2184 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2185 txd->txdseq |= htole16(seq); 2186 2187 if (!hasqos) { 2188 /* Use HW sequence numbering for non-QoS frames. */ 2189 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2190 txd->txdseq |= htole16(0x8000); /* WTF? */ 2191 } 2192 2193 /* Compute Tx descriptor checksum. */ 2194 sum = 0; 2195 for (i = 0; i < (int)sizeof(*txd) / 2; i++) 2196 sum ^= ((uint16_t *)txd)[i]; 2197 txd->txdsum = sum; /* NB: already little endian. */ 2198 2199 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2200 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2201 m_freem(m); 2202 2203 s = splnet(); 2204 data->pipe = pipe; 2205 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2206 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2207 urtwn_txeof); 2208 error = usbd_transfer(data->xfer); 2209 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2210 error != USBD_IN_PROGRESS)) { 2211 splx(s); 2212 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2213 device_xname(sc->sc_dev), __func__, error)); 2214 mutex_enter(&sc->sc_tx_mtx); 2215 /* Put this Tx buffer back to our free list. */ 2216 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2217 mutex_exit(&sc->sc_tx_mtx); 2218 return (error); 2219 } 2220 splx(s); 2221 ieee80211_free_node(ni); 2222 return (0); 2223 } 2224 2225 static void 2226 urtwn_start(struct ifnet *ifp) 2227 { 2228 struct urtwn_softc *sc = ifp->if_softc; 2229 struct ieee80211com *ic = &sc->sc_ic; 2230 struct ether_header *eh; 2231 struct ieee80211_node *ni; 2232 struct mbuf *m; 2233 2234 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2235 2236 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2237 return; 2238 2239 for (;;) { 2240 mutex_enter(&sc->sc_tx_mtx); 2241 if (TAILQ_EMPTY(&sc->tx_free_list)) { 2242 mutex_exit(&sc->sc_tx_mtx); 2243 ifp->if_flags |= IFF_OACTIVE; 2244 break; 2245 } 2246 mutex_exit(&sc->sc_tx_mtx); 2247 2248 /* Send pending management frames first. */ 2249 IF_DEQUEUE(&ic->ic_mgtq, m); 2250 if (m != NULL) { 2251 ni = (void *)m->m_pkthdr.rcvif; 2252 m->m_pkthdr.rcvif = NULL; 2253 goto sendit; 2254 } 2255 if (ic->ic_state != IEEE80211_S_RUN) 2256 break; 2257 2258 /* Encapsulate and send data frames. */ 2259 IFQ_DEQUEUE(&ifp->if_snd, m); 2260 if (m == NULL) 2261 break; 2262 if (m->m_len < (int)sizeof(*eh) && 2263 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2264 ifp->if_oerrors++; 2265 continue; 2266 } 2267 eh = mtod(m, struct ether_header *); 2268 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2269 if (ni == NULL) { 2270 m_freem(m); 2271 ifp->if_oerrors++; 2272 continue; 2273 } 2274 2275 bpf_mtap(ifp, m); 2276 2277 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2278 ieee80211_free_node(ni); 2279 ifp->if_oerrors++; 2280 continue; 2281 } 2282 sendit: 2283 bpf_mtap3(ic->ic_rawbpf, m); 2284 2285 if (urtwn_tx(sc, m, ni) != 0) { 2286 ieee80211_free_node(ni); 2287 ifp->if_oerrors++; 2288 continue; 2289 } 2290 2291 sc->tx_timer = 5; 2292 ifp->if_timer = 1; 2293 } 2294 } 2295 2296 static void 2297 urtwn_watchdog(struct ifnet *ifp) 2298 { 2299 struct urtwn_softc *sc = ifp->if_softc; 2300 2301 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2302 2303 ifp->if_timer = 0; 2304 2305 if (sc->tx_timer > 0) { 2306 if (--sc->tx_timer == 0) { 2307 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2308 /* urtwn_init(ifp); XXX needs a process context! */ 2309 ifp->if_oerrors++; 2310 return; 2311 } 2312 ifp->if_timer = 1; 2313 } 2314 ieee80211_watchdog(&sc->sc_ic); 2315 } 2316 2317 static int 2318 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2319 { 2320 struct urtwn_softc *sc = ifp->if_softc; 2321 struct ieee80211com *ic = &sc->sc_ic; 2322 struct ifaddr *ifa; 2323 int s, error = 0; 2324 2325 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2326 device_xname(sc->sc_dev), __func__, cmd, data)); 2327 2328 s = splnet(); 2329 2330 switch (cmd) { 2331 case SIOCSIFADDR: 2332 ifa = (struct ifaddr *)data; 2333 ifp->if_flags |= IFF_UP; 2334 #ifdef INET 2335 if (ifa->ifa_addr->sa_family == AF_INET) 2336 arp_ifinit(&ic->ic_ac, ifa); 2337 #endif 2338 /*FALLTHROUGH*/ 2339 case SIOCSIFFLAGS: 2340 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2341 break; 2342 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2343 case IFF_UP|IFF_RUNNING: 2344 break; 2345 case IFF_UP: 2346 urtwn_init(ifp); 2347 break; 2348 case IFF_RUNNING: 2349 urtwn_stop(ifp, 1); 2350 break; 2351 case 0: 2352 break; 2353 } 2354 break; 2355 2356 case SIOCADDMULTI: 2357 case SIOCDELMULTI: 2358 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2359 /* setup multicast filter, etc */ 2360 error = 0; 2361 } 2362 break; 2363 2364 case SIOCS80211CHANNEL: 2365 error = ieee80211_ioctl(ic, cmd, data); 2366 if (error == ENETRESET && 2367 ic->ic_opmode == IEEE80211_M_MONITOR) { 2368 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2369 (IFF_UP | IFF_RUNNING)) { 2370 urtwn_set_chan(sc, ic->ic_ibss_chan, 2371 IEEE80211_HTINFO_2NDCHAN_NONE); 2372 } 2373 error = 0; 2374 } 2375 break; 2376 2377 default: 2378 error = ieee80211_ioctl(ic, cmd, data); 2379 break; 2380 } 2381 if (error == ENETRESET) { 2382 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2383 (IFF_UP | IFF_RUNNING)) { 2384 urtwn_init(ifp); 2385 } 2386 error = 0; 2387 } 2388 2389 splx(s); 2390 2391 return (error); 2392 } 2393 2394 static int 2395 urtwn_power_on(struct urtwn_softc *sc) 2396 { 2397 uint32_t reg; 2398 int ntries; 2399 2400 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2401 2402 /* Wait for autoload done bit. */ 2403 for (ntries = 0; ntries < 1000; ntries++) { 2404 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2405 break; 2406 DELAY(5); 2407 } 2408 if (ntries == 1000) { 2409 aprint_error_dev(sc->sc_dev, 2410 "timeout waiting for chip autoload\n"); 2411 return (ETIMEDOUT); 2412 } 2413 2414 /* Unlock ISO/CLK/Power control register. */ 2415 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2416 /* Move SPS into PWM mode. */ 2417 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2418 DELAY(100); 2419 2420 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2421 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2422 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2423 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2424 DELAY(100); 2425 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2426 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2427 ~R92C_SYS_ISO_CTRL_MD2PP); 2428 } 2429 2430 /* Auto enable WLAN. */ 2431 urtwn_write_2(sc, R92C_APS_FSMCO, 2432 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2433 for (ntries = 0; ntries < 1000; ntries++) { 2434 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2435 R92C_APS_FSMCO_APFM_ONMAC)) 2436 break; 2437 DELAY(5); 2438 } 2439 if (ntries == 1000) { 2440 aprint_error_dev(sc->sc_dev, 2441 "timeout waiting for MAC auto ON\n"); 2442 return (ETIMEDOUT); 2443 } 2444 2445 /* Enable radio, GPIO and LED functions. */ 2446 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2447 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2448 urtwn_write_2(sc, R92C_APS_FSMCO, 2449 R92C_APS_FSMCO_AFSM_HSUS | 2450 R92C_APS_FSMCO_PDN_EN | 2451 R92C_APS_FSMCO_PFM_ALDN); 2452 2453 /* Release RF digital isolation. */ 2454 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2455 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2456 2457 /* Initialize MAC. */ 2458 urtwn_write_1(sc, R92C_APSD_CTRL, 2459 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2460 for (ntries = 0; ntries < 200; ntries++) { 2461 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2462 R92C_APSD_CTRL_OFF_STATUS)) 2463 break; 2464 DELAY(5); 2465 } 2466 if (ntries == 200) { 2467 aprint_error_dev(sc->sc_dev, 2468 "timeout waiting for MAC initialization\n"); 2469 return (ETIMEDOUT); 2470 } 2471 2472 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2473 reg = urtwn_read_2(sc, R92C_CR); 2474 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2475 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2476 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2477 R92C_CR_ENSEC; 2478 urtwn_write_2(sc, R92C_CR, reg); 2479 2480 urtwn_write_1(sc, 0xfe10, 0x19); 2481 return (0); 2482 } 2483 2484 static int 2485 urtwn_llt_init(struct urtwn_softc *sc) 2486 { 2487 int i, error; 2488 2489 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2490 2491 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2492 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2493 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2494 return (error); 2495 } 2496 /* NB: 0xff indicates end-of-list. */ 2497 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2498 return (error); 2499 /* 2500 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2501 * as ring buffer. 2502 */ 2503 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2504 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2505 return (error); 2506 } 2507 /* Make the last page point to the beginning of the ring buffer. */ 2508 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2509 return (error); 2510 } 2511 2512 static void 2513 urtwn_fw_reset(struct urtwn_softc *sc) 2514 { 2515 uint16_t reg; 2516 int ntries; 2517 2518 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2519 2520 /* Tell 8051 to reset itself. */ 2521 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2522 2523 /* Wait until 8051 resets by itself. */ 2524 for (ntries = 0; ntries < 100; ntries++) { 2525 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2526 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2527 return; 2528 DELAY(50); 2529 } 2530 /* Force 8051 reset. */ 2531 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2532 } 2533 2534 static int 2535 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2536 { 2537 uint32_t reg; 2538 int off, mlen, error = 0; 2539 2540 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2541 device_xname(sc->sc_dev), __func__, page, buf, len)); 2542 2543 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2544 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2545 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2546 2547 off = R92C_FW_START_ADDR; 2548 while (len > 0) { 2549 if (len > 196) 2550 mlen = 196; 2551 else if (len > 4) 2552 mlen = 4; 2553 else 2554 mlen = 1; 2555 error = urtwn_write_region(sc, off, buf, mlen); 2556 if (error != 0) 2557 break; 2558 off += mlen; 2559 buf += mlen; 2560 len -= mlen; 2561 } 2562 return (error); 2563 } 2564 2565 static int 2566 urtwn_load_firmware(struct urtwn_softc *sc) 2567 { 2568 firmware_handle_t fwh; 2569 const struct r92c_fw_hdr *hdr; 2570 const char *name; 2571 u_char *fw, *ptr; 2572 size_t len; 2573 uint32_t reg; 2574 int mlen, ntries, page, error; 2575 2576 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2577 2578 /* Read firmware image from the filesystem. */ 2579 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2580 URTWN_CHIP_UMC_A_CUT) 2581 name = "urtwn-rtl8192cfwU"; 2582 else 2583 name = "urtwn-rtl8192cfwT"; 2584 if ((error = firmware_open("urtwn", name, &fwh)) != 0) { 2585 aprint_error_dev(sc->sc_dev, 2586 "failed loadfirmware of file %s (error %d)\n", name, error); 2587 return (error); 2588 } 2589 len = firmware_get_size(fwh); 2590 fw = firmware_malloc(len); 2591 if (fw == NULL) { 2592 aprint_error_dev(sc->sc_dev, 2593 "failed to allocate firmware memory\n"); 2594 firmware_close(fwh); 2595 return (ENOMEM); 2596 } 2597 error = firmware_read(fwh, 0, fw, len); 2598 firmware_close(fwh); 2599 if (error != 0) { 2600 aprint_error_dev(sc->sc_dev, 2601 "failed to read firmware (error %d)\n", error); 2602 firmware_free(fw, 0); 2603 return (error); 2604 } 2605 2606 ptr = fw; 2607 hdr = (const struct r92c_fw_hdr *)ptr; 2608 /* Check if there is a valid FW header and skip it. */ 2609 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2610 (le16toh(hdr->signature) >> 4) == 0x92c) { 2611 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2612 device_xname(sc->sc_dev), __func__, 2613 le16toh(hdr->version), le16toh(hdr->subversion), 2614 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2615 ptr += sizeof(*hdr); 2616 len -= sizeof(*hdr); 2617 } 2618 2619 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2620 urtwn_fw_reset(sc); 2621 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2622 } 2623 2624 /* download enabled */ 2625 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2626 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2627 R92C_SYS_FUNC_EN_CPUEN); 2628 urtwn_write_1(sc, R92C_MCUFWDL, 2629 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2630 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2631 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2632 2633 /* download firmware */ 2634 for (page = 0; len > 0; page++) { 2635 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2636 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2637 if (error != 0) { 2638 aprint_error_dev(sc->sc_dev, 2639 "could not load firmware page %d\n", page); 2640 goto fail; 2641 } 2642 ptr += mlen; 2643 len -= mlen; 2644 } 2645 2646 /* download disable */ 2647 urtwn_write_1(sc, R92C_MCUFWDL, 2648 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2649 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2650 2651 /* Wait for checksum report. */ 2652 for (ntries = 0; ntries < 1000; ntries++) { 2653 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2654 break; 2655 DELAY(5); 2656 } 2657 if (ntries == 1000) { 2658 aprint_error_dev(sc->sc_dev, 2659 "timeout waiting for checksum report\n"); 2660 error = ETIMEDOUT; 2661 goto fail; 2662 } 2663 2664 /* Wait for firmware readiness. */ 2665 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2666 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2667 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2668 for (ntries = 0; ntries < 1000; ntries++) { 2669 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2670 break; 2671 DELAY(5); 2672 } 2673 if (ntries == 1000) { 2674 aprint_error_dev(sc->sc_dev, 2675 "timeout waiting for firmware readiness\n"); 2676 error = ETIMEDOUT; 2677 goto fail; 2678 } 2679 fail: 2680 firmware_free(fw, 0); 2681 return (error); 2682 } 2683 2684 static int 2685 urtwn_dma_init(struct urtwn_softc *sc) 2686 { 2687 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2688 uint32_t reg; 2689 int error; 2690 2691 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2692 2693 /* Initialize LLT table. */ 2694 error = urtwn_llt_init(sc); 2695 if (error != 0) 2696 return (error); 2697 2698 /* Get Tx queues to USB endpoints mapping. */ 2699 hashq = hasnq = haslq = 0; 2700 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2701 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2702 device_xname(sc->sc_dev), __func__, reg)); 2703 if (MS(reg, R92C_USB_EP_HQ) != 0) 2704 hashq = 1; 2705 if (MS(reg, R92C_USB_EP_NQ) != 0) 2706 hasnq = 1; 2707 if (MS(reg, R92C_USB_EP_LQ) != 0) 2708 haslq = 1; 2709 nqueues = hashq + hasnq + haslq; 2710 if (nqueues == 0) 2711 return (EIO); 2712 /* Get the number of pages for each queue. */ 2713 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2714 /* The remaining pages are assigned to the high priority queue. */ 2715 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2716 2717 /* Set number of pages for normal priority queue. */ 2718 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2719 urtwn_write_4(sc, R92C_RQPN, 2720 /* Set number of pages for public queue. */ 2721 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2722 /* Set number of pages for high priority queue. */ 2723 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2724 /* Set number of pages for low priority queue. */ 2725 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2726 /* Load values. */ 2727 R92C_RQPN_LD); 2728 2729 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2730 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2731 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2732 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2733 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2734 2735 /* Set queue to USB pipe mapping. */ 2736 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2737 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2738 if (nqueues == 1) { 2739 if (hashq) { 2740 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2741 } else if (hasnq) { 2742 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2743 } else { 2744 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2745 } 2746 } else if (nqueues == 2) { 2747 /* All 2-endpoints configs have a high priority queue. */ 2748 if (!hashq) { 2749 return (EIO); 2750 } 2751 if (hasnq) { 2752 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2753 } else { 2754 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2755 } 2756 } else { 2757 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2758 } 2759 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2760 2761 /* Set Tx/Rx transfer page boundary. */ 2762 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2763 2764 /* Set Tx/Rx transfer page size. */ 2765 urtwn_write_1(sc, R92C_PBP, 2766 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2767 return (0); 2768 } 2769 2770 static void 2771 urtwn_mac_init(struct urtwn_softc *sc) 2772 { 2773 int i; 2774 2775 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2776 2777 /* Write MAC initialization values. */ 2778 for (i = 0; i < (int)__arraycount(rtl8192cu_mac); i++) 2779 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2780 } 2781 2782 static void 2783 urtwn_bb_init(struct urtwn_softc *sc) 2784 { 2785 const struct urtwn_bb_prog *prog; 2786 uint32_t reg; 2787 int i; 2788 2789 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2790 2791 /* Enable BB and RF. */ 2792 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2793 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2794 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2795 R92C_SYS_FUNC_EN_DIO_RF); 2796 2797 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2798 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2799 2800 urtwn_write_1(sc, R92C_RF_CTRL, 2801 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2802 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2803 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2804 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2805 2806 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2807 urtwn_write_1(sc, 0x15, 0xe9); 2808 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2809 2810 /* Select BB programming based on board type. */ 2811 if (!(sc->chip & URTWN_CHIP_92C)) { 2812 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2813 prog = &rtl8188ce_bb_prog; 2814 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2815 prog = &rtl8188ru_bb_prog; 2816 } else { 2817 prog = &rtl8188cu_bb_prog; 2818 } 2819 } else { 2820 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2821 prog = &rtl8192ce_bb_prog; 2822 } else { 2823 prog = &rtl8192cu_bb_prog; 2824 } 2825 } 2826 /* Write BB initialization values. */ 2827 for (i = 0; i < prog->count; i++) { 2828 /* additional delay depend on registers */ 2829 switch (prog->regs[i]) { 2830 case 0xfe: 2831 usbd_delay_ms(sc->sc_udev, 50); 2832 break; 2833 case 0xfd: 2834 usbd_delay_ms(sc->sc_udev, 5); 2835 break; 2836 case 0xfc: 2837 usbd_delay_ms(sc->sc_udev, 1); 2838 break; 2839 case 0xfb: 2840 DELAY(50); 2841 break; 2842 case 0xfa: 2843 DELAY(5); 2844 break; 2845 case 0xf9: 2846 DELAY(1); 2847 break; 2848 } 2849 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2850 DELAY(1); 2851 } 2852 2853 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2854 /* 8192C 1T only configuration. */ 2855 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2856 reg = (reg & ~0x00000003) | 0x2; 2857 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2858 2859 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2860 reg = (reg & ~0x00300033) | 0x00200022; 2861 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2862 2863 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2864 reg = (reg & ~0xff000000) | (0x45 << 24); 2865 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2866 2867 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2868 reg = (reg & ~0x000000ff) | 0x23; 2869 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2870 2871 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2872 reg = (reg & ~0x00000030) | (1 << 4); 2873 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2874 2875 reg = urtwn_bb_read(sc, 0xe74); 2876 reg = (reg & ~0x0c000000) | (2 << 26); 2877 urtwn_bb_write(sc, 0xe74, reg); 2878 reg = urtwn_bb_read(sc, 0xe78); 2879 reg = (reg & ~0x0c000000) | (2 << 26); 2880 urtwn_bb_write(sc, 0xe78, reg); 2881 reg = urtwn_bb_read(sc, 0xe7c); 2882 reg = (reg & ~0x0c000000) | (2 << 26); 2883 urtwn_bb_write(sc, 0xe7c, reg); 2884 reg = urtwn_bb_read(sc, 0xe80); 2885 reg = (reg & ~0x0c000000) | (2 << 26); 2886 urtwn_bb_write(sc, 0xe80, reg); 2887 reg = urtwn_bb_read(sc, 0xe88); 2888 reg = (reg & ~0x0c000000) | (2 << 26); 2889 urtwn_bb_write(sc, 0xe88, reg); 2890 } 2891 2892 /* Write AGC values. */ 2893 for (i = 0; i < prog->agccount; i++) { 2894 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 2895 DELAY(1); 2896 } 2897 2898 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2899 R92C_HSSI_PARAM2_CCK_HIPWR) { 2900 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 2901 } 2902 } 2903 2904 static void 2905 urtwn_rf_init(struct urtwn_softc *sc) 2906 { 2907 const struct urtwn_rf_prog *prog; 2908 uint32_t reg, mask, saved; 2909 int i, j, idx; 2910 2911 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2912 2913 /* Select RF programming based on board type. */ 2914 if (!(sc->chip & URTWN_CHIP_92C)) { 2915 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2916 prog = rtl8188ce_rf_prog; 2917 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2918 prog = rtl8188ru_rf_prog; 2919 } else { 2920 prog = rtl8188cu_rf_prog; 2921 } 2922 } else { 2923 prog = rtl8192ce_rf_prog; 2924 } 2925 2926 for (i = 0; i < sc->nrxchains; i++) { 2927 /* Save RF_ENV control type. */ 2928 idx = i / 2; 2929 mask = 0xffffU << ((i % 2) * 16); 2930 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 2931 2932 /* Set RF_ENV enable. */ 2933 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2934 reg |= 0x100000; 2935 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2936 DELAY(1); 2937 2938 /* Set RF_ENV output high. */ 2939 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2940 reg |= 0x10; 2941 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2942 DELAY(1); 2943 2944 /* Set address and data lengths of RF registers. */ 2945 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2946 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2947 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2948 DELAY(1); 2949 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2950 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2951 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2952 DELAY(1); 2953 2954 /* Write RF initialization values for this chain. */ 2955 for (j = 0; j < prog[i].count; j++) { 2956 if (prog[i].regs[j] >= 0xf9 && 2957 prog[i].regs[j] <= 0xfe) { 2958 /* 2959 * These are fake RF registers offsets that 2960 * indicate a delay is required. 2961 */ 2962 usbd_delay_ms(sc->sc_udev, 50); 2963 continue; 2964 } 2965 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 2966 DELAY(1); 2967 } 2968 2969 /* Restore RF_ENV control type. */ 2970 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 2971 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 2972 } 2973 2974 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2975 URTWN_CHIP_UMC_A_CUT) { 2976 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2977 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2978 } 2979 2980 /* Cache RF register CHNLBW. */ 2981 for (i = 0; i < 2; i++) { 2982 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2983 } 2984 } 2985 2986 static void 2987 urtwn_cam_init(struct urtwn_softc *sc) 2988 { 2989 uint32_t content, command; 2990 uint8_t idx; 2991 int i; 2992 2993 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2994 2995 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 2996 content = (idx & 3) 2997 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 2998 | R92C_CAM_VALID; 2999 3000 command = R92C_CAMCMD_POLLING 3001 | R92C_CAMCMD_WRITE 3002 | R92C_CAM_CTL0(idx); 3003 3004 urtwn_write_4(sc, R92C_CAMWRITE, content); 3005 urtwn_write_4(sc, R92C_CAMCMD, command); 3006 } 3007 3008 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3009 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3010 if (i == 0) { 3011 content = (idx & 3) 3012 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3013 | R92C_CAM_VALID; 3014 } else { 3015 content = 0; 3016 } 3017 3018 command = R92C_CAMCMD_POLLING 3019 | R92C_CAMCMD_WRITE 3020 | R92C_CAM_CTL0(idx) 3021 | (u_int)i; 3022 3023 urtwn_write_4(sc, R92C_CAMWRITE, content); 3024 urtwn_write_4(sc, R92C_CAMCMD, command); 3025 } 3026 } 3027 3028 /* Invalidate all CAM entries. */ 3029 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3030 } 3031 3032 static void 3033 urtwn_pa_bias_init(struct urtwn_softc *sc) 3034 { 3035 uint8_t reg; 3036 int i; 3037 3038 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3039 3040 for (i = 0; i < sc->nrxchains; i++) { 3041 if (sc->pa_setting & (1U << i)) 3042 continue; 3043 3044 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3045 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3046 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3047 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3048 } 3049 if (!(sc->pa_setting & 0x10)) { 3050 reg = urtwn_read_1(sc, 0x16); 3051 reg = (reg & ~0xf0) | 0x90; 3052 urtwn_write_1(sc, 0x16, reg); 3053 } 3054 } 3055 3056 static void 3057 urtwn_rxfilter_init(struct urtwn_softc *sc) 3058 { 3059 3060 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3061 3062 /* Initialize Rx filter. */ 3063 /* TODO: use better filter for monitor mode. */ 3064 urtwn_write_4(sc, R92C_RCR, 3065 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3066 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3067 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3068 /* Accept all multicast frames. */ 3069 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3070 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3071 /* Accept all management frames. */ 3072 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3073 /* Reject all control frames. */ 3074 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3075 /* Accept all data frames. */ 3076 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3077 } 3078 3079 static void 3080 urtwn_edca_init(struct urtwn_softc *sc) 3081 { 3082 3083 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3084 3085 /* set spec SIFS (used in NAV) */ 3086 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3087 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3088 3089 /* set SIFS CCK/OFDM */ 3090 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3091 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3092 3093 /* TXOP */ 3094 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3095 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3096 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3097 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3098 } 3099 3100 static void 3101 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3102 uint16_t power[URTWN_RIDX_COUNT]) 3103 { 3104 uint32_t reg; 3105 3106 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3107 __func__, chain)); 3108 3109 /* Write per-CCK rate Tx power. */ 3110 if (chain == 0) { 3111 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3112 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3113 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3114 3115 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3116 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3117 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3118 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3119 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3120 } else { 3121 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3122 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3123 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3124 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3125 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3126 3127 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3128 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3129 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3130 } 3131 /* Write per-OFDM rate Tx power. */ 3132 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3133 SM(R92C_TXAGC_RATE06, power[ 4]) | 3134 SM(R92C_TXAGC_RATE09, power[ 5]) | 3135 SM(R92C_TXAGC_RATE12, power[ 6]) | 3136 SM(R92C_TXAGC_RATE18, power[ 7])); 3137 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3138 SM(R92C_TXAGC_RATE24, power[ 8]) | 3139 SM(R92C_TXAGC_RATE36, power[ 9]) | 3140 SM(R92C_TXAGC_RATE48, power[10]) | 3141 SM(R92C_TXAGC_RATE54, power[11])); 3142 /* Write per-MCS Tx power. */ 3143 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3144 SM(R92C_TXAGC_MCS00, power[12]) | 3145 SM(R92C_TXAGC_MCS01, power[13]) | 3146 SM(R92C_TXAGC_MCS02, power[14]) | 3147 SM(R92C_TXAGC_MCS03, power[15])); 3148 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3149 SM(R92C_TXAGC_MCS04, power[16]) | 3150 SM(R92C_TXAGC_MCS05, power[17]) | 3151 SM(R92C_TXAGC_MCS06, power[18]) | 3152 SM(R92C_TXAGC_MCS07, power[19])); 3153 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3154 SM(R92C_TXAGC_MCS08, power[20]) | 3155 SM(R92C_TXAGC_MCS09, power[21]) | 3156 SM(R92C_TXAGC_MCS10, power[22]) | 3157 SM(R92C_TXAGC_MCS11, power[23])); 3158 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3159 SM(R92C_TXAGC_MCS12, power[24]) | 3160 SM(R92C_TXAGC_MCS13, power[25]) | 3161 SM(R92C_TXAGC_MCS14, power[26]) | 3162 SM(R92C_TXAGC_MCS15, power[27])); 3163 } 3164 3165 static void 3166 urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, 3167 uint16_t power[URTWN_RIDX_COUNT]) 3168 { 3169 struct r92c_rom *rom = &sc->rom; 3170 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3171 const struct urtwn_txpwr *base; 3172 int ridx, group; 3173 3174 DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", 3175 device_xname(sc->sc_dev), __func__, chain, chan)); 3176 3177 /* Determine channel group. */ 3178 if (chan <= 3) { 3179 group = 0; 3180 } else if (chan <= 9) { 3181 group = 1; 3182 } else { 3183 group = 2; 3184 } 3185 3186 /* Get original Tx power based on board type and RF chain. */ 3187 if (!(sc->chip & URTWN_CHIP_92C)) { 3188 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3189 base = &rtl8188ru_txagc[chain]; 3190 } else { 3191 base = &rtl8192cu_txagc[chain]; 3192 } 3193 } else { 3194 base = &rtl8192cu_txagc[chain]; 3195 } 3196 3197 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3198 if (sc->regulatory == 0) { 3199 for (ridx = 0; ridx <= 3; ridx++) { 3200 power[ridx] = base->pwr[0][ridx]; 3201 } 3202 } 3203 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3204 if (sc->regulatory == 3) { 3205 power[ridx] = base->pwr[0][ridx]; 3206 /* Apply vendor limits. */ 3207 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3208 maxpow = rom->ht40_max_pwr[group]; 3209 } else { 3210 maxpow = rom->ht20_max_pwr[group]; 3211 } 3212 maxpow = (maxpow >> (chain * 4)) & 0xf; 3213 if (power[ridx] > maxpow) { 3214 power[ridx] = maxpow; 3215 } 3216 } else if (sc->regulatory == 1) { 3217 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3218 power[ridx] = base->pwr[group][ridx]; 3219 } 3220 } else if (sc->regulatory != 2) { 3221 power[ridx] = base->pwr[0][ridx]; 3222 } 3223 } 3224 3225 /* Compute per-CCK rate Tx power. */ 3226 cckpow = rom->cck_tx_pwr[chain][group]; 3227 for (ridx = 0; ridx <= 3; ridx++) { 3228 power[ridx] += cckpow; 3229 if (power[ridx] > R92C_MAX_TX_PWR) { 3230 power[ridx] = R92C_MAX_TX_PWR; 3231 } 3232 } 3233 3234 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3235 if (sc->ntxchains > 1) { 3236 /* Apply reduction for 2 spatial streams. */ 3237 diff = rom->ht40_2s_tx_pwr_diff[group]; 3238 diff = (diff >> (chain * 4)) & 0xf; 3239 htpow = (htpow > diff) ? htpow - diff : 0; 3240 } 3241 3242 /* Compute per-OFDM rate Tx power. */ 3243 diff = rom->ofdm_tx_pwr_diff[group]; 3244 diff = (diff >> (chain * 4)) & 0xf; 3245 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3246 for (ridx = 4; ridx <= 11; ridx++) { 3247 power[ridx] += ofdmpow; 3248 if (power[ridx] > R92C_MAX_TX_PWR) { 3249 power[ridx] = R92C_MAX_TX_PWR; 3250 } 3251 } 3252 3253 /* Compute per-MCS Tx power. */ 3254 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3255 diff = rom->ht20_tx_pwr_diff[group]; 3256 diff = (diff >> (chain * 4)) & 0xf; 3257 htpow += diff; /* HT40->HT20 correction. */ 3258 } 3259 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3260 power[ridx] += htpow; 3261 if (power[ridx] > R92C_MAX_TX_PWR) { 3262 power[ridx] = R92C_MAX_TX_PWR; 3263 } 3264 } 3265 #ifdef URTWN_DEBUG 3266 if (urtwn_debug & DBG_RF) { 3267 /* Dump per-rate Tx power values. */ 3268 printf("%s: %s: Tx power for chain %d:\n", 3269 device_xname(sc->sc_dev), __func__, chain); 3270 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3271 printf("%s: %s: Rate %d = %u\n", 3272 device_xname(sc->sc_dev), __func__, ridx, 3273 power[ridx]); 3274 } 3275 } 3276 #endif 3277 } 3278 3279 static void 3280 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3281 { 3282 uint16_t power[URTWN_RIDX_COUNT]; 3283 int i; 3284 3285 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3286 3287 for (i = 0; i < sc->ntxchains; i++) { 3288 /* Compute per-rate Tx power values. */ 3289 urtwn_get_txpower(sc, i, chan, ht40m, power); 3290 /* Write per-rate Tx power values to hardware. */ 3291 urtwn_write_txpower(sc, i, power); 3292 } 3293 } 3294 3295 static void 3296 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3297 { 3298 struct ieee80211com *ic = &sc->sc_ic; 3299 u_int chan; 3300 int i; 3301 3302 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3303 3304 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3305 __func__, chan)); 3306 3307 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3308 chan += 2; 3309 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3310 chan -= 2; 3311 } 3312 3313 /* Set Tx power for this new channel. */ 3314 urtwn_set_txpower(sc, chan, ht40m); 3315 3316 for (i = 0; i < sc->nrxchains; i++) { 3317 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3318 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3319 } 3320 3321 if (ht40m) { 3322 /* Is secondary channel below or above primary? */ 3323 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3324 uint32_t reg; 3325 3326 urtwn_write_1(sc, R92C_BWOPMODE, 3327 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3328 3329 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3330 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3331 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3332 3333 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3334 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3335 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3336 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3337 3338 /* Set CCK side band. */ 3339 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3340 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3341 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3342 3343 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3344 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3345 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3346 3347 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3348 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3349 ~R92C_FPGA0_ANAPARAM2_CBW20); 3350 3351 reg = urtwn_bb_read(sc, 0x818); 3352 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3353 urtwn_bb_write(sc, 0x818, reg); 3354 3355 /* Select 40MHz bandwidth. */ 3356 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3357 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3358 } else { 3359 urtwn_write_1(sc, R92C_BWOPMODE, 3360 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3361 3362 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3363 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3364 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3365 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3366 3367 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3368 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3369 R92C_FPGA0_ANAPARAM2_CBW20); 3370 3371 /* Select 20MHz bandwidth. */ 3372 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3373 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3374 } 3375 } 3376 3377 static void 3378 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3379 { 3380 3381 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3382 __func__, inited)); 3383 3384 /* TODO */ 3385 } 3386 3387 static void 3388 urtwn_lc_calib(struct urtwn_softc *sc) 3389 { 3390 uint32_t rf_ac[2]; 3391 uint8_t txmode; 3392 int i; 3393 3394 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3395 3396 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3397 if ((txmode & 0x70) != 0) { 3398 /* Disable all continuous Tx. */ 3399 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3400 3401 /* Set RF mode to standby mode. */ 3402 for (i = 0; i < sc->nrxchains; i++) { 3403 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3404 urtwn_rf_write(sc, i, R92C_RF_AC, 3405 RW(rf_ac[i], R92C_RF_AC_MODE, 3406 R92C_RF_AC_MODE_STANDBY)); 3407 } 3408 } else { 3409 /* Block all Tx queues. */ 3410 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3411 } 3412 /* Start calibration. */ 3413 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3414 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3415 3416 /* Give calibration the time to complete. */ 3417 usbd_delay_ms(sc->sc_udev, 100); 3418 3419 /* Restore configuration. */ 3420 if ((txmode & 0x70) != 0) { 3421 /* Restore Tx mode. */ 3422 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3423 /* Restore RF mode. */ 3424 for (i = 0; i < sc->nrxchains; i++) { 3425 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3426 } 3427 } else { 3428 /* Unblock all Tx queues. */ 3429 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3430 } 3431 } 3432 3433 static void 3434 urtwn_temp_calib(struct urtwn_softc *sc) 3435 { 3436 int temp; 3437 3438 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3439 3440 if (sc->thcal_state == 0) { 3441 /* Start measuring temperature. */ 3442 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3443 device_xname(sc->sc_dev), __func__)); 3444 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3445 sc->thcal_state = 1; 3446 return; 3447 } 3448 sc->thcal_state = 0; 3449 3450 /* Read measured temperature. */ 3451 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3452 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3453 __func__, temp)); 3454 if (temp == 0) /* Read failed, skip. */ 3455 return; 3456 3457 /* 3458 * Redo LC calibration if temperature changed significantly since 3459 * last calibration. 3460 */ 3461 if (sc->thcal_lctemp == 0) { 3462 /* First LC calibration is performed in urtwn_init(). */ 3463 sc->thcal_lctemp = temp; 3464 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3465 DPRINTFN(DBG_RF, 3466 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3467 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3468 temp)); 3469 urtwn_lc_calib(sc); 3470 /* Record temperature of last LC calibration. */ 3471 sc->thcal_lctemp = temp; 3472 } 3473 } 3474 3475 static int 3476 urtwn_init(struct ifnet *ifp) 3477 { 3478 struct urtwn_softc *sc = ifp->if_softc; 3479 struct ieee80211com *ic = &sc->sc_ic; 3480 struct urtwn_rx_data *data; 3481 uint32_t reg; 3482 int i, error; 3483 3484 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3485 3486 urtwn_stop(ifp, 0); 3487 3488 mutex_enter(&sc->sc_task_mtx); 3489 /* Init host async commands ring. */ 3490 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3491 mutex_exit(&sc->sc_task_mtx); 3492 3493 mutex_enter(&sc->sc_fwcmd_mtx); 3494 /* Init firmware commands ring. */ 3495 sc->fwcur = 0; 3496 mutex_exit(&sc->sc_fwcmd_mtx); 3497 3498 /* Allocate Tx/Rx buffers. */ 3499 error = urtwn_alloc_rx_list(sc); 3500 if (error != 0) { 3501 aprint_error_dev(sc->sc_dev, 3502 "could not allocate Rx buffers\n"); 3503 goto fail; 3504 } 3505 error = urtwn_alloc_tx_list(sc); 3506 if (error != 0) { 3507 aprint_error_dev(sc->sc_dev, 3508 "could not allocate Tx buffers\n"); 3509 goto fail; 3510 } 3511 3512 /* Power on adapter. */ 3513 error = urtwn_power_on(sc); 3514 if (error != 0) 3515 goto fail; 3516 3517 /* Initialize DMA. */ 3518 error = urtwn_dma_init(sc); 3519 if (error != 0) 3520 goto fail; 3521 3522 /* Set info size in Rx descriptors (in 64-bit words). */ 3523 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3524 3525 /* Init interrupts. */ 3526 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3527 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3528 3529 /* Set MAC address. */ 3530 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3531 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3532 3533 /* Set initial network type. */ 3534 reg = urtwn_read_4(sc, R92C_CR); 3535 switch (ic->ic_opmode) { 3536 case IEEE80211_M_STA: 3537 default: 3538 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3539 break; 3540 3541 case IEEE80211_M_IBSS: 3542 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3543 break; 3544 } 3545 urtwn_write_4(sc, R92C_CR, reg); 3546 3547 urtwn_rxfilter_init(sc); 3548 3549 /* Set response rate */ 3550 reg = urtwn_read_4(sc, R92C_RRSR); 3551 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3552 urtwn_write_4(sc, R92C_RRSR, reg); 3553 3554 /* SIFS (used in NAV) */ 3555 urtwn_write_2(sc, R92C_SPEC_SIFS, 3556 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3557 3558 /* Set short/long retry limits. */ 3559 urtwn_write_2(sc, R92C_RL, 3560 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3561 3562 /* Initialize EDCA parameters. */ 3563 urtwn_edca_init(sc); 3564 3565 /* Setup rate fallback. */ 3566 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3567 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3568 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3569 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3570 3571 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3572 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3573 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3574 /* Set ACK timeout. */ 3575 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3576 3577 /* Setup USB aggregation. */ 3578 /* Tx */ 3579 reg = urtwn_read_4(sc, R92C_TDECTRL); 3580 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3581 urtwn_write_4(sc, R92C_TDECTRL, reg); 3582 /* Rx */ 3583 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3584 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3585 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3586 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3587 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3588 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3589 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3590 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3591 3592 /* Initialize beacon parameters. */ 3593 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3594 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3595 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3596 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3597 3598 /* Setup AMPDU aggregation. */ 3599 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3600 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3601 urtwn_write_2(sc, 0x4ca, 0x0708); 3602 3603 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3604 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3605 3606 /* Load 8051 microcode. */ 3607 error = urtwn_load_firmware(sc); 3608 if (error != 0) 3609 goto fail; 3610 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3611 3612 /* Initialize MAC/BB/RF blocks. */ 3613 urtwn_mac_init(sc); 3614 urtwn_write_4(sc, R92C_RCR, 3615 urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); 3616 urtwn_bb_init(sc); 3617 urtwn_rf_init(sc); 3618 3619 /* Turn CCK and OFDM blocks on. */ 3620 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3621 reg |= R92C_RFMOD_CCK_EN; 3622 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3623 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3624 reg |= R92C_RFMOD_OFDM_EN; 3625 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3626 3627 /* Clear per-station keys table. */ 3628 urtwn_cam_init(sc); 3629 3630 /* Enable hardware sequence numbering. */ 3631 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3632 3633 /* Perform LO and IQ calibrations. */ 3634 urtwn_iq_calib(sc, sc->iqk_inited); 3635 sc->iqk_inited = true; 3636 3637 /* Perform LC calibration. */ 3638 urtwn_lc_calib(sc); 3639 3640 /* Fix USB interference issue. */ 3641 urtwn_write_1(sc, 0xfe40, 0xe0); 3642 urtwn_write_1(sc, 0xfe41, 0x8d); 3643 urtwn_write_1(sc, 0xfe42, 0x80); 3644 urtwn_write_4(sc, 0x20c, 0xfd0320); 3645 3646 urtwn_pa_bias_init(sc); 3647 3648 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3649 /* 1T1R */ 3650 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3651 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3652 } 3653 3654 /* Initialize GPIO setting. */ 3655 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3656 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3657 3658 /* Fix for lower temperature. */ 3659 urtwn_write_1(sc, 0x15, 0xe9); 3660 3661 /* Set default channel. */ 3662 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3663 urtwn_set_chan(sc, ic->ic_ibss_chan, IEEE80211_HTINFO_2NDCHAN_NONE); 3664 3665 /* Queue Rx xfers. */ 3666 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3667 data = &sc->rx_data[i]; 3668 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3669 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3670 USBD_NO_TIMEOUT, urtwn_rxeof); 3671 error = usbd_transfer(data->xfer); 3672 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3673 error != USBD_IN_PROGRESS)) 3674 goto fail; 3675 } 3676 3677 /* We're ready to go. */ 3678 ifp->if_flags &= ~IFF_OACTIVE; 3679 ifp->if_flags |= IFF_RUNNING; 3680 3681 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3682 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3683 else 3684 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3685 return (0); 3686 3687 fail: 3688 urtwn_stop(ifp, 1); 3689 return (error); 3690 } 3691 3692 static void 3693 urtwn_stop(struct ifnet *ifp, int disable) 3694 { 3695 struct urtwn_softc *sc = ifp->if_softc; 3696 struct ieee80211com *ic = &sc->sc_ic; 3697 int i, s; 3698 3699 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3700 3701 sc->tx_timer = 0; 3702 ifp->if_timer = 0; 3703 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3704 3705 s = splusb(); 3706 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3707 urtwn_wait_async(sc); 3708 splx(s); 3709 3710 callout_stop(&sc->sc_scan_to); 3711 callout_stop(&sc->sc_calib_to); 3712 3713 /* Abort Tx. */ 3714 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3715 if (sc->tx_pipe[i] != NULL) 3716 usbd_abort_pipe(sc->tx_pipe[i]); 3717 } 3718 3719 /* Stop Rx pipe. */ 3720 usbd_abort_pipe(sc->rx_pipe); 3721 3722 /* Free Tx/Rx buffers. */ 3723 urtwn_free_tx_list(sc); 3724 urtwn_free_rx_list(sc); 3725 3726 if (disable) 3727 urtwn_chip_stop(sc); 3728 } 3729 3730 static void 3731 urtwn_chip_stop(struct urtwn_softc *sc) 3732 { 3733 uint32_t reg; 3734 bool disabled = true; 3735 3736 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3737 3738 /* 3739 * RF Off Sequence 3740 */ 3741 /* Pause MAC TX queue */ 3742 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3743 3744 /* Disable RF */ 3745 urtwn_rf_write(sc, 0, 0, 0); 3746 3747 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3748 3749 /* Reset BB state machine */ 3750 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3751 R92C_SYS_FUNC_EN_USBD | 3752 R92C_SYS_FUNC_EN_USBA | 3753 R92C_SYS_FUNC_EN_BB_GLB_RST); 3754 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3755 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3756 3757 /* 3758 * Reset digital sequence 3759 */ 3760 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3761 /* Reset MCU ready status */ 3762 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3763 /* If firmware in ram code, do reset */ 3764 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3765 urtwn_fw_reset(sc); 3766 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3767 } 3768 } 3769 3770 /* Reset MAC and Enable 8051 */ 3771 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3772 3773 /* Reset MCU ready status */ 3774 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3775 3776 if (disabled) { 3777 /* Disable MAC clock */ 3778 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3779 /* Disable AFE PLL */ 3780 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3781 /* Gated AFE DIG_CLOCK */ 3782 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3783 /* Isolated digital to PON */ 3784 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3785 } 3786 3787 /* 3788 * Pull GPIO PIN to balance level and LED control 3789 */ 3790 /* 1. Disable GPIO[7:0] */ 3791 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3792 3793 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3794 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3795 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3796 3797 /* Disable GPIO[10:8] */ 3798 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3799 3800 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3801 reg |= (((reg & 0x000f) << 4) | 0x0780); 3802 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3803 3804 /* Disable LED0 & 1 */ 3805 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3806 3807 /* 3808 * Reset digital sequence 3809 */ 3810 if (disabled) { 3811 /* Disable ELDR clock */ 3812 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3813 /* Isolated ELDR to PON */ 3814 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3815 } 3816 3817 /* 3818 * Disable analog sequence 3819 */ 3820 if (disabled) { 3821 /* Disable A15 power */ 3822 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3823 /* Disable digital core power */ 3824 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3825 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3826 ~R92C_LDOV12D_CTRL_LDV12_EN); 3827 } 3828 3829 /* Enter PFM mode */ 3830 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3831 3832 /* Set USB suspend */ 3833 urtwn_write_2(sc, R92C_APS_FSMCO, 3834 R92C_APS_FSMCO_APDM_HOST | 3835 R92C_APS_FSMCO_AFSM_HSUS | 3836 R92C_APS_FSMCO_PFM_ALDN); 3837 3838 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3839 } 3840 3841 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 3842 3843 #ifdef _MODULE 3844 #include "ioconf.c" 3845 #endif 3846 3847 static int 3848 if_urtwn_modcmd(modcmd_t cmd, void *aux) 3849 { 3850 int error = 0; 3851 3852 switch (cmd) { 3853 case MODULE_CMD_INIT: 3854 #ifdef _MODULE 3855 error = config_init_component(cfdriver_ioconf_urtwn, 3856 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3857 #endif 3858 return (error); 3859 case MODULE_CMD_FINI: 3860 #ifdef _MODULE 3861 error = config_fini_component(cfdriver_ioconf_urtwn, 3862 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3863 #endif 3864 return (error); 3865 default: 3866 return (ENOTTY); 3867 } 3868 } 3869
Indexes created Tue Sep 30 07:10:03 GMT 2025