if_urtwn.c revision 1.103
1 /* $NetBSD: if_urtwn.c,v 1.103 2022/04/06 22:01:45 mlelstv Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.103 2022/04/06 22:01:45 mlelstv Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 217 218 /* URTWN_RTL8192EU */ 219 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 220 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 221 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 222 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 223 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 224 }; 225 #undef URTWN_DEV 226 #undef URTWN_RTL8188E_DEV 227 #undef URTWN_RTL8192EU_DEV 228 229 static int urtwn_match(device_t, cfdata_t, void *); 230 static void urtwn_attach(device_t, device_t, void *); 231 static int urtwn_detach(device_t, int); 232 static int urtwn_activate(device_t, enum devact); 233 234 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 235 urtwn_attach, urtwn_detach, urtwn_activate); 236 237 static int urtwn_open_pipes(struct urtwn_softc *); 238 static void urtwn_close_pipes(struct urtwn_softc *); 239 static int urtwn_alloc_rx_list(struct urtwn_softc *); 240 static void urtwn_free_rx_list(struct urtwn_softc *); 241 static int urtwn_alloc_tx_list(struct urtwn_softc *); 242 static void urtwn_free_tx_list(struct urtwn_softc *); 243 static void urtwn_task(void *); 244 static void urtwn_do_async(struct urtwn_softc *, 245 void (*)(struct urtwn_softc *, void *), void *, int); 246 static void urtwn_wait_async(struct urtwn_softc *); 247 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 248 int); 249 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 250 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 251 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 252 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 253 int); 254 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 257 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 258 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 259 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 260 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 261 uint32_t); 262 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 267 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 268 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 269 static void urtwn_efuse_read(struct urtwn_softc *); 270 static void urtwn_efuse_switch_power(struct urtwn_softc *); 271 static int urtwn_read_chipid(struct urtwn_softc *); 272 #ifdef URTWN_DEBUG 273 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 274 #endif 275 static void urtwn_read_rom(struct urtwn_softc *); 276 static void urtwn_r88e_read_rom(struct urtwn_softc *); 277 static int urtwn_media_change(struct ifnet *); 278 static int urtwn_ra_init(struct urtwn_softc *); 279 static int urtwn_get_nettype(struct urtwn_softc *); 280 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 281 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 282 static void urtwn_set_led(struct urtwn_softc *, int, int); 283 static void urtwn_calib_to(void *); 284 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 285 static void urtwn_next_scan(void *); 286 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 287 int); 288 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 289 static int urtwn_wme_update(struct ieee80211com *); 290 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 291 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 292 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 293 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 294 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 295 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 296 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 297 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 298 struct ieee80211_node *, struct urtwn_tx_data *); 299 static struct urtwn_tx_data * 300 urtwn_get_tx_data(struct urtwn_softc *, size_t); 301 static void urtwn_start(struct ifnet *); 302 static void urtwn_watchdog(struct ifnet *); 303 static int urtwn_ioctl(struct ifnet *, u_long, void *); 304 static int urtwn_r92c_power_on(struct urtwn_softc *); 305 static int urtwn_r92e_power_on(struct urtwn_softc *); 306 static int urtwn_r88e_power_on(struct urtwn_softc *); 307 static int urtwn_llt_init(struct urtwn_softc *); 308 static void urtwn_fw_reset(struct urtwn_softc *); 309 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 310 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 311 static int urtwn_load_firmware(struct urtwn_softc *); 312 static int urtwn_r92c_dma_init(struct urtwn_softc *); 313 static int urtwn_r88e_dma_init(struct urtwn_softc *); 314 static void urtwn_mac_init(struct urtwn_softc *); 315 static void urtwn_bb_init(struct urtwn_softc *); 316 static void urtwn_rf_init(struct urtwn_softc *); 317 static void urtwn_cam_init(struct urtwn_softc *); 318 static void urtwn_pa_bias_init(struct urtwn_softc *); 319 static void urtwn_rxfilter_init(struct urtwn_softc *); 320 static void urtwn_edca_init(struct urtwn_softc *); 321 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 322 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 323 uint16_t[]); 324 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 325 u_int, uint16_t[]); 326 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 327 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 328 u_int); 329 static void urtwn_iq_calib(struct urtwn_softc *, bool); 330 static void urtwn_lc_calib(struct urtwn_softc *); 331 static void urtwn_temp_calib(struct urtwn_softc *); 332 static int urtwn_init(struct ifnet *); 333 static void urtwn_stop(struct ifnet *, int); 334 static int urtwn_reset(struct ifnet *); 335 static void urtwn_chip_stop(struct urtwn_softc *); 336 static void urtwn_newassoc(struct ieee80211_node *, int); 337 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 338 339 /* Aliases. */ 340 #define urtwn_bb_write urtwn_write_4 341 #define urtwn_bb_read urtwn_read_4 342 343 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 344 345 static const uint16_t addaReg[] = { 346 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 347 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 348 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 349 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 350 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 351 }; 352 353 static int 354 urtwn_match(device_t parent, cfdata_t match, void *aux) 355 { 356 struct usb_attach_arg *uaa = aux; 357 358 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 359 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 360 } 361 362 static void 363 urtwn_attach(device_t parent, device_t self, void *aux) 364 { 365 struct urtwn_softc *sc = device_private(self); 366 struct ieee80211com *ic = &sc->sc_ic; 367 struct ifnet *ifp = &sc->sc_if; 368 struct usb_attach_arg *uaa = aux; 369 char *devinfop; 370 const struct urtwn_dev *dev; 371 usb_device_request_t req; 372 size_t i; 373 int error; 374 375 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 376 377 sc->sc_dev = self; 378 sc->sc_udev = uaa->uaa_device; 379 380 sc->chip = 0; 381 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 382 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 383 SET(sc->chip, URTWN_CHIP_88E); 384 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 385 SET(sc->chip, URTWN_CHIP_92EU); 386 387 aprint_naive("\n"); 388 aprint_normal("\n"); 389 390 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 391 aprint_normal_dev(self, "%s\n", devinfop); 392 usbd_devinfo_free(devinfop); 393 394 req.bmRequestType = UT_WRITE_DEVICE; 395 req.bRequest = UR_SET_FEATURE; 396 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 397 USETW(req.wIndex, UHF_PORT_SUSPEND); 398 USETW(req.wLength, 0); 399 400 (void) usbd_do_request(sc->sc_udev, &req, 0); 401 402 cv_init(&sc->sc_task_cv, "urtwntsk"); 403 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 404 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 405 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 406 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 407 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 408 409 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 410 411 callout_init(&sc->sc_scan_to, 0); 412 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 413 callout_init(&sc->sc_calib_to, 0); 414 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 415 416 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 417 RND_TYPE_NET, RND_FLAG_DEFAULT); 418 419 error = usbd_set_config_no(sc->sc_udev, 1, 0); 420 if (error != 0) { 421 aprint_error_dev(self, "failed to set configuration" 422 ", err=%s\n", usbd_errstr(error)); 423 goto fail; 424 } 425 426 /* Get the first interface handle. */ 427 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 428 if (error != 0) { 429 aprint_error_dev(self, "could not get interface handle\n"); 430 goto fail; 431 } 432 433 error = urtwn_read_chipid(sc); 434 if (error != 0) { 435 aprint_error_dev(self, "unsupported test chip\n"); 436 goto fail; 437 } 438 439 /* Determine number of Tx/Rx chains. */ 440 if (sc->chip & URTWN_CHIP_92C) { 441 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 442 sc->nrxchains = 2; 443 } else if (sc->chip & URTWN_CHIP_92EU) { 444 sc->ntxchains = 2; 445 sc->nrxchains = 2; 446 } else { 447 sc->ntxchains = 1; 448 sc->nrxchains = 1; 449 } 450 451 if (ISSET(sc->chip, URTWN_CHIP_88E) || 452 ISSET(sc->chip, URTWN_CHIP_92EU)) 453 urtwn_r88e_read_rom(sc); 454 else 455 urtwn_read_rom(sc); 456 457 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 458 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 459 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 460 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 461 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 462 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 463 "8188CUS", sc->ntxchains, sc->nrxchains, 464 ether_sprintf(ic->ic_myaddr)); 465 466 error = urtwn_open_pipes(sc); 467 if (error != 0) { 468 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 469 goto fail; 470 } 471 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 472 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 473 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 474 475 /* 476 * Setup the 802.11 device. 477 */ 478 ic->ic_ifp = ifp; 479 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 480 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 481 ic->ic_state = IEEE80211_S_INIT; 482 483 /* Set device capabilities. */ 484 ic->ic_caps = 485 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 486 IEEE80211_C_IBSS | /* IBSS mode supported */ 487 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 488 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 489 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 490 IEEE80211_C_WME | /* 802.11e */ 491 IEEE80211_C_WPA; /* 802.11i */ 492 493 /* Set supported .11b and .11g rates. */ 494 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 495 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 496 497 /* Set supported .11b and .11g channels (1 through 14). */ 498 for (i = 1; i <= 14; i++) { 499 ic->ic_channels[i].ic_freq = 500 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 501 ic->ic_channels[i].ic_flags = 502 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 503 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 504 } 505 506 ifp->if_softc = sc; 507 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 508 ifp->if_init = urtwn_init; 509 ifp->if_ioctl = urtwn_ioctl; 510 ifp->if_start = urtwn_start; 511 ifp->if_watchdog = urtwn_watchdog; 512 IFQ_SET_READY(&ifp->if_snd); 513 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 514 515 if_initialize(ifp); 516 ieee80211_ifattach(ic); 517 518 /* override default methods */ 519 ic->ic_newassoc = urtwn_newassoc; 520 ic->ic_reset = urtwn_reset; 521 ic->ic_wme.wme_update = urtwn_wme_update; 522 523 /* Override state transition machine. */ 524 sc->sc_newstate = ic->ic_newstate; 525 ic->ic_newstate = urtwn_newstate; 526 527 /* XXX media locking needs revisiting */ 528 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 529 ieee80211_media_init_with_lock(ic, 530 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 531 532 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 533 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 534 &sc->sc_drvbpf); 535 536 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 537 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 538 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 539 540 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 541 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 542 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 543 544 ifp->if_percpuq = if_percpuq_create(ifp); 545 if_register(ifp); 546 547 ieee80211_announce(ic); 548 549 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 550 551 if (!pmf_device_register(self, NULL, NULL)) 552 aprint_error_dev(self, "couldn't establish power handler\n"); 553 554 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 555 return; 556 557 fail: 558 sc->sc_dying = 1; 559 aprint_error_dev(self, "attach failed\n"); 560 } 561 562 static int 563 urtwn_detach(device_t self, int flags) 564 { 565 struct urtwn_softc *sc = device_private(self); 566 struct ifnet *ifp = &sc->sc_if; 567 int s; 568 569 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 570 571 pmf_device_deregister(self); 572 573 s = splusb(); 574 575 sc->sc_dying = 1; 576 577 callout_halt(&sc->sc_scan_to, NULL); 578 callout_halt(&sc->sc_calib_to, NULL); 579 580 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 581 urtwn_stop(ifp, 0); 582 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 583 NULL); 584 585 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 586 bpf_detach(ifp); 587 ieee80211_ifdetach(&sc->sc_ic); 588 if_detach(ifp); 589 590 mutex_destroy(&sc->sc_media_mtx); 591 592 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 593 urtwn_close_pipes(sc); 594 } 595 596 splx(s); 597 598 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 599 600 rnd_detach_source(&sc->rnd_source); 601 602 callout_destroy(&sc->sc_scan_to); 603 callout_destroy(&sc->sc_calib_to); 604 605 cv_destroy(&sc->sc_task_cv); 606 mutex_destroy(&sc->sc_write_mtx); 607 mutex_destroy(&sc->sc_fwcmd_mtx); 608 mutex_destroy(&sc->sc_tx_mtx); 609 mutex_destroy(&sc->sc_rx_mtx); 610 mutex_destroy(&sc->sc_task_mtx); 611 612 return 0; 613 } 614 615 static int 616 urtwn_activate(device_t self, enum devact act) 617 { 618 struct urtwn_softc *sc = device_private(self); 619 620 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 621 622 switch (act) { 623 case DVACT_DEACTIVATE: 624 if_deactivate(sc->sc_ic.ic_ifp); 625 return 0; 626 default: 627 return EOPNOTSUPP; 628 } 629 } 630 631 static int 632 urtwn_open_pipes(struct urtwn_softc *sc) 633 { 634 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 635 static uint8_t epaddr[R92C_MAX_EPOUT]; 636 static uint8_t rxepaddr[R92C_MAX_EPIN]; 637 usb_interface_descriptor_t *id; 638 usb_endpoint_descriptor_t *ed; 639 size_t i, ntx = 0, nrx = 0; 640 int error; 641 642 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 643 644 /* Determine the number of bulk-out pipes. */ 645 id = usbd_get_interface_descriptor(sc->sc_iface); 646 for (i = 0; i < id->bNumEndpoints; i++) { 647 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 648 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 649 continue; 650 } 651 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 652 if (ntx < sizeof(epaddr)) 653 epaddr[ntx] = ed->bEndpointAddress; 654 ntx++; 655 } 656 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 657 if (nrx < sizeof(rxepaddr)) 658 rxepaddr[nrx] = ed->bEndpointAddress; 659 nrx++; 660 } 661 } 662 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 663 aprint_error_dev(sc->sc_dev, 664 "%zd: invalid number of Rx bulk pipes\n", nrx); 665 return EIO; 666 } 667 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 668 aprint_error_dev(sc->sc_dev, 669 "%zd: invalid number of Tx bulk pipes\n", ntx); 670 return EIO; 671 } 672 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 673 nrx, ntx, 0, 0); 674 sc->rx_npipe = nrx; 675 sc->tx_npipe = ntx; 676 677 /* Open bulk-in pipe at address 0x81. */ 678 for (i = 0; i < nrx; i++) { 679 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 680 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 681 if (error != 0) { 682 aprint_error_dev(sc->sc_dev, 683 "could not open Rx bulk pipe 0x%02x: %d\n", 684 rxepaddr[i], error); 685 goto fail; 686 } 687 } 688 689 /* Open bulk-out pipes (up to 3). */ 690 for (i = 0; i < ntx; i++) { 691 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 692 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 693 if (error != 0) { 694 aprint_error_dev(sc->sc_dev, 695 "could not open Tx bulk pipe 0x%02x: %d\n", 696 epaddr[i], error); 697 goto fail; 698 } 699 } 700 701 /* Map 802.11 access categories to USB pipes. */ 702 sc->ac2idx[WME_AC_BK] = 703 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 704 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 705 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 706 707 fail: 708 if (error != 0) 709 urtwn_close_pipes(sc); 710 return error; 711 } 712 713 static void 714 urtwn_close_pipes(struct urtwn_softc *sc) 715 { 716 struct usbd_pipe *pipe; 717 size_t i; 718 719 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 720 721 /* Close Rx pipes. */ 722 CTASSERT(sizeof(pipe) == sizeof(void *)); 723 for (i = 0; i < sc->rx_npipe; i++) { 724 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 725 if (pipe != NULL) { 726 usbd_close_pipe(pipe); 727 } 728 } 729 730 /* Close Tx pipes. */ 731 for (i = 0; i < sc->tx_npipe; i++) { 732 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 733 if (pipe != NULL) { 734 usbd_close_pipe(pipe); 735 } 736 } 737 } 738 739 static int __noinline 740 urtwn_alloc_rx_list(struct urtwn_softc *sc) 741 { 742 struct urtwn_rx_data *data; 743 size_t i; 744 int error = 0; 745 746 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 747 748 for (size_t j = 0; j < sc->rx_npipe; j++) { 749 TAILQ_INIT(&sc->rx_free_list[j]); 750 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 751 data = &sc->rx_data[j][i]; 752 753 data->sc = sc; /* Backpointer for callbacks. */ 754 755 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 756 0, 0, &data->xfer); 757 if (error) { 758 aprint_error_dev(sc->sc_dev, 759 "could not allocate xfer\n"); 760 break; 761 } 762 763 data->buf = usbd_get_buffer(data->xfer); 764 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 765 } 766 } 767 if (error != 0) 768 urtwn_free_rx_list(sc); 769 return error; 770 } 771 772 static void 773 urtwn_free_rx_list(struct urtwn_softc *sc) 774 { 775 struct usbd_xfer *xfer; 776 size_t i; 777 778 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 779 780 /* NB: Caller must abort pipe first. */ 781 for (size_t j = 0; j < sc->rx_npipe; j++) { 782 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 783 CTASSERT(sizeof(xfer) == sizeof(void *)); 784 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 785 if (xfer != NULL) 786 usbd_destroy_xfer(xfer); 787 } 788 } 789 } 790 791 static int __noinline 792 urtwn_alloc_tx_list(struct urtwn_softc *sc) 793 { 794 struct urtwn_tx_data *data; 795 size_t i; 796 int error = 0; 797 798 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 799 800 mutex_enter(&sc->sc_tx_mtx); 801 for (size_t j = 0; j < sc->tx_npipe; j++) { 802 TAILQ_INIT(&sc->tx_free_list[j]); 803 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 804 data = &sc->tx_data[j][i]; 805 806 data->sc = sc; /* Backpointer for callbacks. */ 807 data->pidx = j; 808 809 error = usbd_create_xfer(sc->tx_pipe[j], 810 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 811 &data->xfer); 812 if (error) { 813 aprint_error_dev(sc->sc_dev, 814 "could not allocate xfer\n"); 815 goto fail; 816 } 817 818 data->buf = usbd_get_buffer(data->xfer); 819 820 /* Append this Tx buffer to our free list. */ 821 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 822 } 823 } 824 mutex_exit(&sc->sc_tx_mtx); 825 return 0; 826 827 fail: 828 urtwn_free_tx_list(sc); 829 mutex_exit(&sc->sc_tx_mtx); 830 return error; 831 } 832 833 static void 834 urtwn_free_tx_list(struct urtwn_softc *sc) 835 { 836 struct usbd_xfer *xfer; 837 size_t i; 838 839 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 840 841 /* NB: Caller must abort pipe first. */ 842 for (size_t j = 0; j < sc->tx_npipe; j++) { 843 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 844 CTASSERT(sizeof(xfer) == sizeof(void *)); 845 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 846 if (xfer != NULL) 847 usbd_destroy_xfer(xfer); 848 } 849 } 850 } 851 852 static int 853 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 854 struct ieee80211_node *ni) 855 { 856 struct urtwn_tx_data *data = 857 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 858 859 if (data == NULL) 860 return ENOBUFS; 861 862 return urtwn_tx(sc, m, ni, data); 863 } 864 865 static void 866 urtwn_task(void *arg) 867 { 868 struct urtwn_softc *sc = arg; 869 struct ieee80211com *ic = &sc->sc_ic; 870 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 871 struct urtwn_host_cmd *cmd; 872 int s; 873 874 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 875 if (ic->ic_state == IEEE80211_S_RUN && 876 (ic->ic_opmode == IEEE80211_M_HOSTAP || 877 ic->ic_opmode == IEEE80211_M_IBSS)) { 878 879 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 880 &sc->sc_bo); 881 if (m == NULL) { 882 aprint_error_dev(sc->sc_dev, 883 "could not allocate beacon"); 884 } 885 886 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 887 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 888 } 889 890 /* beacon is no longer needed */ 891 m_freem(m); 892 } 893 894 /* Process host commands. */ 895 s = splusb(); 896 mutex_spin_enter(&sc->sc_task_mtx); 897 while (ring->next != ring->cur) { 898 cmd = &ring->cmd[ring->next]; 899 mutex_spin_exit(&sc->sc_task_mtx); 900 splx(s); 901 /* Invoke callback with kernel lock held. */ 902 cmd->cb(sc, cmd->data); 903 s = splusb(); 904 mutex_spin_enter(&sc->sc_task_mtx); 905 ring->queued--; 906 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 907 } 908 cv_broadcast(&sc->sc_task_cv); 909 mutex_spin_exit(&sc->sc_task_mtx); 910 splx(s); 911 } 912 913 static void 914 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 915 void *arg, int len) 916 { 917 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 918 struct urtwn_host_cmd *cmd; 919 int s; 920 921 URTWNHIST_FUNC(); 922 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 923 (uintptr_t)cb, (uintptr_t)arg, len, 0); 924 925 s = splusb(); 926 mutex_spin_enter(&sc->sc_task_mtx); 927 cmd = &ring->cmd[ring->cur]; 928 cmd->cb = cb; 929 KASSERT(len <= sizeof(cmd->data)); 930 memcpy(cmd->data, arg, len); 931 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 932 933 /* If there is no pending command already, schedule a task. */ 934 if (!sc->sc_dying && ++ring->queued == 1) { 935 mutex_spin_exit(&sc->sc_task_mtx); 936 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 937 } else 938 mutex_spin_exit(&sc->sc_task_mtx); 939 splx(s); 940 } 941 942 static void 943 urtwn_wait_async(struct urtwn_softc *sc) 944 { 945 946 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 947 948 /* Wait for all queued asynchronous commands to complete. */ 949 mutex_spin_enter(&sc->sc_task_mtx); 950 while (sc->cmdq.queued > 0) 951 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 952 mutex_spin_exit(&sc->sc_task_mtx); 953 } 954 955 static int 956 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 957 int len) 958 { 959 usb_device_request_t req; 960 usbd_status error; 961 962 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 963 KASSERT(mutex_owned(&sc->sc_write_mtx)); 964 965 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 966 req.bRequest = R92C_REQ_REGS; 967 USETW(req.wValue, addr); 968 USETW(req.wIndex, 0); 969 USETW(req.wLength, len); 970 error = usbd_do_request(sc->sc_udev, &req, buf); 971 if (error != USBD_NORMAL_COMPLETION) { 972 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 973 error, addr, len, 0); 974 } 975 return error; 976 } 977 978 static void 979 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 980 { 981 982 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 983 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 984 985 urtwn_write_region_1(sc, addr, &val, 1); 986 } 987 988 static void 989 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 990 { 991 uint8_t buf[2]; 992 993 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 994 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 995 996 buf[0] = (uint8_t)val; 997 buf[1] = (uint8_t)(val >> 8); 998 urtwn_write_region_1(sc, addr, buf, 2); 999 } 1000 1001 static void 1002 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1003 { 1004 uint8_t buf[4]; 1005 1006 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1007 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1008 1009 buf[0] = (uint8_t)val; 1010 buf[1] = (uint8_t)(val >> 8); 1011 buf[2] = (uint8_t)(val >> 16); 1012 buf[3] = (uint8_t)(val >> 24); 1013 urtwn_write_region_1(sc, addr, buf, 4); 1014 } 1015 1016 static int 1017 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1018 { 1019 1020 URTWNHIST_FUNC(); 1021 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1022 1023 return urtwn_write_region_1(sc, addr, buf, len); 1024 } 1025 1026 static int 1027 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1028 int len) 1029 { 1030 usb_device_request_t req; 1031 usbd_status error; 1032 1033 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1034 1035 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1036 req.bRequest = R92C_REQ_REGS; 1037 USETW(req.wValue, addr); 1038 USETW(req.wIndex, 0); 1039 USETW(req.wLength, len); 1040 error = usbd_do_request(sc->sc_udev, &req, buf); 1041 if (error != USBD_NORMAL_COMPLETION) { 1042 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1043 error, addr, len, 0); 1044 } 1045 return error; 1046 } 1047 1048 static uint8_t 1049 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1050 { 1051 uint8_t val; 1052 1053 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1054 1055 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1056 return 0xff; 1057 1058 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1059 return val; 1060 } 1061 1062 static uint16_t 1063 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1064 { 1065 uint8_t buf[2]; 1066 uint16_t val; 1067 1068 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1069 1070 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1071 return 0xffff; 1072 1073 val = LE_READ_2(&buf[0]); 1074 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1075 return val; 1076 } 1077 1078 static uint32_t 1079 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1080 { 1081 uint8_t buf[4]; 1082 uint32_t val; 1083 1084 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1085 1086 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1087 return 0xffffffff; 1088 1089 val = LE_READ_4(&buf[0]); 1090 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1091 return val; 1092 } 1093 1094 static int 1095 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1096 { 1097 struct r92c_fw_cmd cmd; 1098 uint8_t *cp; 1099 int fwcur; 1100 int ntries; 1101 1102 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1103 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1104 1105 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1106 1107 mutex_enter(&sc->sc_fwcmd_mtx); 1108 fwcur = sc->fwcur; 1109 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1110 1111 /* Wait for current FW box to be empty. */ 1112 for (ntries = 0; ntries < 100; ntries++) { 1113 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1114 break; 1115 urtwn_delay_ms(sc, 2); 1116 } 1117 if (ntries == 100) { 1118 aprint_error_dev(sc->sc_dev, 1119 "could not send firmware command %d\n", id); 1120 mutex_exit(&sc->sc_fwcmd_mtx); 1121 return ETIMEDOUT; 1122 } 1123 1124 memset(&cmd, 0, sizeof(cmd)); 1125 KASSERT(len <= sizeof(cmd.msg)); 1126 memcpy(cmd.msg, buf, len); 1127 1128 /* Write the first word last since that will trigger the FW. */ 1129 cp = (uint8_t *)&cmd; 1130 cmd.id = id; 1131 if (len >= 4) { 1132 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1133 cmd.id |= R92C_CMD_FLAG_EXT; 1134 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1135 &cp[1], 2); 1136 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1137 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1138 ((uint32_t)cp[5] << 24)); 1139 } else { 1140 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1141 &cp[4], 2); 1142 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1143 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1144 ((uint32_t)cp[3] << 24)); 1145 } 1146 } else { 1147 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1148 } 1149 mutex_exit(&sc->sc_fwcmd_mtx); 1150 1151 return 0; 1152 } 1153 1154 static __inline void 1155 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1156 { 1157 1158 sc->sc_rf_write(sc, chain, addr, val); 1159 } 1160 1161 static void 1162 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1163 uint32_t val) 1164 { 1165 1166 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1167 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1168 } 1169 1170 static void 1171 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1172 uint32_t val) 1173 { 1174 1175 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1176 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1177 } 1178 1179 static void 1180 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1181 uint32_t val) 1182 { 1183 1184 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1185 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1186 } 1187 1188 static uint32_t 1189 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1190 { 1191 uint32_t reg[R92C_MAX_CHAINS], val; 1192 1193 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1194 if (chain != 0) { 1195 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1196 } 1197 1198 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1199 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1200 urtwn_delay_ms(sc, 1); 1201 1202 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1203 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1204 R92C_HSSI_PARAM2_READ_EDGE); 1205 urtwn_delay_ms(sc, 1); 1206 1207 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1208 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1209 urtwn_delay_ms(sc, 1); 1210 1211 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1212 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1213 } else { 1214 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1215 } 1216 return MS(val, R92C_LSSI_READBACK_DATA); 1217 } 1218 1219 static int 1220 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1221 { 1222 int ntries; 1223 1224 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1225 1226 urtwn_write_4(sc, R92C_LLT_INIT, 1227 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1228 SM(R92C_LLT_INIT_ADDR, addr) | 1229 SM(R92C_LLT_INIT_DATA, data)); 1230 /* Wait for write operation to complete. */ 1231 for (ntries = 0; ntries < 20; ntries++) { 1232 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1233 R92C_LLT_INIT_OP_NO_ACTIVE) { 1234 /* Done */ 1235 return 0; 1236 } 1237 DELAY(5); 1238 } 1239 return ETIMEDOUT; 1240 } 1241 1242 static uint8_t 1243 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1244 { 1245 uint32_t reg; 1246 int ntries; 1247 1248 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1249 1250 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1251 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1252 reg &= ~R92C_EFUSE_CTRL_VALID; 1253 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1254 1255 /* Wait for read operation to complete. */ 1256 for (ntries = 0; ntries < 100; ntries++) { 1257 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1258 if (reg & R92C_EFUSE_CTRL_VALID) { 1259 /* Done */ 1260 return MS(reg, R92C_EFUSE_CTRL_DATA); 1261 } 1262 DELAY(5); 1263 } 1264 aprint_error_dev(sc->sc_dev, 1265 "could not read efuse byte at address 0x%04x\n", addr); 1266 return 0xff; 1267 } 1268 1269 static void 1270 urtwn_efuse_read(struct urtwn_softc *sc) 1271 { 1272 uint8_t *rom = (uint8_t *)&sc->rom; 1273 uint32_t reg; 1274 uint16_t addr = 0; 1275 uint8_t off, msk; 1276 size_t i; 1277 1278 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1279 1280 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1281 1282 urtwn_efuse_switch_power(sc); 1283 1284 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1285 while (addr < 512) { 1286 reg = urtwn_efuse_read_1(sc, addr); 1287 if (reg == 0xff) 1288 break; 1289 addr++; 1290 off = reg >> 4; 1291 msk = reg & 0xf; 1292 for (i = 0; i < 4; i++) { 1293 if (msk & (1U << i)) 1294 continue; 1295 1296 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1297 addr++; 1298 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1299 addr++; 1300 } 1301 } 1302 #ifdef URTWN_DEBUG 1303 /* Dump ROM content. */ 1304 for (i = 0; i < (int)sizeof(sc->rom); i++) 1305 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1306 #endif 1307 } 1308 1309 static void 1310 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1311 { 1312 uint32_t reg; 1313 1314 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1315 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1316 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1317 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1318 } 1319 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1320 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1321 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1322 reg | R92C_SYS_FUNC_EN_ELDR); 1323 } 1324 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1325 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1326 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1327 urtwn_write_2(sc, R92C_SYS_CLKR, 1328 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1329 } 1330 } 1331 1332 static int 1333 urtwn_read_chipid(struct urtwn_softc *sc) 1334 { 1335 uint32_t reg; 1336 1337 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1338 1339 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1340 ISSET(sc->chip, URTWN_CHIP_92EU)) 1341 return 0; 1342 1343 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1344 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1345 /* test chip, not supported */ 1346 return EIO; 1347 } 1348 if (reg & R92C_SYS_CFG_TYPE_92C) { 1349 sc->chip |= URTWN_CHIP_92C; 1350 /* Check if it is a castrated 8192C. */ 1351 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1352 R92C_HPON_FSM_CHIP_BONDING_ID) == 1353 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1354 sc->chip |= URTWN_CHIP_92C_1T2R; 1355 } 1356 } 1357 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1358 sc->chip |= URTWN_CHIP_UMC; 1359 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1360 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1361 } 1362 } 1363 return 0; 1364 } 1365 1366 #ifdef URTWN_DEBUG 1367 static void 1368 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1369 { 1370 1371 aprint_normal_dev(sc->sc_dev, 1372 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1373 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1374 1375 aprint_normal_dev(sc->sc_dev, 1376 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1377 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1378 1379 aprint_normal_dev(sc->sc_dev, 1380 "macaddr %s\n", 1381 ether_sprintf(rp->macaddr)); 1382 1383 aprint_normal_dev(sc->sc_dev, 1384 "string %s, subcustomer_id %#x\n", 1385 rp->string, rp->subcustomer_id); 1386 1387 aprint_normal_dev(sc->sc_dev, 1388 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1389 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1390 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1391 1392 aprint_normal_dev(sc->sc_dev, 1393 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1394 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1395 rp->ht40_1s_tx_pwr[0][2], 1396 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1397 rp->ht40_1s_tx_pwr[1][2]); 1398 1399 aprint_normal_dev(sc->sc_dev, 1400 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1401 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1402 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1403 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1404 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1405 1406 aprint_normal_dev(sc->sc_dev, 1407 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1408 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1409 rp->ht20_tx_pwr_diff[2] & 0xf, 1410 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1411 rp->ht20_tx_pwr_diff[2] >> 4); 1412 1413 aprint_normal_dev(sc->sc_dev, 1414 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1415 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1416 rp->ofdm_tx_pwr_diff[2] & 0xf, 1417 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1418 rp->ofdm_tx_pwr_diff[2] >> 4); 1419 1420 aprint_normal_dev(sc->sc_dev, 1421 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1422 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1423 rp->ht40_max_pwr[2] & 0xf, 1424 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1425 rp->ht40_max_pwr[2] >> 4); 1426 1427 aprint_normal_dev(sc->sc_dev, 1428 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1429 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1430 rp->ht20_max_pwr[2] & 0xf, 1431 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1432 rp->ht20_max_pwr[2] >> 4); 1433 1434 aprint_normal_dev(sc->sc_dev, 1435 "xtal_calib %d, tssi %d %d, thermal %d\n", 1436 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1437 1438 aprint_normal_dev(sc->sc_dev, 1439 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1440 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1441 1442 aprint_normal_dev(sc->sc_dev, 1443 "channnel_plan %d, version %d customer_id %#x\n", 1444 rp->channel_plan, rp->version, rp->curstomer_id); 1445 } 1446 #endif 1447 1448 static void 1449 urtwn_read_rom(struct urtwn_softc *sc) 1450 { 1451 struct ieee80211com *ic = &sc->sc_ic; 1452 struct r92c_rom *rom = &sc->rom; 1453 1454 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1455 1456 mutex_enter(&sc->sc_write_mtx); 1457 1458 /* Read full ROM image. */ 1459 urtwn_efuse_read(sc); 1460 #ifdef URTWN_DEBUG 1461 if (urtwn_debug & DBG_REG) 1462 urtwn_dump_rom(sc, rom); 1463 #endif 1464 1465 /* XXX Weird but this is what the vendor driver does. */ 1466 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1467 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1468 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1469 1470 DPRINTFN(DBG_INIT, 1471 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1472 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1473 1474 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1475 1476 sc->sc_rf_write = urtwn_r92c_rf_write; 1477 sc->sc_power_on = urtwn_r92c_power_on; 1478 sc->sc_dma_init = urtwn_r92c_dma_init; 1479 1480 mutex_exit(&sc->sc_write_mtx); 1481 } 1482 1483 static void 1484 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1485 { 1486 struct ieee80211com *ic = &sc->sc_ic; 1487 uint8_t *rom = sc->r88e_rom; 1488 uint32_t reg; 1489 uint16_t addr = 0; 1490 uint8_t off, msk, tmp; 1491 int i; 1492 1493 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1494 1495 mutex_enter(&sc->sc_write_mtx); 1496 1497 off = 0; 1498 urtwn_efuse_switch_power(sc); 1499 1500 /* Read full ROM image. */ 1501 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1502 while (addr < 4096) { 1503 reg = urtwn_efuse_read_1(sc, addr); 1504 if (reg == 0xff) 1505 break; 1506 addr++; 1507 if ((reg & 0x1f) == 0x0f) { 1508 tmp = (reg & 0xe0) >> 5; 1509 reg = urtwn_efuse_read_1(sc, addr); 1510 if ((reg & 0x0f) != 0x0f) 1511 off = ((reg & 0xf0) >> 1) | tmp; 1512 addr++; 1513 } else 1514 off = reg >> 4; 1515 msk = reg & 0xf; 1516 for (i = 0; i < 4; i++) { 1517 if (msk & (1 << i)) 1518 continue; 1519 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1520 addr++; 1521 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1522 addr++; 1523 } 1524 } 1525 #ifdef URTWN_DEBUG 1526 if (urtwn_debug & DBG_REG) { 1527 } 1528 #endif 1529 1530 addr = 0x10; 1531 for (i = 0; i < 6; i++) 1532 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1533 for (i = 0; i < 5; i++) 1534 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1535 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1536 if (sc->bw20_tx_pwr_diff & 0x08) 1537 sc->bw20_tx_pwr_diff |= 0xf0; 1538 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1539 if (sc->ofdm_tx_pwr_diff & 0x08) 1540 sc->ofdm_tx_pwr_diff |= 0xf0; 1541 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1542 1543 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1544 1545 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1546 sc->sc_power_on = urtwn_r92e_power_on; 1547 sc->sc_rf_write = urtwn_r92e_rf_write; 1548 } else { 1549 sc->sc_power_on = urtwn_r88e_power_on; 1550 sc->sc_rf_write = urtwn_r88e_rf_write; 1551 } 1552 sc->sc_dma_init = urtwn_r88e_dma_init; 1553 1554 mutex_exit(&sc->sc_write_mtx); 1555 } 1556 1557 static int 1558 urtwn_media_change(struct ifnet *ifp) 1559 { 1560 int error; 1561 1562 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1563 1564 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1565 return error; 1566 1567 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1568 (IFF_UP | IFF_RUNNING)) { 1569 urtwn_init(ifp); 1570 } 1571 return 0; 1572 } 1573 1574 /* 1575 * Initialize rate adaptation in firmware. 1576 */ 1577 static int __noinline 1578 urtwn_ra_init(struct urtwn_softc *sc) 1579 { 1580 static const uint8_t map[] = { 1581 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1582 }; 1583 struct ieee80211com *ic = &sc->sc_ic; 1584 struct ieee80211_node *ni = ic->ic_bss; 1585 struct ieee80211_rateset *rs = &ni->ni_rates; 1586 struct r92c_fw_cmd_macid_cfg cmd; 1587 uint32_t rates, basicrates; 1588 uint32_t rrsr_mask, rrsr_rate; 1589 uint8_t mode; 1590 size_t maxrate, maxbasicrate, i, j; 1591 int error; 1592 1593 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1594 1595 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1596 1597 /* Get normal and basic rates mask. */ 1598 rates = basicrates = 1; 1599 maxrate = maxbasicrate = 0; 1600 for (i = 0; i < rs->rs_nrates; i++) { 1601 /* Convert 802.11 rate to HW rate index. */ 1602 for (j = 0; j < __arraycount(map); j++) { 1603 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1604 break; 1605 } 1606 } 1607 if (j == __arraycount(map)) { 1608 /* Unknown rate, skip. */ 1609 continue; 1610 } 1611 1612 rates |= 1U << j; 1613 if (j > maxrate) { 1614 maxrate = j; 1615 } 1616 1617 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1618 basicrates |= 1U << j; 1619 if (j > maxbasicrate) { 1620 maxbasicrate = j; 1621 } 1622 } 1623 } 1624 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1625 mode = R92C_RAID_11B; 1626 } else { 1627 mode = R92C_RAID_11BG; 1628 } 1629 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1630 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1631 "maxrate=%jx, maxbasicrate=%jx", 1632 rates, basicrates, maxrate, maxbasicrate); 1633 1634 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1635 maxbasicrate |= R92C_RATE_SHORTGI; 1636 maxrate |= R92C_RATE_SHORTGI; 1637 } 1638 1639 /* Set rates mask for group addressed frames. */ 1640 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1641 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1642 cmd.macid |= RTWN_MACID_SHORTGI; 1643 cmd.mask = htole32((mode << 28) | basicrates); 1644 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1645 if (error != 0) { 1646 aprint_error_dev(sc->sc_dev, 1647 "could not add broadcast station\n"); 1648 return error; 1649 } 1650 /* Set initial MRR rate. */ 1651 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1652 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1653 1654 /* Set rates mask for unicast frames. */ 1655 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1656 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1657 cmd.macid |= RTWN_MACID_SHORTGI; 1658 cmd.mask = htole32((mode << 28) | rates); 1659 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1660 if (error != 0) { 1661 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1662 return error; 1663 } 1664 /* Set initial MRR rate. */ 1665 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1666 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1667 1668 rrsr_rate = ic->ic_fixed_rate; 1669 if (rrsr_rate == -1) 1670 rrsr_rate = 11; 1671 1672 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1673 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1674 1675 /* Indicate highest supported rate. */ 1676 ni->ni_txrate = rs->rs_nrates - 1; 1677 1678 return 0; 1679 } 1680 1681 static int 1682 urtwn_get_nettype(struct urtwn_softc *sc) 1683 { 1684 struct ieee80211com *ic = &sc->sc_ic; 1685 int type; 1686 1687 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1688 1689 switch (ic->ic_opmode) { 1690 case IEEE80211_M_STA: 1691 type = R92C_CR_NETTYPE_INFRA; 1692 break; 1693 1694 case IEEE80211_M_IBSS: 1695 type = R92C_CR_NETTYPE_ADHOC; 1696 break; 1697 1698 default: 1699 type = R92C_CR_NETTYPE_NOLINK; 1700 break; 1701 } 1702 1703 return type; 1704 } 1705 1706 static void 1707 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1708 { 1709 uint8_t reg; 1710 1711 URTWNHIST_FUNC(); 1712 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1713 1714 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1715 1716 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1717 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1718 } 1719 1720 static void 1721 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1722 { 1723 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1724 uint64_t tsf; 1725 1726 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1727 1728 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1729 1730 /* Enable TSF synchronization. */ 1731 urtwn_write_1(sc, R92C_BCN_CTRL, 1732 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1733 1734 /* Correct TSF */ 1735 urtwn_write_1(sc, R92C_BCN_CTRL, 1736 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1737 1738 /* Set initial TSF. */ 1739 tsf = ni->ni_tstamp.tsf; 1740 tsf = le64toh(tsf); 1741 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1742 tsf -= IEEE80211_DUR_TU; 1743 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1744 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1745 1746 urtwn_write_1(sc, R92C_BCN_CTRL, 1747 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1748 } 1749 1750 static void 1751 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1752 { 1753 uint8_t reg; 1754 1755 URTWNHIST_FUNC(); 1756 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1757 1758 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1759 1760 if (led == URTWN_LED_LINK) { 1761 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1762 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1763 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1764 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1765 (R92C_LEDCFG0_DIS << 1)); 1766 if (on) { 1767 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1768 R92E_LEDSON; 1769 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1770 } 1771 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1772 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1773 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1774 if (!on) { 1775 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1776 urtwn_write_1(sc, R92C_LEDCFG2, 1777 reg | R92C_LEDCFG0_DIS); 1778 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1779 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1780 reg & 0xfe); 1781 } 1782 } else { 1783 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1784 if (!on) { 1785 reg |= R92C_LEDCFG0_DIS; 1786 } 1787 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1788 } 1789 sc->ledlink = on; /* Save LED state. */ 1790 } 1791 } 1792 1793 static void 1794 urtwn_calib_to(void *arg) 1795 { 1796 struct urtwn_softc *sc = arg; 1797 1798 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1799 1800 if (sc->sc_dying) 1801 return; 1802 1803 /* Do it in a process context. */ 1804 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1805 } 1806 1807 /* ARGSUSED */ 1808 static void 1809 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1810 { 1811 struct r92c_fw_cmd_rssi cmd; 1812 struct r92e_fw_cmd_rssi cmde; 1813 1814 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1815 1816 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1817 goto restart_timer; 1818 1819 mutex_enter(&sc->sc_write_mtx); 1820 if (sc->avg_pwdb != -1) { 1821 /* Indicate Rx signal strength to FW for rate adaptation. */ 1822 memset(&cmd, 0, sizeof(cmd)); 1823 memset(&cmde, 0, sizeof(cmde)); 1824 cmd.macid = 0; /* BSS. */ 1825 cmde.macid = 0; /* BSS. */ 1826 cmd.pwdb = sc->avg_pwdb; 1827 cmde.pwdb = sc->avg_pwdb; 1828 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1829 sc->avg_pwdb, 0, 0, 0); 1830 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1831 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1832 sizeof(cmd)); 1833 } else { 1834 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1835 sizeof(cmde)); 1836 } 1837 } 1838 1839 /* Do temperature compensation. */ 1840 urtwn_temp_calib(sc); 1841 mutex_exit(&sc->sc_write_mtx); 1842 1843 restart_timer: 1844 if (!sc->sc_dying) { 1845 /* Restart calibration timer. */ 1846 callout_schedule(&sc->sc_calib_to, hz); 1847 } 1848 } 1849 1850 static void 1851 urtwn_next_scan(void *arg) 1852 { 1853 struct urtwn_softc *sc = arg; 1854 int s; 1855 1856 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1857 1858 if (sc->sc_dying) 1859 return; 1860 1861 s = splnet(); 1862 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1863 ieee80211_next_scan(&sc->sc_ic); 1864 splx(s); 1865 } 1866 1867 static void 1868 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1869 { 1870 URTWNHIST_FUNC(); 1871 URTWNHIST_CALLARGS("new node %06jx%06jx", 1872 ni->ni_macaddr[0] << 2 | 1873 ni->ni_macaddr[1] << 1 | 1874 ni->ni_macaddr[2], 1875 ni->ni_macaddr[3] << 2 | 1876 ni->ni_macaddr[4] << 1 | 1877 ni->ni_macaddr[5], 1878 0, 0); 1879 /* start with lowest Tx rate */ 1880 ni->ni_txrate = 0; 1881 } 1882 1883 static int 1884 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1885 { 1886 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1887 struct urtwn_cmd_newstate cmd; 1888 1889 URTWNHIST_FUNC(); 1890 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1891 1892 callout_stop(&sc->sc_scan_to); 1893 callout_stop(&sc->sc_calib_to); 1894 1895 /* Do it in a process context. */ 1896 cmd.state = nstate; 1897 cmd.arg = arg; 1898 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1899 return 0; 1900 } 1901 1902 static void 1903 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1904 { 1905 struct urtwn_cmd_newstate *cmd = arg; 1906 struct ieee80211com *ic = &sc->sc_ic; 1907 struct ieee80211_node *ni; 1908 enum ieee80211_state ostate = ic->ic_state; 1909 enum ieee80211_state nstate = cmd->state; 1910 uint32_t reg; 1911 uint8_t sifs_time, msr; 1912 int s; 1913 1914 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1915 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1916 1917 s = splnet(); 1918 mutex_enter(&sc->sc_write_mtx); 1919 1920 callout_stop(&sc->sc_scan_to); 1921 callout_stop(&sc->sc_calib_to); 1922 1923 switch (ostate) { 1924 case IEEE80211_S_INIT: 1925 break; 1926 1927 case IEEE80211_S_SCAN: 1928 if (nstate != IEEE80211_S_SCAN) { 1929 /* 1930 * End of scanning 1931 */ 1932 /* flush 4-AC Queue after site_survey */ 1933 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1934 1935 /* Allow Rx from our BSSID only. */ 1936 urtwn_write_4(sc, R92C_RCR, 1937 urtwn_read_4(sc, R92C_RCR) | 1938 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1939 } 1940 break; 1941 1942 case IEEE80211_S_AUTH: 1943 case IEEE80211_S_ASSOC: 1944 break; 1945 1946 case IEEE80211_S_RUN: 1947 /* Turn link LED off. */ 1948 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1949 1950 /* Set media status to 'No Link'. */ 1951 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1952 1953 /* Stop Rx of data frames. */ 1954 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1955 1956 /* Reset TSF. */ 1957 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1958 1959 /* Disable TSF synchronization. */ 1960 urtwn_write_1(sc, R92C_BCN_CTRL, 1961 urtwn_read_1(sc, R92C_BCN_CTRL) | 1962 R92C_BCN_CTRL_DIS_TSF_UDT0); 1963 1964 /* Back to 20MHz mode */ 1965 urtwn_set_chan(sc, ic->ic_curchan, 1966 IEEE80211_HTINFO_2NDCHAN_NONE); 1967 1968 if (ic->ic_opmode == IEEE80211_M_IBSS || 1969 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1970 /* Stop BCN */ 1971 urtwn_write_1(sc, R92C_BCN_CTRL, 1972 urtwn_read_1(sc, R92C_BCN_CTRL) & 1973 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1974 } 1975 1976 /* Reset EDCA parameters. */ 1977 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1978 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1979 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1980 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1981 1982 /* flush all cam entries */ 1983 urtwn_cam_init(sc); 1984 break; 1985 } 1986 1987 switch (nstate) { 1988 case IEEE80211_S_INIT: 1989 /* Turn link LED off. */ 1990 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1991 break; 1992 1993 case IEEE80211_S_SCAN: 1994 if (ostate != IEEE80211_S_SCAN) { 1995 /* 1996 * Begin of scanning 1997 */ 1998 1999 /* Set gain for scanning. */ 2000 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2001 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2002 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2003 2004 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2005 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2006 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2007 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2008 } 2009 2010 /* Set media status to 'No Link'. */ 2011 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2012 2013 /* Allow Rx from any BSSID. */ 2014 urtwn_write_4(sc, R92C_RCR, 2015 urtwn_read_4(sc, R92C_RCR) & 2016 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2017 2018 /* Stop Rx of data frames. */ 2019 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2020 2021 /* Disable update TSF */ 2022 urtwn_write_1(sc, R92C_BCN_CTRL, 2023 urtwn_read_1(sc, R92C_BCN_CTRL) | 2024 R92C_BCN_CTRL_DIS_TSF_UDT0); 2025 } 2026 2027 /* Make link LED blink during scan. */ 2028 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2029 2030 /* Pause AC Tx queues. */ 2031 urtwn_write_1(sc, R92C_TXPAUSE, 2032 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2033 2034 urtwn_set_chan(sc, ic->ic_curchan, 2035 IEEE80211_HTINFO_2NDCHAN_NONE); 2036 2037 /* Start periodic scan. */ 2038 if (!sc->sc_dying) 2039 callout_schedule(&sc->sc_scan_to, hz / 5); 2040 break; 2041 2042 case IEEE80211_S_AUTH: 2043 /* Set initial gain under link. */ 2044 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2045 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2046 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2047 2048 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2049 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2050 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2051 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2052 } 2053 2054 /* Set media status to 'No Link'. */ 2055 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2056 2057 /* Allow Rx from any BSSID. */ 2058 urtwn_write_4(sc, R92C_RCR, 2059 urtwn_read_4(sc, R92C_RCR) & 2060 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2061 2062 urtwn_set_chan(sc, ic->ic_curchan, 2063 IEEE80211_HTINFO_2NDCHAN_NONE); 2064 break; 2065 2066 case IEEE80211_S_ASSOC: 2067 break; 2068 2069 case IEEE80211_S_RUN: 2070 ni = ic->ic_bss; 2071 2072 /* XXX: Set 20MHz mode */ 2073 urtwn_set_chan(sc, ic->ic_curchan, 2074 IEEE80211_HTINFO_2NDCHAN_NONE); 2075 2076 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2077 /* Back to 20MHz mode */ 2078 urtwn_set_chan(sc, ic->ic_curchan, 2079 IEEE80211_HTINFO_2NDCHAN_NONE); 2080 2081 /* Set media status to 'No Link'. */ 2082 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2083 2084 /* Enable Rx of data frames. */ 2085 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2086 2087 /* Allow Rx from any BSSID. */ 2088 urtwn_write_4(sc, R92C_RCR, 2089 urtwn_read_4(sc, R92C_RCR) & 2090 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2091 2092 /* Accept Rx data/control/management frames */ 2093 urtwn_write_4(sc, R92C_RCR, 2094 urtwn_read_4(sc, R92C_RCR) | 2095 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2096 2097 /* Turn link LED on. */ 2098 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2099 break; 2100 } 2101 2102 /* Set media status to 'Associated'. */ 2103 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2104 2105 /* Set BSSID. */ 2106 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2107 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2108 2109 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2110 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2111 } else { 2112 /* 802.11b/g */ 2113 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2114 } 2115 2116 /* Enable Rx of data frames. */ 2117 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2118 2119 /* Set beacon interval. */ 2120 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2121 2122 msr = urtwn_read_1(sc, R92C_MSR); 2123 msr &= R92C_MSR_MASK; 2124 switch (ic->ic_opmode) { 2125 case IEEE80211_M_STA: 2126 /* Allow Rx from our BSSID only. */ 2127 urtwn_write_4(sc, R92C_RCR, 2128 urtwn_read_4(sc, R92C_RCR) | 2129 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2130 2131 /* Enable TSF synchronization. */ 2132 urtwn_tsf_sync_enable(sc); 2133 2134 msr |= R92C_MSR_INFRA; 2135 break; 2136 case IEEE80211_M_HOSTAP: 2137 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2138 2139 /* Allow Rx from any BSSID. */ 2140 urtwn_write_4(sc, R92C_RCR, 2141 urtwn_read_4(sc, R92C_RCR) & 2142 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2143 2144 /* Reset TSF timer to zero. */ 2145 reg = urtwn_read_4(sc, R92C_TCR); 2146 reg &= ~0x01; 2147 urtwn_write_4(sc, R92C_TCR, reg); 2148 reg |= 0x01; 2149 urtwn_write_4(sc, R92C_TCR, reg); 2150 2151 msr |= R92C_MSR_AP; 2152 break; 2153 default: 2154 msr |= R92C_MSR_ADHOC; 2155 break; 2156 } 2157 urtwn_write_1(sc, R92C_MSR, msr); 2158 2159 sifs_time = 10; 2160 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2161 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2162 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2163 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2164 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2165 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2166 2167 /* Initialize rate adaptation. */ 2168 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2169 ISSET(sc->chip, URTWN_CHIP_92EU)) 2170 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2171 else 2172 urtwn_ra_init(sc); 2173 2174 /* Turn link LED on. */ 2175 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2176 2177 /* Reset average RSSI. */ 2178 sc->avg_pwdb = -1; 2179 2180 /* Reset temperature calibration state machine. */ 2181 sc->thcal_state = 0; 2182 sc->thcal_lctemp = 0; 2183 2184 /* Start periodic calibration. */ 2185 if (!sc->sc_dying) 2186 callout_schedule(&sc->sc_calib_to, hz); 2187 break; 2188 } 2189 2190 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2191 2192 mutex_exit(&sc->sc_write_mtx); 2193 splx(s); 2194 } 2195 2196 static int 2197 urtwn_wme_update(struct ieee80211com *ic) 2198 { 2199 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2200 2201 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2202 2203 /* don't override default WME values if WME is not actually enabled */ 2204 if (!(ic->ic_flags & IEEE80211_F_WME)) 2205 return 0; 2206 2207 /* Do it in a process context. */ 2208 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2209 return 0; 2210 } 2211 2212 static void 2213 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2214 { 2215 static const uint16_t ac2reg[WME_NUM_AC] = { 2216 R92C_EDCA_BE_PARAM, 2217 R92C_EDCA_BK_PARAM, 2218 R92C_EDCA_VI_PARAM, 2219 R92C_EDCA_VO_PARAM 2220 }; 2221 struct ieee80211com *ic = &sc->sc_ic; 2222 const struct wmeParams *wmep; 2223 int ac, aifs, slottime; 2224 int s; 2225 2226 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2227 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2228 2229 s = splnet(); 2230 mutex_enter(&sc->sc_write_mtx); 2231 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2232 for (ac = 0; ac < WME_NUM_AC; ac++) { 2233 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2234 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2235 aifs = wmep->wmep_aifsn * slottime + 10; 2236 urtwn_write_4(sc, ac2reg[ac], 2237 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2238 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2239 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2240 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2241 } 2242 mutex_exit(&sc->sc_write_mtx); 2243 splx(s); 2244 } 2245 2246 static void 2247 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2248 { 2249 int pwdb; 2250 2251 URTWNHIST_FUNC(); 2252 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2253 2254 /* Convert antenna signal to percentage. */ 2255 if (rssi <= -100 || rssi >= 20) 2256 pwdb = 0; 2257 else if (rssi >= 0) 2258 pwdb = 100; 2259 else 2260 pwdb = 100 + rssi; 2261 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2262 if (rate <= 3) { 2263 /* CCK gain is smaller than OFDM/MCS gain. */ 2264 pwdb += 6; 2265 if (pwdb > 100) 2266 pwdb = 100; 2267 if (pwdb <= 14) 2268 pwdb -= 4; 2269 else if (pwdb <= 26) 2270 pwdb -= 8; 2271 else if (pwdb <= 34) 2272 pwdb -= 6; 2273 else if (pwdb <= 42) 2274 pwdb -= 2; 2275 } 2276 } 2277 if (sc->avg_pwdb == -1) /* Init. */ 2278 sc->avg_pwdb = pwdb; 2279 else if (sc->avg_pwdb < pwdb) 2280 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2281 else 2282 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2283 2284 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2285 rate, rssi, pwdb, sc->avg_pwdb); 2286 } 2287 2288 static int8_t 2289 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2290 { 2291 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2292 struct r92c_rx_phystat *phy; 2293 struct r92c_rx_cck *cck; 2294 uint8_t rpt; 2295 int8_t rssi; 2296 2297 URTWNHIST_FUNC(); 2298 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2299 2300 if (rate <= 3) { 2301 cck = (struct r92c_rx_cck *)physt; 2302 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2303 rpt = (cck->agc_rpt >> 5) & 0x3; 2304 rssi = (cck->agc_rpt & 0x1f) << 1; 2305 } else { 2306 rpt = (cck->agc_rpt >> 6) & 0x3; 2307 rssi = cck->agc_rpt & 0x3e; 2308 } 2309 rssi = cckoff[rpt] - rssi; 2310 } else { /* OFDM/HT. */ 2311 phy = (struct r92c_rx_phystat *)physt; 2312 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2313 } 2314 return rssi; 2315 } 2316 2317 static int8_t 2318 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2319 { 2320 struct r92c_rx_phystat *phy; 2321 struct r88e_rx_cck *cck; 2322 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2323 int8_t rssi; 2324 2325 URTWNHIST_FUNC(); 2326 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2327 2328 rssi = 0; 2329 if (rate <= 3) { 2330 cck = (struct r88e_rx_cck *)physt; 2331 cck_agc_rpt = cck->agc_rpt; 2332 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2333 vga_idx = cck_agc_rpt & 0x1f; 2334 switch (lna_idx) { 2335 case 7: 2336 if (vga_idx <= 27) 2337 rssi = -100 + 2* (27 - vga_idx); 2338 else 2339 rssi = -100; 2340 break; 2341 case 6: 2342 rssi = -48 + 2 * (2 - vga_idx); 2343 break; 2344 case 5: 2345 rssi = -42 + 2 * (7 - vga_idx); 2346 break; 2347 case 4: 2348 rssi = -36 + 2 * (7 - vga_idx); 2349 break; 2350 case 3: 2351 rssi = -24 + 2 * (7 - vga_idx); 2352 break; 2353 case 2: 2354 rssi = -12 + 2 * (5 - vga_idx); 2355 break; 2356 case 1: 2357 rssi = 8 - (2 * vga_idx); 2358 break; 2359 case 0: 2360 rssi = 14 - (2 * vga_idx); 2361 break; 2362 } 2363 rssi += 6; 2364 } else { /* OFDM/HT. */ 2365 phy = (struct r92c_rx_phystat *)physt; 2366 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2367 } 2368 return rssi; 2369 } 2370 2371 static void 2372 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2373 { 2374 struct ieee80211com *ic = &sc->sc_ic; 2375 struct ifnet *ifp = ic->ic_ifp; 2376 struct ieee80211_frame *wh; 2377 struct ieee80211_node *ni; 2378 struct r92c_rx_desc_usb *stat; 2379 uint32_t rxdw0, rxdw3; 2380 struct mbuf *m; 2381 uint8_t rate; 2382 int8_t rssi = 0; 2383 int s, infosz; 2384 2385 URTWNHIST_FUNC(); 2386 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2387 2388 stat = (struct r92c_rx_desc_usb *)buf; 2389 rxdw0 = le32toh(stat->rxdw0); 2390 rxdw3 = le32toh(stat->rxdw3); 2391 2392 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2393 /* 2394 * This should not happen since we setup our Rx filter 2395 * to not receive these frames. 2396 */ 2397 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2398 if_statinc(ifp, if_ierrors); 2399 return; 2400 } 2401 /* 2402 * XXX: This will drop most control packets. Do we really 2403 * want this in IEEE80211_M_MONITOR mode? 2404 */ 2405 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2406 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2407 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2408 ic->ic_stats.is_rx_tooshort++; 2409 if_statinc(ifp, if_ierrors); 2410 return; 2411 } 2412 if (__predict_false(pktlen > MCLBYTES)) { 2413 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2414 if_statinc(ifp, if_ierrors); 2415 return; 2416 } 2417 2418 rate = MS(rxdw3, R92C_RXDW3_RATE); 2419 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2420 2421 /* Get RSSI from PHY status descriptor if present. */ 2422 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2423 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2424 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2425 else 2426 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2427 /* Update our average RSSI. */ 2428 urtwn_update_avgrssi(sc, rate, rssi); 2429 } 2430 2431 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2432 pktlen, rate, infosz, rssi); 2433 2434 MGETHDR(m, M_DONTWAIT, MT_DATA); 2435 if (__predict_false(m == NULL)) { 2436 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2437 ic->ic_stats.is_rx_nobuf++; 2438 if_statinc(ifp, if_ierrors); 2439 return; 2440 } 2441 if (pktlen > (int)MHLEN) { 2442 MCLGET(m, M_DONTWAIT); 2443 if (__predict_false(!(m->m_flags & M_EXT))) { 2444 aprint_error_dev(sc->sc_dev, 2445 "couldn't allocate rx mbuf cluster\n"); 2446 m_freem(m); 2447 ic->ic_stats.is_rx_nobuf++; 2448 if_statinc(ifp, if_ierrors); 2449 return; 2450 } 2451 } 2452 2453 /* Finalize mbuf. */ 2454 m_set_rcvif(m, ifp); 2455 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2456 memcpy(mtod(m, uint8_t *), wh, pktlen); 2457 m->m_pkthdr.len = m->m_len = pktlen; 2458 2459 s = splnet(); 2460 if (__predict_false(sc->sc_drvbpf != NULL)) { 2461 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2462 2463 tap->wr_flags = 0; 2464 if (!(rxdw3 & R92C_RXDW3_HT)) { 2465 switch (rate) { 2466 /* CCK. */ 2467 case 0: tap->wr_rate = 2; break; 2468 case 1: tap->wr_rate = 4; break; 2469 case 2: tap->wr_rate = 11; break; 2470 case 3: tap->wr_rate = 22; break; 2471 /* OFDM. */ 2472 case 4: tap->wr_rate = 12; break; 2473 case 5: tap->wr_rate = 18; break; 2474 case 6: tap->wr_rate = 24; break; 2475 case 7: tap->wr_rate = 36; break; 2476 case 8: tap->wr_rate = 48; break; 2477 case 9: tap->wr_rate = 72; break; 2478 case 10: tap->wr_rate = 96; break; 2479 case 11: tap->wr_rate = 108; break; 2480 } 2481 } else if (rate >= 12) { /* MCS0~15. */ 2482 /* Bit 7 set means HT MCS instead of rate. */ 2483 tap->wr_rate = 0x80 | (rate - 12); 2484 } 2485 tap->wr_dbm_antsignal = rssi; 2486 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2487 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2488 2489 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2490 } 2491 2492 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2493 2494 /* push the frame up to the 802.11 stack */ 2495 ieee80211_input(ic, m, ni, rssi, 0); 2496 2497 /* Node is no longer needed. */ 2498 ieee80211_free_node(ni); 2499 2500 splx(s); 2501 } 2502 2503 static void 2504 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2505 { 2506 struct urtwn_rx_data *data = priv; 2507 struct urtwn_softc *sc = data->sc; 2508 struct r92c_rx_desc_usb *stat; 2509 size_t pidx = data->pidx; 2510 uint32_t rxdw0; 2511 uint8_t *buf; 2512 int len, totlen, pktlen, infosz, npkts; 2513 2514 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2515 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2516 2517 mutex_enter(&sc->sc_rx_mtx); 2518 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2519 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2520 /* Put this Rx buffer back to our free list. */ 2521 mutex_exit(&sc->sc_rx_mtx); 2522 2523 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2524 if (status == USBD_STALLED) 2525 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2526 else if (status != USBD_CANCELLED) 2527 goto resubmit; 2528 return; 2529 } 2530 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2531 2532 if (__predict_false(len < (int)sizeof(*stat))) { 2533 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2534 goto resubmit; 2535 } 2536 buf = data->buf; 2537 2538 /* Get the number of encapsulated frames. */ 2539 stat = (struct r92c_rx_desc_usb *)buf; 2540 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2541 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2542 else 2543 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2544 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2545 2546 if (npkts != 0) 2547 rnd_add_uint32(&sc->rnd_source, npkts); 2548 2549 /* Process all of them. */ 2550 while (npkts-- > 0) { 2551 if (__predict_false(len < (int)sizeof(*stat))) { 2552 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2553 len, 0, 0, 0); 2554 break; 2555 } 2556 stat = (struct r92c_rx_desc_usb *)buf; 2557 rxdw0 = le32toh(stat->rxdw0); 2558 2559 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2560 if (__predict_false(pktlen == 0)) { 2561 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2562 break; 2563 } 2564 2565 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2566 2567 /* Make sure everything fits in xfer. */ 2568 totlen = sizeof(*stat) + infosz + pktlen; 2569 if (__predict_false(totlen > len)) { 2570 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2571 (int)sizeof(*stat), infosz, pktlen, len); 2572 break; 2573 } 2574 2575 /* Process 802.11 frame. */ 2576 urtwn_rx_frame(sc, buf, pktlen); 2577 2578 /* Next chunk is 128-byte aligned. */ 2579 totlen = roundup2(totlen, 128); 2580 buf += totlen; 2581 len -= totlen; 2582 } 2583 2584 resubmit: 2585 /* Setup a new transfer. */ 2586 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2587 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2588 (void)usbd_transfer(xfer); 2589 } 2590 2591 static void 2592 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2593 { 2594 size_t pidx = data->pidx; 2595 2596 mutex_enter(&sc->sc_tx_mtx); 2597 /* Put this Tx buffer back to our free list. */ 2598 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2599 mutex_exit(&sc->sc_tx_mtx); 2600 } 2601 2602 static void 2603 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2604 { 2605 struct urtwn_tx_data *data = priv; 2606 struct urtwn_softc *sc = data->sc; 2607 struct ifnet *ifp = &sc->sc_if; 2608 size_t pidx = data->pidx; 2609 int s; 2610 2611 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2612 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2613 2614 urtwn_put_tx_data(sc, data); 2615 2616 s = splnet(); 2617 sc->tx_timer = 0; 2618 ifp->if_flags &= ~IFF_OACTIVE; 2619 2620 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2621 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2622 if (status == USBD_STALLED) { 2623 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2624 usbd_clear_endpoint_stall_async(pipe); 2625 } 2626 device_printf(sc->sc_dev, "device timeout\n"); 2627 if_statinc(ifp, if_oerrors); 2628 } 2629 splx(s); 2630 return; 2631 } 2632 2633 if_statinc(ifp, if_opackets); 2634 urtwn_start(ifp); 2635 splx(s); 2636 2637 } 2638 2639 static int 2640 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2641 struct urtwn_tx_data *data) 2642 { 2643 struct ieee80211com *ic = &sc->sc_ic; 2644 struct ieee80211_frame *wh; 2645 struct ieee80211_key *k = NULL; 2646 struct r92c_tx_desc_usb *txd; 2647 size_t i, padsize, xferlen, txd_len; 2648 uint16_t seq, sum; 2649 uint8_t raid, type, tid; 2650 int s, hasqos, error; 2651 2652 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2653 2654 wh = mtod(m, struct ieee80211_frame *); 2655 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2656 txd_len = sizeof(*txd); 2657 2658 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2659 txd_len = 32; 2660 2661 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2662 k = ieee80211_crypto_encap(ic, ni, m); 2663 if (k == NULL) { 2664 urtwn_put_tx_data(sc, data); 2665 m_free(m); 2666 return ENOBUFS; 2667 } 2668 2669 /* packet header may have moved, reset our local pointer */ 2670 wh = mtod(m, struct ieee80211_frame *); 2671 } 2672 2673 if (__predict_false(sc->sc_drvbpf != NULL)) { 2674 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2675 2676 tap->wt_flags = 0; 2677 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2678 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2679 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2680 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2681 2682 /* XXX: set tap->wt_rate? */ 2683 2684 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2685 } 2686 2687 /* non-qos data frames */ 2688 tid = R92C_TXDW1_QSEL_BE; 2689 if ((hasqos = ieee80211_has_qos(wh))) { 2690 /* data frames in 11n mode */ 2691 struct ieee80211_qosframe *qwh = (void *)wh; 2692 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2693 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2694 tid = R92C_TXDW1_QSEL_MGNT; 2695 } 2696 2697 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2698 padsize = 8; 2699 else 2700 padsize = 0; 2701 2702 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2703 padsize = 0; 2704 2705 /* Fill Tx descriptor. */ 2706 txd = (struct r92c_tx_desc_usb *)data->buf; 2707 memset(txd, 0, txd_len + padsize); 2708 2709 txd->txdw0 |= htole32( 2710 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2711 SM(R92C_TXDW0_OFFSET, txd_len)); 2712 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2713 txd->txdw0 |= htole32( 2714 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2715 } 2716 2717 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2718 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2719 2720 /* fix pad field */ 2721 if (padsize > 0) { 2722 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2723 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2724 } 2725 2726 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2727 type == IEEE80211_FC0_TYPE_DATA) { 2728 if (ic->ic_curmode == IEEE80211_MODE_11B) 2729 raid = R92C_RAID_11B; 2730 else 2731 raid = R92C_RAID_11BG; 2732 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2733 tid, raid, 0, 0); 2734 2735 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2736 txd->txdw1 |= htole32( 2737 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2738 SM(R92C_TXDW1_QSEL, tid) | 2739 SM(R92C_TXDW1_RAID, raid) | 2740 R92C_TXDW1_AGGBK); 2741 } else 2742 txd->txdw1 |= htole32( 2743 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2744 SM(R92C_TXDW1_QSEL, tid) | 2745 SM(R92C_TXDW1_RAID, raid) | 2746 R92C_TXDW1_AGGBK); 2747 2748 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2749 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2750 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2751 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2752 2753 if (hasqos) { 2754 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2755 } 2756 2757 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2758 /* for 11g */ 2759 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2760 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2761 R92C_TXDW4_HWRTSEN); 2762 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2763 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2764 R92C_TXDW4_HWRTSEN); 2765 } 2766 } 2767 /* Send RTS at OFDM24. */ 2768 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2769 txd->txdw5 |= htole32(0x0001ff00); 2770 /* Send data at OFDM54. */ 2771 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2772 txd->txdw5 |= htole32(0x13 & 0x3f); 2773 else 2774 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2775 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2776 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2777 txd->txdw1 |= htole32( 2778 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2779 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2780 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2781 2782 /* Force CCK1. */ 2783 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2784 /* Use 1Mbps */ 2785 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2786 } else { 2787 /* broadcast or multicast packets */ 2788 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2789 txd->txdw1 |= htole32( 2790 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2791 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2792 2793 /* Force CCK1. */ 2794 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2795 /* Use 1Mbps */ 2796 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2797 } 2798 /* Set sequence number */ 2799 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2800 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2801 txd->txdseq |= htole16(seq); 2802 2803 if (!hasqos) { 2804 /* Use HW sequence numbering for non-QoS frames. */ 2805 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2806 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2807 } 2808 } else { 2809 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2810 R92E_HWSEQ_SHIFT); 2811 if (!hasqos) { 2812 /* Use HW sequence numbering for non-QoS frames. */ 2813 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2814 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2815 } 2816 } 2817 2818 /* Compute Tx descriptor checksum. */ 2819 sum = 0; 2820 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2821 sum ^= ((uint16_t *)txd)[i]; 2822 txd->txdsum = sum; /* NB: already little endian. */ 2823 2824 xferlen = txd_len + m->m_pkthdr.len + padsize; 2825 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2826 2827 s = splnet(); 2828 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2829 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2830 urtwn_txeof); 2831 error = usbd_transfer(data->xfer); 2832 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2833 error != USBD_IN_PROGRESS)) { 2834 splx(s); 2835 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2836 return error; 2837 } 2838 splx(s); 2839 return 0; 2840 } 2841 2842 struct urtwn_tx_data * 2843 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2844 { 2845 struct urtwn_tx_data *data = NULL; 2846 2847 mutex_enter(&sc->sc_tx_mtx); 2848 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2849 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2850 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2851 } 2852 mutex_exit(&sc->sc_tx_mtx); 2853 2854 return data; 2855 } 2856 2857 static void 2858 urtwn_start(struct ifnet *ifp) 2859 { 2860 struct urtwn_softc *sc = ifp->if_softc; 2861 struct ieee80211com *ic = &sc->sc_ic; 2862 struct urtwn_tx_data *data; 2863 struct ether_header *eh; 2864 struct ieee80211_node *ni; 2865 struct mbuf *m; 2866 2867 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2868 2869 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2870 return; 2871 2872 data = NULL; 2873 for (;;) { 2874 /* Send pending management frames first. */ 2875 IF_POLL(&ic->ic_mgtq, m); 2876 if (m != NULL) { 2877 /* Use AC_VO for management frames. */ 2878 2879 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2880 2881 if (data == NULL) { 2882 ifp->if_flags |= IFF_OACTIVE; 2883 DPRINTFN(DBG_TX, "empty tx_free_list", 2884 0, 0, 0, 0); 2885 return; 2886 } 2887 IF_DEQUEUE(&ic->ic_mgtq, m); 2888 ni = M_GETCTX(m, struct ieee80211_node *); 2889 M_CLEARCTX(m); 2890 goto sendit; 2891 } 2892 if (ic->ic_state != IEEE80211_S_RUN) 2893 break; 2894 2895 /* Encapsulate and send data frames. */ 2896 IFQ_POLL(&ifp->if_snd, m); 2897 if (m == NULL) 2898 break; 2899 2900 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2901 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2902 uint8_t qid = WME_AC_BE; 2903 if (ieee80211_has_qos(wh)) { 2904 /* data frames in 11n mode */ 2905 struct ieee80211_qosframe *qwh = (void *)wh; 2906 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2907 qid = TID_TO_WME_AC(tid); 2908 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2909 qid = WME_AC_VO; 2910 } 2911 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2912 2913 if (data == NULL) { 2914 ifp->if_flags |= IFF_OACTIVE; 2915 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2916 return; 2917 } 2918 IFQ_DEQUEUE(&ifp->if_snd, m); 2919 2920 if (m->m_len < (int)sizeof(*eh) && 2921 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2922 device_printf(sc->sc_dev, "m_pullup failed\n"); 2923 if_statinc(ifp, if_oerrors); 2924 urtwn_put_tx_data(sc, data); 2925 m_freem(m); 2926 continue; 2927 } 2928 eh = mtod(m, struct ether_header *); 2929 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2930 if (ni == NULL) { 2931 device_printf(sc->sc_dev, 2932 "unable to find transmit node\n"); 2933 if_statinc(ifp, if_oerrors); 2934 urtwn_put_tx_data(sc, data); 2935 m_freem(m); 2936 continue; 2937 } 2938 2939 bpf_mtap(ifp, m, BPF_D_OUT); 2940 2941 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2942 ieee80211_free_node(ni); 2943 device_printf(sc->sc_dev, 2944 "unable to encapsulate packet\n"); 2945 if_statinc(ifp, if_oerrors); 2946 urtwn_put_tx_data(sc, data); 2947 m_freem(m); 2948 continue; 2949 } 2950 sendit: 2951 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2952 2953 if (urtwn_tx(sc, m, ni, data) != 0) { 2954 m_freem(m); 2955 ieee80211_free_node(ni); 2956 device_printf(sc->sc_dev, 2957 "unable to transmit packet\n"); 2958 if_statinc(ifp, if_oerrors); 2959 continue; 2960 } 2961 m_freem(m); 2962 ieee80211_free_node(ni); 2963 sc->tx_timer = 5; 2964 ifp->if_timer = 1; 2965 } 2966 } 2967 2968 static void 2969 urtwn_watchdog(struct ifnet *ifp) 2970 { 2971 struct urtwn_softc *sc = ifp->if_softc; 2972 2973 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2974 2975 ifp->if_timer = 0; 2976 2977 if (sc->tx_timer > 0) { 2978 if (--sc->tx_timer == 0) { 2979 device_printf(sc->sc_dev, "device timeout\n"); 2980 /* urtwn_init(ifp); XXX needs a process context! */ 2981 if_statinc(ifp, if_oerrors); 2982 return; 2983 } 2984 ifp->if_timer = 1; 2985 } 2986 ieee80211_watchdog(&sc->sc_ic); 2987 } 2988 2989 static int 2990 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2991 { 2992 struct urtwn_softc *sc = ifp->if_softc; 2993 struct ieee80211com *ic = &sc->sc_ic; 2994 int s, error = 0; 2995 2996 URTWNHIST_FUNC(); 2997 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2998 0, 0); 2999 3000 s = splnet(); 3001 3002 switch (cmd) { 3003 case SIOCSIFFLAGS: 3004 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3005 break; 3006 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3007 case IFF_UP | IFF_RUNNING: 3008 break; 3009 case IFF_UP: 3010 urtwn_init(ifp); 3011 break; 3012 case IFF_RUNNING: 3013 urtwn_stop(ifp, 1); 3014 break; 3015 case 0: 3016 break; 3017 } 3018 break; 3019 3020 case SIOCADDMULTI: 3021 case SIOCDELMULTI: 3022 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3023 /* setup multicast filter, etc */ 3024 error = 0; 3025 } 3026 break; 3027 3028 case SIOCS80211CHANNEL: 3029 /* 3030 * This allows for fast channel switching in monitor mode 3031 * (used by kismet). In IBSS mode, we must explicitly reset 3032 * the interface to generate a new beacon frame. 3033 */ 3034 error = ieee80211_ioctl(ic, cmd, data); 3035 if (error == ENETRESET && 3036 ic->ic_opmode == IEEE80211_M_MONITOR) { 3037 urtwn_set_chan(sc, ic->ic_curchan, 3038 IEEE80211_HTINFO_2NDCHAN_NONE); 3039 error = 0; 3040 } 3041 break; 3042 3043 default: 3044 error = ieee80211_ioctl(ic, cmd, data); 3045 break; 3046 } 3047 if (error == ENETRESET) { 3048 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3049 (IFF_UP | IFF_RUNNING) && 3050 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3051 urtwn_init(ifp); 3052 } 3053 error = 0; 3054 } 3055 3056 splx(s); 3057 3058 return error; 3059 } 3060 3061 static __inline int 3062 urtwn_power_on(struct urtwn_softc *sc) 3063 { 3064 3065 return sc->sc_power_on(sc); 3066 } 3067 3068 static int 3069 urtwn_r92c_power_on(struct urtwn_softc *sc) 3070 { 3071 uint32_t reg; 3072 int ntries; 3073 3074 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3075 3076 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3077 3078 /* Wait for autoload done bit. */ 3079 for (ntries = 0; ntries < 1000; ntries++) { 3080 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3081 break; 3082 DELAY(5); 3083 } 3084 if (ntries == 1000) { 3085 aprint_error_dev(sc->sc_dev, 3086 "timeout waiting for chip autoload\n"); 3087 return ETIMEDOUT; 3088 } 3089 3090 /* Unlock ISO/CLK/Power control register. */ 3091 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3092 DELAY(5); 3093 /* Move SPS into PWM mode. */ 3094 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3095 DELAY(5); 3096 3097 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3098 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3099 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3100 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3101 DELAY(100); 3102 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3103 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3104 ~R92C_SYS_ISO_CTRL_MD2PP); 3105 } 3106 3107 /* Auto enable WLAN. */ 3108 urtwn_write_2(sc, R92C_APS_FSMCO, 3109 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3110 for (ntries = 0; ntries < 1000; ntries++) { 3111 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3112 R92C_APS_FSMCO_APFM_ONMAC)) 3113 break; 3114 DELAY(100); 3115 } 3116 if (ntries == 1000) { 3117 aprint_error_dev(sc->sc_dev, 3118 "timeout waiting for MAC auto ON\n"); 3119 return ETIMEDOUT; 3120 } 3121 3122 /* Enable radio, GPIO and LED functions. */ 3123 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3124 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3125 urtwn_write_2(sc, R92C_APS_FSMCO, 3126 R92C_APS_FSMCO_AFSM_HSUS | 3127 R92C_APS_FSMCO_PDN_EN | 3128 R92C_APS_FSMCO_PFM_ALDN); 3129 3130 /* Release RF digital isolation. */ 3131 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3132 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3133 3134 /* Initialize MAC. */ 3135 urtwn_write_1(sc, R92C_APSD_CTRL, 3136 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3137 for (ntries = 0; ntries < 200; ntries++) { 3138 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3139 R92C_APSD_CTRL_OFF_STATUS)) 3140 break; 3141 DELAY(5); 3142 } 3143 if (ntries == 200) { 3144 aprint_error_dev(sc->sc_dev, 3145 "timeout waiting for MAC initialization\n"); 3146 return ETIMEDOUT; 3147 } 3148 3149 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3150 reg = urtwn_read_2(sc, R92C_CR); 3151 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3152 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3153 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3154 R92C_CR_ENSEC; 3155 urtwn_write_2(sc, R92C_CR, reg); 3156 3157 urtwn_write_1(sc, 0xfe10, 0x19); 3158 3159 urtwn_delay_ms(sc, 1); 3160 3161 return 0; 3162 } 3163 3164 static int 3165 urtwn_r92e_power_on(struct urtwn_softc *sc) 3166 { 3167 uint32_t reg; 3168 uint32_t val; 3169 int ntries; 3170 3171 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3172 3173 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3174 3175 /* Enable radio, GPIO and LED functions. */ 3176 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3177 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3178 urtwn_write_2(sc, R92C_APS_FSMCO, 3179 R92C_APS_FSMCO_AFSM_HSUS | 3180 R92C_APS_FSMCO_PDN_EN | 3181 R92C_APS_FSMCO_PFM_ALDN); 3182 3183 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3184 /* LDO. */ 3185 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3186 } 3187 else { 3188 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3189 R92C_SYS_SWR_CTRL2) & 0xffff); 3190 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3191 } 3192 3193 for (ntries = 0; ntries < 2; ntries++) { 3194 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3195 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3196 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3197 R92C_AFE_CTRL4)); 3198 } 3199 3200 /* Reset BB. */ 3201 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3202 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3203 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3204 3205 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3206 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3207 3208 /* Disable HWPDN. */ 3209 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3210 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3211 3212 /* Disable WL suspend. */ 3213 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3214 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3215 R92C_APS_FSMCO_AFSM_HSUS)); 3216 3217 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3218 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3219 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3220 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3221 for (ntries = 0; ntries < 10000; ntries++) { 3222 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3223 R92C_APS_FSMCO_APFM_ONMAC; 3224 if (val == 0x0) 3225 break; 3226 DELAY(10); 3227 } 3228 if (ntries == 10000) { 3229 aprint_error_dev(sc->sc_dev, 3230 "timeout waiting for chip power up\n"); 3231 return ETIMEDOUT; 3232 } 3233 3234 urtwn_write_2(sc, R92C_CR, 0x00); 3235 reg = urtwn_read_2(sc, R92C_CR); 3236 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3237 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3238 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3239 urtwn_write_2(sc, R92C_CR, reg); 3240 3241 return 0; 3242 } 3243 3244 static int 3245 urtwn_r88e_power_on(struct urtwn_softc *sc) 3246 { 3247 uint32_t reg; 3248 uint8_t val; 3249 int ntries; 3250 3251 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3252 3253 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3254 3255 /* Wait for power ready bit. */ 3256 for (ntries = 0; ntries < 5000; ntries++) { 3257 val = urtwn_read_1(sc, 0x6) & 0x2; 3258 if (val == 0x2) 3259 break; 3260 DELAY(10); 3261 } 3262 if (ntries == 5000) { 3263 aprint_error_dev(sc->sc_dev, 3264 "timeout waiting for chip power up\n"); 3265 return ETIMEDOUT; 3266 } 3267 3268 /* Reset BB. */ 3269 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3270 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3271 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3272 3273 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3274 3275 /* Disable HWPDN. */ 3276 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3277 3278 /* Disable WL suspend. */ 3279 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3280 3281 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3282 for (ntries = 0; ntries < 5000; ntries++) { 3283 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3284 break; 3285 DELAY(10); 3286 } 3287 if (ntries == 5000) 3288 return ETIMEDOUT; 3289 3290 /* Enable LDO normal mode. */ 3291 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3292 3293 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3294 urtwn_write_2(sc, R92C_CR, 0); 3295 reg = urtwn_read_2(sc, R92C_CR); 3296 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3297 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3298 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3299 urtwn_write_2(sc, R92C_CR, reg); 3300 3301 return 0; 3302 } 3303 3304 static int __noinline 3305 urtwn_llt_init(struct urtwn_softc *sc) 3306 { 3307 size_t i, page_count, pktbuf_count; 3308 uint32_t val; 3309 int error; 3310 3311 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3312 3313 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3314 3315 if (sc->chip & URTWN_CHIP_88E) 3316 page_count = R88E_TX_PAGE_COUNT; 3317 else if (sc->chip & URTWN_CHIP_92EU) 3318 page_count = R92E_TX_PAGE_COUNT; 3319 else 3320 page_count = R92C_TX_PAGE_COUNT; 3321 if (sc->chip & URTWN_CHIP_88E) 3322 pktbuf_count = R88E_TXPKTBUF_COUNT; 3323 else if (sc->chip & URTWN_CHIP_92EU) 3324 pktbuf_count = R88E_TXPKTBUF_COUNT; 3325 else 3326 pktbuf_count = R92C_TXPKTBUF_COUNT; 3327 3328 if (sc->chip & URTWN_CHIP_92EU) { 3329 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3330 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3331 DELAY(100); 3332 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3333 if (val & R92E_AUTO_LLT_EN) 3334 return EIO; 3335 return 0; 3336 } 3337 3338 /* Reserve pages [0; page_count]. */ 3339 for (i = 0; i < page_count; i++) { 3340 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3341 return error; 3342 } 3343 /* NB: 0xff indicates end-of-list. */ 3344 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3345 return error; 3346 /* 3347 * Use pages [page_count + 1; pktbuf_count - 1] 3348 * as ring buffer. 3349 */ 3350 for (++i; i < pktbuf_count - 1; i++) { 3351 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3352 return error; 3353 } 3354 /* Make the last page point to the beginning of the ring buffer. */ 3355 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3356 return error; 3357 } 3358 3359 static void 3360 urtwn_fw_reset(struct urtwn_softc *sc) 3361 { 3362 uint16_t reg; 3363 int ntries; 3364 3365 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3366 3367 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3368 3369 /* Tell 8051 to reset itself. */ 3370 mutex_enter(&sc->sc_fwcmd_mtx); 3371 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3372 sc->fwcur = 0; 3373 mutex_exit(&sc->sc_fwcmd_mtx); 3374 3375 /* Wait until 8051 resets by itself. */ 3376 for (ntries = 0; ntries < 100; ntries++) { 3377 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3378 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3379 return; 3380 DELAY(50); 3381 } 3382 /* Force 8051 reset. */ 3383 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3384 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3385 } 3386 3387 static void 3388 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3389 { 3390 uint16_t reg; 3391 3392 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3393 3394 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3395 3396 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3397 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3398 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3399 } 3400 DELAY(50); 3401 3402 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3403 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3404 DELAY(50); 3405 3406 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3407 DELAY(50); 3408 3409 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3410 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3411 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3412 } 3413 DELAY(50); 3414 3415 mutex_enter(&sc->sc_fwcmd_mtx); 3416 /* Init firmware commands ring. */ 3417 sc->fwcur = 0; 3418 mutex_exit(&sc->sc_fwcmd_mtx); 3419 3420 } 3421 3422 static int 3423 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3424 { 3425 uint32_t reg; 3426 int off, mlen, error = 0; 3427 3428 URTWNHIST_FUNC(); 3429 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3430 page, (uintptr_t)buf, len, 0); 3431 3432 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3433 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3434 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3435 3436 off = R92C_FW_START_ADDR; 3437 while (len > 0) { 3438 if (len > 196) 3439 mlen = 196; 3440 else if (len > 4) 3441 mlen = 4; 3442 else 3443 mlen = 1; 3444 error = urtwn_write_region(sc, off, buf, mlen); 3445 if (error != 0) 3446 break; 3447 off += mlen; 3448 buf += mlen; 3449 len -= mlen; 3450 } 3451 return error; 3452 } 3453 3454 static int __noinline 3455 urtwn_load_firmware(struct urtwn_softc *sc) 3456 { 3457 firmware_handle_t fwh; 3458 const struct r92c_fw_hdr *hdr; 3459 const char *name; 3460 u_char *fw, *ptr; 3461 size_t len; 3462 uint32_t reg; 3463 int mlen, ntries, page, error; 3464 3465 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3466 3467 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3468 3469 /* Read firmware image from the filesystem. */ 3470 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3471 name = "rtl8188eufw.bin"; 3472 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3473 name = "rtl8192eefw.bin"; 3474 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3475 URTWN_CHIP_UMC_A_CUT) 3476 name = "rtl8192cfwU.bin"; 3477 else 3478 name = "rtl8192cfw.bin"; 3479 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3480 aprint_error_dev(sc->sc_dev, 3481 "failed load firmware of file %s (error %d)\n", name, 3482 error); 3483 return error; 3484 } 3485 const size_t fwlen = len = firmware_get_size(fwh); 3486 fw = firmware_malloc(len); 3487 if (fw == NULL) { 3488 aprint_error_dev(sc->sc_dev, 3489 "failed to allocate firmware memory\n"); 3490 firmware_close(fwh); 3491 return ENOMEM; 3492 } 3493 error = firmware_read(fwh, 0, fw, len); 3494 firmware_close(fwh); 3495 if (error != 0) { 3496 aprint_error_dev(sc->sc_dev, 3497 "failed to read firmware (error %d)\n", error); 3498 firmware_free(fw, fwlen); 3499 return error; 3500 } 3501 3502 len = fwlen; 3503 ptr = fw; 3504 hdr = (const struct r92c_fw_hdr *)ptr; 3505 /* Check if there is a valid FW header and skip it. */ 3506 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3507 (le16toh(hdr->signature) >> 4) == 0x88e || 3508 (le16toh(hdr->signature) >> 4) == 0x92e || 3509 (le16toh(hdr->signature) >> 4) == 0x92c) { 3510 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3511 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3512 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3513 hdr->month, hdr->date, hdr->hour, hdr->minute); 3514 ptr += sizeof(*hdr); 3515 len -= sizeof(*hdr); 3516 } 3517 3518 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3519 /* Reset MCU ready status */ 3520 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3521 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3522 ISSET(sc->chip, URTWN_CHIP_92EU)) 3523 urtwn_r88e_fw_reset(sc); 3524 else 3525 urtwn_fw_reset(sc); 3526 } 3527 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3528 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3529 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3530 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3531 R92C_SYS_FUNC_EN_CPUEN); 3532 } 3533 3534 /* download enabled */ 3535 urtwn_write_1(sc, R92C_MCUFWDL, 3536 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3537 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3538 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3539 3540 /* Reset the FWDL checksum. */ 3541 urtwn_write_1(sc, R92C_MCUFWDL, 3542 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3543 3544 DELAY(50); 3545 /* download firmware */ 3546 for (page = 0; len > 0; page++) { 3547 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3548 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3549 if (error != 0) { 3550 aprint_error_dev(sc->sc_dev, 3551 "could not load firmware page %d\n", page); 3552 goto fail; 3553 } 3554 ptr += mlen; 3555 len -= mlen; 3556 } 3557 3558 /* download disable */ 3559 urtwn_write_1(sc, R92C_MCUFWDL, 3560 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3561 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3562 3563 /* Wait for checksum report. */ 3564 for (ntries = 0; ntries < 1000; ntries++) { 3565 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3566 break; 3567 DELAY(5); 3568 } 3569 if (ntries == 1000) { 3570 aprint_error_dev(sc->sc_dev, 3571 "timeout waiting for checksum report\n"); 3572 error = ETIMEDOUT; 3573 goto fail; 3574 } 3575 3576 /* Wait for firmware readiness. */ 3577 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3578 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3579 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3580 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3581 ISSET(sc->chip, URTWN_CHIP_92EU)) 3582 urtwn_r88e_fw_reset(sc); 3583 for (ntries = 0; ntries < 6000; ntries++) { 3584 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3585 break; 3586 DELAY(5); 3587 } 3588 if (ntries == 6000) { 3589 aprint_error_dev(sc->sc_dev, 3590 "timeout waiting for firmware readiness\n"); 3591 error = ETIMEDOUT; 3592 goto fail; 3593 } 3594 fail: 3595 firmware_free(fw, fwlen); 3596 return error; 3597 } 3598 3599 static __inline int 3600 urtwn_dma_init(struct urtwn_softc *sc) 3601 { 3602 3603 return sc->sc_dma_init(sc); 3604 } 3605 3606 static int 3607 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3608 { 3609 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3610 uint32_t reg; 3611 int error; 3612 3613 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3614 3615 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3616 3617 /* Initialize LLT table. */ 3618 error = urtwn_llt_init(sc); 3619 if (error != 0) 3620 return error; 3621 3622 /* Get Tx queues to USB endpoints mapping. */ 3623 hashq = hasnq = haslq = 0; 3624 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3625 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3626 if (MS(reg, R92C_USB_EP_HQ) != 0) 3627 hashq = 1; 3628 if (MS(reg, R92C_USB_EP_NQ) != 0) 3629 hasnq = 1; 3630 if (MS(reg, R92C_USB_EP_LQ) != 0) 3631 haslq = 1; 3632 nqueues = hashq + hasnq + haslq; 3633 if (nqueues == 0) 3634 return EIO; 3635 /* Get the number of pages for each queue. */ 3636 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3637 /* The remaining pages are assigned to the high priority queue. */ 3638 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3639 3640 /* Set number of pages for normal priority queue. */ 3641 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3642 urtwn_write_4(sc, R92C_RQPN, 3643 /* Set number of pages for public queue. */ 3644 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3645 /* Set number of pages for high priority queue. */ 3646 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3647 /* Set number of pages for low priority queue. */ 3648 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3649 /* Load values. */ 3650 R92C_RQPN_LD); 3651 3652 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3653 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3654 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3655 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3656 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3657 3658 /* Set queue to USB pipe mapping. */ 3659 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3660 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3661 if (nqueues == 1) { 3662 if (hashq) { 3663 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3664 } else if (hasnq) { 3665 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3666 } else { 3667 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3668 } 3669 } else if (nqueues == 2) { 3670 /* All 2-endpoints configs have a high priority queue. */ 3671 if (!hashq) { 3672 return EIO; 3673 } 3674 if (hasnq) { 3675 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3676 } else { 3677 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3678 } 3679 } else { 3680 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3681 } 3682 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3683 3684 /* Set Tx/Rx transfer page boundary. */ 3685 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3686 3687 /* Set Tx/Rx transfer page size. */ 3688 urtwn_write_1(sc, R92C_PBP, 3689 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3690 return 0; 3691 } 3692 3693 static int 3694 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3695 { 3696 usb_interface_descriptor_t *id; 3697 uint32_t reg; 3698 int nqueues; 3699 int error; 3700 3701 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3702 3703 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3704 3705 /* Initialize LLT table. */ 3706 error = urtwn_llt_init(sc); 3707 if (error != 0) 3708 return error; 3709 3710 /* Get Tx queues to USB endpoints mapping. */ 3711 id = usbd_get_interface_descriptor(sc->sc_iface); 3712 nqueues = id->bNumEndpoints - 1; 3713 if (nqueues == 0) 3714 return EIO; 3715 3716 /* Set number of pages for normal priority queue. */ 3717 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3718 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3719 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3720 3721 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3722 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3723 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3724 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3725 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3726 3727 /* Set queue to USB pipe mapping. */ 3728 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3729 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3730 if (nqueues == 1) 3731 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3732 else if (nqueues == 2) 3733 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3734 else 3735 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3736 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3737 3738 /* Set Tx/Rx transfer page boundary. */ 3739 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3740 3741 /* Set Tx/Rx transfer page size. */ 3742 urtwn_write_1(sc, R92C_PBP, 3743 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3744 3745 return 0; 3746 } 3747 3748 static void __noinline 3749 urtwn_mac_init(struct urtwn_softc *sc) 3750 { 3751 size_t i; 3752 3753 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3754 3755 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3756 3757 /* Write MAC initialization values. */ 3758 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3759 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3760 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3761 rtl8188eu_mac[i].val); 3762 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3763 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3764 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3765 rtl8192eu_mac[i].val); 3766 } else { 3767 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3768 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3769 rtl8192cu_mac[i].val); 3770 } 3771 } 3772 3773 static void __noinline 3774 urtwn_bb_init(struct urtwn_softc *sc) 3775 { 3776 const struct rtwn_bb_prog *prog; 3777 uint32_t reg; 3778 uint8_t crystalcap; 3779 size_t i; 3780 3781 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3782 3783 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3784 3785 /* Enable BB and RF. */ 3786 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3787 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3788 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3789 R92C_SYS_FUNC_EN_DIO_RF); 3790 3791 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3792 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3793 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3794 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3795 } 3796 3797 urtwn_write_1(sc, R92C_RF_CTRL, 3798 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3799 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3800 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3801 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3802 3803 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3804 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3805 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3806 urtwn_write_1(sc, 0x15, 0xe9); 3807 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3808 } 3809 3810 /* Select BB programming based on board type. */ 3811 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3812 prog = &rtl8188eu_bb_prog; 3813 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3814 prog = &rtl8192eu_bb_prog; 3815 else if (!(sc->chip & URTWN_CHIP_92C)) { 3816 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3817 prog = &rtl8188ce_bb_prog; 3818 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3819 prog = &rtl8188ru_bb_prog; 3820 } else { 3821 prog = &rtl8188cu_bb_prog; 3822 } 3823 } else { 3824 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3825 prog = &rtl8192ce_bb_prog; 3826 } else { 3827 prog = &rtl8192cu_bb_prog; 3828 } 3829 } 3830 /* Write BB initialization values. */ 3831 for (i = 0; i < prog->count; i++) { 3832 /* additional delay depend on registers */ 3833 switch (prog->regs[i]) { 3834 case 0xfe: 3835 urtwn_delay_ms(sc, 50); 3836 break; 3837 case 0xfd: 3838 urtwn_delay_ms(sc, 5); 3839 break; 3840 case 0xfc: 3841 urtwn_delay_ms(sc, 1); 3842 break; 3843 case 0xfb: 3844 DELAY(50); 3845 break; 3846 case 0xfa: 3847 DELAY(5); 3848 break; 3849 case 0xf9: 3850 DELAY(1); 3851 break; 3852 } 3853 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3854 DELAY(1); 3855 } 3856 3857 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3858 /* 8192C 1T only configuration. */ 3859 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3860 reg = (reg & ~0x00000003) | 0x2; 3861 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3862 3863 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3864 reg = (reg & ~0x00300033) | 0x00200022; 3865 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3866 3867 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3868 reg = (reg & ~0xff000000) | (0x45 << 24); 3869 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3870 3871 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3872 reg = (reg & ~0x000000ff) | 0x23; 3873 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3874 3875 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3876 reg = (reg & ~0x00000030) | (1 << 4); 3877 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3878 3879 reg = urtwn_bb_read(sc, 0xe74); 3880 reg = (reg & ~0x0c000000) | (2 << 26); 3881 urtwn_bb_write(sc, 0xe74, reg); 3882 reg = urtwn_bb_read(sc, 0xe78); 3883 reg = (reg & ~0x0c000000) | (2 << 26); 3884 urtwn_bb_write(sc, 0xe78, reg); 3885 reg = urtwn_bb_read(sc, 0xe7c); 3886 reg = (reg & ~0x0c000000) | (2 << 26); 3887 urtwn_bb_write(sc, 0xe7c, reg); 3888 reg = urtwn_bb_read(sc, 0xe80); 3889 reg = (reg & ~0x0c000000) | (2 << 26); 3890 urtwn_bb_write(sc, 0xe80, reg); 3891 reg = urtwn_bb_read(sc, 0xe88); 3892 reg = (reg & ~0x0c000000) | (2 << 26); 3893 urtwn_bb_write(sc, 0xe88, reg); 3894 } 3895 3896 /* Write AGC values. */ 3897 for (i = 0; i < prog->agccount; i++) { 3898 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3899 DELAY(1); 3900 } 3901 3902 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3903 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3904 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3905 DELAY(1); 3906 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3907 DELAY(1); 3908 } 3909 3910 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3911 crystalcap = sc->r88e_rom[0xb9]; 3912 if (crystalcap == 0x00) 3913 crystalcap = 0x20; 3914 crystalcap &= 0x3f; 3915 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3916 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3917 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3918 crystalcap | crystalcap << 6)); 3919 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3920 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3921 crystalcap = sc->r88e_rom[0xb9]; 3922 if (crystalcap == 0xff) 3923 crystalcap = 0x20; 3924 crystalcap &= 0x3f; 3925 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3926 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3927 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3928 crystalcap | crystalcap << 6)); 3929 } else { 3930 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3931 R92C_HSSI_PARAM2_CCK_HIPWR) { 3932 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3933 } 3934 } 3935 } 3936 3937 static void __noinline 3938 urtwn_rf_init(struct urtwn_softc *sc) 3939 { 3940 const struct rtwn_rf_prog *prog; 3941 uint32_t reg, mask, saved; 3942 size_t i, j, idx; 3943 3944 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3945 3946 /* Select RF programming based on board type. */ 3947 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3948 prog = rtl8188eu_rf_prog; 3949 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3950 prog = rtl8192eu_rf_prog; 3951 else if (!(sc->chip & URTWN_CHIP_92C)) { 3952 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3953 prog = rtl8188ce_rf_prog; 3954 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3955 prog = rtl8188ru_rf_prog; 3956 } else { 3957 prog = rtl8188cu_rf_prog; 3958 } 3959 } else { 3960 prog = rtl8192ce_rf_prog; 3961 } 3962 3963 for (i = 0; i < sc->nrxchains; i++) { 3964 /* Save RF_ENV control type. */ 3965 idx = i / 2; 3966 mask = 0xffffU << ((i % 2) * 16); 3967 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3968 3969 /* Set RF_ENV enable. */ 3970 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3971 reg |= 0x100000; 3972 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3973 DELAY(50); 3974 3975 /* Set RF_ENV output high. */ 3976 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3977 reg |= 0x10; 3978 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3979 DELAY(50); 3980 3981 /* Set address and data lengths of RF registers. */ 3982 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3983 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3984 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3985 DELAY(50); 3986 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3987 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3988 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3989 DELAY(50); 3990 3991 /* Write RF initialization values for this chain. */ 3992 for (j = 0; j < prog[i].count; j++) { 3993 if (prog[i].regs[j] >= 0xf9 && 3994 prog[i].regs[j] <= 0xfe) { 3995 /* 3996 * These are fake RF registers offsets that 3997 * indicate a delay is required. 3998 */ 3999 urtwn_delay_ms(sc, 50); 4000 continue; 4001 } 4002 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4003 DELAY(5); 4004 } 4005 4006 /* Restore RF_ENV control type. */ 4007 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4008 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4009 } 4010 4011 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4012 URTWN_CHIP_UMC_A_CUT) { 4013 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4014 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4015 } 4016 4017 /* Cache RF register CHNLBW. */ 4018 for (i = 0; i < 2; i++) { 4019 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4020 } 4021 } 4022 4023 static void __noinline 4024 urtwn_cam_init(struct urtwn_softc *sc) 4025 { 4026 uint32_t content, command; 4027 uint8_t idx; 4028 size_t i; 4029 4030 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4031 4032 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4033 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4034 return; 4035 4036 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4037 content = (idx & 3) 4038 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4039 | R92C_CAM_VALID; 4040 4041 command = R92C_CAMCMD_POLLING 4042 | R92C_CAMCMD_WRITE 4043 | R92C_CAM_CTL0(idx); 4044 4045 urtwn_write_4(sc, R92C_CAMWRITE, content); 4046 urtwn_write_4(sc, R92C_CAMCMD, command); 4047 } 4048 4049 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4050 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4051 if (i == 0) { 4052 content = (idx & 3) 4053 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4054 | R92C_CAM_VALID; 4055 } else { 4056 content = 0; 4057 } 4058 4059 command = R92C_CAMCMD_POLLING 4060 | R92C_CAMCMD_WRITE 4061 | R92C_CAM_CTL0(idx) 4062 | i; 4063 4064 urtwn_write_4(sc, R92C_CAMWRITE, content); 4065 urtwn_write_4(sc, R92C_CAMCMD, command); 4066 } 4067 } 4068 4069 /* Invalidate all CAM entries. */ 4070 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4071 } 4072 4073 static void __noinline 4074 urtwn_pa_bias_init(struct urtwn_softc *sc) 4075 { 4076 uint8_t reg; 4077 size_t i; 4078 4079 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4080 4081 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4082 4083 for (i = 0; i < sc->nrxchains; i++) { 4084 if (sc->pa_setting & (1U << i)) 4085 continue; 4086 4087 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4088 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4089 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4090 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4091 } 4092 if (!(sc->pa_setting & 0x10)) { 4093 reg = urtwn_read_1(sc, 0x16); 4094 reg = (reg & ~0xf0) | 0x90; 4095 urtwn_write_1(sc, 0x16, reg); 4096 } 4097 } 4098 4099 static void __noinline 4100 urtwn_rxfilter_init(struct urtwn_softc *sc) 4101 { 4102 4103 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4104 4105 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4106 4107 /* Initialize Rx filter. */ 4108 /* TODO: use better filter for monitor mode. */ 4109 urtwn_write_4(sc, R92C_RCR, 4110 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4111 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4112 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4113 /* Accept all multicast frames. */ 4114 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4115 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4116 /* Accept all management frames. */ 4117 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4118 /* Reject all control frames. */ 4119 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4120 /* Accept all data frames. */ 4121 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4122 } 4123 4124 static void __noinline 4125 urtwn_edca_init(struct urtwn_softc *sc) 4126 { 4127 4128 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4129 4130 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4131 4132 /* set spec SIFS (used in NAV) */ 4133 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4134 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4135 4136 /* set SIFS CCK/OFDM */ 4137 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4138 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4139 4140 /* TXOP */ 4141 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4142 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4143 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4144 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4145 } 4146 4147 static void 4148 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4149 uint16_t power[URTWN_RIDX_COUNT]) 4150 { 4151 uint32_t reg; 4152 4153 URTWNHIST_FUNC(); 4154 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4155 4156 /* Write per-CCK rate Tx power. */ 4157 if (chain == 0) { 4158 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4159 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4160 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4161 4162 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4163 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4164 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4165 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4166 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4167 } else { 4168 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4169 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4170 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4171 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4172 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4173 4174 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4175 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4176 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4177 } 4178 /* Write per-OFDM rate Tx power. */ 4179 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4180 SM(R92C_TXAGC_RATE06, power[ 4]) | 4181 SM(R92C_TXAGC_RATE09, power[ 5]) | 4182 SM(R92C_TXAGC_RATE12, power[ 6]) | 4183 SM(R92C_TXAGC_RATE18, power[ 7])); 4184 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4185 SM(R92C_TXAGC_RATE24, power[ 8]) | 4186 SM(R92C_TXAGC_RATE36, power[ 9]) | 4187 SM(R92C_TXAGC_RATE48, power[10]) | 4188 SM(R92C_TXAGC_RATE54, power[11])); 4189 /* Write per-MCS Tx power. */ 4190 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4191 SM(R92C_TXAGC_MCS00, power[12]) | 4192 SM(R92C_TXAGC_MCS01, power[13]) | 4193 SM(R92C_TXAGC_MCS02, power[14]) | 4194 SM(R92C_TXAGC_MCS03, power[15])); 4195 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4196 SM(R92C_TXAGC_MCS04, power[16]) | 4197 SM(R92C_TXAGC_MCS05, power[17]) | 4198 SM(R92C_TXAGC_MCS06, power[18]) | 4199 SM(R92C_TXAGC_MCS07, power[19])); 4200 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4201 SM(R92C_TXAGC_MCS08, power[20]) | 4202 SM(R92C_TXAGC_MCS09, power[21]) | 4203 SM(R92C_TXAGC_MCS10, power[22]) | 4204 SM(R92C_TXAGC_MCS11, power[23])); 4205 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4206 SM(R92C_TXAGC_MCS12, power[24]) | 4207 SM(R92C_TXAGC_MCS13, power[25]) | 4208 SM(R92C_TXAGC_MCS14, power[26]) | 4209 SM(R92C_TXAGC_MCS15, power[27])); 4210 } 4211 4212 static void 4213 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4214 uint16_t power[URTWN_RIDX_COUNT]) 4215 { 4216 struct r92c_rom *rom = &sc->rom; 4217 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4218 const struct rtwn_txpwr *base; 4219 int ridx, group; 4220 4221 URTWNHIST_FUNC(); 4222 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4223 4224 /* Determine channel group. */ 4225 if (chan <= 3) { 4226 group = 0; 4227 } else if (chan <= 9) { 4228 group = 1; 4229 } else { 4230 group = 2; 4231 } 4232 4233 /* Get original Tx power based on board type and RF chain. */ 4234 if (!(sc->chip & URTWN_CHIP_92C)) { 4235 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4236 base = &rtl8188ru_txagc[chain]; 4237 } else { 4238 base = &rtl8192cu_txagc[chain]; 4239 } 4240 } else { 4241 base = &rtl8192cu_txagc[chain]; 4242 } 4243 4244 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4245 if (sc->regulatory == 0) { 4246 for (ridx = 0; ridx <= 3; ridx++) { 4247 power[ridx] = base->pwr[0][ridx]; 4248 } 4249 } 4250 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4251 if (sc->regulatory == 3) { 4252 power[ridx] = base->pwr[0][ridx]; 4253 /* Apply vendor limits. */ 4254 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4255 maxpow = rom->ht40_max_pwr[group]; 4256 } else { 4257 maxpow = rom->ht20_max_pwr[group]; 4258 } 4259 maxpow = (maxpow >> (chain * 4)) & 0xf; 4260 if (power[ridx] > maxpow) { 4261 power[ridx] = maxpow; 4262 } 4263 } else if (sc->regulatory == 1) { 4264 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4265 power[ridx] = base->pwr[group][ridx]; 4266 } 4267 } else if (sc->regulatory != 2) { 4268 power[ridx] = base->pwr[0][ridx]; 4269 } 4270 } 4271 4272 /* Compute per-CCK rate Tx power. */ 4273 cckpow = rom->cck_tx_pwr[chain][group]; 4274 for (ridx = 0; ridx <= 3; ridx++) { 4275 power[ridx] += cckpow; 4276 if (power[ridx] > R92C_MAX_TX_PWR) { 4277 power[ridx] = R92C_MAX_TX_PWR; 4278 } 4279 } 4280 4281 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4282 if (sc->ntxchains > 1) { 4283 /* Apply reduction for 2 spatial streams. */ 4284 diff = rom->ht40_2s_tx_pwr_diff[group]; 4285 diff = (diff >> (chain * 4)) & 0xf; 4286 htpow = (htpow > diff) ? htpow - diff : 0; 4287 } 4288 4289 /* Compute per-OFDM rate Tx power. */ 4290 diff = rom->ofdm_tx_pwr_diff[group]; 4291 diff = (diff >> (chain * 4)) & 0xf; 4292 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4293 for (ridx = 4; ridx <= 11; ridx++) { 4294 power[ridx] += ofdmpow; 4295 if (power[ridx] > R92C_MAX_TX_PWR) { 4296 power[ridx] = R92C_MAX_TX_PWR; 4297 } 4298 } 4299 4300 /* Compute per-MCS Tx power. */ 4301 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4302 diff = rom->ht20_tx_pwr_diff[group]; 4303 diff = (diff >> (chain * 4)) & 0xf; 4304 htpow += diff; /* HT40->HT20 correction. */ 4305 } 4306 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4307 power[ridx] += htpow; 4308 if (power[ridx] > R92C_MAX_TX_PWR) { 4309 power[ridx] = R92C_MAX_TX_PWR; 4310 } 4311 } 4312 #ifdef URTWN_DEBUG 4313 if (urtwn_debug & DBG_RF) { 4314 /* Dump per-rate Tx power values. */ 4315 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4316 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4317 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4318 } 4319 #endif 4320 } 4321 4322 void 4323 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4324 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4325 { 4326 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4327 const struct rtwn_r88e_txpwr *base; 4328 int ridx, group; 4329 4330 URTWNHIST_FUNC(); 4331 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4332 4333 /* Determine channel group. */ 4334 if (chan <= 2) 4335 group = 0; 4336 else if (chan <= 5) 4337 group = 1; 4338 else if (chan <= 8) 4339 group = 2; 4340 else if (chan <= 11) 4341 group = 3; 4342 else if (chan <= 13) 4343 group = 4; 4344 else 4345 group = 5; 4346 4347 /* Get original Tx power based on board type and RF chain. */ 4348 base = &rtl8188eu_txagc[chain]; 4349 4350 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4351 if (sc->regulatory == 0) { 4352 for (ridx = 0; ridx <= 3; ridx++) 4353 power[ridx] = base->pwr[0][ridx]; 4354 } 4355 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4356 if (sc->regulatory == 3) 4357 power[ridx] = base->pwr[0][ridx]; 4358 else if (sc->regulatory == 1) { 4359 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4360 power[ridx] = base->pwr[group][ridx]; 4361 } else if (sc->regulatory != 2) 4362 power[ridx] = base->pwr[0][ridx]; 4363 } 4364 4365 /* Compute per-CCK rate Tx power. */ 4366 cckpow = sc->cck_tx_pwr[group]; 4367 for (ridx = 0; ridx <= 3; ridx++) { 4368 power[ridx] += cckpow; 4369 if (power[ridx] > R92C_MAX_TX_PWR) 4370 power[ridx] = R92C_MAX_TX_PWR; 4371 } 4372 4373 htpow = sc->ht40_tx_pwr[group]; 4374 4375 /* Compute per-OFDM rate Tx power. */ 4376 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4377 for (ridx = 4; ridx <= 11; ridx++) { 4378 power[ridx] += ofdmpow; 4379 if (power[ridx] > R92C_MAX_TX_PWR) 4380 power[ridx] = R92C_MAX_TX_PWR; 4381 } 4382 4383 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4384 for (ridx = 12; ridx <= 27; ridx++) { 4385 power[ridx] += bw20pow; 4386 if (power[ridx] > R92C_MAX_TX_PWR) 4387 power[ridx] = R92C_MAX_TX_PWR; 4388 } 4389 } 4390 4391 static void 4392 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4393 { 4394 uint16_t power[URTWN_RIDX_COUNT]; 4395 size_t i; 4396 4397 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4398 4399 for (i = 0; i < sc->ntxchains; i++) { 4400 /* Compute per-rate Tx power values. */ 4401 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4402 ISSET(sc->chip, URTWN_CHIP_92EU)) 4403 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4404 else 4405 urtwn_get_txpower(sc, i, chan, ht40m, power); 4406 /* Write per-rate Tx power values to hardware. */ 4407 urtwn_write_txpower(sc, i, power); 4408 } 4409 } 4410 4411 static void __noinline 4412 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4413 { 4414 struct ieee80211com *ic = &sc->sc_ic; 4415 u_int chan; 4416 size_t i; 4417 4418 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4419 4420 URTWNHIST_FUNC(); 4421 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4422 4423 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4424 4425 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4426 chan += 2; 4427 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4428 chan -= 2; 4429 } 4430 4431 /* Set Tx power for this new channel. */ 4432 urtwn_set_txpower(sc, chan, ht40m); 4433 4434 for (i = 0; i < sc->nrxchains; i++) { 4435 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4436 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4437 } 4438 4439 if (ht40m) { 4440 /* Is secondary channel below or above primary? */ 4441 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4442 uint32_t reg; 4443 4444 urtwn_write_1(sc, R92C_BWOPMODE, 4445 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4446 4447 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4448 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4449 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4450 4451 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4452 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4453 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4454 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4455 4456 /* Set CCK side band. */ 4457 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4458 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4459 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4460 4461 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4462 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4463 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4464 4465 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4466 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4467 ~R92C_FPGA0_ANAPARAM2_CBW20); 4468 4469 reg = urtwn_bb_read(sc, 0x818); 4470 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4471 urtwn_bb_write(sc, 0x818, reg); 4472 4473 /* Select 40MHz bandwidth. */ 4474 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4475 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4476 } else { 4477 urtwn_write_1(sc, R92C_BWOPMODE, 4478 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4479 4480 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4481 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4482 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4483 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4484 4485 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4486 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4487 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4488 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4489 R92C_FPGA0_ANAPARAM2_CBW20); 4490 } 4491 4492 /* Select 20MHz bandwidth. */ 4493 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4494 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4495 (ISSET(sc->chip, URTWN_CHIP_88E) || 4496 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4497 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4498 } 4499 } 4500 4501 static void __noinline 4502 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4503 { 4504 4505 URTWNHIST_FUNC(); 4506 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4507 4508 uint32_t addaBackup[16], iqkBackup[4], piMode; 4509 4510 #ifdef notyet 4511 uint32_t odfm0_agccore_regs[3]; 4512 uint32_t ant_regs[3]; 4513 uint32_t rf_regs[8]; 4514 #endif 4515 uint32_t reg0, reg1, reg2; 4516 int i, attempt; 4517 4518 #ifdef notyet 4519 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4520 R92E_STBC_SETTING + 2)); 4521 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4522 /* Save AGCCORE regs. */ 4523 for (i = 0; i < sc->nrxchains; i++) { 4524 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4525 R92C_OFDM0_AGCCORE1(i)); 4526 } 4527 #endif 4528 /* Save BB regs. */ 4529 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4530 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4531 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4532 4533 /* Save adda regs to be restored when finished. */ 4534 for (i = 0; i < __arraycount(addaReg); i++) 4535 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4536 /* Save mac regs. */ 4537 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4538 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4539 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4540 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4541 4542 #ifdef notyet 4543 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4544 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4545 4546 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4547 for (i = 0; i < sc->nrxchains; i++) 4548 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4549 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4550 #endif 4551 4552 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4553 R92C_HSSI_PARAM1_PI); 4554 if (piMode == 0) { 4555 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4556 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4557 R92C_HSSI_PARAM1_PI); 4558 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4559 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4560 R92C_HSSI_PARAM1_PI); 4561 } 4562 4563 attempt = 1; 4564 4565 next_attempt: 4566 4567 /* Set mac regs for calibration. */ 4568 for (i = 0; i < __arraycount(addaReg); i++) { 4569 urtwn_bb_write(sc, addaReg[i], 4570 addaReg[__arraycount(addaReg) - 1]); 4571 } 4572 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4573 R92C_CCK0_AFESETTING)); 4574 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4575 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4576 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4577 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4578 4579 if (sc->ntxchains > 1) 4580 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4581 4582 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4583 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4584 ~R92C_BCN_CTRL_EN_BCN)); 4585 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4586 ~R92C_BCN_CTRL_EN_BCN)); 4587 4588 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4589 ~R92C_GPIO_MUXCFG_ENBT)); 4590 4591 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4592 4593 if (sc->ntxchains > 1) 4594 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4595 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4596 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4597 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4598 4599 /* Restore BB regs. */ 4600 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4601 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4602 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4603 4604 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4605 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4606 if (sc->nrxchains > 1) 4607 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4608 4609 if (attempt-- > 0) 4610 goto next_attempt; 4611 4612 /* Restore mode. */ 4613 if (piMode == 0) { 4614 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4615 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4616 ~R92C_HSSI_PARAM1_PI); 4617 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4618 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4619 ~R92C_HSSI_PARAM1_PI); 4620 } 4621 4622 #ifdef notyet 4623 for (i = 0; i < sc->nrxchains; i++) { 4624 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4625 odfm0_agccore_regs[i]); 4626 } 4627 #endif 4628 4629 /* Restore adda regs. */ 4630 for (i = 0; i < __arraycount(addaReg); i++) 4631 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4632 /* Restore mac regs. */ 4633 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4634 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4635 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4636 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4637 4638 #ifdef notyet 4639 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4640 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4641 4642 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4643 for (i = 0; i < sc->nrxchains; i++) 4644 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4645 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4646 #endif 4647 } 4648 4649 static void 4650 urtwn_lc_calib(struct urtwn_softc *sc) 4651 { 4652 uint32_t rf_ac[2]; 4653 uint8_t txmode; 4654 size_t i; 4655 4656 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4657 4658 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4659 4660 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4661 if ((txmode & 0x70) != 0) { 4662 /* Disable all continuous Tx. */ 4663 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4664 4665 /* Set RF mode to standby mode. */ 4666 for (i = 0; i < sc->nrxchains; i++) { 4667 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4668 urtwn_rf_write(sc, i, R92C_RF_AC, 4669 RW(rf_ac[i], R92C_RF_AC_MODE, 4670 R92C_RF_AC_MODE_STANDBY)); 4671 } 4672 } else { 4673 /* Block all Tx queues. */ 4674 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4675 } 4676 /* Start calibration. */ 4677 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4678 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4679 4680 /* Give calibration the time to complete. */ 4681 urtwn_delay_ms(sc, 100); 4682 4683 /* Restore configuration. */ 4684 if ((txmode & 0x70) != 0) { 4685 /* Restore Tx mode. */ 4686 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4687 /* Restore RF mode. */ 4688 for (i = 0; i < sc->nrxchains; i++) { 4689 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4690 } 4691 } else { 4692 /* Unblock all Tx queues. */ 4693 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4694 } 4695 } 4696 4697 static void 4698 urtwn_temp_calib(struct urtwn_softc *sc) 4699 { 4700 int temp, t_meter_reg; 4701 4702 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4703 4704 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4705 4706 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4707 t_meter_reg = R92C_RF_T_METER; 4708 else 4709 t_meter_reg = R92E_RF_T_METER; 4710 4711 if (sc->thcal_state == 0) { 4712 /* Start measuring temperature. */ 4713 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4714 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4715 sc->thcal_state = 1; 4716 return; 4717 } 4718 sc->thcal_state = 0; 4719 4720 /* Read measured temperature. */ 4721 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4722 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4723 if (temp == 0) /* Read failed, skip. */ 4724 return; 4725 4726 /* 4727 * Redo LC calibration if temperature changed significantly since 4728 * last calibration. 4729 */ 4730 if (sc->thcal_lctemp == 0) { 4731 /* First LC calibration is performed in urtwn_init(). */ 4732 sc->thcal_lctemp = temp; 4733 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4734 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4735 sc->thcal_lctemp, temp, 0, 0); 4736 urtwn_lc_calib(sc); 4737 /* Record temperature of last LC calibration. */ 4738 sc->thcal_lctemp = temp; 4739 } 4740 } 4741 4742 static int 4743 urtwn_init(struct ifnet *ifp) 4744 { 4745 struct urtwn_softc *sc = ifp->if_softc; 4746 struct ieee80211com *ic = &sc->sc_ic; 4747 struct urtwn_rx_data *data; 4748 uint32_t reg; 4749 size_t i; 4750 int error; 4751 4752 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4753 4754 urtwn_stop(ifp, 0); 4755 4756 mutex_enter(&sc->sc_write_mtx); 4757 4758 mutex_enter(&sc->sc_task_mtx); 4759 /* Init host async commands ring. */ 4760 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4761 mutex_exit(&sc->sc_task_mtx); 4762 4763 mutex_enter(&sc->sc_fwcmd_mtx); 4764 /* Init firmware commands ring. */ 4765 sc->fwcur = 0; 4766 mutex_exit(&sc->sc_fwcmd_mtx); 4767 4768 /* Allocate Tx/Rx buffers. */ 4769 error = urtwn_alloc_rx_list(sc); 4770 if (error != 0) { 4771 aprint_error_dev(sc->sc_dev, 4772 "could not allocate Rx buffers\n"); 4773 goto fail; 4774 } 4775 error = urtwn_alloc_tx_list(sc); 4776 if (error != 0) { 4777 aprint_error_dev(sc->sc_dev, 4778 "could not allocate Tx buffers\n"); 4779 goto fail; 4780 } 4781 4782 /* Power on adapter. */ 4783 error = urtwn_power_on(sc); 4784 if (error != 0) 4785 goto fail; 4786 4787 /* Initialize DMA. */ 4788 error = urtwn_dma_init(sc); 4789 if (error != 0) 4790 goto fail; 4791 4792 /* Set info size in Rx descriptors (in 64-bit words). */ 4793 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4794 4795 /* Init interrupts. */ 4796 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4797 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4798 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4799 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4800 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4801 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4802 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4803 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4804 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4805 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4806 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4807 } 4808 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4809 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4810 } else { 4811 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4812 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4813 } 4814 4815 /* Set MAC address. */ 4816 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4817 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4818 4819 /* Set initial network type. */ 4820 reg = urtwn_read_4(sc, R92C_CR); 4821 switch (ic->ic_opmode) { 4822 case IEEE80211_M_STA: 4823 default: 4824 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4825 break; 4826 4827 case IEEE80211_M_IBSS: 4828 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4829 break; 4830 } 4831 urtwn_write_4(sc, R92C_CR, reg); 4832 4833 /* Set response rate */ 4834 reg = urtwn_read_4(sc, R92C_RRSR); 4835 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4836 urtwn_write_4(sc, R92C_RRSR, reg); 4837 4838 /* SIFS (used in NAV) */ 4839 urtwn_write_2(sc, R92C_SPEC_SIFS, 4840 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4841 4842 /* Set short/long retry limits. */ 4843 urtwn_write_2(sc, R92C_RL, 4844 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4845 4846 /* Initialize EDCA parameters. */ 4847 urtwn_edca_init(sc); 4848 4849 /* Setup rate fallback. */ 4850 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4851 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4852 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4853 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4854 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4855 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4856 } 4857 4858 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4859 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4860 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4861 /* Set ACK timeout. */ 4862 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4863 4864 /* Setup USB aggregation. */ 4865 /* Tx */ 4866 reg = urtwn_read_4(sc, R92C_TDECTRL); 4867 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4868 urtwn_write_4(sc, R92C_TDECTRL, reg); 4869 /* Rx */ 4870 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4871 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4872 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4873 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4874 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4875 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4876 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4877 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4878 ISSET(sc->chip, URTWN_CHIP_92EU)) 4879 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4880 else 4881 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4882 4883 /* Initialize beacon parameters. */ 4884 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4885 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4886 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4887 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4888 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4889 4890 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4891 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4892 /* Setup AMPDU aggregation. */ 4893 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4894 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4895 urtwn_write_2(sc, 0x4ca, 0x0708); 4896 4897 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4898 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4899 } 4900 4901 /* Load 8051 microcode. */ 4902 error = urtwn_load_firmware(sc); 4903 if (error != 0) 4904 goto fail; 4905 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4906 4907 /* Initialize MAC/BB/RF blocks. */ 4908 /* 4909 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4910 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4911 * XXX: This setting should be removed from rtl8192cu_mac[]. 4912 */ 4913 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4914 urtwn_rxfilter_init(sc); // reset R92C_RCR 4915 urtwn_bb_init(sc); 4916 urtwn_rf_init(sc); 4917 4918 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4919 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4920 urtwn_write_2(sc, R92C_CR, 4921 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4922 R92C_CR_MACRXEN); 4923 } 4924 4925 /* Turn CCK and OFDM blocks on. */ 4926 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4927 reg |= R92C_RFMOD_CCK_EN; 4928 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4929 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4930 reg |= R92C_RFMOD_OFDM_EN; 4931 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4932 4933 /* Clear per-station keys table. */ 4934 urtwn_cam_init(sc); 4935 4936 /* Enable hardware sequence numbering. */ 4937 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4938 4939 /* Perform LO and IQ calibrations. */ 4940 urtwn_iq_calib(sc, sc->iqk_inited); 4941 sc->iqk_inited = true; 4942 4943 /* Perform LC calibration. */ 4944 urtwn_lc_calib(sc); 4945 4946 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4947 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4948 /* Fix USB interference issue. */ 4949 urtwn_write_1(sc, 0xfe40, 0xe0); 4950 urtwn_write_1(sc, 0xfe41, 0x8d); 4951 urtwn_write_1(sc, 0xfe42, 0x80); 4952 urtwn_write_4(sc, 0x20c, 0xfd0320); 4953 4954 urtwn_pa_bias_init(sc); 4955 } 4956 4957 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4958 !(sc->chip & URTWN_CHIP_92EU)) { 4959 /* 1T1R */ 4960 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4961 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4962 } 4963 4964 /* Initialize GPIO setting. */ 4965 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4966 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4967 4968 /* Fix for lower temperature. */ 4969 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4970 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4971 urtwn_write_1(sc, 0x15, 0xe9); 4972 4973 /* Set default channel. */ 4974 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4975 4976 /* Queue Rx xfers. */ 4977 for (size_t j = 0; j < sc->rx_npipe; j++) { 4978 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4979 data = &sc->rx_data[j][i]; 4980 usbd_setup_xfer(data->xfer, data, data->buf, 4981 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4982 urtwn_rxeof); 4983 error = usbd_transfer(data->xfer); 4984 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4985 error != USBD_IN_PROGRESS)) 4986 goto fail; 4987 } 4988 } 4989 4990 /* We're ready to go. */ 4991 ifp->if_flags &= ~IFF_OACTIVE; 4992 ifp->if_flags |= IFF_RUNNING; 4993 sc->sc_running = true; 4994 4995 mutex_exit(&sc->sc_write_mtx); 4996 4997 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4998 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4999 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5000 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5001 urtwn_wait_async(sc); 5002 5003 return 0; 5004 5005 fail: 5006 mutex_exit(&sc->sc_write_mtx); 5007 5008 urtwn_stop(ifp, 1); 5009 return error; 5010 } 5011 5012 static void __noinline 5013 urtwn_stop(struct ifnet *ifp, int disable) 5014 { 5015 struct urtwn_softc *sc = ifp->if_softc; 5016 struct ieee80211com *ic = &sc->sc_ic; 5017 size_t i; 5018 int s; 5019 5020 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5021 5022 s = splusb(); 5023 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5024 urtwn_wait_async(sc); 5025 splx(s); 5026 5027 sc->tx_timer = 0; 5028 ifp->if_timer = 0; 5029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5030 5031 callout_stop(&sc->sc_scan_to); 5032 callout_stop(&sc->sc_calib_to); 5033 5034 /* Abort Tx. */ 5035 for (i = 0; i < sc->tx_npipe; i++) { 5036 if (sc->tx_pipe[i] != NULL) 5037 usbd_abort_pipe(sc->tx_pipe[i]); 5038 } 5039 5040 /* Stop Rx pipe. */ 5041 for (i = 0; i < sc->rx_npipe; i++) { 5042 if (sc->rx_pipe[i] != NULL) 5043 usbd_abort_pipe(sc->rx_pipe[i]); 5044 } 5045 5046 /* Free Tx/Rx buffers. */ 5047 urtwn_free_tx_list(sc); 5048 urtwn_free_rx_list(sc); 5049 5050 sc->sc_running = false; 5051 if (disable) 5052 urtwn_chip_stop(sc); 5053 } 5054 5055 static int 5056 urtwn_reset(struct ifnet *ifp) 5057 { 5058 struct urtwn_softc *sc = ifp->if_softc; 5059 struct ieee80211com *ic = &sc->sc_ic; 5060 5061 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5062 return ENETRESET; 5063 5064 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5065 5066 return 0; 5067 } 5068 5069 static void 5070 urtwn_chip_stop(struct urtwn_softc *sc) 5071 { 5072 uint32_t reg; 5073 bool disabled = true; 5074 5075 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5076 5077 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5078 ISSET(sc->chip, URTWN_CHIP_92EU)) 5079 return; 5080 5081 mutex_enter(&sc->sc_write_mtx); 5082 5083 /* 5084 * RF Off Sequence 5085 */ 5086 /* Pause MAC TX queue */ 5087 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5088 5089 /* Disable RF */ 5090 urtwn_rf_write(sc, 0, 0, 0); 5091 5092 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5093 5094 /* Reset BB state machine */ 5095 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5096 R92C_SYS_FUNC_EN_USBD | 5097 R92C_SYS_FUNC_EN_USBA | 5098 R92C_SYS_FUNC_EN_BB_GLB_RST); 5099 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5100 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5101 5102 /* 5103 * Reset digital sequence 5104 */ 5105 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5106 /* Reset MCU ready status */ 5107 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5108 /* If firmware in ram code, do reset */ 5109 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5110 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5111 ISSET(sc->chip, URTWN_CHIP_92EU)) 5112 urtwn_r88e_fw_reset(sc); 5113 else 5114 urtwn_fw_reset(sc); 5115 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5116 } 5117 } 5118 5119 /* Reset MAC and Enable 8051 */ 5120 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5121 5122 /* Reset MCU ready status */ 5123 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5124 5125 if (disabled) { 5126 /* Disable MAC clock */ 5127 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5128 /* Disable AFE PLL */ 5129 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5130 /* Gated AFE DIG_CLOCK */ 5131 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5132 /* Isolated digital to PON */ 5133 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5134 } 5135 5136 /* 5137 * Pull GPIO PIN to balance level and LED control 5138 */ 5139 /* 1. Disable GPIO[7:0] */ 5140 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5141 5142 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5143 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5144 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5145 5146 /* Disable GPIO[10:8] */ 5147 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5148 5149 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5150 reg |= (((reg & 0x000f) << 4) | 0x0780); 5151 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5152 5153 /* Disable LED0 & 1 */ 5154 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5155 5156 /* 5157 * Reset digital sequence 5158 */ 5159 if (disabled) { 5160 /* Disable ELDR clock */ 5161 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5162 /* Isolated ELDR to PON */ 5163 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5164 } 5165 5166 /* 5167 * Disable analog sequence 5168 */ 5169 if (disabled) { 5170 /* Disable A15 power */ 5171 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5172 /* Disable digital core power */ 5173 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5174 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5175 ~R92C_LDOV12D_CTRL_LDV12_EN); 5176 } 5177 5178 /* Enter PFM mode */ 5179 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5180 5181 /* Set USB suspend */ 5182 urtwn_write_2(sc, R92C_APS_FSMCO, 5183 R92C_APS_FSMCO_APDM_HOST | 5184 R92C_APS_FSMCO_AFSM_HSUS | 5185 R92C_APS_FSMCO_PFM_ALDN); 5186 5187 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5188 5189 mutex_exit(&sc->sc_write_mtx); 5190 } 5191 5192 static void 5193 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5194 { 5195 if (sc->sc_running == false) 5196 DELAY(ms * 1000); 5197 else 5198 usbd_delay_ms(sc->sc_udev, ms); 5199 } 5200 5201 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5202 5203 #ifdef _MODULE 5204 #include "ioconf.c" 5205 #endif 5206 5207 static int 5208 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5209 { 5210 int error = 0; 5211 5212 switch (cmd) { 5213 case MODULE_CMD_INIT: 5214 #ifdef _MODULE 5215 error = config_init_component(cfdriver_ioconf_urtwn, 5216 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5217 #endif 5218 return error; 5219 case MODULE_CMD_FINI: 5220 #ifdef _MODULE 5221 error = config_fini_component(cfdriver_ioconf_urtwn, 5222 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5223 #endif 5224 return error; 5225 default: 5226 return ENOTTY; 5227 } 5228 } 5229
Indexes created Tue Sep 30 20:09:53 GMT 2025