if_urtwn.c revision 1.105.4.1
1 /* $NetBSD: if_urtwn.c,v 1.105.4.1 2024/03/10 18:57:11 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.105.4.1 2024/03/10 18:57:11 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(TRENDNET, TEW648UBM), 207 URTWN_DEV(ZYXEL, RTL8192CU), 208 209 /* URTWN_RTL8188E */ 210 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 211 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 213 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 214 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 215 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 216 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 217 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 218 219 /* URTWN_RTL8192EU */ 220 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 221 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 222 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 223 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 224 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 225 }; 226 #undef URTWN_DEV 227 #undef URTWN_RTL8188E_DEV 228 #undef URTWN_RTL8192EU_DEV 229 230 static int urtwn_match(device_t, cfdata_t, void *); 231 static void urtwn_attach(device_t, device_t, void *); 232 static int urtwn_detach(device_t, int); 233 static int urtwn_activate(device_t, enum devact); 234 235 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 236 urtwn_attach, urtwn_detach, urtwn_activate); 237 238 static int urtwn_open_pipes(struct urtwn_softc *); 239 static void urtwn_close_pipes(struct urtwn_softc *); 240 static int urtwn_alloc_rx_list(struct urtwn_softc *); 241 static void urtwn_free_rx_list(struct urtwn_softc *); 242 static int urtwn_alloc_tx_list(struct urtwn_softc *); 243 static void urtwn_free_tx_list(struct urtwn_softc *); 244 static void urtwn_task(void *); 245 static void urtwn_do_async(struct urtwn_softc *, 246 void (*)(struct urtwn_softc *, void *), void *, int); 247 static void urtwn_wait_async(struct urtwn_softc *); 248 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 249 int); 250 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 251 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 252 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 253 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 254 int); 255 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 256 int); 257 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 258 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 259 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 260 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 261 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 262 uint32_t); 263 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 264 uint32_t); 265 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 266 uint32_t); 267 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 268 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 269 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 270 static void urtwn_efuse_read(struct urtwn_softc *); 271 static void urtwn_efuse_switch_power(struct urtwn_softc *); 272 static int urtwn_read_chipid(struct urtwn_softc *); 273 #ifdef URTWN_DEBUG 274 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 275 #endif 276 static void urtwn_read_rom(struct urtwn_softc *); 277 static void urtwn_r88e_read_rom(struct urtwn_softc *); 278 static int urtwn_media_change(struct ifnet *); 279 static int urtwn_ra_init(struct urtwn_softc *); 280 static int urtwn_get_nettype(struct urtwn_softc *); 281 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 282 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 283 static void urtwn_set_led(struct urtwn_softc *, int, int); 284 static void urtwn_calib_to(void *); 285 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 286 static void urtwn_next_scan(void *); 287 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 288 int); 289 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 290 static int urtwn_wme_update(struct ieee80211com *); 291 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 292 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 293 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 294 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 295 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 296 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 297 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 298 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 299 struct ieee80211_node *, struct urtwn_tx_data *); 300 static struct urtwn_tx_data * 301 urtwn_get_tx_data(struct urtwn_softc *, size_t); 302 static void urtwn_start(struct ifnet *); 303 static void urtwn_watchdog(struct ifnet *); 304 static int urtwn_ioctl(struct ifnet *, u_long, void *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ifnet *); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 340 /* Aliases. */ 341 #define urtwn_bb_write urtwn_write_4 342 #define urtwn_bb_read urtwn_read_4 343 344 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 345 346 static const uint16_t addaReg[] = { 347 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 348 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 349 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 350 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 351 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 352 }; 353 354 static int 355 urtwn_match(device_t parent, cfdata_t match, void *aux) 356 { 357 struct usb_attach_arg *uaa = aux; 358 359 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 360 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 361 } 362 363 static void 364 urtwn_attach(device_t parent, device_t self, void *aux) 365 { 366 struct urtwn_softc *sc = device_private(self); 367 struct ieee80211com *ic = &sc->sc_ic; 368 struct ifnet *ifp = &sc->sc_if; 369 struct usb_attach_arg *uaa = aux; 370 char *devinfop; 371 const struct urtwn_dev *dev; 372 usb_device_request_t req; 373 size_t i; 374 int error; 375 376 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 377 378 sc->sc_dev = self; 379 sc->sc_udev = uaa->uaa_device; 380 381 sc->chip = 0; 382 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 383 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 384 SET(sc->chip, URTWN_CHIP_88E); 385 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 386 SET(sc->chip, URTWN_CHIP_92EU); 387 388 aprint_naive("\n"); 389 aprint_normal("\n"); 390 391 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 392 aprint_normal_dev(self, "%s\n", devinfop); 393 usbd_devinfo_free(devinfop); 394 395 req.bmRequestType = UT_WRITE_DEVICE; 396 req.bRequest = UR_SET_FEATURE; 397 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 398 USETW(req.wIndex, UHF_PORT_SUSPEND); 399 USETW(req.wLength, 0); 400 401 (void) usbd_do_request(sc->sc_udev, &req, 0); 402 403 cv_init(&sc->sc_task_cv, "urtwntsk"); 404 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 405 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 406 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 407 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 408 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 409 410 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 411 412 callout_init(&sc->sc_scan_to, 0); 413 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 414 callout_init(&sc->sc_calib_to, 0); 415 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 416 417 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 418 RND_TYPE_NET, RND_FLAG_DEFAULT); 419 420 error = usbd_set_config_no(sc->sc_udev, 1, 0); 421 if (error != 0) { 422 aprint_error_dev(self, "failed to set configuration" 423 ", err=%s\n", usbd_errstr(error)); 424 goto fail; 425 } 426 427 /* Get the first interface handle. */ 428 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 429 if (error != 0) { 430 aprint_error_dev(self, "could not get interface handle\n"); 431 goto fail; 432 } 433 434 error = urtwn_read_chipid(sc); 435 if (error != 0) { 436 aprint_error_dev(self, "unsupported test chip\n"); 437 goto fail; 438 } 439 440 /* Determine number of Tx/Rx chains. */ 441 if (sc->chip & URTWN_CHIP_92C) { 442 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 443 sc->nrxchains = 2; 444 } else if (sc->chip & URTWN_CHIP_92EU) { 445 sc->ntxchains = 2; 446 sc->nrxchains = 2; 447 } else { 448 sc->ntxchains = 1; 449 sc->nrxchains = 1; 450 } 451 452 if (ISSET(sc->chip, URTWN_CHIP_88E) || 453 ISSET(sc->chip, URTWN_CHIP_92EU)) 454 urtwn_r88e_read_rom(sc); 455 else 456 urtwn_read_rom(sc); 457 458 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 459 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 460 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 461 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 462 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 463 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 464 "8188CUS", sc->ntxchains, sc->nrxchains, 465 ether_sprintf(ic->ic_myaddr)); 466 467 error = urtwn_open_pipes(sc); 468 if (error != 0) { 469 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 470 goto fail; 471 } 472 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 473 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 474 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 475 476 /* 477 * Setup the 802.11 device. 478 */ 479 ic->ic_ifp = ifp; 480 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 481 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 482 ic->ic_state = IEEE80211_S_INIT; 483 484 /* Set device capabilities. */ 485 ic->ic_caps = 486 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 487 IEEE80211_C_IBSS | /* IBSS mode supported */ 488 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 489 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 490 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 491 IEEE80211_C_WME | /* 802.11e */ 492 IEEE80211_C_WPA; /* 802.11i */ 493 494 /* Set supported .11b and .11g rates. */ 495 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 496 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 497 498 /* Set supported .11b and .11g channels (1 through 14). */ 499 for (i = 1; i <= 14; i++) { 500 ic->ic_channels[i].ic_freq = 501 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 502 ic->ic_channels[i].ic_flags = 503 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 504 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 505 } 506 507 ifp->if_softc = sc; 508 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 509 ifp->if_init = urtwn_init; 510 ifp->if_ioctl = urtwn_ioctl; 511 ifp->if_start = urtwn_start; 512 ifp->if_watchdog = urtwn_watchdog; 513 IFQ_SET_READY(&ifp->if_snd); 514 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 515 516 if_initialize(ifp); 517 ieee80211_ifattach(ic); 518 519 /* override default methods */ 520 ic->ic_newassoc = urtwn_newassoc; 521 ic->ic_reset = urtwn_reset; 522 ic->ic_wme.wme_update = urtwn_wme_update; 523 524 /* Override state transition machine. */ 525 sc->sc_newstate = ic->ic_newstate; 526 ic->ic_newstate = urtwn_newstate; 527 528 /* XXX media locking needs revisiting */ 529 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 530 ieee80211_media_init_with_lock(ic, 531 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 532 533 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 534 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 535 &sc->sc_drvbpf); 536 537 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 538 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 539 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 540 541 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 542 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 543 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 544 545 ifp->if_percpuq = if_percpuq_create(ifp); 546 if_register(ifp); 547 548 ieee80211_announce(ic); 549 550 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 551 552 if (!pmf_device_register(self, NULL, NULL)) 553 aprint_error_dev(self, "couldn't establish power handler\n"); 554 555 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 556 return; 557 558 fail: 559 sc->sc_dying = 1; 560 aprint_error_dev(self, "attach failed\n"); 561 } 562 563 static int 564 urtwn_detach(device_t self, int flags) 565 { 566 struct urtwn_softc *sc = device_private(self); 567 struct ifnet *ifp = &sc->sc_if; 568 int s; 569 570 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 571 572 pmf_device_deregister(self); 573 574 s = splusb(); 575 576 sc->sc_dying = 1; 577 578 callout_halt(&sc->sc_scan_to, NULL); 579 callout_halt(&sc->sc_calib_to, NULL); 580 581 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 582 urtwn_stop(ifp, 0); 583 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 584 NULL); 585 586 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 587 bpf_detach(ifp); 588 ieee80211_ifdetach(&sc->sc_ic); 589 if_detach(ifp); 590 591 mutex_destroy(&sc->sc_media_mtx); 592 593 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 594 urtwn_close_pipes(sc); 595 } 596 597 splx(s); 598 599 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 600 601 rnd_detach_source(&sc->rnd_source); 602 603 callout_destroy(&sc->sc_scan_to); 604 callout_destroy(&sc->sc_calib_to); 605 606 cv_destroy(&sc->sc_task_cv); 607 mutex_destroy(&sc->sc_write_mtx); 608 mutex_destroy(&sc->sc_fwcmd_mtx); 609 mutex_destroy(&sc->sc_tx_mtx); 610 mutex_destroy(&sc->sc_rx_mtx); 611 mutex_destroy(&sc->sc_task_mtx); 612 613 return 0; 614 } 615 616 static int 617 urtwn_activate(device_t self, enum devact act) 618 { 619 struct urtwn_softc *sc = device_private(self); 620 621 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 622 623 switch (act) { 624 case DVACT_DEACTIVATE: 625 if_deactivate(sc->sc_ic.ic_ifp); 626 return 0; 627 default: 628 return EOPNOTSUPP; 629 } 630 } 631 632 static int 633 urtwn_open_pipes(struct urtwn_softc *sc) 634 { 635 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 636 static uint8_t epaddr[R92C_MAX_EPOUT]; 637 static uint8_t rxepaddr[R92C_MAX_EPIN]; 638 usb_interface_descriptor_t *id; 639 usb_endpoint_descriptor_t *ed; 640 size_t i, ntx = 0, nrx = 0; 641 int error; 642 643 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 644 645 /* Determine the number of bulk-out pipes. */ 646 id = usbd_get_interface_descriptor(sc->sc_iface); 647 for (i = 0; i < id->bNumEndpoints; i++) { 648 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 649 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 650 continue; 651 } 652 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 653 if (ntx < sizeof(epaddr)) 654 epaddr[ntx] = ed->bEndpointAddress; 655 ntx++; 656 } 657 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 658 if (nrx < sizeof(rxepaddr)) 659 rxepaddr[nrx] = ed->bEndpointAddress; 660 nrx++; 661 } 662 } 663 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 664 aprint_error_dev(sc->sc_dev, 665 "%zd: invalid number of Rx bulk pipes\n", nrx); 666 return EIO; 667 } 668 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 669 aprint_error_dev(sc->sc_dev, 670 "%zd: invalid number of Tx bulk pipes\n", ntx); 671 return EIO; 672 } 673 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 674 nrx, ntx, 0, 0); 675 sc->rx_npipe = nrx; 676 sc->tx_npipe = ntx; 677 678 /* Open bulk-in pipe at address 0x81. */ 679 for (i = 0; i < nrx; i++) { 680 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 681 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 682 if (error != 0) { 683 aprint_error_dev(sc->sc_dev, 684 "could not open Rx bulk pipe 0x%02x: %d\n", 685 rxepaddr[i], error); 686 goto fail; 687 } 688 } 689 690 /* Open bulk-out pipes (up to 3). */ 691 for (i = 0; i < ntx; i++) { 692 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 693 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 694 if (error != 0) { 695 aprint_error_dev(sc->sc_dev, 696 "could not open Tx bulk pipe 0x%02x: %d\n", 697 epaddr[i], error); 698 goto fail; 699 } 700 } 701 702 /* Map 802.11 access categories to USB pipes. */ 703 sc->ac2idx[WME_AC_BK] = 704 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 705 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 706 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 707 708 fail: 709 if (error != 0) 710 urtwn_close_pipes(sc); 711 return error; 712 } 713 714 static void 715 urtwn_close_pipes(struct urtwn_softc *sc) 716 { 717 struct usbd_pipe *pipe; 718 size_t i; 719 720 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 721 722 /* Close Rx pipes. */ 723 CTASSERT(sizeof(pipe) == sizeof(void *)); 724 for (i = 0; i < sc->rx_npipe; i++) { 725 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 726 if (pipe != NULL) { 727 usbd_close_pipe(pipe); 728 } 729 } 730 731 /* Close Tx pipes. */ 732 for (i = 0; i < sc->tx_npipe; i++) { 733 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 734 if (pipe != NULL) { 735 usbd_close_pipe(pipe); 736 } 737 } 738 } 739 740 static int __noinline 741 urtwn_alloc_rx_list(struct urtwn_softc *sc) 742 { 743 struct urtwn_rx_data *data; 744 size_t i; 745 int error = 0; 746 747 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 748 749 for (size_t j = 0; j < sc->rx_npipe; j++) { 750 TAILQ_INIT(&sc->rx_free_list[j]); 751 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 752 data = &sc->rx_data[j][i]; 753 754 data->sc = sc; /* Backpointer for callbacks. */ 755 756 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 757 0, 0, &data->xfer); 758 if (error) { 759 aprint_error_dev(sc->sc_dev, 760 "could not allocate xfer\n"); 761 break; 762 } 763 764 data->buf = usbd_get_buffer(data->xfer); 765 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 766 } 767 } 768 if (error != 0) 769 urtwn_free_rx_list(sc); 770 return error; 771 } 772 773 static void 774 urtwn_free_rx_list(struct urtwn_softc *sc) 775 { 776 struct usbd_xfer *xfer; 777 size_t i; 778 779 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 780 781 /* NB: Caller must abort pipe first. */ 782 for (size_t j = 0; j < sc->rx_npipe; j++) { 783 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 784 CTASSERT(sizeof(xfer) == sizeof(void *)); 785 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 786 if (xfer != NULL) 787 usbd_destroy_xfer(xfer); 788 } 789 } 790 } 791 792 static int __noinline 793 urtwn_alloc_tx_list(struct urtwn_softc *sc) 794 { 795 struct urtwn_tx_data *data; 796 size_t i; 797 int error = 0; 798 799 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 800 801 mutex_enter(&sc->sc_tx_mtx); 802 for (size_t j = 0; j < sc->tx_npipe; j++) { 803 TAILQ_INIT(&sc->tx_free_list[j]); 804 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 805 data = &sc->tx_data[j][i]; 806 807 data->sc = sc; /* Backpointer for callbacks. */ 808 data->pidx = j; 809 810 error = usbd_create_xfer(sc->tx_pipe[j], 811 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 812 &data->xfer); 813 if (error) { 814 aprint_error_dev(sc->sc_dev, 815 "could not allocate xfer\n"); 816 goto fail; 817 } 818 819 data->buf = usbd_get_buffer(data->xfer); 820 821 /* Append this Tx buffer to our free list. */ 822 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 823 } 824 } 825 mutex_exit(&sc->sc_tx_mtx); 826 return 0; 827 828 fail: 829 urtwn_free_tx_list(sc); 830 mutex_exit(&sc->sc_tx_mtx); 831 return error; 832 } 833 834 static void 835 urtwn_free_tx_list(struct urtwn_softc *sc) 836 { 837 struct usbd_xfer *xfer; 838 size_t i; 839 840 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 841 842 /* NB: Caller must abort pipe first. */ 843 for (size_t j = 0; j < sc->tx_npipe; j++) { 844 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 845 CTASSERT(sizeof(xfer) == sizeof(void *)); 846 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 847 if (xfer != NULL) 848 usbd_destroy_xfer(xfer); 849 } 850 } 851 } 852 853 static int 854 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 855 struct ieee80211_node *ni) 856 { 857 struct urtwn_tx_data *data = 858 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 859 860 if (data == NULL) 861 return ENOBUFS; 862 863 return urtwn_tx(sc, m, ni, data); 864 } 865 866 static void 867 urtwn_cmdq_invariants(struct urtwn_softc *sc) 868 { 869 struct urtwn_host_cmd_ring *const ring = &sc->cmdq; 870 871 KASSERT(mutex_owned(&sc->sc_task_mtx)); 872 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 873 "%s: cur=%d next=%d queued=%d", 874 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 875 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 876 "%s: cur=%d next=%d queued=%d", 877 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 878 KASSERTMSG((ring->queued >= 0 && 879 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 880 "%s: %d commands queued", 881 device_xname(sc->sc_dev), ring->queued); 882 } 883 884 static void 885 urtwn_task(void *arg) 886 { 887 struct urtwn_softc *sc = arg; 888 struct ieee80211com *ic = &sc->sc_ic; 889 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 890 struct urtwn_host_cmd *cmd; 891 int s; 892 893 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 894 if (ic->ic_state == IEEE80211_S_RUN && 895 (ic->ic_opmode == IEEE80211_M_HOSTAP || 896 ic->ic_opmode == IEEE80211_M_IBSS)) { 897 898 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 899 &sc->sc_bo); 900 if (m == NULL) { 901 aprint_error_dev(sc->sc_dev, 902 "could not allocate beacon"); 903 } 904 905 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 906 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 907 } 908 909 /* beacon is no longer needed */ 910 m_freem(m); 911 } 912 913 /* Process host commands. */ 914 s = splusb(); 915 mutex_spin_enter(&sc->sc_task_mtx); 916 urtwn_cmdq_invariants(sc); 917 while (ring->next != ring->cur) { 918 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 919 device_xname(sc->sc_dev), 920 ring->cur, ring->next, ring->queued); 921 cmd = &ring->cmd[ring->next]; 922 mutex_spin_exit(&sc->sc_task_mtx); 923 splx(s); 924 /* Invoke callback with kernel lock held. */ 925 cmd->cb(sc, cmd->data); 926 s = splusb(); 927 mutex_spin_enter(&sc->sc_task_mtx); 928 urtwn_cmdq_invariants(sc); 929 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 930 device_xname(sc->sc_dev), 931 ring->cur, ring->next, ring->queued); 932 ring->queued--; 933 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 934 } 935 cv_broadcast(&sc->sc_task_cv); 936 mutex_spin_exit(&sc->sc_task_mtx); 937 splx(s); 938 } 939 940 static void 941 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 942 void *arg, int len) 943 { 944 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 945 struct urtwn_host_cmd *cmd; 946 bool schedtask = false; 947 int s; 948 949 URTWNHIST_FUNC(); 950 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 951 (uintptr_t)cb, (uintptr_t)arg, len, 0); 952 953 s = splusb(); 954 mutex_spin_enter(&sc->sc_task_mtx); 955 urtwn_cmdq_invariants(sc); 956 cmd = &ring->cmd[ring->cur]; 957 cmd->cb = cb; 958 KASSERT(len <= sizeof(cmd->data)); 959 memcpy(cmd->data, arg, len); 960 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 961 962 /* 963 * Schedule a task to process the command if need be. 964 */ 965 if (!sc->sc_dying) { 966 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 967 device_printf(sc->sc_dev, "command queue overflow\n"); 968 else if (ring->queued++ == 0) 969 schedtask = true; 970 } 971 mutex_spin_exit(&sc->sc_task_mtx); 972 splx(s); 973 974 if (schedtask) 975 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 976 } 977 978 static void 979 urtwn_wait_async(struct urtwn_softc *sc) 980 { 981 982 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 983 984 /* Wait for all queued asynchronous commands to complete. */ 985 mutex_spin_enter(&sc->sc_task_mtx); 986 while (sc->cmdq.queued > 0) 987 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 988 mutex_spin_exit(&sc->sc_task_mtx); 989 } 990 991 static int 992 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 993 int len) 994 { 995 usb_device_request_t req; 996 usbd_status error; 997 998 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 999 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1000 1001 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1002 req.bRequest = R92C_REQ_REGS; 1003 USETW(req.wValue, addr); 1004 USETW(req.wIndex, 0); 1005 USETW(req.wLength, len); 1006 error = usbd_do_request(sc->sc_udev, &req, buf); 1007 if (error != USBD_NORMAL_COMPLETION) { 1008 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1009 error, addr, len, 0); 1010 } 1011 return error; 1012 } 1013 1014 static void 1015 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1016 { 1017 1018 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1019 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1020 1021 urtwn_write_region_1(sc, addr, &val, 1); 1022 } 1023 1024 static void 1025 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1026 { 1027 uint8_t buf[2]; 1028 1029 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1030 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1031 1032 buf[0] = (uint8_t)val; 1033 buf[1] = (uint8_t)(val >> 8); 1034 urtwn_write_region_1(sc, addr, buf, 2); 1035 } 1036 1037 static void 1038 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1039 { 1040 uint8_t buf[4]; 1041 1042 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1043 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1044 1045 buf[0] = (uint8_t)val; 1046 buf[1] = (uint8_t)(val >> 8); 1047 buf[2] = (uint8_t)(val >> 16); 1048 buf[3] = (uint8_t)(val >> 24); 1049 urtwn_write_region_1(sc, addr, buf, 4); 1050 } 1051 1052 static int 1053 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1054 { 1055 1056 URTWNHIST_FUNC(); 1057 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1058 1059 return urtwn_write_region_1(sc, addr, buf, len); 1060 } 1061 1062 static int 1063 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1064 int len) 1065 { 1066 usb_device_request_t req; 1067 usbd_status error; 1068 1069 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1070 1071 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1072 req.bRequest = R92C_REQ_REGS; 1073 USETW(req.wValue, addr); 1074 USETW(req.wIndex, 0); 1075 USETW(req.wLength, len); 1076 error = usbd_do_request(sc->sc_udev, &req, buf); 1077 if (error != USBD_NORMAL_COMPLETION) { 1078 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1079 error, addr, len, 0); 1080 } 1081 return error; 1082 } 1083 1084 static uint8_t 1085 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1086 { 1087 uint8_t val; 1088 1089 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1090 1091 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1092 return 0xff; 1093 1094 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1095 return val; 1096 } 1097 1098 static uint16_t 1099 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1100 { 1101 uint8_t buf[2]; 1102 uint16_t val; 1103 1104 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1105 1106 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1107 return 0xffff; 1108 1109 val = LE_READ_2(&buf[0]); 1110 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1111 return val; 1112 } 1113 1114 static uint32_t 1115 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1116 { 1117 uint8_t buf[4]; 1118 uint32_t val; 1119 1120 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1121 1122 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1123 return 0xffffffff; 1124 1125 val = LE_READ_4(&buf[0]); 1126 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1127 return val; 1128 } 1129 1130 static int 1131 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1132 { 1133 struct r92c_fw_cmd cmd; 1134 uint8_t *cp; 1135 int fwcur; 1136 int ntries; 1137 1138 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1139 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1140 1141 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1142 1143 mutex_enter(&sc->sc_fwcmd_mtx); 1144 fwcur = sc->fwcur; 1145 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1146 1147 /* Wait for current FW box to be empty. */ 1148 for (ntries = 0; ntries < 100; ntries++) { 1149 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1150 break; 1151 urtwn_delay_ms(sc, 2); 1152 } 1153 if (ntries == 100) { 1154 aprint_error_dev(sc->sc_dev, 1155 "could not send firmware command %d\n", id); 1156 mutex_exit(&sc->sc_fwcmd_mtx); 1157 return ETIMEDOUT; 1158 } 1159 1160 memset(&cmd, 0, sizeof(cmd)); 1161 KASSERT(len <= sizeof(cmd.msg)); 1162 memcpy(cmd.msg, buf, len); 1163 1164 /* Write the first word last since that will trigger the FW. */ 1165 cp = (uint8_t *)&cmd; 1166 cmd.id = id; 1167 if (len >= 4) { 1168 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1169 cmd.id |= R92C_CMD_FLAG_EXT; 1170 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1171 &cp[1], 2); 1172 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1173 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1174 ((uint32_t)cp[5] << 24)); 1175 } else { 1176 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1177 &cp[4], 2); 1178 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1179 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1180 ((uint32_t)cp[3] << 24)); 1181 } 1182 } else { 1183 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1184 } 1185 mutex_exit(&sc->sc_fwcmd_mtx); 1186 1187 return 0; 1188 } 1189 1190 static __inline void 1191 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1192 { 1193 1194 sc->sc_rf_write(sc, chain, addr, val); 1195 } 1196 1197 static void 1198 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1199 uint32_t val) 1200 { 1201 1202 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1203 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1204 } 1205 1206 static void 1207 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1208 uint32_t val) 1209 { 1210 1211 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1212 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1213 } 1214 1215 static void 1216 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1217 uint32_t val) 1218 { 1219 1220 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1221 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1222 } 1223 1224 static uint32_t 1225 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1226 { 1227 uint32_t reg[R92C_MAX_CHAINS], val; 1228 1229 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1230 if (chain != 0) { 1231 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1232 } 1233 1234 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1235 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1236 urtwn_delay_ms(sc, 1); 1237 1238 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1239 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1240 R92C_HSSI_PARAM2_READ_EDGE); 1241 urtwn_delay_ms(sc, 1); 1242 1243 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1244 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1245 urtwn_delay_ms(sc, 1); 1246 1247 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1248 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1249 } else { 1250 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1251 } 1252 return MS(val, R92C_LSSI_READBACK_DATA); 1253 } 1254 1255 static int 1256 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1257 { 1258 int ntries; 1259 1260 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1261 1262 urtwn_write_4(sc, R92C_LLT_INIT, 1263 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1264 SM(R92C_LLT_INIT_ADDR, addr) | 1265 SM(R92C_LLT_INIT_DATA, data)); 1266 /* Wait for write operation to complete. */ 1267 for (ntries = 0; ntries < 20; ntries++) { 1268 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1269 R92C_LLT_INIT_OP_NO_ACTIVE) { 1270 /* Done */ 1271 return 0; 1272 } 1273 DELAY(5); 1274 } 1275 return ETIMEDOUT; 1276 } 1277 1278 static uint8_t 1279 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1280 { 1281 uint32_t reg; 1282 int ntries; 1283 1284 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1285 1286 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1287 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1288 reg &= ~R92C_EFUSE_CTRL_VALID; 1289 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1290 1291 /* Wait for read operation to complete. */ 1292 for (ntries = 0; ntries < 100; ntries++) { 1293 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1294 if (reg & R92C_EFUSE_CTRL_VALID) { 1295 /* Done */ 1296 return MS(reg, R92C_EFUSE_CTRL_DATA); 1297 } 1298 DELAY(5); 1299 } 1300 aprint_error_dev(sc->sc_dev, 1301 "could not read efuse byte at address 0x%04x\n", addr); 1302 return 0xff; 1303 } 1304 1305 static void 1306 urtwn_efuse_read(struct urtwn_softc *sc) 1307 { 1308 uint8_t *rom = (uint8_t *)&sc->rom; 1309 uint32_t reg; 1310 uint16_t addr = 0; 1311 uint8_t off, msk; 1312 size_t i; 1313 1314 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1315 1316 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1317 1318 urtwn_efuse_switch_power(sc); 1319 1320 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1321 while (addr < 512) { 1322 reg = urtwn_efuse_read_1(sc, addr); 1323 if (reg == 0xff) 1324 break; 1325 addr++; 1326 off = reg >> 4; 1327 msk = reg & 0xf; 1328 for (i = 0; i < 4; i++) { 1329 if (msk & (1U << i)) 1330 continue; 1331 1332 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1333 addr++; 1334 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1335 addr++; 1336 } 1337 } 1338 #ifdef URTWN_DEBUG 1339 /* Dump ROM content. */ 1340 for (i = 0; i < (int)sizeof(sc->rom); i++) 1341 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1342 #endif 1343 } 1344 1345 static void 1346 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1347 { 1348 uint32_t reg; 1349 1350 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1351 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1352 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1353 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1354 } 1355 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1356 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1357 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1358 reg | R92C_SYS_FUNC_EN_ELDR); 1359 } 1360 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1361 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1362 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1363 urtwn_write_2(sc, R92C_SYS_CLKR, 1364 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1365 } 1366 } 1367 1368 static int 1369 urtwn_read_chipid(struct urtwn_softc *sc) 1370 { 1371 uint32_t reg; 1372 1373 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1374 1375 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1376 ISSET(sc->chip, URTWN_CHIP_92EU)) 1377 return 0; 1378 1379 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1380 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1381 /* test chip, not supported */ 1382 return EIO; 1383 } 1384 if (reg & R92C_SYS_CFG_TYPE_92C) { 1385 sc->chip |= URTWN_CHIP_92C; 1386 /* Check if it is a castrated 8192C. */ 1387 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1388 R92C_HPON_FSM_CHIP_BONDING_ID) == 1389 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1390 sc->chip |= URTWN_CHIP_92C_1T2R; 1391 } 1392 } 1393 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1394 sc->chip |= URTWN_CHIP_UMC; 1395 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1396 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1397 } 1398 } 1399 return 0; 1400 } 1401 1402 #ifdef URTWN_DEBUG 1403 static void 1404 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1405 { 1406 1407 aprint_normal_dev(sc->sc_dev, 1408 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1409 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1410 1411 aprint_normal_dev(sc->sc_dev, 1412 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1413 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1414 1415 aprint_normal_dev(sc->sc_dev, 1416 "macaddr %s\n", 1417 ether_sprintf(rp->macaddr)); 1418 1419 aprint_normal_dev(sc->sc_dev, 1420 "string %s, subcustomer_id %#x\n", 1421 rp->string, rp->subcustomer_id); 1422 1423 aprint_normal_dev(sc->sc_dev, 1424 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1425 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1426 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1427 1428 aprint_normal_dev(sc->sc_dev, 1429 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1430 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1431 rp->ht40_1s_tx_pwr[0][2], 1432 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1433 rp->ht40_1s_tx_pwr[1][2]); 1434 1435 aprint_normal_dev(sc->sc_dev, 1436 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1437 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1438 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1439 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1440 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1441 1442 aprint_normal_dev(sc->sc_dev, 1443 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1444 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1445 rp->ht20_tx_pwr_diff[2] & 0xf, 1446 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1447 rp->ht20_tx_pwr_diff[2] >> 4); 1448 1449 aprint_normal_dev(sc->sc_dev, 1450 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1451 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1452 rp->ofdm_tx_pwr_diff[2] & 0xf, 1453 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1454 rp->ofdm_tx_pwr_diff[2] >> 4); 1455 1456 aprint_normal_dev(sc->sc_dev, 1457 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1458 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1459 rp->ht40_max_pwr[2] & 0xf, 1460 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1461 rp->ht40_max_pwr[2] >> 4); 1462 1463 aprint_normal_dev(sc->sc_dev, 1464 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1465 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1466 rp->ht20_max_pwr[2] & 0xf, 1467 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1468 rp->ht20_max_pwr[2] >> 4); 1469 1470 aprint_normal_dev(sc->sc_dev, 1471 "xtal_calib %d, tssi %d %d, thermal %d\n", 1472 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1473 1474 aprint_normal_dev(sc->sc_dev, 1475 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1476 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1477 1478 aprint_normal_dev(sc->sc_dev, 1479 "channnel_plan %d, version %d customer_id %#x\n", 1480 rp->channel_plan, rp->version, rp->curstomer_id); 1481 } 1482 #endif 1483 1484 static void 1485 urtwn_read_rom(struct urtwn_softc *sc) 1486 { 1487 struct ieee80211com *ic = &sc->sc_ic; 1488 struct r92c_rom *rom = &sc->rom; 1489 1490 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1491 1492 mutex_enter(&sc->sc_write_mtx); 1493 1494 /* Read full ROM image. */ 1495 urtwn_efuse_read(sc); 1496 #ifdef URTWN_DEBUG 1497 if (urtwn_debug & DBG_REG) 1498 urtwn_dump_rom(sc, rom); 1499 #endif 1500 1501 /* XXX Weird but this is what the vendor driver does. */ 1502 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1503 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1504 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1505 1506 DPRINTFN(DBG_INIT, 1507 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1508 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1509 1510 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1511 1512 sc->sc_rf_write = urtwn_r92c_rf_write; 1513 sc->sc_power_on = urtwn_r92c_power_on; 1514 sc->sc_dma_init = urtwn_r92c_dma_init; 1515 1516 mutex_exit(&sc->sc_write_mtx); 1517 } 1518 1519 static void 1520 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1521 { 1522 struct ieee80211com *ic = &sc->sc_ic; 1523 uint8_t *rom = sc->r88e_rom; 1524 uint32_t reg; 1525 uint16_t addr = 0; 1526 uint8_t off, msk, tmp; 1527 int i; 1528 1529 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1530 1531 mutex_enter(&sc->sc_write_mtx); 1532 1533 off = 0; 1534 urtwn_efuse_switch_power(sc); 1535 1536 /* Read full ROM image. */ 1537 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1538 while (addr < 4096) { 1539 reg = urtwn_efuse_read_1(sc, addr); 1540 if (reg == 0xff) 1541 break; 1542 addr++; 1543 if ((reg & 0x1f) == 0x0f) { 1544 tmp = (reg & 0xe0) >> 5; 1545 reg = urtwn_efuse_read_1(sc, addr); 1546 if ((reg & 0x0f) != 0x0f) 1547 off = ((reg & 0xf0) >> 1) | tmp; 1548 addr++; 1549 } else 1550 off = reg >> 4; 1551 msk = reg & 0xf; 1552 for (i = 0; i < 4; i++) { 1553 if (msk & (1 << i)) 1554 continue; 1555 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1556 addr++; 1557 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1558 addr++; 1559 } 1560 } 1561 #ifdef URTWN_DEBUG 1562 if (urtwn_debug & DBG_REG) { 1563 } 1564 #endif 1565 1566 addr = 0x10; 1567 for (i = 0; i < 6; i++) 1568 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1569 for (i = 0; i < 5; i++) 1570 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1571 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1572 if (sc->bw20_tx_pwr_diff & 0x08) 1573 sc->bw20_tx_pwr_diff |= 0xf0; 1574 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1575 if (sc->ofdm_tx_pwr_diff & 0x08) 1576 sc->ofdm_tx_pwr_diff |= 0xf0; 1577 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1578 1579 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1580 1581 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1582 sc->sc_power_on = urtwn_r92e_power_on; 1583 sc->sc_rf_write = urtwn_r92e_rf_write; 1584 } else { 1585 sc->sc_power_on = urtwn_r88e_power_on; 1586 sc->sc_rf_write = urtwn_r88e_rf_write; 1587 } 1588 sc->sc_dma_init = urtwn_r88e_dma_init; 1589 1590 mutex_exit(&sc->sc_write_mtx); 1591 } 1592 1593 static int 1594 urtwn_media_change(struct ifnet *ifp) 1595 { 1596 int error; 1597 1598 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1599 1600 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1601 return error; 1602 1603 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1604 (IFF_UP | IFF_RUNNING)) { 1605 urtwn_init(ifp); 1606 } 1607 return 0; 1608 } 1609 1610 /* 1611 * Initialize rate adaptation in firmware. 1612 */ 1613 static int __noinline 1614 urtwn_ra_init(struct urtwn_softc *sc) 1615 { 1616 static const uint8_t map[] = { 1617 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1618 }; 1619 struct ieee80211com *ic = &sc->sc_ic; 1620 struct ieee80211_node *ni = ic->ic_bss; 1621 struct ieee80211_rateset *rs = &ni->ni_rates; 1622 struct r92c_fw_cmd_macid_cfg cmd; 1623 uint32_t rates, basicrates; 1624 uint32_t rrsr_mask, rrsr_rate; 1625 uint8_t mode; 1626 size_t maxrate, maxbasicrate, i, j; 1627 int error; 1628 1629 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1630 1631 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1632 1633 /* Get normal and basic rates mask. */ 1634 rates = basicrates = 1; 1635 maxrate = maxbasicrate = 0; 1636 for (i = 0; i < rs->rs_nrates; i++) { 1637 /* Convert 802.11 rate to HW rate index. */ 1638 for (j = 0; j < __arraycount(map); j++) { 1639 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1640 break; 1641 } 1642 } 1643 if (j == __arraycount(map)) { 1644 /* Unknown rate, skip. */ 1645 continue; 1646 } 1647 1648 rates |= 1U << j; 1649 if (j > maxrate) { 1650 maxrate = j; 1651 } 1652 1653 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1654 basicrates |= 1U << j; 1655 if (j > maxbasicrate) { 1656 maxbasicrate = j; 1657 } 1658 } 1659 } 1660 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1661 mode = R92C_RAID_11B; 1662 } else { 1663 mode = R92C_RAID_11BG; 1664 } 1665 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1666 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1667 "maxrate=%jx, maxbasicrate=%jx", 1668 rates, basicrates, maxrate, maxbasicrate); 1669 1670 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1671 maxbasicrate |= R92C_RATE_SHORTGI; 1672 maxrate |= R92C_RATE_SHORTGI; 1673 } 1674 1675 /* Set rates mask for group addressed frames. */ 1676 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1677 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1678 cmd.macid |= RTWN_MACID_SHORTGI; 1679 cmd.mask = htole32((mode << 28) | basicrates); 1680 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1681 if (error != 0) { 1682 aprint_error_dev(sc->sc_dev, 1683 "could not add broadcast station\n"); 1684 return error; 1685 } 1686 /* Set initial MRR rate. */ 1687 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1688 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1689 1690 /* Set rates mask for unicast frames. */ 1691 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1692 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1693 cmd.macid |= RTWN_MACID_SHORTGI; 1694 cmd.mask = htole32((mode << 28) | rates); 1695 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1696 if (error != 0) { 1697 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1698 return error; 1699 } 1700 /* Set initial MRR rate. */ 1701 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1702 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1703 1704 rrsr_rate = ic->ic_fixed_rate; 1705 if (rrsr_rate == -1) 1706 rrsr_rate = 11; 1707 1708 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1709 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1710 1711 /* Indicate highest supported rate. */ 1712 ni->ni_txrate = rs->rs_nrates - 1; 1713 1714 return 0; 1715 } 1716 1717 static int 1718 urtwn_get_nettype(struct urtwn_softc *sc) 1719 { 1720 struct ieee80211com *ic = &sc->sc_ic; 1721 int type; 1722 1723 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1724 1725 switch (ic->ic_opmode) { 1726 case IEEE80211_M_STA: 1727 type = R92C_CR_NETTYPE_INFRA; 1728 break; 1729 1730 case IEEE80211_M_IBSS: 1731 type = R92C_CR_NETTYPE_ADHOC; 1732 break; 1733 1734 default: 1735 type = R92C_CR_NETTYPE_NOLINK; 1736 break; 1737 } 1738 1739 return type; 1740 } 1741 1742 static void 1743 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1744 { 1745 uint8_t reg; 1746 1747 URTWNHIST_FUNC(); 1748 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1749 1750 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1751 1752 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1753 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1754 } 1755 1756 static void 1757 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1758 { 1759 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1760 uint64_t tsf; 1761 1762 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1763 1764 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1765 1766 /* Enable TSF synchronization. */ 1767 urtwn_write_1(sc, R92C_BCN_CTRL, 1768 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1769 1770 /* Correct TSF */ 1771 urtwn_write_1(sc, R92C_BCN_CTRL, 1772 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1773 1774 /* Set initial TSF. */ 1775 tsf = ni->ni_tstamp.tsf; 1776 tsf = le64toh(tsf); 1777 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1778 tsf -= IEEE80211_DUR_TU; 1779 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1780 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1781 1782 urtwn_write_1(sc, R92C_BCN_CTRL, 1783 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1784 } 1785 1786 static void 1787 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1788 { 1789 uint8_t reg; 1790 1791 URTWNHIST_FUNC(); 1792 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1793 1794 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1795 1796 if (led == URTWN_LED_LINK) { 1797 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1798 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1799 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1800 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1801 (R92C_LEDCFG0_DIS << 1)); 1802 if (on) { 1803 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1804 R92E_LEDSON; 1805 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1806 } 1807 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1808 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1809 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1810 if (!on) { 1811 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1812 urtwn_write_1(sc, R92C_LEDCFG2, 1813 reg | R92C_LEDCFG0_DIS); 1814 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1815 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1816 reg & 0xfe); 1817 } 1818 } else { 1819 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1820 if (!on) { 1821 reg |= R92C_LEDCFG0_DIS; 1822 } 1823 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1824 } 1825 sc->ledlink = on; /* Save LED state. */ 1826 } 1827 } 1828 1829 static void 1830 urtwn_calib_to(void *arg) 1831 { 1832 struct urtwn_softc *sc = arg; 1833 1834 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1835 1836 if (sc->sc_dying) 1837 return; 1838 1839 /* Do it in a process context. */ 1840 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1841 } 1842 1843 /* ARGSUSED */ 1844 static void 1845 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1846 { 1847 struct r92c_fw_cmd_rssi cmd; 1848 struct r92e_fw_cmd_rssi cmde; 1849 1850 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1851 1852 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1853 goto restart_timer; 1854 1855 mutex_enter(&sc->sc_write_mtx); 1856 if (sc->avg_pwdb != -1) { 1857 /* Indicate Rx signal strength to FW for rate adaptation. */ 1858 memset(&cmd, 0, sizeof(cmd)); 1859 memset(&cmde, 0, sizeof(cmde)); 1860 cmd.macid = 0; /* BSS. */ 1861 cmde.macid = 0; /* BSS. */ 1862 cmd.pwdb = sc->avg_pwdb; 1863 cmde.pwdb = sc->avg_pwdb; 1864 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1865 sc->avg_pwdb, 0, 0, 0); 1866 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1867 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1868 sizeof(cmd)); 1869 } else { 1870 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1871 sizeof(cmde)); 1872 } 1873 } 1874 1875 /* Do temperature compensation. */ 1876 urtwn_temp_calib(sc); 1877 mutex_exit(&sc->sc_write_mtx); 1878 1879 restart_timer: 1880 if (!sc->sc_dying) { 1881 /* Restart calibration timer. */ 1882 callout_schedule(&sc->sc_calib_to, hz); 1883 } 1884 } 1885 1886 static void 1887 urtwn_next_scan(void *arg) 1888 { 1889 struct urtwn_softc *sc = arg; 1890 int s; 1891 1892 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1893 1894 if (sc->sc_dying) 1895 return; 1896 1897 s = splnet(); 1898 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1899 ieee80211_next_scan(&sc->sc_ic); 1900 splx(s); 1901 } 1902 1903 static void 1904 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1905 { 1906 URTWNHIST_FUNC(); 1907 URTWNHIST_CALLARGS("new node %06jx%06jx", 1908 ni->ni_macaddr[0] << 2 | 1909 ni->ni_macaddr[1] << 1 | 1910 ni->ni_macaddr[2], 1911 ni->ni_macaddr[3] << 2 | 1912 ni->ni_macaddr[4] << 1 | 1913 ni->ni_macaddr[5], 1914 0, 0); 1915 /* start with lowest Tx rate */ 1916 ni->ni_txrate = 0; 1917 } 1918 1919 static int 1920 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1921 { 1922 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1923 struct urtwn_cmd_newstate cmd; 1924 1925 URTWNHIST_FUNC(); 1926 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1927 1928 callout_stop(&sc->sc_scan_to); 1929 callout_stop(&sc->sc_calib_to); 1930 1931 /* Do it in a process context. */ 1932 cmd.state = nstate; 1933 cmd.arg = arg; 1934 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1935 return 0; 1936 } 1937 1938 static void 1939 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1940 { 1941 struct urtwn_cmd_newstate *cmd = arg; 1942 struct ieee80211com *ic = &sc->sc_ic; 1943 struct ieee80211_node *ni; 1944 enum ieee80211_state ostate = ic->ic_state; 1945 enum ieee80211_state nstate = cmd->state; 1946 uint32_t reg; 1947 uint8_t sifs_time, msr; 1948 int s; 1949 1950 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1951 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1952 1953 s = splnet(); 1954 mutex_enter(&sc->sc_write_mtx); 1955 1956 callout_stop(&sc->sc_scan_to); 1957 callout_stop(&sc->sc_calib_to); 1958 1959 switch (ostate) { 1960 case IEEE80211_S_INIT: 1961 break; 1962 1963 case IEEE80211_S_SCAN: 1964 if (nstate != IEEE80211_S_SCAN) { 1965 /* 1966 * End of scanning 1967 */ 1968 /* flush 4-AC Queue after site_survey */ 1969 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1970 1971 /* Allow Rx from our BSSID only. */ 1972 urtwn_write_4(sc, R92C_RCR, 1973 urtwn_read_4(sc, R92C_RCR) | 1974 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1975 } 1976 break; 1977 1978 case IEEE80211_S_AUTH: 1979 case IEEE80211_S_ASSOC: 1980 break; 1981 1982 case IEEE80211_S_RUN: 1983 /* Turn link LED off. */ 1984 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1985 1986 /* Set media status to 'No Link'. */ 1987 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1988 1989 /* Stop Rx of data frames. */ 1990 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1991 1992 /* Reset TSF. */ 1993 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1994 1995 /* Disable TSF synchronization. */ 1996 urtwn_write_1(sc, R92C_BCN_CTRL, 1997 urtwn_read_1(sc, R92C_BCN_CTRL) | 1998 R92C_BCN_CTRL_DIS_TSF_UDT0); 1999 2000 /* Back to 20MHz mode */ 2001 urtwn_set_chan(sc, ic->ic_curchan, 2002 IEEE80211_HTINFO_2NDCHAN_NONE); 2003 2004 if (ic->ic_opmode == IEEE80211_M_IBSS || 2005 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2006 /* Stop BCN */ 2007 urtwn_write_1(sc, R92C_BCN_CTRL, 2008 urtwn_read_1(sc, R92C_BCN_CTRL) & 2009 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2010 } 2011 2012 /* Reset EDCA parameters. */ 2013 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2014 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2015 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2016 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2017 2018 /* flush all cam entries */ 2019 urtwn_cam_init(sc); 2020 break; 2021 } 2022 2023 switch (nstate) { 2024 case IEEE80211_S_INIT: 2025 /* Turn link LED off. */ 2026 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2027 break; 2028 2029 case IEEE80211_S_SCAN: 2030 if (ostate != IEEE80211_S_SCAN) { 2031 /* 2032 * Begin of scanning 2033 */ 2034 2035 /* Set gain for scanning. */ 2036 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2037 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2038 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2039 2040 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2041 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2042 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2043 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2044 } 2045 2046 /* Set media status to 'No Link'. */ 2047 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2048 2049 /* Allow Rx from any BSSID. */ 2050 urtwn_write_4(sc, R92C_RCR, 2051 urtwn_read_4(sc, R92C_RCR) & 2052 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2053 2054 /* Stop Rx of data frames. */ 2055 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2056 2057 /* Disable update TSF */ 2058 urtwn_write_1(sc, R92C_BCN_CTRL, 2059 urtwn_read_1(sc, R92C_BCN_CTRL) | 2060 R92C_BCN_CTRL_DIS_TSF_UDT0); 2061 } 2062 2063 /* Make link LED blink during scan. */ 2064 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2065 2066 /* Pause AC Tx queues. */ 2067 urtwn_write_1(sc, R92C_TXPAUSE, 2068 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2069 2070 urtwn_set_chan(sc, ic->ic_curchan, 2071 IEEE80211_HTINFO_2NDCHAN_NONE); 2072 2073 /* Start periodic scan. */ 2074 if (!sc->sc_dying) 2075 callout_schedule(&sc->sc_scan_to, hz / 5); 2076 break; 2077 2078 case IEEE80211_S_AUTH: 2079 /* Set initial gain under link. */ 2080 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2081 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2082 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2083 2084 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2085 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2086 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2087 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2088 } 2089 2090 /* Set media status to 'No Link'. */ 2091 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2092 2093 /* Allow Rx from any BSSID. */ 2094 urtwn_write_4(sc, R92C_RCR, 2095 urtwn_read_4(sc, R92C_RCR) & 2096 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2097 2098 urtwn_set_chan(sc, ic->ic_curchan, 2099 IEEE80211_HTINFO_2NDCHAN_NONE); 2100 break; 2101 2102 case IEEE80211_S_ASSOC: 2103 break; 2104 2105 case IEEE80211_S_RUN: 2106 ni = ic->ic_bss; 2107 2108 /* XXX: Set 20MHz mode */ 2109 urtwn_set_chan(sc, ic->ic_curchan, 2110 IEEE80211_HTINFO_2NDCHAN_NONE); 2111 2112 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2113 /* Back to 20MHz mode */ 2114 urtwn_set_chan(sc, ic->ic_curchan, 2115 IEEE80211_HTINFO_2NDCHAN_NONE); 2116 2117 /* Set media status to 'No Link'. */ 2118 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2119 2120 /* Enable Rx of data frames. */ 2121 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2122 2123 /* Allow Rx from any BSSID. */ 2124 urtwn_write_4(sc, R92C_RCR, 2125 urtwn_read_4(sc, R92C_RCR) & 2126 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2127 2128 /* Accept Rx data/control/management frames */ 2129 urtwn_write_4(sc, R92C_RCR, 2130 urtwn_read_4(sc, R92C_RCR) | 2131 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2132 2133 /* Turn link LED on. */ 2134 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2135 break; 2136 } 2137 2138 /* Set media status to 'Associated'. */ 2139 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2140 2141 /* Set BSSID. */ 2142 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2143 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2144 2145 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2146 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2147 } else { 2148 /* 802.11b/g */ 2149 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2150 } 2151 2152 /* Enable Rx of data frames. */ 2153 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2154 2155 /* Set beacon interval. */ 2156 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2157 2158 msr = urtwn_read_1(sc, R92C_MSR); 2159 msr &= R92C_MSR_MASK; 2160 switch (ic->ic_opmode) { 2161 case IEEE80211_M_STA: 2162 /* Allow Rx from our BSSID only. */ 2163 urtwn_write_4(sc, R92C_RCR, 2164 urtwn_read_4(sc, R92C_RCR) | 2165 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2166 2167 /* Enable TSF synchronization. */ 2168 urtwn_tsf_sync_enable(sc); 2169 2170 msr |= R92C_MSR_INFRA; 2171 break; 2172 case IEEE80211_M_HOSTAP: 2173 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2174 2175 /* Allow Rx from any BSSID. */ 2176 urtwn_write_4(sc, R92C_RCR, 2177 urtwn_read_4(sc, R92C_RCR) & 2178 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2179 2180 /* Reset TSF timer to zero. */ 2181 reg = urtwn_read_4(sc, R92C_TCR); 2182 reg &= ~0x01; 2183 urtwn_write_4(sc, R92C_TCR, reg); 2184 reg |= 0x01; 2185 urtwn_write_4(sc, R92C_TCR, reg); 2186 2187 msr |= R92C_MSR_AP; 2188 break; 2189 default: 2190 msr |= R92C_MSR_ADHOC; 2191 break; 2192 } 2193 urtwn_write_1(sc, R92C_MSR, msr); 2194 2195 sifs_time = 10; 2196 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2197 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2198 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2199 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2200 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2201 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2202 2203 /* Initialize rate adaptation. */ 2204 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2205 ISSET(sc->chip, URTWN_CHIP_92EU)) 2206 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2207 else 2208 urtwn_ra_init(sc); 2209 2210 /* Turn link LED on. */ 2211 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2212 2213 /* Reset average RSSI. */ 2214 sc->avg_pwdb = -1; 2215 2216 /* Reset temperature calibration state machine. */ 2217 sc->thcal_state = 0; 2218 sc->thcal_lctemp = 0; 2219 2220 /* Start periodic calibration. */ 2221 if (!sc->sc_dying) 2222 callout_schedule(&sc->sc_calib_to, hz); 2223 break; 2224 } 2225 2226 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2227 2228 mutex_exit(&sc->sc_write_mtx); 2229 splx(s); 2230 } 2231 2232 static int 2233 urtwn_wme_update(struct ieee80211com *ic) 2234 { 2235 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2236 2237 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2238 2239 /* don't override default WME values if WME is not actually enabled */ 2240 if (!(ic->ic_flags & IEEE80211_F_WME)) 2241 return 0; 2242 2243 /* Do it in a process context. */ 2244 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2245 return 0; 2246 } 2247 2248 static void 2249 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2250 { 2251 static const uint16_t ac2reg[WME_NUM_AC] = { 2252 R92C_EDCA_BE_PARAM, 2253 R92C_EDCA_BK_PARAM, 2254 R92C_EDCA_VI_PARAM, 2255 R92C_EDCA_VO_PARAM 2256 }; 2257 struct ieee80211com *ic = &sc->sc_ic; 2258 const struct wmeParams *wmep; 2259 int ac, aifs, slottime; 2260 int s; 2261 2262 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2263 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2264 2265 s = splnet(); 2266 mutex_enter(&sc->sc_write_mtx); 2267 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2268 for (ac = 0; ac < WME_NUM_AC; ac++) { 2269 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2270 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2271 aifs = wmep->wmep_aifsn * slottime + 10; 2272 urtwn_write_4(sc, ac2reg[ac], 2273 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2274 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2275 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2276 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2277 } 2278 mutex_exit(&sc->sc_write_mtx); 2279 splx(s); 2280 } 2281 2282 static void 2283 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2284 { 2285 int pwdb; 2286 2287 URTWNHIST_FUNC(); 2288 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2289 2290 /* Convert antenna signal to percentage. */ 2291 if (rssi <= -100 || rssi >= 20) 2292 pwdb = 0; 2293 else if (rssi >= 0) 2294 pwdb = 100; 2295 else 2296 pwdb = 100 + rssi; 2297 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2298 if (rate <= 3) { 2299 /* CCK gain is smaller than OFDM/MCS gain. */ 2300 pwdb += 6; 2301 if (pwdb > 100) 2302 pwdb = 100; 2303 if (pwdb <= 14) 2304 pwdb -= 4; 2305 else if (pwdb <= 26) 2306 pwdb -= 8; 2307 else if (pwdb <= 34) 2308 pwdb -= 6; 2309 else if (pwdb <= 42) 2310 pwdb -= 2; 2311 } 2312 } 2313 if (sc->avg_pwdb == -1) /* Init. */ 2314 sc->avg_pwdb = pwdb; 2315 else if (sc->avg_pwdb < pwdb) 2316 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2317 else 2318 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2319 2320 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2321 rate, rssi, pwdb, sc->avg_pwdb); 2322 } 2323 2324 static int8_t 2325 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2326 { 2327 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2328 struct r92c_rx_phystat *phy; 2329 struct r92c_rx_cck *cck; 2330 uint8_t rpt; 2331 int8_t rssi; 2332 2333 URTWNHIST_FUNC(); 2334 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2335 2336 if (rate <= 3) { 2337 cck = (struct r92c_rx_cck *)physt; 2338 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2339 rpt = (cck->agc_rpt >> 5) & 0x3; 2340 rssi = (cck->agc_rpt & 0x1f) << 1; 2341 } else { 2342 rpt = (cck->agc_rpt >> 6) & 0x3; 2343 rssi = cck->agc_rpt & 0x3e; 2344 } 2345 rssi = cckoff[rpt] - rssi; 2346 } else { /* OFDM/HT. */ 2347 phy = (struct r92c_rx_phystat *)physt; 2348 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2349 } 2350 return rssi; 2351 } 2352 2353 static int8_t 2354 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2355 { 2356 struct r92c_rx_phystat *phy; 2357 struct r88e_rx_cck *cck; 2358 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2359 int8_t rssi; 2360 2361 URTWNHIST_FUNC(); 2362 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2363 2364 rssi = 0; 2365 if (rate <= 3) { 2366 cck = (struct r88e_rx_cck *)physt; 2367 cck_agc_rpt = cck->agc_rpt; 2368 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2369 vga_idx = cck_agc_rpt & 0x1f; 2370 switch (lna_idx) { 2371 case 7: 2372 if (vga_idx <= 27) 2373 rssi = -100 + 2* (27 - vga_idx); 2374 else 2375 rssi = -100; 2376 break; 2377 case 6: 2378 rssi = -48 + 2 * (2 - vga_idx); 2379 break; 2380 case 5: 2381 rssi = -42 + 2 * (7 - vga_idx); 2382 break; 2383 case 4: 2384 rssi = -36 + 2 * (7 - vga_idx); 2385 break; 2386 case 3: 2387 rssi = -24 + 2 * (7 - vga_idx); 2388 break; 2389 case 2: 2390 rssi = -12 + 2 * (5 - vga_idx); 2391 break; 2392 case 1: 2393 rssi = 8 - (2 * vga_idx); 2394 break; 2395 case 0: 2396 rssi = 14 - (2 * vga_idx); 2397 break; 2398 } 2399 rssi += 6; 2400 } else { /* OFDM/HT. */ 2401 phy = (struct r92c_rx_phystat *)physt; 2402 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2403 } 2404 return rssi; 2405 } 2406 2407 static void 2408 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2409 { 2410 struct ieee80211com *ic = &sc->sc_ic; 2411 struct ifnet *ifp = ic->ic_ifp; 2412 struct ieee80211_frame *wh; 2413 struct ieee80211_node *ni; 2414 struct r92c_rx_desc_usb *stat; 2415 uint32_t rxdw0, rxdw3; 2416 struct mbuf *m; 2417 uint8_t rate; 2418 int8_t rssi = 0; 2419 int s, infosz; 2420 2421 URTWNHIST_FUNC(); 2422 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2423 2424 stat = (struct r92c_rx_desc_usb *)buf; 2425 rxdw0 = le32toh(stat->rxdw0); 2426 rxdw3 = le32toh(stat->rxdw3); 2427 2428 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2429 /* 2430 * This should not happen since we setup our Rx filter 2431 * to not receive these frames. 2432 */ 2433 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2434 if_statinc(ifp, if_ierrors); 2435 return; 2436 } 2437 /* 2438 * XXX: This will drop most control packets. Do we really 2439 * want this in IEEE80211_M_MONITOR mode? 2440 */ 2441 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2442 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2443 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2444 ic->ic_stats.is_rx_tooshort++; 2445 if_statinc(ifp, if_ierrors); 2446 return; 2447 } 2448 if (__predict_false(pktlen > MCLBYTES)) { 2449 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2450 if_statinc(ifp, if_ierrors); 2451 return; 2452 } 2453 2454 rate = MS(rxdw3, R92C_RXDW3_RATE); 2455 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2456 2457 /* Get RSSI from PHY status descriptor if present. */ 2458 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2459 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2460 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2461 else 2462 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2463 /* Update our average RSSI. */ 2464 urtwn_update_avgrssi(sc, rate, rssi); 2465 } 2466 2467 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2468 pktlen, rate, infosz, rssi); 2469 2470 MGETHDR(m, M_DONTWAIT, MT_DATA); 2471 if (__predict_false(m == NULL)) { 2472 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2473 ic->ic_stats.is_rx_nobuf++; 2474 if_statinc(ifp, if_ierrors); 2475 return; 2476 } 2477 if (pktlen > (int)MHLEN) { 2478 MCLGET(m, M_DONTWAIT); 2479 if (__predict_false(!(m->m_flags & M_EXT))) { 2480 aprint_error_dev(sc->sc_dev, 2481 "couldn't allocate rx mbuf cluster\n"); 2482 m_freem(m); 2483 ic->ic_stats.is_rx_nobuf++; 2484 if_statinc(ifp, if_ierrors); 2485 return; 2486 } 2487 } 2488 2489 /* Finalize mbuf. */ 2490 m_set_rcvif(m, ifp); 2491 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2492 memcpy(mtod(m, uint8_t *), wh, pktlen); 2493 m->m_pkthdr.len = m->m_len = pktlen; 2494 2495 s = splnet(); 2496 if (__predict_false(sc->sc_drvbpf != NULL)) { 2497 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2498 2499 tap->wr_flags = 0; 2500 if (!(rxdw3 & R92C_RXDW3_HT)) { 2501 switch (rate) { 2502 /* CCK. */ 2503 case 0: tap->wr_rate = 2; break; 2504 case 1: tap->wr_rate = 4; break; 2505 case 2: tap->wr_rate = 11; break; 2506 case 3: tap->wr_rate = 22; break; 2507 /* OFDM. */ 2508 case 4: tap->wr_rate = 12; break; 2509 case 5: tap->wr_rate = 18; break; 2510 case 6: tap->wr_rate = 24; break; 2511 case 7: tap->wr_rate = 36; break; 2512 case 8: tap->wr_rate = 48; break; 2513 case 9: tap->wr_rate = 72; break; 2514 case 10: tap->wr_rate = 96; break; 2515 case 11: tap->wr_rate = 108; break; 2516 } 2517 } else if (rate >= 12) { /* MCS0~15. */ 2518 /* Bit 7 set means HT MCS instead of rate. */ 2519 tap->wr_rate = 0x80 | (rate - 12); 2520 } 2521 tap->wr_dbm_antsignal = rssi; 2522 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2523 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2524 2525 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2526 } 2527 2528 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2529 2530 /* push the frame up to the 802.11 stack */ 2531 ieee80211_input(ic, m, ni, rssi, 0); 2532 2533 /* Node is no longer needed. */ 2534 ieee80211_free_node(ni); 2535 2536 splx(s); 2537 } 2538 2539 static void 2540 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2541 { 2542 struct urtwn_rx_data *data = priv; 2543 struct urtwn_softc *sc = data->sc; 2544 struct r92c_rx_desc_usb *stat; 2545 size_t pidx = data->pidx; 2546 uint32_t rxdw0; 2547 uint8_t *buf; 2548 int len, totlen, pktlen, infosz, npkts; 2549 2550 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2551 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2552 2553 mutex_enter(&sc->sc_rx_mtx); 2554 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2555 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2556 /* Put this Rx buffer back to our free list. */ 2557 mutex_exit(&sc->sc_rx_mtx); 2558 2559 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2560 if (status == USBD_STALLED) 2561 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2562 else if (status != USBD_CANCELLED) 2563 goto resubmit; 2564 return; 2565 } 2566 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2567 2568 if (__predict_false(len < (int)sizeof(*stat))) { 2569 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2570 goto resubmit; 2571 } 2572 buf = data->buf; 2573 2574 /* Get the number of encapsulated frames. */ 2575 stat = (struct r92c_rx_desc_usb *)buf; 2576 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2577 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2578 else 2579 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2580 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2581 2582 if (npkts != 0) 2583 rnd_add_uint32(&sc->rnd_source, npkts); 2584 2585 /* Process all of them. */ 2586 while (npkts-- > 0) { 2587 if (__predict_false(len < (int)sizeof(*stat))) { 2588 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2589 len, 0, 0, 0); 2590 break; 2591 } 2592 stat = (struct r92c_rx_desc_usb *)buf; 2593 rxdw0 = le32toh(stat->rxdw0); 2594 2595 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2596 if (__predict_false(pktlen == 0)) { 2597 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2598 break; 2599 } 2600 2601 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2602 2603 /* Make sure everything fits in xfer. */ 2604 totlen = sizeof(*stat) + infosz + pktlen; 2605 if (__predict_false(totlen > len)) { 2606 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2607 (int)sizeof(*stat), infosz, pktlen, len); 2608 break; 2609 } 2610 2611 /* Process 802.11 frame. */ 2612 urtwn_rx_frame(sc, buf, pktlen); 2613 2614 /* Next chunk is 128-byte aligned. */ 2615 totlen = roundup2(totlen, 128); 2616 buf += totlen; 2617 len -= totlen; 2618 } 2619 2620 resubmit: 2621 /* Setup a new transfer. */ 2622 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2623 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2624 (void)usbd_transfer(xfer); 2625 } 2626 2627 static void 2628 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2629 { 2630 size_t pidx = data->pidx; 2631 2632 mutex_enter(&sc->sc_tx_mtx); 2633 /* Put this Tx buffer back to our free list. */ 2634 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2635 mutex_exit(&sc->sc_tx_mtx); 2636 } 2637 2638 static void 2639 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2640 { 2641 struct urtwn_tx_data *data = priv; 2642 struct urtwn_softc *sc = data->sc; 2643 struct ifnet *ifp = &sc->sc_if; 2644 size_t pidx = data->pidx; 2645 int s; 2646 2647 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2648 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2649 2650 urtwn_put_tx_data(sc, data); 2651 2652 s = splnet(); 2653 sc->tx_timer = 0; 2654 ifp->if_flags &= ~IFF_OACTIVE; 2655 2656 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2657 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2658 if (status == USBD_STALLED) { 2659 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2660 usbd_clear_endpoint_stall_async(pipe); 2661 } 2662 device_printf(sc->sc_dev, "transmit failed, %s\n", 2663 usbd_errstr(status)); 2664 if_statinc(ifp, if_oerrors); 2665 } 2666 splx(s); 2667 return; 2668 } 2669 2670 if_statinc(ifp, if_opackets); 2671 urtwn_start(ifp); 2672 splx(s); 2673 2674 } 2675 2676 static int 2677 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2678 struct urtwn_tx_data *data) 2679 { 2680 struct ieee80211com *ic = &sc->sc_ic; 2681 struct ieee80211_frame *wh; 2682 struct ieee80211_key *k = NULL; 2683 struct r92c_tx_desc_usb *txd; 2684 size_t i, padsize, xferlen, txd_len; 2685 uint16_t seq, sum; 2686 uint8_t raid, type, tid; 2687 int s, hasqos, error; 2688 2689 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2690 2691 wh = mtod(m, struct ieee80211_frame *); 2692 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2693 txd_len = sizeof(*txd); 2694 2695 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2696 txd_len = 32; 2697 2698 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2699 k = ieee80211_crypto_encap(ic, ni, m); 2700 if (k == NULL) { 2701 urtwn_put_tx_data(sc, data); 2702 m_free(m); 2703 return ENOBUFS; 2704 } 2705 2706 /* packet header may have moved, reset our local pointer */ 2707 wh = mtod(m, struct ieee80211_frame *); 2708 } 2709 2710 if (__predict_false(sc->sc_drvbpf != NULL)) { 2711 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2712 2713 tap->wt_flags = 0; 2714 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2715 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2716 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2717 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2718 2719 /* XXX: set tap->wt_rate? */ 2720 2721 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2722 } 2723 2724 /* non-qos data frames */ 2725 tid = R92C_TXDW1_QSEL_BE; 2726 if ((hasqos = ieee80211_has_qos(wh))) { 2727 /* data frames in 11n mode */ 2728 struct ieee80211_qosframe *qwh = (void *)wh; 2729 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2730 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2731 tid = R92C_TXDW1_QSEL_MGNT; 2732 } 2733 2734 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2735 padsize = 8; 2736 else 2737 padsize = 0; 2738 2739 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2740 padsize = 0; 2741 2742 /* Fill Tx descriptor. */ 2743 txd = (struct r92c_tx_desc_usb *)data->buf; 2744 memset(txd, 0, txd_len + padsize); 2745 2746 txd->txdw0 |= htole32( 2747 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2748 SM(R92C_TXDW0_OFFSET, txd_len)); 2749 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2750 txd->txdw0 |= htole32( 2751 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2752 } 2753 2754 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2755 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2756 2757 /* fix pad field */ 2758 if (padsize > 0) { 2759 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2760 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2761 } 2762 2763 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2764 type == IEEE80211_FC0_TYPE_DATA) { 2765 if (ic->ic_curmode == IEEE80211_MODE_11B) 2766 raid = R92C_RAID_11B; 2767 else 2768 raid = R92C_RAID_11BG; 2769 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2770 tid, raid, 0, 0); 2771 2772 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2773 txd->txdw1 |= htole32( 2774 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2775 SM(R92C_TXDW1_QSEL, tid) | 2776 SM(R92C_TXDW1_RAID, raid) | 2777 R92C_TXDW1_AGGBK); 2778 } else 2779 txd->txdw1 |= htole32( 2780 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2781 SM(R92C_TXDW1_QSEL, tid) | 2782 SM(R92C_TXDW1_RAID, raid) | 2783 R92C_TXDW1_AGGBK); 2784 2785 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2786 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2787 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2788 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2789 2790 if (hasqos) { 2791 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2792 } 2793 2794 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2795 /* for 11g */ 2796 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2797 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2798 R92C_TXDW4_HWRTSEN); 2799 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2800 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2801 R92C_TXDW4_HWRTSEN); 2802 } 2803 } 2804 /* Send RTS at OFDM24. */ 2805 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2806 txd->txdw5 |= htole32(0x0001ff00); 2807 /* Send data at OFDM54. */ 2808 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2809 txd->txdw5 |= htole32(0x13 & 0x3f); 2810 else 2811 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2812 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2813 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2814 txd->txdw1 |= htole32( 2815 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2816 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2817 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2818 2819 /* Force CCK1. */ 2820 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2821 /* Use 1Mbps */ 2822 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2823 } else { 2824 /* broadcast or multicast packets */ 2825 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2826 txd->txdw1 |= htole32( 2827 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2828 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2829 2830 /* Force CCK1. */ 2831 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2832 /* Use 1Mbps */ 2833 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2834 } 2835 /* Set sequence number */ 2836 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2837 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2838 txd->txdseq |= htole16(seq); 2839 2840 if (!hasqos) { 2841 /* Use HW sequence numbering for non-QoS frames. */ 2842 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2843 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2844 } 2845 } else { 2846 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2847 R92E_HWSEQ_SHIFT); 2848 if (!hasqos) { 2849 /* Use HW sequence numbering for non-QoS frames. */ 2850 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2851 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2852 } 2853 } 2854 2855 /* Compute Tx descriptor checksum. */ 2856 sum = 0; 2857 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2858 sum ^= ((uint16_t *)txd)[i]; 2859 txd->txdsum = sum; /* NB: already little endian. */ 2860 2861 xferlen = txd_len + m->m_pkthdr.len + padsize; 2862 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2863 2864 s = splnet(); 2865 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2866 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2867 urtwn_txeof); 2868 error = usbd_transfer(data->xfer); 2869 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2870 error != USBD_IN_PROGRESS)) { 2871 splx(s); 2872 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2873 return error; 2874 } 2875 splx(s); 2876 return 0; 2877 } 2878 2879 struct urtwn_tx_data * 2880 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2881 { 2882 struct urtwn_tx_data *data = NULL; 2883 2884 mutex_enter(&sc->sc_tx_mtx); 2885 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2886 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2887 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2888 } 2889 mutex_exit(&sc->sc_tx_mtx); 2890 2891 return data; 2892 } 2893 2894 static void 2895 urtwn_start(struct ifnet *ifp) 2896 { 2897 struct urtwn_softc *sc = ifp->if_softc; 2898 struct ieee80211com *ic = &sc->sc_ic; 2899 struct urtwn_tx_data *data; 2900 struct ether_header *eh; 2901 struct ieee80211_node *ni; 2902 struct mbuf *m; 2903 2904 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2905 2906 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2907 return; 2908 2909 data = NULL; 2910 for (;;) { 2911 /* Send pending management frames first. */ 2912 IF_POLL(&ic->ic_mgtq, m); 2913 if (m != NULL) { 2914 /* Use AC_VO for management frames. */ 2915 2916 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2917 2918 if (data == NULL) { 2919 ifp->if_flags |= IFF_OACTIVE; 2920 DPRINTFN(DBG_TX, "empty tx_free_list", 2921 0, 0, 0, 0); 2922 return; 2923 } 2924 IF_DEQUEUE(&ic->ic_mgtq, m); 2925 ni = M_GETCTX(m, struct ieee80211_node *); 2926 M_CLEARCTX(m); 2927 goto sendit; 2928 } 2929 if (ic->ic_state != IEEE80211_S_RUN) 2930 break; 2931 2932 /* Encapsulate and send data frames. */ 2933 IFQ_POLL(&ifp->if_snd, m); 2934 if (m == NULL) 2935 break; 2936 2937 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2938 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2939 uint8_t qid = WME_AC_BE; 2940 if (ieee80211_has_qos(wh)) { 2941 /* data frames in 11n mode */ 2942 struct ieee80211_qosframe *qwh = (void *)wh; 2943 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2944 qid = TID_TO_WME_AC(tid); 2945 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2946 qid = WME_AC_VO; 2947 } 2948 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2949 2950 if (data == NULL) { 2951 ifp->if_flags |= IFF_OACTIVE; 2952 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2953 return; 2954 } 2955 IFQ_DEQUEUE(&ifp->if_snd, m); 2956 2957 if (m->m_len < (int)sizeof(*eh) && 2958 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2959 device_printf(sc->sc_dev, "m_pullup failed\n"); 2960 if_statinc(ifp, if_oerrors); 2961 urtwn_put_tx_data(sc, data); 2962 m_freem(m); 2963 continue; 2964 } 2965 eh = mtod(m, struct ether_header *); 2966 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2967 if (ni == NULL) { 2968 device_printf(sc->sc_dev, 2969 "unable to find transmit node\n"); 2970 if_statinc(ifp, if_oerrors); 2971 urtwn_put_tx_data(sc, data); 2972 m_freem(m); 2973 continue; 2974 } 2975 2976 bpf_mtap(ifp, m, BPF_D_OUT); 2977 2978 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2979 ieee80211_free_node(ni); 2980 device_printf(sc->sc_dev, 2981 "unable to encapsulate packet\n"); 2982 if_statinc(ifp, if_oerrors); 2983 urtwn_put_tx_data(sc, data); 2984 m_freem(m); 2985 continue; 2986 } 2987 sendit: 2988 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2989 2990 if (urtwn_tx(sc, m, ni, data) != 0) { 2991 m_freem(m); 2992 ieee80211_free_node(ni); 2993 device_printf(sc->sc_dev, 2994 "unable to transmit packet\n"); 2995 if_statinc(ifp, if_oerrors); 2996 continue; 2997 } 2998 m_freem(m); 2999 ieee80211_free_node(ni); 3000 sc->tx_timer = 5; 3001 ifp->if_timer = 1; 3002 } 3003 } 3004 3005 static void 3006 urtwn_watchdog(struct ifnet *ifp) 3007 { 3008 struct urtwn_softc *sc = ifp->if_softc; 3009 3010 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3011 3012 ifp->if_timer = 0; 3013 3014 if (sc->tx_timer > 0) { 3015 if (--sc->tx_timer == 0) { 3016 device_printf(sc->sc_dev, "device timeout\n"); 3017 /* urtwn_init(ifp); XXX needs a process context! */ 3018 if_statinc(ifp, if_oerrors); 3019 return; 3020 } 3021 ifp->if_timer = 1; 3022 } 3023 ieee80211_watchdog(&sc->sc_ic); 3024 } 3025 3026 static int 3027 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3028 { 3029 struct urtwn_softc *sc = ifp->if_softc; 3030 struct ieee80211com *ic = &sc->sc_ic; 3031 int s, error = 0; 3032 3033 URTWNHIST_FUNC(); 3034 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3035 0, 0); 3036 3037 s = splnet(); 3038 3039 switch (cmd) { 3040 case SIOCSIFFLAGS: 3041 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3042 break; 3043 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3044 case IFF_UP | IFF_RUNNING: 3045 break; 3046 case IFF_UP: 3047 urtwn_init(ifp); 3048 break; 3049 case IFF_RUNNING: 3050 urtwn_stop(ifp, 1); 3051 break; 3052 case 0: 3053 break; 3054 } 3055 break; 3056 3057 case SIOCADDMULTI: 3058 case SIOCDELMULTI: 3059 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3060 /* setup multicast filter, etc */ 3061 error = 0; 3062 } 3063 break; 3064 3065 case SIOCS80211CHANNEL: 3066 /* 3067 * This allows for fast channel switching in monitor mode 3068 * (used by kismet). In IBSS mode, we must explicitly reset 3069 * the interface to generate a new beacon frame. 3070 */ 3071 error = ieee80211_ioctl(ic, cmd, data); 3072 if (error == ENETRESET && 3073 ic->ic_opmode == IEEE80211_M_MONITOR) { 3074 urtwn_set_chan(sc, ic->ic_curchan, 3075 IEEE80211_HTINFO_2NDCHAN_NONE); 3076 error = 0; 3077 } 3078 break; 3079 3080 default: 3081 error = ieee80211_ioctl(ic, cmd, data); 3082 break; 3083 } 3084 if (error == ENETRESET) { 3085 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3086 (IFF_UP | IFF_RUNNING) && 3087 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3088 urtwn_init(ifp); 3089 } 3090 error = 0; 3091 } 3092 3093 splx(s); 3094 3095 return error; 3096 } 3097 3098 static __inline int 3099 urtwn_power_on(struct urtwn_softc *sc) 3100 { 3101 3102 return sc->sc_power_on(sc); 3103 } 3104 3105 static int 3106 urtwn_r92c_power_on(struct urtwn_softc *sc) 3107 { 3108 uint32_t reg; 3109 int ntries; 3110 3111 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3112 3113 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3114 3115 /* Wait for autoload done bit. */ 3116 for (ntries = 0; ntries < 1000; ntries++) { 3117 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3118 break; 3119 DELAY(5); 3120 } 3121 if (ntries == 1000) { 3122 aprint_error_dev(sc->sc_dev, 3123 "timeout waiting for chip autoload\n"); 3124 return ETIMEDOUT; 3125 } 3126 3127 /* Unlock ISO/CLK/Power control register. */ 3128 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3129 DELAY(5); 3130 /* Move SPS into PWM mode. */ 3131 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3132 DELAY(5); 3133 3134 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3135 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3136 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3137 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3138 DELAY(100); 3139 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3140 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3141 ~R92C_SYS_ISO_CTRL_MD2PP); 3142 } 3143 3144 /* Auto enable WLAN. */ 3145 urtwn_write_2(sc, R92C_APS_FSMCO, 3146 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3147 for (ntries = 0; ntries < 1000; ntries++) { 3148 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3149 R92C_APS_FSMCO_APFM_ONMAC)) 3150 break; 3151 DELAY(100); 3152 } 3153 if (ntries == 1000) { 3154 aprint_error_dev(sc->sc_dev, 3155 "timeout waiting for MAC auto ON\n"); 3156 return ETIMEDOUT; 3157 } 3158 3159 /* Enable radio, GPIO and LED functions. */ 3160 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3161 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3162 urtwn_write_2(sc, R92C_APS_FSMCO, 3163 R92C_APS_FSMCO_AFSM_HSUS | 3164 R92C_APS_FSMCO_PDN_EN | 3165 R92C_APS_FSMCO_PFM_ALDN); 3166 3167 /* Release RF digital isolation. */ 3168 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3169 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3170 3171 /* Initialize MAC. */ 3172 urtwn_write_1(sc, R92C_APSD_CTRL, 3173 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3174 for (ntries = 0; ntries < 200; ntries++) { 3175 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3176 R92C_APSD_CTRL_OFF_STATUS)) 3177 break; 3178 DELAY(5); 3179 } 3180 if (ntries == 200) { 3181 aprint_error_dev(sc->sc_dev, 3182 "timeout waiting for MAC initialization\n"); 3183 return ETIMEDOUT; 3184 } 3185 3186 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3187 reg = urtwn_read_2(sc, R92C_CR); 3188 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3189 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3190 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3191 R92C_CR_ENSEC; 3192 urtwn_write_2(sc, R92C_CR, reg); 3193 3194 urtwn_write_1(sc, 0xfe10, 0x19); 3195 3196 urtwn_delay_ms(sc, 1); 3197 3198 return 0; 3199 } 3200 3201 static int 3202 urtwn_r92e_power_on(struct urtwn_softc *sc) 3203 { 3204 uint32_t reg; 3205 uint32_t val; 3206 int ntries; 3207 3208 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3209 3210 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3211 3212 /* Enable radio, GPIO and LED functions. */ 3213 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3214 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3215 urtwn_write_2(sc, R92C_APS_FSMCO, 3216 R92C_APS_FSMCO_AFSM_HSUS | 3217 R92C_APS_FSMCO_PDN_EN | 3218 R92C_APS_FSMCO_PFM_ALDN); 3219 3220 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3221 /* LDO. */ 3222 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3223 } 3224 else { 3225 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3226 R92C_SYS_SWR_CTRL2) & 0xffff); 3227 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3228 } 3229 3230 for (ntries = 0; ntries < 2; ntries++) { 3231 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3232 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3233 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3234 R92C_AFE_CTRL4)); 3235 } 3236 3237 /* Reset BB. */ 3238 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3239 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3240 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3241 3242 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3243 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3244 3245 /* Disable HWPDN. */ 3246 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3247 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3248 3249 /* Disable WL suspend. */ 3250 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3251 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3252 R92C_APS_FSMCO_AFSM_HSUS)); 3253 3254 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3255 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3256 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3257 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3258 for (ntries = 0; ntries < 10000; ntries++) { 3259 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3260 R92C_APS_FSMCO_APFM_ONMAC; 3261 if (val == 0x0) 3262 break; 3263 DELAY(10); 3264 } 3265 if (ntries == 10000) { 3266 aprint_error_dev(sc->sc_dev, 3267 "timeout waiting for chip power up\n"); 3268 return ETIMEDOUT; 3269 } 3270 3271 urtwn_write_2(sc, R92C_CR, 0x00); 3272 reg = urtwn_read_2(sc, R92C_CR); 3273 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3274 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3275 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3276 urtwn_write_2(sc, R92C_CR, reg); 3277 3278 return 0; 3279 } 3280 3281 static int 3282 urtwn_r88e_power_on(struct urtwn_softc *sc) 3283 { 3284 uint32_t reg; 3285 uint8_t val; 3286 int ntries; 3287 3288 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3289 3290 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3291 3292 /* Wait for power ready bit. */ 3293 for (ntries = 0; ntries < 5000; ntries++) { 3294 val = urtwn_read_1(sc, 0x6) & 0x2; 3295 if (val == 0x2) 3296 break; 3297 DELAY(10); 3298 } 3299 if (ntries == 5000) { 3300 aprint_error_dev(sc->sc_dev, 3301 "timeout waiting for chip power up\n"); 3302 return ETIMEDOUT; 3303 } 3304 3305 /* Reset BB. */ 3306 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3307 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3308 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3309 3310 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3311 3312 /* Disable HWPDN. */ 3313 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3314 3315 /* Disable WL suspend. */ 3316 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3317 3318 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3319 for (ntries = 0; ntries < 5000; ntries++) { 3320 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3321 break; 3322 DELAY(10); 3323 } 3324 if (ntries == 5000) 3325 return ETIMEDOUT; 3326 3327 /* Enable LDO normal mode. */ 3328 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3329 3330 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3331 urtwn_write_2(sc, R92C_CR, 0); 3332 reg = urtwn_read_2(sc, R92C_CR); 3333 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3334 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3335 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3336 urtwn_write_2(sc, R92C_CR, reg); 3337 3338 return 0; 3339 } 3340 3341 static int __noinline 3342 urtwn_llt_init(struct urtwn_softc *sc) 3343 { 3344 size_t i, page_count, pktbuf_count; 3345 uint32_t val; 3346 int error; 3347 3348 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3349 3350 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3351 3352 if (sc->chip & URTWN_CHIP_88E) 3353 page_count = R88E_TX_PAGE_COUNT; 3354 else if (sc->chip & URTWN_CHIP_92EU) 3355 page_count = R92E_TX_PAGE_COUNT; 3356 else 3357 page_count = R92C_TX_PAGE_COUNT; 3358 if (sc->chip & URTWN_CHIP_88E) 3359 pktbuf_count = R88E_TXPKTBUF_COUNT; 3360 else if (sc->chip & URTWN_CHIP_92EU) 3361 pktbuf_count = R88E_TXPKTBUF_COUNT; 3362 else 3363 pktbuf_count = R92C_TXPKTBUF_COUNT; 3364 3365 if (sc->chip & URTWN_CHIP_92EU) { 3366 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3367 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3368 DELAY(100); 3369 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3370 if (val & R92E_AUTO_LLT_EN) 3371 return EIO; 3372 return 0; 3373 } 3374 3375 /* Reserve pages [0; page_count]. */ 3376 for (i = 0; i < page_count; i++) { 3377 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3378 return error; 3379 } 3380 /* NB: 0xff indicates end-of-list. */ 3381 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3382 return error; 3383 /* 3384 * Use pages [page_count + 1; pktbuf_count - 1] 3385 * as ring buffer. 3386 */ 3387 for (++i; i < pktbuf_count - 1; i++) { 3388 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3389 return error; 3390 } 3391 /* Make the last page point to the beginning of the ring buffer. */ 3392 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3393 return error; 3394 } 3395 3396 static void 3397 urtwn_fw_reset(struct urtwn_softc *sc) 3398 { 3399 uint16_t reg; 3400 int ntries; 3401 3402 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3403 3404 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3405 3406 /* Tell 8051 to reset itself. */ 3407 mutex_enter(&sc->sc_fwcmd_mtx); 3408 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3409 sc->fwcur = 0; 3410 mutex_exit(&sc->sc_fwcmd_mtx); 3411 3412 /* Wait until 8051 resets by itself. */ 3413 for (ntries = 0; ntries < 100; ntries++) { 3414 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3415 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3416 return; 3417 DELAY(50); 3418 } 3419 /* Force 8051 reset. */ 3420 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3421 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3422 } 3423 3424 static void 3425 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3426 { 3427 uint16_t reg; 3428 3429 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3430 3431 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3432 3433 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3434 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3435 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3436 } 3437 DELAY(50); 3438 3439 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3440 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3441 DELAY(50); 3442 3443 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3444 DELAY(50); 3445 3446 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3447 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3448 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3449 } 3450 DELAY(50); 3451 3452 mutex_enter(&sc->sc_fwcmd_mtx); 3453 /* Init firmware commands ring. */ 3454 sc->fwcur = 0; 3455 mutex_exit(&sc->sc_fwcmd_mtx); 3456 3457 } 3458 3459 static int 3460 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3461 { 3462 uint32_t reg; 3463 int off, mlen, error = 0; 3464 3465 URTWNHIST_FUNC(); 3466 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3467 page, (uintptr_t)buf, len, 0); 3468 3469 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3470 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3471 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3472 3473 off = R92C_FW_START_ADDR; 3474 while (len > 0) { 3475 if (len > 196) 3476 mlen = 196; 3477 else if (len > 4) 3478 mlen = 4; 3479 else 3480 mlen = 1; 3481 error = urtwn_write_region(sc, off, buf, mlen); 3482 if (error != 0) 3483 break; 3484 off += mlen; 3485 buf += mlen; 3486 len -= mlen; 3487 } 3488 return error; 3489 } 3490 3491 static int __noinline 3492 urtwn_load_firmware(struct urtwn_softc *sc) 3493 { 3494 firmware_handle_t fwh; 3495 const struct r92c_fw_hdr *hdr; 3496 const char *name; 3497 u_char *fw, *ptr; 3498 size_t len; 3499 uint32_t reg; 3500 int mlen, ntries, page, error; 3501 3502 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3503 3504 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3505 3506 /* Read firmware image from the filesystem. */ 3507 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3508 name = "rtl8188eufw.bin"; 3509 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3510 name = "rtl8192eefw.bin"; 3511 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3512 URTWN_CHIP_UMC_A_CUT) 3513 name = "rtl8192cfwU.bin"; 3514 else 3515 name = "rtl8192cfw.bin"; 3516 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3517 aprint_error_dev(sc->sc_dev, 3518 "failed load firmware of file %s (error %d)\n", name, 3519 error); 3520 return error; 3521 } 3522 const size_t fwlen = len = firmware_get_size(fwh); 3523 fw = firmware_malloc(len); 3524 if (fw == NULL) { 3525 aprint_error_dev(sc->sc_dev, 3526 "failed to allocate firmware memory\n"); 3527 firmware_close(fwh); 3528 return ENOMEM; 3529 } 3530 error = firmware_read(fwh, 0, fw, len); 3531 firmware_close(fwh); 3532 if (error != 0) { 3533 aprint_error_dev(sc->sc_dev, 3534 "failed to read firmware (error %d)\n", error); 3535 firmware_free(fw, fwlen); 3536 return error; 3537 } 3538 3539 len = fwlen; 3540 ptr = fw; 3541 hdr = (const struct r92c_fw_hdr *)ptr; 3542 /* Check if there is a valid FW header and skip it. */ 3543 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3544 (le16toh(hdr->signature) >> 4) == 0x88e || 3545 (le16toh(hdr->signature) >> 4) == 0x92e || 3546 (le16toh(hdr->signature) >> 4) == 0x92c) { 3547 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3548 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3549 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3550 hdr->month, hdr->date, hdr->hour, hdr->minute); 3551 ptr += sizeof(*hdr); 3552 len -= sizeof(*hdr); 3553 } 3554 3555 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3556 /* Reset MCU ready status */ 3557 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3558 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3559 ISSET(sc->chip, URTWN_CHIP_92EU)) 3560 urtwn_r88e_fw_reset(sc); 3561 else 3562 urtwn_fw_reset(sc); 3563 } 3564 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3565 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3566 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3567 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3568 R92C_SYS_FUNC_EN_CPUEN); 3569 } 3570 3571 /* download enabled */ 3572 urtwn_write_1(sc, R92C_MCUFWDL, 3573 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3574 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3575 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3576 3577 /* Reset the FWDL checksum. */ 3578 urtwn_write_1(sc, R92C_MCUFWDL, 3579 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3580 3581 DELAY(50); 3582 /* download firmware */ 3583 for (page = 0; len > 0; page++) { 3584 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3585 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3586 if (error != 0) { 3587 aprint_error_dev(sc->sc_dev, 3588 "could not load firmware page %d\n", page); 3589 goto fail; 3590 } 3591 ptr += mlen; 3592 len -= mlen; 3593 } 3594 3595 /* download disable */ 3596 urtwn_write_1(sc, R92C_MCUFWDL, 3597 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3598 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3599 3600 /* Wait for checksum report. */ 3601 for (ntries = 0; ntries < 1000; ntries++) { 3602 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3603 break; 3604 DELAY(5); 3605 } 3606 if (ntries == 1000) { 3607 aprint_error_dev(sc->sc_dev, 3608 "timeout waiting for checksum report\n"); 3609 error = ETIMEDOUT; 3610 goto fail; 3611 } 3612 3613 /* Wait for firmware readiness. */ 3614 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3615 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3616 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3617 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3618 ISSET(sc->chip, URTWN_CHIP_92EU)) 3619 urtwn_r88e_fw_reset(sc); 3620 for (ntries = 0; ntries < 6000; ntries++) { 3621 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3622 break; 3623 DELAY(5); 3624 } 3625 if (ntries == 6000) { 3626 aprint_error_dev(sc->sc_dev, 3627 "timeout waiting for firmware readiness\n"); 3628 error = ETIMEDOUT; 3629 goto fail; 3630 } 3631 fail: 3632 firmware_free(fw, fwlen); 3633 return error; 3634 } 3635 3636 static __inline int 3637 urtwn_dma_init(struct urtwn_softc *sc) 3638 { 3639 3640 return sc->sc_dma_init(sc); 3641 } 3642 3643 static int 3644 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3645 { 3646 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3647 uint32_t reg; 3648 int error; 3649 3650 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3651 3652 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3653 3654 /* Initialize LLT table. */ 3655 error = urtwn_llt_init(sc); 3656 if (error != 0) 3657 return error; 3658 3659 /* Get Tx queues to USB endpoints mapping. */ 3660 hashq = hasnq = haslq = 0; 3661 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3662 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3663 if (MS(reg, R92C_USB_EP_HQ) != 0) 3664 hashq = 1; 3665 if (MS(reg, R92C_USB_EP_NQ) != 0) 3666 hasnq = 1; 3667 if (MS(reg, R92C_USB_EP_LQ) != 0) 3668 haslq = 1; 3669 nqueues = hashq + hasnq + haslq; 3670 if (nqueues == 0) 3671 return EIO; 3672 /* Get the number of pages for each queue. */ 3673 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3674 /* The remaining pages are assigned to the high priority queue. */ 3675 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3676 3677 /* Set number of pages for normal priority queue. */ 3678 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3679 urtwn_write_4(sc, R92C_RQPN, 3680 /* Set number of pages for public queue. */ 3681 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3682 /* Set number of pages for high priority queue. */ 3683 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3684 /* Set number of pages for low priority queue. */ 3685 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3686 /* Load values. */ 3687 R92C_RQPN_LD); 3688 3689 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3690 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3691 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3692 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3693 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3694 3695 /* Set queue to USB pipe mapping. */ 3696 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3697 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3698 if (nqueues == 1) { 3699 if (hashq) { 3700 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3701 } else if (hasnq) { 3702 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3703 } else { 3704 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3705 } 3706 } else if (nqueues == 2) { 3707 /* All 2-endpoints configs have a high priority queue. */ 3708 if (!hashq) { 3709 return EIO; 3710 } 3711 if (hasnq) { 3712 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3713 } else { 3714 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3715 } 3716 } else { 3717 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3718 } 3719 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3720 3721 /* Set Tx/Rx transfer page boundary. */ 3722 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3723 3724 /* Set Tx/Rx transfer page size. */ 3725 urtwn_write_1(sc, R92C_PBP, 3726 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3727 return 0; 3728 } 3729 3730 static int 3731 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3732 { 3733 usb_interface_descriptor_t *id; 3734 uint32_t reg; 3735 int nqueues; 3736 int error; 3737 3738 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3739 3740 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3741 3742 /* Initialize LLT table. */ 3743 error = urtwn_llt_init(sc); 3744 if (error != 0) 3745 return error; 3746 3747 /* Get Tx queues to USB endpoints mapping. */ 3748 id = usbd_get_interface_descriptor(sc->sc_iface); 3749 nqueues = id->bNumEndpoints - 1; 3750 if (nqueues == 0) 3751 return EIO; 3752 3753 /* Set number of pages for normal priority queue. */ 3754 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3755 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3756 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3757 3758 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3759 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3760 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3761 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3762 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3763 3764 /* Set queue to USB pipe mapping. */ 3765 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3766 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3767 if (nqueues == 1) 3768 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3769 else if (nqueues == 2) 3770 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3771 else 3772 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3773 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3774 3775 /* Set Tx/Rx transfer page boundary. */ 3776 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3777 3778 /* Set Tx/Rx transfer page size. */ 3779 urtwn_write_1(sc, R92C_PBP, 3780 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3781 3782 return 0; 3783 } 3784 3785 static void __noinline 3786 urtwn_mac_init(struct urtwn_softc *sc) 3787 { 3788 size_t i; 3789 3790 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3791 3792 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3793 3794 /* Write MAC initialization values. */ 3795 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3796 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3797 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3798 rtl8188eu_mac[i].val); 3799 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3800 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3801 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3802 rtl8192eu_mac[i].val); 3803 } else { 3804 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3805 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3806 rtl8192cu_mac[i].val); 3807 } 3808 } 3809 3810 static void __noinline 3811 urtwn_bb_init(struct urtwn_softc *sc) 3812 { 3813 const struct rtwn_bb_prog *prog; 3814 uint32_t reg; 3815 uint8_t crystalcap; 3816 size_t i; 3817 3818 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3819 3820 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3821 3822 /* Enable BB and RF. */ 3823 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3824 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3825 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3826 R92C_SYS_FUNC_EN_DIO_RF); 3827 3828 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3829 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3830 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3831 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3832 } 3833 3834 urtwn_write_1(sc, R92C_RF_CTRL, 3835 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3836 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3837 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3838 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3839 3840 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3841 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3842 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3843 urtwn_write_1(sc, 0x15, 0xe9); 3844 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3845 } 3846 3847 /* Select BB programming based on board type. */ 3848 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3849 prog = &rtl8188eu_bb_prog; 3850 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3851 prog = &rtl8192eu_bb_prog; 3852 else if (!(sc->chip & URTWN_CHIP_92C)) { 3853 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3854 prog = &rtl8188ce_bb_prog; 3855 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3856 prog = &rtl8188ru_bb_prog; 3857 } else { 3858 prog = &rtl8188cu_bb_prog; 3859 } 3860 } else { 3861 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3862 prog = &rtl8192ce_bb_prog; 3863 } else { 3864 prog = &rtl8192cu_bb_prog; 3865 } 3866 } 3867 /* Write BB initialization values. */ 3868 for (i = 0; i < prog->count; i++) { 3869 /* additional delay depend on registers */ 3870 switch (prog->regs[i]) { 3871 case 0xfe: 3872 urtwn_delay_ms(sc, 50); 3873 break; 3874 case 0xfd: 3875 urtwn_delay_ms(sc, 5); 3876 break; 3877 case 0xfc: 3878 urtwn_delay_ms(sc, 1); 3879 break; 3880 case 0xfb: 3881 DELAY(50); 3882 break; 3883 case 0xfa: 3884 DELAY(5); 3885 break; 3886 case 0xf9: 3887 DELAY(1); 3888 break; 3889 } 3890 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3891 DELAY(1); 3892 } 3893 3894 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3895 /* 8192C 1T only configuration. */ 3896 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3897 reg = (reg & ~0x00000003) | 0x2; 3898 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3899 3900 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3901 reg = (reg & ~0x00300033) | 0x00200022; 3902 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3903 3904 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3905 reg = (reg & ~0xff000000) | (0x45 << 24); 3906 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3907 3908 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3909 reg = (reg & ~0x000000ff) | 0x23; 3910 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3911 3912 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3913 reg = (reg & ~0x00000030) | (1 << 4); 3914 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3915 3916 reg = urtwn_bb_read(sc, 0xe74); 3917 reg = (reg & ~0x0c000000) | (2 << 26); 3918 urtwn_bb_write(sc, 0xe74, reg); 3919 reg = urtwn_bb_read(sc, 0xe78); 3920 reg = (reg & ~0x0c000000) | (2 << 26); 3921 urtwn_bb_write(sc, 0xe78, reg); 3922 reg = urtwn_bb_read(sc, 0xe7c); 3923 reg = (reg & ~0x0c000000) | (2 << 26); 3924 urtwn_bb_write(sc, 0xe7c, reg); 3925 reg = urtwn_bb_read(sc, 0xe80); 3926 reg = (reg & ~0x0c000000) | (2 << 26); 3927 urtwn_bb_write(sc, 0xe80, reg); 3928 reg = urtwn_bb_read(sc, 0xe88); 3929 reg = (reg & ~0x0c000000) | (2 << 26); 3930 urtwn_bb_write(sc, 0xe88, reg); 3931 } 3932 3933 /* Write AGC values. */ 3934 for (i = 0; i < prog->agccount; i++) { 3935 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3936 DELAY(1); 3937 } 3938 3939 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3940 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3941 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3942 DELAY(1); 3943 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3944 DELAY(1); 3945 } 3946 3947 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3948 crystalcap = sc->r88e_rom[0xb9]; 3949 if (crystalcap == 0x00) 3950 crystalcap = 0x20; 3951 crystalcap &= 0x3f; 3952 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3953 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3954 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3955 crystalcap | crystalcap << 6)); 3956 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3957 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3958 crystalcap = sc->r88e_rom[0xb9]; 3959 if (crystalcap == 0xff) 3960 crystalcap = 0x20; 3961 crystalcap &= 0x3f; 3962 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3963 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3964 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3965 crystalcap | crystalcap << 6)); 3966 } else { 3967 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3968 R92C_HSSI_PARAM2_CCK_HIPWR) { 3969 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3970 } 3971 } 3972 } 3973 3974 static void __noinline 3975 urtwn_rf_init(struct urtwn_softc *sc) 3976 { 3977 const struct rtwn_rf_prog *prog; 3978 uint32_t reg, mask, saved; 3979 size_t i, j, idx; 3980 3981 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3982 3983 /* Select RF programming based on board type. */ 3984 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3985 prog = rtl8188eu_rf_prog; 3986 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3987 prog = rtl8192eu_rf_prog; 3988 else if (!(sc->chip & URTWN_CHIP_92C)) { 3989 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3990 prog = rtl8188ce_rf_prog; 3991 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3992 prog = rtl8188ru_rf_prog; 3993 } else { 3994 prog = rtl8188cu_rf_prog; 3995 } 3996 } else { 3997 prog = rtl8192ce_rf_prog; 3998 } 3999 4000 for (i = 0; i < sc->nrxchains; i++) { 4001 /* Save RF_ENV control type. */ 4002 idx = i / 2; 4003 mask = 0xffffU << ((i % 2) * 16); 4004 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4005 4006 /* Set RF_ENV enable. */ 4007 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4008 reg |= 0x100000; 4009 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4010 DELAY(50); 4011 4012 /* Set RF_ENV output high. */ 4013 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4014 reg |= 0x10; 4015 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4016 DELAY(50); 4017 4018 /* Set address and data lengths of RF registers. */ 4019 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4020 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4021 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4022 DELAY(50); 4023 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4024 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4025 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4026 DELAY(50); 4027 4028 /* Write RF initialization values for this chain. */ 4029 for (j = 0; j < prog[i].count; j++) { 4030 if (prog[i].regs[j] >= 0xf9 && 4031 prog[i].regs[j] <= 0xfe) { 4032 /* 4033 * These are fake RF registers offsets that 4034 * indicate a delay is required. 4035 */ 4036 urtwn_delay_ms(sc, 50); 4037 continue; 4038 } 4039 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4040 DELAY(5); 4041 } 4042 4043 /* Restore RF_ENV control type. */ 4044 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4045 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4046 } 4047 4048 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4049 URTWN_CHIP_UMC_A_CUT) { 4050 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4051 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4052 } 4053 4054 /* Cache RF register CHNLBW. */ 4055 for (i = 0; i < 2; i++) { 4056 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4057 } 4058 } 4059 4060 static void __noinline 4061 urtwn_cam_init(struct urtwn_softc *sc) 4062 { 4063 uint32_t content, command; 4064 uint8_t idx; 4065 size_t i; 4066 4067 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4068 4069 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4070 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4071 return; 4072 4073 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4074 content = (idx & 3) 4075 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4076 | R92C_CAM_VALID; 4077 4078 command = R92C_CAMCMD_POLLING 4079 | R92C_CAMCMD_WRITE 4080 | R92C_CAM_CTL0(idx); 4081 4082 urtwn_write_4(sc, R92C_CAMWRITE, content); 4083 urtwn_write_4(sc, R92C_CAMCMD, command); 4084 } 4085 4086 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4087 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4088 if (i == 0) { 4089 content = (idx & 3) 4090 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4091 | R92C_CAM_VALID; 4092 } else { 4093 content = 0; 4094 } 4095 4096 command = R92C_CAMCMD_POLLING 4097 | R92C_CAMCMD_WRITE 4098 | R92C_CAM_CTL0(idx) 4099 | i; 4100 4101 urtwn_write_4(sc, R92C_CAMWRITE, content); 4102 urtwn_write_4(sc, R92C_CAMCMD, command); 4103 } 4104 } 4105 4106 /* Invalidate all CAM entries. */ 4107 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4108 } 4109 4110 static void __noinline 4111 urtwn_pa_bias_init(struct urtwn_softc *sc) 4112 { 4113 uint8_t reg; 4114 size_t i; 4115 4116 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4117 4118 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4119 4120 for (i = 0; i < sc->nrxchains; i++) { 4121 if (sc->pa_setting & (1U << i)) 4122 continue; 4123 4124 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4125 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4126 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4127 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4128 } 4129 if (!(sc->pa_setting & 0x10)) { 4130 reg = urtwn_read_1(sc, 0x16); 4131 reg = (reg & ~0xf0) | 0x90; 4132 urtwn_write_1(sc, 0x16, reg); 4133 } 4134 } 4135 4136 static void __noinline 4137 urtwn_rxfilter_init(struct urtwn_softc *sc) 4138 { 4139 4140 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4141 4142 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4143 4144 /* Initialize Rx filter. */ 4145 /* TODO: use better filter for monitor mode. */ 4146 urtwn_write_4(sc, R92C_RCR, 4147 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4148 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4149 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4150 /* Accept all multicast frames. */ 4151 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4152 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4153 /* Accept all management frames. */ 4154 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4155 /* Reject all control frames. */ 4156 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4157 /* Accept all data frames. */ 4158 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4159 } 4160 4161 static void __noinline 4162 urtwn_edca_init(struct urtwn_softc *sc) 4163 { 4164 4165 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4166 4167 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4168 4169 /* set spec SIFS (used in NAV) */ 4170 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4171 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4172 4173 /* set SIFS CCK/OFDM */ 4174 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4175 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4176 4177 /* TXOP */ 4178 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4179 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4180 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4181 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4182 } 4183 4184 static void 4185 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4186 uint16_t power[URTWN_RIDX_COUNT]) 4187 { 4188 uint32_t reg; 4189 4190 URTWNHIST_FUNC(); 4191 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4192 4193 /* Write per-CCK rate Tx power. */ 4194 if (chain == 0) { 4195 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4196 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4197 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4198 4199 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4200 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4201 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4202 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4203 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4204 } else { 4205 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4206 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4207 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4208 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4209 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4210 4211 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4212 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4213 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4214 } 4215 /* Write per-OFDM rate Tx power. */ 4216 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4217 SM(R92C_TXAGC_RATE06, power[ 4]) | 4218 SM(R92C_TXAGC_RATE09, power[ 5]) | 4219 SM(R92C_TXAGC_RATE12, power[ 6]) | 4220 SM(R92C_TXAGC_RATE18, power[ 7])); 4221 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4222 SM(R92C_TXAGC_RATE24, power[ 8]) | 4223 SM(R92C_TXAGC_RATE36, power[ 9]) | 4224 SM(R92C_TXAGC_RATE48, power[10]) | 4225 SM(R92C_TXAGC_RATE54, power[11])); 4226 /* Write per-MCS Tx power. */ 4227 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4228 SM(R92C_TXAGC_MCS00, power[12]) | 4229 SM(R92C_TXAGC_MCS01, power[13]) | 4230 SM(R92C_TXAGC_MCS02, power[14]) | 4231 SM(R92C_TXAGC_MCS03, power[15])); 4232 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4233 SM(R92C_TXAGC_MCS04, power[16]) | 4234 SM(R92C_TXAGC_MCS05, power[17]) | 4235 SM(R92C_TXAGC_MCS06, power[18]) | 4236 SM(R92C_TXAGC_MCS07, power[19])); 4237 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4238 SM(R92C_TXAGC_MCS08, power[20]) | 4239 SM(R92C_TXAGC_MCS09, power[21]) | 4240 SM(R92C_TXAGC_MCS10, power[22]) | 4241 SM(R92C_TXAGC_MCS11, power[23])); 4242 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4243 SM(R92C_TXAGC_MCS12, power[24]) | 4244 SM(R92C_TXAGC_MCS13, power[25]) | 4245 SM(R92C_TXAGC_MCS14, power[26]) | 4246 SM(R92C_TXAGC_MCS15, power[27])); 4247 } 4248 4249 static void 4250 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4251 uint16_t power[URTWN_RIDX_COUNT]) 4252 { 4253 struct r92c_rom *rom = &sc->rom; 4254 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4255 const struct rtwn_txpwr *base; 4256 int ridx, group; 4257 4258 URTWNHIST_FUNC(); 4259 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4260 4261 /* Determine channel group. */ 4262 if (chan <= 3) { 4263 group = 0; 4264 } else if (chan <= 9) { 4265 group = 1; 4266 } else { 4267 group = 2; 4268 } 4269 4270 /* Get original Tx power based on board type and RF chain. */ 4271 if (!(sc->chip & URTWN_CHIP_92C)) { 4272 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4273 base = &rtl8188ru_txagc[chain]; 4274 } else { 4275 base = &rtl8192cu_txagc[chain]; 4276 } 4277 } else { 4278 base = &rtl8192cu_txagc[chain]; 4279 } 4280 4281 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4282 if (sc->regulatory == 0) { 4283 for (ridx = 0; ridx <= 3; ridx++) { 4284 power[ridx] = base->pwr[0][ridx]; 4285 } 4286 } 4287 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4288 if (sc->regulatory == 3) { 4289 power[ridx] = base->pwr[0][ridx]; 4290 /* Apply vendor limits. */ 4291 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4292 maxpow = rom->ht40_max_pwr[group]; 4293 } else { 4294 maxpow = rom->ht20_max_pwr[group]; 4295 } 4296 maxpow = (maxpow >> (chain * 4)) & 0xf; 4297 if (power[ridx] > maxpow) { 4298 power[ridx] = maxpow; 4299 } 4300 } else if (sc->regulatory == 1) { 4301 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4302 power[ridx] = base->pwr[group][ridx]; 4303 } 4304 } else if (sc->regulatory != 2) { 4305 power[ridx] = base->pwr[0][ridx]; 4306 } 4307 } 4308 4309 /* Compute per-CCK rate Tx power. */ 4310 cckpow = rom->cck_tx_pwr[chain][group]; 4311 for (ridx = 0; ridx <= 3; ridx++) { 4312 power[ridx] += cckpow; 4313 if (power[ridx] > R92C_MAX_TX_PWR) { 4314 power[ridx] = R92C_MAX_TX_PWR; 4315 } 4316 } 4317 4318 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4319 if (sc->ntxchains > 1) { 4320 /* Apply reduction for 2 spatial streams. */ 4321 diff = rom->ht40_2s_tx_pwr_diff[group]; 4322 diff = (diff >> (chain * 4)) & 0xf; 4323 htpow = (htpow > diff) ? htpow - diff : 0; 4324 } 4325 4326 /* Compute per-OFDM rate Tx power. */ 4327 diff = rom->ofdm_tx_pwr_diff[group]; 4328 diff = (diff >> (chain * 4)) & 0xf; 4329 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4330 for (ridx = 4; ridx <= 11; ridx++) { 4331 power[ridx] += ofdmpow; 4332 if (power[ridx] > R92C_MAX_TX_PWR) { 4333 power[ridx] = R92C_MAX_TX_PWR; 4334 } 4335 } 4336 4337 /* Compute per-MCS Tx power. */ 4338 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4339 diff = rom->ht20_tx_pwr_diff[group]; 4340 diff = (diff >> (chain * 4)) & 0xf; 4341 htpow += diff; /* HT40->HT20 correction. */ 4342 } 4343 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4344 power[ridx] += htpow; 4345 if (power[ridx] > R92C_MAX_TX_PWR) { 4346 power[ridx] = R92C_MAX_TX_PWR; 4347 } 4348 } 4349 #ifdef URTWN_DEBUG 4350 if (urtwn_debug & DBG_RF) { 4351 /* Dump per-rate Tx power values. */ 4352 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4353 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4354 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4355 } 4356 #endif 4357 } 4358 4359 void 4360 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4361 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4362 { 4363 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4364 const struct rtwn_r88e_txpwr *base; 4365 int ridx, group; 4366 4367 URTWNHIST_FUNC(); 4368 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4369 4370 /* Determine channel group. */ 4371 if (chan <= 2) 4372 group = 0; 4373 else if (chan <= 5) 4374 group = 1; 4375 else if (chan <= 8) 4376 group = 2; 4377 else if (chan <= 11) 4378 group = 3; 4379 else if (chan <= 13) 4380 group = 4; 4381 else 4382 group = 5; 4383 4384 /* Get original Tx power based on board type and RF chain. */ 4385 base = &rtl8188eu_txagc[chain]; 4386 4387 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4388 if (sc->regulatory == 0) { 4389 for (ridx = 0; ridx <= 3; ridx++) 4390 power[ridx] = base->pwr[0][ridx]; 4391 } 4392 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4393 if (sc->regulatory == 3) 4394 power[ridx] = base->pwr[0][ridx]; 4395 else if (sc->regulatory == 1) { 4396 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4397 power[ridx] = base->pwr[group][ridx]; 4398 } else if (sc->regulatory != 2) 4399 power[ridx] = base->pwr[0][ridx]; 4400 } 4401 4402 /* Compute per-CCK rate Tx power. */ 4403 cckpow = sc->cck_tx_pwr[group]; 4404 for (ridx = 0; ridx <= 3; ridx++) { 4405 power[ridx] += cckpow; 4406 if (power[ridx] > R92C_MAX_TX_PWR) 4407 power[ridx] = R92C_MAX_TX_PWR; 4408 } 4409 4410 htpow = sc->ht40_tx_pwr[group]; 4411 4412 /* Compute per-OFDM rate Tx power. */ 4413 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4414 for (ridx = 4; ridx <= 11; ridx++) { 4415 power[ridx] += ofdmpow; 4416 if (power[ridx] > R92C_MAX_TX_PWR) 4417 power[ridx] = R92C_MAX_TX_PWR; 4418 } 4419 4420 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4421 for (ridx = 12; ridx <= 27; ridx++) { 4422 power[ridx] += bw20pow; 4423 if (power[ridx] > R92C_MAX_TX_PWR) 4424 power[ridx] = R92C_MAX_TX_PWR; 4425 } 4426 } 4427 4428 static void 4429 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4430 { 4431 uint16_t power[URTWN_RIDX_COUNT]; 4432 size_t i; 4433 4434 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4435 4436 for (i = 0; i < sc->ntxchains; i++) { 4437 /* Compute per-rate Tx power values. */ 4438 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4439 ISSET(sc->chip, URTWN_CHIP_92EU)) 4440 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4441 else 4442 urtwn_get_txpower(sc, i, chan, ht40m, power); 4443 /* Write per-rate Tx power values to hardware. */ 4444 urtwn_write_txpower(sc, i, power); 4445 } 4446 } 4447 4448 static void __noinline 4449 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4450 { 4451 struct ieee80211com *ic = &sc->sc_ic; 4452 u_int chan; 4453 size_t i; 4454 4455 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4456 4457 URTWNHIST_FUNC(); 4458 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4459 4460 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4461 4462 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4463 chan += 2; 4464 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4465 chan -= 2; 4466 } 4467 4468 /* Set Tx power for this new channel. */ 4469 urtwn_set_txpower(sc, chan, ht40m); 4470 4471 for (i = 0; i < sc->nrxchains; i++) { 4472 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4473 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4474 } 4475 4476 if (ht40m) { 4477 /* Is secondary channel below or above primary? */ 4478 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4479 uint32_t reg; 4480 4481 urtwn_write_1(sc, R92C_BWOPMODE, 4482 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4483 4484 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4485 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4486 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4487 4488 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4489 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4490 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4491 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4492 4493 /* Set CCK side band. */ 4494 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4495 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4496 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4497 4498 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4499 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4500 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4501 4502 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4503 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4504 ~R92C_FPGA0_ANAPARAM2_CBW20); 4505 4506 reg = urtwn_bb_read(sc, 0x818); 4507 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4508 urtwn_bb_write(sc, 0x818, reg); 4509 4510 /* Select 40MHz bandwidth. */ 4511 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4512 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4513 } else { 4514 urtwn_write_1(sc, R92C_BWOPMODE, 4515 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4516 4517 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4518 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4519 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4520 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4521 4522 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4523 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4524 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4525 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4526 R92C_FPGA0_ANAPARAM2_CBW20); 4527 } 4528 4529 /* Select 20MHz bandwidth. */ 4530 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4531 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4532 (ISSET(sc->chip, URTWN_CHIP_88E) || 4533 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4534 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4535 } 4536 } 4537 4538 static void __noinline 4539 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4540 { 4541 4542 URTWNHIST_FUNC(); 4543 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4544 4545 uint32_t addaBackup[16], iqkBackup[4], piMode; 4546 4547 #ifdef notyet 4548 uint32_t odfm0_agccore_regs[3]; 4549 uint32_t ant_regs[3]; 4550 uint32_t rf_regs[8]; 4551 #endif 4552 uint32_t reg0, reg1, reg2; 4553 int i, attempt; 4554 4555 #ifdef notyet 4556 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4557 R92E_STBC_SETTING + 2)); 4558 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4559 /* Save AGCCORE regs. */ 4560 for (i = 0; i < sc->nrxchains; i++) { 4561 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4562 R92C_OFDM0_AGCCORE1(i)); 4563 } 4564 #endif 4565 /* Save BB regs. */ 4566 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4567 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4568 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4569 4570 /* Save adda regs to be restored when finished. */ 4571 for (i = 0; i < __arraycount(addaReg); i++) 4572 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4573 /* Save mac regs. */ 4574 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4575 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4576 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4577 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4578 4579 #ifdef notyet 4580 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4581 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4582 4583 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4584 for (i = 0; i < sc->nrxchains; i++) 4585 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4586 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4587 #endif 4588 4589 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4590 R92C_HSSI_PARAM1_PI); 4591 if (piMode == 0) { 4592 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4593 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4594 R92C_HSSI_PARAM1_PI); 4595 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4596 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4597 R92C_HSSI_PARAM1_PI); 4598 } 4599 4600 attempt = 1; 4601 4602 next_attempt: 4603 4604 /* Set mac regs for calibration. */ 4605 for (i = 0; i < __arraycount(addaReg); i++) { 4606 urtwn_bb_write(sc, addaReg[i], 4607 addaReg[__arraycount(addaReg) - 1]); 4608 } 4609 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4610 R92C_CCK0_AFESETTING)); 4611 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4612 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4613 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4614 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4615 4616 if (sc->ntxchains > 1) 4617 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4618 4619 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4620 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4621 ~R92C_BCN_CTRL_EN_BCN)); 4622 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4623 ~R92C_BCN_CTRL_EN_BCN)); 4624 4625 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4626 ~R92C_GPIO_MUXCFG_ENBT)); 4627 4628 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4629 4630 if (sc->ntxchains > 1) 4631 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4632 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4633 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4634 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4635 4636 /* Restore BB regs. */ 4637 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4638 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4639 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4640 4641 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4642 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4643 if (sc->nrxchains > 1) 4644 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4645 4646 if (attempt-- > 0) 4647 goto next_attempt; 4648 4649 /* Restore mode. */ 4650 if (piMode == 0) { 4651 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4652 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4653 ~R92C_HSSI_PARAM1_PI); 4654 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4655 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4656 ~R92C_HSSI_PARAM1_PI); 4657 } 4658 4659 #ifdef notyet 4660 for (i = 0; i < sc->nrxchains; i++) { 4661 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4662 odfm0_agccore_regs[i]); 4663 } 4664 #endif 4665 4666 /* Restore adda regs. */ 4667 for (i = 0; i < __arraycount(addaReg); i++) 4668 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4669 /* Restore mac regs. */ 4670 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4671 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4672 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4673 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4674 4675 #ifdef notyet 4676 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4677 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4678 4679 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4680 for (i = 0; i < sc->nrxchains; i++) 4681 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4682 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4683 #endif 4684 } 4685 4686 static void 4687 urtwn_lc_calib(struct urtwn_softc *sc) 4688 { 4689 uint32_t rf_ac[2]; 4690 uint8_t txmode; 4691 size_t i; 4692 4693 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4694 4695 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4696 4697 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4698 if ((txmode & 0x70) != 0) { 4699 /* Disable all continuous Tx. */ 4700 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4701 4702 /* Set RF mode to standby mode. */ 4703 for (i = 0; i < sc->nrxchains; i++) { 4704 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4705 urtwn_rf_write(sc, i, R92C_RF_AC, 4706 RW(rf_ac[i], R92C_RF_AC_MODE, 4707 R92C_RF_AC_MODE_STANDBY)); 4708 } 4709 } else { 4710 /* Block all Tx queues. */ 4711 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4712 } 4713 /* Start calibration. */ 4714 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4715 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4716 4717 /* Give calibration the time to complete. */ 4718 urtwn_delay_ms(sc, 100); 4719 4720 /* Restore configuration. */ 4721 if ((txmode & 0x70) != 0) { 4722 /* Restore Tx mode. */ 4723 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4724 /* Restore RF mode. */ 4725 for (i = 0; i < sc->nrxchains; i++) { 4726 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4727 } 4728 } else { 4729 /* Unblock all Tx queues. */ 4730 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4731 } 4732 } 4733 4734 static void 4735 urtwn_temp_calib(struct urtwn_softc *sc) 4736 { 4737 int temp, t_meter_reg; 4738 4739 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4740 4741 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4742 4743 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4744 t_meter_reg = R92C_RF_T_METER; 4745 else 4746 t_meter_reg = R92E_RF_T_METER; 4747 4748 if (sc->thcal_state == 0) { 4749 /* Start measuring temperature. */ 4750 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4751 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4752 sc->thcal_state = 1; 4753 return; 4754 } 4755 sc->thcal_state = 0; 4756 4757 /* Read measured temperature. */ 4758 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4759 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4760 if (temp == 0) /* Read failed, skip. */ 4761 return; 4762 4763 /* 4764 * Redo LC calibration if temperature changed significantly since 4765 * last calibration. 4766 */ 4767 if (sc->thcal_lctemp == 0) { 4768 /* First LC calibration is performed in urtwn_init(). */ 4769 sc->thcal_lctemp = temp; 4770 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4771 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4772 sc->thcal_lctemp, temp, 0, 0); 4773 urtwn_lc_calib(sc); 4774 /* Record temperature of last LC calibration. */ 4775 sc->thcal_lctemp = temp; 4776 } 4777 } 4778 4779 static int 4780 urtwn_init(struct ifnet *ifp) 4781 { 4782 struct urtwn_softc *sc = ifp->if_softc; 4783 struct ieee80211com *ic = &sc->sc_ic; 4784 struct urtwn_rx_data *data; 4785 uint32_t reg; 4786 size_t i; 4787 int error; 4788 4789 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4790 4791 urtwn_stop(ifp, 0); 4792 4793 mutex_enter(&sc->sc_write_mtx); 4794 4795 mutex_enter(&sc->sc_task_mtx); 4796 /* Init host async commands ring. */ 4797 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4798 mutex_exit(&sc->sc_task_mtx); 4799 4800 mutex_enter(&sc->sc_fwcmd_mtx); 4801 /* Init firmware commands ring. */ 4802 sc->fwcur = 0; 4803 mutex_exit(&sc->sc_fwcmd_mtx); 4804 4805 /* Allocate Tx/Rx buffers. */ 4806 error = urtwn_alloc_rx_list(sc); 4807 if (error != 0) { 4808 aprint_error_dev(sc->sc_dev, 4809 "could not allocate Rx buffers\n"); 4810 goto fail; 4811 } 4812 error = urtwn_alloc_tx_list(sc); 4813 if (error != 0) { 4814 aprint_error_dev(sc->sc_dev, 4815 "could not allocate Tx buffers\n"); 4816 goto fail; 4817 } 4818 4819 /* Power on adapter. */ 4820 error = urtwn_power_on(sc); 4821 if (error != 0) 4822 goto fail; 4823 4824 /* Initialize DMA. */ 4825 error = urtwn_dma_init(sc); 4826 if (error != 0) 4827 goto fail; 4828 4829 /* Set info size in Rx descriptors (in 64-bit words). */ 4830 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4831 4832 /* Init interrupts. */ 4833 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4834 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4835 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4836 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4837 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4838 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4839 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4840 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4841 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4842 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4843 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4844 } 4845 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4846 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4847 } else { 4848 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4849 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4850 } 4851 4852 /* Set MAC address. */ 4853 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4854 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4855 4856 /* Set initial network type. */ 4857 reg = urtwn_read_4(sc, R92C_CR); 4858 switch (ic->ic_opmode) { 4859 case IEEE80211_M_STA: 4860 default: 4861 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4862 break; 4863 4864 case IEEE80211_M_IBSS: 4865 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4866 break; 4867 } 4868 urtwn_write_4(sc, R92C_CR, reg); 4869 4870 /* Set response rate */ 4871 reg = urtwn_read_4(sc, R92C_RRSR); 4872 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4873 urtwn_write_4(sc, R92C_RRSR, reg); 4874 4875 /* SIFS (used in NAV) */ 4876 urtwn_write_2(sc, R92C_SPEC_SIFS, 4877 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4878 4879 /* Set short/long retry limits. */ 4880 urtwn_write_2(sc, R92C_RL, 4881 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4882 4883 /* Initialize EDCA parameters. */ 4884 urtwn_edca_init(sc); 4885 4886 /* Setup rate fallback. */ 4887 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4888 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4889 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4890 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4891 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4892 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4893 } 4894 4895 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4896 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4897 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4898 /* Set ACK timeout. */ 4899 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4900 4901 /* Setup USB aggregation. */ 4902 /* Tx */ 4903 reg = urtwn_read_4(sc, R92C_TDECTRL); 4904 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4905 urtwn_write_4(sc, R92C_TDECTRL, reg); 4906 /* Rx */ 4907 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4908 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4909 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4910 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4911 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4912 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4913 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4914 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4915 ISSET(sc->chip, URTWN_CHIP_92EU)) 4916 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4917 else 4918 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4919 4920 /* Initialize beacon parameters. */ 4921 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4922 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4923 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4924 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4925 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4926 4927 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4928 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4929 /* Setup AMPDU aggregation. */ 4930 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4931 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4932 urtwn_write_2(sc, 0x4ca, 0x0708); 4933 4934 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4935 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4936 } 4937 4938 /* Load 8051 microcode. */ 4939 error = urtwn_load_firmware(sc); 4940 if (error != 0) 4941 goto fail; 4942 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4943 4944 /* Initialize MAC/BB/RF blocks. */ 4945 /* 4946 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4947 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4948 * XXX: This setting should be removed from rtl8192cu_mac[]. 4949 */ 4950 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4951 urtwn_rxfilter_init(sc); // reset R92C_RCR 4952 urtwn_bb_init(sc); 4953 urtwn_rf_init(sc); 4954 4955 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4956 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4957 urtwn_write_2(sc, R92C_CR, 4958 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4959 R92C_CR_MACRXEN); 4960 } 4961 4962 /* Turn CCK and OFDM blocks on. */ 4963 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4964 reg |= R92C_RFMOD_CCK_EN; 4965 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4966 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4967 reg |= R92C_RFMOD_OFDM_EN; 4968 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4969 4970 /* Clear per-station keys table. */ 4971 urtwn_cam_init(sc); 4972 4973 /* Enable hardware sequence numbering. */ 4974 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4975 4976 /* Perform LO and IQ calibrations. */ 4977 urtwn_iq_calib(sc, sc->iqk_inited); 4978 sc->iqk_inited = true; 4979 4980 /* Perform LC calibration. */ 4981 urtwn_lc_calib(sc); 4982 4983 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4984 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4985 /* Fix USB interference issue. */ 4986 urtwn_write_1(sc, 0xfe40, 0xe0); 4987 urtwn_write_1(sc, 0xfe41, 0x8d); 4988 urtwn_write_1(sc, 0xfe42, 0x80); 4989 urtwn_write_4(sc, 0x20c, 0xfd0320); 4990 4991 urtwn_pa_bias_init(sc); 4992 } 4993 4994 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4995 !(sc->chip & URTWN_CHIP_92EU)) { 4996 /* 1T1R */ 4997 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4998 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4999 } 5000 5001 /* Initialize GPIO setting. */ 5002 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5003 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5004 5005 /* Fix for lower temperature. */ 5006 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5007 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5008 urtwn_write_1(sc, 0x15, 0xe9); 5009 5010 /* Set default channel. */ 5011 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5012 5013 /* Queue Rx xfers. */ 5014 for (size_t j = 0; j < sc->rx_npipe; j++) { 5015 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5016 data = &sc->rx_data[j][i]; 5017 usbd_setup_xfer(data->xfer, data, data->buf, 5018 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5019 urtwn_rxeof); 5020 error = usbd_transfer(data->xfer); 5021 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5022 error != USBD_IN_PROGRESS)) 5023 goto fail; 5024 } 5025 } 5026 5027 /* We're ready to go. */ 5028 ifp->if_flags &= ~IFF_OACTIVE; 5029 ifp->if_flags |= IFF_RUNNING; 5030 sc->sc_running = true; 5031 5032 mutex_exit(&sc->sc_write_mtx); 5033 5034 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5035 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5036 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5037 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5038 urtwn_wait_async(sc); 5039 5040 return 0; 5041 5042 fail: 5043 mutex_exit(&sc->sc_write_mtx); 5044 5045 urtwn_stop(ifp, 1); 5046 return error; 5047 } 5048 5049 static void __noinline 5050 urtwn_stop(struct ifnet *ifp, int disable) 5051 { 5052 struct urtwn_softc *sc = ifp->if_softc; 5053 struct ieee80211com *ic = &sc->sc_ic; 5054 size_t i; 5055 int s; 5056 5057 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5058 5059 s = splusb(); 5060 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5061 urtwn_wait_async(sc); 5062 splx(s); 5063 5064 sc->tx_timer = 0; 5065 ifp->if_timer = 0; 5066 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5067 5068 callout_stop(&sc->sc_scan_to); 5069 callout_stop(&sc->sc_calib_to); 5070 5071 /* Abort Tx. */ 5072 for (i = 0; i < sc->tx_npipe; i++) { 5073 if (sc->tx_pipe[i] != NULL) 5074 usbd_abort_pipe(sc->tx_pipe[i]); 5075 } 5076 5077 /* Stop Rx pipe. */ 5078 for (i = 0; i < sc->rx_npipe; i++) { 5079 if (sc->rx_pipe[i] != NULL) 5080 usbd_abort_pipe(sc->rx_pipe[i]); 5081 } 5082 5083 /* Free Tx/Rx buffers. */ 5084 urtwn_free_tx_list(sc); 5085 urtwn_free_rx_list(sc); 5086 5087 sc->sc_running = false; 5088 if (disable) 5089 urtwn_chip_stop(sc); 5090 } 5091 5092 static int 5093 urtwn_reset(struct ifnet *ifp) 5094 { 5095 struct urtwn_softc *sc = ifp->if_softc; 5096 struct ieee80211com *ic = &sc->sc_ic; 5097 5098 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5099 return ENETRESET; 5100 5101 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5102 5103 return 0; 5104 } 5105 5106 static void 5107 urtwn_chip_stop(struct urtwn_softc *sc) 5108 { 5109 uint32_t reg; 5110 bool disabled = true; 5111 5112 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5113 5114 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5115 ISSET(sc->chip, URTWN_CHIP_92EU)) 5116 return; 5117 5118 mutex_enter(&sc->sc_write_mtx); 5119 5120 /* 5121 * RF Off Sequence 5122 */ 5123 /* Pause MAC TX queue */ 5124 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5125 5126 /* Disable RF */ 5127 urtwn_rf_write(sc, 0, 0, 0); 5128 5129 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5130 5131 /* Reset BB state machine */ 5132 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5133 R92C_SYS_FUNC_EN_USBD | 5134 R92C_SYS_FUNC_EN_USBA | 5135 R92C_SYS_FUNC_EN_BB_GLB_RST); 5136 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5137 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5138 5139 /* 5140 * Reset digital sequence 5141 */ 5142 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5143 /* Reset MCU ready status */ 5144 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5145 /* If firmware in ram code, do reset */ 5146 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5147 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5148 ISSET(sc->chip, URTWN_CHIP_92EU)) 5149 urtwn_r88e_fw_reset(sc); 5150 else 5151 urtwn_fw_reset(sc); 5152 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5153 } 5154 } 5155 5156 /* Reset MAC and Enable 8051 */ 5157 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5158 5159 /* Reset MCU ready status */ 5160 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5161 5162 if (disabled) { 5163 /* Disable MAC clock */ 5164 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5165 /* Disable AFE PLL */ 5166 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5167 /* Gated AFE DIG_CLOCK */ 5168 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5169 /* Isolated digital to PON */ 5170 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5171 } 5172 5173 /* 5174 * Pull GPIO PIN to balance level and LED control 5175 */ 5176 /* 1. Disable GPIO[7:0] */ 5177 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5178 5179 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5180 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5181 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5182 5183 /* Disable GPIO[10:8] */ 5184 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5185 5186 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5187 reg |= (((reg & 0x000f) << 4) | 0x0780); 5188 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5189 5190 /* Disable LED0 & 1 */ 5191 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5192 5193 /* 5194 * Reset digital sequence 5195 */ 5196 if (disabled) { 5197 /* Disable ELDR clock */ 5198 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5199 /* Isolated ELDR to PON */ 5200 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5201 } 5202 5203 /* 5204 * Disable analog sequence 5205 */ 5206 if (disabled) { 5207 /* Disable A15 power */ 5208 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5209 /* Disable digital core power */ 5210 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5211 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5212 ~R92C_LDOV12D_CTRL_LDV12_EN); 5213 } 5214 5215 /* Enter PFM mode */ 5216 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5217 5218 /* Set USB suspend */ 5219 urtwn_write_2(sc, R92C_APS_FSMCO, 5220 R92C_APS_FSMCO_APDM_HOST | 5221 R92C_APS_FSMCO_AFSM_HSUS | 5222 R92C_APS_FSMCO_PFM_ALDN); 5223 5224 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5225 5226 mutex_exit(&sc->sc_write_mtx); 5227 } 5228 5229 static void 5230 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5231 { 5232 if (sc->sc_running == false) 5233 DELAY(ms * 1000); 5234 else 5235 usbd_delay_ms(sc->sc_udev, ms); 5236 } 5237 5238 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5239 5240 #ifdef _MODULE 5241 #include "ioconf.c" 5242 #endif 5243 5244 static int 5245 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5246 { 5247 int error = 0; 5248 5249 switch (cmd) { 5250 case MODULE_CMD_INIT: 5251 #ifdef _MODULE 5252 error = config_init_component(cfdriver_ioconf_urtwn, 5253 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5254 #endif 5255 return error; 5256 case MODULE_CMD_FINI: 5257 #ifdef _MODULE 5258 error = config_fini_component(cfdriver_ioconf_urtwn, 5259 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5260 #endif 5261 return error; 5262 default: 5263 return ENOTTY; 5264 } 5265 } 5266
Indexes created Thu Oct 02 14:10:14 GMT 2025