if_urtwn.c revision 1.105.4.2
1 /* $NetBSD: if_urtwn.c,v 1.105.4.2 2024/06/20 17:52:12 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.105.4.2 2024/06/20 17:52:12 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(TRENDNET, TEW648UBM), 207 URTWN_DEV(ZYXEL, RTL8192CU), 208 209 /* URTWN_RTL8188E */ 210 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 211 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 212 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 213 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 214 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 215 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 216 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 217 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 218 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 219 220 /* URTWN_RTL8192EU */ 221 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 222 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 223 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 224 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 225 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 226 }; 227 #undef URTWN_DEV 228 #undef URTWN_RTL8188E_DEV 229 #undef URTWN_RTL8192EU_DEV 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct urtwn_softc *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 289 int); 290 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_ioctl(struct ifnet *, u_long, void *); 306 static int urtwn_r92c_power_on(struct urtwn_softc *); 307 static int urtwn_r92e_power_on(struct urtwn_softc *); 308 static int urtwn_r88e_power_on(struct urtwn_softc *); 309 static int urtwn_llt_init(struct urtwn_softc *); 310 static void urtwn_fw_reset(struct urtwn_softc *); 311 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 312 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 313 static int urtwn_load_firmware(struct urtwn_softc *); 314 static int urtwn_r92c_dma_init(struct urtwn_softc *); 315 static int urtwn_r88e_dma_init(struct urtwn_softc *); 316 static void urtwn_mac_init(struct urtwn_softc *); 317 static void urtwn_bb_init(struct urtwn_softc *); 318 static void urtwn_rf_init(struct urtwn_softc *); 319 static void urtwn_cam_init(struct urtwn_softc *); 320 static void urtwn_pa_bias_init(struct urtwn_softc *); 321 static void urtwn_rxfilter_init(struct urtwn_softc *); 322 static void urtwn_edca_init(struct urtwn_softc *); 323 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 324 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 325 uint16_t[]); 326 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 327 u_int, uint16_t[]); 328 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 329 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 330 u_int); 331 static void urtwn_iq_calib(struct urtwn_softc *, bool); 332 static void urtwn_lc_calib(struct urtwn_softc *); 333 static void urtwn_temp_calib(struct urtwn_softc *); 334 static int urtwn_init(struct ifnet *); 335 static void urtwn_stop(struct ifnet *, int); 336 static int urtwn_reset(struct ifnet *); 337 static void urtwn_chip_stop(struct urtwn_softc *); 338 static void urtwn_newassoc(struct ieee80211_node *, int); 339 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 340 341 /* Aliases. */ 342 #define urtwn_bb_write urtwn_write_4 343 #define urtwn_bb_read urtwn_read_4 344 345 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 346 347 static const uint16_t addaReg[] = { 348 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 349 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 350 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 351 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 352 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 353 }; 354 355 static int 356 urtwn_match(device_t parent, cfdata_t match, void *aux) 357 { 358 struct usb_attach_arg *uaa = aux; 359 360 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 361 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 362 } 363 364 static void 365 urtwn_attach(device_t parent, device_t self, void *aux) 366 { 367 struct urtwn_softc *sc = device_private(self); 368 struct ieee80211com *ic = &sc->sc_ic; 369 struct ifnet *ifp = &sc->sc_if; 370 struct usb_attach_arg *uaa = aux; 371 char *devinfop; 372 const struct urtwn_dev *dev; 373 usb_device_request_t req; 374 size_t i; 375 int error; 376 377 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 378 379 sc->sc_dev = self; 380 sc->sc_udev = uaa->uaa_device; 381 382 sc->chip = 0; 383 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 384 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 385 SET(sc->chip, URTWN_CHIP_88E); 386 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 387 SET(sc->chip, URTWN_CHIP_92EU); 388 389 aprint_naive("\n"); 390 aprint_normal("\n"); 391 392 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 393 aprint_normal_dev(self, "%s\n", devinfop); 394 usbd_devinfo_free(devinfop); 395 396 req.bmRequestType = UT_WRITE_DEVICE; 397 req.bRequest = UR_SET_FEATURE; 398 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 399 USETW(req.wIndex, UHF_PORT_SUSPEND); 400 USETW(req.wLength, 0); 401 402 (void) usbd_do_request(sc->sc_udev, &req, 0); 403 404 cv_init(&sc->sc_task_cv, "urtwntsk"); 405 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 406 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 407 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 408 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 409 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 410 411 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 412 413 callout_init(&sc->sc_scan_to, 0); 414 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 415 callout_init(&sc->sc_calib_to, 0); 416 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 417 418 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 419 RND_TYPE_NET, RND_FLAG_DEFAULT); 420 421 error = usbd_set_config_no(sc->sc_udev, 1, 0); 422 if (error != 0) { 423 aprint_error_dev(self, "failed to set configuration" 424 ", err=%s\n", usbd_errstr(error)); 425 goto fail; 426 } 427 428 /* Get the first interface handle. */ 429 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 430 if (error != 0) { 431 aprint_error_dev(self, "could not get interface handle\n"); 432 goto fail; 433 } 434 435 error = urtwn_read_chipid(sc); 436 if (error != 0) { 437 aprint_error_dev(self, "unsupported test chip\n"); 438 goto fail; 439 } 440 441 /* Determine number of Tx/Rx chains. */ 442 if (sc->chip & URTWN_CHIP_92C) { 443 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 444 sc->nrxchains = 2; 445 } else if (sc->chip & URTWN_CHIP_92EU) { 446 sc->ntxchains = 2; 447 sc->nrxchains = 2; 448 } else { 449 sc->ntxchains = 1; 450 sc->nrxchains = 1; 451 } 452 453 if (ISSET(sc->chip, URTWN_CHIP_88E) || 454 ISSET(sc->chip, URTWN_CHIP_92EU)) 455 urtwn_r88e_read_rom(sc); 456 else 457 urtwn_read_rom(sc); 458 459 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 460 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 461 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 462 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 463 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 464 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 465 "8188CUS", sc->ntxchains, sc->nrxchains, 466 ether_sprintf(ic->ic_myaddr)); 467 468 error = urtwn_open_pipes(sc); 469 if (error != 0) { 470 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 471 goto fail; 472 } 473 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 474 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 475 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 476 477 /* 478 * Setup the 802.11 device. 479 */ 480 ic->ic_ifp = ifp; 481 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 482 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 483 ic->ic_state = IEEE80211_S_INIT; 484 485 /* Set device capabilities. */ 486 ic->ic_caps = 487 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 488 IEEE80211_C_IBSS | /* IBSS mode supported */ 489 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 490 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 491 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 492 IEEE80211_C_WME | /* 802.11e */ 493 IEEE80211_C_WPA; /* 802.11i */ 494 495 /* Set supported .11b and .11g rates. */ 496 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 497 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 498 499 /* Set supported .11b and .11g channels (1 through 14). */ 500 for (i = 1; i <= 14; i++) { 501 ic->ic_channels[i].ic_freq = 502 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 503 ic->ic_channels[i].ic_flags = 504 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 505 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 506 } 507 508 ifp->if_softc = sc; 509 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 510 ifp->if_init = urtwn_init; 511 ifp->if_ioctl = urtwn_ioctl; 512 ifp->if_start = urtwn_start; 513 ifp->if_watchdog = urtwn_watchdog; 514 IFQ_SET_READY(&ifp->if_snd); 515 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 516 517 if_initialize(ifp); 518 ieee80211_ifattach(ic); 519 520 /* override default methods */ 521 ic->ic_newassoc = urtwn_newassoc; 522 ic->ic_reset = urtwn_reset; 523 ic->ic_wme.wme_update = urtwn_wme_update; 524 525 /* Override state transition machine. */ 526 sc->sc_newstate = ic->ic_newstate; 527 ic->ic_newstate = urtwn_newstate; 528 529 /* XXX media locking needs revisiting */ 530 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 531 ieee80211_media_init_with_lock(ic, 532 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 533 534 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 535 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 536 &sc->sc_drvbpf); 537 538 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 539 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 540 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 541 542 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 543 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 544 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 545 546 ifp->if_percpuq = if_percpuq_create(ifp); 547 if_register(ifp); 548 549 ieee80211_announce(ic); 550 551 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 552 553 if (!pmf_device_register(self, NULL, NULL)) 554 aprint_error_dev(self, "couldn't establish power handler\n"); 555 556 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 557 return; 558 559 fail: 560 sc->sc_dying = 1; 561 aprint_error_dev(self, "attach failed\n"); 562 } 563 564 static int 565 urtwn_detach(device_t self, int flags) 566 { 567 struct urtwn_softc *sc = device_private(self); 568 struct ifnet *ifp = &sc->sc_if; 569 int s; 570 571 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 572 573 pmf_device_deregister(self); 574 575 s = splusb(); 576 577 sc->sc_dying = 1; 578 579 callout_halt(&sc->sc_scan_to, NULL); 580 callout_halt(&sc->sc_calib_to, NULL); 581 582 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 583 urtwn_stop(ifp, 0); 584 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 585 NULL); 586 587 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 588 bpf_detach(ifp); 589 ieee80211_ifdetach(&sc->sc_ic); 590 if_detach(ifp); 591 592 mutex_destroy(&sc->sc_media_mtx); 593 594 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 595 urtwn_close_pipes(sc); 596 } 597 598 splx(s); 599 600 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 601 602 rnd_detach_source(&sc->rnd_source); 603 604 callout_destroy(&sc->sc_scan_to); 605 callout_destroy(&sc->sc_calib_to); 606 607 cv_destroy(&sc->sc_task_cv); 608 mutex_destroy(&sc->sc_write_mtx); 609 mutex_destroy(&sc->sc_fwcmd_mtx); 610 mutex_destroy(&sc->sc_tx_mtx); 611 mutex_destroy(&sc->sc_rx_mtx); 612 mutex_destroy(&sc->sc_task_mtx); 613 614 return 0; 615 } 616 617 static int 618 urtwn_activate(device_t self, enum devact act) 619 { 620 struct urtwn_softc *sc = device_private(self); 621 622 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 623 624 switch (act) { 625 case DVACT_DEACTIVATE: 626 if_deactivate(sc->sc_ic.ic_ifp); 627 return 0; 628 default: 629 return EOPNOTSUPP; 630 } 631 } 632 633 static int 634 urtwn_open_pipes(struct urtwn_softc *sc) 635 { 636 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 637 static uint8_t epaddr[R92C_MAX_EPOUT]; 638 static uint8_t rxepaddr[R92C_MAX_EPIN]; 639 usb_interface_descriptor_t *id; 640 usb_endpoint_descriptor_t *ed; 641 size_t i, ntx = 0, nrx = 0; 642 int error; 643 644 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 645 646 /* Determine the number of bulk-out pipes. */ 647 id = usbd_get_interface_descriptor(sc->sc_iface); 648 for (i = 0; i < id->bNumEndpoints; i++) { 649 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 650 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 651 continue; 652 } 653 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 654 if (ntx < sizeof(epaddr)) 655 epaddr[ntx] = ed->bEndpointAddress; 656 ntx++; 657 } 658 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 659 if (nrx < sizeof(rxepaddr)) 660 rxepaddr[nrx] = ed->bEndpointAddress; 661 nrx++; 662 } 663 } 664 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 665 aprint_error_dev(sc->sc_dev, 666 "%zd: invalid number of Rx bulk pipes\n", nrx); 667 return EIO; 668 } 669 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 670 aprint_error_dev(sc->sc_dev, 671 "%zd: invalid number of Tx bulk pipes\n", ntx); 672 return EIO; 673 } 674 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 675 nrx, ntx, 0, 0); 676 sc->rx_npipe = nrx; 677 sc->tx_npipe = ntx; 678 679 /* Open bulk-in pipe at address 0x81. */ 680 for (i = 0; i < nrx; i++) { 681 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 682 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 683 if (error != 0) { 684 aprint_error_dev(sc->sc_dev, 685 "could not open Rx bulk pipe 0x%02x: %d\n", 686 rxepaddr[i], error); 687 goto fail; 688 } 689 } 690 691 /* Open bulk-out pipes (up to 3). */ 692 for (i = 0; i < ntx; i++) { 693 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 694 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 695 if (error != 0) { 696 aprint_error_dev(sc->sc_dev, 697 "could not open Tx bulk pipe 0x%02x: %d\n", 698 epaddr[i], error); 699 goto fail; 700 } 701 } 702 703 /* Map 802.11 access categories to USB pipes. */ 704 sc->ac2idx[WME_AC_BK] = 705 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 706 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 707 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 708 709 fail: 710 if (error != 0) 711 urtwn_close_pipes(sc); 712 return error; 713 } 714 715 static void 716 urtwn_close_pipes(struct urtwn_softc *sc) 717 { 718 struct usbd_pipe *pipe; 719 size_t i; 720 721 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 722 723 /* Close Rx pipes. */ 724 CTASSERT(sizeof(pipe) == sizeof(void *)); 725 for (i = 0; i < sc->rx_npipe; i++) { 726 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 727 if (pipe != NULL) { 728 usbd_close_pipe(pipe); 729 } 730 } 731 732 /* Close Tx pipes. */ 733 for (i = 0; i < sc->tx_npipe; i++) { 734 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 735 if (pipe != NULL) { 736 usbd_close_pipe(pipe); 737 } 738 } 739 } 740 741 static int __noinline 742 urtwn_alloc_rx_list(struct urtwn_softc *sc) 743 { 744 struct urtwn_rx_data *data; 745 size_t i; 746 int error = 0; 747 748 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 749 750 for (size_t j = 0; j < sc->rx_npipe; j++) { 751 TAILQ_INIT(&sc->rx_free_list[j]); 752 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 753 data = &sc->rx_data[j][i]; 754 755 data->sc = sc; /* Backpointer for callbacks. */ 756 757 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 758 0, 0, &data->xfer); 759 if (error) { 760 aprint_error_dev(sc->sc_dev, 761 "could not allocate xfer\n"); 762 break; 763 } 764 765 data->buf = usbd_get_buffer(data->xfer); 766 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 767 } 768 } 769 if (error != 0) 770 urtwn_free_rx_list(sc); 771 return error; 772 } 773 774 static void 775 urtwn_free_rx_list(struct urtwn_softc *sc) 776 { 777 struct usbd_xfer *xfer; 778 size_t i; 779 780 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 781 782 /* NB: Caller must abort pipe first. */ 783 for (size_t j = 0; j < sc->rx_npipe; j++) { 784 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 785 CTASSERT(sizeof(xfer) == sizeof(void *)); 786 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 787 if (xfer != NULL) 788 usbd_destroy_xfer(xfer); 789 } 790 } 791 } 792 793 static int __noinline 794 urtwn_alloc_tx_list(struct urtwn_softc *sc) 795 { 796 struct urtwn_tx_data *data; 797 size_t i; 798 int error = 0; 799 800 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 801 802 mutex_enter(&sc->sc_tx_mtx); 803 for (size_t j = 0; j < sc->tx_npipe; j++) { 804 TAILQ_INIT(&sc->tx_free_list[j]); 805 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 806 data = &sc->tx_data[j][i]; 807 808 data->sc = sc; /* Backpointer for callbacks. */ 809 data->pidx = j; 810 811 error = usbd_create_xfer(sc->tx_pipe[j], 812 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 813 &data->xfer); 814 if (error) { 815 aprint_error_dev(sc->sc_dev, 816 "could not allocate xfer\n"); 817 goto fail; 818 } 819 820 data->buf = usbd_get_buffer(data->xfer); 821 822 /* Append this Tx buffer to our free list. */ 823 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 824 } 825 } 826 mutex_exit(&sc->sc_tx_mtx); 827 return 0; 828 829 fail: 830 urtwn_free_tx_list(sc); 831 mutex_exit(&sc->sc_tx_mtx); 832 return error; 833 } 834 835 static void 836 urtwn_free_tx_list(struct urtwn_softc *sc) 837 { 838 struct usbd_xfer *xfer; 839 size_t i; 840 841 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 842 843 /* NB: Caller must abort pipe first. */ 844 for (size_t j = 0; j < sc->tx_npipe; j++) { 845 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 846 CTASSERT(sizeof(xfer) == sizeof(void *)); 847 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 848 if (xfer != NULL) 849 usbd_destroy_xfer(xfer); 850 } 851 } 852 } 853 854 static int 855 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 856 struct ieee80211_node *ni) 857 { 858 struct urtwn_tx_data *data = 859 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 860 861 if (data == NULL) 862 return ENOBUFS; 863 864 return urtwn_tx(sc, m, ni, data); 865 } 866 867 static void 868 urtwn_cmdq_invariants(struct urtwn_softc *sc) 869 { 870 struct urtwn_host_cmd_ring *const ring = &sc->cmdq; 871 872 KASSERT(mutex_owned(&sc->sc_task_mtx)); 873 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 874 "%s: cur=%d next=%d queued=%d", 875 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 876 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 877 "%s: cur=%d next=%d queued=%d", 878 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 879 KASSERTMSG((ring->queued >= 0 && 880 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 881 "%s: %d commands queued", 882 device_xname(sc->sc_dev), ring->queued); 883 } 884 885 static void 886 urtwn_task(void *arg) 887 { 888 struct urtwn_softc *sc = arg; 889 struct ieee80211com *ic = &sc->sc_ic; 890 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 891 struct urtwn_host_cmd *cmd; 892 int s; 893 894 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 895 if (ic->ic_state == IEEE80211_S_RUN && 896 (ic->ic_opmode == IEEE80211_M_HOSTAP || 897 ic->ic_opmode == IEEE80211_M_IBSS)) { 898 899 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 900 &sc->sc_bo); 901 if (m == NULL) { 902 aprint_error_dev(sc->sc_dev, 903 "could not allocate beacon"); 904 } 905 906 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 907 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 908 } 909 910 /* beacon is no longer needed */ 911 m_freem(m); 912 } 913 914 /* Process host commands. */ 915 s = splusb(); 916 mutex_spin_enter(&sc->sc_task_mtx); 917 urtwn_cmdq_invariants(sc); 918 while (ring->next != ring->cur) { 919 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 920 device_xname(sc->sc_dev), 921 ring->cur, ring->next, ring->queued); 922 cmd = &ring->cmd[ring->next]; 923 mutex_spin_exit(&sc->sc_task_mtx); 924 splx(s); 925 /* Invoke callback with kernel lock held. */ 926 cmd->cb(sc, cmd->data); 927 s = splusb(); 928 mutex_spin_enter(&sc->sc_task_mtx); 929 urtwn_cmdq_invariants(sc); 930 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 931 device_xname(sc->sc_dev), 932 ring->cur, ring->next, ring->queued); 933 ring->queued--; 934 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 935 } 936 cv_broadcast(&sc->sc_task_cv); 937 mutex_spin_exit(&sc->sc_task_mtx); 938 splx(s); 939 } 940 941 static void 942 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 943 void *arg, int len) 944 { 945 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 946 struct urtwn_host_cmd *cmd; 947 bool schedtask = false; 948 int s; 949 950 URTWNHIST_FUNC(); 951 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 952 (uintptr_t)cb, (uintptr_t)arg, len, 0); 953 954 s = splusb(); 955 mutex_spin_enter(&sc->sc_task_mtx); 956 urtwn_cmdq_invariants(sc); 957 cmd = &ring->cmd[ring->cur]; 958 cmd->cb = cb; 959 KASSERT(len <= sizeof(cmd->data)); 960 memcpy(cmd->data, arg, len); 961 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 962 963 /* 964 * Schedule a task to process the command if need be. 965 */ 966 if (!sc->sc_dying) { 967 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 968 device_printf(sc->sc_dev, "command queue overflow\n"); 969 else if (ring->queued++ == 0) 970 schedtask = true; 971 } 972 mutex_spin_exit(&sc->sc_task_mtx); 973 splx(s); 974 975 if (schedtask) 976 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 977 } 978 979 static void 980 urtwn_wait_async(struct urtwn_softc *sc) 981 { 982 983 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 984 985 /* Wait for all queued asynchronous commands to complete. */ 986 mutex_spin_enter(&sc->sc_task_mtx); 987 while (sc->cmdq.queued > 0) 988 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 989 mutex_spin_exit(&sc->sc_task_mtx); 990 } 991 992 static int 993 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 994 int len) 995 { 996 usb_device_request_t req; 997 usbd_status error; 998 999 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1000 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1001 1002 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1003 req.bRequest = R92C_REQ_REGS; 1004 USETW(req.wValue, addr); 1005 USETW(req.wIndex, 0); 1006 USETW(req.wLength, len); 1007 error = usbd_do_request(sc->sc_udev, &req, buf); 1008 if (error != USBD_NORMAL_COMPLETION) { 1009 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1010 error, addr, len, 0); 1011 } 1012 return error; 1013 } 1014 1015 static void 1016 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1017 { 1018 1019 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1020 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1021 1022 urtwn_write_region_1(sc, addr, &val, 1); 1023 } 1024 1025 static void 1026 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1027 { 1028 uint8_t buf[2]; 1029 1030 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1031 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1032 1033 buf[0] = (uint8_t)val; 1034 buf[1] = (uint8_t)(val >> 8); 1035 urtwn_write_region_1(sc, addr, buf, 2); 1036 } 1037 1038 static void 1039 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1040 { 1041 uint8_t buf[4]; 1042 1043 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1044 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1045 1046 buf[0] = (uint8_t)val; 1047 buf[1] = (uint8_t)(val >> 8); 1048 buf[2] = (uint8_t)(val >> 16); 1049 buf[3] = (uint8_t)(val >> 24); 1050 urtwn_write_region_1(sc, addr, buf, 4); 1051 } 1052 1053 static int 1054 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1055 { 1056 1057 URTWNHIST_FUNC(); 1058 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1059 1060 return urtwn_write_region_1(sc, addr, buf, len); 1061 } 1062 1063 static int 1064 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1065 int len) 1066 { 1067 usb_device_request_t req; 1068 usbd_status error; 1069 1070 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1071 1072 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1073 req.bRequest = R92C_REQ_REGS; 1074 USETW(req.wValue, addr); 1075 USETW(req.wIndex, 0); 1076 USETW(req.wLength, len); 1077 error = usbd_do_request(sc->sc_udev, &req, buf); 1078 if (error != USBD_NORMAL_COMPLETION) { 1079 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1080 error, addr, len, 0); 1081 } 1082 return error; 1083 } 1084 1085 static uint8_t 1086 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1087 { 1088 uint8_t val; 1089 1090 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1091 1092 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1093 return 0xff; 1094 1095 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1096 return val; 1097 } 1098 1099 static uint16_t 1100 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1101 { 1102 uint8_t buf[2]; 1103 uint16_t val; 1104 1105 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1106 1107 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1108 return 0xffff; 1109 1110 val = LE_READ_2(&buf[0]); 1111 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1112 return val; 1113 } 1114 1115 static uint32_t 1116 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1117 { 1118 uint8_t buf[4]; 1119 uint32_t val; 1120 1121 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1122 1123 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1124 return 0xffffffff; 1125 1126 val = LE_READ_4(&buf[0]); 1127 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1128 return val; 1129 } 1130 1131 static int 1132 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1133 { 1134 struct r92c_fw_cmd cmd; 1135 uint8_t *cp; 1136 int fwcur; 1137 int ntries; 1138 1139 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1140 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1141 1142 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1143 1144 mutex_enter(&sc->sc_fwcmd_mtx); 1145 fwcur = sc->fwcur; 1146 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1147 1148 /* Wait for current FW box to be empty. */ 1149 for (ntries = 0; ntries < 100; ntries++) { 1150 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1151 break; 1152 urtwn_delay_ms(sc, 2); 1153 } 1154 if (ntries == 100) { 1155 aprint_error_dev(sc->sc_dev, 1156 "could not send firmware command %d\n", id); 1157 mutex_exit(&sc->sc_fwcmd_mtx); 1158 return ETIMEDOUT; 1159 } 1160 1161 memset(&cmd, 0, sizeof(cmd)); 1162 KASSERT(len <= sizeof(cmd.msg)); 1163 memcpy(cmd.msg, buf, len); 1164 1165 /* Write the first word last since that will trigger the FW. */ 1166 cp = (uint8_t *)&cmd; 1167 cmd.id = id; 1168 if (len >= 4) { 1169 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1170 cmd.id |= R92C_CMD_FLAG_EXT; 1171 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1172 &cp[1], 2); 1173 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1174 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1175 ((uint32_t)cp[5] << 24)); 1176 } else { 1177 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1178 &cp[4], 2); 1179 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1180 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1181 ((uint32_t)cp[3] << 24)); 1182 } 1183 } else { 1184 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1185 } 1186 mutex_exit(&sc->sc_fwcmd_mtx); 1187 1188 return 0; 1189 } 1190 1191 static __inline void 1192 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1193 { 1194 1195 sc->sc_rf_write(sc, chain, addr, val); 1196 } 1197 1198 static void 1199 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1200 uint32_t val) 1201 { 1202 1203 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1204 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1205 } 1206 1207 static void 1208 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1209 uint32_t val) 1210 { 1211 1212 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1213 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1214 } 1215 1216 static void 1217 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1218 uint32_t val) 1219 { 1220 1221 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1222 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1223 } 1224 1225 static uint32_t 1226 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1227 { 1228 uint32_t reg[R92C_MAX_CHAINS], val; 1229 1230 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1231 if (chain != 0) { 1232 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1233 } 1234 1235 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1236 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1237 urtwn_delay_ms(sc, 1); 1238 1239 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1240 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1241 R92C_HSSI_PARAM2_READ_EDGE); 1242 urtwn_delay_ms(sc, 1); 1243 1244 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1245 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1246 urtwn_delay_ms(sc, 1); 1247 1248 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1249 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1250 } else { 1251 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1252 } 1253 return MS(val, R92C_LSSI_READBACK_DATA); 1254 } 1255 1256 static int 1257 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1258 { 1259 int ntries; 1260 1261 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1262 1263 urtwn_write_4(sc, R92C_LLT_INIT, 1264 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1265 SM(R92C_LLT_INIT_ADDR, addr) | 1266 SM(R92C_LLT_INIT_DATA, data)); 1267 /* Wait for write operation to complete. */ 1268 for (ntries = 0; ntries < 20; ntries++) { 1269 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1270 R92C_LLT_INIT_OP_NO_ACTIVE) { 1271 /* Done */ 1272 return 0; 1273 } 1274 DELAY(5); 1275 } 1276 return ETIMEDOUT; 1277 } 1278 1279 static uint8_t 1280 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1281 { 1282 uint32_t reg; 1283 int ntries; 1284 1285 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1286 1287 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1288 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1289 reg &= ~R92C_EFUSE_CTRL_VALID; 1290 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1291 1292 /* Wait for read operation to complete. */ 1293 for (ntries = 0; ntries < 100; ntries++) { 1294 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1295 if (reg & R92C_EFUSE_CTRL_VALID) { 1296 /* Done */ 1297 return MS(reg, R92C_EFUSE_CTRL_DATA); 1298 } 1299 DELAY(5); 1300 } 1301 aprint_error_dev(sc->sc_dev, 1302 "could not read efuse byte at address 0x%04x\n", addr); 1303 return 0xff; 1304 } 1305 1306 static void 1307 urtwn_efuse_read(struct urtwn_softc *sc) 1308 { 1309 uint8_t *rom = (uint8_t *)&sc->rom; 1310 uint32_t reg; 1311 uint16_t addr = 0; 1312 uint8_t off, msk; 1313 size_t i; 1314 1315 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1316 1317 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1318 1319 urtwn_efuse_switch_power(sc); 1320 1321 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1322 while (addr < 512) { 1323 reg = urtwn_efuse_read_1(sc, addr); 1324 if (reg == 0xff) 1325 break; 1326 addr++; 1327 off = reg >> 4; 1328 msk = reg & 0xf; 1329 for (i = 0; i < 4; i++) { 1330 if (msk & (1U << i)) 1331 continue; 1332 1333 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1334 addr++; 1335 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1336 addr++; 1337 } 1338 } 1339 #ifdef URTWN_DEBUG 1340 /* Dump ROM content. */ 1341 for (i = 0; i < (int)sizeof(sc->rom); i++) 1342 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1343 #endif 1344 } 1345 1346 static void 1347 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1348 { 1349 uint32_t reg; 1350 1351 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1352 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1353 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1354 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1355 } 1356 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1357 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1358 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1359 reg | R92C_SYS_FUNC_EN_ELDR); 1360 } 1361 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1362 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1363 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1364 urtwn_write_2(sc, R92C_SYS_CLKR, 1365 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1366 } 1367 } 1368 1369 static int 1370 urtwn_read_chipid(struct urtwn_softc *sc) 1371 { 1372 uint32_t reg; 1373 1374 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1375 1376 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1377 ISSET(sc->chip, URTWN_CHIP_92EU)) 1378 return 0; 1379 1380 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1381 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1382 /* test chip, not supported */ 1383 return EIO; 1384 } 1385 if (reg & R92C_SYS_CFG_TYPE_92C) { 1386 sc->chip |= URTWN_CHIP_92C; 1387 /* Check if it is a castrated 8192C. */ 1388 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1389 R92C_HPON_FSM_CHIP_BONDING_ID) == 1390 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1391 sc->chip |= URTWN_CHIP_92C_1T2R; 1392 } 1393 } 1394 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1395 sc->chip |= URTWN_CHIP_UMC; 1396 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1397 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1398 } 1399 } 1400 return 0; 1401 } 1402 1403 #ifdef URTWN_DEBUG 1404 static void 1405 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1406 { 1407 1408 aprint_normal_dev(sc->sc_dev, 1409 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1410 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1411 1412 aprint_normal_dev(sc->sc_dev, 1413 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1414 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1415 1416 aprint_normal_dev(sc->sc_dev, 1417 "macaddr %s\n", 1418 ether_sprintf(rp->macaddr)); 1419 1420 aprint_normal_dev(sc->sc_dev, 1421 "string %s, subcustomer_id %#x\n", 1422 rp->string, rp->subcustomer_id); 1423 1424 aprint_normal_dev(sc->sc_dev, 1425 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1426 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1427 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1428 1429 aprint_normal_dev(sc->sc_dev, 1430 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1431 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1432 rp->ht40_1s_tx_pwr[0][2], 1433 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1434 rp->ht40_1s_tx_pwr[1][2]); 1435 1436 aprint_normal_dev(sc->sc_dev, 1437 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1438 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1439 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1440 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1441 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1442 1443 aprint_normal_dev(sc->sc_dev, 1444 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1445 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1446 rp->ht20_tx_pwr_diff[2] & 0xf, 1447 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1448 rp->ht20_tx_pwr_diff[2] >> 4); 1449 1450 aprint_normal_dev(sc->sc_dev, 1451 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1452 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1453 rp->ofdm_tx_pwr_diff[2] & 0xf, 1454 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1455 rp->ofdm_tx_pwr_diff[2] >> 4); 1456 1457 aprint_normal_dev(sc->sc_dev, 1458 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1459 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1460 rp->ht40_max_pwr[2] & 0xf, 1461 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1462 rp->ht40_max_pwr[2] >> 4); 1463 1464 aprint_normal_dev(sc->sc_dev, 1465 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1466 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1467 rp->ht20_max_pwr[2] & 0xf, 1468 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1469 rp->ht20_max_pwr[2] >> 4); 1470 1471 aprint_normal_dev(sc->sc_dev, 1472 "xtal_calib %d, tssi %d %d, thermal %d\n", 1473 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1474 1475 aprint_normal_dev(sc->sc_dev, 1476 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1477 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1478 1479 aprint_normal_dev(sc->sc_dev, 1480 "channnel_plan %d, version %d customer_id %#x\n", 1481 rp->channel_plan, rp->version, rp->curstomer_id); 1482 } 1483 #endif 1484 1485 static void 1486 urtwn_read_rom(struct urtwn_softc *sc) 1487 { 1488 struct ieee80211com *ic = &sc->sc_ic; 1489 struct r92c_rom *rom = &sc->rom; 1490 1491 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1492 1493 mutex_enter(&sc->sc_write_mtx); 1494 1495 /* Read full ROM image. */ 1496 urtwn_efuse_read(sc); 1497 #ifdef URTWN_DEBUG 1498 if (urtwn_debug & DBG_REG) 1499 urtwn_dump_rom(sc, rom); 1500 #endif 1501 1502 /* XXX Weird but this is what the vendor driver does. */ 1503 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1504 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1505 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1506 1507 DPRINTFN(DBG_INIT, 1508 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1509 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1510 1511 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1512 1513 sc->sc_rf_write = urtwn_r92c_rf_write; 1514 sc->sc_power_on = urtwn_r92c_power_on; 1515 sc->sc_dma_init = urtwn_r92c_dma_init; 1516 1517 mutex_exit(&sc->sc_write_mtx); 1518 } 1519 1520 static void 1521 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1522 { 1523 struct ieee80211com *ic = &sc->sc_ic; 1524 uint8_t *rom = sc->r88e_rom; 1525 uint32_t reg; 1526 uint16_t addr = 0; 1527 uint8_t off, msk, tmp; 1528 int i; 1529 1530 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1531 1532 mutex_enter(&sc->sc_write_mtx); 1533 1534 off = 0; 1535 urtwn_efuse_switch_power(sc); 1536 1537 /* Read full ROM image. */ 1538 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1539 while (addr < 4096) { 1540 reg = urtwn_efuse_read_1(sc, addr); 1541 if (reg == 0xff) 1542 break; 1543 addr++; 1544 if ((reg & 0x1f) == 0x0f) { 1545 tmp = (reg & 0xe0) >> 5; 1546 reg = urtwn_efuse_read_1(sc, addr); 1547 if ((reg & 0x0f) != 0x0f) 1548 off = ((reg & 0xf0) >> 1) | tmp; 1549 addr++; 1550 } else 1551 off = reg >> 4; 1552 msk = reg & 0xf; 1553 for (i = 0; i < 4; i++) { 1554 if (msk & (1 << i)) 1555 continue; 1556 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1557 addr++; 1558 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1559 addr++; 1560 } 1561 } 1562 #ifdef URTWN_DEBUG 1563 if (urtwn_debug & DBG_REG) { 1564 } 1565 #endif 1566 1567 addr = 0x10; 1568 for (i = 0; i < 6; i++) 1569 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1570 for (i = 0; i < 5; i++) 1571 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1572 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1573 if (sc->bw20_tx_pwr_diff & 0x08) 1574 sc->bw20_tx_pwr_diff |= 0xf0; 1575 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1576 if (sc->ofdm_tx_pwr_diff & 0x08) 1577 sc->ofdm_tx_pwr_diff |= 0xf0; 1578 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1579 1580 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1581 1582 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1583 sc->sc_power_on = urtwn_r92e_power_on; 1584 sc->sc_rf_write = urtwn_r92e_rf_write; 1585 } else { 1586 sc->sc_power_on = urtwn_r88e_power_on; 1587 sc->sc_rf_write = urtwn_r88e_rf_write; 1588 } 1589 sc->sc_dma_init = urtwn_r88e_dma_init; 1590 1591 mutex_exit(&sc->sc_write_mtx); 1592 } 1593 1594 static int 1595 urtwn_media_change(struct ifnet *ifp) 1596 { 1597 int error; 1598 1599 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1600 1601 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1602 return error; 1603 1604 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1605 (IFF_UP | IFF_RUNNING)) { 1606 urtwn_init(ifp); 1607 } 1608 return 0; 1609 } 1610 1611 /* 1612 * Initialize rate adaptation in firmware. 1613 */ 1614 static int __noinline 1615 urtwn_ra_init(struct urtwn_softc *sc) 1616 { 1617 static const uint8_t map[] = { 1618 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1619 }; 1620 struct ieee80211com *ic = &sc->sc_ic; 1621 struct ieee80211_node *ni = ic->ic_bss; 1622 struct ieee80211_rateset *rs = &ni->ni_rates; 1623 struct r92c_fw_cmd_macid_cfg cmd; 1624 uint32_t rates, basicrates; 1625 uint32_t rrsr_mask, rrsr_rate; 1626 uint8_t mode; 1627 size_t maxrate, maxbasicrate, i, j; 1628 int error; 1629 1630 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1631 1632 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1633 1634 /* Get normal and basic rates mask. */ 1635 rates = basicrates = 1; 1636 maxrate = maxbasicrate = 0; 1637 for (i = 0; i < rs->rs_nrates; i++) { 1638 /* Convert 802.11 rate to HW rate index. */ 1639 for (j = 0; j < __arraycount(map); j++) { 1640 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1641 break; 1642 } 1643 } 1644 if (j == __arraycount(map)) { 1645 /* Unknown rate, skip. */ 1646 continue; 1647 } 1648 1649 rates |= 1U << j; 1650 if (j > maxrate) { 1651 maxrate = j; 1652 } 1653 1654 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1655 basicrates |= 1U << j; 1656 if (j > maxbasicrate) { 1657 maxbasicrate = j; 1658 } 1659 } 1660 } 1661 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1662 mode = R92C_RAID_11B; 1663 } else { 1664 mode = R92C_RAID_11BG; 1665 } 1666 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1667 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1668 "maxrate=%jx, maxbasicrate=%jx", 1669 rates, basicrates, maxrate, maxbasicrate); 1670 1671 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1672 maxbasicrate |= R92C_RATE_SHORTGI; 1673 maxrate |= R92C_RATE_SHORTGI; 1674 } 1675 1676 /* Set rates mask for group addressed frames. */ 1677 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1678 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1679 cmd.macid |= RTWN_MACID_SHORTGI; 1680 cmd.mask = htole32((mode << 28) | basicrates); 1681 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1682 if (error != 0) { 1683 aprint_error_dev(sc->sc_dev, 1684 "could not add broadcast station\n"); 1685 return error; 1686 } 1687 /* Set initial MRR rate. */ 1688 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1689 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1690 1691 /* Set rates mask for unicast frames. */ 1692 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1693 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1694 cmd.macid |= RTWN_MACID_SHORTGI; 1695 cmd.mask = htole32((mode << 28) | rates); 1696 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1697 if (error != 0) { 1698 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1699 return error; 1700 } 1701 /* Set initial MRR rate. */ 1702 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1703 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1704 1705 rrsr_rate = ic->ic_fixed_rate; 1706 if (rrsr_rate == -1) 1707 rrsr_rate = 11; 1708 1709 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1710 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1711 1712 /* Indicate highest supported rate. */ 1713 ni->ni_txrate = rs->rs_nrates - 1; 1714 1715 return 0; 1716 } 1717 1718 static int 1719 urtwn_get_nettype(struct urtwn_softc *sc) 1720 { 1721 struct ieee80211com *ic = &sc->sc_ic; 1722 int type; 1723 1724 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1725 1726 switch (ic->ic_opmode) { 1727 case IEEE80211_M_STA: 1728 type = R92C_CR_NETTYPE_INFRA; 1729 break; 1730 1731 case IEEE80211_M_IBSS: 1732 type = R92C_CR_NETTYPE_ADHOC; 1733 break; 1734 1735 default: 1736 type = R92C_CR_NETTYPE_NOLINK; 1737 break; 1738 } 1739 1740 return type; 1741 } 1742 1743 static void 1744 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1745 { 1746 uint8_t reg; 1747 1748 URTWNHIST_FUNC(); 1749 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1750 1751 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1752 1753 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1754 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1755 } 1756 1757 static void 1758 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1759 { 1760 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1761 uint64_t tsf; 1762 1763 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1764 1765 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1766 1767 /* Enable TSF synchronization. */ 1768 urtwn_write_1(sc, R92C_BCN_CTRL, 1769 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1770 1771 /* Correct TSF */ 1772 urtwn_write_1(sc, R92C_BCN_CTRL, 1773 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1774 1775 /* Set initial TSF. */ 1776 tsf = ni->ni_tstamp.tsf; 1777 tsf = le64toh(tsf); 1778 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1779 tsf -= IEEE80211_DUR_TU; 1780 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1781 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1782 1783 urtwn_write_1(sc, R92C_BCN_CTRL, 1784 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1785 } 1786 1787 static void 1788 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1789 { 1790 uint8_t reg; 1791 1792 URTWNHIST_FUNC(); 1793 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1794 1795 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1796 1797 if (led == URTWN_LED_LINK) { 1798 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1799 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1800 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1801 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1802 (R92C_LEDCFG0_DIS << 1)); 1803 if (on) { 1804 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1805 R92E_LEDSON; 1806 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1807 } 1808 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1809 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1810 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1811 if (!on) { 1812 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1813 urtwn_write_1(sc, R92C_LEDCFG2, 1814 reg | R92C_LEDCFG0_DIS); 1815 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1816 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1817 reg & 0xfe); 1818 } 1819 } else { 1820 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1821 if (!on) { 1822 reg |= R92C_LEDCFG0_DIS; 1823 } 1824 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1825 } 1826 sc->ledlink = on; /* Save LED state. */ 1827 } 1828 } 1829 1830 static void 1831 urtwn_calib_to(void *arg) 1832 { 1833 struct urtwn_softc *sc = arg; 1834 1835 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1836 1837 if (sc->sc_dying) 1838 return; 1839 1840 /* Do it in a process context. */ 1841 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1842 } 1843 1844 /* ARGSUSED */ 1845 static void 1846 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1847 { 1848 struct r92c_fw_cmd_rssi cmd; 1849 struct r92e_fw_cmd_rssi cmde; 1850 1851 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1852 1853 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1854 goto restart_timer; 1855 1856 mutex_enter(&sc->sc_write_mtx); 1857 if (sc->avg_pwdb != -1) { 1858 /* Indicate Rx signal strength to FW for rate adaptation. */ 1859 memset(&cmd, 0, sizeof(cmd)); 1860 memset(&cmde, 0, sizeof(cmde)); 1861 cmd.macid = 0; /* BSS. */ 1862 cmde.macid = 0; /* BSS. */ 1863 cmd.pwdb = sc->avg_pwdb; 1864 cmde.pwdb = sc->avg_pwdb; 1865 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1866 sc->avg_pwdb, 0, 0, 0); 1867 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1868 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1869 sizeof(cmd)); 1870 } else { 1871 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1872 sizeof(cmde)); 1873 } 1874 } 1875 1876 /* Do temperature compensation. */ 1877 urtwn_temp_calib(sc); 1878 mutex_exit(&sc->sc_write_mtx); 1879 1880 restart_timer: 1881 if (!sc->sc_dying) { 1882 /* Restart calibration timer. */ 1883 callout_schedule(&sc->sc_calib_to, hz); 1884 } 1885 } 1886 1887 static void 1888 urtwn_next_scan(void *arg) 1889 { 1890 struct urtwn_softc *sc = arg; 1891 int s; 1892 1893 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1894 1895 if (sc->sc_dying) 1896 return; 1897 1898 s = splnet(); 1899 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1900 ieee80211_next_scan(&sc->sc_ic); 1901 splx(s); 1902 } 1903 1904 static void 1905 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1906 { 1907 URTWNHIST_FUNC(); 1908 URTWNHIST_CALLARGS("new node %06jx%06jx", 1909 ni->ni_macaddr[0] << 2 | 1910 ni->ni_macaddr[1] << 1 | 1911 ni->ni_macaddr[2], 1912 ni->ni_macaddr[3] << 2 | 1913 ni->ni_macaddr[4] << 1 | 1914 ni->ni_macaddr[5], 1915 0, 0); 1916 /* start with lowest Tx rate */ 1917 ni->ni_txrate = 0; 1918 } 1919 1920 static int 1921 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1922 { 1923 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1924 struct urtwn_cmd_newstate cmd; 1925 1926 URTWNHIST_FUNC(); 1927 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1928 1929 callout_stop(&sc->sc_scan_to); 1930 callout_stop(&sc->sc_calib_to); 1931 1932 /* Do it in a process context. */ 1933 cmd.state = nstate; 1934 cmd.arg = arg; 1935 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1936 return 0; 1937 } 1938 1939 static void 1940 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1941 { 1942 struct urtwn_cmd_newstate *cmd = arg; 1943 struct ieee80211com *ic = &sc->sc_ic; 1944 struct ieee80211_node *ni; 1945 enum ieee80211_state ostate = ic->ic_state; 1946 enum ieee80211_state nstate = cmd->state; 1947 uint32_t reg; 1948 uint8_t sifs_time, msr; 1949 int s; 1950 1951 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1952 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1953 1954 s = splnet(); 1955 mutex_enter(&sc->sc_write_mtx); 1956 1957 callout_stop(&sc->sc_scan_to); 1958 callout_stop(&sc->sc_calib_to); 1959 1960 switch (ostate) { 1961 case IEEE80211_S_INIT: 1962 break; 1963 1964 case IEEE80211_S_SCAN: 1965 if (nstate != IEEE80211_S_SCAN) { 1966 /* 1967 * End of scanning 1968 */ 1969 /* flush 4-AC Queue after site_survey */ 1970 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1971 1972 /* Allow Rx from our BSSID only. */ 1973 urtwn_write_4(sc, R92C_RCR, 1974 urtwn_read_4(sc, R92C_RCR) | 1975 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1976 } 1977 break; 1978 1979 case IEEE80211_S_AUTH: 1980 case IEEE80211_S_ASSOC: 1981 break; 1982 1983 case IEEE80211_S_RUN: 1984 /* Turn link LED off. */ 1985 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1986 1987 /* Set media status to 'No Link'. */ 1988 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1989 1990 /* Stop Rx of data frames. */ 1991 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1992 1993 /* Reset TSF. */ 1994 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1995 1996 /* Disable TSF synchronization. */ 1997 urtwn_write_1(sc, R92C_BCN_CTRL, 1998 urtwn_read_1(sc, R92C_BCN_CTRL) | 1999 R92C_BCN_CTRL_DIS_TSF_UDT0); 2000 2001 /* Back to 20MHz mode */ 2002 urtwn_set_chan(sc, ic->ic_curchan, 2003 IEEE80211_HTINFO_2NDCHAN_NONE); 2004 2005 if (ic->ic_opmode == IEEE80211_M_IBSS || 2006 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2007 /* Stop BCN */ 2008 urtwn_write_1(sc, R92C_BCN_CTRL, 2009 urtwn_read_1(sc, R92C_BCN_CTRL) & 2010 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2011 } 2012 2013 /* Reset EDCA parameters. */ 2014 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2015 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2016 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2017 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2018 2019 /* flush all cam entries */ 2020 urtwn_cam_init(sc); 2021 break; 2022 } 2023 2024 switch (nstate) { 2025 case IEEE80211_S_INIT: 2026 /* Turn link LED off. */ 2027 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2028 break; 2029 2030 case IEEE80211_S_SCAN: 2031 if (ostate != IEEE80211_S_SCAN) { 2032 /* 2033 * Begin of scanning 2034 */ 2035 2036 /* Set gain for scanning. */ 2037 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2038 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2039 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2040 2041 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2042 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2043 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2044 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2045 } 2046 2047 /* Set media status to 'No Link'. */ 2048 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2049 2050 /* Allow Rx from any BSSID. */ 2051 urtwn_write_4(sc, R92C_RCR, 2052 urtwn_read_4(sc, R92C_RCR) & 2053 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2054 2055 /* Stop Rx of data frames. */ 2056 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2057 2058 /* Disable update TSF */ 2059 urtwn_write_1(sc, R92C_BCN_CTRL, 2060 urtwn_read_1(sc, R92C_BCN_CTRL) | 2061 R92C_BCN_CTRL_DIS_TSF_UDT0); 2062 } 2063 2064 /* Make link LED blink during scan. */ 2065 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2066 2067 /* Pause AC Tx queues. */ 2068 urtwn_write_1(sc, R92C_TXPAUSE, 2069 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2070 2071 urtwn_set_chan(sc, ic->ic_curchan, 2072 IEEE80211_HTINFO_2NDCHAN_NONE); 2073 2074 /* Start periodic scan. */ 2075 if (!sc->sc_dying) 2076 callout_schedule(&sc->sc_scan_to, hz / 5); 2077 break; 2078 2079 case IEEE80211_S_AUTH: 2080 /* Set initial gain under link. */ 2081 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2082 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2083 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2084 2085 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2086 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2087 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2088 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2089 } 2090 2091 /* Set media status to 'No Link'. */ 2092 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2093 2094 /* Allow Rx from any BSSID. */ 2095 urtwn_write_4(sc, R92C_RCR, 2096 urtwn_read_4(sc, R92C_RCR) & 2097 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2098 2099 urtwn_set_chan(sc, ic->ic_curchan, 2100 IEEE80211_HTINFO_2NDCHAN_NONE); 2101 break; 2102 2103 case IEEE80211_S_ASSOC: 2104 break; 2105 2106 case IEEE80211_S_RUN: 2107 ni = ic->ic_bss; 2108 2109 /* XXX: Set 20MHz mode */ 2110 urtwn_set_chan(sc, ic->ic_curchan, 2111 IEEE80211_HTINFO_2NDCHAN_NONE); 2112 2113 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2114 /* Back to 20MHz mode */ 2115 urtwn_set_chan(sc, ic->ic_curchan, 2116 IEEE80211_HTINFO_2NDCHAN_NONE); 2117 2118 /* Set media status to 'No Link'. */ 2119 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2120 2121 /* Enable Rx of data frames. */ 2122 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2123 2124 /* Allow Rx from any BSSID. */ 2125 urtwn_write_4(sc, R92C_RCR, 2126 urtwn_read_4(sc, R92C_RCR) & 2127 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2128 2129 /* Accept Rx data/control/management frames */ 2130 urtwn_write_4(sc, R92C_RCR, 2131 urtwn_read_4(sc, R92C_RCR) | 2132 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2133 2134 /* Turn link LED on. */ 2135 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2136 break; 2137 } 2138 2139 /* Set media status to 'Associated'. */ 2140 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2141 2142 /* Set BSSID. */ 2143 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2144 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2145 2146 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2147 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2148 } else { 2149 /* 802.11b/g */ 2150 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2151 } 2152 2153 /* Enable Rx of data frames. */ 2154 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2155 2156 /* Set beacon interval. */ 2157 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2158 2159 msr = urtwn_read_1(sc, R92C_MSR); 2160 msr &= R92C_MSR_MASK; 2161 switch (ic->ic_opmode) { 2162 case IEEE80211_M_STA: 2163 /* Allow Rx from our BSSID only. */ 2164 urtwn_write_4(sc, R92C_RCR, 2165 urtwn_read_4(sc, R92C_RCR) | 2166 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2167 2168 /* Enable TSF synchronization. */ 2169 urtwn_tsf_sync_enable(sc); 2170 2171 msr |= R92C_MSR_INFRA; 2172 break; 2173 case IEEE80211_M_HOSTAP: 2174 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2175 2176 /* Allow Rx from any BSSID. */ 2177 urtwn_write_4(sc, R92C_RCR, 2178 urtwn_read_4(sc, R92C_RCR) & 2179 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2180 2181 /* Reset TSF timer to zero. */ 2182 reg = urtwn_read_4(sc, R92C_TCR); 2183 reg &= ~0x01; 2184 urtwn_write_4(sc, R92C_TCR, reg); 2185 reg |= 0x01; 2186 urtwn_write_4(sc, R92C_TCR, reg); 2187 2188 msr |= R92C_MSR_AP; 2189 break; 2190 default: 2191 msr |= R92C_MSR_ADHOC; 2192 break; 2193 } 2194 urtwn_write_1(sc, R92C_MSR, msr); 2195 2196 sifs_time = 10; 2197 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2198 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2199 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2200 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2201 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2202 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2203 2204 /* Initialize rate adaptation. */ 2205 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2206 ISSET(sc->chip, URTWN_CHIP_92EU)) 2207 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2208 else 2209 urtwn_ra_init(sc); 2210 2211 /* Turn link LED on. */ 2212 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2213 2214 /* Reset average RSSI. */ 2215 sc->avg_pwdb = -1; 2216 2217 /* Reset temperature calibration state machine. */ 2218 sc->thcal_state = 0; 2219 sc->thcal_lctemp = 0; 2220 2221 /* Start periodic calibration. */ 2222 if (!sc->sc_dying) 2223 callout_schedule(&sc->sc_calib_to, hz); 2224 break; 2225 } 2226 2227 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2228 2229 mutex_exit(&sc->sc_write_mtx); 2230 splx(s); 2231 } 2232 2233 static int 2234 urtwn_wme_update(struct ieee80211com *ic) 2235 { 2236 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2237 2238 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2239 2240 /* don't override default WME values if WME is not actually enabled */ 2241 if (!(ic->ic_flags & IEEE80211_F_WME)) 2242 return 0; 2243 2244 /* Do it in a process context. */ 2245 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2246 return 0; 2247 } 2248 2249 static void 2250 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2251 { 2252 static const uint16_t ac2reg[WME_NUM_AC] = { 2253 R92C_EDCA_BE_PARAM, 2254 R92C_EDCA_BK_PARAM, 2255 R92C_EDCA_VI_PARAM, 2256 R92C_EDCA_VO_PARAM 2257 }; 2258 struct ieee80211com *ic = &sc->sc_ic; 2259 const struct wmeParams *wmep; 2260 int ac, aifs, slottime; 2261 int s; 2262 2263 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2264 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2265 2266 s = splnet(); 2267 mutex_enter(&sc->sc_write_mtx); 2268 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2269 for (ac = 0; ac < WME_NUM_AC; ac++) { 2270 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2271 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2272 aifs = wmep->wmep_aifsn * slottime + 10; 2273 urtwn_write_4(sc, ac2reg[ac], 2274 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2275 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2276 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2277 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2278 } 2279 mutex_exit(&sc->sc_write_mtx); 2280 splx(s); 2281 } 2282 2283 static void 2284 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2285 { 2286 int pwdb; 2287 2288 URTWNHIST_FUNC(); 2289 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2290 2291 /* Convert antenna signal to percentage. */ 2292 if (rssi <= -100 || rssi >= 20) 2293 pwdb = 0; 2294 else if (rssi >= 0) 2295 pwdb = 100; 2296 else 2297 pwdb = 100 + rssi; 2298 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2299 if (rate <= 3) { 2300 /* CCK gain is smaller than OFDM/MCS gain. */ 2301 pwdb += 6; 2302 if (pwdb > 100) 2303 pwdb = 100; 2304 if (pwdb <= 14) 2305 pwdb -= 4; 2306 else if (pwdb <= 26) 2307 pwdb -= 8; 2308 else if (pwdb <= 34) 2309 pwdb -= 6; 2310 else if (pwdb <= 42) 2311 pwdb -= 2; 2312 } 2313 } 2314 if (sc->avg_pwdb == -1) /* Init. */ 2315 sc->avg_pwdb = pwdb; 2316 else if (sc->avg_pwdb < pwdb) 2317 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2318 else 2319 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2320 2321 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2322 rate, rssi, pwdb, sc->avg_pwdb); 2323 } 2324 2325 static int8_t 2326 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2327 { 2328 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2329 struct r92c_rx_phystat *phy; 2330 struct r92c_rx_cck *cck; 2331 uint8_t rpt; 2332 int8_t rssi; 2333 2334 URTWNHIST_FUNC(); 2335 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2336 2337 if (rate <= 3) { 2338 cck = (struct r92c_rx_cck *)physt; 2339 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2340 rpt = (cck->agc_rpt >> 5) & 0x3; 2341 rssi = (cck->agc_rpt & 0x1f) << 1; 2342 } else { 2343 rpt = (cck->agc_rpt >> 6) & 0x3; 2344 rssi = cck->agc_rpt & 0x3e; 2345 } 2346 rssi = cckoff[rpt] - rssi; 2347 } else { /* OFDM/HT. */ 2348 phy = (struct r92c_rx_phystat *)physt; 2349 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2350 } 2351 return rssi; 2352 } 2353 2354 static int8_t 2355 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2356 { 2357 struct r92c_rx_phystat *phy; 2358 struct r88e_rx_cck *cck; 2359 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2360 int8_t rssi; 2361 2362 URTWNHIST_FUNC(); 2363 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2364 2365 rssi = 0; 2366 if (rate <= 3) { 2367 cck = (struct r88e_rx_cck *)physt; 2368 cck_agc_rpt = cck->agc_rpt; 2369 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2370 vga_idx = cck_agc_rpt & 0x1f; 2371 switch (lna_idx) { 2372 case 7: 2373 if (vga_idx <= 27) 2374 rssi = -100 + 2* (27 - vga_idx); 2375 else 2376 rssi = -100; 2377 break; 2378 case 6: 2379 rssi = -48 + 2 * (2 - vga_idx); 2380 break; 2381 case 5: 2382 rssi = -42 + 2 * (7 - vga_idx); 2383 break; 2384 case 4: 2385 rssi = -36 + 2 * (7 - vga_idx); 2386 break; 2387 case 3: 2388 rssi = -24 + 2 * (7 - vga_idx); 2389 break; 2390 case 2: 2391 rssi = -12 + 2 * (5 - vga_idx); 2392 break; 2393 case 1: 2394 rssi = 8 - (2 * vga_idx); 2395 break; 2396 case 0: 2397 rssi = 14 - (2 * vga_idx); 2398 break; 2399 } 2400 rssi += 6; 2401 } else { /* OFDM/HT. */ 2402 phy = (struct r92c_rx_phystat *)physt; 2403 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2404 } 2405 return rssi; 2406 } 2407 2408 static void 2409 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2410 { 2411 struct ieee80211com *ic = &sc->sc_ic; 2412 struct ifnet *ifp = ic->ic_ifp; 2413 struct ieee80211_frame *wh; 2414 struct ieee80211_node *ni; 2415 struct r92c_rx_desc_usb *stat; 2416 uint32_t rxdw0, rxdw3; 2417 struct mbuf *m; 2418 uint8_t rate; 2419 int8_t rssi = 0; 2420 int s, infosz; 2421 2422 URTWNHIST_FUNC(); 2423 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2424 2425 stat = (struct r92c_rx_desc_usb *)buf; 2426 rxdw0 = le32toh(stat->rxdw0); 2427 rxdw3 = le32toh(stat->rxdw3); 2428 2429 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2430 /* 2431 * This should not happen since we setup our Rx filter 2432 * to not receive these frames. 2433 */ 2434 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2435 if_statinc(ifp, if_ierrors); 2436 return; 2437 } 2438 /* 2439 * XXX: This will drop most control packets. Do we really 2440 * want this in IEEE80211_M_MONITOR mode? 2441 */ 2442 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2443 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2444 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2445 ic->ic_stats.is_rx_tooshort++; 2446 if_statinc(ifp, if_ierrors); 2447 return; 2448 } 2449 if (__predict_false(pktlen > MCLBYTES)) { 2450 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2451 if_statinc(ifp, if_ierrors); 2452 return; 2453 } 2454 2455 rate = MS(rxdw3, R92C_RXDW3_RATE); 2456 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2457 2458 /* Get RSSI from PHY status descriptor if present. */ 2459 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2460 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2461 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2462 else 2463 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2464 /* Update our average RSSI. */ 2465 urtwn_update_avgrssi(sc, rate, rssi); 2466 } 2467 2468 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2469 pktlen, rate, infosz, rssi); 2470 2471 MGETHDR(m, M_DONTWAIT, MT_DATA); 2472 if (__predict_false(m == NULL)) { 2473 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2474 ic->ic_stats.is_rx_nobuf++; 2475 if_statinc(ifp, if_ierrors); 2476 return; 2477 } 2478 if (pktlen > (int)MHLEN) { 2479 MCLGET(m, M_DONTWAIT); 2480 if (__predict_false(!(m->m_flags & M_EXT))) { 2481 aprint_error_dev(sc->sc_dev, 2482 "couldn't allocate rx mbuf cluster\n"); 2483 m_freem(m); 2484 ic->ic_stats.is_rx_nobuf++; 2485 if_statinc(ifp, if_ierrors); 2486 return; 2487 } 2488 } 2489 2490 /* Finalize mbuf. */ 2491 m_set_rcvif(m, ifp); 2492 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2493 memcpy(mtod(m, uint8_t *), wh, pktlen); 2494 m->m_pkthdr.len = m->m_len = pktlen; 2495 2496 s = splnet(); 2497 if (__predict_false(sc->sc_drvbpf != NULL)) { 2498 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2499 2500 tap->wr_flags = 0; 2501 if (!(rxdw3 & R92C_RXDW3_HT)) { 2502 switch (rate) { 2503 /* CCK. */ 2504 case 0: tap->wr_rate = 2; break; 2505 case 1: tap->wr_rate = 4; break; 2506 case 2: tap->wr_rate = 11; break; 2507 case 3: tap->wr_rate = 22; break; 2508 /* OFDM. */ 2509 case 4: tap->wr_rate = 12; break; 2510 case 5: tap->wr_rate = 18; break; 2511 case 6: tap->wr_rate = 24; break; 2512 case 7: tap->wr_rate = 36; break; 2513 case 8: tap->wr_rate = 48; break; 2514 case 9: tap->wr_rate = 72; break; 2515 case 10: tap->wr_rate = 96; break; 2516 case 11: tap->wr_rate = 108; break; 2517 } 2518 } else if (rate >= 12) { /* MCS0~15. */ 2519 /* Bit 7 set means HT MCS instead of rate. */ 2520 tap->wr_rate = 0x80 | (rate - 12); 2521 } 2522 tap->wr_dbm_antsignal = rssi; 2523 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2524 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2525 2526 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2527 } 2528 2529 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2530 2531 /* push the frame up to the 802.11 stack */ 2532 ieee80211_input(ic, m, ni, rssi, 0); 2533 2534 /* Node is no longer needed. */ 2535 ieee80211_free_node(ni); 2536 2537 splx(s); 2538 } 2539 2540 static void 2541 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2542 { 2543 struct urtwn_rx_data *data = priv; 2544 struct urtwn_softc *sc = data->sc; 2545 struct r92c_rx_desc_usb *stat; 2546 size_t pidx = data->pidx; 2547 uint32_t rxdw0; 2548 uint8_t *buf; 2549 int len, totlen, pktlen, infosz, npkts; 2550 2551 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2552 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2553 2554 mutex_enter(&sc->sc_rx_mtx); 2555 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2556 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2557 /* Put this Rx buffer back to our free list. */ 2558 mutex_exit(&sc->sc_rx_mtx); 2559 2560 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2561 if (status == USBD_STALLED) 2562 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2563 else if (status != USBD_CANCELLED) 2564 goto resubmit; 2565 return; 2566 } 2567 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2568 2569 if (__predict_false(len < (int)sizeof(*stat))) { 2570 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2571 goto resubmit; 2572 } 2573 buf = data->buf; 2574 2575 /* Get the number of encapsulated frames. */ 2576 stat = (struct r92c_rx_desc_usb *)buf; 2577 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2578 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2579 else 2580 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2581 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2582 2583 if (npkts != 0) 2584 rnd_add_uint32(&sc->rnd_source, npkts); 2585 2586 /* Process all of them. */ 2587 while (npkts-- > 0) { 2588 if (__predict_false(len < (int)sizeof(*stat))) { 2589 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2590 len, 0, 0, 0); 2591 break; 2592 } 2593 stat = (struct r92c_rx_desc_usb *)buf; 2594 rxdw0 = le32toh(stat->rxdw0); 2595 2596 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2597 if (__predict_false(pktlen == 0)) { 2598 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2599 break; 2600 } 2601 2602 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2603 2604 /* Make sure everything fits in xfer. */ 2605 totlen = sizeof(*stat) + infosz + pktlen; 2606 if (__predict_false(totlen > len)) { 2607 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2608 (int)sizeof(*stat), infosz, pktlen, len); 2609 break; 2610 } 2611 2612 /* Process 802.11 frame. */ 2613 urtwn_rx_frame(sc, buf, pktlen); 2614 2615 /* Next chunk is 128-byte aligned. */ 2616 totlen = roundup2(totlen, 128); 2617 buf += totlen; 2618 len -= totlen; 2619 } 2620 2621 resubmit: 2622 /* Setup a new transfer. */ 2623 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2624 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2625 (void)usbd_transfer(xfer); 2626 } 2627 2628 static void 2629 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2630 { 2631 size_t pidx = data->pidx; 2632 2633 mutex_enter(&sc->sc_tx_mtx); 2634 /* Put this Tx buffer back to our free list. */ 2635 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2636 mutex_exit(&sc->sc_tx_mtx); 2637 } 2638 2639 static void 2640 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2641 { 2642 struct urtwn_tx_data *data = priv; 2643 struct urtwn_softc *sc = data->sc; 2644 struct ifnet *ifp = &sc->sc_if; 2645 size_t pidx = data->pidx; 2646 int s; 2647 2648 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2649 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2650 2651 urtwn_put_tx_data(sc, data); 2652 2653 s = splnet(); 2654 sc->tx_timer = 0; 2655 ifp->if_flags &= ~IFF_OACTIVE; 2656 2657 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2658 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2659 if (status == USBD_STALLED) { 2660 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2661 usbd_clear_endpoint_stall_async(pipe); 2662 } 2663 device_printf(sc->sc_dev, "transmit failed, %s\n", 2664 usbd_errstr(status)); 2665 if_statinc(ifp, if_oerrors); 2666 } 2667 splx(s); 2668 return; 2669 } 2670 2671 if_statinc(ifp, if_opackets); 2672 urtwn_start(ifp); 2673 splx(s); 2674 2675 } 2676 2677 static int 2678 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2679 struct urtwn_tx_data *data) 2680 { 2681 struct ieee80211com *ic = &sc->sc_ic; 2682 struct ieee80211_frame *wh; 2683 struct ieee80211_key *k = NULL; 2684 struct r92c_tx_desc_usb *txd; 2685 size_t i, padsize, xferlen, txd_len; 2686 uint16_t seq, sum; 2687 uint8_t raid, type, tid; 2688 int s, hasqos, error; 2689 2690 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2691 2692 wh = mtod(m, struct ieee80211_frame *); 2693 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2694 txd_len = sizeof(*txd); 2695 2696 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2697 txd_len = 32; 2698 2699 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2700 k = ieee80211_crypto_encap(ic, ni, m); 2701 if (k == NULL) { 2702 urtwn_put_tx_data(sc, data); 2703 m_free(m); 2704 return ENOBUFS; 2705 } 2706 2707 /* packet header may have moved, reset our local pointer */ 2708 wh = mtod(m, struct ieee80211_frame *); 2709 } 2710 2711 if (__predict_false(sc->sc_drvbpf != NULL)) { 2712 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2713 2714 tap->wt_flags = 0; 2715 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2716 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2717 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2718 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2719 2720 /* XXX: set tap->wt_rate? */ 2721 2722 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2723 } 2724 2725 /* non-qos data frames */ 2726 tid = R92C_TXDW1_QSEL_BE; 2727 if ((hasqos = ieee80211_has_qos(wh))) { 2728 /* data frames in 11n mode */ 2729 struct ieee80211_qosframe *qwh = (void *)wh; 2730 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2731 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2732 tid = R92C_TXDW1_QSEL_MGNT; 2733 } 2734 2735 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2736 padsize = 8; 2737 else 2738 padsize = 0; 2739 2740 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2741 padsize = 0; 2742 2743 /* Fill Tx descriptor. */ 2744 txd = (struct r92c_tx_desc_usb *)data->buf; 2745 memset(txd, 0, txd_len + padsize); 2746 2747 txd->txdw0 |= htole32( 2748 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2749 SM(R92C_TXDW0_OFFSET, txd_len)); 2750 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2751 txd->txdw0 |= htole32( 2752 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2753 } 2754 2755 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2756 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2757 2758 /* fix pad field */ 2759 if (padsize > 0) { 2760 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2761 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2762 } 2763 2764 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2765 type == IEEE80211_FC0_TYPE_DATA) { 2766 if (ic->ic_curmode == IEEE80211_MODE_11B) 2767 raid = R92C_RAID_11B; 2768 else 2769 raid = R92C_RAID_11BG; 2770 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2771 tid, raid, 0, 0); 2772 2773 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2774 txd->txdw1 |= htole32( 2775 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2776 SM(R92C_TXDW1_QSEL, tid) | 2777 SM(R92C_TXDW1_RAID, raid) | 2778 R92C_TXDW1_AGGBK); 2779 } else 2780 txd->txdw1 |= htole32( 2781 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2782 SM(R92C_TXDW1_QSEL, tid) | 2783 SM(R92C_TXDW1_RAID, raid) | 2784 R92C_TXDW1_AGGBK); 2785 2786 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2787 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2788 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2789 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2790 2791 if (hasqos) { 2792 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2793 } 2794 2795 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2796 /* for 11g */ 2797 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2798 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2799 R92C_TXDW4_HWRTSEN); 2800 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2801 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2802 R92C_TXDW4_HWRTSEN); 2803 } 2804 } 2805 /* Send RTS at OFDM24. */ 2806 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2807 txd->txdw5 |= htole32(0x0001ff00); 2808 /* Send data at OFDM54. */ 2809 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2810 txd->txdw5 |= htole32(0x13 & 0x3f); 2811 else 2812 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2813 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2814 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2815 txd->txdw1 |= htole32( 2816 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2817 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2818 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2819 2820 /* Force CCK1. */ 2821 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2822 /* Use 1Mbps */ 2823 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2824 } else { 2825 /* broadcast or multicast packets */ 2826 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2827 txd->txdw1 |= htole32( 2828 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2829 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2830 2831 /* Force CCK1. */ 2832 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2833 /* Use 1Mbps */ 2834 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2835 } 2836 /* Set sequence number */ 2837 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2838 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2839 txd->txdseq |= htole16(seq); 2840 2841 if (!hasqos) { 2842 /* Use HW sequence numbering for non-QoS frames. */ 2843 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2844 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2845 } 2846 } else { 2847 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2848 R92E_HWSEQ_SHIFT); 2849 if (!hasqos) { 2850 /* Use HW sequence numbering for non-QoS frames. */ 2851 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2852 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2853 } 2854 } 2855 2856 /* Compute Tx descriptor checksum. */ 2857 sum = 0; 2858 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2859 sum ^= ((uint16_t *)txd)[i]; 2860 txd->txdsum = sum; /* NB: already little endian. */ 2861 2862 xferlen = txd_len + m->m_pkthdr.len + padsize; 2863 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2864 2865 s = splnet(); 2866 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2867 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2868 urtwn_txeof); 2869 error = usbd_transfer(data->xfer); 2870 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2871 error != USBD_IN_PROGRESS)) { 2872 splx(s); 2873 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2874 return error; 2875 } 2876 splx(s); 2877 return 0; 2878 } 2879 2880 struct urtwn_tx_data * 2881 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2882 { 2883 struct urtwn_tx_data *data = NULL; 2884 2885 mutex_enter(&sc->sc_tx_mtx); 2886 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2887 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2888 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2889 } 2890 mutex_exit(&sc->sc_tx_mtx); 2891 2892 return data; 2893 } 2894 2895 static void 2896 urtwn_start(struct ifnet *ifp) 2897 { 2898 struct urtwn_softc *sc = ifp->if_softc; 2899 struct ieee80211com *ic = &sc->sc_ic; 2900 struct urtwn_tx_data *data; 2901 struct ether_header *eh; 2902 struct ieee80211_node *ni; 2903 struct mbuf *m; 2904 2905 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2906 2907 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2908 return; 2909 2910 data = NULL; 2911 for (;;) { 2912 /* Send pending management frames first. */ 2913 IF_POLL(&ic->ic_mgtq, m); 2914 if (m != NULL) { 2915 /* Use AC_VO for management frames. */ 2916 2917 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2918 2919 if (data == NULL) { 2920 ifp->if_flags |= IFF_OACTIVE; 2921 DPRINTFN(DBG_TX, "empty tx_free_list", 2922 0, 0, 0, 0); 2923 return; 2924 } 2925 IF_DEQUEUE(&ic->ic_mgtq, m); 2926 ni = M_GETCTX(m, struct ieee80211_node *); 2927 M_CLEARCTX(m); 2928 goto sendit; 2929 } 2930 if (ic->ic_state != IEEE80211_S_RUN) 2931 break; 2932 2933 /* Encapsulate and send data frames. */ 2934 IFQ_POLL(&ifp->if_snd, m); 2935 if (m == NULL) 2936 break; 2937 2938 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2939 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2940 uint8_t qid = WME_AC_BE; 2941 if (ieee80211_has_qos(wh)) { 2942 /* data frames in 11n mode */ 2943 struct ieee80211_qosframe *qwh = (void *)wh; 2944 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2945 qid = TID_TO_WME_AC(tid); 2946 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2947 qid = WME_AC_VO; 2948 } 2949 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2950 2951 if (data == NULL) { 2952 ifp->if_flags |= IFF_OACTIVE; 2953 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2954 return; 2955 } 2956 IFQ_DEQUEUE(&ifp->if_snd, m); 2957 2958 if (m->m_len < (int)sizeof(*eh) && 2959 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2960 device_printf(sc->sc_dev, "m_pullup failed\n"); 2961 if_statinc(ifp, if_oerrors); 2962 urtwn_put_tx_data(sc, data); 2963 m_freem(m); 2964 continue; 2965 } 2966 eh = mtod(m, struct ether_header *); 2967 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2968 if (ni == NULL) { 2969 device_printf(sc->sc_dev, 2970 "unable to find transmit node\n"); 2971 if_statinc(ifp, if_oerrors); 2972 urtwn_put_tx_data(sc, data); 2973 m_freem(m); 2974 continue; 2975 } 2976 2977 bpf_mtap(ifp, m, BPF_D_OUT); 2978 2979 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2980 ieee80211_free_node(ni); 2981 device_printf(sc->sc_dev, 2982 "unable to encapsulate packet\n"); 2983 if_statinc(ifp, if_oerrors); 2984 urtwn_put_tx_data(sc, data); 2985 m_freem(m); 2986 continue; 2987 } 2988 sendit: 2989 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2990 2991 if (urtwn_tx(sc, m, ni, data) != 0) { 2992 m_freem(m); 2993 ieee80211_free_node(ni); 2994 device_printf(sc->sc_dev, 2995 "unable to transmit packet\n"); 2996 if_statinc(ifp, if_oerrors); 2997 continue; 2998 } 2999 m_freem(m); 3000 ieee80211_free_node(ni); 3001 sc->tx_timer = 5; 3002 ifp->if_timer = 1; 3003 } 3004 } 3005 3006 static void 3007 urtwn_watchdog(struct ifnet *ifp) 3008 { 3009 struct urtwn_softc *sc = ifp->if_softc; 3010 3011 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3012 3013 ifp->if_timer = 0; 3014 3015 if (sc->tx_timer > 0) { 3016 if (--sc->tx_timer == 0) { 3017 device_printf(sc->sc_dev, "device timeout\n"); 3018 /* urtwn_init(ifp); XXX needs a process context! */ 3019 if_statinc(ifp, if_oerrors); 3020 return; 3021 } 3022 ifp->if_timer = 1; 3023 } 3024 ieee80211_watchdog(&sc->sc_ic); 3025 } 3026 3027 static int 3028 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3029 { 3030 struct urtwn_softc *sc = ifp->if_softc; 3031 struct ieee80211com *ic = &sc->sc_ic; 3032 int s, error = 0; 3033 3034 URTWNHIST_FUNC(); 3035 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3036 0, 0); 3037 3038 s = splnet(); 3039 3040 switch (cmd) { 3041 case SIOCSIFFLAGS: 3042 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3043 break; 3044 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3045 case IFF_UP | IFF_RUNNING: 3046 break; 3047 case IFF_UP: 3048 urtwn_init(ifp); 3049 break; 3050 case IFF_RUNNING: 3051 urtwn_stop(ifp, 1); 3052 break; 3053 case 0: 3054 break; 3055 } 3056 break; 3057 3058 case SIOCADDMULTI: 3059 case SIOCDELMULTI: 3060 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3061 /* setup multicast filter, etc */ 3062 error = 0; 3063 } 3064 break; 3065 3066 case SIOCS80211CHANNEL: 3067 /* 3068 * This allows for fast channel switching in monitor mode 3069 * (used by kismet). In IBSS mode, we must explicitly reset 3070 * the interface to generate a new beacon frame. 3071 */ 3072 error = ieee80211_ioctl(ic, cmd, data); 3073 if (error == ENETRESET && 3074 ic->ic_opmode == IEEE80211_M_MONITOR) { 3075 urtwn_set_chan(sc, ic->ic_curchan, 3076 IEEE80211_HTINFO_2NDCHAN_NONE); 3077 error = 0; 3078 } 3079 break; 3080 3081 default: 3082 error = ieee80211_ioctl(ic, cmd, data); 3083 break; 3084 } 3085 if (error == ENETRESET) { 3086 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3087 (IFF_UP | IFF_RUNNING) && 3088 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3089 urtwn_init(ifp); 3090 } 3091 error = 0; 3092 } 3093 3094 splx(s); 3095 3096 return error; 3097 } 3098 3099 static __inline int 3100 urtwn_power_on(struct urtwn_softc *sc) 3101 { 3102 3103 return sc->sc_power_on(sc); 3104 } 3105 3106 static int 3107 urtwn_r92c_power_on(struct urtwn_softc *sc) 3108 { 3109 uint32_t reg; 3110 int ntries; 3111 3112 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3113 3114 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3115 3116 /* Wait for autoload done bit. */ 3117 for (ntries = 0; ntries < 1000; ntries++) { 3118 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3119 break; 3120 DELAY(5); 3121 } 3122 if (ntries == 1000) { 3123 aprint_error_dev(sc->sc_dev, 3124 "timeout waiting for chip autoload\n"); 3125 return ETIMEDOUT; 3126 } 3127 3128 /* Unlock ISO/CLK/Power control register. */ 3129 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3130 DELAY(5); 3131 /* Move SPS into PWM mode. */ 3132 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3133 DELAY(5); 3134 3135 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3136 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3137 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3138 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3139 DELAY(100); 3140 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3141 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3142 ~R92C_SYS_ISO_CTRL_MD2PP); 3143 } 3144 3145 /* Auto enable WLAN. */ 3146 urtwn_write_2(sc, R92C_APS_FSMCO, 3147 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3148 for (ntries = 0; ntries < 1000; ntries++) { 3149 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3150 R92C_APS_FSMCO_APFM_ONMAC)) 3151 break; 3152 DELAY(100); 3153 } 3154 if (ntries == 1000) { 3155 aprint_error_dev(sc->sc_dev, 3156 "timeout waiting for MAC auto ON\n"); 3157 return ETIMEDOUT; 3158 } 3159 3160 /* Enable radio, GPIO and LED functions. */ 3161 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3162 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3163 urtwn_write_2(sc, R92C_APS_FSMCO, 3164 R92C_APS_FSMCO_AFSM_HSUS | 3165 R92C_APS_FSMCO_PDN_EN | 3166 R92C_APS_FSMCO_PFM_ALDN); 3167 3168 /* Release RF digital isolation. */ 3169 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3170 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3171 3172 /* Initialize MAC. */ 3173 urtwn_write_1(sc, R92C_APSD_CTRL, 3174 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3175 for (ntries = 0; ntries < 200; ntries++) { 3176 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3177 R92C_APSD_CTRL_OFF_STATUS)) 3178 break; 3179 DELAY(5); 3180 } 3181 if (ntries == 200) { 3182 aprint_error_dev(sc->sc_dev, 3183 "timeout waiting for MAC initialization\n"); 3184 return ETIMEDOUT; 3185 } 3186 3187 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3188 reg = urtwn_read_2(sc, R92C_CR); 3189 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3190 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3191 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3192 R92C_CR_ENSEC; 3193 urtwn_write_2(sc, R92C_CR, reg); 3194 3195 urtwn_write_1(sc, 0xfe10, 0x19); 3196 3197 urtwn_delay_ms(sc, 1); 3198 3199 return 0; 3200 } 3201 3202 static int 3203 urtwn_r92e_power_on(struct urtwn_softc *sc) 3204 { 3205 uint32_t reg; 3206 uint32_t val; 3207 int ntries; 3208 3209 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3210 3211 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3212 3213 /* Enable radio, GPIO and LED functions. */ 3214 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3215 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3216 urtwn_write_2(sc, R92C_APS_FSMCO, 3217 R92C_APS_FSMCO_AFSM_HSUS | 3218 R92C_APS_FSMCO_PDN_EN | 3219 R92C_APS_FSMCO_PFM_ALDN); 3220 3221 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3222 /* LDO. */ 3223 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3224 } 3225 else { 3226 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3227 R92C_SYS_SWR_CTRL2) & 0xffff); 3228 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3229 } 3230 3231 for (ntries = 0; ntries < 2; ntries++) { 3232 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3233 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3234 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3235 R92C_AFE_CTRL4)); 3236 } 3237 3238 /* Reset BB. */ 3239 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3240 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3241 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3242 3243 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3244 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3245 3246 /* Disable HWPDN. */ 3247 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3248 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3249 3250 /* Disable WL suspend. */ 3251 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3252 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3253 R92C_APS_FSMCO_AFSM_HSUS)); 3254 3255 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3256 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3257 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3258 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3259 for (ntries = 0; ntries < 10000; ntries++) { 3260 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3261 R92C_APS_FSMCO_APFM_ONMAC; 3262 if (val == 0x0) 3263 break; 3264 DELAY(10); 3265 } 3266 if (ntries == 10000) { 3267 aprint_error_dev(sc->sc_dev, 3268 "timeout waiting for chip power up\n"); 3269 return ETIMEDOUT; 3270 } 3271 3272 urtwn_write_2(sc, R92C_CR, 0x00); 3273 reg = urtwn_read_2(sc, R92C_CR); 3274 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3275 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3276 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3277 urtwn_write_2(sc, R92C_CR, reg); 3278 3279 return 0; 3280 } 3281 3282 static int 3283 urtwn_r88e_power_on(struct urtwn_softc *sc) 3284 { 3285 uint32_t reg; 3286 uint8_t val; 3287 int ntries; 3288 3289 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3290 3291 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3292 3293 /* Wait for power ready bit. */ 3294 for (ntries = 0; ntries < 5000; ntries++) { 3295 val = urtwn_read_1(sc, 0x6) & 0x2; 3296 if (val == 0x2) 3297 break; 3298 DELAY(10); 3299 } 3300 if (ntries == 5000) { 3301 aprint_error_dev(sc->sc_dev, 3302 "timeout waiting for chip power up\n"); 3303 return ETIMEDOUT; 3304 } 3305 3306 /* Reset BB. */ 3307 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3308 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3309 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3310 3311 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3312 3313 /* Disable HWPDN. */ 3314 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3315 3316 /* Disable WL suspend. */ 3317 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3318 3319 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3320 for (ntries = 0; ntries < 5000; ntries++) { 3321 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3322 break; 3323 DELAY(10); 3324 } 3325 if (ntries == 5000) 3326 return ETIMEDOUT; 3327 3328 /* Enable LDO normal mode. */ 3329 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3330 3331 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3332 urtwn_write_2(sc, R92C_CR, 0); 3333 reg = urtwn_read_2(sc, R92C_CR); 3334 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3335 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3336 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3337 urtwn_write_2(sc, R92C_CR, reg); 3338 3339 return 0; 3340 } 3341 3342 static int __noinline 3343 urtwn_llt_init(struct urtwn_softc *sc) 3344 { 3345 size_t i, page_count, pktbuf_count; 3346 uint32_t val; 3347 int error; 3348 3349 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3350 3351 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3352 3353 if (sc->chip & URTWN_CHIP_88E) 3354 page_count = R88E_TX_PAGE_COUNT; 3355 else if (sc->chip & URTWN_CHIP_92EU) 3356 page_count = R92E_TX_PAGE_COUNT; 3357 else 3358 page_count = R92C_TX_PAGE_COUNT; 3359 if (sc->chip & URTWN_CHIP_88E) 3360 pktbuf_count = R88E_TXPKTBUF_COUNT; 3361 else if (sc->chip & URTWN_CHIP_92EU) 3362 pktbuf_count = R88E_TXPKTBUF_COUNT; 3363 else 3364 pktbuf_count = R92C_TXPKTBUF_COUNT; 3365 3366 if (sc->chip & URTWN_CHIP_92EU) { 3367 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3368 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3369 DELAY(100); 3370 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3371 if (val & R92E_AUTO_LLT_EN) 3372 return EIO; 3373 return 0; 3374 } 3375 3376 /* Reserve pages [0; page_count]. */ 3377 for (i = 0; i < page_count; i++) { 3378 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3379 return error; 3380 } 3381 /* NB: 0xff indicates end-of-list. */ 3382 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3383 return error; 3384 /* 3385 * Use pages [page_count + 1; pktbuf_count - 1] 3386 * as ring buffer. 3387 */ 3388 for (++i; i < pktbuf_count - 1; i++) { 3389 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3390 return error; 3391 } 3392 /* Make the last page point to the beginning of the ring buffer. */ 3393 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3394 return error; 3395 } 3396 3397 static void 3398 urtwn_fw_reset(struct urtwn_softc *sc) 3399 { 3400 uint16_t reg; 3401 int ntries; 3402 3403 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3404 3405 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3406 3407 /* Tell 8051 to reset itself. */ 3408 mutex_enter(&sc->sc_fwcmd_mtx); 3409 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3410 sc->fwcur = 0; 3411 mutex_exit(&sc->sc_fwcmd_mtx); 3412 3413 /* Wait until 8051 resets by itself. */ 3414 for (ntries = 0; ntries < 100; ntries++) { 3415 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3416 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3417 return; 3418 DELAY(50); 3419 } 3420 /* Force 8051 reset. */ 3421 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3422 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3423 } 3424 3425 static void 3426 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3427 { 3428 uint16_t reg; 3429 3430 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3431 3432 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3433 3434 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3435 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3436 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3437 } 3438 DELAY(50); 3439 3440 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3441 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3442 DELAY(50); 3443 3444 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3445 DELAY(50); 3446 3447 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3448 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3449 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3450 } 3451 DELAY(50); 3452 3453 mutex_enter(&sc->sc_fwcmd_mtx); 3454 /* Init firmware commands ring. */ 3455 sc->fwcur = 0; 3456 mutex_exit(&sc->sc_fwcmd_mtx); 3457 3458 } 3459 3460 static int 3461 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3462 { 3463 uint32_t reg; 3464 int off, mlen, error = 0; 3465 3466 URTWNHIST_FUNC(); 3467 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3468 page, (uintptr_t)buf, len, 0); 3469 3470 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3471 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3472 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3473 3474 off = R92C_FW_START_ADDR; 3475 while (len > 0) { 3476 if (len > 196) 3477 mlen = 196; 3478 else if (len > 4) 3479 mlen = 4; 3480 else 3481 mlen = 1; 3482 error = urtwn_write_region(sc, off, buf, mlen); 3483 if (error != 0) 3484 break; 3485 off += mlen; 3486 buf += mlen; 3487 len -= mlen; 3488 } 3489 return error; 3490 } 3491 3492 static int __noinline 3493 urtwn_load_firmware(struct urtwn_softc *sc) 3494 { 3495 firmware_handle_t fwh; 3496 const struct r92c_fw_hdr *hdr; 3497 const char *name; 3498 u_char *fw, *ptr; 3499 size_t len; 3500 uint32_t reg; 3501 int mlen, ntries, page, error; 3502 3503 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3504 3505 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3506 3507 /* Read firmware image from the filesystem. */ 3508 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3509 name = "rtl8188eufw.bin"; 3510 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3511 name = "rtl8192eefw.bin"; 3512 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3513 URTWN_CHIP_UMC_A_CUT) 3514 name = "rtl8192cfwU.bin"; 3515 else 3516 name = "rtl8192cfw.bin"; 3517 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3518 aprint_error_dev(sc->sc_dev, 3519 "failed load firmware of file %s (error %d)\n", name, 3520 error); 3521 return error; 3522 } 3523 const size_t fwlen = len = firmware_get_size(fwh); 3524 fw = firmware_malloc(len); 3525 if (fw == NULL) { 3526 aprint_error_dev(sc->sc_dev, 3527 "failed to allocate firmware memory\n"); 3528 firmware_close(fwh); 3529 return ENOMEM; 3530 } 3531 error = firmware_read(fwh, 0, fw, len); 3532 firmware_close(fwh); 3533 if (error != 0) { 3534 aprint_error_dev(sc->sc_dev, 3535 "failed to read firmware (error %d)\n", error); 3536 firmware_free(fw, fwlen); 3537 return error; 3538 } 3539 3540 len = fwlen; 3541 ptr = fw; 3542 hdr = (const struct r92c_fw_hdr *)ptr; 3543 /* Check if there is a valid FW header and skip it. */ 3544 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3545 (le16toh(hdr->signature) >> 4) == 0x88e || 3546 (le16toh(hdr->signature) >> 4) == 0x92e || 3547 (le16toh(hdr->signature) >> 4) == 0x92c) { 3548 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3549 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3550 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3551 hdr->month, hdr->date, hdr->hour, hdr->minute); 3552 ptr += sizeof(*hdr); 3553 len -= sizeof(*hdr); 3554 } 3555 3556 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3557 /* Reset MCU ready status */ 3558 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3559 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3560 ISSET(sc->chip, URTWN_CHIP_92EU)) 3561 urtwn_r88e_fw_reset(sc); 3562 else 3563 urtwn_fw_reset(sc); 3564 } 3565 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3566 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3567 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3568 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3569 R92C_SYS_FUNC_EN_CPUEN); 3570 } 3571 3572 /* download enabled */ 3573 urtwn_write_1(sc, R92C_MCUFWDL, 3574 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3575 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3576 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3577 3578 /* Reset the FWDL checksum. */ 3579 urtwn_write_1(sc, R92C_MCUFWDL, 3580 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3581 3582 DELAY(50); 3583 /* download firmware */ 3584 for (page = 0; len > 0; page++) { 3585 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3586 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3587 if (error != 0) { 3588 aprint_error_dev(sc->sc_dev, 3589 "could not load firmware page %d\n", page); 3590 goto fail; 3591 } 3592 ptr += mlen; 3593 len -= mlen; 3594 } 3595 3596 /* download disable */ 3597 urtwn_write_1(sc, R92C_MCUFWDL, 3598 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3599 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3600 3601 /* Wait for checksum report. */ 3602 for (ntries = 0; ntries < 1000; ntries++) { 3603 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3604 break; 3605 DELAY(5); 3606 } 3607 if (ntries == 1000) { 3608 aprint_error_dev(sc->sc_dev, 3609 "timeout waiting for checksum report\n"); 3610 error = ETIMEDOUT; 3611 goto fail; 3612 } 3613 3614 /* Wait for firmware readiness. */ 3615 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3616 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3617 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3618 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3619 ISSET(sc->chip, URTWN_CHIP_92EU)) 3620 urtwn_r88e_fw_reset(sc); 3621 for (ntries = 0; ntries < 6000; ntries++) { 3622 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3623 break; 3624 DELAY(5); 3625 } 3626 if (ntries == 6000) { 3627 aprint_error_dev(sc->sc_dev, 3628 "timeout waiting for firmware readiness\n"); 3629 error = ETIMEDOUT; 3630 goto fail; 3631 } 3632 fail: 3633 firmware_free(fw, fwlen); 3634 return error; 3635 } 3636 3637 static __inline int 3638 urtwn_dma_init(struct urtwn_softc *sc) 3639 { 3640 3641 return sc->sc_dma_init(sc); 3642 } 3643 3644 static int 3645 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3646 { 3647 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3648 uint32_t reg; 3649 int error; 3650 3651 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3652 3653 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3654 3655 /* Initialize LLT table. */ 3656 error = urtwn_llt_init(sc); 3657 if (error != 0) 3658 return error; 3659 3660 /* Get Tx queues to USB endpoints mapping. */ 3661 hashq = hasnq = haslq = 0; 3662 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3663 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3664 if (MS(reg, R92C_USB_EP_HQ) != 0) 3665 hashq = 1; 3666 if (MS(reg, R92C_USB_EP_NQ) != 0) 3667 hasnq = 1; 3668 if (MS(reg, R92C_USB_EP_LQ) != 0) 3669 haslq = 1; 3670 nqueues = hashq + hasnq + haslq; 3671 if (nqueues == 0) 3672 return EIO; 3673 /* Get the number of pages for each queue. */ 3674 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3675 /* The remaining pages are assigned to the high priority queue. */ 3676 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3677 3678 /* Set number of pages for normal priority queue. */ 3679 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3680 urtwn_write_4(sc, R92C_RQPN, 3681 /* Set number of pages for public queue. */ 3682 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3683 /* Set number of pages for high priority queue. */ 3684 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3685 /* Set number of pages for low priority queue. */ 3686 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3687 /* Load values. */ 3688 R92C_RQPN_LD); 3689 3690 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3691 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3692 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3693 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3694 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3695 3696 /* Set queue to USB pipe mapping. */ 3697 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3698 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3699 if (nqueues == 1) { 3700 if (hashq) { 3701 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3702 } else if (hasnq) { 3703 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3704 } else { 3705 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3706 } 3707 } else if (nqueues == 2) { 3708 /* All 2-endpoints configs have a high priority queue. */ 3709 if (!hashq) { 3710 return EIO; 3711 } 3712 if (hasnq) { 3713 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3714 } else { 3715 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3716 } 3717 } else { 3718 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3719 } 3720 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3721 3722 /* Set Tx/Rx transfer page boundary. */ 3723 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3724 3725 /* Set Tx/Rx transfer page size. */ 3726 urtwn_write_1(sc, R92C_PBP, 3727 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3728 return 0; 3729 } 3730 3731 static int 3732 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3733 { 3734 usb_interface_descriptor_t *id; 3735 uint32_t reg; 3736 int nqueues; 3737 int error; 3738 3739 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3740 3741 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3742 3743 /* Initialize LLT table. */ 3744 error = urtwn_llt_init(sc); 3745 if (error != 0) 3746 return error; 3747 3748 /* Get Tx queues to USB endpoints mapping. */ 3749 id = usbd_get_interface_descriptor(sc->sc_iface); 3750 nqueues = id->bNumEndpoints - 1; 3751 if (nqueues == 0) 3752 return EIO; 3753 3754 /* Set number of pages for normal priority queue. */ 3755 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3756 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3757 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3758 3759 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3760 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3761 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3762 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3763 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3764 3765 /* Set queue to USB pipe mapping. */ 3766 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3767 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3768 if (nqueues == 1) 3769 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3770 else if (nqueues == 2) 3771 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3772 else 3773 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3774 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3775 3776 /* Set Tx/Rx transfer page boundary. */ 3777 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3778 3779 /* Set Tx/Rx transfer page size. */ 3780 urtwn_write_1(sc, R92C_PBP, 3781 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3782 3783 return 0; 3784 } 3785 3786 static void __noinline 3787 urtwn_mac_init(struct urtwn_softc *sc) 3788 { 3789 size_t i; 3790 3791 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3792 3793 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3794 3795 /* Write MAC initialization values. */ 3796 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3797 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3798 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3799 rtl8188eu_mac[i].val); 3800 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3801 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3802 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3803 rtl8192eu_mac[i].val); 3804 } else { 3805 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3806 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3807 rtl8192cu_mac[i].val); 3808 } 3809 } 3810 3811 static void __noinline 3812 urtwn_bb_init(struct urtwn_softc *sc) 3813 { 3814 const struct rtwn_bb_prog *prog; 3815 uint32_t reg; 3816 uint8_t crystalcap; 3817 size_t i; 3818 3819 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3820 3821 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3822 3823 /* Enable BB and RF. */ 3824 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3825 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3826 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3827 R92C_SYS_FUNC_EN_DIO_RF); 3828 3829 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3830 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3831 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3832 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3833 } 3834 3835 urtwn_write_1(sc, R92C_RF_CTRL, 3836 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3837 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3838 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3839 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3840 3841 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3842 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3843 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3844 urtwn_write_1(sc, 0x15, 0xe9); 3845 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3846 } 3847 3848 /* Select BB programming based on board type. */ 3849 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3850 prog = &rtl8188eu_bb_prog; 3851 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3852 prog = &rtl8192eu_bb_prog; 3853 else if (!(sc->chip & URTWN_CHIP_92C)) { 3854 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3855 prog = &rtl8188ce_bb_prog; 3856 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3857 prog = &rtl8188ru_bb_prog; 3858 } else { 3859 prog = &rtl8188cu_bb_prog; 3860 } 3861 } else { 3862 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3863 prog = &rtl8192ce_bb_prog; 3864 } else { 3865 prog = &rtl8192cu_bb_prog; 3866 } 3867 } 3868 /* Write BB initialization values. */ 3869 for (i = 0; i < prog->count; i++) { 3870 /* additional delay depend on registers */ 3871 switch (prog->regs[i]) { 3872 case 0xfe: 3873 urtwn_delay_ms(sc, 50); 3874 break; 3875 case 0xfd: 3876 urtwn_delay_ms(sc, 5); 3877 break; 3878 case 0xfc: 3879 urtwn_delay_ms(sc, 1); 3880 break; 3881 case 0xfb: 3882 DELAY(50); 3883 break; 3884 case 0xfa: 3885 DELAY(5); 3886 break; 3887 case 0xf9: 3888 DELAY(1); 3889 break; 3890 } 3891 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3892 DELAY(1); 3893 } 3894 3895 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3896 /* 8192C 1T only configuration. */ 3897 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3898 reg = (reg & ~0x00000003) | 0x2; 3899 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3900 3901 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3902 reg = (reg & ~0x00300033) | 0x00200022; 3903 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3904 3905 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3906 reg = (reg & ~0xff000000) | (0x45 << 24); 3907 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3908 3909 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3910 reg = (reg & ~0x000000ff) | 0x23; 3911 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3912 3913 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3914 reg = (reg & ~0x00000030) | (1 << 4); 3915 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3916 3917 reg = urtwn_bb_read(sc, 0xe74); 3918 reg = (reg & ~0x0c000000) | (2 << 26); 3919 urtwn_bb_write(sc, 0xe74, reg); 3920 reg = urtwn_bb_read(sc, 0xe78); 3921 reg = (reg & ~0x0c000000) | (2 << 26); 3922 urtwn_bb_write(sc, 0xe78, reg); 3923 reg = urtwn_bb_read(sc, 0xe7c); 3924 reg = (reg & ~0x0c000000) | (2 << 26); 3925 urtwn_bb_write(sc, 0xe7c, reg); 3926 reg = urtwn_bb_read(sc, 0xe80); 3927 reg = (reg & ~0x0c000000) | (2 << 26); 3928 urtwn_bb_write(sc, 0xe80, reg); 3929 reg = urtwn_bb_read(sc, 0xe88); 3930 reg = (reg & ~0x0c000000) | (2 << 26); 3931 urtwn_bb_write(sc, 0xe88, reg); 3932 } 3933 3934 /* Write AGC values. */ 3935 for (i = 0; i < prog->agccount; i++) { 3936 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3937 DELAY(1); 3938 } 3939 3940 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3941 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3942 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3943 DELAY(1); 3944 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3945 DELAY(1); 3946 } 3947 3948 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3949 crystalcap = sc->r88e_rom[0xb9]; 3950 if (crystalcap == 0x00) 3951 crystalcap = 0x20; 3952 crystalcap &= 0x3f; 3953 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3954 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3955 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3956 crystalcap | crystalcap << 6)); 3957 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3958 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3959 crystalcap = sc->r88e_rom[0xb9]; 3960 if (crystalcap == 0xff) 3961 crystalcap = 0x20; 3962 crystalcap &= 0x3f; 3963 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3964 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3965 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3966 crystalcap | crystalcap << 6)); 3967 } else { 3968 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3969 R92C_HSSI_PARAM2_CCK_HIPWR) { 3970 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3971 } 3972 } 3973 } 3974 3975 static void __noinline 3976 urtwn_rf_init(struct urtwn_softc *sc) 3977 { 3978 const struct rtwn_rf_prog *prog; 3979 uint32_t reg, mask, saved; 3980 size_t i, j, idx; 3981 3982 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3983 3984 /* Select RF programming based on board type. */ 3985 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3986 prog = rtl8188eu_rf_prog; 3987 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3988 prog = rtl8192eu_rf_prog; 3989 else if (!(sc->chip & URTWN_CHIP_92C)) { 3990 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3991 prog = rtl8188ce_rf_prog; 3992 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3993 prog = rtl8188ru_rf_prog; 3994 } else { 3995 prog = rtl8188cu_rf_prog; 3996 } 3997 } else { 3998 prog = rtl8192ce_rf_prog; 3999 } 4000 4001 for (i = 0; i < sc->nrxchains; i++) { 4002 /* Save RF_ENV control type. */ 4003 idx = i / 2; 4004 mask = 0xffffU << ((i % 2) * 16); 4005 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4006 4007 /* Set RF_ENV enable. */ 4008 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4009 reg |= 0x100000; 4010 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4011 DELAY(50); 4012 4013 /* Set RF_ENV output high. */ 4014 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4015 reg |= 0x10; 4016 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4017 DELAY(50); 4018 4019 /* Set address and data lengths of RF registers. */ 4020 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4021 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4022 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4023 DELAY(50); 4024 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4025 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4026 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4027 DELAY(50); 4028 4029 /* Write RF initialization values for this chain. */ 4030 for (j = 0; j < prog[i].count; j++) { 4031 if (prog[i].regs[j] >= 0xf9 && 4032 prog[i].regs[j] <= 0xfe) { 4033 /* 4034 * These are fake RF registers offsets that 4035 * indicate a delay is required. 4036 */ 4037 urtwn_delay_ms(sc, 50); 4038 continue; 4039 } 4040 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4041 DELAY(5); 4042 } 4043 4044 /* Restore RF_ENV control type. */ 4045 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4046 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4047 } 4048 4049 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4050 URTWN_CHIP_UMC_A_CUT) { 4051 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4052 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4053 } 4054 4055 /* Cache RF register CHNLBW. */ 4056 for (i = 0; i < 2; i++) { 4057 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4058 } 4059 } 4060 4061 static void __noinline 4062 urtwn_cam_init(struct urtwn_softc *sc) 4063 { 4064 uint32_t content, command; 4065 uint8_t idx; 4066 size_t i; 4067 4068 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4069 4070 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4071 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4072 return; 4073 4074 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4075 content = (idx & 3) 4076 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4077 | R92C_CAM_VALID; 4078 4079 command = R92C_CAMCMD_POLLING 4080 | R92C_CAMCMD_WRITE 4081 | R92C_CAM_CTL0(idx); 4082 4083 urtwn_write_4(sc, R92C_CAMWRITE, content); 4084 urtwn_write_4(sc, R92C_CAMCMD, command); 4085 } 4086 4087 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4088 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4089 if (i == 0) { 4090 content = (idx & 3) 4091 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4092 | R92C_CAM_VALID; 4093 } else { 4094 content = 0; 4095 } 4096 4097 command = R92C_CAMCMD_POLLING 4098 | R92C_CAMCMD_WRITE 4099 | R92C_CAM_CTL0(idx) 4100 | i; 4101 4102 urtwn_write_4(sc, R92C_CAMWRITE, content); 4103 urtwn_write_4(sc, R92C_CAMCMD, command); 4104 } 4105 } 4106 4107 /* Invalidate all CAM entries. */ 4108 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4109 } 4110 4111 static void __noinline 4112 urtwn_pa_bias_init(struct urtwn_softc *sc) 4113 { 4114 uint8_t reg; 4115 size_t i; 4116 4117 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4118 4119 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4120 4121 for (i = 0; i < sc->nrxchains; i++) { 4122 if (sc->pa_setting & (1U << i)) 4123 continue; 4124 4125 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4126 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4127 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4128 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4129 } 4130 if (!(sc->pa_setting & 0x10)) { 4131 reg = urtwn_read_1(sc, 0x16); 4132 reg = (reg & ~0xf0) | 0x90; 4133 urtwn_write_1(sc, 0x16, reg); 4134 } 4135 } 4136 4137 static void __noinline 4138 urtwn_rxfilter_init(struct urtwn_softc *sc) 4139 { 4140 4141 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4142 4143 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4144 4145 /* Initialize Rx filter. */ 4146 /* TODO: use better filter for monitor mode. */ 4147 urtwn_write_4(sc, R92C_RCR, 4148 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4149 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4150 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4151 /* Accept all multicast frames. */ 4152 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4153 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4154 /* Accept all management frames. */ 4155 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4156 /* Reject all control frames. */ 4157 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4158 /* Accept all data frames. */ 4159 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4160 } 4161 4162 static void __noinline 4163 urtwn_edca_init(struct urtwn_softc *sc) 4164 { 4165 4166 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4167 4168 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4169 4170 /* set spec SIFS (used in NAV) */ 4171 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4172 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4173 4174 /* set SIFS CCK/OFDM */ 4175 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4176 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4177 4178 /* TXOP */ 4179 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4180 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4181 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4182 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4183 } 4184 4185 static void 4186 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4187 uint16_t power[URTWN_RIDX_COUNT]) 4188 { 4189 uint32_t reg; 4190 4191 URTWNHIST_FUNC(); 4192 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4193 4194 /* Write per-CCK rate Tx power. */ 4195 if (chain == 0) { 4196 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4197 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4198 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4199 4200 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4201 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4202 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4203 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4204 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4205 } else { 4206 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4207 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4208 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4209 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4210 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4211 4212 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4213 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4214 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4215 } 4216 /* Write per-OFDM rate Tx power. */ 4217 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4218 SM(R92C_TXAGC_RATE06, power[ 4]) | 4219 SM(R92C_TXAGC_RATE09, power[ 5]) | 4220 SM(R92C_TXAGC_RATE12, power[ 6]) | 4221 SM(R92C_TXAGC_RATE18, power[ 7])); 4222 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4223 SM(R92C_TXAGC_RATE24, power[ 8]) | 4224 SM(R92C_TXAGC_RATE36, power[ 9]) | 4225 SM(R92C_TXAGC_RATE48, power[10]) | 4226 SM(R92C_TXAGC_RATE54, power[11])); 4227 /* Write per-MCS Tx power. */ 4228 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4229 SM(R92C_TXAGC_MCS00, power[12]) | 4230 SM(R92C_TXAGC_MCS01, power[13]) | 4231 SM(R92C_TXAGC_MCS02, power[14]) | 4232 SM(R92C_TXAGC_MCS03, power[15])); 4233 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4234 SM(R92C_TXAGC_MCS04, power[16]) | 4235 SM(R92C_TXAGC_MCS05, power[17]) | 4236 SM(R92C_TXAGC_MCS06, power[18]) | 4237 SM(R92C_TXAGC_MCS07, power[19])); 4238 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4239 SM(R92C_TXAGC_MCS08, power[20]) | 4240 SM(R92C_TXAGC_MCS09, power[21]) | 4241 SM(R92C_TXAGC_MCS10, power[22]) | 4242 SM(R92C_TXAGC_MCS11, power[23])); 4243 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4244 SM(R92C_TXAGC_MCS12, power[24]) | 4245 SM(R92C_TXAGC_MCS13, power[25]) | 4246 SM(R92C_TXAGC_MCS14, power[26]) | 4247 SM(R92C_TXAGC_MCS15, power[27])); 4248 } 4249 4250 static void 4251 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4252 uint16_t power[URTWN_RIDX_COUNT]) 4253 { 4254 struct r92c_rom *rom = &sc->rom; 4255 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4256 const struct rtwn_txpwr *base; 4257 int ridx, group; 4258 4259 URTWNHIST_FUNC(); 4260 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4261 4262 /* Determine channel group. */ 4263 if (chan <= 3) { 4264 group = 0; 4265 } else if (chan <= 9) { 4266 group = 1; 4267 } else { 4268 group = 2; 4269 } 4270 4271 /* Get original Tx power based on board type and RF chain. */ 4272 if (!(sc->chip & URTWN_CHIP_92C)) { 4273 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4274 base = &rtl8188ru_txagc[chain]; 4275 } else { 4276 base = &rtl8192cu_txagc[chain]; 4277 } 4278 } else { 4279 base = &rtl8192cu_txagc[chain]; 4280 } 4281 4282 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4283 if (sc->regulatory == 0) { 4284 for (ridx = 0; ridx <= 3; ridx++) { 4285 power[ridx] = base->pwr[0][ridx]; 4286 } 4287 } 4288 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4289 if (sc->regulatory == 3) { 4290 power[ridx] = base->pwr[0][ridx]; 4291 /* Apply vendor limits. */ 4292 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4293 maxpow = rom->ht40_max_pwr[group]; 4294 } else { 4295 maxpow = rom->ht20_max_pwr[group]; 4296 } 4297 maxpow = (maxpow >> (chain * 4)) & 0xf; 4298 if (power[ridx] > maxpow) { 4299 power[ridx] = maxpow; 4300 } 4301 } else if (sc->regulatory == 1) { 4302 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4303 power[ridx] = base->pwr[group][ridx]; 4304 } 4305 } else if (sc->regulatory != 2) { 4306 power[ridx] = base->pwr[0][ridx]; 4307 } 4308 } 4309 4310 /* Compute per-CCK rate Tx power. */ 4311 cckpow = rom->cck_tx_pwr[chain][group]; 4312 for (ridx = 0; ridx <= 3; ridx++) { 4313 power[ridx] += cckpow; 4314 if (power[ridx] > R92C_MAX_TX_PWR) { 4315 power[ridx] = R92C_MAX_TX_PWR; 4316 } 4317 } 4318 4319 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4320 if (sc->ntxchains > 1) { 4321 /* Apply reduction for 2 spatial streams. */ 4322 diff = rom->ht40_2s_tx_pwr_diff[group]; 4323 diff = (diff >> (chain * 4)) & 0xf; 4324 htpow = (htpow > diff) ? htpow - diff : 0; 4325 } 4326 4327 /* Compute per-OFDM rate Tx power. */ 4328 diff = rom->ofdm_tx_pwr_diff[group]; 4329 diff = (diff >> (chain * 4)) & 0xf; 4330 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4331 for (ridx = 4; ridx <= 11; ridx++) { 4332 power[ridx] += ofdmpow; 4333 if (power[ridx] > R92C_MAX_TX_PWR) { 4334 power[ridx] = R92C_MAX_TX_PWR; 4335 } 4336 } 4337 4338 /* Compute per-MCS Tx power. */ 4339 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4340 diff = rom->ht20_tx_pwr_diff[group]; 4341 diff = (diff >> (chain * 4)) & 0xf; 4342 htpow += diff; /* HT40->HT20 correction. */ 4343 } 4344 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4345 power[ridx] += htpow; 4346 if (power[ridx] > R92C_MAX_TX_PWR) { 4347 power[ridx] = R92C_MAX_TX_PWR; 4348 } 4349 } 4350 #ifdef URTWN_DEBUG 4351 if (urtwn_debug & DBG_RF) { 4352 /* Dump per-rate Tx power values. */ 4353 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4354 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4355 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4356 } 4357 #endif 4358 } 4359 4360 void 4361 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4362 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4363 { 4364 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4365 const struct rtwn_r88e_txpwr *base; 4366 int ridx, group; 4367 4368 URTWNHIST_FUNC(); 4369 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4370 4371 /* Determine channel group. */ 4372 if (chan <= 2) 4373 group = 0; 4374 else if (chan <= 5) 4375 group = 1; 4376 else if (chan <= 8) 4377 group = 2; 4378 else if (chan <= 11) 4379 group = 3; 4380 else if (chan <= 13) 4381 group = 4; 4382 else 4383 group = 5; 4384 4385 /* Get original Tx power based on board type and RF chain. */ 4386 base = &rtl8188eu_txagc[chain]; 4387 4388 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4389 if (sc->regulatory == 0) { 4390 for (ridx = 0; ridx <= 3; ridx++) 4391 power[ridx] = base->pwr[0][ridx]; 4392 } 4393 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4394 if (sc->regulatory == 3) 4395 power[ridx] = base->pwr[0][ridx]; 4396 else if (sc->regulatory == 1) { 4397 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4398 power[ridx] = base->pwr[group][ridx]; 4399 } else if (sc->regulatory != 2) 4400 power[ridx] = base->pwr[0][ridx]; 4401 } 4402 4403 /* Compute per-CCK rate Tx power. */ 4404 cckpow = sc->cck_tx_pwr[group]; 4405 for (ridx = 0; ridx <= 3; ridx++) { 4406 power[ridx] += cckpow; 4407 if (power[ridx] > R92C_MAX_TX_PWR) 4408 power[ridx] = R92C_MAX_TX_PWR; 4409 } 4410 4411 htpow = sc->ht40_tx_pwr[group]; 4412 4413 /* Compute per-OFDM rate Tx power. */ 4414 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4415 for (ridx = 4; ridx <= 11; ridx++) { 4416 power[ridx] += ofdmpow; 4417 if (power[ridx] > R92C_MAX_TX_PWR) 4418 power[ridx] = R92C_MAX_TX_PWR; 4419 } 4420 4421 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4422 for (ridx = 12; ridx <= 27; ridx++) { 4423 power[ridx] += bw20pow; 4424 if (power[ridx] > R92C_MAX_TX_PWR) 4425 power[ridx] = R92C_MAX_TX_PWR; 4426 } 4427 } 4428 4429 static void 4430 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4431 { 4432 uint16_t power[URTWN_RIDX_COUNT]; 4433 size_t i; 4434 4435 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4436 4437 for (i = 0; i < sc->ntxchains; i++) { 4438 /* Compute per-rate Tx power values. */ 4439 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4440 ISSET(sc->chip, URTWN_CHIP_92EU)) 4441 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4442 else 4443 urtwn_get_txpower(sc, i, chan, ht40m, power); 4444 /* Write per-rate Tx power values to hardware. */ 4445 urtwn_write_txpower(sc, i, power); 4446 } 4447 } 4448 4449 static void __noinline 4450 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4451 { 4452 struct ieee80211com *ic = &sc->sc_ic; 4453 u_int chan; 4454 size_t i; 4455 4456 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4457 4458 URTWNHIST_FUNC(); 4459 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4460 4461 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4462 4463 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4464 chan += 2; 4465 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4466 chan -= 2; 4467 } 4468 4469 /* Set Tx power for this new channel. */ 4470 urtwn_set_txpower(sc, chan, ht40m); 4471 4472 for (i = 0; i < sc->nrxchains; i++) { 4473 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4474 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4475 } 4476 4477 if (ht40m) { 4478 /* Is secondary channel below or above primary? */ 4479 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4480 uint32_t reg; 4481 4482 urtwn_write_1(sc, R92C_BWOPMODE, 4483 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4484 4485 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4486 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4487 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4488 4489 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4490 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4491 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4492 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4493 4494 /* Set CCK side band. */ 4495 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4496 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4497 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4498 4499 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4500 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4501 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4502 4503 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4504 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4505 ~R92C_FPGA0_ANAPARAM2_CBW20); 4506 4507 reg = urtwn_bb_read(sc, 0x818); 4508 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4509 urtwn_bb_write(sc, 0x818, reg); 4510 4511 /* Select 40MHz bandwidth. */ 4512 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4513 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4514 } else { 4515 urtwn_write_1(sc, R92C_BWOPMODE, 4516 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4517 4518 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4519 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4520 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4521 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4522 4523 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4524 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4525 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4526 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4527 R92C_FPGA0_ANAPARAM2_CBW20); 4528 } 4529 4530 /* Select 20MHz bandwidth. */ 4531 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4532 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4533 (ISSET(sc->chip, URTWN_CHIP_88E) || 4534 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4535 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4536 } 4537 } 4538 4539 static void __noinline 4540 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4541 { 4542 4543 URTWNHIST_FUNC(); 4544 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4545 4546 uint32_t addaBackup[16], iqkBackup[4], piMode; 4547 4548 #ifdef notyet 4549 uint32_t odfm0_agccore_regs[3]; 4550 uint32_t ant_regs[3]; 4551 uint32_t rf_regs[8]; 4552 #endif 4553 uint32_t reg0, reg1, reg2; 4554 int i, attempt; 4555 4556 #ifdef notyet 4557 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4558 R92E_STBC_SETTING + 2)); 4559 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4560 /* Save AGCCORE regs. */ 4561 for (i = 0; i < sc->nrxchains; i++) { 4562 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4563 R92C_OFDM0_AGCCORE1(i)); 4564 } 4565 #endif 4566 /* Save BB regs. */ 4567 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4568 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4569 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4570 4571 /* Save adda regs to be restored when finished. */ 4572 for (i = 0; i < __arraycount(addaReg); i++) 4573 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4574 /* Save mac regs. */ 4575 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4576 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4577 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4578 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4579 4580 #ifdef notyet 4581 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4582 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4583 4584 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4585 for (i = 0; i < sc->nrxchains; i++) 4586 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4587 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4588 #endif 4589 4590 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4591 R92C_HSSI_PARAM1_PI); 4592 if (piMode == 0) { 4593 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4594 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4595 R92C_HSSI_PARAM1_PI); 4596 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4597 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4598 R92C_HSSI_PARAM1_PI); 4599 } 4600 4601 attempt = 1; 4602 4603 next_attempt: 4604 4605 /* Set mac regs for calibration. */ 4606 for (i = 0; i < __arraycount(addaReg); i++) { 4607 urtwn_bb_write(sc, addaReg[i], 4608 addaReg[__arraycount(addaReg) - 1]); 4609 } 4610 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4611 R92C_CCK0_AFESETTING)); 4612 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4613 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4614 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4615 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4616 4617 if (sc->ntxchains > 1) 4618 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4619 4620 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4621 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4622 ~R92C_BCN_CTRL_EN_BCN)); 4623 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4624 ~R92C_BCN_CTRL_EN_BCN)); 4625 4626 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4627 ~R92C_GPIO_MUXCFG_ENBT)); 4628 4629 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4630 4631 if (sc->ntxchains > 1) 4632 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4633 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4634 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4635 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4636 4637 /* Restore BB regs. */ 4638 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4639 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4640 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4641 4642 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4643 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4644 if (sc->nrxchains > 1) 4645 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4646 4647 if (attempt-- > 0) 4648 goto next_attempt; 4649 4650 /* Restore mode. */ 4651 if (piMode == 0) { 4652 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4653 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4654 ~R92C_HSSI_PARAM1_PI); 4655 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4656 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4657 ~R92C_HSSI_PARAM1_PI); 4658 } 4659 4660 #ifdef notyet 4661 for (i = 0; i < sc->nrxchains; i++) { 4662 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4663 odfm0_agccore_regs[i]); 4664 } 4665 #endif 4666 4667 /* Restore adda regs. */ 4668 for (i = 0; i < __arraycount(addaReg); i++) 4669 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4670 /* Restore mac regs. */ 4671 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4672 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4673 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4674 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4675 4676 #ifdef notyet 4677 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4678 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4679 4680 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4681 for (i = 0; i < sc->nrxchains; i++) 4682 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4683 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4684 #endif 4685 } 4686 4687 static void 4688 urtwn_lc_calib(struct urtwn_softc *sc) 4689 { 4690 uint32_t rf_ac[2]; 4691 uint8_t txmode; 4692 size_t i; 4693 4694 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4695 4696 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4697 4698 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4699 if ((txmode & 0x70) != 0) { 4700 /* Disable all continuous Tx. */ 4701 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4702 4703 /* Set RF mode to standby mode. */ 4704 for (i = 0; i < sc->nrxchains; i++) { 4705 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4706 urtwn_rf_write(sc, i, R92C_RF_AC, 4707 RW(rf_ac[i], R92C_RF_AC_MODE, 4708 R92C_RF_AC_MODE_STANDBY)); 4709 } 4710 } else { 4711 /* Block all Tx queues. */ 4712 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4713 } 4714 /* Start calibration. */ 4715 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4716 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4717 4718 /* Give calibration the time to complete. */ 4719 urtwn_delay_ms(sc, 100); 4720 4721 /* Restore configuration. */ 4722 if ((txmode & 0x70) != 0) { 4723 /* Restore Tx mode. */ 4724 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4725 /* Restore RF mode. */ 4726 for (i = 0; i < sc->nrxchains; i++) { 4727 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4728 } 4729 } else { 4730 /* Unblock all Tx queues. */ 4731 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4732 } 4733 } 4734 4735 static void 4736 urtwn_temp_calib(struct urtwn_softc *sc) 4737 { 4738 int temp, t_meter_reg; 4739 4740 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4741 4742 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4743 4744 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4745 t_meter_reg = R92C_RF_T_METER; 4746 else 4747 t_meter_reg = R92E_RF_T_METER; 4748 4749 if (sc->thcal_state == 0) { 4750 /* Start measuring temperature. */ 4751 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4752 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4753 sc->thcal_state = 1; 4754 return; 4755 } 4756 sc->thcal_state = 0; 4757 4758 /* Read measured temperature. */ 4759 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4760 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4761 if (temp == 0) /* Read failed, skip. */ 4762 return; 4763 4764 /* 4765 * Redo LC calibration if temperature changed significantly since 4766 * last calibration. 4767 */ 4768 if (sc->thcal_lctemp == 0) { 4769 /* First LC calibration is performed in urtwn_init(). */ 4770 sc->thcal_lctemp = temp; 4771 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4772 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4773 sc->thcal_lctemp, temp, 0, 0); 4774 urtwn_lc_calib(sc); 4775 /* Record temperature of last LC calibration. */ 4776 sc->thcal_lctemp = temp; 4777 } 4778 } 4779 4780 static int 4781 urtwn_init(struct ifnet *ifp) 4782 { 4783 struct urtwn_softc *sc = ifp->if_softc; 4784 struct ieee80211com *ic = &sc->sc_ic; 4785 struct urtwn_rx_data *data; 4786 uint32_t reg; 4787 size_t i; 4788 int error; 4789 4790 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4791 4792 urtwn_stop(ifp, 0); 4793 4794 mutex_enter(&sc->sc_write_mtx); 4795 4796 mutex_enter(&sc->sc_task_mtx); 4797 /* Init host async commands ring. */ 4798 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4799 mutex_exit(&sc->sc_task_mtx); 4800 4801 mutex_enter(&sc->sc_fwcmd_mtx); 4802 /* Init firmware commands ring. */ 4803 sc->fwcur = 0; 4804 mutex_exit(&sc->sc_fwcmd_mtx); 4805 4806 /* Allocate Tx/Rx buffers. */ 4807 error = urtwn_alloc_rx_list(sc); 4808 if (error != 0) { 4809 aprint_error_dev(sc->sc_dev, 4810 "could not allocate Rx buffers\n"); 4811 goto fail; 4812 } 4813 error = urtwn_alloc_tx_list(sc); 4814 if (error != 0) { 4815 aprint_error_dev(sc->sc_dev, 4816 "could not allocate Tx buffers\n"); 4817 goto fail; 4818 } 4819 4820 /* Power on adapter. */ 4821 error = urtwn_power_on(sc); 4822 if (error != 0) 4823 goto fail; 4824 4825 /* Initialize DMA. */ 4826 error = urtwn_dma_init(sc); 4827 if (error != 0) 4828 goto fail; 4829 4830 /* Set info size in Rx descriptors (in 64-bit words). */ 4831 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4832 4833 /* Init interrupts. */ 4834 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4835 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4836 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4837 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4838 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4839 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4840 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4841 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4842 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4843 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4844 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4845 } 4846 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4847 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4848 } else { 4849 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4850 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4851 } 4852 4853 /* Set MAC address. */ 4854 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4855 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4856 4857 /* Set initial network type. */ 4858 reg = urtwn_read_4(sc, R92C_CR); 4859 switch (ic->ic_opmode) { 4860 case IEEE80211_M_STA: 4861 default: 4862 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4863 break; 4864 4865 case IEEE80211_M_IBSS: 4866 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4867 break; 4868 } 4869 urtwn_write_4(sc, R92C_CR, reg); 4870 4871 /* Set response rate */ 4872 reg = urtwn_read_4(sc, R92C_RRSR); 4873 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4874 urtwn_write_4(sc, R92C_RRSR, reg); 4875 4876 /* SIFS (used in NAV) */ 4877 urtwn_write_2(sc, R92C_SPEC_SIFS, 4878 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4879 4880 /* Set short/long retry limits. */ 4881 urtwn_write_2(sc, R92C_RL, 4882 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4883 4884 /* Initialize EDCA parameters. */ 4885 urtwn_edca_init(sc); 4886 4887 /* Setup rate fallback. */ 4888 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4889 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4890 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4891 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4892 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4893 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4894 } 4895 4896 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4897 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4898 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4899 /* Set ACK timeout. */ 4900 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4901 4902 /* Setup USB aggregation. */ 4903 /* Tx */ 4904 reg = urtwn_read_4(sc, R92C_TDECTRL); 4905 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4906 urtwn_write_4(sc, R92C_TDECTRL, reg); 4907 /* Rx */ 4908 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4909 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4910 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4911 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4912 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4913 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4914 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4915 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4916 ISSET(sc->chip, URTWN_CHIP_92EU)) 4917 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4918 else 4919 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4920 4921 /* Initialize beacon parameters. */ 4922 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4923 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4924 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4925 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4926 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4927 4928 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4929 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4930 /* Setup AMPDU aggregation. */ 4931 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4932 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4933 urtwn_write_2(sc, 0x4ca, 0x0708); 4934 4935 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4936 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4937 } 4938 4939 /* Load 8051 microcode. */ 4940 error = urtwn_load_firmware(sc); 4941 if (error != 0) 4942 goto fail; 4943 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4944 4945 /* Initialize MAC/BB/RF blocks. */ 4946 /* 4947 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4948 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4949 * XXX: This setting should be removed from rtl8192cu_mac[]. 4950 */ 4951 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4952 urtwn_rxfilter_init(sc); // reset R92C_RCR 4953 urtwn_bb_init(sc); 4954 urtwn_rf_init(sc); 4955 4956 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4957 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4958 urtwn_write_2(sc, R92C_CR, 4959 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4960 R92C_CR_MACRXEN); 4961 } 4962 4963 /* Turn CCK and OFDM blocks on. */ 4964 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4965 reg |= R92C_RFMOD_CCK_EN; 4966 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4967 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4968 reg |= R92C_RFMOD_OFDM_EN; 4969 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4970 4971 /* Clear per-station keys table. */ 4972 urtwn_cam_init(sc); 4973 4974 /* Enable hardware sequence numbering. */ 4975 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4976 4977 /* Perform LO and IQ calibrations. */ 4978 urtwn_iq_calib(sc, sc->iqk_inited); 4979 sc->iqk_inited = true; 4980 4981 /* Perform LC calibration. */ 4982 urtwn_lc_calib(sc); 4983 4984 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4985 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4986 /* Fix USB interference issue. */ 4987 urtwn_write_1(sc, 0xfe40, 0xe0); 4988 urtwn_write_1(sc, 0xfe41, 0x8d); 4989 urtwn_write_1(sc, 0xfe42, 0x80); 4990 urtwn_write_4(sc, 0x20c, 0xfd0320); 4991 4992 urtwn_pa_bias_init(sc); 4993 } 4994 4995 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4996 !(sc->chip & URTWN_CHIP_92EU)) { 4997 /* 1T1R */ 4998 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4999 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5000 } 5001 5002 /* Initialize GPIO setting. */ 5003 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5004 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5005 5006 /* Fix for lower temperature. */ 5007 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5008 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5009 urtwn_write_1(sc, 0x15, 0xe9); 5010 5011 /* Set default channel. */ 5012 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5013 5014 /* Queue Rx xfers. */ 5015 for (size_t j = 0; j < sc->rx_npipe; j++) { 5016 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5017 data = &sc->rx_data[j][i]; 5018 usbd_setup_xfer(data->xfer, data, data->buf, 5019 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5020 urtwn_rxeof); 5021 error = usbd_transfer(data->xfer); 5022 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5023 error != USBD_IN_PROGRESS)) 5024 goto fail; 5025 } 5026 } 5027 5028 /* We're ready to go. */ 5029 ifp->if_flags &= ~IFF_OACTIVE; 5030 ifp->if_flags |= IFF_RUNNING; 5031 sc->sc_running = true; 5032 5033 mutex_exit(&sc->sc_write_mtx); 5034 5035 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5036 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5037 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5038 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5039 urtwn_wait_async(sc); 5040 5041 return 0; 5042 5043 fail: 5044 mutex_exit(&sc->sc_write_mtx); 5045 5046 urtwn_stop(ifp, 1); 5047 return error; 5048 } 5049 5050 static void __noinline 5051 urtwn_stop(struct ifnet *ifp, int disable) 5052 { 5053 struct urtwn_softc *sc = ifp->if_softc; 5054 struct ieee80211com *ic = &sc->sc_ic; 5055 size_t i; 5056 int s; 5057 5058 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5059 5060 s = splusb(); 5061 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5062 urtwn_wait_async(sc); 5063 splx(s); 5064 5065 sc->tx_timer = 0; 5066 ifp->if_timer = 0; 5067 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5068 5069 callout_stop(&sc->sc_scan_to); 5070 callout_stop(&sc->sc_calib_to); 5071 5072 /* Abort Tx. */ 5073 for (i = 0; i < sc->tx_npipe; i++) { 5074 if (sc->tx_pipe[i] != NULL) 5075 usbd_abort_pipe(sc->tx_pipe[i]); 5076 } 5077 5078 /* Stop Rx pipe. */ 5079 for (i = 0; i < sc->rx_npipe; i++) { 5080 if (sc->rx_pipe[i] != NULL) 5081 usbd_abort_pipe(sc->rx_pipe[i]); 5082 } 5083 5084 /* Free Tx/Rx buffers. */ 5085 urtwn_free_tx_list(sc); 5086 urtwn_free_rx_list(sc); 5087 5088 sc->sc_running = false; 5089 if (disable) 5090 urtwn_chip_stop(sc); 5091 } 5092 5093 static int 5094 urtwn_reset(struct ifnet *ifp) 5095 { 5096 struct urtwn_softc *sc = ifp->if_softc; 5097 struct ieee80211com *ic = &sc->sc_ic; 5098 5099 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5100 return ENETRESET; 5101 5102 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5103 5104 return 0; 5105 } 5106 5107 static void 5108 urtwn_chip_stop(struct urtwn_softc *sc) 5109 { 5110 uint32_t reg; 5111 bool disabled = true; 5112 5113 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5114 5115 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5116 ISSET(sc->chip, URTWN_CHIP_92EU)) 5117 return; 5118 5119 mutex_enter(&sc->sc_write_mtx); 5120 5121 /* 5122 * RF Off Sequence 5123 */ 5124 /* Pause MAC TX queue */ 5125 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5126 5127 /* Disable RF */ 5128 urtwn_rf_write(sc, 0, 0, 0); 5129 5130 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5131 5132 /* Reset BB state machine */ 5133 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5134 R92C_SYS_FUNC_EN_USBD | 5135 R92C_SYS_FUNC_EN_USBA | 5136 R92C_SYS_FUNC_EN_BB_GLB_RST); 5137 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5138 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5139 5140 /* 5141 * Reset digital sequence 5142 */ 5143 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5144 /* Reset MCU ready status */ 5145 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5146 /* If firmware in ram code, do reset */ 5147 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5148 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5149 ISSET(sc->chip, URTWN_CHIP_92EU)) 5150 urtwn_r88e_fw_reset(sc); 5151 else 5152 urtwn_fw_reset(sc); 5153 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5154 } 5155 } 5156 5157 /* Reset MAC and Enable 8051 */ 5158 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5159 5160 /* Reset MCU ready status */ 5161 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5162 5163 if (disabled) { 5164 /* Disable MAC clock */ 5165 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5166 /* Disable AFE PLL */ 5167 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5168 /* Gated AFE DIG_CLOCK */ 5169 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5170 /* Isolated digital to PON */ 5171 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5172 } 5173 5174 /* 5175 * Pull GPIO PIN to balance level and LED control 5176 */ 5177 /* 1. Disable GPIO[7:0] */ 5178 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5179 5180 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5181 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5182 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5183 5184 /* Disable GPIO[10:8] */ 5185 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5186 5187 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5188 reg |= (((reg & 0x000f) << 4) | 0x0780); 5189 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5190 5191 /* Disable LED0 & 1 */ 5192 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5193 5194 /* 5195 * Reset digital sequence 5196 */ 5197 if (disabled) { 5198 /* Disable ELDR clock */ 5199 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5200 /* Isolated ELDR to PON */ 5201 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5202 } 5203 5204 /* 5205 * Disable analog sequence 5206 */ 5207 if (disabled) { 5208 /* Disable A15 power */ 5209 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5210 /* Disable digital core power */ 5211 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5212 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5213 ~R92C_LDOV12D_CTRL_LDV12_EN); 5214 } 5215 5216 /* Enter PFM mode */ 5217 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5218 5219 /* Set USB suspend */ 5220 urtwn_write_2(sc, R92C_APS_FSMCO, 5221 R92C_APS_FSMCO_APDM_HOST | 5222 R92C_APS_FSMCO_AFSM_HSUS | 5223 R92C_APS_FSMCO_PFM_ALDN); 5224 5225 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5226 5227 mutex_exit(&sc->sc_write_mtx); 5228 } 5229 5230 static void 5231 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5232 { 5233 if (sc->sc_running == false) 5234 DELAY(ms * 1000); 5235 else 5236 usbd_delay_ms(sc->sc_udev, ms); 5237 } 5238 5239 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5240 5241 #ifdef _MODULE 5242 #include "ioconf.c" 5243 #endif 5244 5245 static int 5246 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5247 { 5248 int error = 0; 5249 5250 switch (cmd) { 5251 case MODULE_CMD_INIT: 5252 #ifdef _MODULE 5253 error = config_init_component(cfdriver_ioconf_urtwn, 5254 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5255 #endif 5256 return error; 5257 case MODULE_CMD_FINI: 5258 #ifdef _MODULE 5259 error = config_fini_component(cfdriver_ioconf_urtwn, 5260 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5261 #endif 5262 return error; 5263 default: 5264 return ENOTTY; 5265 } 5266 } 5267
Indexes created Thu Oct 02 14:10:14 GMT 2025