if_urtwn.c revision 1.105.4.4
1 /* $NetBSD: if_urtwn.c,v 1.105.4.4 2025/09/23 12:42:24 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.105.4.4 2025/09/23 12:42:24 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 141 URTWN_DEV(AZUREWAVE, RTL8188CU), 142 URTWN_DEV(BELKIN, F7D2102), 143 URTWN_DEV(BELKIN, RTL8188CU), 144 URTWN_DEV(BELKIN, RTL8188CUS), 145 URTWN_DEV(BELKIN, RTL8192CU), 146 URTWN_DEV(BELKIN, RTL8192CU_1), 147 URTWN_DEV(BELKIN, RTL8192CU_2), 148 URTWN_DEV(CHICONY, RTL8188CUS_1), 149 URTWN_DEV(CHICONY, RTL8188CUS_2), 150 URTWN_DEV(CHICONY, RTL8188CUS_3), 151 URTWN_DEV(CHICONY, RTL8188CUS_4), 152 URTWN_DEV(CHICONY, RTL8188CUS_5), 153 URTWN_DEV(CHICONY, RTL8188CUS_6), 154 URTWN_DEV(COMPARE, RTL8192CU), 155 URTWN_DEV(COREGA, RTL8192CU), 156 URTWN_DEV(DLINK, DWA131B), 157 URTWN_DEV(DLINK, RTL8188CU), 158 URTWN_DEV(DLINK, RTL8192CU_1), 159 URTWN_DEV(DLINK, RTL8192CU_2), 160 URTWN_DEV(DLINK, RTL8192CU_3), 161 URTWN_DEV(DLINK, RTL8192CU_4), 162 URTWN_DEV(EDIMAX, RTL8188CU), 163 URTWN_DEV(EDIMAX, RTL8192CU), 164 URTWN_DEV(FEIXUN, RTL8188CU), 165 URTWN_DEV(FEIXUN, RTL8192CU), 166 URTWN_DEV(GUILLEMOT, HWNUP150), 167 URTWN_DEV(GUILLEMOT, RTL8192CU), 168 URTWN_DEV(HAWKING, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU_2), 170 URTWN_DEV(HP3, RTL8188CU), 171 URTWN_DEV(IODATA, WNG150UM), 172 URTWN_DEV(IODATA, RTL8192CU), 173 URTWN_DEV(NETGEAR, WNA1000M), 174 URTWN_DEV(NETGEAR, RTL8192CU), 175 URTWN_DEV(NETGEAR4, RTL8188CU), 176 URTWN_DEV(NOVATECH, RTL8188CU), 177 URTWN_DEV(PLANEX2, RTL8188CU_1), 178 URTWN_DEV(PLANEX2, RTL8188CU_2), 179 URTWN_DEV(PLANEX2, RTL8192CU), 180 URTWN_DEV(PLANEX2, RTL8188CU_3), 181 URTWN_DEV(PLANEX2, RTL8188CU_4), 182 URTWN_DEV(PLANEX2, RTL8188CUS), 183 URTWN_DEV(REALTEK, RTL8188CE_0), 184 URTWN_DEV(REALTEK, RTL8188CE_1), 185 URTWN_DEV(REALTEK, RTL8188CTV), 186 URTWN_DEV(REALTEK, RTL8188CU_0), 187 URTWN_DEV(REALTEK, RTL8188CU_1), 188 URTWN_DEV(REALTEK, RTL8188CU_2), 189 URTWN_DEV(REALTEK, RTL8188CU_3), 190 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 191 URTWN_DEV(REALTEK, RTL8188CUS), 192 URTWN_DEV(REALTEK, RTL8188RU), 193 URTWN_DEV(REALTEK, RTL8188RU_2), 194 URTWN_DEV(REALTEK, RTL8188RU_3), 195 URTWN_DEV(REALTEK, RTL8191CU), 196 URTWN_DEV(REALTEK, RTL8192CE), 197 URTWN_DEV(REALTEK, RTL8192CU), 198 URTWN_DEV(SITECOMEU, RTL8188CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU_2), 200 URTWN_DEV(SITECOMEU, RTL8192CU), 201 URTWN_DEV(SITECOMEU, RTL8192CUR2), 202 URTWN_DEV(TPLINK, RTL8192CU), 203 URTWN_DEV(TRENDNET, RTL8188CU), 204 URTWN_DEV(TRENDNET, RTL8192CU), 205 URTWN_DEV(TRENDNET, TEW648UBM), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(ASUSTEK, USBN10NANO_B1), 210 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 211 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 212 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 213 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 214 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 215 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 216 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 217 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 218 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 219 220 /* URTWN_RTL8192EU */ 221 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 222 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 223 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 224 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 225 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 226 }; 227 #undef URTWN_DEV 228 #undef URTWN_RTL8188E_DEV 229 #undef URTWN_RTL8192EU_DEV 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct urtwn_softc *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 289 int); 290 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_ioctl(struct ifnet *, u_long, void *); 306 static int urtwn_r92c_power_on(struct urtwn_softc *); 307 static int urtwn_r92e_power_on(struct urtwn_softc *); 308 static int urtwn_r88e_power_on(struct urtwn_softc *); 309 static int urtwn_llt_init(struct urtwn_softc *); 310 static void urtwn_fw_reset(struct urtwn_softc *); 311 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 312 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 313 static int urtwn_load_firmware(struct urtwn_softc *); 314 static int urtwn_r92c_dma_init(struct urtwn_softc *); 315 static int urtwn_r88e_dma_init(struct urtwn_softc *); 316 static void urtwn_mac_init(struct urtwn_softc *); 317 static void urtwn_bb_init(struct urtwn_softc *); 318 static void urtwn_rf_init(struct urtwn_softc *); 319 static void urtwn_cam_init(struct urtwn_softc *); 320 static void urtwn_pa_bias_init(struct urtwn_softc *); 321 static void urtwn_rxfilter_init(struct urtwn_softc *); 322 static void urtwn_edca_init(struct urtwn_softc *); 323 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 324 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 325 uint16_t[]); 326 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 327 u_int, uint16_t[]); 328 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 329 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 330 u_int); 331 static void urtwn_iq_calib(struct urtwn_softc *, bool); 332 static void urtwn_lc_calib(struct urtwn_softc *); 333 static void urtwn_temp_calib(struct urtwn_softc *); 334 static int urtwn_init(struct ifnet *); 335 static void urtwn_stop(struct ifnet *, int); 336 static int urtwn_reset(struct ifnet *); 337 static void urtwn_chip_stop(struct urtwn_softc *); 338 static void urtwn_newassoc(struct ieee80211_node *, int); 339 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 340 341 /* Aliases. */ 342 #define urtwn_bb_write urtwn_write_4 343 #define urtwn_bb_read urtwn_read_4 344 345 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 346 347 static const uint16_t addaReg[] = { 348 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 349 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 350 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 351 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 352 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 353 }; 354 355 static int 356 urtwn_match(device_t parent, cfdata_t match, void *aux) 357 { 358 struct usb_attach_arg *uaa = aux; 359 360 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 361 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 362 } 363 364 static void 365 urtwn_attach(device_t parent, device_t self, void *aux) 366 { 367 struct urtwn_softc *sc = device_private(self); 368 struct ieee80211com *ic = &sc->sc_ic; 369 struct ifnet *ifp = &sc->sc_if; 370 struct usb_attach_arg *uaa = aux; 371 char *devinfop; 372 const struct urtwn_dev *dev; 373 usb_device_request_t req; 374 size_t i; 375 int error; 376 377 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 378 379 sc->sc_dev = self; 380 sc->sc_udev = uaa->uaa_device; 381 382 sc->chip = 0; 383 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 384 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 385 SET(sc->chip, URTWN_CHIP_88E); 386 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 387 SET(sc->chip, URTWN_CHIP_92EU); 388 389 aprint_naive("\n"); 390 aprint_normal("\n"); 391 392 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 393 aprint_normal_dev(self, "%s\n", devinfop); 394 usbd_devinfo_free(devinfop); 395 396 req.bmRequestType = UT_WRITE_DEVICE; 397 req.bRequest = UR_SET_FEATURE; 398 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 399 USETW(req.wIndex, UHF_PORT_SUSPEND); 400 USETW(req.wLength, 0); 401 402 (void) usbd_do_request(sc->sc_udev, &req, 0); 403 404 cv_init(&sc->sc_task_cv, "urtwntsk"); 405 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 406 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 407 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 408 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 409 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 410 411 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 412 413 callout_init(&sc->sc_scan_to, 0); 414 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 415 callout_init(&sc->sc_calib_to, 0); 416 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 417 418 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 419 RND_TYPE_NET, RND_FLAG_DEFAULT); 420 421 error = usbd_set_config_no(sc->sc_udev, 1, 0); 422 if (error != 0) { 423 aprint_error_dev(self, "failed to set configuration" 424 ", err=%s\n", usbd_errstr(error)); 425 goto fail; 426 } 427 428 /* Get the first interface handle. */ 429 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 430 if (error != 0) { 431 aprint_error_dev(self, "could not get interface handle\n"); 432 goto fail; 433 } 434 435 error = urtwn_read_chipid(sc); 436 if (error != 0) { 437 aprint_error_dev(self, "unsupported test chip\n"); 438 goto fail; 439 } 440 441 /* Determine number of Tx/Rx chains. */ 442 if (sc->chip & URTWN_CHIP_92C) { 443 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 444 sc->nrxchains = 2; 445 } else if (sc->chip & URTWN_CHIP_92EU) { 446 sc->ntxchains = 2; 447 sc->nrxchains = 2; 448 } else { 449 sc->ntxchains = 1; 450 sc->nrxchains = 1; 451 } 452 453 if (ISSET(sc->chip, URTWN_CHIP_88E) || 454 ISSET(sc->chip, URTWN_CHIP_92EU)) 455 urtwn_r88e_read_rom(sc); 456 else 457 urtwn_read_rom(sc); 458 459 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 460 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 461 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 462 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 463 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 464 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 465 "8188CUS", sc->ntxchains, sc->nrxchains, 466 ether_sprintf(ic->ic_myaddr)); 467 468 error = urtwn_open_pipes(sc); 469 if (error != 0) { 470 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 471 goto fail; 472 } 473 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 474 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 475 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 476 477 /* 478 * Setup the 802.11 device. 479 */ 480 ic->ic_ifp = ifp; 481 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 482 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 483 ic->ic_state = IEEE80211_S_INIT; 484 485 /* Set device capabilities. */ 486 ic->ic_caps = 487 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 488 IEEE80211_C_IBSS | /* IBSS mode supported */ 489 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 490 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 491 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 492 IEEE80211_C_WME | /* 802.11e */ 493 IEEE80211_C_WPA; /* 802.11i */ 494 495 /* Set supported .11b and .11g rates. */ 496 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 497 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 498 499 /* Set supported .11b and .11g channels (1 through 14). */ 500 for (i = 1; i <= 14; i++) { 501 ic->ic_channels[i].ic_freq = 502 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 503 ic->ic_channels[i].ic_flags = 504 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 505 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 506 } 507 508 ifp->if_softc = sc; 509 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 510 ifp->if_init = urtwn_init; 511 ifp->if_ioctl = urtwn_ioctl; 512 ifp->if_start = urtwn_start; 513 ifp->if_watchdog = urtwn_watchdog; 514 IFQ_SET_READY(&ifp->if_snd); 515 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 516 517 if_initialize(ifp); 518 ieee80211_ifattach(ic); 519 520 /* override default methods */ 521 ic->ic_newassoc = urtwn_newassoc; 522 ic->ic_reset = urtwn_reset; 523 ic->ic_wme.wme_update = urtwn_wme_update; 524 525 /* Override state transition machine. */ 526 sc->sc_newstate = ic->ic_newstate; 527 ic->ic_newstate = urtwn_newstate; 528 529 /* XXX media locking needs revisiting */ 530 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 531 ieee80211_media_init_with_lock(ic, 532 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 533 534 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 535 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 536 &sc->sc_drvbpf); 537 538 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 539 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 540 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 541 542 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 543 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 544 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 545 546 ifp->if_percpuq = if_percpuq_create(ifp); 547 if_register(ifp); 548 549 ieee80211_announce(ic); 550 551 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 552 553 if (!pmf_device_register(self, NULL, NULL)) 554 aprint_error_dev(self, "couldn't establish power handler\n"); 555 556 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 557 return; 558 559 fail: 560 sc->sc_dying = 1; 561 aprint_error_dev(self, "attach failed\n"); 562 } 563 564 static int 565 urtwn_detach(device_t self, int flags) 566 { 567 struct urtwn_softc *sc = device_private(self); 568 struct ifnet *ifp = &sc->sc_if; 569 int s; 570 571 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 572 573 pmf_device_deregister(self); 574 575 s = splusb(); 576 577 sc->sc_dying = 1; 578 579 callout_halt(&sc->sc_scan_to, NULL); 580 callout_halt(&sc->sc_calib_to, NULL); 581 582 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 583 urtwn_stop(ifp, 0); 584 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 585 NULL); 586 587 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 588 bpf_detach(ifp); 589 ieee80211_ifdetach(&sc->sc_ic); 590 if_detach(ifp); 591 592 mutex_destroy(&sc->sc_media_mtx); 593 594 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 595 urtwn_close_pipes(sc); 596 } 597 598 splx(s); 599 600 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 601 602 rnd_detach_source(&sc->rnd_source); 603 604 callout_destroy(&sc->sc_scan_to); 605 callout_destroy(&sc->sc_calib_to); 606 607 cv_destroy(&sc->sc_task_cv); 608 mutex_destroy(&sc->sc_write_mtx); 609 mutex_destroy(&sc->sc_fwcmd_mtx); 610 mutex_destroy(&sc->sc_tx_mtx); 611 mutex_destroy(&sc->sc_rx_mtx); 612 mutex_destroy(&sc->sc_task_mtx); 613 614 return 0; 615 } 616 617 static int 618 urtwn_activate(device_t self, enum devact act) 619 { 620 struct urtwn_softc *sc = device_private(self); 621 622 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 623 624 switch (act) { 625 case DVACT_DEACTIVATE: 626 if_deactivate(sc->sc_ic.ic_ifp); 627 return 0; 628 default: 629 return EOPNOTSUPP; 630 } 631 } 632 633 static int 634 urtwn_open_pipes(struct urtwn_softc *sc) 635 { 636 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 637 static uint8_t epaddr[R92C_MAX_EPOUT]; 638 static uint8_t rxepaddr[R92C_MAX_EPIN]; 639 usb_interface_descriptor_t *id; 640 usb_endpoint_descriptor_t *ed; 641 size_t i, ntx = 0, nrx = 0; 642 int error; 643 644 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 645 646 /* Determine the number of bulk-out pipes. */ 647 id = usbd_get_interface_descriptor(sc->sc_iface); 648 for (i = 0; i < id->bNumEndpoints; i++) { 649 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 650 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 651 continue; 652 } 653 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 654 if (ntx < sizeof(epaddr)) 655 epaddr[ntx] = ed->bEndpointAddress; 656 ntx++; 657 } 658 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 659 if (nrx < sizeof(rxepaddr)) 660 rxepaddr[nrx] = ed->bEndpointAddress; 661 nrx++; 662 } 663 } 664 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 665 aprint_error_dev(sc->sc_dev, 666 "%zd: invalid number of Rx bulk pipes\n", nrx); 667 return EIO; 668 } 669 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 670 aprint_error_dev(sc->sc_dev, 671 "%zd: invalid number of Tx bulk pipes\n", ntx); 672 return EIO; 673 } 674 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 675 nrx, ntx, 0, 0); 676 sc->rx_npipe = nrx; 677 sc->tx_npipe = ntx; 678 679 /* Open bulk-in pipe at address 0x81. */ 680 for (i = 0; i < nrx; i++) { 681 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 682 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 683 if (error != 0) { 684 aprint_error_dev(sc->sc_dev, 685 "could not open Rx bulk pipe 0x%02x: %d\n", 686 rxepaddr[i], error); 687 goto fail; 688 } 689 } 690 691 /* Open bulk-out pipes (up to 3). */ 692 for (i = 0; i < ntx; i++) { 693 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 694 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 695 if (error != 0) { 696 aprint_error_dev(sc->sc_dev, 697 "could not open Tx bulk pipe 0x%02x: %d\n", 698 epaddr[i], error); 699 goto fail; 700 } 701 } 702 703 /* Map 802.11 access categories to USB pipes. */ 704 sc->ac2idx[WME_AC_BK] = 705 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 706 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 707 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 708 709 fail: 710 if (error != 0) 711 urtwn_close_pipes(sc); 712 return error; 713 } 714 715 static void 716 urtwn_close_pipes(struct urtwn_softc *sc) 717 { 718 struct usbd_pipe *pipe; 719 size_t i; 720 721 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 722 723 /* Close Rx pipes. */ 724 CTASSERT(sizeof(pipe) == sizeof(void *)); 725 for (i = 0; i < sc->rx_npipe; i++) { 726 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 727 if (pipe != NULL) { 728 usbd_close_pipe(pipe); 729 } 730 } 731 732 /* Close Tx pipes. */ 733 for (i = 0; i < sc->tx_npipe; i++) { 734 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 735 if (pipe != NULL) { 736 usbd_close_pipe(pipe); 737 } 738 } 739 } 740 741 static int __noinline 742 urtwn_alloc_rx_list(struct urtwn_softc *sc) 743 { 744 struct urtwn_rx_data *data; 745 size_t i; 746 int error = 0; 747 748 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 749 750 for (size_t j = 0; j < sc->rx_npipe; j++) { 751 TAILQ_INIT(&sc->rx_free_list[j]); 752 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 753 data = &sc->rx_data[j][i]; 754 755 data->sc = sc; /* Backpointer for callbacks. */ 756 data->pidx = j; 757 758 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 759 0, 0, &data->xfer); 760 if (error) { 761 aprint_error_dev(sc->sc_dev, 762 "could not allocate xfer\n"); 763 break; 764 } 765 766 data->buf = usbd_get_buffer(data->xfer); 767 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 768 } 769 } 770 if (error != 0) 771 urtwn_free_rx_list(sc); 772 return error; 773 } 774 775 static void 776 urtwn_free_rx_list(struct urtwn_softc *sc) 777 { 778 struct usbd_xfer *xfer; 779 size_t i; 780 781 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 782 783 /* NB: Caller must abort pipe first. */ 784 for (size_t j = 0; j < sc->rx_npipe; j++) { 785 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 786 CTASSERT(sizeof(xfer) == sizeof(void *)); 787 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 788 if (xfer != NULL) 789 usbd_destroy_xfer(xfer); 790 } 791 } 792 } 793 794 static int __noinline 795 urtwn_alloc_tx_list(struct urtwn_softc *sc) 796 { 797 struct urtwn_tx_data *data; 798 size_t i; 799 int error = 0; 800 801 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 802 803 mutex_enter(&sc->sc_tx_mtx); 804 for (size_t j = 0; j < sc->tx_npipe; j++) { 805 TAILQ_INIT(&sc->tx_free_list[j]); 806 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 807 data = &sc->tx_data[j][i]; 808 809 data->sc = sc; /* Backpointer for callbacks. */ 810 data->pidx = j; 811 812 error = usbd_create_xfer(sc->tx_pipe[j], 813 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 814 &data->xfer); 815 if (error) { 816 aprint_error_dev(sc->sc_dev, 817 "could not allocate xfer\n"); 818 goto fail; 819 } 820 821 data->buf = usbd_get_buffer(data->xfer); 822 823 /* Append this Tx buffer to our free list. */ 824 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 825 } 826 } 827 mutex_exit(&sc->sc_tx_mtx); 828 return 0; 829 830 fail: 831 urtwn_free_tx_list(sc); 832 mutex_exit(&sc->sc_tx_mtx); 833 return error; 834 } 835 836 static void 837 urtwn_free_tx_list(struct urtwn_softc *sc) 838 { 839 struct usbd_xfer *xfer; 840 size_t i; 841 842 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 843 844 /* NB: Caller must abort pipe first. */ 845 for (size_t j = 0; j < sc->tx_npipe; j++) { 846 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 847 CTASSERT(sizeof(xfer) == sizeof(void *)); 848 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 849 if (xfer != NULL) 850 usbd_destroy_xfer(xfer); 851 } 852 } 853 } 854 855 static int 856 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 857 struct ieee80211_node *ni) 858 { 859 struct urtwn_tx_data *data = 860 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 861 862 if (data == NULL) 863 return ENOBUFS; 864 865 return urtwn_tx(sc, m, ni, data); 866 } 867 868 static void 869 urtwn_cmdq_invariants(struct urtwn_softc *sc) 870 { 871 struct urtwn_host_cmd_ring *const ring = &sc->cmdq; 872 873 KASSERT(mutex_owned(&sc->sc_task_mtx)); 874 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 875 "%s: cur=%d next=%d queued=%d", 876 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 877 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 878 "%s: cur=%d next=%d queued=%d", 879 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 880 KASSERTMSG((ring->queued >= 0 && 881 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 882 "%s: %d commands queued", 883 device_xname(sc->sc_dev), ring->queued); 884 } 885 886 static void 887 urtwn_task(void *arg) 888 { 889 struct urtwn_softc *sc = arg; 890 struct ieee80211com *ic = &sc->sc_ic; 891 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 892 struct urtwn_host_cmd *cmd; 893 int s; 894 895 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 896 if (ic->ic_state == IEEE80211_S_RUN && 897 (ic->ic_opmode == IEEE80211_M_HOSTAP || 898 ic->ic_opmode == IEEE80211_M_IBSS)) { 899 900 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 901 &sc->sc_bo); 902 if (m == NULL) { 903 aprint_error_dev(sc->sc_dev, 904 "could not allocate beacon"); 905 } 906 907 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 908 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 909 } 910 911 /* beacon is no longer needed */ 912 m_freem(m); 913 } 914 915 /* Process host commands. */ 916 s = splusb(); 917 mutex_spin_enter(&sc->sc_task_mtx); 918 urtwn_cmdq_invariants(sc); 919 while (ring->next != ring->cur) { 920 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 921 device_xname(sc->sc_dev), 922 ring->cur, ring->next, ring->queued); 923 cmd = &ring->cmd[ring->next]; 924 mutex_spin_exit(&sc->sc_task_mtx); 925 splx(s); 926 /* Invoke callback with kernel lock held. */ 927 cmd->cb(sc, cmd->data); 928 s = splusb(); 929 mutex_spin_enter(&sc->sc_task_mtx); 930 urtwn_cmdq_invariants(sc); 931 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 932 device_xname(sc->sc_dev), 933 ring->cur, ring->next, ring->queued); 934 ring->queued--; 935 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 936 } 937 cv_broadcast(&sc->sc_task_cv); 938 mutex_spin_exit(&sc->sc_task_mtx); 939 splx(s); 940 } 941 942 static void 943 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 944 void *arg, int len) 945 { 946 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 947 struct urtwn_host_cmd *cmd; 948 bool schedtask = false; 949 int s; 950 951 URTWNHIST_FUNC(); 952 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 953 (uintptr_t)cb, (uintptr_t)arg, len, 0); 954 955 s = splusb(); 956 mutex_spin_enter(&sc->sc_task_mtx); 957 urtwn_cmdq_invariants(sc); 958 cmd = &ring->cmd[ring->cur]; 959 cmd->cb = cb; 960 KASSERT(len <= sizeof(cmd->data)); 961 memcpy(cmd->data, arg, len); 962 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 963 964 /* 965 * Schedule a task to process the command if need be. 966 */ 967 if (!sc->sc_dying) { 968 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 969 device_printf(sc->sc_dev, "command queue overflow\n"); 970 else if (ring->queued++ == 0) 971 schedtask = true; 972 } 973 mutex_spin_exit(&sc->sc_task_mtx); 974 splx(s); 975 976 if (schedtask) 977 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 978 } 979 980 static void 981 urtwn_wait_async(struct urtwn_softc *sc) 982 { 983 984 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 985 986 /* Wait for all queued asynchronous commands to complete. */ 987 mutex_spin_enter(&sc->sc_task_mtx); 988 while (sc->cmdq.queued > 0) 989 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 990 mutex_spin_exit(&sc->sc_task_mtx); 991 } 992 993 static int 994 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 995 int len) 996 { 997 usb_device_request_t req; 998 usbd_status error; 999 1000 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1001 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1002 1003 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1004 req.bRequest = R92C_REQ_REGS; 1005 USETW(req.wValue, addr); 1006 USETW(req.wIndex, 0); 1007 USETW(req.wLength, len); 1008 error = usbd_do_request(sc->sc_udev, &req, buf); 1009 if (error != USBD_NORMAL_COMPLETION) { 1010 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1011 error, addr, len, 0); 1012 } 1013 return error; 1014 } 1015 1016 static void 1017 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1018 { 1019 1020 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1021 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1022 1023 urtwn_write_region_1(sc, addr, &val, 1); 1024 } 1025 1026 static void 1027 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1028 { 1029 uint8_t buf[2]; 1030 1031 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1032 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1033 1034 buf[0] = (uint8_t)val; 1035 buf[1] = (uint8_t)(val >> 8); 1036 urtwn_write_region_1(sc, addr, buf, 2); 1037 } 1038 1039 static void 1040 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1041 { 1042 uint8_t buf[4]; 1043 1044 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1045 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1046 1047 buf[0] = (uint8_t)val; 1048 buf[1] = (uint8_t)(val >> 8); 1049 buf[2] = (uint8_t)(val >> 16); 1050 buf[3] = (uint8_t)(val >> 24); 1051 urtwn_write_region_1(sc, addr, buf, 4); 1052 } 1053 1054 static int 1055 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1056 { 1057 1058 URTWNHIST_FUNC(); 1059 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1060 1061 return urtwn_write_region_1(sc, addr, buf, len); 1062 } 1063 1064 static int 1065 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1066 int len) 1067 { 1068 usb_device_request_t req; 1069 usbd_status error; 1070 1071 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1072 1073 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1074 req.bRequest = R92C_REQ_REGS; 1075 USETW(req.wValue, addr); 1076 USETW(req.wIndex, 0); 1077 USETW(req.wLength, len); 1078 error = usbd_do_request(sc->sc_udev, &req, buf); 1079 if (error != USBD_NORMAL_COMPLETION) { 1080 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1081 error, addr, len, 0); 1082 } 1083 return error; 1084 } 1085 1086 static uint8_t 1087 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1088 { 1089 uint8_t val; 1090 1091 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1092 1093 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1094 return 0xff; 1095 1096 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1097 return val; 1098 } 1099 1100 static uint16_t 1101 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1102 { 1103 uint8_t buf[2]; 1104 uint16_t val; 1105 1106 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1107 1108 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1109 return 0xffff; 1110 1111 val = LE_READ_2(&buf[0]); 1112 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1113 return val; 1114 } 1115 1116 static uint32_t 1117 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1118 { 1119 uint8_t buf[4]; 1120 uint32_t val; 1121 1122 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1123 1124 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1125 return 0xffffffff; 1126 1127 val = LE_READ_4(&buf[0]); 1128 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1129 return val; 1130 } 1131 1132 static int 1133 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1134 { 1135 struct r92c_fw_cmd cmd; 1136 uint8_t *cp; 1137 int fwcur; 1138 int ntries; 1139 1140 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1141 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1142 1143 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1144 1145 mutex_enter(&sc->sc_fwcmd_mtx); 1146 fwcur = sc->fwcur; 1147 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1148 1149 /* Wait for current FW box to be empty. */ 1150 for (ntries = 0; ntries < 100; ntries++) { 1151 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1152 break; 1153 urtwn_delay_ms(sc, 2); 1154 } 1155 if (ntries == 100) { 1156 aprint_error_dev(sc->sc_dev, 1157 "could not send firmware command %d\n", id); 1158 mutex_exit(&sc->sc_fwcmd_mtx); 1159 return ETIMEDOUT; 1160 } 1161 1162 memset(&cmd, 0, sizeof(cmd)); 1163 KASSERT(len <= sizeof(cmd.msg)); 1164 memcpy(cmd.msg, buf, len); 1165 1166 /* Write the first word last since that will trigger the FW. */ 1167 cp = (uint8_t *)&cmd; 1168 cmd.id = id; 1169 if (len >= 4) { 1170 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1171 cmd.id |= R92C_CMD_FLAG_EXT; 1172 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1173 &cp[1], 2); 1174 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1175 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1176 ((uint32_t)cp[5] << 24)); 1177 } else { 1178 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1179 &cp[4], 2); 1180 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1181 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1182 ((uint32_t)cp[3] << 24)); 1183 } 1184 } else { 1185 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1186 } 1187 mutex_exit(&sc->sc_fwcmd_mtx); 1188 1189 return 0; 1190 } 1191 1192 static __inline void 1193 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1194 { 1195 1196 sc->sc_rf_write(sc, chain, addr, val); 1197 } 1198 1199 static void 1200 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1201 uint32_t val) 1202 { 1203 1204 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1205 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1206 } 1207 1208 static void 1209 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1210 uint32_t val) 1211 { 1212 1213 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1214 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1215 } 1216 1217 static void 1218 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1219 uint32_t val) 1220 { 1221 1222 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1223 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1224 } 1225 1226 static uint32_t 1227 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1228 { 1229 uint32_t reg[R92C_MAX_CHAINS], val; 1230 1231 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1232 if (chain != 0) { 1233 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1234 } 1235 1236 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1237 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1238 urtwn_delay_ms(sc, 1); 1239 1240 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1241 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1242 R92C_HSSI_PARAM2_READ_EDGE); 1243 urtwn_delay_ms(sc, 1); 1244 1245 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1246 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1247 urtwn_delay_ms(sc, 1); 1248 1249 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1250 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1251 } else { 1252 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1253 } 1254 return MS(val, R92C_LSSI_READBACK_DATA); 1255 } 1256 1257 static int 1258 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1259 { 1260 int ntries; 1261 1262 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1263 1264 urtwn_write_4(sc, R92C_LLT_INIT, 1265 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1266 SM(R92C_LLT_INIT_ADDR, addr) | 1267 SM(R92C_LLT_INIT_DATA, data)); 1268 /* Wait for write operation to complete. */ 1269 for (ntries = 0; ntries < 20; ntries++) { 1270 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1271 R92C_LLT_INIT_OP_NO_ACTIVE) { 1272 /* Done */ 1273 return 0; 1274 } 1275 DELAY(5); 1276 } 1277 return ETIMEDOUT; 1278 } 1279 1280 static uint8_t 1281 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1282 { 1283 uint32_t reg; 1284 int ntries; 1285 1286 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1287 1288 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1289 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1290 reg &= ~R92C_EFUSE_CTRL_VALID; 1291 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1292 1293 /* Wait for read operation to complete. */ 1294 for (ntries = 0; ntries < 100; ntries++) { 1295 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1296 if (reg & R92C_EFUSE_CTRL_VALID) { 1297 /* Done */ 1298 return MS(reg, R92C_EFUSE_CTRL_DATA); 1299 } 1300 DELAY(5); 1301 } 1302 aprint_error_dev(sc->sc_dev, 1303 "could not read efuse byte at address 0x%04x\n", addr); 1304 return 0xff; 1305 } 1306 1307 static void 1308 urtwn_efuse_read(struct urtwn_softc *sc) 1309 { 1310 uint8_t *rom = (uint8_t *)&sc->rom; 1311 uint32_t reg; 1312 uint16_t addr = 0; 1313 uint8_t off, msk; 1314 size_t i; 1315 1316 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1317 1318 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1319 1320 urtwn_efuse_switch_power(sc); 1321 1322 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1323 while (addr < 512) { 1324 reg = urtwn_efuse_read_1(sc, addr); 1325 if (reg == 0xff) 1326 break; 1327 addr++; 1328 off = reg >> 4; 1329 msk = reg & 0xf; 1330 for (i = 0; i < 4; i++) { 1331 if (msk & (1U << i)) 1332 continue; 1333 1334 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1335 addr++; 1336 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1337 addr++; 1338 } 1339 } 1340 #ifdef URTWN_DEBUG 1341 /* Dump ROM content. */ 1342 for (i = 0; i < (int)sizeof(sc->rom); i++) 1343 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1344 #endif 1345 } 1346 1347 static void 1348 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1349 { 1350 uint32_t reg; 1351 1352 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1353 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1354 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1355 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1356 } 1357 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1358 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1359 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1360 reg | R92C_SYS_FUNC_EN_ELDR); 1361 } 1362 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1363 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1364 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1365 urtwn_write_2(sc, R92C_SYS_CLKR, 1366 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1367 } 1368 } 1369 1370 static int 1371 urtwn_read_chipid(struct urtwn_softc *sc) 1372 { 1373 uint32_t reg; 1374 1375 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1376 1377 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1378 ISSET(sc->chip, URTWN_CHIP_92EU)) 1379 return 0; 1380 1381 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1382 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1383 /* test chip, not supported */ 1384 return EIO; 1385 } 1386 if (reg & R92C_SYS_CFG_TYPE_92C) { 1387 sc->chip |= URTWN_CHIP_92C; 1388 /* Check if it is a castrated 8192C. */ 1389 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1390 R92C_HPON_FSM_CHIP_BONDING_ID) == 1391 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1392 sc->chip |= URTWN_CHIP_92C_1T2R; 1393 } 1394 } 1395 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1396 sc->chip |= URTWN_CHIP_UMC; 1397 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1398 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1399 } 1400 } 1401 return 0; 1402 } 1403 1404 #ifdef URTWN_DEBUG 1405 static void 1406 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1407 { 1408 1409 aprint_normal_dev(sc->sc_dev, 1410 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1411 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1412 1413 aprint_normal_dev(sc->sc_dev, 1414 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1415 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1416 1417 aprint_normal_dev(sc->sc_dev, 1418 "macaddr %s\n", 1419 ether_sprintf(rp->macaddr)); 1420 1421 aprint_normal_dev(sc->sc_dev, 1422 "string %s, subcustomer_id %#x\n", 1423 rp->string, rp->subcustomer_id); 1424 1425 aprint_normal_dev(sc->sc_dev, 1426 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1427 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1428 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1429 1430 aprint_normal_dev(sc->sc_dev, 1431 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1432 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1433 rp->ht40_1s_tx_pwr[0][2], 1434 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1435 rp->ht40_1s_tx_pwr[1][2]); 1436 1437 aprint_normal_dev(sc->sc_dev, 1438 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1439 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1440 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1441 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1442 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1443 1444 aprint_normal_dev(sc->sc_dev, 1445 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1446 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1447 rp->ht20_tx_pwr_diff[2] & 0xf, 1448 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1449 rp->ht20_tx_pwr_diff[2] >> 4); 1450 1451 aprint_normal_dev(sc->sc_dev, 1452 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1453 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1454 rp->ofdm_tx_pwr_diff[2] & 0xf, 1455 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1456 rp->ofdm_tx_pwr_diff[2] >> 4); 1457 1458 aprint_normal_dev(sc->sc_dev, 1459 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1460 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1461 rp->ht40_max_pwr[2] & 0xf, 1462 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1463 rp->ht40_max_pwr[2] >> 4); 1464 1465 aprint_normal_dev(sc->sc_dev, 1466 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1467 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1468 rp->ht20_max_pwr[2] & 0xf, 1469 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1470 rp->ht20_max_pwr[2] >> 4); 1471 1472 aprint_normal_dev(sc->sc_dev, 1473 "xtal_calib %d, tssi %d %d, thermal %d\n", 1474 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1475 1476 aprint_normal_dev(sc->sc_dev, 1477 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1478 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1479 1480 aprint_normal_dev(sc->sc_dev, 1481 "channnel_plan %d, version %d customer_id %#x\n", 1482 rp->channel_plan, rp->version, rp->curstomer_id); 1483 } 1484 #endif 1485 1486 static void 1487 urtwn_read_rom(struct urtwn_softc *sc) 1488 { 1489 struct ieee80211com *ic = &sc->sc_ic; 1490 struct r92c_rom *rom = &sc->rom; 1491 1492 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1493 1494 mutex_enter(&sc->sc_write_mtx); 1495 1496 /* Read full ROM image. */ 1497 urtwn_efuse_read(sc); 1498 #ifdef URTWN_DEBUG 1499 if (urtwn_debug & DBG_REG) 1500 urtwn_dump_rom(sc, rom); 1501 #endif 1502 1503 /* XXX Weird but this is what the vendor driver does. */ 1504 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1505 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1506 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1507 1508 DPRINTFN(DBG_INIT, 1509 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1510 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1511 1512 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1513 1514 sc->sc_rf_write = urtwn_r92c_rf_write; 1515 sc->sc_power_on = urtwn_r92c_power_on; 1516 sc->sc_dma_init = urtwn_r92c_dma_init; 1517 1518 mutex_exit(&sc->sc_write_mtx); 1519 } 1520 1521 static void 1522 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1523 { 1524 struct ieee80211com *ic = &sc->sc_ic; 1525 uint8_t *rom = sc->r88e_rom; 1526 uint32_t reg; 1527 uint16_t addr = 0; 1528 uint8_t off, msk, tmp; 1529 int i; 1530 1531 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1532 1533 mutex_enter(&sc->sc_write_mtx); 1534 1535 off = 0; 1536 urtwn_efuse_switch_power(sc); 1537 1538 /* Read full ROM image. */ 1539 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1540 while (addr < 4096) { 1541 reg = urtwn_efuse_read_1(sc, addr); 1542 if (reg == 0xff) 1543 break; 1544 addr++; 1545 if ((reg & 0x1f) == 0x0f) { 1546 tmp = (reg & 0xe0) >> 5; 1547 reg = urtwn_efuse_read_1(sc, addr); 1548 if ((reg & 0x0f) != 0x0f) 1549 off = ((reg & 0xf0) >> 1) | tmp; 1550 addr++; 1551 } else 1552 off = reg >> 4; 1553 msk = reg & 0xf; 1554 for (i = 0; i < 4; i++) { 1555 if (msk & (1 << i)) 1556 continue; 1557 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1558 addr++; 1559 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1560 addr++; 1561 } 1562 } 1563 #ifdef URTWN_DEBUG 1564 if (urtwn_debug & DBG_REG) { 1565 } 1566 #endif 1567 1568 addr = 0x10; 1569 for (i = 0; i < 6; i++) 1570 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1571 for (i = 0; i < 5; i++) 1572 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1573 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1574 if (sc->bw20_tx_pwr_diff & 0x08) 1575 sc->bw20_tx_pwr_diff |= 0xf0; 1576 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1577 if (sc->ofdm_tx_pwr_diff & 0x08) 1578 sc->ofdm_tx_pwr_diff |= 0xf0; 1579 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1580 1581 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1582 1583 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1584 sc->sc_power_on = urtwn_r92e_power_on; 1585 sc->sc_rf_write = urtwn_r92e_rf_write; 1586 } else { 1587 sc->sc_power_on = urtwn_r88e_power_on; 1588 sc->sc_rf_write = urtwn_r88e_rf_write; 1589 } 1590 sc->sc_dma_init = urtwn_r88e_dma_init; 1591 1592 mutex_exit(&sc->sc_write_mtx); 1593 } 1594 1595 static int 1596 urtwn_media_change(struct ifnet *ifp) 1597 { 1598 int error; 1599 1600 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1601 1602 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1603 return error; 1604 1605 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1606 (IFF_UP | IFF_RUNNING)) { 1607 urtwn_init(ifp); 1608 } 1609 return 0; 1610 } 1611 1612 /* 1613 * Initialize rate adaptation in firmware. 1614 */ 1615 static int __noinline 1616 urtwn_ra_init(struct urtwn_softc *sc) 1617 { 1618 static const uint8_t map[] = { 1619 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1620 }; 1621 struct ieee80211com *ic = &sc->sc_ic; 1622 struct ieee80211_node *ni = ic->ic_bss; 1623 struct ieee80211_rateset *rs = &ni->ni_rates; 1624 struct r92c_fw_cmd_macid_cfg cmd; 1625 uint32_t rates, basicrates; 1626 uint32_t rrsr_mask, rrsr_rate; 1627 uint8_t mode; 1628 size_t maxrate, maxbasicrate, i, j; 1629 int error; 1630 1631 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1632 1633 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1634 1635 /* Get normal and basic rates mask. */ 1636 rates = basicrates = 1; 1637 maxrate = maxbasicrate = 0; 1638 for (i = 0; i < rs->rs_nrates; i++) { 1639 /* Convert 802.11 rate to HW rate index. */ 1640 for (j = 0; j < __arraycount(map); j++) { 1641 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1642 break; 1643 } 1644 } 1645 if (j == __arraycount(map)) { 1646 /* Unknown rate, skip. */ 1647 continue; 1648 } 1649 1650 rates |= 1U << j; 1651 if (j > maxrate) { 1652 maxrate = j; 1653 } 1654 1655 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1656 basicrates |= 1U << j; 1657 if (j > maxbasicrate) { 1658 maxbasicrate = j; 1659 } 1660 } 1661 } 1662 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1663 mode = R92C_RAID_11B; 1664 } else { 1665 mode = R92C_RAID_11BG; 1666 } 1667 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1668 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1669 "maxrate=%jx, maxbasicrate=%jx", 1670 rates, basicrates, maxrate, maxbasicrate); 1671 1672 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1673 maxbasicrate |= R92C_RATE_SHORTGI; 1674 maxrate |= R92C_RATE_SHORTGI; 1675 } 1676 1677 /* Set rates mask for group addressed frames. */ 1678 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1679 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1680 cmd.macid |= RTWN_MACID_SHORTGI; 1681 cmd.mask = htole32((mode << 28) | basicrates); 1682 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1683 if (error != 0) { 1684 aprint_error_dev(sc->sc_dev, 1685 "could not add broadcast station\n"); 1686 return error; 1687 } 1688 /* Set initial MRR rate. */ 1689 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1690 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1691 1692 /* Set rates mask for unicast frames. */ 1693 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1694 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1695 cmd.macid |= RTWN_MACID_SHORTGI; 1696 cmd.mask = htole32((mode << 28) | rates); 1697 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1698 if (error != 0) { 1699 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1700 return error; 1701 } 1702 /* Set initial MRR rate. */ 1703 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1704 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1705 1706 rrsr_rate = ic->ic_fixed_rate; 1707 if (rrsr_rate == -1) 1708 rrsr_rate = 11; 1709 1710 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1711 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1712 1713 /* Indicate highest supported rate. */ 1714 ni->ni_txrate = rs->rs_nrates - 1; 1715 1716 return 0; 1717 } 1718 1719 static int 1720 urtwn_get_nettype(struct urtwn_softc *sc) 1721 { 1722 struct ieee80211com *ic = &sc->sc_ic; 1723 int type; 1724 1725 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1726 1727 switch (ic->ic_opmode) { 1728 case IEEE80211_M_STA: 1729 type = R92C_CR_NETTYPE_INFRA; 1730 break; 1731 1732 case IEEE80211_M_IBSS: 1733 type = R92C_CR_NETTYPE_ADHOC; 1734 break; 1735 1736 default: 1737 type = R92C_CR_NETTYPE_NOLINK; 1738 break; 1739 } 1740 1741 return type; 1742 } 1743 1744 static void 1745 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1746 { 1747 uint8_t reg; 1748 1749 URTWNHIST_FUNC(); 1750 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1751 1752 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1753 1754 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1755 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1756 } 1757 1758 static void 1759 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1760 { 1761 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1762 uint64_t tsf; 1763 1764 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1765 1766 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1767 1768 /* Enable TSF synchronization. */ 1769 urtwn_write_1(sc, R92C_BCN_CTRL, 1770 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1771 1772 /* Correct TSF */ 1773 urtwn_write_1(sc, R92C_BCN_CTRL, 1774 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1775 1776 /* Set initial TSF. */ 1777 tsf = ni->ni_tstamp.tsf; 1778 tsf = le64toh(tsf); 1779 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1780 tsf -= IEEE80211_DUR_TU; 1781 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1782 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1783 1784 urtwn_write_1(sc, R92C_BCN_CTRL, 1785 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1786 } 1787 1788 static void 1789 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1790 { 1791 uint8_t reg; 1792 1793 URTWNHIST_FUNC(); 1794 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1795 1796 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1797 1798 if (led == URTWN_LED_LINK) { 1799 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1800 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1801 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1802 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1803 (R92C_LEDCFG0_DIS << 1)); 1804 if (on) { 1805 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1806 R92E_LEDSON; 1807 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1808 } 1809 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1810 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1811 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1812 if (!on) { 1813 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1814 urtwn_write_1(sc, R92C_LEDCFG2, 1815 reg | R92C_LEDCFG0_DIS); 1816 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1817 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1818 reg & 0xfe); 1819 } 1820 } else { 1821 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1822 if (!on) { 1823 reg |= R92C_LEDCFG0_DIS; 1824 } 1825 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1826 } 1827 sc->ledlink = on; /* Save LED state. */ 1828 } 1829 } 1830 1831 static void 1832 urtwn_calib_to(void *arg) 1833 { 1834 struct urtwn_softc *sc = arg; 1835 1836 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1837 1838 if (sc->sc_dying) 1839 return; 1840 1841 /* Do it in a process context. */ 1842 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1843 } 1844 1845 /* ARGSUSED */ 1846 static void 1847 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1848 { 1849 struct r92c_fw_cmd_rssi cmd; 1850 struct r92e_fw_cmd_rssi cmde; 1851 1852 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1853 1854 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1855 goto restart_timer; 1856 1857 mutex_enter(&sc->sc_write_mtx); 1858 if (sc->avg_pwdb != -1) { 1859 /* Indicate Rx signal strength to FW for rate adaptation. */ 1860 memset(&cmd, 0, sizeof(cmd)); 1861 memset(&cmde, 0, sizeof(cmde)); 1862 cmd.macid = 0; /* BSS. */ 1863 cmde.macid = 0; /* BSS. */ 1864 cmd.pwdb = sc->avg_pwdb; 1865 cmde.pwdb = sc->avg_pwdb; 1866 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1867 sc->avg_pwdb, 0, 0, 0); 1868 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1869 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1870 sizeof(cmd)); 1871 } else { 1872 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1873 sizeof(cmde)); 1874 } 1875 } 1876 1877 /* Do temperature compensation. */ 1878 urtwn_temp_calib(sc); 1879 mutex_exit(&sc->sc_write_mtx); 1880 1881 restart_timer: 1882 if (!sc->sc_dying) { 1883 /* Restart calibration timer. */ 1884 callout_schedule(&sc->sc_calib_to, hz); 1885 } 1886 } 1887 1888 static void 1889 urtwn_next_scan(void *arg) 1890 { 1891 struct urtwn_softc *sc = arg; 1892 int s; 1893 1894 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1895 1896 if (sc->sc_dying) 1897 return; 1898 1899 s = splnet(); 1900 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1901 ieee80211_next_scan(&sc->sc_ic); 1902 splx(s); 1903 } 1904 1905 static void 1906 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1907 { 1908 URTWNHIST_FUNC(); 1909 URTWNHIST_CALLARGS("new node %06jx%06jx", 1910 ni->ni_macaddr[0] << 2 | 1911 ni->ni_macaddr[1] << 1 | 1912 ni->ni_macaddr[2], 1913 ni->ni_macaddr[3] << 2 | 1914 ni->ni_macaddr[4] << 1 | 1915 ni->ni_macaddr[5], 1916 0, 0); 1917 /* start with lowest Tx rate */ 1918 ni->ni_txrate = 0; 1919 } 1920 1921 static int 1922 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1923 { 1924 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1925 struct urtwn_cmd_newstate cmd; 1926 1927 URTWNHIST_FUNC(); 1928 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1929 1930 callout_stop(&sc->sc_scan_to); 1931 callout_stop(&sc->sc_calib_to); 1932 1933 /* Do it in a process context. */ 1934 cmd.state = nstate; 1935 cmd.arg = arg; 1936 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1937 return 0; 1938 } 1939 1940 static void 1941 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1942 { 1943 struct urtwn_cmd_newstate *cmd = arg; 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 struct ieee80211_node *ni; 1946 enum ieee80211_state ostate = ic->ic_state; 1947 enum ieee80211_state nstate = cmd->state; 1948 uint32_t reg; 1949 uint8_t sifs_time, msr; 1950 int s; 1951 1952 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1953 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1954 1955 s = splnet(); 1956 mutex_enter(&sc->sc_write_mtx); 1957 1958 callout_stop(&sc->sc_scan_to); 1959 callout_stop(&sc->sc_calib_to); 1960 1961 switch (ostate) { 1962 case IEEE80211_S_INIT: 1963 break; 1964 1965 case IEEE80211_S_SCAN: 1966 if (nstate != IEEE80211_S_SCAN) { 1967 /* 1968 * End of scanning 1969 */ 1970 /* flush 4-AC Queue after site_survey */ 1971 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1972 1973 /* Allow Rx from our BSSID only. */ 1974 urtwn_write_4(sc, R92C_RCR, 1975 urtwn_read_4(sc, R92C_RCR) | 1976 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1977 } 1978 break; 1979 1980 case IEEE80211_S_AUTH: 1981 case IEEE80211_S_ASSOC: 1982 break; 1983 1984 case IEEE80211_S_RUN: 1985 /* Turn link LED off. */ 1986 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1987 1988 /* Set media status to 'No Link'. */ 1989 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1990 1991 /* Stop Rx of data frames. */ 1992 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1993 1994 /* Reset TSF. */ 1995 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1996 1997 /* Disable TSF synchronization. */ 1998 urtwn_write_1(sc, R92C_BCN_CTRL, 1999 urtwn_read_1(sc, R92C_BCN_CTRL) | 2000 R92C_BCN_CTRL_DIS_TSF_UDT0); 2001 2002 /* Back to 20MHz mode */ 2003 urtwn_set_chan(sc, ic->ic_curchan, 2004 IEEE80211_HTINFO_2NDCHAN_NONE); 2005 2006 if (ic->ic_opmode == IEEE80211_M_IBSS || 2007 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2008 /* Stop BCN */ 2009 urtwn_write_1(sc, R92C_BCN_CTRL, 2010 urtwn_read_1(sc, R92C_BCN_CTRL) & 2011 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2012 } 2013 2014 /* Reset EDCA parameters. */ 2015 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2016 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2017 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2018 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2019 2020 /* flush all cam entries */ 2021 urtwn_cam_init(sc); 2022 break; 2023 } 2024 2025 switch (nstate) { 2026 case IEEE80211_S_INIT: 2027 /* Turn link LED off. */ 2028 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2029 break; 2030 2031 case IEEE80211_S_SCAN: 2032 if (ostate != IEEE80211_S_SCAN) { 2033 /* 2034 * Begin of scanning 2035 */ 2036 2037 /* Set gain for scanning. */ 2038 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2039 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2040 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2041 2042 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2043 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2044 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2045 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2046 } 2047 2048 /* Set media status to 'No Link'. */ 2049 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2050 2051 /* Allow Rx from any BSSID. */ 2052 urtwn_write_4(sc, R92C_RCR, 2053 urtwn_read_4(sc, R92C_RCR) & 2054 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2055 2056 /* Stop Rx of data frames. */ 2057 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2058 2059 /* Disable update TSF */ 2060 urtwn_write_1(sc, R92C_BCN_CTRL, 2061 urtwn_read_1(sc, R92C_BCN_CTRL) | 2062 R92C_BCN_CTRL_DIS_TSF_UDT0); 2063 } 2064 2065 /* Make link LED blink during scan. */ 2066 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2067 2068 /* Pause AC Tx queues. */ 2069 urtwn_write_1(sc, R92C_TXPAUSE, 2070 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2071 2072 urtwn_set_chan(sc, ic->ic_curchan, 2073 IEEE80211_HTINFO_2NDCHAN_NONE); 2074 2075 /* Start periodic scan. */ 2076 if (!sc->sc_dying) 2077 callout_schedule(&sc->sc_scan_to, hz / 5); 2078 break; 2079 2080 case IEEE80211_S_AUTH: 2081 /* Set initial gain under link. */ 2082 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2083 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2084 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2085 2086 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2087 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2088 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2089 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2090 } 2091 2092 /* Set media status to 'No Link'. */ 2093 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2094 2095 /* Allow Rx from any BSSID. */ 2096 urtwn_write_4(sc, R92C_RCR, 2097 urtwn_read_4(sc, R92C_RCR) & 2098 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2099 2100 urtwn_set_chan(sc, ic->ic_curchan, 2101 IEEE80211_HTINFO_2NDCHAN_NONE); 2102 break; 2103 2104 case IEEE80211_S_ASSOC: 2105 break; 2106 2107 case IEEE80211_S_RUN: 2108 ni = ic->ic_bss; 2109 2110 /* XXX: Set 20MHz mode */ 2111 urtwn_set_chan(sc, ic->ic_curchan, 2112 IEEE80211_HTINFO_2NDCHAN_NONE); 2113 2114 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2115 /* Back to 20MHz mode */ 2116 urtwn_set_chan(sc, ic->ic_curchan, 2117 IEEE80211_HTINFO_2NDCHAN_NONE); 2118 2119 /* Set media status to 'No Link'. */ 2120 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2121 2122 /* Enable Rx of data frames. */ 2123 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2124 2125 /* Allow Rx from any BSSID. */ 2126 urtwn_write_4(sc, R92C_RCR, 2127 urtwn_read_4(sc, R92C_RCR) & 2128 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2129 2130 /* Accept Rx data/control/management frames */ 2131 urtwn_write_4(sc, R92C_RCR, 2132 urtwn_read_4(sc, R92C_RCR) | 2133 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2134 2135 /* Turn link LED on. */ 2136 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2137 break; 2138 } 2139 2140 /* Set media status to 'Associated'. */ 2141 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2142 2143 /* Set BSSID. */ 2144 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2145 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2146 2147 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2148 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2149 } else { 2150 /* 802.11b/g */ 2151 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2152 } 2153 2154 /* Enable Rx of data frames. */ 2155 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2156 2157 /* Set beacon interval. */ 2158 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2159 2160 msr = urtwn_read_1(sc, R92C_MSR); 2161 msr &= R92C_MSR_MASK; 2162 switch (ic->ic_opmode) { 2163 case IEEE80211_M_STA: 2164 /* Allow Rx from our BSSID only. */ 2165 urtwn_write_4(sc, R92C_RCR, 2166 urtwn_read_4(sc, R92C_RCR) | 2167 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2168 2169 /* Enable TSF synchronization. */ 2170 urtwn_tsf_sync_enable(sc); 2171 2172 msr |= R92C_MSR_INFRA; 2173 break; 2174 case IEEE80211_M_HOSTAP: 2175 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2176 2177 /* Allow Rx from any BSSID. */ 2178 urtwn_write_4(sc, R92C_RCR, 2179 urtwn_read_4(sc, R92C_RCR) & 2180 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2181 2182 /* Reset TSF timer to zero. */ 2183 reg = urtwn_read_4(sc, R92C_TCR); 2184 reg &= ~0x01; 2185 urtwn_write_4(sc, R92C_TCR, reg); 2186 reg |= 0x01; 2187 urtwn_write_4(sc, R92C_TCR, reg); 2188 2189 msr |= R92C_MSR_AP; 2190 break; 2191 default: 2192 msr |= R92C_MSR_ADHOC; 2193 break; 2194 } 2195 urtwn_write_1(sc, R92C_MSR, msr); 2196 2197 sifs_time = 10; 2198 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2199 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2200 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2201 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2202 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2203 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2204 2205 /* Initialize rate adaptation. */ 2206 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2207 ISSET(sc->chip, URTWN_CHIP_92EU)) 2208 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2209 else 2210 urtwn_ra_init(sc); 2211 2212 /* Turn link LED on. */ 2213 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2214 2215 /* Reset average RSSI. */ 2216 sc->avg_pwdb = -1; 2217 2218 /* Reset temperature calibration state machine. */ 2219 sc->thcal_state = 0; 2220 sc->thcal_lctemp = 0; 2221 2222 /* Start periodic calibration. */ 2223 if (!sc->sc_dying) 2224 callout_schedule(&sc->sc_calib_to, hz); 2225 break; 2226 } 2227 2228 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2229 2230 mutex_exit(&sc->sc_write_mtx); 2231 splx(s); 2232 } 2233 2234 static int 2235 urtwn_wme_update(struct ieee80211com *ic) 2236 { 2237 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2238 2239 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2240 2241 /* don't override default WME values if WME is not actually enabled */ 2242 if (!(ic->ic_flags & IEEE80211_F_WME)) 2243 return 0; 2244 2245 /* Do it in a process context. */ 2246 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2247 return 0; 2248 } 2249 2250 static void 2251 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2252 { 2253 static const uint16_t ac2reg[WME_NUM_AC] = { 2254 R92C_EDCA_BE_PARAM, 2255 R92C_EDCA_BK_PARAM, 2256 R92C_EDCA_VI_PARAM, 2257 R92C_EDCA_VO_PARAM 2258 }; 2259 struct ieee80211com *ic = &sc->sc_ic; 2260 const struct wmeParams *wmep; 2261 int ac, aifs, slottime; 2262 int s; 2263 2264 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2265 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2266 2267 s = splnet(); 2268 mutex_enter(&sc->sc_write_mtx); 2269 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2270 for (ac = 0; ac < WME_NUM_AC; ac++) { 2271 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2272 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2273 aifs = wmep->wmep_aifsn * slottime + 10; 2274 urtwn_write_4(sc, ac2reg[ac], 2275 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2276 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2277 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2278 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2279 } 2280 mutex_exit(&sc->sc_write_mtx); 2281 splx(s); 2282 } 2283 2284 static void 2285 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2286 { 2287 int pwdb; 2288 2289 URTWNHIST_FUNC(); 2290 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2291 2292 /* Convert antenna signal to percentage. */ 2293 if (rssi <= -100 || rssi >= 20) 2294 pwdb = 0; 2295 else if (rssi >= 0) 2296 pwdb = 100; 2297 else 2298 pwdb = 100 + rssi; 2299 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2300 if (rate <= 3) { 2301 /* CCK gain is smaller than OFDM/MCS gain. */ 2302 pwdb += 6; 2303 if (pwdb > 100) 2304 pwdb = 100; 2305 if (pwdb <= 14) 2306 pwdb -= 4; 2307 else if (pwdb <= 26) 2308 pwdb -= 8; 2309 else if (pwdb <= 34) 2310 pwdb -= 6; 2311 else if (pwdb <= 42) 2312 pwdb -= 2; 2313 } 2314 } 2315 if (sc->avg_pwdb == -1) /* Init. */ 2316 sc->avg_pwdb = pwdb; 2317 else if (sc->avg_pwdb < pwdb) 2318 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2319 else 2320 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2321 2322 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2323 rate, rssi, pwdb, sc->avg_pwdb); 2324 } 2325 2326 static int8_t 2327 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2328 { 2329 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2330 struct r92c_rx_phystat *phy; 2331 struct r92c_rx_cck *cck; 2332 uint8_t rpt; 2333 int8_t rssi; 2334 2335 URTWNHIST_FUNC(); 2336 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2337 2338 if (rate <= 3) { 2339 cck = (struct r92c_rx_cck *)physt; 2340 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2341 rpt = (cck->agc_rpt >> 5) & 0x3; 2342 rssi = (cck->agc_rpt & 0x1f) << 1; 2343 } else { 2344 rpt = (cck->agc_rpt >> 6) & 0x3; 2345 rssi = cck->agc_rpt & 0x3e; 2346 } 2347 rssi = cckoff[rpt] - rssi; 2348 } else { /* OFDM/HT. */ 2349 phy = (struct r92c_rx_phystat *)physt; 2350 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2351 } 2352 return rssi; 2353 } 2354 2355 static int8_t 2356 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2357 { 2358 struct r92c_rx_phystat *phy; 2359 struct r88e_rx_cck *cck; 2360 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2361 int8_t rssi; 2362 2363 URTWNHIST_FUNC(); 2364 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2365 2366 rssi = 0; 2367 if (rate <= 3) { 2368 cck = (struct r88e_rx_cck *)physt; 2369 cck_agc_rpt = cck->agc_rpt; 2370 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2371 vga_idx = cck_agc_rpt & 0x1f; 2372 switch (lna_idx) { 2373 case 7: 2374 if (vga_idx <= 27) 2375 rssi = -100 + 2* (27 - vga_idx); 2376 else 2377 rssi = -100; 2378 break; 2379 case 6: 2380 rssi = -48 + 2 * (2 - vga_idx); 2381 break; 2382 case 5: 2383 rssi = -42 + 2 * (7 - vga_idx); 2384 break; 2385 case 4: 2386 rssi = -36 + 2 * (7 - vga_idx); 2387 break; 2388 case 3: 2389 rssi = -24 + 2 * (7 - vga_idx); 2390 break; 2391 case 2: 2392 rssi = -12 + 2 * (5 - vga_idx); 2393 break; 2394 case 1: 2395 rssi = 8 - (2 * vga_idx); 2396 break; 2397 case 0: 2398 rssi = 14 - (2 * vga_idx); 2399 break; 2400 } 2401 rssi += 6; 2402 } else { /* OFDM/HT. */ 2403 phy = (struct r92c_rx_phystat *)physt; 2404 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2405 } 2406 return rssi; 2407 } 2408 2409 static void 2410 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2411 { 2412 struct ieee80211com *ic = &sc->sc_ic; 2413 struct ifnet *ifp = ic->ic_ifp; 2414 struct ieee80211_frame *wh; 2415 struct ieee80211_node *ni; 2416 struct r92c_rx_desc_usb *stat; 2417 uint32_t rxdw0, rxdw3; 2418 struct mbuf *m; 2419 uint8_t rate; 2420 int8_t rssi = 0; 2421 int s, infosz; 2422 2423 URTWNHIST_FUNC(); 2424 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2425 2426 stat = (struct r92c_rx_desc_usb *)buf; 2427 rxdw0 = le32toh(stat->rxdw0); 2428 rxdw3 = le32toh(stat->rxdw3); 2429 2430 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2431 /* 2432 * This should not happen since we setup our Rx filter 2433 * to not receive these frames. 2434 */ 2435 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2436 if_statinc(ifp, if_ierrors); 2437 return; 2438 } 2439 /* 2440 * XXX: This will drop most control packets. Do we really 2441 * want this in IEEE80211_M_MONITOR mode? 2442 */ 2443 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2444 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2445 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2446 ic->ic_stats.is_rx_tooshort++; 2447 if_statinc(ifp, if_ierrors); 2448 return; 2449 } 2450 if (__predict_false(pktlen > MCLBYTES)) { 2451 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2452 if_statinc(ifp, if_ierrors); 2453 return; 2454 } 2455 2456 rate = MS(rxdw3, R92C_RXDW3_RATE); 2457 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2458 2459 /* Get RSSI from PHY status descriptor if present. */ 2460 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2461 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2462 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2463 else 2464 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2465 /* Update our average RSSI. */ 2466 urtwn_update_avgrssi(sc, rate, rssi); 2467 } 2468 2469 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2470 pktlen, rate, infosz, rssi); 2471 2472 MGETHDR(m, M_DONTWAIT, MT_DATA); 2473 if (__predict_false(m == NULL)) { 2474 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2475 ic->ic_stats.is_rx_nobuf++; 2476 if_statinc(ifp, if_ierrors); 2477 return; 2478 } 2479 if (pktlen > (int)MHLEN) { 2480 MCLGET(m, M_DONTWAIT); 2481 if (__predict_false(!(m->m_flags & M_EXT))) { 2482 aprint_error_dev(sc->sc_dev, 2483 "couldn't allocate rx mbuf cluster\n"); 2484 m_freem(m); 2485 ic->ic_stats.is_rx_nobuf++; 2486 if_statinc(ifp, if_ierrors); 2487 return; 2488 } 2489 } 2490 2491 /* Finalize mbuf. */ 2492 m_set_rcvif(m, ifp); 2493 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2494 memcpy(mtod(m, uint8_t *), wh, pktlen); 2495 m->m_pkthdr.len = m->m_len = pktlen; 2496 2497 s = splnet(); 2498 if (__predict_false(sc->sc_drvbpf != NULL)) { 2499 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2500 2501 tap->wr_flags = 0; 2502 if (!(rxdw3 & R92C_RXDW3_HT)) { 2503 switch (rate) { 2504 /* CCK. */ 2505 case 0: tap->wr_rate = 2; break; 2506 case 1: tap->wr_rate = 4; break; 2507 case 2: tap->wr_rate = 11; break; 2508 case 3: tap->wr_rate = 22; break; 2509 /* OFDM. */ 2510 case 4: tap->wr_rate = 12; break; 2511 case 5: tap->wr_rate = 18; break; 2512 case 6: tap->wr_rate = 24; break; 2513 case 7: tap->wr_rate = 36; break; 2514 case 8: tap->wr_rate = 48; break; 2515 case 9: tap->wr_rate = 72; break; 2516 case 10: tap->wr_rate = 96; break; 2517 case 11: tap->wr_rate = 108; break; 2518 } 2519 } else if (rate >= 12) { /* MCS0~15. */ 2520 /* Bit 7 set means HT MCS instead of rate. */ 2521 tap->wr_rate = 0x80 | (rate - 12); 2522 } 2523 tap->wr_dbm_antsignal = rssi; 2524 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2525 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2526 2527 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2528 } 2529 2530 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2531 2532 /* push the frame up to the 802.11 stack */ 2533 ieee80211_input(ic, m, ni, rssi, 0); 2534 2535 /* Node is no longer needed. */ 2536 ieee80211_free_node(ni); 2537 2538 splx(s); 2539 } 2540 2541 static void 2542 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2543 { 2544 struct urtwn_rx_data *data = priv; 2545 struct urtwn_softc *sc = data->sc; 2546 struct r92c_rx_desc_usb *stat; 2547 size_t pidx = data->pidx; 2548 uint32_t rxdw0; 2549 uint8_t *buf; 2550 int len, totlen, pktlen, infosz, npkts, pktspacing; 2551 2552 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2553 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2554 2555 mutex_enter(&sc->sc_rx_mtx); 2556 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2557 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2558 /* Put this Rx buffer back to our free list. */ 2559 mutex_exit(&sc->sc_rx_mtx); 2560 2561 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2562 if (status == USBD_STALLED) 2563 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2564 else if (status != USBD_CANCELLED) 2565 goto resubmit; 2566 return; 2567 } 2568 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2569 2570 if (__predict_false(len < (int)sizeof(*stat))) { 2571 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2572 goto resubmit; 2573 } 2574 buf = data->buf; 2575 2576 /* Get the number of encapsulated frames. */ 2577 stat = (struct r92c_rx_desc_usb *)buf; 2578 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2579 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2580 else 2581 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2582 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2583 2584 if (npkts != 0) 2585 rnd_add_uint32(&sc->rnd_source, npkts); 2586 2587 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2588 pktspacing = 8; 2589 else 2590 pktspacing = 128; 2591 2592 /* Process all of them. */ 2593 while (npkts-- > 0 && len > 0) { 2594 if (__predict_false(len < (int)sizeof(*stat))) { 2595 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2596 len, 0, 0, 0); 2597 break; 2598 } 2599 stat = (struct r92c_rx_desc_usb *)buf; 2600 rxdw0 = le32toh(stat->rxdw0); 2601 2602 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2603 if (__predict_false(pktlen == 0)) { 2604 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2605 break; 2606 } 2607 2608 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2609 2610 /* Make sure everything fits in xfer. */ 2611 totlen = sizeof(*stat) + infosz + pktlen; 2612 if (__predict_false(totlen > len)) { 2613 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2614 (int)sizeof(*stat), infosz, pktlen, len); 2615 break; 2616 } 2617 2618 /* Process 802.11 frame. */ 2619 urtwn_rx_frame(sc, buf, pktlen); 2620 2621 totlen = roundup2(totlen, pktspacing); 2622 buf += totlen; 2623 len -= totlen; 2624 } 2625 2626 resubmit: 2627 /* Setup a new transfer. */ 2628 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2629 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2630 (void)usbd_transfer(xfer); 2631 } 2632 2633 static void 2634 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2635 { 2636 size_t pidx = data->pidx; 2637 2638 mutex_enter(&sc->sc_tx_mtx); 2639 /* Put this Tx buffer back to our free list. */ 2640 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2641 mutex_exit(&sc->sc_tx_mtx); 2642 } 2643 2644 static void 2645 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2646 { 2647 struct urtwn_tx_data *data = priv; 2648 struct urtwn_softc *sc = data->sc; 2649 struct ifnet *ifp = &sc->sc_if; 2650 size_t pidx = data->pidx; 2651 int s; 2652 2653 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2654 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2655 2656 urtwn_put_tx_data(sc, data); 2657 2658 s = splnet(); 2659 sc->tx_timer = 0; 2660 ifp->if_flags &= ~IFF_OACTIVE; 2661 2662 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2663 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2664 if (status == USBD_STALLED) { 2665 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2666 usbd_clear_endpoint_stall_async(pipe); 2667 } 2668 device_printf(sc->sc_dev, "transmit failed, %s\n", 2669 usbd_errstr(status)); 2670 if_statinc(ifp, if_oerrors); 2671 } 2672 splx(s); 2673 return; 2674 } 2675 2676 if_statinc(ifp, if_opackets); 2677 urtwn_start(ifp); 2678 splx(s); 2679 2680 } 2681 2682 static int 2683 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2684 struct urtwn_tx_data *data) 2685 { 2686 struct ieee80211com *ic = &sc->sc_ic; 2687 struct ieee80211_frame *wh; 2688 struct ieee80211_key *k = NULL; 2689 struct r92c_tx_desc_usb *txd; 2690 size_t i, padsize, xferlen, txd_len; 2691 uint16_t seq, sum; 2692 uint8_t raid, type, tid; 2693 int s, hasqos, error; 2694 2695 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2696 2697 wh = mtod(m, struct ieee80211_frame *); 2698 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2699 txd_len = sizeof(*txd); 2700 2701 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2702 txd_len = 32; 2703 2704 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2705 k = ieee80211_crypto_encap(ic, ni, m); 2706 if (k == NULL) { 2707 urtwn_put_tx_data(sc, data); 2708 m_free(m); 2709 return ENOBUFS; 2710 } 2711 2712 /* packet header may have moved, reset our local pointer */ 2713 wh = mtod(m, struct ieee80211_frame *); 2714 } 2715 2716 if (__predict_false(sc->sc_drvbpf != NULL)) { 2717 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2718 2719 tap->wt_flags = 0; 2720 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2721 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2722 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2723 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2724 2725 /* XXX: set tap->wt_rate? */ 2726 2727 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2728 } 2729 2730 /* non-qos data frames */ 2731 tid = R92C_TXDW1_QSEL_BE; 2732 if ((hasqos = ieee80211_has_qos(wh))) { 2733 /* data frames in 11n mode */ 2734 struct ieee80211_qosframe *qwh = (void *)wh; 2735 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2736 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2737 tid = R92C_TXDW1_QSEL_MGNT; 2738 } 2739 2740 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2741 padsize = 8; 2742 else 2743 padsize = 0; 2744 2745 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2746 padsize = 0; 2747 2748 /* Fill Tx descriptor. */ 2749 txd = (struct r92c_tx_desc_usb *)data->buf; 2750 memset(txd, 0, txd_len + padsize); 2751 2752 txd->txdw0 |= htole32( 2753 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2754 SM(R92C_TXDW0_OFFSET, txd_len)); 2755 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2756 txd->txdw0 |= htole32( 2757 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2758 } 2759 2760 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2761 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2762 2763 /* fix pad field */ 2764 if (padsize > 0) { 2765 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2766 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2767 } 2768 2769 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2770 type == IEEE80211_FC0_TYPE_DATA) { 2771 if (ic->ic_curmode == IEEE80211_MODE_11B) 2772 raid = R92C_RAID_11B; 2773 else 2774 raid = R92C_RAID_11BG; 2775 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2776 tid, raid, 0, 0); 2777 2778 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2779 txd->txdw1 |= htole32( 2780 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2781 SM(R92C_TXDW1_QSEL, tid) | 2782 SM(R92C_TXDW1_RAID, raid) | 2783 R92C_TXDW1_AGGBK); 2784 } else 2785 txd->txdw1 |= htole32( 2786 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2787 SM(R92C_TXDW1_QSEL, tid) | 2788 SM(R92C_TXDW1_RAID, raid) | 2789 R92C_TXDW1_AGGBK); 2790 2791 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2792 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2793 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2794 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2795 2796 if (hasqos) { 2797 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2798 } 2799 2800 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2801 /* for 11g */ 2802 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2803 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2804 R92C_TXDW4_HWRTSEN); 2805 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2806 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2807 R92C_TXDW4_HWRTSEN); 2808 } 2809 } 2810 /* Send RTS at OFDM24. */ 2811 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2812 txd->txdw5 |= htole32(0x0001ff00); 2813 /* Send data at OFDM54. */ 2814 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2815 txd->txdw5 |= htole32(0x13 & 0x3f); 2816 else 2817 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2818 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2819 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2820 txd->txdw1 |= htole32( 2821 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2822 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2823 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2824 2825 /* Force CCK1. */ 2826 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2827 /* Use 1Mbps */ 2828 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2829 } else { 2830 /* broadcast or multicast packets */ 2831 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2832 txd->txdw1 |= htole32( 2833 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2834 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2835 2836 /* Force CCK1. */ 2837 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2838 /* Use 1Mbps */ 2839 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2840 } 2841 /* Set sequence number */ 2842 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2843 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2844 txd->txdseq |= htole16(seq); 2845 2846 if (!hasqos) { 2847 /* Use HW sequence numbering for non-QoS frames. */ 2848 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2849 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2850 } 2851 } else { 2852 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2853 R92E_HWSEQ_SHIFT); 2854 if (!hasqos) { 2855 /* Use HW sequence numbering for non-QoS frames. */ 2856 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2857 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2858 } 2859 } 2860 2861 /* Compute Tx descriptor checksum. */ 2862 sum = 0; 2863 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2864 sum ^= ((uint16_t *)txd)[i]; 2865 txd->txdsum = sum; /* NB: already little endian. */ 2866 2867 xferlen = txd_len + m->m_pkthdr.len + padsize; 2868 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2869 2870 s = splnet(); 2871 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2872 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2873 urtwn_txeof); 2874 error = usbd_transfer(data->xfer); 2875 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2876 error != USBD_IN_PROGRESS)) { 2877 splx(s); 2878 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2879 return error; 2880 } 2881 splx(s); 2882 return 0; 2883 } 2884 2885 struct urtwn_tx_data * 2886 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2887 { 2888 struct urtwn_tx_data *data = NULL; 2889 2890 mutex_enter(&sc->sc_tx_mtx); 2891 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2892 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2893 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2894 } 2895 mutex_exit(&sc->sc_tx_mtx); 2896 2897 return data; 2898 } 2899 2900 static void 2901 urtwn_start(struct ifnet *ifp) 2902 { 2903 struct urtwn_softc *sc = ifp->if_softc; 2904 struct ieee80211com *ic = &sc->sc_ic; 2905 struct urtwn_tx_data *data; 2906 struct ether_header *eh; 2907 struct ieee80211_node *ni; 2908 struct mbuf *m; 2909 2910 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2911 2912 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2913 return; 2914 2915 data = NULL; 2916 for (;;) { 2917 /* Send pending management frames first. */ 2918 IF_POLL(&ic->ic_mgtq, m); 2919 if (m != NULL) { 2920 /* Use AC_VO for management frames. */ 2921 2922 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2923 2924 if (data == NULL) { 2925 ifp->if_flags |= IFF_OACTIVE; 2926 DPRINTFN(DBG_TX, "empty tx_free_list", 2927 0, 0, 0, 0); 2928 return; 2929 } 2930 IF_DEQUEUE(&ic->ic_mgtq, m); 2931 ni = M_GETCTX(m, struct ieee80211_node *); 2932 M_CLEARCTX(m); 2933 goto sendit; 2934 } 2935 if (ic->ic_state != IEEE80211_S_RUN) 2936 break; 2937 2938 /* Encapsulate and send data frames. */ 2939 IFQ_POLL(&ifp->if_snd, m); 2940 if (m == NULL) 2941 break; 2942 2943 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2944 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2945 uint8_t qid = WME_AC_BE; 2946 if (ieee80211_has_qos(wh)) { 2947 /* data frames in 11n mode */ 2948 struct ieee80211_qosframe *qwh = (void *)wh; 2949 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2950 qid = TID_TO_WME_AC(tid); 2951 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2952 qid = WME_AC_VO; 2953 } 2954 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2955 2956 if (data == NULL) { 2957 ifp->if_flags |= IFF_OACTIVE; 2958 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2959 return; 2960 } 2961 IFQ_DEQUEUE(&ifp->if_snd, m); 2962 2963 if (m->m_len < (int)sizeof(*eh) && 2964 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2965 device_printf(sc->sc_dev, "m_pullup failed\n"); 2966 if_statinc(ifp, if_oerrors); 2967 urtwn_put_tx_data(sc, data); 2968 m_freem(m); 2969 continue; 2970 } 2971 eh = mtod(m, struct ether_header *); 2972 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2973 if (ni == NULL) { 2974 device_printf(sc->sc_dev, 2975 "unable to find transmit node\n"); 2976 if_statinc(ifp, if_oerrors); 2977 urtwn_put_tx_data(sc, data); 2978 m_freem(m); 2979 continue; 2980 } 2981 2982 bpf_mtap(ifp, m, BPF_D_OUT); 2983 2984 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2985 ieee80211_free_node(ni); 2986 device_printf(sc->sc_dev, 2987 "unable to encapsulate packet\n"); 2988 if_statinc(ifp, if_oerrors); 2989 urtwn_put_tx_data(sc, data); 2990 m_freem(m); 2991 continue; 2992 } 2993 sendit: 2994 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2995 2996 if (urtwn_tx(sc, m, ni, data) != 0) { 2997 m_freem(m); 2998 ieee80211_free_node(ni); 2999 device_printf(sc->sc_dev, 3000 "unable to transmit packet\n"); 3001 if_statinc(ifp, if_oerrors); 3002 urtwn_put_tx_data(sc, data); 3003 continue; 3004 } 3005 m_freem(m); 3006 ieee80211_free_node(ni); 3007 sc->tx_timer = 5; 3008 ifp->if_timer = 1; 3009 } 3010 } 3011 3012 static void 3013 urtwn_watchdog(struct ifnet *ifp) 3014 { 3015 struct urtwn_softc *sc = ifp->if_softc; 3016 3017 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3018 3019 ifp->if_timer = 0; 3020 3021 if (sc->tx_timer > 0) { 3022 if (--sc->tx_timer == 0) { 3023 device_printf(sc->sc_dev, "device timeout\n"); 3024 /* urtwn_init(ifp); XXX needs a process context! */ 3025 if_statinc(ifp, if_oerrors); 3026 return; 3027 } 3028 ifp->if_timer = 1; 3029 } 3030 ieee80211_watchdog(&sc->sc_ic); 3031 } 3032 3033 static int 3034 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3035 { 3036 struct urtwn_softc *sc = ifp->if_softc; 3037 struct ieee80211com *ic = &sc->sc_ic; 3038 int s, error = 0; 3039 3040 URTWNHIST_FUNC(); 3041 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3042 0, 0); 3043 3044 s = splnet(); 3045 3046 switch (cmd) { 3047 case SIOCSIFFLAGS: 3048 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3049 break; 3050 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3051 case IFF_UP | IFF_RUNNING: 3052 break; 3053 case IFF_UP: 3054 urtwn_init(ifp); 3055 break; 3056 case IFF_RUNNING: 3057 urtwn_stop(ifp, 1); 3058 break; 3059 case 0: 3060 break; 3061 } 3062 break; 3063 3064 case SIOCADDMULTI: 3065 case SIOCDELMULTI: 3066 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3067 /* setup multicast filter, etc */ 3068 error = 0; 3069 } 3070 break; 3071 3072 case SIOCS80211CHANNEL: 3073 /* 3074 * This allows for fast channel switching in monitor mode 3075 * (used by kismet). In IBSS mode, we must explicitly reset 3076 * the interface to generate a new beacon frame. 3077 */ 3078 error = ieee80211_ioctl(ic, cmd, data); 3079 if (error == ENETRESET && 3080 ic->ic_opmode == IEEE80211_M_MONITOR) { 3081 urtwn_set_chan(sc, ic->ic_curchan, 3082 IEEE80211_HTINFO_2NDCHAN_NONE); 3083 error = 0; 3084 } 3085 break; 3086 3087 default: 3088 error = ieee80211_ioctl(ic, cmd, data); 3089 break; 3090 } 3091 if (error == ENETRESET) { 3092 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3093 (IFF_UP | IFF_RUNNING) && 3094 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3095 urtwn_init(ifp); 3096 } 3097 error = 0; 3098 } 3099 3100 splx(s); 3101 3102 return error; 3103 } 3104 3105 static __inline int 3106 urtwn_power_on(struct urtwn_softc *sc) 3107 { 3108 3109 return sc->sc_power_on(sc); 3110 } 3111 3112 static int 3113 urtwn_r92c_power_on(struct urtwn_softc *sc) 3114 { 3115 uint32_t reg; 3116 int ntries; 3117 3118 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3119 3120 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3121 3122 /* Wait for autoload done bit. */ 3123 for (ntries = 0; ntries < 1000; ntries++) { 3124 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3125 break; 3126 DELAY(5); 3127 } 3128 if (ntries == 1000) { 3129 aprint_error_dev(sc->sc_dev, 3130 "timeout waiting for chip autoload\n"); 3131 return ETIMEDOUT; 3132 } 3133 3134 /* Unlock ISO/CLK/Power control register. */ 3135 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3136 DELAY(5); 3137 /* Move SPS into PWM mode. */ 3138 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3139 DELAY(5); 3140 3141 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3142 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3143 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3144 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3145 DELAY(100); 3146 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3147 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3148 ~R92C_SYS_ISO_CTRL_MD2PP); 3149 } 3150 3151 /* Auto enable WLAN. */ 3152 urtwn_write_2(sc, R92C_APS_FSMCO, 3153 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3154 for (ntries = 0; ntries < 1000; ntries++) { 3155 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3156 R92C_APS_FSMCO_APFM_ONMAC)) 3157 break; 3158 DELAY(100); 3159 } 3160 if (ntries == 1000) { 3161 aprint_error_dev(sc->sc_dev, 3162 "timeout waiting for MAC auto ON\n"); 3163 return ETIMEDOUT; 3164 } 3165 3166 /* Enable radio, GPIO and LED functions. */ 3167 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3168 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3169 urtwn_write_2(sc, R92C_APS_FSMCO, 3170 R92C_APS_FSMCO_AFSM_HSUS | 3171 R92C_APS_FSMCO_PDN_EN | 3172 R92C_APS_FSMCO_PFM_ALDN); 3173 3174 /* Release RF digital isolation. */ 3175 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3176 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3177 3178 /* Initialize MAC. */ 3179 urtwn_write_1(sc, R92C_APSD_CTRL, 3180 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3181 for (ntries = 0; ntries < 200; ntries++) { 3182 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3183 R92C_APSD_CTRL_OFF_STATUS)) 3184 break; 3185 DELAY(5); 3186 } 3187 if (ntries == 200) { 3188 aprint_error_dev(sc->sc_dev, 3189 "timeout waiting for MAC initialization\n"); 3190 return ETIMEDOUT; 3191 } 3192 3193 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3194 reg = urtwn_read_2(sc, R92C_CR); 3195 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3196 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3197 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3198 R92C_CR_ENSEC; 3199 urtwn_write_2(sc, R92C_CR, reg); 3200 3201 urtwn_write_1(sc, 0xfe10, 0x19); 3202 3203 urtwn_delay_ms(sc, 1); 3204 3205 return 0; 3206 } 3207 3208 static int 3209 urtwn_r92e_power_on(struct urtwn_softc *sc) 3210 { 3211 uint32_t reg; 3212 uint32_t val; 3213 int ntries; 3214 3215 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3216 3217 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3218 3219 /* Enable radio, GPIO and LED functions. */ 3220 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3221 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3222 urtwn_write_2(sc, R92C_APS_FSMCO, 3223 R92C_APS_FSMCO_AFSM_HSUS | 3224 R92C_APS_FSMCO_PDN_EN | 3225 R92C_APS_FSMCO_PFM_ALDN); 3226 3227 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3228 /* LDO. */ 3229 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3230 } 3231 else { 3232 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3233 R92C_SYS_SWR_CTRL2) & 0xffff); 3234 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3235 } 3236 3237 for (ntries = 0; ntries < 2; ntries++) { 3238 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3239 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3240 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3241 R92C_AFE_CTRL4)); 3242 } 3243 3244 /* Reset BB. */ 3245 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3246 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3247 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3248 3249 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3250 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3251 3252 /* Disable HWPDN. */ 3253 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3254 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3255 3256 /* Disable WL suspend. */ 3257 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3258 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3259 R92C_APS_FSMCO_AFSM_HSUS)); 3260 3261 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3262 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3263 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3264 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3265 for (ntries = 0; ntries < 10000; ntries++) { 3266 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3267 R92C_APS_FSMCO_APFM_ONMAC; 3268 if (val == 0x0) 3269 break; 3270 DELAY(10); 3271 } 3272 if (ntries == 10000) { 3273 aprint_error_dev(sc->sc_dev, 3274 "timeout waiting for chip power up\n"); 3275 return ETIMEDOUT; 3276 } 3277 3278 urtwn_write_2(sc, R92C_CR, 0x00); 3279 reg = urtwn_read_2(sc, R92C_CR); 3280 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3281 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3282 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3283 urtwn_write_2(sc, R92C_CR, reg); 3284 3285 return 0; 3286 } 3287 3288 static int 3289 urtwn_r88e_power_on(struct urtwn_softc *sc) 3290 { 3291 uint32_t reg; 3292 uint8_t val; 3293 int ntries; 3294 3295 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3296 3297 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3298 3299 /* Wait for power ready bit. */ 3300 for (ntries = 0; ntries < 5000; ntries++) { 3301 val = urtwn_read_1(sc, 0x6) & 0x2; 3302 if (val == 0x2) 3303 break; 3304 DELAY(10); 3305 } 3306 if (ntries == 5000) { 3307 aprint_error_dev(sc->sc_dev, 3308 "timeout waiting for chip power up\n"); 3309 return ETIMEDOUT; 3310 } 3311 3312 /* Reset BB. */ 3313 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3314 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3315 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3316 3317 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3318 3319 /* Disable HWPDN. */ 3320 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3321 3322 /* Disable WL suspend. */ 3323 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3324 3325 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3326 for (ntries = 0; ntries < 5000; ntries++) { 3327 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3328 break; 3329 DELAY(10); 3330 } 3331 if (ntries == 5000) 3332 return ETIMEDOUT; 3333 3334 /* Enable LDO normal mode. */ 3335 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3336 3337 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3338 urtwn_write_2(sc, R92C_CR, 0); 3339 reg = urtwn_read_2(sc, R92C_CR); 3340 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3341 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3342 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3343 urtwn_write_2(sc, R92C_CR, reg); 3344 3345 return 0; 3346 } 3347 3348 static int __noinline 3349 urtwn_llt_init(struct urtwn_softc *sc) 3350 { 3351 size_t i, page_count, pktbuf_count; 3352 uint32_t val; 3353 int error; 3354 3355 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3356 3357 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3358 3359 if (sc->chip & URTWN_CHIP_88E) 3360 page_count = R88E_TX_PAGE_COUNT; 3361 else if (sc->chip & URTWN_CHIP_92EU) 3362 page_count = R92E_TX_PAGE_COUNT; 3363 else 3364 page_count = R92C_TX_PAGE_COUNT; 3365 if (sc->chip & URTWN_CHIP_88E) 3366 pktbuf_count = R88E_TXPKTBUF_COUNT; 3367 else if (sc->chip & URTWN_CHIP_92EU) 3368 pktbuf_count = R92E_TXPKTBUF_COUNT; 3369 else 3370 pktbuf_count = R92C_TXPKTBUF_COUNT; 3371 3372 if (sc->chip & URTWN_CHIP_92EU) { 3373 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3374 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3375 DELAY(100); 3376 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3377 if (val & R92E_AUTO_LLT_EN) 3378 return EIO; 3379 return 0; 3380 } 3381 3382 /* Reserve pages [0; page_count]. */ 3383 for (i = 0; i < page_count; i++) { 3384 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3385 return error; 3386 } 3387 /* NB: 0xff indicates end-of-list. */ 3388 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3389 return error; 3390 /* 3391 * Use pages [page_count + 1; pktbuf_count - 1] 3392 * as ring buffer. 3393 */ 3394 for (++i; i < pktbuf_count - 1; i++) { 3395 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3396 return error; 3397 } 3398 /* Make the last page point to the beginning of the ring buffer. */ 3399 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3400 return error; 3401 } 3402 3403 static void 3404 urtwn_fw_reset(struct urtwn_softc *sc) 3405 { 3406 uint16_t reg; 3407 int ntries; 3408 3409 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3410 3411 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3412 3413 /* Tell 8051 to reset itself. */ 3414 mutex_enter(&sc->sc_fwcmd_mtx); 3415 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3416 sc->fwcur = 0; 3417 mutex_exit(&sc->sc_fwcmd_mtx); 3418 3419 /* Wait until 8051 resets by itself. */ 3420 for (ntries = 0; ntries < 100; ntries++) { 3421 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3422 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3423 return; 3424 DELAY(50); 3425 } 3426 /* Force 8051 reset. */ 3427 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3428 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3429 } 3430 3431 static void 3432 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3433 { 3434 uint16_t reg; 3435 3436 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3437 3438 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3439 3440 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3441 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3442 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3443 } 3444 DELAY(50); 3445 3446 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3447 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3448 DELAY(50); 3449 3450 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3451 DELAY(50); 3452 3453 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3454 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3455 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3456 } 3457 DELAY(50); 3458 3459 mutex_enter(&sc->sc_fwcmd_mtx); 3460 /* Init firmware commands ring. */ 3461 sc->fwcur = 0; 3462 mutex_exit(&sc->sc_fwcmd_mtx); 3463 3464 } 3465 3466 static int 3467 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3468 { 3469 uint32_t reg; 3470 int off, mlen, error = 0; 3471 3472 URTWNHIST_FUNC(); 3473 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3474 page, (uintptr_t)buf, len, 0); 3475 3476 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3477 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3478 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3479 3480 off = R92C_FW_START_ADDR; 3481 while (len > 0) { 3482 if (len > 196) 3483 mlen = 196; 3484 else if (len > 4) 3485 mlen = 4; 3486 else 3487 mlen = 1; 3488 error = urtwn_write_region(sc, off, buf, mlen); 3489 if (error != 0) 3490 break; 3491 off += mlen; 3492 buf += mlen; 3493 len -= mlen; 3494 } 3495 return error; 3496 } 3497 3498 static int __noinline 3499 urtwn_load_firmware(struct urtwn_softc *sc) 3500 { 3501 firmware_handle_t fwh; 3502 const struct r92c_fw_hdr *hdr; 3503 const char *name; 3504 u_char *fw, *ptr; 3505 size_t len; 3506 uint32_t reg; 3507 int mlen, ntries, page, error; 3508 3509 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3510 3511 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3512 3513 /* Read firmware image from the filesystem. */ 3514 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3515 name = "rtl8188eufw.bin"; 3516 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3517 name = "rtl8192eefw.bin"; 3518 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3519 URTWN_CHIP_UMC_A_CUT) 3520 name = "rtl8192cfwU.bin"; 3521 else 3522 name = "rtl8192cfw.bin"; 3523 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3524 aprint_error_dev(sc->sc_dev, 3525 "failed load firmware of file %s (error %d)\n", name, 3526 error); 3527 return error; 3528 } 3529 const size_t fwlen = len = firmware_get_size(fwh); 3530 fw = firmware_malloc(len); 3531 if (fw == NULL) { 3532 aprint_error_dev(sc->sc_dev, 3533 "failed to allocate firmware memory\n"); 3534 firmware_close(fwh); 3535 return ENOMEM; 3536 } 3537 error = firmware_read(fwh, 0, fw, len); 3538 firmware_close(fwh); 3539 if (error != 0) { 3540 aprint_error_dev(sc->sc_dev, 3541 "failed to read firmware (error %d)\n", error); 3542 firmware_free(fw, fwlen); 3543 return error; 3544 } 3545 3546 len = fwlen; 3547 ptr = fw; 3548 hdr = (const struct r92c_fw_hdr *)ptr; 3549 /* Check if there is a valid FW header and skip it. */ 3550 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3551 (le16toh(hdr->signature) >> 4) == 0x88e || 3552 (le16toh(hdr->signature) >> 4) == 0x92e || 3553 (le16toh(hdr->signature) >> 4) == 0x92c) { 3554 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3555 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3556 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3557 hdr->month, hdr->date, hdr->hour, hdr->minute); 3558 ptr += sizeof(*hdr); 3559 len -= sizeof(*hdr); 3560 } 3561 3562 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3563 /* Reset MCU ready status */ 3564 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3565 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3566 ISSET(sc->chip, URTWN_CHIP_92EU)) 3567 urtwn_r88e_fw_reset(sc); 3568 else 3569 urtwn_fw_reset(sc); 3570 } 3571 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3572 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3573 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3574 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3575 R92C_SYS_FUNC_EN_CPUEN); 3576 } 3577 3578 /* download enabled */ 3579 urtwn_write_1(sc, R92C_MCUFWDL, 3580 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3581 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3582 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3583 3584 /* Reset the FWDL checksum. */ 3585 urtwn_write_1(sc, R92C_MCUFWDL, 3586 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3587 3588 DELAY(50); 3589 /* download firmware */ 3590 for (page = 0; len > 0; page++) { 3591 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3592 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3593 if (error != 0) { 3594 aprint_error_dev(sc->sc_dev, 3595 "could not load firmware page %d\n", page); 3596 goto fail; 3597 } 3598 ptr += mlen; 3599 len -= mlen; 3600 } 3601 3602 /* download disable */ 3603 urtwn_write_1(sc, R92C_MCUFWDL, 3604 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3605 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3606 3607 /* Wait for checksum report. */ 3608 for (ntries = 0; ntries < 1000; ntries++) { 3609 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3610 break; 3611 DELAY(5); 3612 } 3613 if (ntries == 1000) { 3614 aprint_error_dev(sc->sc_dev, 3615 "timeout waiting for checksum report\n"); 3616 error = ETIMEDOUT; 3617 goto fail; 3618 } 3619 3620 /* Wait for firmware readiness. */ 3621 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3622 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3623 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3624 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3625 ISSET(sc->chip, URTWN_CHIP_92EU)) 3626 urtwn_r88e_fw_reset(sc); 3627 for (ntries = 0; ntries < 6000; ntries++) { 3628 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3629 break; 3630 DELAY(5); 3631 } 3632 if (ntries == 6000) { 3633 aprint_error_dev(sc->sc_dev, 3634 "timeout waiting for firmware readiness\n"); 3635 error = ETIMEDOUT; 3636 goto fail; 3637 } 3638 fail: 3639 firmware_free(fw, fwlen); 3640 return error; 3641 } 3642 3643 static __inline int 3644 urtwn_dma_init(struct urtwn_softc *sc) 3645 { 3646 3647 return sc->sc_dma_init(sc); 3648 } 3649 3650 static int 3651 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3652 { 3653 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3654 uint32_t reg; 3655 int error; 3656 3657 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3658 3659 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3660 3661 /* Initialize LLT table. */ 3662 error = urtwn_llt_init(sc); 3663 if (error != 0) 3664 return error; 3665 3666 /* Get Tx queues to USB endpoints mapping. */ 3667 hashq = hasnq = haslq = 0; 3668 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3669 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3670 if (MS(reg, R92C_USB_EP_HQ) != 0) 3671 hashq = 1; 3672 if (MS(reg, R92C_USB_EP_NQ) != 0) 3673 hasnq = 1; 3674 if (MS(reg, R92C_USB_EP_LQ) != 0) 3675 haslq = 1; 3676 nqueues = hashq + hasnq + haslq; 3677 if (nqueues == 0) 3678 return EIO; 3679 /* Get the number of pages for each queue. */ 3680 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3681 /* The remaining pages are assigned to the high priority queue. */ 3682 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3683 3684 /* Set number of pages for normal priority queue. */ 3685 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3686 urtwn_write_4(sc, R92C_RQPN, 3687 /* Set number of pages for public queue. */ 3688 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3689 /* Set number of pages for high priority queue. */ 3690 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3691 /* Set number of pages for low priority queue. */ 3692 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3693 /* Load values. */ 3694 R92C_RQPN_LD); 3695 3696 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3697 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3698 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3699 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3700 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3701 3702 /* Set queue to USB pipe mapping. */ 3703 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3704 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3705 if (nqueues == 1) { 3706 if (hashq) { 3707 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3708 } else if (hasnq) { 3709 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3710 } else { 3711 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3712 } 3713 } else if (nqueues == 2) { 3714 /* All 2-endpoints configs have a high priority queue. */ 3715 if (!hashq) { 3716 return EIO; 3717 } 3718 if (hasnq) { 3719 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3720 } else { 3721 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3722 } 3723 } else { 3724 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3725 } 3726 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3727 3728 /* Set Tx/Rx transfer page boundary. */ 3729 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3730 3731 /* Set Tx/Rx transfer page size. */ 3732 urtwn_write_1(sc, R92C_PBP, 3733 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3734 return 0; 3735 } 3736 3737 static int 3738 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3739 { 3740 usb_interface_descriptor_t *id; 3741 uint32_t reg; 3742 int nqueues; 3743 int error; 3744 3745 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3746 3747 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3748 3749 /* Initialize LLT table. */ 3750 error = urtwn_llt_init(sc); 3751 if (error != 0) 3752 return error; 3753 3754 /* Get Tx queues to USB endpoints mapping. */ 3755 id = usbd_get_interface_descriptor(sc->sc_iface); 3756 nqueues = id->bNumEndpoints - 1; 3757 if (nqueues == 0) 3758 return EIO; 3759 3760 /* Set number of pages for normal priority queue. */ 3761 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3762 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3763 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3764 3765 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3766 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3767 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3768 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3769 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3770 3771 /* Set queue to USB pipe mapping. */ 3772 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3773 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3774 if (nqueues == 1) 3775 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3776 else if (nqueues == 2) 3777 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3778 else 3779 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3780 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3781 3782 /* Set Tx/Rx transfer page boundary. */ 3783 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3784 3785 /* Set Tx/Rx transfer page size. */ 3786 urtwn_write_1(sc, R92C_PBP, 3787 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3788 3789 return 0; 3790 } 3791 3792 static void __noinline 3793 urtwn_mac_init(struct urtwn_softc *sc) 3794 { 3795 size_t i; 3796 3797 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3798 3799 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3800 3801 /* Write MAC initialization values. */ 3802 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3803 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3804 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3805 rtl8188eu_mac[i].val); 3806 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3807 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3808 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3809 rtl8192eu_mac[i].val); 3810 } else { 3811 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3812 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3813 rtl8192cu_mac[i].val); 3814 } 3815 } 3816 3817 static void __noinline 3818 urtwn_bb_init(struct urtwn_softc *sc) 3819 { 3820 const struct rtwn_bb_prog *prog; 3821 uint32_t reg; 3822 uint8_t crystalcap; 3823 size_t i; 3824 3825 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3826 3827 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3828 3829 /* Enable BB and RF. */ 3830 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3831 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3832 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3833 R92C_SYS_FUNC_EN_DIO_RF); 3834 3835 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3836 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3837 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3838 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3839 } 3840 3841 urtwn_write_1(sc, R92C_RF_CTRL, 3842 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3843 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3844 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3845 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3846 3847 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3848 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3849 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3850 urtwn_write_1(sc, 0x15, 0xe9); 3851 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3852 } 3853 3854 /* Select BB programming based on board type. */ 3855 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3856 prog = &rtl8188eu_bb_prog; 3857 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3858 prog = &rtl8192eu_bb_prog; 3859 else if (!(sc->chip & URTWN_CHIP_92C)) { 3860 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3861 prog = &rtl8188ce_bb_prog; 3862 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3863 prog = &rtl8188ru_bb_prog; 3864 } else { 3865 prog = &rtl8188cu_bb_prog; 3866 } 3867 } else { 3868 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3869 prog = &rtl8192ce_bb_prog; 3870 } else { 3871 prog = &rtl8192cu_bb_prog; 3872 } 3873 } 3874 /* Write BB initialization values. */ 3875 for (i = 0; i < prog->count; i++) { 3876 /* additional delay depend on registers */ 3877 switch (prog->regs[i]) { 3878 case 0xfe: 3879 urtwn_delay_ms(sc, 50); 3880 break; 3881 case 0xfd: 3882 urtwn_delay_ms(sc, 5); 3883 break; 3884 case 0xfc: 3885 urtwn_delay_ms(sc, 1); 3886 break; 3887 case 0xfb: 3888 DELAY(50); 3889 break; 3890 case 0xfa: 3891 DELAY(5); 3892 break; 3893 case 0xf9: 3894 DELAY(1); 3895 break; 3896 } 3897 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3898 DELAY(1); 3899 } 3900 3901 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3902 /* 8192C 1T only configuration. */ 3903 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3904 reg = (reg & ~0x00000003) | 0x2; 3905 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3906 3907 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3908 reg = (reg & ~0x00300033) | 0x00200022; 3909 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3910 3911 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3912 reg = (reg & ~0xff000000) | (0x45 << 24); 3913 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3914 3915 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3916 reg = (reg & ~0x000000ff) | 0x23; 3917 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3918 3919 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3920 reg = (reg & ~0x00000030) | (1 << 4); 3921 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3922 3923 reg = urtwn_bb_read(sc, 0xe74); 3924 reg = (reg & ~0x0c000000) | (2 << 26); 3925 urtwn_bb_write(sc, 0xe74, reg); 3926 reg = urtwn_bb_read(sc, 0xe78); 3927 reg = (reg & ~0x0c000000) | (2 << 26); 3928 urtwn_bb_write(sc, 0xe78, reg); 3929 reg = urtwn_bb_read(sc, 0xe7c); 3930 reg = (reg & ~0x0c000000) | (2 << 26); 3931 urtwn_bb_write(sc, 0xe7c, reg); 3932 reg = urtwn_bb_read(sc, 0xe80); 3933 reg = (reg & ~0x0c000000) | (2 << 26); 3934 urtwn_bb_write(sc, 0xe80, reg); 3935 reg = urtwn_bb_read(sc, 0xe88); 3936 reg = (reg & ~0x0c000000) | (2 << 26); 3937 urtwn_bb_write(sc, 0xe88, reg); 3938 } 3939 3940 /* Write AGC values. */ 3941 for (i = 0; i < prog->agccount; i++) { 3942 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3943 DELAY(1); 3944 } 3945 3946 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3947 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3948 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3949 DELAY(1); 3950 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3951 DELAY(1); 3952 } 3953 3954 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3955 crystalcap = sc->r88e_rom[0xb9]; 3956 if (crystalcap == 0x00) 3957 crystalcap = 0x20; 3958 crystalcap &= 0x3f; 3959 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3960 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3961 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3962 crystalcap | crystalcap << 6)); 3963 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3964 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3965 crystalcap = sc->r88e_rom[0xb9]; 3966 if (crystalcap == 0xff) 3967 crystalcap = 0x20; 3968 crystalcap &= 0x3f; 3969 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3970 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3971 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3972 crystalcap | crystalcap << 6)); 3973 } else { 3974 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3975 R92C_HSSI_PARAM2_CCK_HIPWR) { 3976 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3977 } 3978 } 3979 } 3980 3981 static void __noinline 3982 urtwn_rf_init(struct urtwn_softc *sc) 3983 { 3984 const struct rtwn_rf_prog *prog; 3985 uint32_t reg, mask, saved; 3986 size_t i, j, idx; 3987 3988 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3989 3990 /* Select RF programming based on board type. */ 3991 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3992 prog = rtl8188eu_rf_prog; 3993 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3994 prog = rtl8192eu_rf_prog; 3995 else if (!(sc->chip & URTWN_CHIP_92C)) { 3996 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3997 prog = rtl8188ce_rf_prog; 3998 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3999 prog = rtl8188ru_rf_prog; 4000 } else { 4001 prog = rtl8188cu_rf_prog; 4002 } 4003 } else { 4004 prog = rtl8192ce_rf_prog; 4005 } 4006 4007 for (i = 0; i < sc->nrxchains; i++) { 4008 /* Save RF_ENV control type. */ 4009 idx = i / 2; 4010 mask = 0xffffU << ((i % 2) * 16); 4011 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4012 4013 /* Set RF_ENV enable. */ 4014 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4015 reg |= 0x100000; 4016 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4017 DELAY(50); 4018 4019 /* Set RF_ENV output high. */ 4020 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4021 reg |= 0x10; 4022 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4023 DELAY(50); 4024 4025 /* Set address and data lengths of RF registers. */ 4026 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4027 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4028 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4029 DELAY(50); 4030 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4031 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4032 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4033 DELAY(50); 4034 4035 /* Write RF initialization values for this chain. */ 4036 for (j = 0; j < prog[i].count; j++) { 4037 if (prog[i].regs[j] >= 0xf9 && 4038 prog[i].regs[j] <= 0xfe) { 4039 /* 4040 * These are fake RF registers offsets that 4041 * indicate a delay is required. 4042 */ 4043 urtwn_delay_ms(sc, 50); 4044 continue; 4045 } 4046 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4047 DELAY(5); 4048 } 4049 4050 /* Restore RF_ENV control type. */ 4051 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4052 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4053 } 4054 4055 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4056 URTWN_CHIP_UMC_A_CUT) { 4057 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4058 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4059 } 4060 4061 /* Cache RF register CHNLBW. */ 4062 for (i = 0; i < 2; i++) { 4063 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4064 } 4065 } 4066 4067 static void __noinline 4068 urtwn_cam_init(struct urtwn_softc *sc) 4069 { 4070 uint32_t content, command; 4071 uint8_t idx; 4072 size_t i; 4073 4074 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4075 4076 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4077 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4078 return; 4079 4080 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4081 content = (idx & 3) 4082 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4083 | R92C_CAM_VALID; 4084 4085 command = R92C_CAMCMD_POLLING 4086 | R92C_CAMCMD_WRITE 4087 | R92C_CAM_CTL0(idx); 4088 4089 urtwn_write_4(sc, R92C_CAMWRITE, content); 4090 urtwn_write_4(sc, R92C_CAMCMD, command); 4091 } 4092 4093 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4094 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4095 if (i == 0) { 4096 content = (idx & 3) 4097 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4098 | R92C_CAM_VALID; 4099 } else { 4100 content = 0; 4101 } 4102 4103 command = R92C_CAMCMD_POLLING 4104 | R92C_CAMCMD_WRITE 4105 | R92C_CAM_CTL0(idx) 4106 | i; 4107 4108 urtwn_write_4(sc, R92C_CAMWRITE, content); 4109 urtwn_write_4(sc, R92C_CAMCMD, command); 4110 } 4111 } 4112 4113 /* Invalidate all CAM entries. */ 4114 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4115 } 4116 4117 static void __noinline 4118 urtwn_pa_bias_init(struct urtwn_softc *sc) 4119 { 4120 uint8_t reg; 4121 size_t i; 4122 4123 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4124 4125 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4126 4127 for (i = 0; i < sc->nrxchains; i++) { 4128 if (sc->pa_setting & (1U << i)) 4129 continue; 4130 4131 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4132 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4133 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4134 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4135 } 4136 if (!(sc->pa_setting & 0x10)) { 4137 reg = urtwn_read_1(sc, 0x16); 4138 reg = (reg & ~0xf0) | 0x90; 4139 urtwn_write_1(sc, 0x16, reg); 4140 } 4141 } 4142 4143 static void __noinline 4144 urtwn_rxfilter_init(struct urtwn_softc *sc) 4145 { 4146 4147 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4148 4149 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4150 4151 /* Initialize Rx filter. */ 4152 /* TODO: use better filter for monitor mode. */ 4153 urtwn_write_4(sc, R92C_RCR, 4154 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4155 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4156 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4157 /* Accept all multicast frames. */ 4158 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4159 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4160 /* Accept all management frames. */ 4161 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4162 /* Reject all control frames. */ 4163 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4164 /* Accept all data frames. */ 4165 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4166 } 4167 4168 static void __noinline 4169 urtwn_edca_init(struct urtwn_softc *sc) 4170 { 4171 4172 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4173 4174 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4175 4176 /* set spec SIFS (used in NAV) */ 4177 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4178 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4179 4180 /* set SIFS CCK/OFDM */ 4181 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4182 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4183 4184 /* TXOP */ 4185 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4186 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4187 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4188 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4189 } 4190 4191 static void 4192 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4193 uint16_t power[URTWN_RIDX_COUNT]) 4194 { 4195 uint32_t reg; 4196 4197 URTWNHIST_FUNC(); 4198 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4199 4200 /* Write per-CCK rate Tx power. */ 4201 if (chain == 0) { 4202 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4203 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4204 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4205 4206 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4207 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4208 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4209 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4210 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4211 } else { 4212 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4213 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4214 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4215 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4216 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4217 4218 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4219 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4220 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4221 } 4222 /* Write per-OFDM rate Tx power. */ 4223 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4224 SM(R92C_TXAGC_RATE06, power[ 4]) | 4225 SM(R92C_TXAGC_RATE09, power[ 5]) | 4226 SM(R92C_TXAGC_RATE12, power[ 6]) | 4227 SM(R92C_TXAGC_RATE18, power[ 7])); 4228 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4229 SM(R92C_TXAGC_RATE24, power[ 8]) | 4230 SM(R92C_TXAGC_RATE36, power[ 9]) | 4231 SM(R92C_TXAGC_RATE48, power[10]) | 4232 SM(R92C_TXAGC_RATE54, power[11])); 4233 /* Write per-MCS Tx power. */ 4234 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4235 SM(R92C_TXAGC_MCS00, power[12]) | 4236 SM(R92C_TXAGC_MCS01, power[13]) | 4237 SM(R92C_TXAGC_MCS02, power[14]) | 4238 SM(R92C_TXAGC_MCS03, power[15])); 4239 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4240 SM(R92C_TXAGC_MCS04, power[16]) | 4241 SM(R92C_TXAGC_MCS05, power[17]) | 4242 SM(R92C_TXAGC_MCS06, power[18]) | 4243 SM(R92C_TXAGC_MCS07, power[19])); 4244 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4245 SM(R92C_TXAGC_MCS08, power[20]) | 4246 SM(R92C_TXAGC_MCS09, power[21]) | 4247 SM(R92C_TXAGC_MCS10, power[22]) | 4248 SM(R92C_TXAGC_MCS11, power[23])); 4249 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4250 SM(R92C_TXAGC_MCS12, power[24]) | 4251 SM(R92C_TXAGC_MCS13, power[25]) | 4252 SM(R92C_TXAGC_MCS14, power[26]) | 4253 SM(R92C_TXAGC_MCS15, power[27])); 4254 } 4255 4256 static void 4257 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4258 uint16_t power[URTWN_RIDX_COUNT]) 4259 { 4260 struct r92c_rom *rom = &sc->rom; 4261 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4262 const struct rtwn_txpwr *base; 4263 int ridx, group; 4264 4265 URTWNHIST_FUNC(); 4266 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4267 4268 /* Determine channel group. */ 4269 if (chan <= 3) { 4270 group = 0; 4271 } else if (chan <= 9) { 4272 group = 1; 4273 } else { 4274 group = 2; 4275 } 4276 4277 /* Get original Tx power based on board type and RF chain. */ 4278 if (!(sc->chip & URTWN_CHIP_92C)) { 4279 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4280 base = &rtl8188ru_txagc[chain]; 4281 } else { 4282 base = &rtl8192cu_txagc[chain]; 4283 } 4284 } else { 4285 base = &rtl8192cu_txagc[chain]; 4286 } 4287 4288 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4289 if (sc->regulatory == 0) { 4290 for (ridx = 0; ridx <= 3; ridx++) { 4291 power[ridx] = base->pwr[0][ridx]; 4292 } 4293 } 4294 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4295 if (sc->regulatory == 3) { 4296 power[ridx] = base->pwr[0][ridx]; 4297 /* Apply vendor limits. */ 4298 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4299 maxpow = rom->ht40_max_pwr[group]; 4300 } else { 4301 maxpow = rom->ht20_max_pwr[group]; 4302 } 4303 maxpow = (maxpow >> (chain * 4)) & 0xf; 4304 if (power[ridx] > maxpow) { 4305 power[ridx] = maxpow; 4306 } 4307 } else if (sc->regulatory == 1) { 4308 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4309 power[ridx] = base->pwr[group][ridx]; 4310 } 4311 } else if (sc->regulatory != 2) { 4312 power[ridx] = base->pwr[0][ridx]; 4313 } 4314 } 4315 4316 /* Compute per-CCK rate Tx power. */ 4317 cckpow = rom->cck_tx_pwr[chain][group]; 4318 for (ridx = 0; ridx <= 3; ridx++) { 4319 power[ridx] += cckpow; 4320 if (power[ridx] > R92C_MAX_TX_PWR) { 4321 power[ridx] = R92C_MAX_TX_PWR; 4322 } 4323 } 4324 4325 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4326 if (sc->ntxchains > 1) { 4327 /* Apply reduction for 2 spatial streams. */ 4328 diff = rom->ht40_2s_tx_pwr_diff[group]; 4329 diff = (diff >> (chain * 4)) & 0xf; 4330 htpow = (htpow > diff) ? htpow - diff : 0; 4331 } 4332 4333 /* Compute per-OFDM rate Tx power. */ 4334 diff = rom->ofdm_tx_pwr_diff[group]; 4335 diff = (diff >> (chain * 4)) & 0xf; 4336 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4337 for (ridx = 4; ridx <= 11; ridx++) { 4338 power[ridx] += ofdmpow; 4339 if (power[ridx] > R92C_MAX_TX_PWR) { 4340 power[ridx] = R92C_MAX_TX_PWR; 4341 } 4342 } 4343 4344 /* Compute per-MCS Tx power. */ 4345 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4346 diff = rom->ht20_tx_pwr_diff[group]; 4347 diff = (diff >> (chain * 4)) & 0xf; 4348 htpow += diff; /* HT40->HT20 correction. */ 4349 } 4350 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4351 power[ridx] += htpow; 4352 if (power[ridx] > R92C_MAX_TX_PWR) { 4353 power[ridx] = R92C_MAX_TX_PWR; 4354 } 4355 } 4356 #ifdef URTWN_DEBUG 4357 if (urtwn_debug & DBG_RF) { 4358 /* Dump per-rate Tx power values. */ 4359 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4360 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4361 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4362 } 4363 #endif 4364 } 4365 4366 void 4367 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4368 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4369 { 4370 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4371 const struct rtwn_r88e_txpwr *base; 4372 int ridx, group; 4373 4374 URTWNHIST_FUNC(); 4375 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4376 4377 /* Determine channel group. */ 4378 if (chan <= 2) 4379 group = 0; 4380 else if (chan <= 5) 4381 group = 1; 4382 else if (chan <= 8) 4383 group = 2; 4384 else if (chan <= 11) 4385 group = 3; 4386 else if (chan <= 13) 4387 group = 4; 4388 else 4389 group = 5; 4390 4391 /* Get original Tx power based on board type and RF chain. */ 4392 base = &rtl8188eu_txagc[chain]; 4393 4394 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4395 if (sc->regulatory == 0) { 4396 for (ridx = 0; ridx <= 3; ridx++) 4397 power[ridx] = base->pwr[0][ridx]; 4398 } 4399 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4400 if (sc->regulatory == 3) 4401 power[ridx] = base->pwr[0][ridx]; 4402 else if (sc->regulatory == 1) { 4403 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4404 power[ridx] = base->pwr[group][ridx]; 4405 } else if (sc->regulatory != 2) 4406 power[ridx] = base->pwr[0][ridx]; 4407 } 4408 4409 /* Compute per-CCK rate Tx power. */ 4410 cckpow = sc->cck_tx_pwr[group]; 4411 for (ridx = 0; ridx <= 3; ridx++) { 4412 power[ridx] += cckpow; 4413 if (power[ridx] > R92C_MAX_TX_PWR) 4414 power[ridx] = R92C_MAX_TX_PWR; 4415 } 4416 4417 htpow = sc->ht40_tx_pwr[group]; 4418 4419 /* Compute per-OFDM rate Tx power. */ 4420 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4421 for (ridx = 4; ridx <= 11; ridx++) { 4422 power[ridx] += ofdmpow; 4423 if (power[ridx] > R92C_MAX_TX_PWR) 4424 power[ridx] = R92C_MAX_TX_PWR; 4425 } 4426 4427 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4428 for (ridx = 12; ridx <= 27; ridx++) { 4429 power[ridx] += bw20pow; 4430 if (power[ridx] > R92C_MAX_TX_PWR) 4431 power[ridx] = R92C_MAX_TX_PWR; 4432 } 4433 } 4434 4435 static void 4436 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4437 { 4438 uint16_t power[URTWN_RIDX_COUNT]; 4439 size_t i; 4440 4441 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4442 4443 for (i = 0; i < sc->ntxchains; i++) { 4444 /* Compute per-rate Tx power values. */ 4445 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4446 ISSET(sc->chip, URTWN_CHIP_92EU)) 4447 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4448 else 4449 urtwn_get_txpower(sc, i, chan, ht40m, power); 4450 /* Write per-rate Tx power values to hardware. */ 4451 urtwn_write_txpower(sc, i, power); 4452 } 4453 } 4454 4455 static void __noinline 4456 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4457 { 4458 struct ieee80211com *ic = &sc->sc_ic; 4459 u_int chan; 4460 size_t i; 4461 4462 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4463 4464 URTWNHIST_FUNC(); 4465 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4466 4467 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4468 4469 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4470 chan += 2; 4471 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4472 chan -= 2; 4473 } 4474 4475 /* Set Tx power for this new channel. */ 4476 urtwn_set_txpower(sc, chan, ht40m); 4477 4478 for (i = 0; i < sc->nrxchains; i++) { 4479 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4480 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4481 } 4482 4483 if (ht40m) { 4484 /* Is secondary channel below or above primary? */ 4485 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4486 uint32_t reg; 4487 4488 urtwn_write_1(sc, R92C_BWOPMODE, 4489 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4490 4491 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4492 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4493 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4494 4495 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4496 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4497 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4498 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4499 4500 /* Set CCK side band. */ 4501 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4502 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4503 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4504 4505 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4506 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4507 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4508 4509 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4510 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4511 ~R92C_FPGA0_ANAPARAM2_CBW20); 4512 4513 reg = urtwn_bb_read(sc, 0x818); 4514 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4515 urtwn_bb_write(sc, 0x818, reg); 4516 4517 /* Select 40MHz bandwidth. */ 4518 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4519 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4520 } else { 4521 urtwn_write_1(sc, R92C_BWOPMODE, 4522 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4523 4524 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4525 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4526 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4527 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4528 4529 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4530 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4531 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4532 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4533 R92C_FPGA0_ANAPARAM2_CBW20); 4534 } 4535 4536 /* Select 20MHz bandwidth. */ 4537 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4538 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4539 (ISSET(sc->chip, URTWN_CHIP_88E) || 4540 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4541 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4542 } 4543 } 4544 4545 static void __noinline 4546 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4547 { 4548 4549 URTWNHIST_FUNC(); 4550 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4551 4552 uint32_t addaBackup[16], iqkBackup[4], piMode; 4553 4554 #ifdef notyet 4555 uint32_t odfm0_agccore_regs[3]; 4556 uint32_t ant_regs[3]; 4557 uint32_t rf_regs[8]; 4558 #endif 4559 uint32_t reg0, reg1, reg2; 4560 int i, attempt; 4561 4562 #ifdef notyet 4563 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4564 R92E_STBC_SETTING + 2)); 4565 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4566 /* Save AGCCORE regs. */ 4567 for (i = 0; i < sc->nrxchains; i++) { 4568 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4569 R92C_OFDM0_AGCCORE1(i)); 4570 } 4571 #endif 4572 /* Save BB regs. */ 4573 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4574 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4575 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4576 4577 /* Save adda regs to be restored when finished. */ 4578 for (i = 0; i < __arraycount(addaReg); i++) 4579 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4580 /* Save mac regs. */ 4581 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4582 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4583 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4584 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4585 4586 #ifdef notyet 4587 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4588 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4589 4590 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4591 for (i = 0; i < sc->nrxchains; i++) 4592 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4593 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4594 #endif 4595 4596 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4597 R92C_HSSI_PARAM1_PI); 4598 if (piMode == 0) { 4599 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4600 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4601 R92C_HSSI_PARAM1_PI); 4602 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4603 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4604 R92C_HSSI_PARAM1_PI); 4605 } 4606 4607 attempt = 1; 4608 4609 next_attempt: 4610 4611 /* Set mac regs for calibration. */ 4612 for (i = 0; i < __arraycount(addaReg); i++) { 4613 urtwn_bb_write(sc, addaReg[i], 4614 addaReg[__arraycount(addaReg) - 1]); 4615 } 4616 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4617 R92C_CCK0_AFESETTING)); 4618 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4619 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4620 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4621 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4622 4623 if (sc->ntxchains > 1) 4624 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4625 4626 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4627 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4628 ~R92C_BCN_CTRL_EN_BCN)); 4629 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4630 ~R92C_BCN_CTRL_EN_BCN)); 4631 4632 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4633 ~R92C_GPIO_MUXCFG_ENBT)); 4634 4635 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4636 4637 if (sc->ntxchains > 1) 4638 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4639 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4640 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4641 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4642 4643 /* Restore BB regs. */ 4644 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4645 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4646 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4647 4648 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4649 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4650 if (sc->nrxchains > 1) 4651 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4652 4653 if (attempt-- > 0) 4654 goto next_attempt; 4655 4656 /* Restore mode. */ 4657 if (piMode == 0) { 4658 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4659 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4660 ~R92C_HSSI_PARAM1_PI); 4661 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4662 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4663 ~R92C_HSSI_PARAM1_PI); 4664 } 4665 4666 #ifdef notyet 4667 for (i = 0; i < sc->nrxchains; i++) { 4668 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4669 odfm0_agccore_regs[i]); 4670 } 4671 #endif 4672 4673 /* Restore adda regs. */ 4674 for (i = 0; i < __arraycount(addaReg); i++) 4675 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4676 /* Restore mac regs. */ 4677 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4678 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4679 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4680 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4681 4682 #ifdef notyet 4683 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4684 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4685 4686 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4687 for (i = 0; i < sc->nrxchains; i++) 4688 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4689 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4690 #endif 4691 } 4692 4693 static void 4694 urtwn_lc_calib(struct urtwn_softc *sc) 4695 { 4696 uint32_t rf_ac[2]; 4697 uint8_t txmode; 4698 size_t i; 4699 4700 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4701 4702 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4703 4704 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4705 if ((txmode & 0x70) != 0) { 4706 /* Disable all continuous Tx. */ 4707 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4708 4709 /* Set RF mode to standby mode. */ 4710 for (i = 0; i < sc->nrxchains; i++) { 4711 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4712 urtwn_rf_write(sc, i, R92C_RF_AC, 4713 RW(rf_ac[i], R92C_RF_AC_MODE, 4714 R92C_RF_AC_MODE_STANDBY)); 4715 } 4716 } else { 4717 /* Block all Tx queues. */ 4718 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4719 } 4720 /* Start calibration. */ 4721 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4722 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4723 4724 /* Give calibration the time to complete. */ 4725 urtwn_delay_ms(sc, 100); 4726 4727 /* Restore configuration. */ 4728 if ((txmode & 0x70) != 0) { 4729 /* Restore Tx mode. */ 4730 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4731 /* Restore RF mode. */ 4732 for (i = 0; i < sc->nrxchains; i++) { 4733 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4734 } 4735 } else { 4736 /* Unblock all Tx queues. */ 4737 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4738 } 4739 } 4740 4741 static void 4742 urtwn_temp_calib(struct urtwn_softc *sc) 4743 { 4744 int temp, t_meter_reg; 4745 4746 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4747 4748 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4749 4750 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4751 t_meter_reg = R92C_RF_T_METER; 4752 else 4753 t_meter_reg = R92E_RF_T_METER; 4754 4755 if (sc->thcal_state == 0) { 4756 /* Start measuring temperature. */ 4757 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4758 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4759 sc->thcal_state = 1; 4760 return; 4761 } 4762 sc->thcal_state = 0; 4763 4764 /* Read measured temperature. */ 4765 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4766 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4767 if (temp == 0) /* Read failed, skip. */ 4768 return; 4769 4770 /* 4771 * Redo LC calibration if temperature changed significantly since 4772 * last calibration. 4773 */ 4774 if (sc->thcal_lctemp == 0) { 4775 /* First LC calibration is performed in urtwn_init(). */ 4776 sc->thcal_lctemp = temp; 4777 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4778 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4779 sc->thcal_lctemp, temp, 0, 0); 4780 urtwn_lc_calib(sc); 4781 /* Record temperature of last LC calibration. */ 4782 sc->thcal_lctemp = temp; 4783 } 4784 } 4785 4786 static int 4787 urtwn_init(struct ifnet *ifp) 4788 { 4789 struct urtwn_softc *sc = ifp->if_softc; 4790 struct ieee80211com *ic = &sc->sc_ic; 4791 struct urtwn_rx_data *data; 4792 uint32_t reg; 4793 size_t i; 4794 int error; 4795 4796 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4797 4798 urtwn_stop(ifp, 0); 4799 4800 mutex_enter(&sc->sc_write_mtx); 4801 4802 mutex_enter(&sc->sc_task_mtx); 4803 /* Init host async commands ring. */ 4804 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4805 mutex_exit(&sc->sc_task_mtx); 4806 4807 mutex_enter(&sc->sc_fwcmd_mtx); 4808 /* Init firmware commands ring. */ 4809 sc->fwcur = 0; 4810 mutex_exit(&sc->sc_fwcmd_mtx); 4811 4812 /* Allocate Tx/Rx buffers. */ 4813 error = urtwn_alloc_rx_list(sc); 4814 if (error != 0) { 4815 aprint_error_dev(sc->sc_dev, 4816 "could not allocate Rx buffers\n"); 4817 goto fail; 4818 } 4819 error = urtwn_alloc_tx_list(sc); 4820 if (error != 0) { 4821 aprint_error_dev(sc->sc_dev, 4822 "could not allocate Tx buffers\n"); 4823 goto fail; 4824 } 4825 4826 /* Power on adapter. */ 4827 error = urtwn_power_on(sc); 4828 if (error != 0) 4829 goto fail; 4830 4831 /* Initialize DMA. */ 4832 error = urtwn_dma_init(sc); 4833 if (error != 0) 4834 goto fail; 4835 4836 /* Set info size in Rx descriptors (in 64-bit words). */ 4837 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4838 4839 /* Init interrupts. */ 4840 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4841 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4842 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4843 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4844 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4845 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4846 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4847 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4848 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4849 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4850 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4851 } 4852 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4853 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4854 } else { 4855 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4856 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4857 } 4858 4859 /* Set MAC address. */ 4860 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4861 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4862 4863 /* Set initial network type. */ 4864 reg = urtwn_read_4(sc, R92C_CR); 4865 switch (ic->ic_opmode) { 4866 case IEEE80211_M_STA: 4867 default: 4868 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4869 break; 4870 4871 case IEEE80211_M_IBSS: 4872 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4873 break; 4874 } 4875 urtwn_write_4(sc, R92C_CR, reg); 4876 4877 /* Set response rate */ 4878 reg = urtwn_read_4(sc, R92C_RRSR); 4879 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4880 urtwn_write_4(sc, R92C_RRSR, reg); 4881 4882 /* SIFS (used in NAV) */ 4883 urtwn_write_2(sc, R92C_SPEC_SIFS, 4884 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4885 4886 /* Set short/long retry limits. */ 4887 urtwn_write_2(sc, R92C_RL, 4888 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4889 4890 /* Initialize EDCA parameters. */ 4891 urtwn_edca_init(sc); 4892 4893 /* Setup rate fallback. */ 4894 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4895 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4896 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4897 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4898 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4899 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4900 } 4901 4902 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4903 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4904 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4905 /* Set ACK timeout. */ 4906 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4907 4908 /* Setup USB aggregation. */ 4909 /* Tx */ 4910 reg = urtwn_read_4(sc, R92C_TDECTRL); 4911 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4912 urtwn_write_4(sc, R92C_TDECTRL, reg); 4913 /* Rx */ 4914 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4915 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4916 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4917 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4918 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4919 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4920 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4921 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4922 ISSET(sc->chip, URTWN_CHIP_92EU)) 4923 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4924 else 4925 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4926 4927 /* Initialize beacon parameters. */ 4928 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4929 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4930 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4931 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4932 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4933 4934 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4935 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4936 /* Setup AMPDU aggregation. */ 4937 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4938 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4939 urtwn_write_2(sc, 0x4ca, 0x0708); 4940 4941 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4942 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4943 } 4944 4945 /* Load 8051 microcode. */ 4946 error = urtwn_load_firmware(sc); 4947 if (error != 0) 4948 goto fail; 4949 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4950 4951 /* Initialize MAC/BB/RF blocks. */ 4952 /* 4953 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4954 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4955 * XXX: This setting should be removed from rtl8192cu_mac[]. 4956 */ 4957 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4958 urtwn_rxfilter_init(sc); // reset R92C_RCR 4959 urtwn_bb_init(sc); 4960 urtwn_rf_init(sc); 4961 4962 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4963 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4964 urtwn_write_2(sc, R92C_CR, 4965 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4966 R92C_CR_MACRXEN); 4967 } 4968 4969 /* Turn CCK and OFDM blocks on. */ 4970 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4971 reg |= R92C_RFMOD_CCK_EN; 4972 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4973 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4974 reg |= R92C_RFMOD_OFDM_EN; 4975 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4976 4977 /* Clear per-station keys table. */ 4978 urtwn_cam_init(sc); 4979 4980 /* Enable hardware sequence numbering. */ 4981 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4982 4983 /* Perform LO and IQ calibrations. */ 4984 urtwn_iq_calib(sc, sc->iqk_inited); 4985 sc->iqk_inited = true; 4986 4987 /* Perform LC calibration. */ 4988 urtwn_lc_calib(sc); 4989 4990 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4991 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4992 /* Fix USB interference issue. */ 4993 urtwn_write_1(sc, 0xfe40, 0xe0); 4994 urtwn_write_1(sc, 0xfe41, 0x8d); 4995 urtwn_write_1(sc, 0xfe42, 0x80); 4996 urtwn_write_4(sc, 0x20c, 0xfd0320); 4997 4998 urtwn_pa_bias_init(sc); 4999 } 5000 5001 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5002 !(sc->chip & URTWN_CHIP_92EU)) { 5003 /* 1T1R */ 5004 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5005 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5006 } 5007 5008 /* Initialize GPIO setting. */ 5009 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5010 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5011 5012 /* Fix for lower temperature. */ 5013 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5014 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5015 urtwn_write_1(sc, 0x15, 0xe9); 5016 5017 /* Set default channel. */ 5018 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5019 5020 /* Queue Rx xfers. */ 5021 for (size_t j = 0; j < sc->rx_npipe; j++) { 5022 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5023 data = &sc->rx_data[j][i]; 5024 usbd_setup_xfer(data->xfer, data, data->buf, 5025 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5026 urtwn_rxeof); 5027 error = usbd_transfer(data->xfer); 5028 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5029 error != USBD_IN_PROGRESS)) 5030 goto fail; 5031 } 5032 } 5033 5034 /* We're ready to go. */ 5035 ifp->if_flags &= ~IFF_OACTIVE; 5036 ifp->if_flags |= IFF_RUNNING; 5037 sc->sc_running = true; 5038 5039 mutex_exit(&sc->sc_write_mtx); 5040 5041 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5042 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5043 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5044 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5045 urtwn_wait_async(sc); 5046 5047 return 0; 5048 5049 fail: 5050 mutex_exit(&sc->sc_write_mtx); 5051 5052 urtwn_stop(ifp, 1); 5053 return error; 5054 } 5055 5056 static void __noinline 5057 urtwn_stop(struct ifnet *ifp, int disable) 5058 { 5059 struct urtwn_softc *sc = ifp->if_softc; 5060 struct ieee80211com *ic = &sc->sc_ic; 5061 size_t i; 5062 int s; 5063 5064 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5065 5066 s = splusb(); 5067 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5068 urtwn_wait_async(sc); 5069 splx(s); 5070 5071 sc->tx_timer = 0; 5072 ifp->if_timer = 0; 5073 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5074 5075 callout_stop(&sc->sc_scan_to); 5076 callout_stop(&sc->sc_calib_to); 5077 5078 /* Abort Tx. */ 5079 for (i = 0; i < sc->tx_npipe; i++) { 5080 if (sc->tx_pipe[i] != NULL) 5081 usbd_abort_pipe(sc->tx_pipe[i]); 5082 } 5083 5084 /* Stop Rx pipe. */ 5085 for (i = 0; i < sc->rx_npipe; i++) { 5086 if (sc->rx_pipe[i] != NULL) 5087 usbd_abort_pipe(sc->rx_pipe[i]); 5088 } 5089 5090 /* Free Tx/Rx buffers. */ 5091 urtwn_free_tx_list(sc); 5092 urtwn_free_rx_list(sc); 5093 5094 sc->sc_running = false; 5095 if (disable) 5096 urtwn_chip_stop(sc); 5097 } 5098 5099 static int 5100 urtwn_reset(struct ifnet *ifp) 5101 { 5102 struct urtwn_softc *sc = ifp->if_softc; 5103 struct ieee80211com *ic = &sc->sc_ic; 5104 5105 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5106 return ENETRESET; 5107 5108 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5109 5110 return 0; 5111 } 5112 5113 static void 5114 urtwn_chip_stop(struct urtwn_softc *sc) 5115 { 5116 uint32_t reg; 5117 bool disabled = true; 5118 5119 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5120 5121 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5122 ISSET(sc->chip, URTWN_CHIP_92EU)) 5123 return; 5124 5125 mutex_enter(&sc->sc_write_mtx); 5126 5127 /* 5128 * RF Off Sequence 5129 */ 5130 /* Pause MAC TX queue */ 5131 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5132 5133 /* Disable RF */ 5134 urtwn_rf_write(sc, 0, 0, 0); 5135 5136 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5137 5138 /* Reset BB state machine */ 5139 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5140 R92C_SYS_FUNC_EN_USBD | 5141 R92C_SYS_FUNC_EN_USBA | 5142 R92C_SYS_FUNC_EN_BB_GLB_RST); 5143 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5144 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5145 5146 /* 5147 * Reset digital sequence 5148 */ 5149 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5150 /* Reset MCU ready status */ 5151 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5152 /* If firmware in ram code, do reset */ 5153 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5154 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5155 ISSET(sc->chip, URTWN_CHIP_92EU)) 5156 urtwn_r88e_fw_reset(sc); 5157 else 5158 urtwn_fw_reset(sc); 5159 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5160 } 5161 } 5162 5163 /* Reset MAC and Enable 8051 */ 5164 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5165 5166 /* Reset MCU ready status */ 5167 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5168 5169 if (disabled) { 5170 /* Disable MAC clock */ 5171 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5172 /* Disable AFE PLL */ 5173 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5174 /* Gated AFE DIG_CLOCK */ 5175 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5176 /* Isolated digital to PON */ 5177 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5178 } 5179 5180 /* 5181 * Pull GPIO PIN to balance level and LED control 5182 */ 5183 /* 1. Disable GPIO[7:0] */ 5184 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5185 5186 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5187 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5188 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5189 5190 /* Disable GPIO[10:8] */ 5191 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5192 5193 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5194 reg |= (((reg & 0x000f) << 4) | 0x0780); 5195 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5196 5197 /* Disable LED0 & 1 */ 5198 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5199 5200 /* 5201 * Reset digital sequence 5202 */ 5203 if (disabled) { 5204 /* Disable ELDR clock */ 5205 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5206 /* Isolated ELDR to PON */ 5207 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5208 } 5209 5210 /* 5211 * Disable analog sequence 5212 */ 5213 if (disabled) { 5214 /* Disable A15 power */ 5215 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5216 /* Disable digital core power */ 5217 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5218 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5219 ~R92C_LDOV12D_CTRL_LDV12_EN); 5220 } 5221 5222 /* Enter PFM mode */ 5223 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5224 5225 /* Set USB suspend */ 5226 urtwn_write_2(sc, R92C_APS_FSMCO, 5227 R92C_APS_FSMCO_APDM_HOST | 5228 R92C_APS_FSMCO_AFSM_HSUS | 5229 R92C_APS_FSMCO_PFM_ALDN); 5230 5231 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5232 5233 mutex_exit(&sc->sc_write_mtx); 5234 } 5235 5236 static void 5237 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5238 { 5239 if (sc->sc_running == false) 5240 DELAY(ms * 1000); 5241 else 5242 usbd_delay_ms(sc->sc_udev, ms); 5243 } 5244 5245 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5246 5247 #ifdef _MODULE 5248 #include "ioconf.c" 5249 #endif 5250 5251 static int 5252 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5253 { 5254 int error = 0; 5255 5256 switch (cmd) { 5257 case MODULE_CMD_INIT: 5258 #ifdef _MODULE 5259 error = config_init_component(cfdriver_ioconf_urtwn, 5260 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5261 #endif 5262 return error; 5263 case MODULE_CMD_FINI: 5264 #ifdef _MODULE 5265 error = config_fini_component(cfdriver_ioconf_urtwn, 5266 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5267 #endif 5268 return error; 5269 default: 5270 return ENOTTY; 5271 } 5272 } 5273
Indexes created Thu Oct 02 14:10:14 GMT 2025