if_urtwn.c revision 1.108
1 /* $NetBSD: if_urtwn.c,v 1.108 2024/01/06 00:26:26 maya Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.108 2024/01/06 00:26:26 maya Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 99 #ifndef URTWN_DEBUG_DEFAULT 100 #define URTWN_DEBUG_DEFAULT 0 101 #endif 102 103 u_int urtwn_debug = URTWN_DEBUG_DEFAULT; 104 105 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 106 if (urtwn_debug & (n)) { \ 107 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 108 } \ 109 } while (/*CONSTCOND*/0) 110 #define URTWNHIST_FUNC() USBHIST_FUNC() 111 #define URTWNHIST_CALLED() do { \ 112 if (urtwn_debug & DBG_FN) { \ 113 KERNHIST_CALLED(usbhist); \ 114 } \ 115 } while(/*CONSTCOND*/0) 116 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 117 if (urtwn_debug & DBG_FN) { \ 118 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 119 } \ 120 } while(/*CONSTCOND*/0) 121 #else 122 #define DPRINTFN(n, fmt, a, b, c, d) 123 #define URTWNHIST_FUNC() 124 #define URTWNHIST_CALLED() 125 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 126 #endif 127 128 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 129 #define URTWN_RTL8188E_DEV(v,p) \ 130 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 131 #define URTWN_RTL8192EU_DEV(v,p) \ 132 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 133 static const struct urtwn_dev { 134 struct usb_devno dev; 135 uint32_t flags; 136 #define FLAG_RTL8188E __BIT(0) 137 #define FLAG_RTL8192E __BIT(1) 138 } urtwn_devs[] = { 139 URTWN_DEV(ABOCOM, RTL8188CU_1), 140 URTWN_DEV(ABOCOM, RTL8188CU_2), 141 URTWN_DEV(ABOCOM, RTL8192CU), 142 URTWN_DEV(ASUSTEK, RTL8192CU), 143 URTWN_DEV(ASUSTEK, RTL8192CU_3), 144 URTWN_DEV(ASUSTEK, USBN10NANO), 145 URTWN_DEV(ASUSTEK, RTL8192CU_3), 146 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 147 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 148 URTWN_DEV(AZUREWAVE, RTL8188CU), 149 URTWN_DEV(BELKIN, F7D2102), 150 URTWN_DEV(BELKIN, RTL8188CU), 151 URTWN_DEV(BELKIN, RTL8188CUS), 152 URTWN_DEV(BELKIN, RTL8192CU), 153 URTWN_DEV(BELKIN, RTL8192CU_1), 154 URTWN_DEV(BELKIN, RTL8192CU_2), 155 URTWN_DEV(CHICONY, RTL8188CUS_1), 156 URTWN_DEV(CHICONY, RTL8188CUS_2), 157 URTWN_DEV(CHICONY, RTL8188CUS_3), 158 URTWN_DEV(CHICONY, RTL8188CUS_4), 159 URTWN_DEV(CHICONY, RTL8188CUS_5), 160 URTWN_DEV(CHICONY, RTL8188CUS_6), 161 URTWN_DEV(COMPARE, RTL8192CU), 162 URTWN_DEV(COREGA, RTL8192CU), 163 URTWN_DEV(DLINK, DWA131B), 164 URTWN_DEV(DLINK, RTL8188CU), 165 URTWN_DEV(DLINK, RTL8192CU_1), 166 URTWN_DEV(DLINK, RTL8192CU_2), 167 URTWN_DEV(DLINK, RTL8192CU_3), 168 URTWN_DEV(DLINK, RTL8192CU_4), 169 URTWN_DEV(EDIMAX, RTL8188CU), 170 URTWN_DEV(EDIMAX, RTL8192CU), 171 URTWN_DEV(FEIXUN, RTL8188CU), 172 URTWN_DEV(FEIXUN, RTL8192CU), 173 URTWN_DEV(GUILLEMOT, HWNUP150), 174 URTWN_DEV(GUILLEMOT, RTL8192CU), 175 URTWN_DEV(HAWKING, RTL8192CU), 176 URTWN_DEV(HAWKING, RTL8192CU_2), 177 URTWN_DEV(HP3, RTL8188CU), 178 URTWN_DEV(IODATA, WNG150UM), 179 URTWN_DEV(IODATA, RTL8192CU), 180 URTWN_DEV(NETGEAR, WNA1000M), 181 URTWN_DEV(NETGEAR, RTL8192CU), 182 URTWN_DEV(NETGEAR4, RTL8188CU), 183 URTWN_DEV(NOVATECH, RTL8188CU), 184 URTWN_DEV(PLANEX2, RTL8188CU_1), 185 URTWN_DEV(PLANEX2, RTL8188CU_2), 186 URTWN_DEV(PLANEX2, RTL8192CU), 187 URTWN_DEV(PLANEX2, RTL8188CU_3), 188 URTWN_DEV(PLANEX2, RTL8188CU_4), 189 URTWN_DEV(PLANEX2, RTL8188CUS), 190 URTWN_DEV(REALTEK, RTL8188CE_0), 191 URTWN_DEV(REALTEK, RTL8188CE_1), 192 URTWN_DEV(REALTEK, RTL8188CTV), 193 URTWN_DEV(REALTEK, RTL8188CU_0), 194 URTWN_DEV(REALTEK, RTL8188CU_1), 195 URTWN_DEV(REALTEK, RTL8188CU_2), 196 URTWN_DEV(REALTEK, RTL8188CU_3), 197 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 198 URTWN_DEV(REALTEK, RTL8188CUS), 199 URTWN_DEV(REALTEK, RTL8188RU), 200 URTWN_DEV(REALTEK, RTL8188RU_2), 201 URTWN_DEV(REALTEK, RTL8188RU_3), 202 URTWN_DEV(REALTEK, RTL8191CU), 203 URTWN_DEV(REALTEK, RTL8192CE), 204 URTWN_DEV(REALTEK, RTL8192CU), 205 URTWN_DEV(SITECOMEU, RTL8188CU), 206 URTWN_DEV(SITECOMEU, RTL8188CU_2), 207 URTWN_DEV(SITECOMEU, RTL8192CU), 208 URTWN_DEV(SITECOMEU, RTL8192CUR2), 209 URTWN_DEV(TPLINK, RTL8192CU), 210 URTWN_DEV(TRENDNET, RTL8188CU), 211 URTWN_DEV(TRENDNET, RTL8192CU), 212 URTWN_DEV(TRENDNET, TEW648UBM), 213 URTWN_DEV(ZYXEL, RTL8192CU), 214 215 /* URTWN_RTL8188E */ 216 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 217 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 218 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 219 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 220 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 221 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 222 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 223 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 224 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 225 226 /* URTWN_RTL8192EU */ 227 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 228 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 229 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 230 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 231 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 232 }; 233 #undef URTWN_DEV 234 #undef URTWN_RTL8188E_DEV 235 #undef URTWN_RTL8192EU_DEV 236 237 static int urtwn_match(device_t, cfdata_t, void *); 238 static void urtwn_attach(device_t, device_t, void *); 239 static int urtwn_detach(device_t, int); 240 static int urtwn_activate(device_t, enum devact); 241 242 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 243 urtwn_attach, urtwn_detach, urtwn_activate); 244 245 static int urtwn_open_pipes(struct urtwn_softc *); 246 static void urtwn_close_pipes(struct urtwn_softc *); 247 static int urtwn_alloc_rx_list(struct urtwn_softc *); 248 static void urtwn_free_rx_list(struct urtwn_softc *); 249 static int urtwn_alloc_tx_list(struct urtwn_softc *); 250 static void urtwn_free_tx_list(struct urtwn_softc *); 251 static void urtwn_task(void *); 252 static void urtwn_do_async(struct urtwn_softc *, 253 void (*)(struct urtwn_softc *, void *), void *, int); 254 static void urtwn_wait_async(struct urtwn_softc *); 255 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 256 int); 257 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 258 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 259 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 260 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 261 int); 262 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 263 int); 264 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 265 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 266 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 267 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 268 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 269 uint32_t); 270 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 271 uint32_t); 272 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 273 uint32_t); 274 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 275 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 276 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 277 static void urtwn_efuse_read(struct urtwn_softc *); 278 static void urtwn_efuse_switch_power(struct urtwn_softc *); 279 static int urtwn_read_chipid(struct urtwn_softc *); 280 #ifdef URTWN_DEBUG 281 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 282 #endif 283 static void urtwn_read_rom(struct urtwn_softc *); 284 static void urtwn_r88e_read_rom(struct urtwn_softc *); 285 static int urtwn_media_change(struct ifnet *); 286 static int urtwn_ra_init(struct urtwn_softc *); 287 static int urtwn_get_nettype(struct urtwn_softc *); 288 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 289 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 290 static void urtwn_set_led(struct urtwn_softc *, int, int); 291 static void urtwn_calib_to(void *); 292 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 293 static void urtwn_next_scan(void *); 294 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 295 int); 296 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 297 static int urtwn_wme_update(struct ieee80211com *); 298 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 299 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 300 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 301 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 302 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 303 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 304 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 305 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 306 struct ieee80211_node *, struct urtwn_tx_data *); 307 static struct urtwn_tx_data * 308 urtwn_get_tx_data(struct urtwn_softc *, size_t); 309 static void urtwn_start(struct ifnet *); 310 static void urtwn_watchdog(struct ifnet *); 311 static int urtwn_ioctl(struct ifnet *, u_long, void *); 312 static int urtwn_r92c_power_on(struct urtwn_softc *); 313 static int urtwn_r92e_power_on(struct urtwn_softc *); 314 static int urtwn_r88e_power_on(struct urtwn_softc *); 315 static int urtwn_llt_init(struct urtwn_softc *); 316 static void urtwn_fw_reset(struct urtwn_softc *); 317 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 318 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 319 static int urtwn_load_firmware(struct urtwn_softc *); 320 static int urtwn_r92c_dma_init(struct urtwn_softc *); 321 static int urtwn_r88e_dma_init(struct urtwn_softc *); 322 static void urtwn_mac_init(struct urtwn_softc *); 323 static void urtwn_bb_init(struct urtwn_softc *); 324 static void urtwn_rf_init(struct urtwn_softc *); 325 static void urtwn_cam_init(struct urtwn_softc *); 326 static void urtwn_pa_bias_init(struct urtwn_softc *); 327 static void urtwn_rxfilter_init(struct urtwn_softc *); 328 static void urtwn_edca_init(struct urtwn_softc *); 329 static void urtwn_write_txpower(struct urtwn_softc *, int, 330 uint16_t[URTWN_RIDX_COUNT]); 331 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 332 uint16_t[URTWN_RIDX_COUNT]); 333 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 334 u_int, uint16_t[URTWN_RIDX_COUNT]); 335 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 336 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 337 u_int); 338 static void urtwn_iq_calib(struct urtwn_softc *, bool); 339 static void urtwn_lc_calib(struct urtwn_softc *); 340 static void urtwn_temp_calib(struct urtwn_softc *); 341 static int urtwn_init(struct ifnet *); 342 static void urtwn_stop(struct ifnet *, int); 343 static int urtwn_reset(struct ifnet *); 344 static void urtwn_chip_stop(struct urtwn_softc *); 345 static void urtwn_newassoc(struct ieee80211_node *, int); 346 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 347 348 /* Aliases. */ 349 #define urtwn_bb_write urtwn_write_4 350 #define urtwn_bb_read urtwn_read_4 351 352 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 353 354 static const uint16_t addaReg[] = { 355 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 356 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 357 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 358 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 359 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 360 }; 361 362 static int 363 urtwn_match(device_t parent, cfdata_t match, void *aux) 364 { 365 struct usb_attach_arg *uaa = aux; 366 367 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 368 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 369 } 370 371 static void 372 urtwn_attach(device_t parent, device_t self, void *aux) 373 { 374 struct urtwn_softc *sc = device_private(self); 375 struct ieee80211com *ic = &sc->sc_ic; 376 struct ifnet *ifp = &sc->sc_if; 377 struct usb_attach_arg *uaa = aux; 378 char *devinfop; 379 const struct urtwn_dev *dev; 380 usb_device_request_t req; 381 size_t i; 382 int error; 383 384 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 385 386 sc->sc_dev = self; 387 sc->sc_udev = uaa->uaa_device; 388 389 sc->chip = 0; 390 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 391 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 392 SET(sc->chip, URTWN_CHIP_88E); 393 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 394 SET(sc->chip, URTWN_CHIP_92EU); 395 396 aprint_naive("\n"); 397 aprint_normal("\n"); 398 399 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 400 aprint_normal_dev(self, "%s\n", devinfop); 401 usbd_devinfo_free(devinfop); 402 403 req.bmRequestType = UT_WRITE_DEVICE; 404 req.bRequest = UR_SET_FEATURE; 405 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 406 USETW(req.wIndex, UHF_PORT_SUSPEND); 407 USETW(req.wLength, 0); 408 409 (void) usbd_do_request(sc->sc_udev, &req, 0); 410 411 cv_init(&sc->sc_task_cv, "urtwntsk"); 412 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 413 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 414 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 415 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 416 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 417 418 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 419 420 callout_init(&sc->sc_scan_to, 0); 421 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 422 callout_init(&sc->sc_calib_to, 0); 423 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 424 425 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 426 RND_TYPE_NET, RND_FLAG_DEFAULT); 427 428 error = usbd_set_config_no(sc->sc_udev, 1, 0); 429 if (error != 0) { 430 aprint_error_dev(self, "failed to set configuration" 431 ", err=%s\n", usbd_errstr(error)); 432 goto fail; 433 } 434 435 /* Get the first interface handle. */ 436 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 437 if (error != 0) { 438 aprint_error_dev(self, "could not get interface handle\n"); 439 goto fail; 440 } 441 442 error = urtwn_read_chipid(sc); 443 if (error != 0) { 444 aprint_error_dev(self, "unsupported test chip\n"); 445 goto fail; 446 } 447 448 /* Determine number of Tx/Rx chains. */ 449 if (sc->chip & URTWN_CHIP_92C) { 450 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 451 sc->nrxchains = 2; 452 } else if (sc->chip & URTWN_CHIP_92EU) { 453 sc->ntxchains = 2; 454 sc->nrxchains = 2; 455 } else { 456 sc->ntxchains = 1; 457 sc->nrxchains = 1; 458 } 459 460 if (ISSET(sc->chip, URTWN_CHIP_88E) || 461 ISSET(sc->chip, URTWN_CHIP_92EU)) 462 urtwn_r88e_read_rom(sc); 463 else 464 urtwn_read_rom(sc); 465 466 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 467 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 468 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 469 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 470 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 471 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 472 "8188CUS", sc->ntxchains, sc->nrxchains, 473 ether_sprintf(ic->ic_myaddr)); 474 475 error = urtwn_open_pipes(sc); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 478 goto fail; 479 } 480 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 481 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 482 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 483 484 /* 485 * Setup the 802.11 device. 486 */ 487 ic->ic_ifp = ifp; 488 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 489 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 490 ic->ic_state = IEEE80211_S_INIT; 491 492 /* Set device capabilities. */ 493 ic->ic_caps = 494 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 495 IEEE80211_C_IBSS | /* IBSS mode supported */ 496 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 497 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 498 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 499 IEEE80211_C_WME | /* 802.11e */ 500 IEEE80211_C_WPA; /* 802.11i */ 501 502 /* Set supported .11b and .11g rates. */ 503 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 504 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 505 506 /* Set supported .11b and .11g channels (1 through 14). */ 507 for (i = 1; i <= 14; i++) { 508 ic->ic_channels[i].ic_freq = 509 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 510 ic->ic_channels[i].ic_flags = 511 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 512 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 513 } 514 515 ifp->if_softc = sc; 516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 517 ifp->if_init = urtwn_init; 518 ifp->if_ioctl = urtwn_ioctl; 519 ifp->if_start = urtwn_start; 520 ifp->if_watchdog = urtwn_watchdog; 521 IFQ_SET_READY(&ifp->if_snd); 522 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 523 524 if_initialize(ifp); 525 ieee80211_ifattach(ic); 526 527 /* override default methods */ 528 ic->ic_newassoc = urtwn_newassoc; 529 ic->ic_reset = urtwn_reset; 530 ic->ic_wme.wme_update = urtwn_wme_update; 531 532 /* Override state transition machine. */ 533 sc->sc_newstate = ic->ic_newstate; 534 ic->ic_newstate = urtwn_newstate; 535 536 /* XXX media locking needs revisiting */ 537 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 538 ieee80211_media_init_with_lock(ic, 539 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 540 541 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 542 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 543 &sc->sc_drvbpf); 544 545 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 546 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 547 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 548 549 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 550 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 551 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 552 553 ifp->if_percpuq = if_percpuq_create(ifp); 554 if_register(ifp); 555 556 ieee80211_announce(ic); 557 558 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 559 560 if (!pmf_device_register(self, NULL, NULL)) 561 aprint_error_dev(self, "couldn't establish power handler\n"); 562 563 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 564 return; 565 566 fail: 567 sc->sc_dying = 1; 568 aprint_error_dev(self, "attach failed\n"); 569 } 570 571 static int 572 urtwn_detach(device_t self, int flags) 573 { 574 struct urtwn_softc *sc = device_private(self); 575 struct ifnet *ifp = &sc->sc_if; 576 int s; 577 578 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 579 580 pmf_device_deregister(self); 581 582 s = splusb(); 583 584 sc->sc_dying = 1; 585 586 callout_halt(&sc->sc_scan_to, NULL); 587 callout_halt(&sc->sc_calib_to, NULL); 588 589 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 590 urtwn_stop(ifp, 0); 591 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 592 NULL); 593 594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 595 bpf_detach(ifp); 596 ieee80211_ifdetach(&sc->sc_ic); 597 if_detach(ifp); 598 599 mutex_destroy(&sc->sc_media_mtx); 600 601 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 602 urtwn_close_pipes(sc); 603 } 604 605 splx(s); 606 607 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 608 609 rnd_detach_source(&sc->rnd_source); 610 611 callout_destroy(&sc->sc_scan_to); 612 callout_destroy(&sc->sc_calib_to); 613 614 cv_destroy(&sc->sc_task_cv); 615 mutex_destroy(&sc->sc_write_mtx); 616 mutex_destroy(&sc->sc_fwcmd_mtx); 617 mutex_destroy(&sc->sc_tx_mtx); 618 mutex_destroy(&sc->sc_rx_mtx); 619 mutex_destroy(&sc->sc_task_mtx); 620 621 return 0; 622 } 623 624 static int 625 urtwn_activate(device_t self, enum devact act) 626 { 627 struct urtwn_softc *sc = device_private(self); 628 629 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 630 631 switch (act) { 632 case DVACT_DEACTIVATE: 633 if_deactivate(sc->sc_ic.ic_ifp); 634 return 0; 635 default: 636 return EOPNOTSUPP; 637 } 638 } 639 640 static int 641 urtwn_open_pipes(struct urtwn_softc *sc) 642 { 643 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 644 static uint8_t epaddr[R92C_MAX_EPOUT]; 645 static uint8_t rxepaddr[R92C_MAX_EPIN]; 646 usb_interface_descriptor_t *id; 647 usb_endpoint_descriptor_t *ed; 648 size_t i, ntx = 0, nrx = 0; 649 int error; 650 651 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 652 653 /* Determine the number of bulk-out pipes. */ 654 id = usbd_get_interface_descriptor(sc->sc_iface); 655 for (i = 0; i < id->bNumEndpoints; i++) { 656 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 657 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 658 continue; 659 } 660 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 661 if (ntx < sizeof(epaddr)) 662 epaddr[ntx] = ed->bEndpointAddress; 663 ntx++; 664 } 665 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 666 if (nrx < sizeof(rxepaddr)) 667 rxepaddr[nrx] = ed->bEndpointAddress; 668 nrx++; 669 } 670 } 671 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 672 aprint_error_dev(sc->sc_dev, 673 "%zd: invalid number of Rx bulk pipes\n", nrx); 674 return EIO; 675 } 676 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 677 aprint_error_dev(sc->sc_dev, 678 "%zd: invalid number of Tx bulk pipes\n", ntx); 679 return EIO; 680 } 681 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 682 nrx, ntx, 0, 0); 683 sc->rx_npipe = nrx; 684 sc->tx_npipe = ntx; 685 686 /* Open bulk-in pipe at address 0x81. */ 687 for (i = 0; i < nrx; i++) { 688 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 689 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 690 if (error != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "could not open Rx bulk pipe 0x%02x: %d\n", 693 rxepaddr[i], error); 694 goto fail; 695 } 696 } 697 698 /* Open bulk-out pipes (up to 3). */ 699 for (i = 0; i < ntx; i++) { 700 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 701 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 702 if (error != 0) { 703 aprint_error_dev(sc->sc_dev, 704 "could not open Tx bulk pipe 0x%02x: %d\n", 705 epaddr[i], error); 706 goto fail; 707 } 708 } 709 710 /* Map 802.11 access categories to USB pipes. */ 711 sc->ac2idx[WME_AC_BK] = 712 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 713 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 714 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 715 716 fail: 717 if (error != 0) 718 urtwn_close_pipes(sc); 719 return error; 720 } 721 722 static void 723 urtwn_close_pipes(struct urtwn_softc *sc) 724 { 725 struct usbd_pipe *pipe; 726 size_t i; 727 728 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 729 730 /* Close Rx pipes. */ 731 CTASSERT(sizeof(pipe) == sizeof(void *)); 732 for (i = 0; i < sc->rx_npipe; i++) { 733 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 734 if (pipe != NULL) { 735 usbd_close_pipe(pipe); 736 } 737 } 738 739 /* Close Tx pipes. */ 740 for (i = 0; i < sc->tx_npipe; i++) { 741 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 742 if (pipe != NULL) { 743 usbd_close_pipe(pipe); 744 } 745 } 746 } 747 748 static int __noinline 749 urtwn_alloc_rx_list(struct urtwn_softc *sc) 750 { 751 struct urtwn_rx_data *data; 752 size_t i; 753 int error = 0; 754 755 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 756 757 for (size_t j = 0; j < sc->rx_npipe; j++) { 758 TAILQ_INIT(&sc->rx_free_list[j]); 759 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 760 data = &sc->rx_data[j][i]; 761 762 data->sc = sc; /* Backpointer for callbacks. */ 763 764 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 765 0, 0, &data->xfer); 766 if (error) { 767 aprint_error_dev(sc->sc_dev, 768 "could not allocate xfer\n"); 769 break; 770 } 771 772 data->buf = usbd_get_buffer(data->xfer); 773 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 774 } 775 } 776 if (error != 0) 777 urtwn_free_rx_list(sc); 778 return error; 779 } 780 781 static void 782 urtwn_free_rx_list(struct urtwn_softc *sc) 783 { 784 struct usbd_xfer *xfer; 785 size_t i; 786 787 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 788 789 /* NB: Caller must abort pipe first. */ 790 for (size_t j = 0; j < sc->rx_npipe; j++) { 791 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 792 CTASSERT(sizeof(xfer) == sizeof(void *)); 793 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 794 if (xfer != NULL) 795 usbd_destroy_xfer(xfer); 796 } 797 } 798 } 799 800 static int __noinline 801 urtwn_alloc_tx_list(struct urtwn_softc *sc) 802 { 803 struct urtwn_tx_data *data; 804 size_t i; 805 int error = 0; 806 807 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 808 809 mutex_enter(&sc->sc_tx_mtx); 810 for (size_t j = 0; j < sc->tx_npipe; j++) { 811 TAILQ_INIT(&sc->tx_free_list[j]); 812 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 813 data = &sc->tx_data[j][i]; 814 815 data->sc = sc; /* Backpointer for callbacks. */ 816 data->pidx = j; 817 818 error = usbd_create_xfer(sc->tx_pipe[j], 819 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 820 &data->xfer); 821 if (error) { 822 aprint_error_dev(sc->sc_dev, 823 "could not allocate xfer\n"); 824 goto fail; 825 } 826 827 data->buf = usbd_get_buffer(data->xfer); 828 829 /* Append this Tx buffer to our free list. */ 830 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 831 } 832 } 833 mutex_exit(&sc->sc_tx_mtx); 834 return 0; 835 836 fail: 837 urtwn_free_tx_list(sc); 838 mutex_exit(&sc->sc_tx_mtx); 839 return error; 840 } 841 842 static void 843 urtwn_free_tx_list(struct urtwn_softc *sc) 844 { 845 struct usbd_xfer *xfer; 846 size_t i; 847 848 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 849 850 /* NB: Caller must abort pipe first. */ 851 for (size_t j = 0; j < sc->tx_npipe; j++) { 852 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 853 CTASSERT(sizeof(xfer) == sizeof(void *)); 854 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 855 if (xfer != NULL) 856 usbd_destroy_xfer(xfer); 857 } 858 } 859 } 860 861 static int 862 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 863 struct ieee80211_node *ni) 864 { 865 struct urtwn_tx_data *data = 866 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 867 868 if (data == NULL) 869 return ENOBUFS; 870 871 return urtwn_tx(sc, m, ni, data); 872 } 873 874 static void 875 urtwn_task(void *arg) 876 { 877 struct urtwn_softc *sc = arg; 878 struct ieee80211com *ic = &sc->sc_ic; 879 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 880 struct urtwn_host_cmd *cmd; 881 int s; 882 883 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 884 if (ic->ic_state == IEEE80211_S_RUN && 885 (ic->ic_opmode == IEEE80211_M_HOSTAP || 886 ic->ic_opmode == IEEE80211_M_IBSS)) { 887 888 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 889 &sc->sc_bo); 890 if (m == NULL) { 891 aprint_error_dev(sc->sc_dev, 892 "could not allocate beacon"); 893 } 894 895 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 896 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 897 } 898 899 /* beacon is no longer needed */ 900 m_freem(m); 901 } 902 903 /* Process host commands. */ 904 s = splusb(); 905 mutex_spin_enter(&sc->sc_task_mtx); 906 while (ring->next != ring->cur) { 907 cmd = &ring->cmd[ring->next]; 908 mutex_spin_exit(&sc->sc_task_mtx); 909 splx(s); 910 /* Invoke callback with kernel lock held. */ 911 cmd->cb(sc, cmd->data); 912 s = splusb(); 913 mutex_spin_enter(&sc->sc_task_mtx); 914 ring->queued--; 915 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 916 } 917 cv_broadcast(&sc->sc_task_cv); 918 mutex_spin_exit(&sc->sc_task_mtx); 919 splx(s); 920 } 921 922 static void 923 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 924 void *arg, int len) 925 { 926 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 927 struct urtwn_host_cmd *cmd; 928 int s; 929 930 URTWNHIST_FUNC(); 931 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 932 (uintptr_t)cb, (uintptr_t)arg, len, 0); 933 934 s = splusb(); 935 mutex_spin_enter(&sc->sc_task_mtx); 936 cmd = &ring->cmd[ring->cur]; 937 cmd->cb = cb; 938 KASSERT(len <= sizeof(cmd->data)); 939 memcpy(cmd->data, arg, len); 940 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 941 942 /* If there is no pending command already, schedule a task. */ 943 if (!sc->sc_dying && ++ring->queued == 1) { 944 mutex_spin_exit(&sc->sc_task_mtx); 945 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 946 } else 947 mutex_spin_exit(&sc->sc_task_mtx); 948 splx(s); 949 } 950 951 static void 952 urtwn_wait_async(struct urtwn_softc *sc) 953 { 954 955 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 956 957 /* Wait for all queued asynchronous commands to complete. */ 958 mutex_spin_enter(&sc->sc_task_mtx); 959 while (sc->cmdq.queued > 0) 960 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 961 mutex_spin_exit(&sc->sc_task_mtx); 962 } 963 964 static int 965 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 966 int len) 967 { 968 usb_device_request_t req; 969 usbd_status error; 970 971 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 972 KASSERT(mutex_owned(&sc->sc_write_mtx)); 973 974 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 975 req.bRequest = R92C_REQ_REGS; 976 USETW(req.wValue, addr); 977 USETW(req.wIndex, 0); 978 USETW(req.wLength, len); 979 error = usbd_do_request(sc->sc_udev, &req, buf); 980 if (error != USBD_NORMAL_COMPLETION) { 981 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 982 error, addr, len, 0); 983 } 984 return error; 985 } 986 987 static void 988 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 989 { 990 991 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 992 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 993 994 urtwn_write_region_1(sc, addr, &val, 1); 995 } 996 997 static void 998 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 999 { 1000 uint8_t buf[2]; 1001 1002 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1003 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1004 1005 buf[0] = (uint8_t)val; 1006 buf[1] = (uint8_t)(val >> 8); 1007 urtwn_write_region_1(sc, addr, buf, 2); 1008 } 1009 1010 static void 1011 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1012 { 1013 uint8_t buf[4]; 1014 1015 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1016 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1017 1018 buf[0] = (uint8_t)val; 1019 buf[1] = (uint8_t)(val >> 8); 1020 buf[2] = (uint8_t)(val >> 16); 1021 buf[3] = (uint8_t)(val >> 24); 1022 urtwn_write_region_1(sc, addr, buf, 4); 1023 } 1024 1025 static int 1026 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1027 { 1028 1029 URTWNHIST_FUNC(); 1030 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1031 1032 return urtwn_write_region_1(sc, addr, buf, len); 1033 } 1034 1035 static int 1036 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1037 int len) 1038 { 1039 usb_device_request_t req; 1040 usbd_status error; 1041 1042 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1043 1044 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1045 req.bRequest = R92C_REQ_REGS; 1046 USETW(req.wValue, addr); 1047 USETW(req.wIndex, 0); 1048 USETW(req.wLength, len); 1049 error = usbd_do_request(sc->sc_udev, &req, buf); 1050 if (error != USBD_NORMAL_COMPLETION) { 1051 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1052 error, addr, len, 0); 1053 } 1054 return error; 1055 } 1056 1057 static uint8_t 1058 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1059 { 1060 uint8_t val; 1061 1062 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1063 1064 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1065 return 0xff; 1066 1067 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1068 return val; 1069 } 1070 1071 static uint16_t 1072 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1073 { 1074 uint8_t buf[2]; 1075 uint16_t val; 1076 1077 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1078 1079 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1080 return 0xffff; 1081 1082 val = LE_READ_2(&buf[0]); 1083 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1084 return val; 1085 } 1086 1087 static uint32_t 1088 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1089 { 1090 uint8_t buf[4]; 1091 uint32_t val; 1092 1093 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1094 1095 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1096 return 0xffffffff; 1097 1098 val = LE_READ_4(&buf[0]); 1099 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1100 return val; 1101 } 1102 1103 static int 1104 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1105 { 1106 struct r92c_fw_cmd cmd; 1107 uint8_t *cp; 1108 int fwcur; 1109 int ntries; 1110 1111 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1112 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1113 1114 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1115 1116 mutex_enter(&sc->sc_fwcmd_mtx); 1117 fwcur = sc->fwcur; 1118 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1119 1120 /* Wait for current FW box to be empty. */ 1121 for (ntries = 0; ntries < 100; ntries++) { 1122 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1123 break; 1124 urtwn_delay_ms(sc, 2); 1125 } 1126 if (ntries == 100) { 1127 aprint_error_dev(sc->sc_dev, 1128 "could not send firmware command %d\n", id); 1129 mutex_exit(&sc->sc_fwcmd_mtx); 1130 return ETIMEDOUT; 1131 } 1132 1133 memset(&cmd, 0, sizeof(cmd)); 1134 KASSERT(len <= sizeof(cmd.msg)); 1135 memcpy(cmd.msg, buf, len); 1136 1137 /* Write the first word last since that will trigger the FW. */ 1138 cp = (uint8_t *)&cmd; 1139 cmd.id = id; 1140 if (len >= 4) { 1141 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1142 cmd.id |= R92C_CMD_FLAG_EXT; 1143 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1144 &cp[1], 2); 1145 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1146 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1147 ((uint32_t)cp[5] << 24)); 1148 } else { 1149 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1150 &cp[4], 2); 1151 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1152 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1153 ((uint32_t)cp[3] << 24)); 1154 } 1155 } else { 1156 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1157 } 1158 mutex_exit(&sc->sc_fwcmd_mtx); 1159 1160 return 0; 1161 } 1162 1163 static __inline void 1164 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1165 { 1166 1167 sc->sc_rf_write(sc, chain, addr, val); 1168 } 1169 1170 static void 1171 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1172 uint32_t val) 1173 { 1174 1175 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1176 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1177 } 1178 1179 static void 1180 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1181 uint32_t val) 1182 { 1183 1184 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1185 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1186 } 1187 1188 static void 1189 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1190 uint32_t val) 1191 { 1192 1193 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1194 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1195 } 1196 1197 static uint32_t 1198 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1199 { 1200 uint32_t reg[R92C_MAX_CHAINS], val; 1201 1202 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1203 if (chain != 0) { 1204 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1205 } 1206 1207 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1208 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1209 urtwn_delay_ms(sc, 1); 1210 1211 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1212 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1213 R92C_HSSI_PARAM2_READ_EDGE); 1214 urtwn_delay_ms(sc, 1); 1215 1216 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1217 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1218 urtwn_delay_ms(sc, 1); 1219 1220 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1221 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1222 } else { 1223 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1224 } 1225 return MS(val, R92C_LSSI_READBACK_DATA); 1226 } 1227 1228 static int 1229 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1230 { 1231 int ntries; 1232 1233 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1234 1235 urtwn_write_4(sc, R92C_LLT_INIT, 1236 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1237 SM(R92C_LLT_INIT_ADDR, addr) | 1238 SM(R92C_LLT_INIT_DATA, data)); 1239 /* Wait for write operation to complete. */ 1240 for (ntries = 0; ntries < 20; ntries++) { 1241 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1242 R92C_LLT_INIT_OP_NO_ACTIVE) { 1243 /* Done */ 1244 return 0; 1245 } 1246 DELAY(5); 1247 } 1248 return ETIMEDOUT; 1249 } 1250 1251 static uint8_t 1252 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1253 { 1254 uint32_t reg; 1255 int ntries; 1256 1257 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1258 1259 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1260 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1261 reg &= ~R92C_EFUSE_CTRL_VALID; 1262 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1263 1264 /* Wait for read operation to complete. */ 1265 for (ntries = 0; ntries < 100; ntries++) { 1266 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1267 if (reg & R92C_EFUSE_CTRL_VALID) { 1268 /* Done */ 1269 return MS(reg, R92C_EFUSE_CTRL_DATA); 1270 } 1271 DELAY(5); 1272 } 1273 aprint_error_dev(sc->sc_dev, 1274 "could not read efuse byte at address 0x%04x\n", addr); 1275 return 0xff; 1276 } 1277 1278 static void 1279 urtwn_efuse_read(struct urtwn_softc *sc) 1280 { 1281 uint8_t *rom = (uint8_t *)&sc->rom; 1282 uint32_t reg; 1283 uint16_t addr = 0; 1284 uint8_t off, msk; 1285 size_t i; 1286 1287 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1288 1289 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1290 1291 urtwn_efuse_switch_power(sc); 1292 1293 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1294 while (addr < 512) { 1295 reg = urtwn_efuse_read_1(sc, addr); 1296 if (reg == 0xff) 1297 break; 1298 addr++; 1299 off = reg >> 4; 1300 msk = reg & 0xf; 1301 for (i = 0; i < 4; i++) { 1302 if (msk & (1U << i)) 1303 continue; 1304 1305 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1306 addr++; 1307 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1308 addr++; 1309 } 1310 } 1311 #ifdef URTWN_DEBUG 1312 /* Dump ROM content. */ 1313 for (i = 0; i < (int)sizeof(sc->rom); i++) 1314 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1315 #endif 1316 } 1317 1318 static void 1319 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1320 { 1321 uint32_t reg; 1322 1323 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1324 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1325 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1326 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1327 } 1328 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1329 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1330 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1331 reg | R92C_SYS_FUNC_EN_ELDR); 1332 } 1333 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1334 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1335 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1336 urtwn_write_2(sc, R92C_SYS_CLKR, 1337 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1338 } 1339 } 1340 1341 static int 1342 urtwn_read_chipid(struct urtwn_softc *sc) 1343 { 1344 uint32_t reg; 1345 1346 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1347 1348 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1349 ISSET(sc->chip, URTWN_CHIP_92EU)) 1350 return 0; 1351 1352 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1353 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1354 /* test chip, not supported */ 1355 return EIO; 1356 } 1357 if (reg & R92C_SYS_CFG_TYPE_92C) { 1358 sc->chip |= URTWN_CHIP_92C; 1359 /* Check if it is a castrated 8192C. */ 1360 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1361 R92C_HPON_FSM_CHIP_BONDING_ID) == 1362 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1363 sc->chip |= URTWN_CHIP_92C_1T2R; 1364 } 1365 } 1366 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1367 sc->chip |= URTWN_CHIP_UMC; 1368 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1369 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1370 } 1371 } 1372 return 0; 1373 } 1374 1375 #ifdef URTWN_DEBUG 1376 static void 1377 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1378 { 1379 1380 aprint_normal_dev(sc->sc_dev, 1381 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1382 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1383 1384 aprint_normal_dev(sc->sc_dev, 1385 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1386 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1387 1388 aprint_normal_dev(sc->sc_dev, 1389 "macaddr %s\n", 1390 ether_sprintf(rp->macaddr)); 1391 1392 aprint_normal_dev(sc->sc_dev, 1393 "string %s, subcustomer_id %#x\n", 1394 rp->string, rp->subcustomer_id); 1395 1396 aprint_normal_dev(sc->sc_dev, 1397 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1398 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1399 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1400 1401 aprint_normal_dev(sc->sc_dev, 1402 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1403 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1404 rp->ht40_1s_tx_pwr[0][2], 1405 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1406 rp->ht40_1s_tx_pwr[1][2]); 1407 1408 aprint_normal_dev(sc->sc_dev, 1409 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1410 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1411 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1412 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1413 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1414 1415 aprint_normal_dev(sc->sc_dev, 1416 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1417 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1418 rp->ht20_tx_pwr_diff[2] & 0xf, 1419 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1420 rp->ht20_tx_pwr_diff[2] >> 4); 1421 1422 aprint_normal_dev(sc->sc_dev, 1423 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1424 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1425 rp->ofdm_tx_pwr_diff[2] & 0xf, 1426 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1427 rp->ofdm_tx_pwr_diff[2] >> 4); 1428 1429 aprint_normal_dev(sc->sc_dev, 1430 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1431 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1432 rp->ht40_max_pwr[2] & 0xf, 1433 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1434 rp->ht40_max_pwr[2] >> 4); 1435 1436 aprint_normal_dev(sc->sc_dev, 1437 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1438 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1439 rp->ht20_max_pwr[2] & 0xf, 1440 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1441 rp->ht20_max_pwr[2] >> 4); 1442 1443 aprint_normal_dev(sc->sc_dev, 1444 "xtal_calib %d, tssi %d %d, thermal %d\n", 1445 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1446 1447 aprint_normal_dev(sc->sc_dev, 1448 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1449 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1450 1451 aprint_normal_dev(sc->sc_dev, 1452 "channnel_plan %d, version %d customer_id %#x\n", 1453 rp->channel_plan, rp->version, rp->curstomer_id); 1454 } 1455 #endif 1456 1457 static void 1458 urtwn_read_rom(struct urtwn_softc *sc) 1459 { 1460 struct ieee80211com *ic = &sc->sc_ic; 1461 struct r92c_rom *rom = &sc->rom; 1462 1463 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1464 1465 mutex_enter(&sc->sc_write_mtx); 1466 1467 /* Read full ROM image. */ 1468 urtwn_efuse_read(sc); 1469 #ifdef URTWN_DEBUG 1470 if (urtwn_debug & DBG_REG) 1471 urtwn_dump_rom(sc, rom); 1472 #endif 1473 1474 /* XXX Weird but this is what the vendor driver does. */ 1475 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1476 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1477 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1478 1479 DPRINTFN(DBG_INIT, 1480 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1481 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1482 1483 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1484 1485 sc->sc_rf_write = urtwn_r92c_rf_write; 1486 sc->sc_power_on = urtwn_r92c_power_on; 1487 sc->sc_dma_init = urtwn_r92c_dma_init; 1488 1489 mutex_exit(&sc->sc_write_mtx); 1490 } 1491 1492 static void 1493 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1494 { 1495 struct ieee80211com *ic = &sc->sc_ic; 1496 uint8_t *rom = sc->r88e_rom; 1497 uint32_t reg; 1498 uint16_t addr = 0; 1499 uint8_t off, msk, tmp; 1500 int i; 1501 1502 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1503 1504 mutex_enter(&sc->sc_write_mtx); 1505 1506 off = 0; 1507 urtwn_efuse_switch_power(sc); 1508 1509 /* Read full ROM image. */ 1510 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1511 while (addr < 4096) { 1512 reg = urtwn_efuse_read_1(sc, addr); 1513 if (reg == 0xff) 1514 break; 1515 addr++; 1516 if ((reg & 0x1f) == 0x0f) { 1517 tmp = (reg & 0xe0) >> 5; 1518 reg = urtwn_efuse_read_1(sc, addr); 1519 if ((reg & 0x0f) != 0x0f) 1520 off = ((reg & 0xf0) >> 1) | tmp; 1521 addr++; 1522 } else 1523 off = reg >> 4; 1524 msk = reg & 0xf; 1525 for (i = 0; i < 4; i++) { 1526 if (msk & (1 << i)) 1527 continue; 1528 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1529 addr++; 1530 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1531 addr++; 1532 } 1533 } 1534 #ifdef URTWN_DEBUG 1535 if (urtwn_debug & DBG_REG) { 1536 } 1537 #endif 1538 1539 addr = 0x10; 1540 for (i = 0; i < 6; i++) 1541 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1542 for (i = 0; i < 5; i++) 1543 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1544 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1545 if (sc->bw20_tx_pwr_diff & 0x08) 1546 sc->bw20_tx_pwr_diff |= 0xf0; 1547 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1548 if (sc->ofdm_tx_pwr_diff & 0x08) 1549 sc->ofdm_tx_pwr_diff |= 0xf0; 1550 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1551 1552 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1553 1554 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1555 sc->sc_power_on = urtwn_r92e_power_on; 1556 sc->sc_rf_write = urtwn_r92e_rf_write; 1557 } else { 1558 sc->sc_power_on = urtwn_r88e_power_on; 1559 sc->sc_rf_write = urtwn_r88e_rf_write; 1560 } 1561 sc->sc_dma_init = urtwn_r88e_dma_init; 1562 1563 mutex_exit(&sc->sc_write_mtx); 1564 } 1565 1566 static int 1567 urtwn_media_change(struct ifnet *ifp) 1568 { 1569 int error; 1570 1571 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1572 1573 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1574 return error; 1575 1576 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1577 (IFF_UP | IFF_RUNNING)) { 1578 urtwn_init(ifp); 1579 } 1580 return 0; 1581 } 1582 1583 /* 1584 * Initialize rate adaptation in firmware. 1585 */ 1586 static int __noinline 1587 urtwn_ra_init(struct urtwn_softc *sc) 1588 { 1589 static const uint8_t map[] = { 1590 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1591 }; 1592 struct ieee80211com *ic = &sc->sc_ic; 1593 struct ieee80211_node *ni = ic->ic_bss; 1594 struct ieee80211_rateset *rs = &ni->ni_rates; 1595 struct r92c_fw_cmd_macid_cfg cmd; 1596 uint32_t rates, basicrates; 1597 uint32_t rrsr_mask, rrsr_rate; 1598 uint8_t mode; 1599 size_t maxrate, maxbasicrate, i, j; 1600 int error; 1601 1602 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1603 1604 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1605 1606 /* Get normal and basic rates mask. */ 1607 rates = basicrates = 1; 1608 maxrate = maxbasicrate = 0; 1609 for (i = 0; i < rs->rs_nrates; i++) { 1610 /* Convert 802.11 rate to HW rate index. */ 1611 for (j = 0; j < __arraycount(map); j++) { 1612 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1613 break; 1614 } 1615 } 1616 if (j == __arraycount(map)) { 1617 /* Unknown rate, skip. */ 1618 continue; 1619 } 1620 1621 rates |= 1U << j; 1622 if (j > maxrate) { 1623 maxrate = j; 1624 } 1625 1626 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1627 basicrates |= 1U << j; 1628 if (j > maxbasicrate) { 1629 maxbasicrate = j; 1630 } 1631 } 1632 } 1633 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1634 mode = R92C_RAID_11B; 1635 } else { 1636 mode = R92C_RAID_11BG; 1637 } 1638 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1639 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1640 "maxrate=%jx, maxbasicrate=%jx", 1641 rates, basicrates, maxrate, maxbasicrate); 1642 1643 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1644 maxbasicrate |= R92C_RATE_SHORTGI; 1645 maxrate |= R92C_RATE_SHORTGI; 1646 } 1647 1648 /* Set rates mask for group addressed frames. */ 1649 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1650 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1651 cmd.macid |= RTWN_MACID_SHORTGI; 1652 cmd.mask = htole32((mode << 28) | basicrates); 1653 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1654 if (error != 0) { 1655 aprint_error_dev(sc->sc_dev, 1656 "could not add broadcast station\n"); 1657 return error; 1658 } 1659 /* Set initial MRR rate. */ 1660 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1661 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1662 1663 /* Set rates mask for unicast frames. */ 1664 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1665 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1666 cmd.macid |= RTWN_MACID_SHORTGI; 1667 cmd.mask = htole32((mode << 28) | rates); 1668 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1669 if (error != 0) { 1670 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1671 return error; 1672 } 1673 /* Set initial MRR rate. */ 1674 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1675 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1676 1677 rrsr_rate = ic->ic_fixed_rate; 1678 if (rrsr_rate == -1) 1679 rrsr_rate = 11; 1680 1681 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1682 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1683 1684 /* Indicate highest supported rate. */ 1685 ni->ni_txrate = rs->rs_nrates - 1; 1686 1687 return 0; 1688 } 1689 1690 static int 1691 urtwn_get_nettype(struct urtwn_softc *sc) 1692 { 1693 struct ieee80211com *ic = &sc->sc_ic; 1694 int type; 1695 1696 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1697 1698 switch (ic->ic_opmode) { 1699 case IEEE80211_M_STA: 1700 type = R92C_CR_NETTYPE_INFRA; 1701 break; 1702 1703 case IEEE80211_M_IBSS: 1704 type = R92C_CR_NETTYPE_ADHOC; 1705 break; 1706 1707 default: 1708 type = R92C_CR_NETTYPE_NOLINK; 1709 break; 1710 } 1711 1712 return type; 1713 } 1714 1715 static void 1716 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1717 { 1718 uint8_t reg; 1719 1720 URTWNHIST_FUNC(); 1721 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1722 1723 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1724 1725 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1726 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1727 } 1728 1729 static void 1730 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1731 { 1732 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1733 uint64_t tsf; 1734 1735 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1736 1737 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1738 1739 /* Enable TSF synchronization. */ 1740 urtwn_write_1(sc, R92C_BCN_CTRL, 1741 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1742 1743 /* Correct TSF */ 1744 urtwn_write_1(sc, R92C_BCN_CTRL, 1745 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1746 1747 /* Set initial TSF. */ 1748 tsf = ni->ni_tstamp.tsf; 1749 tsf = le64toh(tsf); 1750 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1751 tsf -= IEEE80211_DUR_TU; 1752 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1753 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1754 1755 urtwn_write_1(sc, R92C_BCN_CTRL, 1756 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1757 } 1758 1759 static void 1760 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1761 { 1762 uint8_t reg; 1763 1764 URTWNHIST_FUNC(); 1765 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1766 1767 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1768 1769 if (led == URTWN_LED_LINK) { 1770 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1771 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1772 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1773 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1774 (R92C_LEDCFG0_DIS << 1)); 1775 if (on) { 1776 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1777 R92E_LEDSON; 1778 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1779 } 1780 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1781 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1782 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1783 if (!on) { 1784 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1785 urtwn_write_1(sc, R92C_LEDCFG2, 1786 reg | R92C_LEDCFG0_DIS); 1787 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1788 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1789 reg & 0xfe); 1790 } 1791 } else { 1792 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1793 if (!on) { 1794 reg |= R92C_LEDCFG0_DIS; 1795 } 1796 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1797 } 1798 sc->ledlink = on; /* Save LED state. */ 1799 } 1800 } 1801 1802 static void 1803 urtwn_calib_to(void *arg) 1804 { 1805 struct urtwn_softc *sc = arg; 1806 1807 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1808 1809 if (sc->sc_dying) 1810 return; 1811 1812 /* Do it in a process context. */ 1813 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1814 } 1815 1816 /* ARGSUSED */ 1817 static void 1818 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1819 { 1820 struct r92c_fw_cmd_rssi cmd; 1821 struct r92e_fw_cmd_rssi cmde; 1822 1823 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1824 1825 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1826 goto restart_timer; 1827 1828 mutex_enter(&sc->sc_write_mtx); 1829 if (sc->avg_pwdb != -1) { 1830 /* Indicate Rx signal strength to FW for rate adaptation. */ 1831 memset(&cmd, 0, sizeof(cmd)); 1832 memset(&cmde, 0, sizeof(cmde)); 1833 cmd.macid = 0; /* BSS. */ 1834 cmde.macid = 0; /* BSS. */ 1835 cmd.pwdb = sc->avg_pwdb; 1836 cmde.pwdb = sc->avg_pwdb; 1837 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1838 sc->avg_pwdb, 0, 0, 0); 1839 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1840 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1841 sizeof(cmd)); 1842 } else { 1843 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1844 sizeof(cmde)); 1845 } 1846 } 1847 1848 /* Do temperature compensation. */ 1849 urtwn_temp_calib(sc); 1850 mutex_exit(&sc->sc_write_mtx); 1851 1852 restart_timer: 1853 if (!sc->sc_dying) { 1854 /* Restart calibration timer. */ 1855 callout_schedule(&sc->sc_calib_to, hz); 1856 } 1857 } 1858 1859 static void 1860 urtwn_next_scan(void *arg) 1861 { 1862 struct urtwn_softc *sc = arg; 1863 int s; 1864 1865 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1866 1867 if (sc->sc_dying) 1868 return; 1869 1870 s = splnet(); 1871 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1872 ieee80211_next_scan(&sc->sc_ic); 1873 splx(s); 1874 } 1875 1876 static void 1877 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1878 { 1879 URTWNHIST_FUNC(); 1880 URTWNHIST_CALLARGS("new node %06jx%06jx", 1881 ni->ni_macaddr[0] << 2 | 1882 ni->ni_macaddr[1] << 1 | 1883 ni->ni_macaddr[2], 1884 ni->ni_macaddr[3] << 2 | 1885 ni->ni_macaddr[4] << 1 | 1886 ni->ni_macaddr[5], 1887 0, 0); 1888 /* start with lowest Tx rate */ 1889 ni->ni_txrate = 0; 1890 } 1891 1892 static int 1893 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1894 { 1895 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1896 struct urtwn_cmd_newstate cmd; 1897 1898 URTWNHIST_FUNC(); 1899 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1900 1901 callout_stop(&sc->sc_scan_to); 1902 callout_stop(&sc->sc_calib_to); 1903 1904 /* Do it in a process context. */ 1905 cmd.state = nstate; 1906 cmd.arg = arg; 1907 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1908 return 0; 1909 } 1910 1911 static void 1912 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1913 { 1914 struct urtwn_cmd_newstate *cmd = arg; 1915 struct ieee80211com *ic = &sc->sc_ic; 1916 struct ieee80211_node *ni; 1917 enum ieee80211_state ostate = ic->ic_state; 1918 enum ieee80211_state nstate = cmd->state; 1919 uint32_t reg; 1920 uint8_t sifs_time, msr; 1921 int s; 1922 1923 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1924 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1925 1926 s = splnet(); 1927 mutex_enter(&sc->sc_write_mtx); 1928 1929 callout_stop(&sc->sc_scan_to); 1930 callout_stop(&sc->sc_calib_to); 1931 1932 switch (ostate) { 1933 case IEEE80211_S_INIT: 1934 break; 1935 1936 case IEEE80211_S_SCAN: 1937 if (nstate != IEEE80211_S_SCAN) { 1938 /* 1939 * End of scanning 1940 */ 1941 /* flush 4-AC Queue after site_survey */ 1942 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1943 1944 /* Allow Rx from our BSSID only. */ 1945 urtwn_write_4(sc, R92C_RCR, 1946 urtwn_read_4(sc, R92C_RCR) | 1947 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1948 } 1949 break; 1950 1951 case IEEE80211_S_AUTH: 1952 case IEEE80211_S_ASSOC: 1953 break; 1954 1955 case IEEE80211_S_RUN: 1956 /* Turn link LED off. */ 1957 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1958 1959 /* Set media status to 'No Link'. */ 1960 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1961 1962 /* Stop Rx of data frames. */ 1963 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1964 1965 /* Reset TSF. */ 1966 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1967 1968 /* Disable TSF synchronization. */ 1969 urtwn_write_1(sc, R92C_BCN_CTRL, 1970 urtwn_read_1(sc, R92C_BCN_CTRL) | 1971 R92C_BCN_CTRL_DIS_TSF_UDT0); 1972 1973 /* Back to 20MHz mode */ 1974 urtwn_set_chan(sc, ic->ic_curchan, 1975 IEEE80211_HTINFO_2NDCHAN_NONE); 1976 1977 if (ic->ic_opmode == IEEE80211_M_IBSS || 1978 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1979 /* Stop BCN */ 1980 urtwn_write_1(sc, R92C_BCN_CTRL, 1981 urtwn_read_1(sc, R92C_BCN_CTRL) & 1982 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1983 } 1984 1985 /* Reset EDCA parameters. */ 1986 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1987 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1988 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1989 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1990 1991 /* flush all cam entries */ 1992 urtwn_cam_init(sc); 1993 break; 1994 } 1995 1996 switch (nstate) { 1997 case IEEE80211_S_INIT: 1998 /* Turn link LED off. */ 1999 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2000 break; 2001 2002 case IEEE80211_S_SCAN: 2003 if (ostate != IEEE80211_S_SCAN) { 2004 /* 2005 * Begin of scanning 2006 */ 2007 2008 /* Set gain for scanning. */ 2009 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2010 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2011 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2012 2013 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2014 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2015 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2016 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2017 } 2018 2019 /* Set media status to 'No Link'. */ 2020 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2021 2022 /* Allow Rx from any BSSID. */ 2023 urtwn_write_4(sc, R92C_RCR, 2024 urtwn_read_4(sc, R92C_RCR) & 2025 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2026 2027 /* Stop Rx of data frames. */ 2028 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2029 2030 /* Disable update TSF */ 2031 urtwn_write_1(sc, R92C_BCN_CTRL, 2032 urtwn_read_1(sc, R92C_BCN_CTRL) | 2033 R92C_BCN_CTRL_DIS_TSF_UDT0); 2034 } 2035 2036 /* Make link LED blink during scan. */ 2037 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2038 2039 /* Pause AC Tx queues. */ 2040 urtwn_write_1(sc, R92C_TXPAUSE, 2041 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2042 2043 urtwn_set_chan(sc, ic->ic_curchan, 2044 IEEE80211_HTINFO_2NDCHAN_NONE); 2045 2046 /* Start periodic scan. */ 2047 if (!sc->sc_dying) 2048 callout_schedule(&sc->sc_scan_to, hz / 5); 2049 break; 2050 2051 case IEEE80211_S_AUTH: 2052 /* Set initial gain under link. */ 2053 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2054 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2055 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2056 2057 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2058 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2059 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2060 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2061 } 2062 2063 /* Set media status to 'No Link'. */ 2064 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2065 2066 /* Allow Rx from any BSSID. */ 2067 urtwn_write_4(sc, R92C_RCR, 2068 urtwn_read_4(sc, R92C_RCR) & 2069 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2070 2071 urtwn_set_chan(sc, ic->ic_curchan, 2072 IEEE80211_HTINFO_2NDCHAN_NONE); 2073 break; 2074 2075 case IEEE80211_S_ASSOC: 2076 break; 2077 2078 case IEEE80211_S_RUN: 2079 ni = ic->ic_bss; 2080 2081 /* XXX: Set 20MHz mode */ 2082 urtwn_set_chan(sc, ic->ic_curchan, 2083 IEEE80211_HTINFO_2NDCHAN_NONE); 2084 2085 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2086 /* Back to 20MHz mode */ 2087 urtwn_set_chan(sc, ic->ic_curchan, 2088 IEEE80211_HTINFO_2NDCHAN_NONE); 2089 2090 /* Set media status to 'No Link'. */ 2091 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2092 2093 /* Enable Rx of data frames. */ 2094 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2095 2096 /* Allow Rx from any BSSID. */ 2097 urtwn_write_4(sc, R92C_RCR, 2098 urtwn_read_4(sc, R92C_RCR) & 2099 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2100 2101 /* Accept Rx data/control/management frames */ 2102 urtwn_write_4(sc, R92C_RCR, 2103 urtwn_read_4(sc, R92C_RCR) | 2104 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2105 2106 /* Turn link LED on. */ 2107 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2108 break; 2109 } 2110 2111 /* Set media status to 'Associated'. */ 2112 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2113 2114 /* Set BSSID. */ 2115 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2116 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2117 2118 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2119 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2120 } else { 2121 /* 802.11b/g */ 2122 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2123 } 2124 2125 /* Enable Rx of data frames. */ 2126 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2127 2128 /* Set beacon interval. */ 2129 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2130 2131 msr = urtwn_read_1(sc, R92C_MSR); 2132 msr &= R92C_MSR_MASK; 2133 switch (ic->ic_opmode) { 2134 case IEEE80211_M_STA: 2135 /* Allow Rx from our BSSID only. */ 2136 urtwn_write_4(sc, R92C_RCR, 2137 urtwn_read_4(sc, R92C_RCR) | 2138 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2139 2140 /* Enable TSF synchronization. */ 2141 urtwn_tsf_sync_enable(sc); 2142 2143 msr |= R92C_MSR_INFRA; 2144 break; 2145 case IEEE80211_M_HOSTAP: 2146 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2147 2148 /* Allow Rx from any BSSID. */ 2149 urtwn_write_4(sc, R92C_RCR, 2150 urtwn_read_4(sc, R92C_RCR) & 2151 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2152 2153 /* Reset TSF timer to zero. */ 2154 reg = urtwn_read_4(sc, R92C_TCR); 2155 reg &= ~0x01; 2156 urtwn_write_4(sc, R92C_TCR, reg); 2157 reg |= 0x01; 2158 urtwn_write_4(sc, R92C_TCR, reg); 2159 2160 msr |= R92C_MSR_AP; 2161 break; 2162 default: 2163 msr |= R92C_MSR_ADHOC; 2164 break; 2165 } 2166 urtwn_write_1(sc, R92C_MSR, msr); 2167 2168 sifs_time = 10; 2169 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2170 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2171 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2172 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2173 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2174 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2175 2176 /* Initialize rate adaptation. */ 2177 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2178 ISSET(sc->chip, URTWN_CHIP_92EU)) 2179 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2180 else 2181 urtwn_ra_init(sc); 2182 2183 /* Turn link LED on. */ 2184 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2185 2186 /* Reset average RSSI. */ 2187 sc->avg_pwdb = -1; 2188 2189 /* Reset temperature calibration state machine. */ 2190 sc->thcal_state = 0; 2191 sc->thcal_lctemp = 0; 2192 2193 /* Start periodic calibration. */ 2194 if (!sc->sc_dying) 2195 callout_schedule(&sc->sc_calib_to, hz); 2196 break; 2197 } 2198 2199 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2200 2201 mutex_exit(&sc->sc_write_mtx); 2202 splx(s); 2203 } 2204 2205 static int 2206 urtwn_wme_update(struct ieee80211com *ic) 2207 { 2208 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2209 2210 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2211 2212 /* don't override default WME values if WME is not actually enabled */ 2213 if (!(ic->ic_flags & IEEE80211_F_WME)) 2214 return 0; 2215 2216 /* Do it in a process context. */ 2217 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2218 return 0; 2219 } 2220 2221 static void 2222 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2223 { 2224 static const uint16_t ac2reg[WME_NUM_AC] = { 2225 R92C_EDCA_BE_PARAM, 2226 R92C_EDCA_BK_PARAM, 2227 R92C_EDCA_VI_PARAM, 2228 R92C_EDCA_VO_PARAM 2229 }; 2230 struct ieee80211com *ic = &sc->sc_ic; 2231 const struct wmeParams *wmep; 2232 int ac, aifs, slottime; 2233 int s; 2234 2235 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2236 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2237 2238 s = splnet(); 2239 mutex_enter(&sc->sc_write_mtx); 2240 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2241 for (ac = 0; ac < WME_NUM_AC; ac++) { 2242 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2243 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2244 aifs = wmep->wmep_aifsn * slottime + 10; 2245 urtwn_write_4(sc, ac2reg[ac], 2246 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2247 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2248 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2249 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2250 } 2251 mutex_exit(&sc->sc_write_mtx); 2252 splx(s); 2253 } 2254 2255 static void 2256 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2257 { 2258 int pwdb; 2259 2260 URTWNHIST_FUNC(); 2261 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2262 2263 /* Convert antenna signal to percentage. */ 2264 if (rssi <= -100 || rssi >= 20) 2265 pwdb = 0; 2266 else if (rssi >= 0) 2267 pwdb = 100; 2268 else 2269 pwdb = 100 + rssi; 2270 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2271 if (rate <= 3) { 2272 /* CCK gain is smaller than OFDM/MCS gain. */ 2273 pwdb += 6; 2274 if (pwdb > 100) 2275 pwdb = 100; 2276 if (pwdb <= 14) 2277 pwdb -= 4; 2278 else if (pwdb <= 26) 2279 pwdb -= 8; 2280 else if (pwdb <= 34) 2281 pwdb -= 6; 2282 else if (pwdb <= 42) 2283 pwdb -= 2; 2284 } 2285 } 2286 if (sc->avg_pwdb == -1) /* Init. */ 2287 sc->avg_pwdb = pwdb; 2288 else if (sc->avg_pwdb < pwdb) 2289 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2290 else 2291 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2292 2293 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2294 rate, rssi, pwdb, sc->avg_pwdb); 2295 } 2296 2297 static int8_t 2298 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2299 { 2300 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2301 struct r92c_rx_phystat *phy; 2302 struct r92c_rx_cck *cck; 2303 uint8_t rpt; 2304 int8_t rssi; 2305 2306 URTWNHIST_FUNC(); 2307 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2308 2309 if (rate <= 3) { 2310 cck = (struct r92c_rx_cck *)physt; 2311 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2312 rpt = (cck->agc_rpt >> 5) & 0x3; 2313 rssi = (cck->agc_rpt & 0x1f) << 1; 2314 } else { 2315 rpt = (cck->agc_rpt >> 6) & 0x3; 2316 rssi = cck->agc_rpt & 0x3e; 2317 } 2318 rssi = cckoff[rpt] - rssi; 2319 } else { /* OFDM/HT. */ 2320 phy = (struct r92c_rx_phystat *)physt; 2321 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2322 } 2323 return rssi; 2324 } 2325 2326 static int8_t 2327 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2328 { 2329 struct r92c_rx_phystat *phy; 2330 struct r88e_rx_cck *cck; 2331 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2332 int8_t rssi; 2333 2334 URTWNHIST_FUNC(); 2335 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2336 2337 rssi = 0; 2338 if (rate <= 3) { 2339 cck = (struct r88e_rx_cck *)physt; 2340 cck_agc_rpt = cck->agc_rpt; 2341 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2342 vga_idx = cck_agc_rpt & 0x1f; 2343 switch (lna_idx) { 2344 case 7: 2345 if (vga_idx <= 27) 2346 rssi = -100 + 2* (27 - vga_idx); 2347 else 2348 rssi = -100; 2349 break; 2350 case 6: 2351 rssi = -48 + 2 * (2 - vga_idx); 2352 break; 2353 case 5: 2354 rssi = -42 + 2 * (7 - vga_idx); 2355 break; 2356 case 4: 2357 rssi = -36 + 2 * (7 - vga_idx); 2358 break; 2359 case 3: 2360 rssi = -24 + 2 * (7 - vga_idx); 2361 break; 2362 case 2: 2363 rssi = -12 + 2 * (5 - vga_idx); 2364 break; 2365 case 1: 2366 rssi = 8 - (2 * vga_idx); 2367 break; 2368 case 0: 2369 rssi = 14 - (2 * vga_idx); 2370 break; 2371 } 2372 rssi += 6; 2373 } else { /* OFDM/HT. */ 2374 phy = (struct r92c_rx_phystat *)physt; 2375 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2376 } 2377 return rssi; 2378 } 2379 2380 static void 2381 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2382 { 2383 struct ieee80211com *ic = &sc->sc_ic; 2384 struct ifnet *ifp = ic->ic_ifp; 2385 struct ieee80211_frame *wh; 2386 struct ieee80211_node *ni; 2387 struct r92c_rx_desc_usb *stat; 2388 uint32_t rxdw0, rxdw3; 2389 struct mbuf *m; 2390 uint8_t rate; 2391 int8_t rssi = 0; 2392 int s, infosz; 2393 2394 URTWNHIST_FUNC(); 2395 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2396 2397 stat = (struct r92c_rx_desc_usb *)buf; 2398 rxdw0 = le32toh(stat->rxdw0); 2399 rxdw3 = le32toh(stat->rxdw3); 2400 2401 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2402 /* 2403 * This should not happen since we setup our Rx filter 2404 * to not receive these frames. 2405 */ 2406 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2407 if_statinc(ifp, if_ierrors); 2408 return; 2409 } 2410 /* 2411 * XXX: This will drop most control packets. Do we really 2412 * want this in IEEE80211_M_MONITOR mode? 2413 */ 2414 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2415 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2416 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2417 ic->ic_stats.is_rx_tooshort++; 2418 if_statinc(ifp, if_ierrors); 2419 return; 2420 } 2421 if (__predict_false(pktlen > MCLBYTES)) { 2422 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2423 if_statinc(ifp, if_ierrors); 2424 return; 2425 } 2426 2427 rate = MS(rxdw3, R92C_RXDW3_RATE); 2428 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2429 2430 /* Get RSSI from PHY status descriptor if present. */ 2431 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2432 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2433 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2434 else 2435 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2436 /* Update our average RSSI. */ 2437 urtwn_update_avgrssi(sc, rate, rssi); 2438 } 2439 2440 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2441 pktlen, rate, infosz, rssi); 2442 2443 MGETHDR(m, M_DONTWAIT, MT_DATA); 2444 if (__predict_false(m == NULL)) { 2445 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2446 ic->ic_stats.is_rx_nobuf++; 2447 if_statinc(ifp, if_ierrors); 2448 return; 2449 } 2450 if (pktlen > (int)MHLEN) { 2451 MCLGET(m, M_DONTWAIT); 2452 if (__predict_false(!(m->m_flags & M_EXT))) { 2453 aprint_error_dev(sc->sc_dev, 2454 "couldn't allocate rx mbuf cluster\n"); 2455 m_freem(m); 2456 ic->ic_stats.is_rx_nobuf++; 2457 if_statinc(ifp, if_ierrors); 2458 return; 2459 } 2460 } 2461 2462 /* Finalize mbuf. */ 2463 m_set_rcvif(m, ifp); 2464 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2465 memcpy(mtod(m, uint8_t *), wh, pktlen); 2466 m->m_pkthdr.len = m->m_len = pktlen; 2467 2468 s = splnet(); 2469 if (__predict_false(sc->sc_drvbpf != NULL)) { 2470 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2471 2472 tap->wr_flags = 0; 2473 if (!(rxdw3 & R92C_RXDW3_HT)) { 2474 switch (rate) { 2475 /* CCK. */ 2476 case 0: tap->wr_rate = 2; break; 2477 case 1: tap->wr_rate = 4; break; 2478 case 2: tap->wr_rate = 11; break; 2479 case 3: tap->wr_rate = 22; break; 2480 /* OFDM. */ 2481 case 4: tap->wr_rate = 12; break; 2482 case 5: tap->wr_rate = 18; break; 2483 case 6: tap->wr_rate = 24; break; 2484 case 7: tap->wr_rate = 36; break; 2485 case 8: tap->wr_rate = 48; break; 2486 case 9: tap->wr_rate = 72; break; 2487 case 10: tap->wr_rate = 96; break; 2488 case 11: tap->wr_rate = 108; break; 2489 } 2490 } else if (rate >= 12) { /* MCS0~15. */ 2491 /* Bit 7 set means HT MCS instead of rate. */ 2492 tap->wr_rate = 0x80 | (rate - 12); 2493 } 2494 tap->wr_dbm_antsignal = rssi; 2495 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2496 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2497 2498 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2499 } 2500 2501 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2502 2503 /* push the frame up to the 802.11 stack */ 2504 ieee80211_input(ic, m, ni, rssi, 0); 2505 2506 /* Node is no longer needed. */ 2507 ieee80211_free_node(ni); 2508 2509 splx(s); 2510 } 2511 2512 static void 2513 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2514 { 2515 struct urtwn_rx_data *data = priv; 2516 struct urtwn_softc *sc = data->sc; 2517 struct r92c_rx_desc_usb *stat; 2518 size_t pidx = data->pidx; 2519 uint32_t rxdw0; 2520 uint8_t *buf; 2521 int len, totlen, pktlen, infosz, npkts; 2522 2523 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2524 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2525 2526 mutex_enter(&sc->sc_rx_mtx); 2527 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2528 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2529 /* Put this Rx buffer back to our free list. */ 2530 mutex_exit(&sc->sc_rx_mtx); 2531 2532 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2533 if (status == USBD_STALLED) 2534 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2535 else if (status != USBD_CANCELLED) 2536 goto resubmit; 2537 return; 2538 } 2539 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2540 2541 if (__predict_false(len < (int)sizeof(*stat))) { 2542 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2543 goto resubmit; 2544 } 2545 buf = data->buf; 2546 2547 /* Get the number of encapsulated frames. */ 2548 stat = (struct r92c_rx_desc_usb *)buf; 2549 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2550 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2551 else 2552 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2553 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2554 2555 if (npkts != 0) 2556 rnd_add_uint32(&sc->rnd_source, npkts); 2557 2558 /* Process all of them. */ 2559 while (npkts-- > 0) { 2560 if (__predict_false(len < (int)sizeof(*stat))) { 2561 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2562 len, 0, 0, 0); 2563 break; 2564 } 2565 stat = (struct r92c_rx_desc_usb *)buf; 2566 rxdw0 = le32toh(stat->rxdw0); 2567 2568 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2569 if (__predict_false(pktlen == 0)) { 2570 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2571 break; 2572 } 2573 2574 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2575 2576 /* Make sure everything fits in xfer. */ 2577 totlen = sizeof(*stat) + infosz + pktlen; 2578 if (__predict_false(totlen > len)) { 2579 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2580 (int)sizeof(*stat), infosz, pktlen, len); 2581 break; 2582 } 2583 2584 /* Process 802.11 frame. */ 2585 urtwn_rx_frame(sc, buf, pktlen); 2586 2587 /* Next chunk is 128-byte aligned. */ 2588 totlen = roundup2(totlen, 128); 2589 buf += totlen; 2590 len -= totlen; 2591 } 2592 2593 resubmit: 2594 /* Setup a new transfer. */ 2595 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2596 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2597 (void)usbd_transfer(xfer); 2598 } 2599 2600 static void 2601 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2602 { 2603 size_t pidx = data->pidx; 2604 2605 mutex_enter(&sc->sc_tx_mtx); 2606 /* Put this Tx buffer back to our free list. */ 2607 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2608 mutex_exit(&sc->sc_tx_mtx); 2609 } 2610 2611 static void 2612 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2613 { 2614 struct urtwn_tx_data *data = priv; 2615 struct urtwn_softc *sc = data->sc; 2616 struct ifnet *ifp = &sc->sc_if; 2617 size_t pidx = data->pidx; 2618 int s; 2619 2620 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2621 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2622 2623 urtwn_put_tx_data(sc, data); 2624 2625 s = splnet(); 2626 sc->tx_timer = 0; 2627 ifp->if_flags &= ~IFF_OACTIVE; 2628 2629 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2630 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2631 if (status == USBD_STALLED) { 2632 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2633 usbd_clear_endpoint_stall_async(pipe); 2634 } 2635 device_printf(sc->sc_dev, "transmit failed, %s\n", 2636 usbd_errstr(status)); 2637 if_statinc(ifp, if_oerrors); 2638 } 2639 splx(s); 2640 return; 2641 } 2642 2643 if_statinc(ifp, if_opackets); 2644 urtwn_start(ifp); 2645 splx(s); 2646 2647 } 2648 2649 static int 2650 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2651 struct urtwn_tx_data *data) 2652 { 2653 struct ieee80211com *ic = &sc->sc_ic; 2654 struct ieee80211_frame *wh; 2655 struct ieee80211_key *k = NULL; 2656 struct r92c_tx_desc_usb *txd; 2657 size_t i, padsize, xferlen, txd_len; 2658 uint16_t seq, sum; 2659 uint8_t raid, type, tid; 2660 int s, hasqos, error; 2661 2662 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2663 2664 wh = mtod(m, struct ieee80211_frame *); 2665 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2666 txd_len = sizeof(*txd); 2667 2668 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2669 txd_len = 32; 2670 2671 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2672 k = ieee80211_crypto_encap(ic, ni, m); 2673 if (k == NULL) { 2674 urtwn_put_tx_data(sc, data); 2675 m_free(m); 2676 return ENOBUFS; 2677 } 2678 2679 /* packet header may have moved, reset our local pointer */ 2680 wh = mtod(m, struct ieee80211_frame *); 2681 } 2682 2683 if (__predict_false(sc->sc_drvbpf != NULL)) { 2684 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2685 2686 tap->wt_flags = 0; 2687 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2688 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2689 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2690 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2691 2692 /* XXX: set tap->wt_rate? */ 2693 2694 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2695 } 2696 2697 /* non-qos data frames */ 2698 tid = R92C_TXDW1_QSEL_BE; 2699 if ((hasqos = ieee80211_has_qos(wh))) { 2700 /* data frames in 11n mode */ 2701 struct ieee80211_qosframe *qwh = (void *)wh; 2702 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2703 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2704 tid = R92C_TXDW1_QSEL_MGNT; 2705 } 2706 2707 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2708 padsize = 8; 2709 else 2710 padsize = 0; 2711 2712 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2713 padsize = 0; 2714 2715 /* Fill Tx descriptor. */ 2716 txd = (struct r92c_tx_desc_usb *)data->buf; 2717 memset(txd, 0, txd_len + padsize); 2718 2719 txd->txdw0 |= htole32( 2720 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2721 SM(R92C_TXDW0_OFFSET, txd_len)); 2722 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2723 txd->txdw0 |= htole32( 2724 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2725 } 2726 2727 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2728 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2729 2730 /* fix pad field */ 2731 if (padsize > 0) { 2732 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2733 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2734 } 2735 2736 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2737 type == IEEE80211_FC0_TYPE_DATA) { 2738 if (ic->ic_curmode == IEEE80211_MODE_11B) 2739 raid = R92C_RAID_11B; 2740 else 2741 raid = R92C_RAID_11BG; 2742 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2743 tid, raid, 0, 0); 2744 2745 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2746 txd->txdw1 |= htole32( 2747 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2748 SM(R92C_TXDW1_QSEL, tid) | 2749 SM(R92C_TXDW1_RAID, raid) | 2750 R92C_TXDW1_AGGBK); 2751 } else 2752 txd->txdw1 |= htole32( 2753 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2754 SM(R92C_TXDW1_QSEL, tid) | 2755 SM(R92C_TXDW1_RAID, raid) | 2756 R92C_TXDW1_AGGBK); 2757 2758 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2759 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2760 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2761 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2762 2763 if (hasqos) { 2764 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2765 } 2766 2767 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2768 /* for 11g */ 2769 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2770 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2771 R92C_TXDW4_HWRTSEN); 2772 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2773 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2774 R92C_TXDW4_HWRTSEN); 2775 } 2776 } 2777 /* Send RTS at OFDM24. */ 2778 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2779 txd->txdw5 |= htole32(0x0001ff00); 2780 /* Send data at OFDM54. */ 2781 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2782 txd->txdw5 |= htole32(0x13 & 0x3f); 2783 else 2784 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2785 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2786 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2787 txd->txdw1 |= htole32( 2788 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2789 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2790 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2791 2792 /* Force CCK1. */ 2793 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2794 /* Use 1Mbps */ 2795 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2796 } else { 2797 /* broadcast or multicast packets */ 2798 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2799 txd->txdw1 |= htole32( 2800 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2801 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2802 2803 /* Force CCK1. */ 2804 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2805 /* Use 1Mbps */ 2806 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2807 } 2808 /* Set sequence number */ 2809 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2810 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2811 txd->txdseq |= htole16(seq); 2812 2813 if (!hasqos) { 2814 /* Use HW sequence numbering for non-QoS frames. */ 2815 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2816 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2817 } 2818 } else { 2819 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2820 R92E_HWSEQ_SHIFT); 2821 if (!hasqos) { 2822 /* Use HW sequence numbering for non-QoS frames. */ 2823 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2824 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2825 } 2826 } 2827 2828 /* Compute Tx descriptor checksum. */ 2829 sum = 0; 2830 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2831 sum ^= ((uint16_t *)txd)[i]; 2832 txd->txdsum = sum; /* NB: already little endian. */ 2833 2834 xferlen = txd_len + m->m_pkthdr.len + padsize; 2835 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2836 2837 s = splnet(); 2838 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2839 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2840 urtwn_txeof); 2841 error = usbd_transfer(data->xfer); 2842 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2843 error != USBD_IN_PROGRESS)) { 2844 splx(s); 2845 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2846 return error; 2847 } 2848 splx(s); 2849 return 0; 2850 } 2851 2852 struct urtwn_tx_data * 2853 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2854 { 2855 struct urtwn_tx_data *data = NULL; 2856 2857 mutex_enter(&sc->sc_tx_mtx); 2858 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2859 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2860 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2861 } 2862 mutex_exit(&sc->sc_tx_mtx); 2863 2864 return data; 2865 } 2866 2867 static void 2868 urtwn_start(struct ifnet *ifp) 2869 { 2870 struct urtwn_softc *sc = ifp->if_softc; 2871 struct ieee80211com *ic = &sc->sc_ic; 2872 struct urtwn_tx_data *data; 2873 struct ether_header *eh; 2874 struct ieee80211_node *ni; 2875 struct mbuf *m; 2876 2877 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2878 2879 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2880 return; 2881 2882 data = NULL; 2883 for (;;) { 2884 /* Send pending management frames first. */ 2885 IF_POLL(&ic->ic_mgtq, m); 2886 if (m != NULL) { 2887 /* Use AC_VO for management frames. */ 2888 2889 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2890 2891 if (data == NULL) { 2892 ifp->if_flags |= IFF_OACTIVE; 2893 DPRINTFN(DBG_TX, "empty tx_free_list", 2894 0, 0, 0, 0); 2895 return; 2896 } 2897 IF_DEQUEUE(&ic->ic_mgtq, m); 2898 ni = M_GETCTX(m, struct ieee80211_node *); 2899 M_CLEARCTX(m); 2900 goto sendit; 2901 } 2902 if (ic->ic_state != IEEE80211_S_RUN) 2903 break; 2904 2905 /* Encapsulate and send data frames. */ 2906 IFQ_POLL(&ifp->if_snd, m); 2907 if (m == NULL) 2908 break; 2909 2910 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2911 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2912 uint8_t qid = WME_AC_BE; 2913 if (ieee80211_has_qos(wh)) { 2914 /* data frames in 11n mode */ 2915 struct ieee80211_qosframe *qwh = (void *)wh; 2916 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2917 qid = TID_TO_WME_AC(tid); 2918 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2919 qid = WME_AC_VO; 2920 } 2921 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2922 2923 if (data == NULL) { 2924 ifp->if_flags |= IFF_OACTIVE; 2925 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2926 return; 2927 } 2928 IFQ_DEQUEUE(&ifp->if_snd, m); 2929 2930 if (m->m_len < (int)sizeof(*eh) && 2931 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2932 device_printf(sc->sc_dev, "m_pullup failed\n"); 2933 if_statinc(ifp, if_oerrors); 2934 urtwn_put_tx_data(sc, data); 2935 m_freem(m); 2936 continue; 2937 } 2938 eh = mtod(m, struct ether_header *); 2939 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2940 if (ni == NULL) { 2941 device_printf(sc->sc_dev, 2942 "unable to find transmit node\n"); 2943 if_statinc(ifp, if_oerrors); 2944 urtwn_put_tx_data(sc, data); 2945 m_freem(m); 2946 continue; 2947 } 2948 2949 bpf_mtap(ifp, m, BPF_D_OUT); 2950 2951 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2952 ieee80211_free_node(ni); 2953 device_printf(sc->sc_dev, 2954 "unable to encapsulate packet\n"); 2955 if_statinc(ifp, if_oerrors); 2956 urtwn_put_tx_data(sc, data); 2957 m_freem(m); 2958 continue; 2959 } 2960 sendit: 2961 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2962 2963 if (urtwn_tx(sc, m, ni, data) != 0) { 2964 m_freem(m); 2965 ieee80211_free_node(ni); 2966 device_printf(sc->sc_dev, 2967 "unable to transmit packet\n"); 2968 if_statinc(ifp, if_oerrors); 2969 continue; 2970 } 2971 m_freem(m); 2972 ieee80211_free_node(ni); 2973 sc->tx_timer = 5; 2974 ifp->if_timer = 1; 2975 } 2976 } 2977 2978 static void 2979 urtwn_watchdog(struct ifnet *ifp) 2980 { 2981 struct urtwn_softc *sc = ifp->if_softc; 2982 2983 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2984 2985 ifp->if_timer = 0; 2986 2987 if (sc->tx_timer > 0) { 2988 if (--sc->tx_timer == 0) { 2989 device_printf(sc->sc_dev, "device timeout\n"); 2990 /* urtwn_init(ifp); XXX needs a process context! */ 2991 if_statinc(ifp, if_oerrors); 2992 return; 2993 } 2994 ifp->if_timer = 1; 2995 } 2996 ieee80211_watchdog(&sc->sc_ic); 2997 } 2998 2999 static int 3000 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3001 { 3002 struct urtwn_softc *sc = ifp->if_softc; 3003 struct ieee80211com *ic = &sc->sc_ic; 3004 int s, error = 0; 3005 3006 URTWNHIST_FUNC(); 3007 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3008 0, 0); 3009 3010 s = splnet(); 3011 3012 switch (cmd) { 3013 case SIOCSIFFLAGS: 3014 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3015 break; 3016 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3017 case IFF_UP | IFF_RUNNING: 3018 break; 3019 case IFF_UP: 3020 urtwn_init(ifp); 3021 break; 3022 case IFF_RUNNING: 3023 urtwn_stop(ifp, 1); 3024 break; 3025 case 0: 3026 break; 3027 } 3028 break; 3029 3030 case SIOCADDMULTI: 3031 case SIOCDELMULTI: 3032 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3033 /* setup multicast filter, etc */ 3034 error = 0; 3035 } 3036 break; 3037 3038 case SIOCS80211CHANNEL: 3039 /* 3040 * This allows for fast channel switching in monitor mode 3041 * (used by kismet). In IBSS mode, we must explicitly reset 3042 * the interface to generate a new beacon frame. 3043 */ 3044 error = ieee80211_ioctl(ic, cmd, data); 3045 if (error == ENETRESET && 3046 ic->ic_opmode == IEEE80211_M_MONITOR) { 3047 urtwn_set_chan(sc, ic->ic_curchan, 3048 IEEE80211_HTINFO_2NDCHAN_NONE); 3049 error = 0; 3050 } 3051 break; 3052 3053 default: 3054 error = ieee80211_ioctl(ic, cmd, data); 3055 break; 3056 } 3057 if (error == ENETRESET) { 3058 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3059 (IFF_UP | IFF_RUNNING) && 3060 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3061 urtwn_init(ifp); 3062 } 3063 error = 0; 3064 } 3065 3066 splx(s); 3067 3068 return error; 3069 } 3070 3071 static __inline int 3072 urtwn_power_on(struct urtwn_softc *sc) 3073 { 3074 3075 return sc->sc_power_on(sc); 3076 } 3077 3078 static int 3079 urtwn_r92c_power_on(struct urtwn_softc *sc) 3080 { 3081 uint32_t reg; 3082 int ntries; 3083 3084 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3085 3086 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3087 3088 /* Wait for autoload done bit. */ 3089 for (ntries = 0; ntries < 1000; ntries++) { 3090 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3091 break; 3092 DELAY(5); 3093 } 3094 if (ntries == 1000) { 3095 aprint_error_dev(sc->sc_dev, 3096 "timeout waiting for chip autoload\n"); 3097 return ETIMEDOUT; 3098 } 3099 3100 /* Unlock ISO/CLK/Power control register. */ 3101 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3102 DELAY(5); 3103 /* Move SPS into PWM mode. */ 3104 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3105 DELAY(5); 3106 3107 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3108 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3109 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3110 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3111 DELAY(100); 3112 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3113 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3114 ~R92C_SYS_ISO_CTRL_MD2PP); 3115 } 3116 3117 /* Auto enable WLAN. */ 3118 urtwn_write_2(sc, R92C_APS_FSMCO, 3119 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3120 for (ntries = 0; ntries < 1000; ntries++) { 3121 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3122 R92C_APS_FSMCO_APFM_ONMAC)) 3123 break; 3124 DELAY(100); 3125 } 3126 if (ntries == 1000) { 3127 aprint_error_dev(sc->sc_dev, 3128 "timeout waiting for MAC auto ON\n"); 3129 return ETIMEDOUT; 3130 } 3131 3132 /* Enable radio, GPIO and LED functions. */ 3133 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3134 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3135 urtwn_write_2(sc, R92C_APS_FSMCO, 3136 R92C_APS_FSMCO_AFSM_HSUS | 3137 R92C_APS_FSMCO_PDN_EN | 3138 R92C_APS_FSMCO_PFM_ALDN); 3139 3140 /* Release RF digital isolation. */ 3141 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3142 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3143 3144 /* Initialize MAC. */ 3145 urtwn_write_1(sc, R92C_APSD_CTRL, 3146 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3147 for (ntries = 0; ntries < 200; ntries++) { 3148 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3149 R92C_APSD_CTRL_OFF_STATUS)) 3150 break; 3151 DELAY(5); 3152 } 3153 if (ntries == 200) { 3154 aprint_error_dev(sc->sc_dev, 3155 "timeout waiting for MAC initialization\n"); 3156 return ETIMEDOUT; 3157 } 3158 3159 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3160 reg = urtwn_read_2(sc, R92C_CR); 3161 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3162 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3163 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3164 R92C_CR_ENSEC; 3165 urtwn_write_2(sc, R92C_CR, reg); 3166 3167 urtwn_write_1(sc, 0xfe10, 0x19); 3168 3169 urtwn_delay_ms(sc, 1); 3170 3171 return 0; 3172 } 3173 3174 static int 3175 urtwn_r92e_power_on(struct urtwn_softc *sc) 3176 { 3177 uint32_t reg; 3178 uint32_t val; 3179 int ntries; 3180 3181 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3182 3183 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3184 3185 /* Enable radio, GPIO and LED functions. */ 3186 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3187 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3188 urtwn_write_2(sc, R92C_APS_FSMCO, 3189 R92C_APS_FSMCO_AFSM_HSUS | 3190 R92C_APS_FSMCO_PDN_EN | 3191 R92C_APS_FSMCO_PFM_ALDN); 3192 3193 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3194 /* LDO. */ 3195 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3196 } 3197 else { 3198 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3199 R92C_SYS_SWR_CTRL2) & 0xffff); 3200 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3201 } 3202 3203 for (ntries = 0; ntries < 2; ntries++) { 3204 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3205 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3206 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3207 R92C_AFE_CTRL4)); 3208 } 3209 3210 /* Reset BB. */ 3211 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3212 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3213 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3214 3215 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3216 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3217 3218 /* Disable HWPDN. */ 3219 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3220 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3221 3222 /* Disable WL suspend. */ 3223 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3224 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3225 R92C_APS_FSMCO_AFSM_HSUS)); 3226 3227 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3228 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3229 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3230 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3231 for (ntries = 0; ntries < 10000; ntries++) { 3232 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3233 R92C_APS_FSMCO_APFM_ONMAC; 3234 if (val == 0x0) 3235 break; 3236 DELAY(10); 3237 } 3238 if (ntries == 10000) { 3239 aprint_error_dev(sc->sc_dev, 3240 "timeout waiting for chip power up\n"); 3241 return ETIMEDOUT; 3242 } 3243 3244 urtwn_write_2(sc, R92C_CR, 0x00); 3245 reg = urtwn_read_2(sc, R92C_CR); 3246 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3247 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3248 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3249 urtwn_write_2(sc, R92C_CR, reg); 3250 3251 return 0; 3252 } 3253 3254 static int 3255 urtwn_r88e_power_on(struct urtwn_softc *sc) 3256 { 3257 uint32_t reg; 3258 uint8_t val; 3259 int ntries; 3260 3261 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3262 3263 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3264 3265 /* Wait for power ready bit. */ 3266 for (ntries = 0; ntries < 5000; ntries++) { 3267 val = urtwn_read_1(sc, 0x6) & 0x2; 3268 if (val == 0x2) 3269 break; 3270 DELAY(10); 3271 } 3272 if (ntries == 5000) { 3273 aprint_error_dev(sc->sc_dev, 3274 "timeout waiting for chip power up\n"); 3275 return ETIMEDOUT; 3276 } 3277 3278 /* Reset BB. */ 3279 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3280 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3281 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3282 3283 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3284 3285 /* Disable HWPDN. */ 3286 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3287 3288 /* Disable WL suspend. */ 3289 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3290 3291 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3292 for (ntries = 0; ntries < 5000; ntries++) { 3293 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3294 break; 3295 DELAY(10); 3296 } 3297 if (ntries == 5000) 3298 return ETIMEDOUT; 3299 3300 /* Enable LDO normal mode. */ 3301 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3302 3303 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3304 urtwn_write_2(sc, R92C_CR, 0); 3305 reg = urtwn_read_2(sc, R92C_CR); 3306 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3307 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3308 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3309 urtwn_write_2(sc, R92C_CR, reg); 3310 3311 return 0; 3312 } 3313 3314 static int __noinline 3315 urtwn_llt_init(struct urtwn_softc *sc) 3316 { 3317 size_t i, page_count, pktbuf_count; 3318 uint32_t val; 3319 int error; 3320 3321 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3322 3323 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3324 3325 if (sc->chip & URTWN_CHIP_88E) 3326 page_count = R88E_TX_PAGE_COUNT; 3327 else if (sc->chip & URTWN_CHIP_92EU) 3328 page_count = R92E_TX_PAGE_COUNT; 3329 else 3330 page_count = R92C_TX_PAGE_COUNT; 3331 if (sc->chip & URTWN_CHIP_88E) 3332 pktbuf_count = R88E_TXPKTBUF_COUNT; 3333 else if (sc->chip & URTWN_CHIP_92EU) 3334 pktbuf_count = R88E_TXPKTBUF_COUNT; 3335 else 3336 pktbuf_count = R92C_TXPKTBUF_COUNT; 3337 3338 if (sc->chip & URTWN_CHIP_92EU) { 3339 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3340 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3341 DELAY(100); 3342 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3343 if (val & R92E_AUTO_LLT_EN) 3344 return EIO; 3345 return 0; 3346 } 3347 3348 /* Reserve pages [0; page_count]. */ 3349 for (i = 0; i < page_count; i++) { 3350 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3351 return error; 3352 } 3353 /* NB: 0xff indicates end-of-list. */ 3354 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3355 return error; 3356 /* 3357 * Use pages [page_count + 1; pktbuf_count - 1] 3358 * as ring buffer. 3359 */ 3360 for (++i; i < pktbuf_count - 1; i++) { 3361 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3362 return error; 3363 } 3364 /* Make the last page point to the beginning of the ring buffer. */ 3365 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3366 return error; 3367 } 3368 3369 static void 3370 urtwn_fw_reset(struct urtwn_softc *sc) 3371 { 3372 uint16_t reg; 3373 int ntries; 3374 3375 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3376 3377 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3378 3379 /* Tell 8051 to reset itself. */ 3380 mutex_enter(&sc->sc_fwcmd_mtx); 3381 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3382 sc->fwcur = 0; 3383 mutex_exit(&sc->sc_fwcmd_mtx); 3384 3385 /* Wait until 8051 resets by itself. */ 3386 for (ntries = 0; ntries < 100; ntries++) { 3387 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3388 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3389 return; 3390 DELAY(50); 3391 } 3392 /* Force 8051 reset. */ 3393 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3394 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3395 } 3396 3397 static void 3398 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3399 { 3400 uint16_t reg; 3401 3402 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3403 3404 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3405 3406 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3407 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3408 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3409 } 3410 DELAY(50); 3411 3412 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3413 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3414 DELAY(50); 3415 3416 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3417 DELAY(50); 3418 3419 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3420 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3421 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3422 } 3423 DELAY(50); 3424 3425 mutex_enter(&sc->sc_fwcmd_mtx); 3426 /* Init firmware commands ring. */ 3427 sc->fwcur = 0; 3428 mutex_exit(&sc->sc_fwcmd_mtx); 3429 3430 } 3431 3432 static int 3433 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3434 { 3435 uint32_t reg; 3436 int off, mlen, error = 0; 3437 3438 URTWNHIST_FUNC(); 3439 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3440 page, (uintptr_t)buf, len, 0); 3441 3442 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3443 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3444 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3445 3446 off = R92C_FW_START_ADDR; 3447 while (len > 0) { 3448 if (len > 196) 3449 mlen = 196; 3450 else if (len > 4) 3451 mlen = 4; 3452 else 3453 mlen = 1; 3454 error = urtwn_write_region(sc, off, buf, mlen); 3455 if (error != 0) 3456 break; 3457 off += mlen; 3458 buf += mlen; 3459 len -= mlen; 3460 } 3461 return error; 3462 } 3463 3464 static int __noinline 3465 urtwn_load_firmware(struct urtwn_softc *sc) 3466 { 3467 firmware_handle_t fwh; 3468 const struct r92c_fw_hdr *hdr; 3469 const char *name; 3470 u_char *fw, *ptr; 3471 size_t len; 3472 uint32_t reg; 3473 int mlen, ntries, page, error; 3474 3475 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3476 3477 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3478 3479 /* Read firmware image from the filesystem. */ 3480 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3481 name = "rtl8188eufw.bin"; 3482 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3483 name = "rtl8192eefw.bin"; 3484 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3485 URTWN_CHIP_UMC_A_CUT) 3486 name = "rtl8192cfwU.bin"; 3487 else 3488 name = "rtl8192cfw.bin"; 3489 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3490 aprint_error_dev(sc->sc_dev, 3491 "failed load firmware of file %s (error %d)\n", name, 3492 error); 3493 return error; 3494 } 3495 const size_t fwlen = len = firmware_get_size(fwh); 3496 fw = firmware_malloc(len); 3497 if (fw == NULL) { 3498 aprint_error_dev(sc->sc_dev, 3499 "failed to allocate firmware memory\n"); 3500 firmware_close(fwh); 3501 return ENOMEM; 3502 } 3503 error = firmware_read(fwh, 0, fw, len); 3504 firmware_close(fwh); 3505 if (error != 0) { 3506 aprint_error_dev(sc->sc_dev, 3507 "failed to read firmware (error %d)\n", error); 3508 firmware_free(fw, fwlen); 3509 return error; 3510 } 3511 3512 len = fwlen; 3513 ptr = fw; 3514 hdr = (const struct r92c_fw_hdr *)ptr; 3515 /* Check if there is a valid FW header and skip it. */ 3516 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3517 (le16toh(hdr->signature) >> 4) == 0x88e || 3518 (le16toh(hdr->signature) >> 4) == 0x92e || 3519 (le16toh(hdr->signature) >> 4) == 0x92c) { 3520 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3521 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3522 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3523 hdr->month, hdr->date, hdr->hour, hdr->minute); 3524 ptr += sizeof(*hdr); 3525 len -= sizeof(*hdr); 3526 } 3527 3528 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3529 /* Reset MCU ready status */ 3530 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3531 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3532 ISSET(sc->chip, URTWN_CHIP_92EU)) 3533 urtwn_r88e_fw_reset(sc); 3534 else 3535 urtwn_fw_reset(sc); 3536 } 3537 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3538 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3539 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3540 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3541 R92C_SYS_FUNC_EN_CPUEN); 3542 } 3543 3544 /* download enabled */ 3545 urtwn_write_1(sc, R92C_MCUFWDL, 3546 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3547 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3548 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3549 3550 /* Reset the FWDL checksum. */ 3551 urtwn_write_1(sc, R92C_MCUFWDL, 3552 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3553 3554 DELAY(50); 3555 /* download firmware */ 3556 for (page = 0; len > 0; page++) { 3557 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3558 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3559 if (error != 0) { 3560 aprint_error_dev(sc->sc_dev, 3561 "could not load firmware page %d\n", page); 3562 goto fail; 3563 } 3564 ptr += mlen; 3565 len -= mlen; 3566 } 3567 3568 /* download disable */ 3569 urtwn_write_1(sc, R92C_MCUFWDL, 3570 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3571 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3572 3573 /* Wait for checksum report. */ 3574 for (ntries = 0; ntries < 1000; ntries++) { 3575 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3576 break; 3577 DELAY(5); 3578 } 3579 if (ntries == 1000) { 3580 aprint_error_dev(sc->sc_dev, 3581 "timeout waiting for checksum report\n"); 3582 error = ETIMEDOUT; 3583 goto fail; 3584 } 3585 3586 /* Wait for firmware readiness. */ 3587 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3588 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3589 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3590 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3591 ISSET(sc->chip, URTWN_CHIP_92EU)) 3592 urtwn_r88e_fw_reset(sc); 3593 for (ntries = 0; ntries < 6000; ntries++) { 3594 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3595 break; 3596 DELAY(5); 3597 } 3598 if (ntries == 6000) { 3599 aprint_error_dev(sc->sc_dev, 3600 "timeout waiting for firmware readiness\n"); 3601 error = ETIMEDOUT; 3602 goto fail; 3603 } 3604 fail: 3605 firmware_free(fw, fwlen); 3606 return error; 3607 } 3608 3609 static __inline int 3610 urtwn_dma_init(struct urtwn_softc *sc) 3611 { 3612 3613 return sc->sc_dma_init(sc); 3614 } 3615 3616 static int 3617 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3618 { 3619 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3620 uint32_t reg; 3621 int error; 3622 3623 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3624 3625 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3626 3627 /* Initialize LLT table. */ 3628 error = urtwn_llt_init(sc); 3629 if (error != 0) 3630 return error; 3631 3632 /* Get Tx queues to USB endpoints mapping. */ 3633 hashq = hasnq = haslq = 0; 3634 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3635 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3636 if (MS(reg, R92C_USB_EP_HQ) != 0) 3637 hashq = 1; 3638 if (MS(reg, R92C_USB_EP_NQ) != 0) 3639 hasnq = 1; 3640 if (MS(reg, R92C_USB_EP_LQ) != 0) 3641 haslq = 1; 3642 nqueues = hashq + hasnq + haslq; 3643 if (nqueues == 0) 3644 return EIO; 3645 /* Get the number of pages for each queue. */ 3646 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3647 /* The remaining pages are assigned to the high priority queue. */ 3648 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3649 3650 /* Set number of pages for normal priority queue. */ 3651 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3652 urtwn_write_4(sc, R92C_RQPN, 3653 /* Set number of pages for public queue. */ 3654 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3655 /* Set number of pages for high priority queue. */ 3656 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3657 /* Set number of pages for low priority queue. */ 3658 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3659 /* Load values. */ 3660 R92C_RQPN_LD); 3661 3662 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3663 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3664 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3665 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3666 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3667 3668 /* Set queue to USB pipe mapping. */ 3669 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3670 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3671 if (nqueues == 1) { 3672 if (hashq) { 3673 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3674 } else if (hasnq) { 3675 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3676 } else { 3677 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3678 } 3679 } else if (nqueues == 2) { 3680 /* All 2-endpoints configs have a high priority queue. */ 3681 if (!hashq) { 3682 return EIO; 3683 } 3684 if (hasnq) { 3685 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3686 } else { 3687 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3688 } 3689 } else { 3690 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3691 } 3692 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3693 3694 /* Set Tx/Rx transfer page boundary. */ 3695 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3696 3697 /* Set Tx/Rx transfer page size. */ 3698 urtwn_write_1(sc, R92C_PBP, 3699 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3700 return 0; 3701 } 3702 3703 static int 3704 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3705 { 3706 usb_interface_descriptor_t *id; 3707 uint32_t reg; 3708 int nqueues; 3709 int error; 3710 3711 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3712 3713 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3714 3715 /* Initialize LLT table. */ 3716 error = urtwn_llt_init(sc); 3717 if (error != 0) 3718 return error; 3719 3720 /* Get Tx queues to USB endpoints mapping. */ 3721 id = usbd_get_interface_descriptor(sc->sc_iface); 3722 nqueues = id->bNumEndpoints - 1; 3723 if (nqueues == 0) 3724 return EIO; 3725 3726 /* Set number of pages for normal priority queue. */ 3727 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3728 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3729 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3730 3731 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3732 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3733 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3734 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3735 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3736 3737 /* Set queue to USB pipe mapping. */ 3738 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3739 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3740 if (nqueues == 1) 3741 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3742 else if (nqueues == 2) 3743 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3744 else 3745 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3746 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3747 3748 /* Set Tx/Rx transfer page boundary. */ 3749 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3750 3751 /* Set Tx/Rx transfer page size. */ 3752 urtwn_write_1(sc, R92C_PBP, 3753 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3754 3755 return 0; 3756 } 3757 3758 static void __noinline 3759 urtwn_mac_init(struct urtwn_softc *sc) 3760 { 3761 size_t i; 3762 3763 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3764 3765 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3766 3767 /* Write MAC initialization values. */ 3768 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3769 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3770 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3771 rtl8188eu_mac[i].val); 3772 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3773 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3774 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3775 rtl8192eu_mac[i].val); 3776 } else { 3777 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3778 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3779 rtl8192cu_mac[i].val); 3780 } 3781 } 3782 3783 static void __noinline 3784 urtwn_bb_init(struct urtwn_softc *sc) 3785 { 3786 const struct rtwn_bb_prog *prog; 3787 uint32_t reg; 3788 uint8_t crystalcap; 3789 size_t i; 3790 3791 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3792 3793 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3794 3795 /* Enable BB and RF. */ 3796 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3797 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3798 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3799 R92C_SYS_FUNC_EN_DIO_RF); 3800 3801 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3802 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3803 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3804 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3805 } 3806 3807 urtwn_write_1(sc, R92C_RF_CTRL, 3808 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3809 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3810 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3811 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3812 3813 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3814 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3815 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3816 urtwn_write_1(sc, 0x15, 0xe9); 3817 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3818 } 3819 3820 /* Select BB programming based on board type. */ 3821 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3822 prog = &rtl8188eu_bb_prog; 3823 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3824 prog = &rtl8192eu_bb_prog; 3825 else if (!(sc->chip & URTWN_CHIP_92C)) { 3826 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3827 prog = &rtl8188ce_bb_prog; 3828 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3829 prog = &rtl8188ru_bb_prog; 3830 } else { 3831 prog = &rtl8188cu_bb_prog; 3832 } 3833 } else { 3834 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3835 prog = &rtl8192ce_bb_prog; 3836 } else { 3837 prog = &rtl8192cu_bb_prog; 3838 } 3839 } 3840 /* Write BB initialization values. */ 3841 for (i = 0; i < prog->count; i++) { 3842 /* additional delay depend on registers */ 3843 switch (prog->regs[i]) { 3844 case 0xfe: 3845 urtwn_delay_ms(sc, 50); 3846 break; 3847 case 0xfd: 3848 urtwn_delay_ms(sc, 5); 3849 break; 3850 case 0xfc: 3851 urtwn_delay_ms(sc, 1); 3852 break; 3853 case 0xfb: 3854 DELAY(50); 3855 break; 3856 case 0xfa: 3857 DELAY(5); 3858 break; 3859 case 0xf9: 3860 DELAY(1); 3861 break; 3862 } 3863 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3864 DELAY(1); 3865 } 3866 3867 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3868 /* 8192C 1T only configuration. */ 3869 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3870 reg = (reg & ~0x00000003) | 0x2; 3871 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3872 3873 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3874 reg = (reg & ~0x00300033) | 0x00200022; 3875 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3876 3877 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3878 reg = (reg & ~0xff000000) | (0x45 << 24); 3879 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3880 3881 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3882 reg = (reg & ~0x000000ff) | 0x23; 3883 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3884 3885 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3886 reg = (reg & ~0x00000030) | (1 << 4); 3887 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3888 3889 reg = urtwn_bb_read(sc, 0xe74); 3890 reg = (reg & ~0x0c000000) | (2 << 26); 3891 urtwn_bb_write(sc, 0xe74, reg); 3892 reg = urtwn_bb_read(sc, 0xe78); 3893 reg = (reg & ~0x0c000000) | (2 << 26); 3894 urtwn_bb_write(sc, 0xe78, reg); 3895 reg = urtwn_bb_read(sc, 0xe7c); 3896 reg = (reg & ~0x0c000000) | (2 << 26); 3897 urtwn_bb_write(sc, 0xe7c, reg); 3898 reg = urtwn_bb_read(sc, 0xe80); 3899 reg = (reg & ~0x0c000000) | (2 << 26); 3900 urtwn_bb_write(sc, 0xe80, reg); 3901 reg = urtwn_bb_read(sc, 0xe88); 3902 reg = (reg & ~0x0c000000) | (2 << 26); 3903 urtwn_bb_write(sc, 0xe88, reg); 3904 } 3905 3906 /* Write AGC values. */ 3907 for (i = 0; i < prog->agccount; i++) { 3908 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3909 DELAY(1); 3910 } 3911 3912 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3913 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3914 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3915 DELAY(1); 3916 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3917 DELAY(1); 3918 } 3919 3920 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3921 crystalcap = sc->r88e_rom[0xb9]; 3922 if (crystalcap == 0x00) 3923 crystalcap = 0x20; 3924 crystalcap &= 0x3f; 3925 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3926 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3927 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3928 crystalcap | crystalcap << 6)); 3929 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3930 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3931 crystalcap = sc->r88e_rom[0xb9]; 3932 if (crystalcap == 0xff) 3933 crystalcap = 0x20; 3934 crystalcap &= 0x3f; 3935 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3936 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3937 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3938 crystalcap | crystalcap << 6)); 3939 } else { 3940 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3941 R92C_HSSI_PARAM2_CCK_HIPWR) { 3942 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3943 } 3944 } 3945 } 3946 3947 static void __noinline 3948 urtwn_rf_init(struct urtwn_softc *sc) 3949 { 3950 const struct rtwn_rf_prog *prog; 3951 uint32_t reg, mask, saved; 3952 size_t i, j, idx; 3953 3954 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3955 3956 /* Select RF programming based on board type. */ 3957 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3958 prog = rtl8188eu_rf_prog; 3959 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3960 prog = rtl8192eu_rf_prog; 3961 else if (!(sc->chip & URTWN_CHIP_92C)) { 3962 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3963 prog = rtl8188ce_rf_prog; 3964 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3965 prog = rtl8188ru_rf_prog; 3966 } else { 3967 prog = rtl8188cu_rf_prog; 3968 } 3969 } else { 3970 prog = rtl8192ce_rf_prog; 3971 } 3972 3973 for (i = 0; i < sc->nrxchains; i++) { 3974 /* Save RF_ENV control type. */ 3975 idx = i / 2; 3976 mask = 0xffffU << ((i % 2) * 16); 3977 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3978 3979 /* Set RF_ENV enable. */ 3980 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3981 reg |= 0x100000; 3982 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3983 DELAY(50); 3984 3985 /* Set RF_ENV output high. */ 3986 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3987 reg |= 0x10; 3988 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3989 DELAY(50); 3990 3991 /* Set address and data lengths of RF registers. */ 3992 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3993 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3994 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3995 DELAY(50); 3996 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3997 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3998 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3999 DELAY(50); 4000 4001 /* Write RF initialization values for this chain. */ 4002 for (j = 0; j < prog[i].count; j++) { 4003 if (prog[i].regs[j] >= 0xf9 && 4004 prog[i].regs[j] <= 0xfe) { 4005 /* 4006 * These are fake RF registers offsets that 4007 * indicate a delay is required. 4008 */ 4009 urtwn_delay_ms(sc, 50); 4010 continue; 4011 } 4012 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4013 DELAY(5); 4014 } 4015 4016 /* Restore RF_ENV control type. */ 4017 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4018 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4019 } 4020 4021 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4022 URTWN_CHIP_UMC_A_CUT) { 4023 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4024 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4025 } 4026 4027 /* Cache RF register CHNLBW. */ 4028 for (i = 0; i < 2; i++) { 4029 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4030 } 4031 } 4032 4033 static void __noinline 4034 urtwn_cam_init(struct urtwn_softc *sc) 4035 { 4036 uint32_t content, command; 4037 uint8_t idx; 4038 size_t i; 4039 4040 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4041 4042 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4043 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4044 return; 4045 4046 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4047 content = (idx & 3) 4048 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4049 | R92C_CAM_VALID; 4050 4051 command = R92C_CAMCMD_POLLING 4052 | R92C_CAMCMD_WRITE 4053 | R92C_CAM_CTL0(idx); 4054 4055 urtwn_write_4(sc, R92C_CAMWRITE, content); 4056 urtwn_write_4(sc, R92C_CAMCMD, command); 4057 } 4058 4059 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4060 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4061 if (i == 0) { 4062 content = (idx & 3) 4063 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4064 | R92C_CAM_VALID; 4065 } else { 4066 content = 0; 4067 } 4068 4069 command = R92C_CAMCMD_POLLING 4070 | R92C_CAMCMD_WRITE 4071 | R92C_CAM_CTL0(idx) 4072 | i; 4073 4074 urtwn_write_4(sc, R92C_CAMWRITE, content); 4075 urtwn_write_4(sc, R92C_CAMCMD, command); 4076 } 4077 } 4078 4079 /* Invalidate all CAM entries. */ 4080 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4081 } 4082 4083 static void __noinline 4084 urtwn_pa_bias_init(struct urtwn_softc *sc) 4085 { 4086 uint8_t reg; 4087 size_t i; 4088 4089 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4090 4091 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4092 4093 for (i = 0; i < sc->nrxchains; i++) { 4094 if (sc->pa_setting & (1U << i)) 4095 continue; 4096 4097 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4098 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4099 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4100 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4101 } 4102 if (!(sc->pa_setting & 0x10)) { 4103 reg = urtwn_read_1(sc, 0x16); 4104 reg = (reg & ~0xf0) | 0x90; 4105 urtwn_write_1(sc, 0x16, reg); 4106 } 4107 } 4108 4109 static void __noinline 4110 urtwn_rxfilter_init(struct urtwn_softc *sc) 4111 { 4112 4113 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4114 4115 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4116 4117 /* Initialize Rx filter. */ 4118 /* TODO: use better filter for monitor mode. */ 4119 urtwn_write_4(sc, R92C_RCR, 4120 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4121 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4122 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4123 /* Accept all multicast frames. */ 4124 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4125 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4126 /* Accept all management frames. */ 4127 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4128 /* Reject all control frames. */ 4129 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4130 /* Accept all data frames. */ 4131 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4132 } 4133 4134 static void __noinline 4135 urtwn_edca_init(struct urtwn_softc *sc) 4136 { 4137 4138 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4139 4140 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4141 4142 /* set spec SIFS (used in NAV) */ 4143 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4144 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4145 4146 /* set SIFS CCK/OFDM */ 4147 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4148 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4149 4150 /* TXOP */ 4151 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4152 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4153 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4154 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4155 } 4156 4157 static void 4158 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4159 uint16_t power[URTWN_RIDX_COUNT]) 4160 { 4161 uint32_t reg; 4162 4163 URTWNHIST_FUNC(); 4164 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4165 4166 /* Write per-CCK rate Tx power. */ 4167 if (chain == 0) { 4168 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4169 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4170 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4171 4172 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4173 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4174 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4175 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4176 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4177 } else { 4178 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4179 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4180 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4181 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4182 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4183 4184 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4185 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4186 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4187 } 4188 /* Write per-OFDM rate Tx power. */ 4189 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4190 SM(R92C_TXAGC_RATE06, power[ 4]) | 4191 SM(R92C_TXAGC_RATE09, power[ 5]) | 4192 SM(R92C_TXAGC_RATE12, power[ 6]) | 4193 SM(R92C_TXAGC_RATE18, power[ 7])); 4194 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4195 SM(R92C_TXAGC_RATE24, power[ 8]) | 4196 SM(R92C_TXAGC_RATE36, power[ 9]) | 4197 SM(R92C_TXAGC_RATE48, power[10]) | 4198 SM(R92C_TXAGC_RATE54, power[11])); 4199 /* Write per-MCS Tx power. */ 4200 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4201 SM(R92C_TXAGC_MCS00, power[12]) | 4202 SM(R92C_TXAGC_MCS01, power[13]) | 4203 SM(R92C_TXAGC_MCS02, power[14]) | 4204 SM(R92C_TXAGC_MCS03, power[15])); 4205 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4206 SM(R92C_TXAGC_MCS04, power[16]) | 4207 SM(R92C_TXAGC_MCS05, power[17]) | 4208 SM(R92C_TXAGC_MCS06, power[18]) | 4209 SM(R92C_TXAGC_MCS07, power[19])); 4210 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4211 SM(R92C_TXAGC_MCS08, power[20]) | 4212 SM(R92C_TXAGC_MCS09, power[21]) | 4213 SM(R92C_TXAGC_MCS10, power[22]) | 4214 SM(R92C_TXAGC_MCS11, power[23])); 4215 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4216 SM(R92C_TXAGC_MCS12, power[24]) | 4217 SM(R92C_TXAGC_MCS13, power[25]) | 4218 SM(R92C_TXAGC_MCS14, power[26]) | 4219 SM(R92C_TXAGC_MCS15, power[27])); 4220 } 4221 4222 static void 4223 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4224 uint16_t power[URTWN_RIDX_COUNT]) 4225 { 4226 struct r92c_rom *rom = &sc->rom; 4227 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4228 const struct rtwn_txpwr *base; 4229 int ridx, group; 4230 4231 URTWNHIST_FUNC(); 4232 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4233 4234 /* Determine channel group. */ 4235 if (chan <= 3) { 4236 group = 0; 4237 } else if (chan <= 9) { 4238 group = 1; 4239 } else { 4240 group = 2; 4241 } 4242 4243 /* Get original Tx power based on board type and RF chain. */ 4244 if (!(sc->chip & URTWN_CHIP_92C)) { 4245 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4246 base = &rtl8188ru_txagc[chain]; 4247 } else { 4248 base = &rtl8192cu_txagc[chain]; 4249 } 4250 } else { 4251 base = &rtl8192cu_txagc[chain]; 4252 } 4253 4254 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4255 if (sc->regulatory == 0) { 4256 for (ridx = 0; ridx <= 3; ridx++) { 4257 power[ridx] = base->pwr[0][ridx]; 4258 } 4259 } 4260 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4261 if (sc->regulatory == 3) { 4262 power[ridx] = base->pwr[0][ridx]; 4263 /* Apply vendor limits. */ 4264 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4265 maxpow = rom->ht40_max_pwr[group]; 4266 } else { 4267 maxpow = rom->ht20_max_pwr[group]; 4268 } 4269 maxpow = (maxpow >> (chain * 4)) & 0xf; 4270 if (power[ridx] > maxpow) { 4271 power[ridx] = maxpow; 4272 } 4273 } else if (sc->regulatory == 1) { 4274 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4275 power[ridx] = base->pwr[group][ridx]; 4276 } 4277 } else if (sc->regulatory != 2) { 4278 power[ridx] = base->pwr[0][ridx]; 4279 } 4280 } 4281 4282 /* Compute per-CCK rate Tx power. */ 4283 cckpow = rom->cck_tx_pwr[chain][group]; 4284 for (ridx = 0; ridx <= 3; ridx++) { 4285 power[ridx] += cckpow; 4286 if (power[ridx] > R92C_MAX_TX_PWR) { 4287 power[ridx] = R92C_MAX_TX_PWR; 4288 } 4289 } 4290 4291 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4292 if (sc->ntxchains > 1) { 4293 /* Apply reduction for 2 spatial streams. */ 4294 diff = rom->ht40_2s_tx_pwr_diff[group]; 4295 diff = (diff >> (chain * 4)) & 0xf; 4296 htpow = (htpow > diff) ? htpow - diff : 0; 4297 } 4298 4299 /* Compute per-OFDM rate Tx power. */ 4300 diff = rom->ofdm_tx_pwr_diff[group]; 4301 diff = (diff >> (chain * 4)) & 0xf; 4302 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4303 for (ridx = 4; ridx <= 11; ridx++) { 4304 power[ridx] += ofdmpow; 4305 if (power[ridx] > R92C_MAX_TX_PWR) { 4306 power[ridx] = R92C_MAX_TX_PWR; 4307 } 4308 } 4309 4310 /* Compute per-MCS Tx power. */ 4311 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4312 diff = rom->ht20_tx_pwr_diff[group]; 4313 diff = (diff >> (chain * 4)) & 0xf; 4314 htpow += diff; /* HT40->HT20 correction. */ 4315 } 4316 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4317 power[ridx] += htpow; 4318 if (power[ridx] > R92C_MAX_TX_PWR) { 4319 power[ridx] = R92C_MAX_TX_PWR; 4320 } 4321 } 4322 #ifdef URTWN_DEBUG 4323 if (urtwn_debug & DBG_RF) { 4324 /* Dump per-rate Tx power values. */ 4325 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4326 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4327 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4328 } 4329 #endif 4330 } 4331 4332 void 4333 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4334 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4335 { 4336 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4337 const struct rtwn_r88e_txpwr *base; 4338 int ridx, group; 4339 4340 URTWNHIST_FUNC(); 4341 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4342 4343 /* Determine channel group. */ 4344 if (chan <= 2) 4345 group = 0; 4346 else if (chan <= 5) 4347 group = 1; 4348 else if (chan <= 8) 4349 group = 2; 4350 else if (chan <= 11) 4351 group = 3; 4352 else if (chan <= 13) 4353 group = 4; 4354 else 4355 group = 5; 4356 4357 /* Get original Tx power based on board type and RF chain. */ 4358 base = &rtl8188eu_txagc[chain]; 4359 4360 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4361 if (sc->regulatory == 0) { 4362 for (ridx = 0; ridx <= 3; ridx++) 4363 power[ridx] = base->pwr[0][ridx]; 4364 } 4365 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4366 if (sc->regulatory == 3) 4367 power[ridx] = base->pwr[0][ridx]; 4368 else if (sc->regulatory == 1) { 4369 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4370 power[ridx] = base->pwr[group][ridx]; 4371 } else if (sc->regulatory != 2) 4372 power[ridx] = base->pwr[0][ridx]; 4373 } 4374 4375 /* Compute per-CCK rate Tx power. */ 4376 cckpow = sc->cck_tx_pwr[group]; 4377 for (ridx = 0; ridx <= 3; ridx++) { 4378 power[ridx] += cckpow; 4379 if (power[ridx] > R92C_MAX_TX_PWR) 4380 power[ridx] = R92C_MAX_TX_PWR; 4381 } 4382 4383 htpow = sc->ht40_tx_pwr[group]; 4384 4385 /* Compute per-OFDM rate Tx power. */ 4386 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4387 for (ridx = 4; ridx <= 11; ridx++) { 4388 power[ridx] += ofdmpow; 4389 if (power[ridx] > R92C_MAX_TX_PWR) 4390 power[ridx] = R92C_MAX_TX_PWR; 4391 } 4392 4393 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4394 for (ridx = 12; ridx <= 27; ridx++) { 4395 power[ridx] += bw20pow; 4396 if (power[ridx] > R92C_MAX_TX_PWR) 4397 power[ridx] = R92C_MAX_TX_PWR; 4398 } 4399 } 4400 4401 static void 4402 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4403 { 4404 uint16_t power[URTWN_RIDX_COUNT]; 4405 size_t i; 4406 4407 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4408 4409 for (i = 0; i < sc->ntxchains; i++) { 4410 /* Compute per-rate Tx power values. */ 4411 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4412 ISSET(sc->chip, URTWN_CHIP_92EU)) 4413 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4414 else 4415 urtwn_get_txpower(sc, i, chan, ht40m, power); 4416 /* Write per-rate Tx power values to hardware. */ 4417 urtwn_write_txpower(sc, i, power); 4418 } 4419 } 4420 4421 static void __noinline 4422 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4423 { 4424 struct ieee80211com *ic = &sc->sc_ic; 4425 u_int chan; 4426 size_t i; 4427 4428 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4429 4430 URTWNHIST_FUNC(); 4431 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4432 4433 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4434 4435 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4436 chan += 2; 4437 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4438 chan -= 2; 4439 } 4440 4441 /* Set Tx power for this new channel. */ 4442 urtwn_set_txpower(sc, chan, ht40m); 4443 4444 for (i = 0; i < sc->nrxchains; i++) { 4445 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4446 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4447 } 4448 4449 if (ht40m) { 4450 /* Is secondary channel below or above primary? */ 4451 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4452 uint32_t reg; 4453 4454 urtwn_write_1(sc, R92C_BWOPMODE, 4455 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4456 4457 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4458 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4459 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4460 4461 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4462 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4463 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4464 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4465 4466 /* Set CCK side band. */ 4467 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4468 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4469 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4470 4471 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4472 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4473 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4474 4475 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4476 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4477 ~R92C_FPGA0_ANAPARAM2_CBW20); 4478 4479 reg = urtwn_bb_read(sc, 0x818); 4480 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4481 urtwn_bb_write(sc, 0x818, reg); 4482 4483 /* Select 40MHz bandwidth. */ 4484 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4485 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4486 } else { 4487 urtwn_write_1(sc, R92C_BWOPMODE, 4488 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4489 4490 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4491 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4492 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4493 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4494 4495 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4496 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4497 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4498 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4499 R92C_FPGA0_ANAPARAM2_CBW20); 4500 } 4501 4502 /* Select 20MHz bandwidth. */ 4503 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4504 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4505 (ISSET(sc->chip, URTWN_CHIP_88E) || 4506 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4507 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4508 } 4509 } 4510 4511 static void __noinline 4512 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4513 { 4514 4515 URTWNHIST_FUNC(); 4516 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4517 4518 uint32_t addaBackup[16], iqkBackup[4], piMode; 4519 4520 #ifdef notyet 4521 uint32_t odfm0_agccore_regs[3]; 4522 uint32_t ant_regs[3]; 4523 uint32_t rf_regs[8]; 4524 #endif 4525 uint32_t reg0, reg1, reg2; 4526 int i, attempt; 4527 4528 #ifdef notyet 4529 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4530 R92E_STBC_SETTING + 2)); 4531 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4532 /* Save AGCCORE regs. */ 4533 for (i = 0; i < sc->nrxchains; i++) { 4534 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4535 R92C_OFDM0_AGCCORE1(i)); 4536 } 4537 #endif 4538 /* Save BB regs. */ 4539 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4540 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4541 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4542 4543 /* Save adda regs to be restored when finished. */ 4544 for (i = 0; i < __arraycount(addaReg); i++) 4545 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4546 /* Save mac regs. */ 4547 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4548 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4549 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4550 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4551 4552 #ifdef notyet 4553 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4554 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4555 4556 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4557 for (i = 0; i < sc->nrxchains; i++) 4558 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4559 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4560 #endif 4561 4562 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4563 R92C_HSSI_PARAM1_PI); 4564 if (piMode == 0) { 4565 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4566 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4567 R92C_HSSI_PARAM1_PI); 4568 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4569 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4570 R92C_HSSI_PARAM1_PI); 4571 } 4572 4573 attempt = 1; 4574 4575 next_attempt: 4576 4577 /* Set mac regs for calibration. */ 4578 for (i = 0; i < __arraycount(addaReg); i++) { 4579 urtwn_bb_write(sc, addaReg[i], 4580 addaReg[__arraycount(addaReg) - 1]); 4581 } 4582 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4583 R92C_CCK0_AFESETTING)); 4584 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4585 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4586 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4587 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4588 4589 if (sc->ntxchains > 1) 4590 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4591 4592 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4593 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4594 ~R92C_BCN_CTRL_EN_BCN)); 4595 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4596 ~R92C_BCN_CTRL_EN_BCN)); 4597 4598 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4599 ~R92C_GPIO_MUXCFG_ENBT)); 4600 4601 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4602 4603 if (sc->ntxchains > 1) 4604 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4605 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4606 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4607 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4608 4609 /* Restore BB regs. */ 4610 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4611 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4612 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4613 4614 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4615 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4616 if (sc->nrxchains > 1) 4617 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4618 4619 if (attempt-- > 0) 4620 goto next_attempt; 4621 4622 /* Restore mode. */ 4623 if (piMode == 0) { 4624 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4625 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4626 ~R92C_HSSI_PARAM1_PI); 4627 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4628 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4629 ~R92C_HSSI_PARAM1_PI); 4630 } 4631 4632 #ifdef notyet 4633 for (i = 0; i < sc->nrxchains; i++) { 4634 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4635 odfm0_agccore_regs[i]); 4636 } 4637 #endif 4638 4639 /* Restore adda regs. */ 4640 for (i = 0; i < __arraycount(addaReg); i++) 4641 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4642 /* Restore mac regs. */ 4643 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4644 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4645 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4646 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4647 4648 #ifdef notyet 4649 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4650 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4651 4652 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4653 for (i = 0; i < sc->nrxchains; i++) 4654 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4655 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4656 #endif 4657 } 4658 4659 static void 4660 urtwn_lc_calib(struct urtwn_softc *sc) 4661 { 4662 uint32_t rf_ac[2]; 4663 uint8_t txmode; 4664 size_t i; 4665 4666 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4667 4668 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4669 4670 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4671 if ((txmode & 0x70) != 0) { 4672 /* Disable all continuous Tx. */ 4673 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4674 4675 /* Set RF mode to standby mode. */ 4676 for (i = 0; i < sc->nrxchains; i++) { 4677 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4678 urtwn_rf_write(sc, i, R92C_RF_AC, 4679 RW(rf_ac[i], R92C_RF_AC_MODE, 4680 R92C_RF_AC_MODE_STANDBY)); 4681 } 4682 } else { 4683 /* Block all Tx queues. */ 4684 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4685 } 4686 /* Start calibration. */ 4687 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4688 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4689 4690 /* Give calibration the time to complete. */ 4691 urtwn_delay_ms(sc, 100); 4692 4693 /* Restore configuration. */ 4694 if ((txmode & 0x70) != 0) { 4695 /* Restore Tx mode. */ 4696 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4697 /* Restore RF mode. */ 4698 for (i = 0; i < sc->nrxchains; i++) { 4699 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4700 } 4701 } else { 4702 /* Unblock all Tx queues. */ 4703 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4704 } 4705 } 4706 4707 static void 4708 urtwn_temp_calib(struct urtwn_softc *sc) 4709 { 4710 int temp, t_meter_reg; 4711 4712 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4713 4714 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4715 4716 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4717 t_meter_reg = R92C_RF_T_METER; 4718 else 4719 t_meter_reg = R92E_RF_T_METER; 4720 4721 if (sc->thcal_state == 0) { 4722 /* Start measuring temperature. */ 4723 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4724 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4725 sc->thcal_state = 1; 4726 return; 4727 } 4728 sc->thcal_state = 0; 4729 4730 /* Read measured temperature. */ 4731 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4732 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4733 if (temp == 0) /* Read failed, skip. */ 4734 return; 4735 4736 /* 4737 * Redo LC calibration if temperature changed significantly since 4738 * last calibration. 4739 */ 4740 if (sc->thcal_lctemp == 0) { 4741 /* First LC calibration is performed in urtwn_init(). */ 4742 sc->thcal_lctemp = temp; 4743 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4744 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4745 sc->thcal_lctemp, temp, 0, 0); 4746 urtwn_lc_calib(sc); 4747 /* Record temperature of last LC calibration. */ 4748 sc->thcal_lctemp = temp; 4749 } 4750 } 4751 4752 static int 4753 urtwn_init(struct ifnet *ifp) 4754 { 4755 struct urtwn_softc *sc = ifp->if_softc; 4756 struct ieee80211com *ic = &sc->sc_ic; 4757 struct urtwn_rx_data *data; 4758 uint32_t reg; 4759 size_t i; 4760 int error; 4761 4762 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4763 4764 urtwn_stop(ifp, 0); 4765 4766 mutex_enter(&sc->sc_write_mtx); 4767 4768 mutex_enter(&sc->sc_task_mtx); 4769 /* Init host async commands ring. */ 4770 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4771 mutex_exit(&sc->sc_task_mtx); 4772 4773 mutex_enter(&sc->sc_fwcmd_mtx); 4774 /* Init firmware commands ring. */ 4775 sc->fwcur = 0; 4776 mutex_exit(&sc->sc_fwcmd_mtx); 4777 4778 /* Allocate Tx/Rx buffers. */ 4779 error = urtwn_alloc_rx_list(sc); 4780 if (error != 0) { 4781 aprint_error_dev(sc->sc_dev, 4782 "could not allocate Rx buffers\n"); 4783 goto fail; 4784 } 4785 error = urtwn_alloc_tx_list(sc); 4786 if (error != 0) { 4787 aprint_error_dev(sc->sc_dev, 4788 "could not allocate Tx buffers\n"); 4789 goto fail; 4790 } 4791 4792 /* Power on adapter. */ 4793 error = urtwn_power_on(sc); 4794 if (error != 0) 4795 goto fail; 4796 4797 /* Initialize DMA. */ 4798 error = urtwn_dma_init(sc); 4799 if (error != 0) 4800 goto fail; 4801 4802 /* Set info size in Rx descriptors (in 64-bit words). */ 4803 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4804 4805 /* Init interrupts. */ 4806 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4807 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4808 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4809 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4810 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4811 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4812 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4813 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4814 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4815 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4816 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4817 } 4818 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4819 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4820 } else { 4821 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4822 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4823 } 4824 4825 /* Set MAC address. */ 4826 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4827 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4828 4829 /* Set initial network type. */ 4830 reg = urtwn_read_4(sc, R92C_CR); 4831 switch (ic->ic_opmode) { 4832 case IEEE80211_M_STA: 4833 default: 4834 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4835 break; 4836 4837 case IEEE80211_M_IBSS: 4838 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4839 break; 4840 } 4841 urtwn_write_4(sc, R92C_CR, reg); 4842 4843 /* Set response rate */ 4844 reg = urtwn_read_4(sc, R92C_RRSR); 4845 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4846 urtwn_write_4(sc, R92C_RRSR, reg); 4847 4848 /* SIFS (used in NAV) */ 4849 urtwn_write_2(sc, R92C_SPEC_SIFS, 4850 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4851 4852 /* Set short/long retry limits. */ 4853 urtwn_write_2(sc, R92C_RL, 4854 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4855 4856 /* Initialize EDCA parameters. */ 4857 urtwn_edca_init(sc); 4858 4859 /* Setup rate fallback. */ 4860 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4861 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4862 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4863 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4864 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4865 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4866 } 4867 4868 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4869 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4870 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4871 /* Set ACK timeout. */ 4872 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4873 4874 /* Setup USB aggregation. */ 4875 /* Tx */ 4876 reg = urtwn_read_4(sc, R92C_TDECTRL); 4877 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4878 urtwn_write_4(sc, R92C_TDECTRL, reg); 4879 /* Rx */ 4880 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4881 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4882 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4883 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4884 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4885 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4886 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4887 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4888 ISSET(sc->chip, URTWN_CHIP_92EU)) 4889 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4890 else 4891 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4892 4893 /* Initialize beacon parameters. */ 4894 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4895 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4896 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4897 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4898 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4899 4900 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4901 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4902 /* Setup AMPDU aggregation. */ 4903 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4904 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4905 urtwn_write_2(sc, 0x4ca, 0x0708); 4906 4907 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4908 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4909 } 4910 4911 /* Load 8051 microcode. */ 4912 error = urtwn_load_firmware(sc); 4913 if (error != 0) 4914 goto fail; 4915 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4916 4917 /* Initialize MAC/BB/RF blocks. */ 4918 /* 4919 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4920 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4921 * XXX: This setting should be removed from rtl8192cu_mac[]. 4922 */ 4923 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4924 urtwn_rxfilter_init(sc); // reset R92C_RCR 4925 urtwn_bb_init(sc); 4926 urtwn_rf_init(sc); 4927 4928 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4929 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4930 urtwn_write_2(sc, R92C_CR, 4931 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4932 R92C_CR_MACRXEN); 4933 } 4934 4935 /* Turn CCK and OFDM blocks on. */ 4936 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4937 reg |= R92C_RFMOD_CCK_EN; 4938 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4939 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4940 reg |= R92C_RFMOD_OFDM_EN; 4941 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4942 4943 /* Clear per-station keys table. */ 4944 urtwn_cam_init(sc); 4945 4946 /* Enable hardware sequence numbering. */ 4947 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4948 4949 /* Perform LO and IQ calibrations. */ 4950 urtwn_iq_calib(sc, sc->iqk_inited); 4951 sc->iqk_inited = true; 4952 4953 /* Perform LC calibration. */ 4954 urtwn_lc_calib(sc); 4955 4956 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4957 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4958 /* Fix USB interference issue. */ 4959 urtwn_write_1(sc, 0xfe40, 0xe0); 4960 urtwn_write_1(sc, 0xfe41, 0x8d); 4961 urtwn_write_1(sc, 0xfe42, 0x80); 4962 urtwn_write_4(sc, 0x20c, 0xfd0320); 4963 4964 urtwn_pa_bias_init(sc); 4965 } 4966 4967 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4968 !(sc->chip & URTWN_CHIP_92EU)) { 4969 /* 1T1R */ 4970 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4971 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4972 } 4973 4974 /* Initialize GPIO setting. */ 4975 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4976 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4977 4978 /* Fix for lower temperature. */ 4979 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4980 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4981 urtwn_write_1(sc, 0x15, 0xe9); 4982 4983 /* Set default channel. */ 4984 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4985 4986 /* Queue Rx xfers. */ 4987 for (size_t j = 0; j < sc->rx_npipe; j++) { 4988 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4989 data = &sc->rx_data[j][i]; 4990 usbd_setup_xfer(data->xfer, data, data->buf, 4991 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4992 urtwn_rxeof); 4993 error = usbd_transfer(data->xfer); 4994 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4995 error != USBD_IN_PROGRESS)) 4996 goto fail; 4997 } 4998 } 4999 5000 /* We're ready to go. */ 5001 ifp->if_flags &= ~IFF_OACTIVE; 5002 ifp->if_flags |= IFF_RUNNING; 5003 sc->sc_running = true; 5004 5005 mutex_exit(&sc->sc_write_mtx); 5006 5007 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5008 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5009 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5010 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5011 urtwn_wait_async(sc); 5012 5013 return 0; 5014 5015 fail: 5016 mutex_exit(&sc->sc_write_mtx); 5017 5018 urtwn_stop(ifp, 1); 5019 return error; 5020 } 5021 5022 static void __noinline 5023 urtwn_stop(struct ifnet *ifp, int disable) 5024 { 5025 struct urtwn_softc *sc = ifp->if_softc; 5026 struct ieee80211com *ic = &sc->sc_ic; 5027 size_t i; 5028 int s; 5029 5030 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5031 5032 s = splusb(); 5033 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5034 urtwn_wait_async(sc); 5035 splx(s); 5036 5037 sc->tx_timer = 0; 5038 ifp->if_timer = 0; 5039 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5040 5041 callout_stop(&sc->sc_scan_to); 5042 callout_stop(&sc->sc_calib_to); 5043 5044 /* Abort Tx. */ 5045 for (i = 0; i < sc->tx_npipe; i++) { 5046 if (sc->tx_pipe[i] != NULL) 5047 usbd_abort_pipe(sc->tx_pipe[i]); 5048 } 5049 5050 /* Stop Rx pipe. */ 5051 for (i = 0; i < sc->rx_npipe; i++) { 5052 if (sc->rx_pipe[i] != NULL) 5053 usbd_abort_pipe(sc->rx_pipe[i]); 5054 } 5055 5056 /* Free Tx/Rx buffers. */ 5057 urtwn_free_tx_list(sc); 5058 urtwn_free_rx_list(sc); 5059 5060 sc->sc_running = false; 5061 if (disable) 5062 urtwn_chip_stop(sc); 5063 } 5064 5065 static int 5066 urtwn_reset(struct ifnet *ifp) 5067 { 5068 struct urtwn_softc *sc = ifp->if_softc; 5069 struct ieee80211com *ic = &sc->sc_ic; 5070 5071 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5072 return ENETRESET; 5073 5074 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5075 5076 return 0; 5077 } 5078 5079 static void 5080 urtwn_chip_stop(struct urtwn_softc *sc) 5081 { 5082 uint32_t reg; 5083 bool disabled = true; 5084 5085 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5086 5087 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5088 ISSET(sc->chip, URTWN_CHIP_92EU)) 5089 return; 5090 5091 mutex_enter(&sc->sc_write_mtx); 5092 5093 /* 5094 * RF Off Sequence 5095 */ 5096 /* Pause MAC TX queue */ 5097 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5098 5099 /* Disable RF */ 5100 urtwn_rf_write(sc, 0, 0, 0); 5101 5102 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5103 5104 /* Reset BB state machine */ 5105 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5106 R92C_SYS_FUNC_EN_USBD | 5107 R92C_SYS_FUNC_EN_USBA | 5108 R92C_SYS_FUNC_EN_BB_GLB_RST); 5109 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5110 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5111 5112 /* 5113 * Reset digital sequence 5114 */ 5115 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5116 /* Reset MCU ready status */ 5117 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5118 /* If firmware in ram code, do reset */ 5119 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5120 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5121 ISSET(sc->chip, URTWN_CHIP_92EU)) 5122 urtwn_r88e_fw_reset(sc); 5123 else 5124 urtwn_fw_reset(sc); 5125 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5126 } 5127 } 5128 5129 /* Reset MAC and Enable 8051 */ 5130 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5131 5132 /* Reset MCU ready status */ 5133 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5134 5135 if (disabled) { 5136 /* Disable MAC clock */ 5137 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5138 /* Disable AFE PLL */ 5139 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5140 /* Gated AFE DIG_CLOCK */ 5141 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5142 /* Isolated digital to PON */ 5143 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5144 } 5145 5146 /* 5147 * Pull GPIO PIN to balance level and LED control 5148 */ 5149 /* 1. Disable GPIO[7:0] */ 5150 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5151 5152 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5153 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5154 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5155 5156 /* Disable GPIO[10:8] */ 5157 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5158 5159 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5160 reg |= (((reg & 0x000f) << 4) | 0x0780); 5161 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5162 5163 /* Disable LED0 & 1 */ 5164 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5165 5166 /* 5167 * Reset digital sequence 5168 */ 5169 if (disabled) { 5170 /* Disable ELDR clock */ 5171 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5172 /* Isolated ELDR to PON */ 5173 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5174 } 5175 5176 /* 5177 * Disable analog sequence 5178 */ 5179 if (disabled) { 5180 /* Disable A15 power */ 5181 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5182 /* Disable digital core power */ 5183 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5184 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5185 ~R92C_LDOV12D_CTRL_LDV12_EN); 5186 } 5187 5188 /* Enter PFM mode */ 5189 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5190 5191 /* Set USB suspend */ 5192 urtwn_write_2(sc, R92C_APS_FSMCO, 5193 R92C_APS_FSMCO_APDM_HOST | 5194 R92C_APS_FSMCO_AFSM_HSUS | 5195 R92C_APS_FSMCO_PFM_ALDN); 5196 5197 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5198 5199 mutex_exit(&sc->sc_write_mtx); 5200 } 5201 5202 static void 5203 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5204 { 5205 if (sc->sc_running == false) 5206 DELAY(ms * 1000); 5207 else 5208 usbd_delay_ms(sc->sc_udev, ms); 5209 } 5210 5211 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5212 5213 #ifdef _MODULE 5214 #include "ioconf.c" 5215 #endif 5216 5217 static int 5218 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5219 { 5220 int error = 0; 5221 5222 switch (cmd) { 5223 case MODULE_CMD_INIT: 5224 #ifdef _MODULE 5225 error = config_init_component(cfdriver_ioconf_urtwn, 5226 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5227 #endif 5228 return error; 5229 case MODULE_CMD_FINI: 5230 #ifdef _MODULE 5231 error = config_fini_component(cfdriver_ioconf_urtwn, 5232 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5233 #endif 5234 return error; 5235 default: 5236 return ENOTTY; 5237 } 5238 } 5239
Indexes created Tue Sep 30 06:09:59 GMT 2025