if_urtwn.c revision 1.11
1 /* $NetBSD: if_urtwn.c,v 1.11 2013/01/18 13:45:51 jmcneill Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.11 2013/01/18 13:45:51 jmcneill Exp $"); 26 27 #ifdef _KERNEL_OPT 28 #include "opt_inet.h" 29 #endif 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 #ifdef URTWN_DEBUG 78 #define DBG_INIT __BIT(0) 79 #define DBG_FN __BIT(1) 80 #define DBG_TX __BIT(2) 81 #define DBG_RX __BIT(3) 82 #define DBG_STM __BIT(4) 83 #define DBG_RF __BIT(5) 84 #define DBG_REG __BIT(6) 85 #define DBG_ALL 0xffffffffU 86 u_int urtwn_debug = 0; 87 #define DPRINTFN(n, s) \ 88 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 89 #else 90 #define DPRINTFN(n, s) 91 #endif 92 93 static const struct usb_devno urtwn_devs[] = { 94 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 95 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 96 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 97 { USB_VENDOR_ASUSTEK, USB_PRODUCT_ASUSTEK_RTL8192CU }, 98 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 99 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 100 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 101 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 102 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 103 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 104 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 105 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 106 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 107 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 108 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 109 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 110 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 111 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 112 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 113 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 114 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 115 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 116 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 117 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 118 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 119 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 120 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 121 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 122 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 123 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 124 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 125 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 126 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 127 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 128 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 129 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 130 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 131 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 132 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 133 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 134 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 135 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 136 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 137 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 138 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 139 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 140 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 141 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 142 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 143 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 144 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 145 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 146 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 147 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 148 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 149 }; 150 151 static int urtwn_match(device_t, cfdata_t, void *); 152 static void urtwn_attach(device_t, device_t, void *); 153 static int urtwn_detach(device_t, int); 154 static int urtwn_activate(device_t, enum devact); 155 156 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 157 urtwn_attach, urtwn_detach, urtwn_activate); 158 159 static int urtwn_open_pipes(struct urtwn_softc *); 160 static void urtwn_close_pipes(struct urtwn_softc *); 161 static int urtwn_alloc_rx_list(struct urtwn_softc *); 162 static void urtwn_free_rx_list(struct urtwn_softc *); 163 static int urtwn_alloc_tx_list(struct urtwn_softc *); 164 static void urtwn_free_tx_list(struct urtwn_softc *); 165 static void urtwn_task(void *); 166 static void urtwn_do_async(struct urtwn_softc *, 167 void (*)(struct urtwn_softc *, void *), void *, int); 168 static void urtwn_wait_async(struct urtwn_softc *); 169 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 170 int); 171 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 172 int); 173 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 174 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 175 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 176 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 177 static void urtwn_efuse_read(struct urtwn_softc *); 178 static int urtwn_read_chipid(struct urtwn_softc *); 179 static void urtwn_read_rom(struct urtwn_softc *); 180 static int urtwn_media_change(struct ifnet *); 181 static int urtwn_ra_init(struct urtwn_softc *); 182 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 183 static void urtwn_set_led(struct urtwn_softc *, int, int); 184 static void urtwn_calib_to(void *); 185 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 186 static void urtwn_next_scan(void *); 187 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 188 int); 189 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 190 static int urtwn_wme_update(struct ieee80211com *); 191 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 192 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 193 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 194 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 195 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 196 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 197 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 198 struct ieee80211_node *); 199 static void urtwn_start(struct ifnet *); 200 static void urtwn_watchdog(struct ifnet *); 201 static int urtwn_ioctl(struct ifnet *, u_long, void *); 202 static int urtwn_power_on(struct urtwn_softc *); 203 static int urtwn_llt_init(struct urtwn_softc *); 204 static void urtwn_fw_reset(struct urtwn_softc *); 205 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 206 static int urtwn_load_firmware(struct urtwn_softc *); 207 static int urtwn_dma_init(struct urtwn_softc *); 208 static void urtwn_mac_init(struct urtwn_softc *); 209 static void urtwn_bb_init(struct urtwn_softc *); 210 static void urtwn_rf_init(struct urtwn_softc *); 211 static void urtwn_cam_init(struct urtwn_softc *); 212 static void urtwn_pa_bias_init(struct urtwn_softc *); 213 static void urtwn_rxfilter_init(struct urtwn_softc *); 214 static void urtwn_edca_init(struct urtwn_softc *); 215 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 216 static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, 217 uint16_t[]); 218 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 219 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 220 u_int); 221 static void urtwn_iq_calib(struct urtwn_softc *, bool); 222 static void urtwn_lc_calib(struct urtwn_softc *); 223 static void urtwn_temp_calib(struct urtwn_softc *); 224 static int urtwn_init(struct ifnet *); 225 static void urtwn_stop(struct ifnet *, int); 226 static void urtwn_chip_stop(struct urtwn_softc *); 227 228 /* Aliases. */ 229 #define urtwn_bb_write urtwn_write_4 230 #define urtwn_bb_read urtwn_read_4 231 232 static int 233 urtwn_match(device_t parent, cfdata_t match, void *aux) 234 { 235 struct usb_attach_arg *uaa = aux; 236 237 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 238 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 239 } 240 241 static void 242 urtwn_attach(device_t parent, device_t self, void *aux) 243 { 244 struct urtwn_softc *sc = device_private(self); 245 struct ieee80211com *ic = &sc->sc_ic; 246 struct ifnet *ifp = &sc->sc_if; 247 struct usb_attach_arg *uaa = aux; 248 char *devinfop; 249 int i, error; 250 251 sc->sc_dev = self; 252 sc->sc_udev = uaa->device; 253 254 aprint_naive("\n"); 255 aprint_normal("\n"); 256 257 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 258 aprint_normal_dev(self, "%s\n", devinfop); 259 usbd_devinfo_free(devinfop); 260 261 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 262 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NET); 263 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 264 265 usb_init_task(&sc->sc_task, urtwn_task, sc); 266 267 callout_init(&sc->sc_scan_to, 0); 268 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 269 callout_init(&sc->sc_calib_to, 0); 270 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 271 272 error = usbd_set_config_no(sc->sc_udev, 1, 0); 273 if (error != 0) { 274 aprint_error_dev(self, "failed to set configuration" 275 ", err=%s\n", usbd_errstr(error)); 276 goto fail; 277 } 278 279 /* Get the first interface handle. */ 280 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 281 if (error != 0) { 282 aprint_error_dev(self, "could not get interface handle\n"); 283 goto fail; 284 } 285 286 error = urtwn_read_chipid(sc); 287 if (error != 0) { 288 aprint_error_dev(self, "unsupported test chip\n"); 289 goto fail; 290 } 291 292 /* Determine number of Tx/Rx chains. */ 293 if (sc->chip & URTWN_CHIP_92C) { 294 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 295 sc->nrxchains = 2; 296 } else { 297 sc->ntxchains = 1; 298 sc->nrxchains = 1; 299 } 300 urtwn_read_rom(sc); 301 302 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 303 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 304 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 305 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 306 "8188CUS", sc->ntxchains, sc->nrxchains, 307 ether_sprintf(ic->ic_myaddr)); 308 309 error = urtwn_open_pipes(sc); 310 if (error != 0) { 311 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 312 goto fail; 313 } 314 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 315 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 316 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 317 318 /* 319 * Setup the 802.11 device. 320 */ 321 ic->ic_ifp = ifp; 322 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 323 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 324 ic->ic_state = IEEE80211_S_INIT; 325 326 /* Set device capabilities. */ 327 ic->ic_caps = 328 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 329 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 330 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 331 IEEE80211_C_WME | /* 802.11e */ 332 IEEE80211_C_WPA; /* 802.11i */ 333 334 /* Set supported .11b and .11g rates. */ 335 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 336 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 337 338 /* Set supported .11b and .11g channels (1 through 14). */ 339 for (i = 1; i <= 14; i++) { 340 ic->ic_channels[i].ic_freq = 341 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 342 ic->ic_channels[i].ic_flags = 343 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 344 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 345 } 346 347 ifp->if_softc = sc; 348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 349 ifp->if_init = urtwn_init; 350 ifp->if_ioctl = urtwn_ioctl; 351 ifp->if_start = urtwn_start; 352 ifp->if_watchdog = urtwn_watchdog; 353 IFQ_SET_READY(&ifp->if_snd); 354 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 355 356 if_attach(ifp); 357 ieee80211_ifattach(ic); 358 /* override default methods */ 359 ic->ic_wme.wme_update = urtwn_wme_update; 360 361 /* Override state transition machine. */ 362 sc->sc_newstate = ic->ic_newstate; 363 ic->ic_newstate = urtwn_newstate; 364 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 365 366 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 367 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 368 &sc->sc_drvbpf); 369 370 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 371 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 372 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 373 374 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 375 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 376 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 377 378 ieee80211_announce(ic); 379 380 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 381 382 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 383 return; 384 385 fail: 386 sc->sc_dying = 1; 387 aprint_error_dev(self, "attach failed\n"); 388 } 389 390 static int 391 urtwn_detach(device_t self, int flags) 392 { 393 struct urtwn_softc *sc = device_private(self); 394 struct ifnet *ifp = &sc->sc_if; 395 int s; 396 397 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 398 399 s = splusb(); 400 401 sc->sc_dying = 1; 402 403 callout_stop(&sc->sc_scan_to); 404 callout_stop(&sc->sc_calib_to); 405 406 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 407 usb_rem_task(sc->sc_udev, &sc->sc_task); 408 urtwn_stop(ifp, 0); 409 410 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 411 bpf_detach(ifp); 412 ieee80211_ifdetach(&sc->sc_ic); 413 if_detach(ifp); 414 415 /* Free Tx/Rx buffers. */ 416 urtwn_free_tx_list(sc); 417 urtwn_free_rx_list(sc); 418 419 /* Abort and close Tx/Rx pipes. */ 420 urtwn_close_pipes(sc); 421 } 422 423 splx(s); 424 425 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 426 427 callout_destroy(&sc->sc_scan_to); 428 callout_destroy(&sc->sc_calib_to); 429 mutex_destroy(&sc->sc_fwcmd_mtx); 430 mutex_destroy(&sc->sc_tx_mtx); 431 mutex_destroy(&sc->sc_task_mtx); 432 433 return (0); 434 } 435 436 static int 437 urtwn_activate(device_t self, enum devact act) 438 { 439 struct urtwn_softc *sc = device_private(self); 440 441 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 442 443 switch (act) { 444 case DVACT_DEACTIVATE: 445 if_deactivate(sc->sc_ic.ic_ifp); 446 return (0); 447 default: 448 return (EOPNOTSUPP); 449 } 450 } 451 452 static int 453 urtwn_open_pipes(struct urtwn_softc *sc) 454 { 455 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 456 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 457 usb_interface_descriptor_t *id; 458 usb_endpoint_descriptor_t *ed; 459 int i, ntx = 0, error; 460 461 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 462 463 /* Determine the number of bulk-out pipes. */ 464 id = usbd_get_interface_descriptor(sc->sc_iface); 465 for (i = 0; i < id->bNumEndpoints; i++) { 466 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 467 if (ed != NULL && 468 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 469 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 470 ntx++; 471 } 472 DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", 473 device_xname(sc->sc_dev), __func__, ntx)); 474 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 475 aprint_error_dev(sc->sc_dev, 476 "%d: invalid number of Tx bulk pipes\n", ntx); 477 return (EIO); 478 } 479 sc->rx_npipe = 1; 480 sc->tx_npipe = ntx; 481 482 /* Open bulk-in pipe at address 0x81. */ 483 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 484 &sc->rx_pipe); 485 if (error != 0) { 486 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe\n"); 487 goto fail; 488 } 489 490 /* Open bulk-out pipes (up to 3). */ 491 for (i = 0; i < ntx; i++) { 492 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 493 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 494 if (error != 0) { 495 aprint_error_dev(sc->sc_dev, 496 "could not open Tx bulk pipe 0x%02x\n", epaddr[i]); 497 goto fail; 498 } 499 } 500 501 /* Map 802.11 access categories to USB pipes. */ 502 sc->ac2idx[WME_AC_BK] = 503 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 504 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 505 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 506 507 fail: 508 if (error != 0) 509 urtwn_close_pipes(sc); 510 return (error); 511 } 512 513 static void 514 urtwn_close_pipes(struct urtwn_softc *sc) 515 { 516 int i; 517 518 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 519 520 /* Close Rx pipe. */ 521 if (sc->rx_pipe != NULL) { 522 usbd_abort_pipe(sc->rx_pipe); 523 usbd_close_pipe(sc->rx_pipe); 524 sc->rx_pipe = NULL; 525 } 526 /* Close Tx pipes. */ 527 for (i = 0; i < R92C_MAX_EPOUT; i++) { 528 if (sc->tx_pipe[i] == NULL) 529 continue; 530 usbd_abort_pipe(sc->tx_pipe[i]); 531 usbd_close_pipe(sc->tx_pipe[i]); 532 sc->tx_pipe[i] = NULL; 533 } 534 } 535 536 static int 537 urtwn_alloc_rx_list(struct urtwn_softc *sc) 538 { 539 struct urtwn_rx_data *data; 540 int i, error = 0; 541 542 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 543 544 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 545 data = &sc->rx_data[i]; 546 547 data->sc = sc; /* Backpointer for callbacks. */ 548 549 data->xfer = usbd_alloc_xfer(sc->sc_udev); 550 if (data->xfer == NULL) { 551 aprint_error_dev(sc->sc_dev, 552 "could not allocate xfer\n"); 553 error = ENOMEM; 554 break; 555 } 556 557 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 558 if (data->buf == NULL) { 559 aprint_error_dev(sc->sc_dev, 560 "could not allocate xfer buffer\n"); 561 error = ENOMEM; 562 break; 563 } 564 } 565 if (error != 0) 566 urtwn_free_rx_list(sc); 567 return (error); 568 } 569 570 static void 571 urtwn_free_rx_list(struct urtwn_softc *sc) 572 { 573 int i; 574 575 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 576 577 /* NB: Caller must abort pipe first. */ 578 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 579 if (sc->rx_data[i].xfer != NULL) { 580 usbd_free_xfer(sc->rx_data[i].xfer); 581 sc->rx_data[i].xfer = NULL; 582 } 583 } 584 } 585 586 static int 587 urtwn_alloc_tx_list(struct urtwn_softc *sc) 588 { 589 struct urtwn_tx_data *data; 590 int i, error = 0; 591 592 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 593 594 TAILQ_INIT(&sc->tx_free_list); 595 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 596 data = &sc->tx_data[i]; 597 598 data->sc = sc; /* Backpointer for callbacks. */ 599 600 data->xfer = usbd_alloc_xfer(sc->sc_udev); 601 if (data->xfer == NULL) { 602 aprint_error_dev(sc->sc_dev, 603 "could not allocate xfer\n"); 604 error = ENOMEM; 605 goto fail; 606 } 607 608 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 609 if (data->buf == NULL) { 610 aprint_error_dev(sc->sc_dev, 611 "could not allocate xfer buffer\n"); 612 error = ENOMEM; 613 goto fail; 614 } 615 616 /* Append this Tx buffer to our free list. */ 617 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 618 } 619 return (0); 620 621 fail: 622 urtwn_free_tx_list(sc); 623 return (error); 624 } 625 626 static void 627 urtwn_free_tx_list(struct urtwn_softc *sc) 628 { 629 struct urtwn_tx_data *data; 630 int i; 631 632 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 633 634 /* NB: Caller must abort pipe first. */ 635 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 636 data = &sc->tx_data[i]; 637 638 if (data->xfer != NULL) { 639 usbd_free_xfer(data->xfer); 640 data->xfer = NULL; 641 } 642 } 643 } 644 645 static void 646 urtwn_task(void *arg) 647 { 648 struct urtwn_softc *sc = arg; 649 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 650 struct urtwn_host_cmd *cmd; 651 int s; 652 653 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 654 655 /* Process host commands. */ 656 s = splusb(); 657 mutex_spin_enter(&sc->sc_task_mtx); 658 while (ring->next != ring->cur) { 659 cmd = &ring->cmd[ring->next]; 660 mutex_spin_exit(&sc->sc_task_mtx); 661 splx(s); 662 /* Invoke callback. */ 663 cmd->cb(sc, cmd->data); 664 s = splusb(); 665 mutex_spin_enter(&sc->sc_task_mtx); 666 ring->queued--; 667 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 668 } 669 mutex_spin_exit(&sc->sc_task_mtx); 670 wakeup(&sc->cmdq); 671 splx(s); 672 } 673 674 static void 675 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 676 void *arg, int len) 677 { 678 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 679 struct urtwn_host_cmd *cmd; 680 int s; 681 682 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 683 device_xname(sc->sc_dev), __func__, cb, arg, len)); 684 685 s = splusb(); 686 mutex_spin_enter(&sc->sc_task_mtx); 687 cmd = &ring->cmd[ring->cur]; 688 cmd->cb = cb; 689 KASSERT(len <= sizeof(cmd->data)); 690 memcpy(cmd->data, arg, len); 691 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 692 693 /* If there is no pending command already, schedule a task. */ 694 if (!sc->sc_dying && ++ring->queued == 1) { 695 mutex_spin_exit(&sc->sc_task_mtx); 696 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 697 } else 698 mutex_spin_exit(&sc->sc_task_mtx); 699 splx(s); 700 } 701 702 static void 703 urtwn_wait_async(struct urtwn_softc *sc) 704 { 705 706 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 707 708 /* Wait for all queued asynchronous commands to complete. */ 709 while (sc->cmdq.queued > 0) 710 tsleep(&sc->cmdq, 0, "endtask", 0); 711 } 712 713 static int 714 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 715 int len) 716 { 717 usb_device_request_t req; 718 usbd_status error; 719 720 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 721 req.bRequest = R92C_REQ_REGS; 722 USETW(req.wValue, addr); 723 USETW(req.wIndex, 0); 724 USETW(req.wLength, len); 725 error = usbd_do_request(sc->sc_udev, &req, buf); 726 if (error != USBD_NORMAL_COMPLETION) { 727 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 728 device_xname(sc->sc_dev), __func__, error, addr, len)); 729 } 730 return (error); 731 } 732 733 static void 734 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 735 { 736 737 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 738 device_xname(sc->sc_dev), __func__, addr, val)); 739 740 urtwn_write_region_1(sc, addr, &val, 1); 741 } 742 743 static void 744 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 745 { 746 uint8_t buf[2]; 747 748 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 749 device_xname(sc->sc_dev), __func__, addr, val)); 750 751 buf[0] = (uint8_t)val; 752 buf[1] = (uint8_t)(val >> 8); 753 urtwn_write_region_1(sc, addr, buf, 2); 754 } 755 756 static void 757 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 758 { 759 uint8_t buf[4]; 760 761 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 762 device_xname(sc->sc_dev), __func__, addr, val)); 763 764 buf[0] = (uint8_t)val; 765 buf[1] = (uint8_t)(val >> 8); 766 buf[2] = (uint8_t)(val >> 16); 767 buf[3] = (uint8_t)(val >> 24); 768 urtwn_write_region_1(sc, addr, buf, 4); 769 } 770 771 static int 772 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 773 { 774 775 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 776 device_xname(sc->sc_dev), __func__, addr, len)); 777 778 return urtwn_write_region_1(sc, addr, buf, len); 779 } 780 781 static int 782 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 783 int len) 784 { 785 usb_device_request_t req; 786 usbd_status error; 787 788 req.bmRequestType = UT_READ_VENDOR_DEVICE; 789 req.bRequest = R92C_REQ_REGS; 790 USETW(req.wValue, addr); 791 USETW(req.wIndex, 0); 792 USETW(req.wLength, len); 793 error = usbd_do_request(sc->sc_udev, &req, buf); 794 if (error != USBD_NORMAL_COMPLETION) { 795 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 796 device_xname(sc->sc_dev), __func__, error, addr, len)); 797 } 798 return (error); 799 } 800 801 static uint8_t 802 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 803 { 804 uint8_t val; 805 806 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 807 return (0xff); 808 809 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 810 device_xname(sc->sc_dev), __func__, addr, val)); 811 return (val); 812 } 813 814 static uint16_t 815 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 816 { 817 uint8_t buf[2]; 818 uint16_t val; 819 820 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 821 return (0xffff); 822 823 val = LE_READ_2(&buf[0]); 824 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 825 device_xname(sc->sc_dev), __func__, addr, val)); 826 return (val); 827 } 828 829 static uint32_t 830 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 831 { 832 uint8_t buf[4]; 833 uint32_t val; 834 835 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 836 return (0xffffffff); 837 838 val = LE_READ_4(&buf[0]); 839 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 840 device_xname(sc->sc_dev), __func__, addr, val)); 841 return (val); 842 } 843 844 static int 845 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 846 { 847 struct r92c_fw_cmd cmd; 848 uint8_t *cp; 849 int fwcur; 850 int ntries; 851 852 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 853 device_xname(sc->sc_dev), __func__, id, buf, len)); 854 855 mutex_enter(&sc->sc_fwcmd_mtx); 856 fwcur = sc->fwcur; 857 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 858 mutex_exit(&sc->sc_fwcmd_mtx); 859 860 /* Wait for current FW box to be empty. */ 861 for (ntries = 0; ntries < 100; ntries++) { 862 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 863 break; 864 DELAY(1); 865 } 866 if (ntries == 100) { 867 aprint_error_dev(sc->sc_dev, 868 "could not send firmware command %d\n", id); 869 return (ETIMEDOUT); 870 } 871 872 memset(&cmd, 0, sizeof(cmd)); 873 KASSERT(len <= sizeof(cmd.msg)); 874 memcpy(cmd.msg, buf, len); 875 876 /* Write the first word last since that will trigger the FW. */ 877 cp = (uint8_t *)&cmd; 878 if (len >= 4) { 879 cmd.id = id | R92C_CMD_FLAG_EXT; 880 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 881 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 882 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 883 } else { 884 cmd.id = id; 885 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 886 } 887 888 return (0); 889 } 890 891 static void 892 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 893 { 894 895 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 896 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 897 } 898 899 static uint32_t 900 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 901 { 902 uint32_t reg[R92C_MAX_CHAINS], val; 903 904 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 905 if (chain != 0) { 906 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 907 } 908 909 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 910 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 911 DELAY(1000); 912 913 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 914 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 915 R92C_HSSI_PARAM2_READ_EDGE); 916 DELAY(1000); 917 918 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 919 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 920 DELAY(1000); 921 922 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 923 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 924 } else { 925 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 926 } 927 return (MS(val, R92C_LSSI_READBACK_DATA)); 928 } 929 930 static int 931 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 932 { 933 int ntries; 934 935 urtwn_write_4(sc, R92C_LLT_INIT, 936 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 937 SM(R92C_LLT_INIT_ADDR, addr) | 938 SM(R92C_LLT_INIT_DATA, data)); 939 /* Wait for write operation to complete. */ 940 for (ntries = 0; ntries < 20; ntries++) { 941 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 942 R92C_LLT_INIT_OP_NO_ACTIVE) { 943 /* Done */ 944 return (0); 945 } 946 DELAY(5); 947 } 948 return (ETIMEDOUT); 949 } 950 951 static uint8_t 952 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 953 { 954 uint32_t reg; 955 int ntries; 956 957 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 958 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 959 reg &= ~R92C_EFUSE_CTRL_VALID; 960 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 961 962 /* Wait for read operation to complete. */ 963 for (ntries = 0; ntries < 100; ntries++) { 964 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 965 if (reg & R92C_EFUSE_CTRL_VALID) { 966 /* Done */ 967 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 968 } 969 DELAY(5); 970 } 971 aprint_error_dev(sc->sc_dev, 972 "could not read efuse byte at address 0x%04x\n", addr); 973 return (0xff); 974 } 975 976 static void 977 urtwn_efuse_read(struct urtwn_softc *sc) 978 { 979 uint8_t *rom = (uint8_t *)&sc->rom; 980 uint32_t reg; 981 uint16_t addr = 0; 982 uint8_t off, msk; 983 int i; 984 985 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 986 987 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 988 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 989 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 990 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 991 } 992 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 993 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 994 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 995 reg | R92C_SYS_FUNC_EN_ELDR); 996 } 997 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 998 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 999 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1000 urtwn_write_2(sc, R92C_SYS_CLKR, 1001 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1002 } 1003 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1004 while (addr < 512) { 1005 reg = urtwn_efuse_read_1(sc, addr); 1006 if (reg == 0xff) 1007 break; 1008 addr++; 1009 off = reg >> 4; 1010 msk = reg & 0xf; 1011 for (i = 0; i < 4; i++) { 1012 if (msk & (1U << i)) 1013 continue; 1014 1015 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1016 addr++; 1017 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1018 addr++; 1019 } 1020 } 1021 #ifdef URTWN_DEBUG 1022 if (urtwn_debug & DBG_INIT) { 1023 /* Dump ROM content. */ 1024 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1025 for (i = 0; i < (int)sizeof(sc->rom); i++) 1026 printf(":%02x", rom[i]); 1027 printf("\n"); 1028 } 1029 #endif 1030 } 1031 1032 static int 1033 urtwn_read_chipid(struct urtwn_softc *sc) 1034 { 1035 uint32_t reg; 1036 1037 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1038 1039 sc->chip = 0; 1040 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1041 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1042 /* test chip, not supported */ 1043 return (EIO); 1044 } 1045 if (reg & R92C_SYS_CFG_TYPE_92C) { 1046 sc->chip |= URTWN_CHIP_92C; 1047 /* Check if it is a castrated 8192C. */ 1048 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1049 R92C_HPON_FSM_CHIP_BONDING_ID) == 1050 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1051 sc->chip |= URTWN_CHIP_92C_1T2R; 1052 } 1053 } 1054 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1055 sc->chip |= URTWN_CHIP_UMC; 1056 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1057 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1058 } 1059 } 1060 return (0); 1061 } 1062 1063 #ifdef URTWN_DEBUG 1064 static void 1065 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1066 { 1067 1068 aprint_normal_dev(sc->sc_dev, 1069 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1070 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1071 1072 aprint_normal_dev(sc->sc_dev, 1073 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1074 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1075 1076 aprint_normal_dev(sc->sc_dev, 1077 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1078 rp->macaddr[0], rp->macaddr[1], 1079 rp->macaddr[2], rp->macaddr[3], 1080 rp->macaddr[4], rp->macaddr[5]); 1081 1082 aprint_normal_dev(sc->sc_dev, 1083 "string %s, subcustomer_id 0x%x\n", 1084 rp->string, rp->subcustomer_id); 1085 1086 aprint_normal_dev(sc->sc_dev, 1087 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1088 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1089 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1090 1091 aprint_normal_dev(sc->sc_dev, 1092 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1093 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1094 rp->ht40_1s_tx_pwr[0][2], 1095 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1096 rp->ht40_1s_tx_pwr[1][2]); 1097 1098 aprint_normal_dev(sc->sc_dev, 1099 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1100 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1101 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1102 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1103 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1104 1105 aprint_normal_dev(sc->sc_dev, 1106 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1107 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1108 rp->ht20_tx_pwr_diff[2] & 0xf, 1109 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1110 rp->ht20_tx_pwr_diff[2] >> 4); 1111 1112 aprint_normal_dev(sc->sc_dev, 1113 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1114 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1115 rp->ofdm_tx_pwr_diff[2] & 0xf, 1116 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1117 rp->ofdm_tx_pwr_diff[2] >> 4); 1118 1119 aprint_normal_dev(sc->sc_dev, 1120 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1121 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1122 rp->ht40_max_pwr[2] & 0xf, 1123 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1124 rp->ht40_max_pwr[2] >> 4); 1125 1126 aprint_normal_dev(sc->sc_dev, 1127 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1128 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1129 rp->ht20_max_pwr[2] & 0xf, 1130 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1131 rp->ht20_max_pwr[2] >> 4); 1132 1133 aprint_normal_dev(sc->sc_dev, 1134 "xtal_calib %d, tssi %d %d, thermal %d\n", 1135 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1136 1137 aprint_normal_dev(sc->sc_dev, 1138 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1139 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1140 1141 aprint_normal_dev(sc->sc_dev, 1142 "channnel_plan %d, version %d customer_id 0x%x\n", 1143 rp->channel_plan, rp->version, rp->curstomer_id); 1144 } 1145 #endif 1146 1147 static void 1148 urtwn_read_rom(struct urtwn_softc *sc) 1149 { 1150 struct ieee80211com *ic = &sc->sc_ic; 1151 struct r92c_rom *rom = &sc->rom; 1152 1153 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1154 1155 /* Read full ROM image. */ 1156 urtwn_efuse_read(sc); 1157 #ifdef URTWN_DEBUG 1158 if (urtwn_debug & DBG_REG) 1159 urtwn_dump_rom(sc, rom); 1160 #endif 1161 1162 /* XXX Weird but this is what the vendor driver does. */ 1163 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1164 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1165 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1166 1167 DPRINTFN(DBG_INIT, 1168 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1169 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1170 sc->board_type, sc->regulatory)); 1171 1172 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1173 } 1174 1175 static int 1176 urtwn_media_change(struct ifnet *ifp) 1177 { 1178 #ifdef URTWN_DEBUG 1179 struct urtwn_softc *sc = ifp->if_softc; 1180 #endif 1181 int error; 1182 1183 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1184 1185 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1186 return (error); 1187 1188 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1189 (IFF_UP | IFF_RUNNING)) { 1190 urtwn_init(ifp); 1191 } 1192 return (0); 1193 } 1194 1195 /* 1196 * Initialize rate adaptation in firmware. 1197 */ 1198 static int 1199 urtwn_ra_init(struct urtwn_softc *sc) 1200 { 1201 static const uint8_t map[] = { 1202 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1203 }; 1204 struct ieee80211com *ic = &sc->sc_ic; 1205 struct ieee80211_node *ni = ic->ic_bss; 1206 struct ieee80211_rateset *rs = &ni->ni_rates; 1207 struct r92c_fw_cmd_macid_cfg cmd; 1208 uint32_t rates, basicrates; 1209 uint32_t mask; 1210 uint8_t mode; 1211 int maxrate, maxbasicrate, error, i, j; 1212 1213 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1214 1215 /* Get normal and basic rates mask. */ 1216 rates = basicrates = 0; 1217 maxrate = maxbasicrate = 0; 1218 for (i = 0; i < rs->rs_nrates; i++) { 1219 /* Convert 802.11 rate to HW rate index. */ 1220 for (j = 0; j < (int)__arraycount(map); j++) { 1221 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1222 break; 1223 } 1224 } 1225 if (j == __arraycount(map)) { 1226 /* Unknown rate, skip. */ 1227 continue; 1228 } 1229 1230 rates |= 1U << j; 1231 if (j > maxrate) { 1232 maxrate = j; 1233 } 1234 1235 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1236 basicrates |= 1U << j; 1237 if (j > maxbasicrate) { 1238 maxbasicrate = j; 1239 } 1240 } 1241 } 1242 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1243 mode = R92C_RAID_11B; 1244 } else { 1245 mode = R92C_RAID_11BG; 1246 } 1247 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1248 "maxrate=%x, maxbasicrate=%x\n", 1249 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1250 maxrate, maxbasicrate)); 1251 if (basicrates == 0) { 1252 basicrates |= 1; /* add 1Mbps */ 1253 } 1254 1255 /* Set rates mask for group addressed frames. */ 1256 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1257 mask = (mode << 28) | basicrates; 1258 cmd.mask[0] = (uint8_t)mask; 1259 cmd.mask[1] = (uint8_t)(mask >> 8); 1260 cmd.mask[2] = (uint8_t)(mask >> 16); 1261 cmd.mask[3] = (uint8_t)(mask >> 24); 1262 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1263 if (error != 0) { 1264 aprint_error_dev(sc->sc_dev, 1265 "could not add broadcast station\n"); 1266 return (error); 1267 } 1268 /* Set initial MRR rate. */ 1269 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", 1270 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1271 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1272 1273 /* Set rates mask for unicast frames. */ 1274 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1275 mask = (mode << 28) | rates; 1276 cmd.mask[0] = (uint8_t)mask; 1277 cmd.mask[1] = (uint8_t)(mask >> 8); 1278 cmd.mask[2] = (uint8_t)(mask >> 16); 1279 cmd.mask[3] = (uint8_t)(mask >> 24); 1280 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1281 if (error != 0) { 1282 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1283 return (error); 1284 } 1285 /* Set initial MRR rate. */ 1286 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), 1287 __func__, maxrate)); 1288 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1289 1290 /* Indicate highest supported rate. */ 1291 ni->ni_txrate = rs->rs_nrates - 1; 1292 1293 return (0); 1294 } 1295 1296 static int 1297 urtwn_get_nettype(struct urtwn_softc *sc) 1298 { 1299 struct ieee80211com *ic = &sc->sc_ic; 1300 int type; 1301 1302 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1303 1304 switch (ic->ic_opmode) { 1305 case IEEE80211_M_STA: 1306 type = R92C_CR_NETTYPE_INFRA; 1307 break; 1308 1309 case IEEE80211_M_IBSS: 1310 type = R92C_CR_NETTYPE_ADHOC; 1311 break; 1312 1313 default: 1314 type = R92C_CR_NETTYPE_NOLINK; 1315 break; 1316 } 1317 1318 return (type); 1319 } 1320 1321 static void 1322 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1323 { 1324 uint8_t reg; 1325 1326 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1327 __func__, type)); 1328 1329 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1330 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1331 } 1332 1333 static void 1334 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1335 { 1336 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1337 uint64_t tsf; 1338 1339 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1340 1341 /* Enable TSF synchronization. */ 1342 urtwn_write_1(sc, R92C_BCN_CTRL, 1343 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1344 1345 /* Correct TSF */ 1346 urtwn_write_1(sc, R92C_BCN_CTRL, 1347 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1348 1349 /* Set initial TSF. */ 1350 tsf = ni->ni_tstamp.tsf; 1351 tsf = le64toh(tsf); 1352 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1353 tsf -= IEEE80211_DUR_TU; 1354 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1355 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1356 1357 urtwn_write_1(sc, R92C_BCN_CTRL, 1358 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1359 } 1360 1361 static void 1362 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1363 { 1364 uint8_t reg; 1365 1366 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1367 __func__, led, on)); 1368 1369 if (led == URTWN_LED_LINK) { 1370 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1371 if (!on) { 1372 reg |= R92C_LEDCFG0_DIS; 1373 } 1374 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1375 sc->ledlink = on; /* Save LED state. */ 1376 } 1377 } 1378 1379 static void 1380 urtwn_calib_to(void *arg) 1381 { 1382 struct urtwn_softc *sc = arg; 1383 1384 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1385 1386 if (sc->sc_dying) 1387 return; 1388 1389 /* Do it in a process context. */ 1390 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1391 } 1392 1393 /* ARGSUSED */ 1394 static void 1395 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1396 { 1397 struct r92c_fw_cmd_rssi cmd; 1398 1399 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1400 1401 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1402 goto restart_timer; 1403 1404 if (sc->avg_pwdb != -1) { 1405 /* Indicate Rx signal strength to FW for rate adaptation. */ 1406 memset(&cmd, 0, sizeof(cmd)); 1407 cmd.macid = 0; /* BSS. */ 1408 cmd.pwdb = sc->avg_pwdb; 1409 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1410 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1411 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1412 } 1413 1414 /* Do temperature compensation. */ 1415 urtwn_temp_calib(sc); 1416 1417 restart_timer: 1418 if (!sc->sc_dying) { 1419 /* Restart calibration timer. */ 1420 callout_schedule(&sc->sc_calib_to, hz); 1421 } 1422 } 1423 1424 static void 1425 urtwn_next_scan(void *arg) 1426 { 1427 struct urtwn_softc *sc = arg; 1428 1429 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1430 1431 if (sc->sc_dying) 1432 return; 1433 1434 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1435 ieee80211_next_scan(&sc->sc_ic); 1436 } 1437 1438 static int 1439 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1440 { 1441 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1442 struct urtwn_cmd_newstate cmd; 1443 1444 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1445 device_xname(sc->sc_dev), __func__, 1446 ieee80211_state_name[nstate], nstate, arg)); 1447 1448 callout_stop(&sc->sc_scan_to); 1449 callout_stop(&sc->sc_calib_to); 1450 1451 /* Do it in a process context. */ 1452 cmd.state = nstate; 1453 cmd.arg = arg; 1454 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1455 return (0); 1456 } 1457 1458 static void 1459 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1460 { 1461 struct urtwn_cmd_newstate *cmd = arg; 1462 struct ieee80211com *ic = &sc->sc_ic; 1463 struct ieee80211_node *ni; 1464 enum ieee80211_state ostate = ic->ic_state; 1465 enum ieee80211_state nstate = cmd->state; 1466 uint32_t reg; 1467 uint8_t sifs_time; 1468 int s; 1469 1470 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1471 device_xname(sc->sc_dev), __func__, 1472 ieee80211_state_name[ostate], ostate, 1473 ieee80211_state_name[nstate], nstate)); 1474 1475 s = splnet(); 1476 1477 switch (ostate) { 1478 case IEEE80211_S_INIT: 1479 break; 1480 1481 case IEEE80211_S_SCAN: 1482 if (nstate != IEEE80211_S_SCAN) { 1483 /* 1484 * End of scanning 1485 */ 1486 /* flush 4-AC Queue after site_survey */ 1487 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1488 1489 /* Allow Rx from our BSSID only. */ 1490 urtwn_write_4(sc, R92C_RCR, 1491 urtwn_read_4(sc, R92C_RCR) | 1492 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1493 } 1494 break; 1495 1496 case IEEE80211_S_AUTH: 1497 case IEEE80211_S_ASSOC: 1498 break; 1499 1500 case IEEE80211_S_RUN: 1501 /* Turn link LED off. */ 1502 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1503 1504 /* Set media status to 'No Link'. */ 1505 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1506 1507 /* Stop Rx of data frames. */ 1508 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1509 1510 /* Reset TSF. */ 1511 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1512 1513 /* Disable TSF synchronization. */ 1514 urtwn_write_1(sc, R92C_BCN_CTRL, 1515 urtwn_read_1(sc, R92C_BCN_CTRL) | 1516 R92C_BCN_CTRL_DIS_TSF_UDT0); 1517 1518 /* Back to 20MHz mode */ 1519 urtwn_set_chan(sc, ic->ic_bss->ni_chan, 1520 IEEE80211_HTINFO_2NDCHAN_NONE); 1521 1522 if (ic->ic_opmode == IEEE80211_M_IBSS || 1523 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1524 /* Stop BCN */ 1525 urtwn_write_1(sc, R92C_BCN_CTRL, 1526 urtwn_read_1(sc, R92C_BCN_CTRL) & 1527 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1528 } 1529 1530 /* Reset EDCA parameters. */ 1531 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1532 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1533 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1534 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1535 1536 /* flush all cam entries */ 1537 urtwn_cam_init(sc); 1538 break; 1539 } 1540 1541 switch (nstate) { 1542 case IEEE80211_S_INIT: 1543 /* Turn link LED off. */ 1544 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1545 break; 1546 1547 case IEEE80211_S_SCAN: 1548 if (ostate != IEEE80211_S_SCAN) { 1549 /* 1550 * Begin of scanning 1551 */ 1552 1553 /* Set gain for scanning. */ 1554 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1555 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1556 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1557 1558 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1559 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1560 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1561 1562 /* Set media status to 'No Link'. */ 1563 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1564 1565 /* Allow Rx from any BSSID. */ 1566 urtwn_write_4(sc, R92C_RCR, 1567 urtwn_read_4(sc, R92C_RCR) & 1568 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1569 1570 /* Stop Rx of data frames. */ 1571 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1572 1573 /* Disable update TSF */ 1574 urtwn_write_1(sc, R92C_BCN_CTRL, 1575 urtwn_read_1(sc, R92C_BCN_CTRL) | 1576 R92C_BCN_CTRL_DIS_TSF_UDT0); 1577 } 1578 1579 /* Make link LED blink during scan. */ 1580 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1581 1582 /* Pause AC Tx queues. */ 1583 urtwn_write_1(sc, R92C_TXPAUSE, 1584 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1585 1586 urtwn_set_chan(sc, ic->ic_curchan, 1587 IEEE80211_HTINFO_2NDCHAN_NONE); 1588 1589 /* Start periodic scan. */ 1590 if (!sc->sc_dying) 1591 callout_schedule(&sc->sc_scan_to, hz / 5); 1592 break; 1593 1594 case IEEE80211_S_AUTH: 1595 /* Set initial gain under link. */ 1596 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1597 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1598 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1599 1600 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1601 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1602 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1603 1604 /* Set media status to 'No Link'. */ 1605 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1606 1607 /* Allow Rx from any BSSID. */ 1608 urtwn_write_4(sc, R92C_RCR, 1609 urtwn_read_4(sc, R92C_RCR) & 1610 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1611 1612 urtwn_set_chan(sc, ic->ic_curchan, 1613 IEEE80211_HTINFO_2NDCHAN_NONE); 1614 break; 1615 1616 case IEEE80211_S_ASSOC: 1617 break; 1618 1619 case IEEE80211_S_RUN: 1620 ni = ic->ic_bss; 1621 1622 /* XXX: Set 20MHz mode */ 1623 urtwn_set_chan(sc, ic->ic_curchan, 1624 IEEE80211_HTINFO_2NDCHAN_NONE); 1625 1626 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1627 /* Back to 20MHz mode */ 1628 urtwn_set_chan(sc, ic->ic_ibss_chan, 1629 IEEE80211_HTINFO_2NDCHAN_NONE); 1630 1631 /* Enable Rx of data frames. */ 1632 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1633 1634 /* Turn link LED on. */ 1635 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1636 break; 1637 } 1638 1639 /* Set media status to 'Associated'. */ 1640 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1641 1642 /* Set BSSID. */ 1643 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1644 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1645 1646 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1647 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1648 } else { 1649 /* 802.11b/g */ 1650 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1651 } 1652 1653 /* Enable Rx of data frames. */ 1654 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1655 1656 /* Set beacon interval. */ 1657 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1658 1659 if (ic->ic_opmode == IEEE80211_M_STA) { 1660 /* Allow Rx from our BSSID only. */ 1661 urtwn_write_4(sc, R92C_RCR, 1662 urtwn_read_4(sc, R92C_RCR) | 1663 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1664 1665 /* Enable TSF synchronization. */ 1666 urtwn_tsf_sync_enable(sc); 1667 } 1668 1669 sifs_time = 10; 1670 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1671 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1672 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1673 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1674 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1675 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1676 1677 /* Intialize rate adaptation. */ 1678 urtwn_ra_init(sc); 1679 1680 /* Turn link LED on. */ 1681 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1682 1683 /* Reset average RSSI. */ 1684 sc->avg_pwdb = -1; 1685 1686 /* Reset temperature calibration state machine. */ 1687 sc->thcal_state = 0; 1688 sc->thcal_lctemp = 0; 1689 1690 /* Start periodic calibration. */ 1691 if (!sc->sc_dying) 1692 callout_schedule(&sc->sc_calib_to, hz); 1693 break; 1694 } 1695 1696 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1697 1698 splx(s); 1699 } 1700 1701 static int 1702 urtwn_wme_update(struct ieee80211com *ic) 1703 { 1704 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1705 1706 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1707 1708 /* don't override default WME values if WME is not actually enabled */ 1709 if (!(ic->ic_flags & IEEE80211_F_WME)) 1710 return (0); 1711 1712 /* Do it in a process context. */ 1713 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1714 return (0); 1715 } 1716 1717 static void 1718 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1719 { 1720 static const uint16_t ac2reg[WME_NUM_AC] = { 1721 R92C_EDCA_BE_PARAM, 1722 R92C_EDCA_BK_PARAM, 1723 R92C_EDCA_VI_PARAM, 1724 R92C_EDCA_VO_PARAM 1725 }; 1726 struct ieee80211com *ic = &sc->sc_ic; 1727 const struct wmeParams *wmep; 1728 int ac, aifs, slottime; 1729 int s; 1730 1731 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1732 __func__)); 1733 1734 s = splnet(); 1735 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1736 for (ac = 0; ac < WME_NUM_AC; ac++) { 1737 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1738 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1739 aifs = wmep->wmep_aifsn * slottime + 10; 1740 urtwn_write_4(sc, ac2reg[ac], 1741 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1742 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1743 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1744 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1745 } 1746 splx(s); 1747 } 1748 1749 static void 1750 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1751 { 1752 int pwdb; 1753 1754 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1755 device_xname(sc->sc_dev), __func__, rate, rssi)); 1756 1757 /* Convert antenna signal to percentage. */ 1758 if (rssi <= -100 || rssi >= 20) 1759 pwdb = 0; 1760 else if (rssi >= 0) 1761 pwdb = 100; 1762 else 1763 pwdb = 100 + rssi; 1764 if (rate <= 3) { 1765 /* CCK gain is smaller than OFDM/MCS gain. */ 1766 pwdb += 6; 1767 if (pwdb > 100) 1768 pwdb = 100; 1769 if (pwdb <= 14) 1770 pwdb -= 4; 1771 else if (pwdb <= 26) 1772 pwdb -= 8; 1773 else if (pwdb <= 34) 1774 pwdb -= 6; 1775 else if (pwdb <= 42) 1776 pwdb -= 2; 1777 } 1778 if (sc->avg_pwdb == -1) /* Init. */ 1779 sc->avg_pwdb = pwdb; 1780 else if (sc->avg_pwdb < pwdb) 1781 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1782 else 1783 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1784 1785 DPRINTFN(DBG_RF, ("%s: %s: PWDB=%d EMA=%d\n", device_xname(sc->sc_dev), 1786 __func__, pwdb, sc->avg_pwdb)); 1787 } 1788 1789 static int8_t 1790 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1791 { 1792 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1793 struct r92c_rx_phystat *phy; 1794 struct r92c_rx_cck *cck; 1795 uint8_t rpt; 1796 int8_t rssi; 1797 1798 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1799 __func__, rate)); 1800 1801 if (rate <= 3) { 1802 cck = (struct r92c_rx_cck *)physt; 1803 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1804 rpt = (cck->agc_rpt >> 5) & 0x3; 1805 rssi = (cck->agc_rpt & 0x1f) << 1; 1806 } else { 1807 rpt = (cck->agc_rpt >> 6) & 0x3; 1808 rssi = cck->agc_rpt & 0x3e; 1809 } 1810 rssi = cckoff[rpt] - rssi; 1811 } else { /* OFDM/HT. */ 1812 phy = (struct r92c_rx_phystat *)physt; 1813 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1814 } 1815 return (rssi); 1816 } 1817 1818 static void 1819 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1820 { 1821 struct ieee80211com *ic = &sc->sc_ic; 1822 struct ifnet *ifp = ic->ic_ifp; 1823 struct ieee80211_frame *wh; 1824 struct ieee80211_node *ni; 1825 struct r92c_rx_stat *stat; 1826 uint32_t rxdw0, rxdw3; 1827 struct mbuf *m; 1828 uint8_t rate; 1829 int8_t rssi = 0; 1830 int s, infosz; 1831 1832 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1833 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1834 1835 stat = (struct r92c_rx_stat *)buf; 1836 rxdw0 = le32toh(stat->rxdw0); 1837 rxdw3 = le32toh(stat->rxdw3); 1838 1839 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1840 /* 1841 * This should not happen since we setup our Rx filter 1842 * to not receive these frames. 1843 */ 1844 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1845 device_xname(sc->sc_dev), __func__)); 1846 ifp->if_ierrors++; 1847 return; 1848 } 1849 if (__predict_false(pktlen < (int)sizeof(*wh))) { 1850 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1851 device_xname(sc->sc_dev), __func__, pktlen)); 1852 ic->ic_stats.is_rx_tooshort++; 1853 ifp->if_ierrors++; 1854 return; 1855 } 1856 if (__predict_false(pktlen > MCLBYTES)) { 1857 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1858 device_xname(sc->sc_dev), __func__, pktlen)); 1859 ifp->if_ierrors++; 1860 return; 1861 } 1862 1863 rate = MS(rxdw3, R92C_RXDW3_RATE); 1864 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1865 1866 /* Get RSSI from PHY status descriptor if present. */ 1867 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1868 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1869 /* Update our average RSSI. */ 1870 urtwn_update_avgrssi(sc, rate, rssi); 1871 } 1872 1873 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1874 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1875 1876 MGETHDR(m, M_DONTWAIT, MT_DATA); 1877 if (__predict_false(m == NULL)) { 1878 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1879 ic->ic_stats.is_rx_nobuf++; 1880 ifp->if_ierrors++; 1881 return; 1882 } 1883 if (pktlen > (int)MHLEN) { 1884 MCLGET(m, M_DONTWAIT); 1885 if (__predict_false(!(m->m_flags & M_EXT))) { 1886 aprint_error_dev(sc->sc_dev, 1887 "couldn't allocate rx mbuf cluster\n"); 1888 m_freem(m); 1889 ic->ic_stats.is_rx_nobuf++; 1890 ifp->if_ierrors++; 1891 return; 1892 } 1893 } 1894 1895 /* Finalize mbuf. */ 1896 m->m_pkthdr.rcvif = ifp; 1897 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1898 memcpy(mtod(m, uint8_t *), wh, pktlen); 1899 m->m_pkthdr.len = m->m_len = pktlen; 1900 1901 s = splnet(); 1902 if (__predict_false(sc->sc_drvbpf != NULL)) { 1903 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1904 1905 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1906 if (!(rxdw3 & R92C_RXDW3_HT)) { 1907 switch (rate) { 1908 /* CCK. */ 1909 case 0: tap->wr_rate = 2; break; 1910 case 1: tap->wr_rate = 4; break; 1911 case 2: tap->wr_rate = 11; break; 1912 case 3: tap->wr_rate = 22; break; 1913 /* OFDM. */ 1914 case 4: tap->wr_rate = 12; break; 1915 case 5: tap->wr_rate = 18; break; 1916 case 6: tap->wr_rate = 24; break; 1917 case 7: tap->wr_rate = 36; break; 1918 case 8: tap->wr_rate = 48; break; 1919 case 9: tap->wr_rate = 72; break; 1920 case 10: tap->wr_rate = 96; break; 1921 case 11: tap->wr_rate = 108; break; 1922 } 1923 } else if (rate >= 12) { /* MCS0~15. */ 1924 /* Bit 7 set means HT MCS instead of rate. */ 1925 tap->wr_rate = 0x80 | (rate - 12); 1926 } 1927 tap->wr_dbm_antsignal = rssi; 1928 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1929 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1930 1931 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1932 } 1933 1934 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1935 1936 /* push the frame up to the 802.11 stack */ 1937 ieee80211_input(ic, m, ni, rssi, 0); 1938 1939 /* Node is no longer needed. */ 1940 ieee80211_free_node(ni); 1941 1942 splx(s); 1943 } 1944 1945 static void 1946 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1947 { 1948 struct urtwn_rx_data *data = priv; 1949 struct urtwn_softc *sc = data->sc; 1950 struct r92c_rx_stat *stat; 1951 uint32_t rxdw0; 1952 uint8_t *buf; 1953 int len, totlen, pktlen, infosz, npkts; 1954 1955 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 1956 device_xname(sc->sc_dev), __func__, status)); 1957 1958 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1959 if (status == USBD_STALLED) 1960 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1961 else if (status != USBD_CANCELLED) 1962 goto resubmit; 1963 return; 1964 } 1965 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1966 1967 if (__predict_false(len < (int)sizeof(*stat))) { 1968 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 1969 device_xname(sc->sc_dev), __func__, len)); 1970 goto resubmit; 1971 } 1972 buf = data->buf; 1973 1974 /* Get the number of encapsulated frames. */ 1975 stat = (struct r92c_rx_stat *)buf; 1976 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 1977 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 1978 device_xname(sc->sc_dev), __func__, npkts)); 1979 1980 /* Process all of them. */ 1981 while (npkts-- > 0) { 1982 if (__predict_false(len < (int)sizeof(*stat))) { 1983 DPRINTFN(DBG_RX, 1984 ("%s: %s: len(%d) is short than header\n", 1985 device_xname(sc->sc_dev), __func__, len)); 1986 break; 1987 } 1988 stat = (struct r92c_rx_stat *)buf; 1989 rxdw0 = le32toh(stat->rxdw0); 1990 1991 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1992 if (__predict_false(pktlen == 0)) { 1993 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 1994 device_xname(sc->sc_dev), __func__)); 1995 break; 1996 } 1997 1998 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1999 2000 /* Make sure everything fits in xfer. */ 2001 totlen = sizeof(*stat) + infosz + pktlen; 2002 if (__predict_false(totlen > len)) { 2003 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2004 device_xname(sc->sc_dev), __func__, totlen, 2005 (int)sizeof(*stat), infosz, pktlen, len)); 2006 break; 2007 } 2008 2009 /* Process 802.11 frame. */ 2010 urtwn_rx_frame(sc, buf, pktlen); 2011 2012 /* Next chunk is 128-byte aligned. */ 2013 totlen = roundup2(totlen, 128); 2014 buf += totlen; 2015 len -= totlen; 2016 } 2017 2018 resubmit: 2019 /* Setup a new transfer. */ 2020 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 2021 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 2022 (void)usbd_transfer(xfer); 2023 } 2024 2025 static void 2026 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2027 { 2028 struct urtwn_tx_data *data = priv; 2029 struct urtwn_softc *sc = data->sc; 2030 struct ifnet *ifp = &sc->sc_if; 2031 int s; 2032 2033 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2034 device_xname(sc->sc_dev), __func__, status)); 2035 2036 mutex_enter(&sc->sc_tx_mtx); 2037 /* Put this Tx buffer back to our free list. */ 2038 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2039 mutex_exit(&sc->sc_tx_mtx); 2040 2041 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2042 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2043 if (status == USBD_STALLED) 2044 usbd_clear_endpoint_stall_async(data->pipe); 2045 ifp->if_oerrors++; 2046 } 2047 return; 2048 } 2049 2050 ifp->if_opackets++; 2051 2052 s = splnet(); 2053 sc->tx_timer = 0; 2054 ifp->if_flags &= ~IFF_OACTIVE; 2055 splx(s); 2056 2057 urtwn_start(ifp); 2058 } 2059 2060 static int 2061 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2062 { 2063 struct ieee80211com *ic = &sc->sc_ic; 2064 struct ieee80211_frame *wh; 2065 struct ieee80211_key *k = NULL; 2066 struct urtwn_tx_data *data; 2067 struct r92c_tx_desc *txd; 2068 usbd_pipe_handle pipe; 2069 uint16_t seq, sum; 2070 uint8_t raid, type, tid, qid; 2071 int i, s, hasqos, xferlen, padsize, error; 2072 2073 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2074 2075 wh = mtod(m, struct ieee80211_frame *); 2076 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2077 2078 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2079 k = ieee80211_crypto_encap(ic, ni, m); 2080 if (k == NULL) { 2081 m_freem(m); 2082 return (ENOBUFS); 2083 } 2084 /* packet header may have moved, reset our local pointer */ 2085 wh = mtod(m, struct ieee80211_frame *); 2086 } 2087 2088 if (__predict_false(sc->sc_drvbpf != NULL)) { 2089 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2090 2091 tap->wt_flags = 0; 2092 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2093 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2094 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2095 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2096 2097 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2098 } 2099 2100 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2101 /* data frames in 11n mode */ 2102 struct ieee80211_qosframe *qwh = (void *)wh; 2103 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2104 qid = TID_TO_WME_AC(tid); 2105 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2106 /* Use AC_VO for management frames. */ 2107 qid = WME_AC_VO; 2108 tid = 0; /* compiler happy */ 2109 } else { 2110 /* non-qos data frames */ 2111 tid = R92C_TXDW1_QSEL_BE; 2112 qid = WME_AC_BE; 2113 } 2114 2115 /* Get the USB pipe to use for this AC. */ 2116 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2117 2118 /* Grab a Tx buffer from our free list. */ 2119 mutex_enter(&sc->sc_tx_mtx); 2120 data = TAILQ_FIRST(&sc->tx_free_list); 2121 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2122 mutex_exit(&sc->sc_tx_mtx); 2123 2124 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2125 padsize = 8; 2126 else 2127 padsize = 0; 2128 2129 /* Fill Tx descriptor. */ 2130 txd = (struct r92c_tx_desc *)data->buf; 2131 memset(txd, 0, sizeof(*txd) + padsize); 2132 2133 txd->txdw0 |= htole32( 2134 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2135 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2136 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2137 2138 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2139 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2140 2141 /* fix pad field */ 2142 if (padsize > 0) { 2143 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", 2144 device_xname(sc->sc_dev), __func__, padsize)); 2145 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2146 } 2147 2148 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2149 type == IEEE80211_FC0_TYPE_DATA) { 2150 if (ic->ic_curmode == IEEE80211_MODE_11B) 2151 raid = R92C_RAID_11B; 2152 else 2153 raid = R92C_RAID_11BG; 2154 DPRINTFN(DBG_TX, 2155 ("%s: %s: data packet: tid=%d, raid=%d\n", 2156 device_xname(sc->sc_dev), __func__, tid, raid)); 2157 2158 txd->txdw1 |= htole32( 2159 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2160 SM(R92C_TXDW1_QSEL, tid) | 2161 SM(R92C_TXDW1_RAID, raid) | 2162 R92C_TXDW1_AGGBK); 2163 2164 if (hasqos) { 2165 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2166 } 2167 2168 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2169 /* for 11g */ 2170 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2171 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2172 R92C_TXDW4_HWRTSEN); 2173 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2174 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2175 R92C_TXDW4_HWRTSEN); 2176 } 2177 } 2178 /* Send RTS at OFDM24. */ 2179 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2180 txd->txdw5 |= htole32(0x0001ff00); 2181 /* Send data at OFDM54. */ 2182 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2183 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2184 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2185 device_xname(sc->sc_dev), __func__)); 2186 txd->txdw1 |= htole32( 2187 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2188 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2189 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2190 2191 /* Force CCK1. */ 2192 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2193 /* Use 1Mbps */ 2194 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2195 } else { 2196 /* broadcast or multicast packets */ 2197 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2198 device_xname(sc->sc_dev), __func__)); 2199 txd->txdw1 |= htole32( 2200 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2201 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2202 2203 /* Force CCK1. */ 2204 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2205 /* Use 1Mbps */ 2206 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2207 } 2208 2209 /* Set sequence number */ 2210 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2211 txd->txdseq |= htole16(seq); 2212 2213 if (!hasqos) { 2214 /* Use HW sequence numbering for non-QoS frames. */ 2215 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2216 txd->txdseq |= htole16(0x8000); /* WTF? */ 2217 } 2218 2219 /* Compute Tx descriptor checksum. */ 2220 sum = 0; 2221 for (i = 0; i < (int)sizeof(*txd) / 2; i++) 2222 sum ^= ((uint16_t *)txd)[i]; 2223 txd->txdsum = sum; /* NB: already little endian. */ 2224 2225 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2226 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2227 m_freem(m); 2228 2229 s = splnet(); 2230 data->pipe = pipe; 2231 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2232 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2233 urtwn_txeof); 2234 error = usbd_transfer(data->xfer); 2235 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2236 error != USBD_IN_PROGRESS)) { 2237 splx(s); 2238 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2239 device_xname(sc->sc_dev), __func__, error)); 2240 mutex_enter(&sc->sc_tx_mtx); 2241 /* Put this Tx buffer back to our free list. */ 2242 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2243 mutex_exit(&sc->sc_tx_mtx); 2244 return (error); 2245 } 2246 splx(s); 2247 ieee80211_free_node(ni); 2248 return (0); 2249 } 2250 2251 static void 2252 urtwn_start(struct ifnet *ifp) 2253 { 2254 struct urtwn_softc *sc = ifp->if_softc; 2255 struct ieee80211com *ic = &sc->sc_ic; 2256 struct ether_header *eh; 2257 struct ieee80211_node *ni; 2258 struct mbuf *m; 2259 2260 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2261 2262 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2263 return; 2264 2265 for (;;) { 2266 mutex_enter(&sc->sc_tx_mtx); 2267 if (TAILQ_EMPTY(&sc->tx_free_list)) { 2268 mutex_exit(&sc->sc_tx_mtx); 2269 ifp->if_flags |= IFF_OACTIVE; 2270 break; 2271 } 2272 mutex_exit(&sc->sc_tx_mtx); 2273 2274 /* Send pending management frames first. */ 2275 IF_DEQUEUE(&ic->ic_mgtq, m); 2276 if (m != NULL) { 2277 ni = (void *)m->m_pkthdr.rcvif; 2278 m->m_pkthdr.rcvif = NULL; 2279 goto sendit; 2280 } 2281 if (ic->ic_state != IEEE80211_S_RUN) 2282 break; 2283 2284 /* Encapsulate and send data frames. */ 2285 IFQ_DEQUEUE(&ifp->if_snd, m); 2286 if (m == NULL) 2287 break; 2288 if (m->m_len < (int)sizeof(*eh) && 2289 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2290 ifp->if_oerrors++; 2291 continue; 2292 } 2293 eh = mtod(m, struct ether_header *); 2294 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2295 if (ni == NULL) { 2296 m_freem(m); 2297 ifp->if_oerrors++; 2298 continue; 2299 } 2300 2301 bpf_mtap(ifp, m); 2302 2303 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2304 ieee80211_free_node(ni); 2305 ifp->if_oerrors++; 2306 continue; 2307 } 2308 sendit: 2309 bpf_mtap3(ic->ic_rawbpf, m); 2310 2311 if (urtwn_tx(sc, m, ni) != 0) { 2312 ieee80211_free_node(ni); 2313 ifp->if_oerrors++; 2314 continue; 2315 } 2316 2317 sc->tx_timer = 5; 2318 ifp->if_timer = 1; 2319 } 2320 } 2321 2322 static void 2323 urtwn_watchdog(struct ifnet *ifp) 2324 { 2325 struct urtwn_softc *sc = ifp->if_softc; 2326 2327 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2328 2329 ifp->if_timer = 0; 2330 2331 if (sc->tx_timer > 0) { 2332 if (--sc->tx_timer == 0) { 2333 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2334 /* urtwn_init(ifp); XXX needs a process context! */ 2335 ifp->if_oerrors++; 2336 return; 2337 } 2338 ifp->if_timer = 1; 2339 } 2340 ieee80211_watchdog(&sc->sc_ic); 2341 } 2342 2343 static int 2344 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2345 { 2346 struct urtwn_softc *sc = ifp->if_softc; 2347 struct ieee80211com *ic = &sc->sc_ic; 2348 struct ifaddr *ifa; 2349 int s, error = 0; 2350 2351 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2352 device_xname(sc->sc_dev), __func__, cmd, data)); 2353 2354 s = splnet(); 2355 2356 switch (cmd) { 2357 case SIOCSIFADDR: 2358 ifa = (struct ifaddr *)data; 2359 ifp->if_flags |= IFF_UP; 2360 #ifdef INET 2361 if (ifa->ifa_addr->sa_family == AF_INET) 2362 arp_ifinit(ifp, ifa); 2363 #endif 2364 /*FALLTHROUGH*/ 2365 case SIOCSIFFLAGS: 2366 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2367 break; 2368 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2369 case IFF_UP|IFF_RUNNING: 2370 break; 2371 case IFF_UP: 2372 urtwn_init(ifp); 2373 break; 2374 case IFF_RUNNING: 2375 urtwn_stop(ifp, 1); 2376 break; 2377 case 0: 2378 break; 2379 } 2380 break; 2381 2382 case SIOCADDMULTI: 2383 case SIOCDELMULTI: 2384 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2385 /* setup multicast filter, etc */ 2386 error = 0; 2387 } 2388 break; 2389 2390 case SIOCS80211CHANNEL: 2391 error = ieee80211_ioctl(ic, cmd, data); 2392 if (error == ENETRESET && 2393 ic->ic_opmode == IEEE80211_M_MONITOR) { 2394 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2395 (IFF_UP | IFF_RUNNING)) { 2396 urtwn_set_chan(sc, ic->ic_ibss_chan, 2397 IEEE80211_HTINFO_2NDCHAN_NONE); 2398 } 2399 error = 0; 2400 } 2401 break; 2402 2403 default: 2404 error = ieee80211_ioctl(ic, cmd, data); 2405 break; 2406 } 2407 if (error == ENETRESET) { 2408 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2409 (IFF_UP | IFF_RUNNING)) { 2410 urtwn_init(ifp); 2411 } 2412 error = 0; 2413 } 2414 2415 splx(s); 2416 2417 return (error); 2418 } 2419 2420 static int 2421 urtwn_power_on(struct urtwn_softc *sc) 2422 { 2423 uint32_t reg; 2424 int ntries; 2425 2426 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2427 2428 /* Wait for autoload done bit. */ 2429 for (ntries = 0; ntries < 1000; ntries++) { 2430 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2431 break; 2432 DELAY(5); 2433 } 2434 if (ntries == 1000) { 2435 aprint_error_dev(sc->sc_dev, 2436 "timeout waiting for chip autoload\n"); 2437 return (ETIMEDOUT); 2438 } 2439 2440 /* Unlock ISO/CLK/Power control register. */ 2441 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2442 /* Move SPS into PWM mode. */ 2443 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2444 DELAY(100); 2445 2446 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2447 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2448 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2449 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2450 DELAY(100); 2451 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2452 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2453 ~R92C_SYS_ISO_CTRL_MD2PP); 2454 } 2455 2456 /* Auto enable WLAN. */ 2457 urtwn_write_2(sc, R92C_APS_FSMCO, 2458 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2459 for (ntries = 0; ntries < 1000; ntries++) { 2460 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2461 R92C_APS_FSMCO_APFM_ONMAC)) 2462 break; 2463 DELAY(5); 2464 } 2465 if (ntries == 1000) { 2466 aprint_error_dev(sc->sc_dev, 2467 "timeout waiting for MAC auto ON\n"); 2468 return (ETIMEDOUT); 2469 } 2470 2471 /* Enable radio, GPIO and LED functions. */ 2472 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2473 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2474 urtwn_write_2(sc, R92C_APS_FSMCO, 2475 R92C_APS_FSMCO_AFSM_HSUS | 2476 R92C_APS_FSMCO_PDN_EN | 2477 R92C_APS_FSMCO_PFM_ALDN); 2478 2479 /* Release RF digital isolation. */ 2480 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2481 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2482 2483 /* Initialize MAC. */ 2484 urtwn_write_1(sc, R92C_APSD_CTRL, 2485 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2486 for (ntries = 0; ntries < 200; ntries++) { 2487 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2488 R92C_APSD_CTRL_OFF_STATUS)) 2489 break; 2490 DELAY(5); 2491 } 2492 if (ntries == 200) { 2493 aprint_error_dev(sc->sc_dev, 2494 "timeout waiting for MAC initialization\n"); 2495 return (ETIMEDOUT); 2496 } 2497 2498 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2499 reg = urtwn_read_2(sc, R92C_CR); 2500 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2501 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2502 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2503 R92C_CR_ENSEC; 2504 urtwn_write_2(sc, R92C_CR, reg); 2505 2506 urtwn_write_1(sc, 0xfe10, 0x19); 2507 return (0); 2508 } 2509 2510 static int 2511 urtwn_llt_init(struct urtwn_softc *sc) 2512 { 2513 int i, error; 2514 2515 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2516 2517 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2518 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2519 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2520 return (error); 2521 } 2522 /* NB: 0xff indicates end-of-list. */ 2523 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2524 return (error); 2525 /* 2526 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2527 * as ring buffer. 2528 */ 2529 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2530 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2531 return (error); 2532 } 2533 /* Make the last page point to the beginning of the ring buffer. */ 2534 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2535 return (error); 2536 } 2537 2538 static void 2539 urtwn_fw_reset(struct urtwn_softc *sc) 2540 { 2541 uint16_t reg; 2542 int ntries; 2543 2544 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2545 2546 /* Tell 8051 to reset itself. */ 2547 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2548 2549 /* Wait until 8051 resets by itself. */ 2550 for (ntries = 0; ntries < 100; ntries++) { 2551 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2552 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2553 return; 2554 DELAY(50); 2555 } 2556 /* Force 8051 reset. */ 2557 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2558 } 2559 2560 static int 2561 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2562 { 2563 uint32_t reg; 2564 int off, mlen, error = 0; 2565 2566 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2567 device_xname(sc->sc_dev), __func__, page, buf, len)); 2568 2569 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2570 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2571 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2572 2573 off = R92C_FW_START_ADDR; 2574 while (len > 0) { 2575 if (len > 196) 2576 mlen = 196; 2577 else if (len > 4) 2578 mlen = 4; 2579 else 2580 mlen = 1; 2581 error = urtwn_write_region(sc, off, buf, mlen); 2582 if (error != 0) 2583 break; 2584 off += mlen; 2585 buf += mlen; 2586 len -= mlen; 2587 } 2588 return (error); 2589 } 2590 2591 static int 2592 urtwn_load_firmware(struct urtwn_softc *sc) 2593 { 2594 firmware_handle_t fwh; 2595 const struct r92c_fw_hdr *hdr; 2596 const char *name; 2597 u_char *fw, *ptr; 2598 size_t len; 2599 uint32_t reg; 2600 int mlen, ntries, page, error; 2601 2602 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2603 2604 /* Read firmware image from the filesystem. */ 2605 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2606 URTWN_CHIP_UMC_A_CUT) 2607 name = "rtl8192cfwU.bin"; 2608 else 2609 name = "rtl8192cfw.bin"; 2610 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 2611 aprint_error_dev(sc->sc_dev, 2612 "failed loadfirmware of file %s (error %d)\n", name, error); 2613 return (error); 2614 } 2615 len = firmware_get_size(fwh); 2616 fw = firmware_malloc(len); 2617 if (fw == NULL) { 2618 aprint_error_dev(sc->sc_dev, 2619 "failed to allocate firmware memory\n"); 2620 firmware_close(fwh); 2621 return (ENOMEM); 2622 } 2623 error = firmware_read(fwh, 0, fw, len); 2624 firmware_close(fwh); 2625 if (error != 0) { 2626 aprint_error_dev(sc->sc_dev, 2627 "failed to read firmware (error %d)\n", error); 2628 firmware_free(fw, 0); 2629 return (error); 2630 } 2631 2632 ptr = fw; 2633 hdr = (const struct r92c_fw_hdr *)ptr; 2634 /* Check if there is a valid FW header and skip it. */ 2635 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2636 (le16toh(hdr->signature) >> 4) == 0x92c) { 2637 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2638 device_xname(sc->sc_dev), __func__, 2639 le16toh(hdr->version), le16toh(hdr->subversion), 2640 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2641 ptr += sizeof(*hdr); 2642 len -= sizeof(*hdr); 2643 } 2644 2645 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2646 urtwn_fw_reset(sc); 2647 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2648 } 2649 2650 /* download enabled */ 2651 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2652 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2653 R92C_SYS_FUNC_EN_CPUEN); 2654 urtwn_write_1(sc, R92C_MCUFWDL, 2655 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2656 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2657 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2658 2659 /* download firmware */ 2660 for (page = 0; len > 0; page++) { 2661 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2662 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2663 if (error != 0) { 2664 aprint_error_dev(sc->sc_dev, 2665 "could not load firmware page %d\n", page); 2666 goto fail; 2667 } 2668 ptr += mlen; 2669 len -= mlen; 2670 } 2671 2672 /* download disable */ 2673 urtwn_write_1(sc, R92C_MCUFWDL, 2674 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2675 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2676 2677 /* Wait for checksum report. */ 2678 for (ntries = 0; ntries < 1000; ntries++) { 2679 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2680 break; 2681 DELAY(5); 2682 } 2683 if (ntries == 1000) { 2684 aprint_error_dev(sc->sc_dev, 2685 "timeout waiting for checksum report\n"); 2686 error = ETIMEDOUT; 2687 goto fail; 2688 } 2689 2690 /* Wait for firmware readiness. */ 2691 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2692 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2693 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2694 for (ntries = 0; ntries < 1000; ntries++) { 2695 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2696 break; 2697 DELAY(5); 2698 } 2699 if (ntries == 1000) { 2700 aprint_error_dev(sc->sc_dev, 2701 "timeout waiting for firmware readiness\n"); 2702 error = ETIMEDOUT; 2703 goto fail; 2704 } 2705 fail: 2706 firmware_free(fw, 0); 2707 return (error); 2708 } 2709 2710 static int 2711 urtwn_dma_init(struct urtwn_softc *sc) 2712 { 2713 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2714 uint32_t reg; 2715 int error; 2716 2717 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2718 2719 /* Initialize LLT table. */ 2720 error = urtwn_llt_init(sc); 2721 if (error != 0) 2722 return (error); 2723 2724 /* Get Tx queues to USB endpoints mapping. */ 2725 hashq = hasnq = haslq = 0; 2726 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2727 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2728 device_xname(sc->sc_dev), __func__, reg)); 2729 if (MS(reg, R92C_USB_EP_HQ) != 0) 2730 hashq = 1; 2731 if (MS(reg, R92C_USB_EP_NQ) != 0) 2732 hasnq = 1; 2733 if (MS(reg, R92C_USB_EP_LQ) != 0) 2734 haslq = 1; 2735 nqueues = hashq + hasnq + haslq; 2736 if (nqueues == 0) 2737 return (EIO); 2738 /* Get the number of pages for each queue. */ 2739 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2740 /* The remaining pages are assigned to the high priority queue. */ 2741 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2742 2743 /* Set number of pages for normal priority queue. */ 2744 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2745 urtwn_write_4(sc, R92C_RQPN, 2746 /* Set number of pages for public queue. */ 2747 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2748 /* Set number of pages for high priority queue. */ 2749 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2750 /* Set number of pages for low priority queue. */ 2751 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2752 /* Load values. */ 2753 R92C_RQPN_LD); 2754 2755 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2756 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2757 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2758 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2759 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2760 2761 /* Set queue to USB pipe mapping. */ 2762 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2763 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2764 if (nqueues == 1) { 2765 if (hashq) { 2766 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2767 } else if (hasnq) { 2768 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2769 } else { 2770 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2771 } 2772 } else if (nqueues == 2) { 2773 /* All 2-endpoints configs have a high priority queue. */ 2774 if (!hashq) { 2775 return (EIO); 2776 } 2777 if (hasnq) { 2778 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2779 } else { 2780 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2781 } 2782 } else { 2783 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2784 } 2785 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2786 2787 /* Set Tx/Rx transfer page boundary. */ 2788 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2789 2790 /* Set Tx/Rx transfer page size. */ 2791 urtwn_write_1(sc, R92C_PBP, 2792 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2793 return (0); 2794 } 2795 2796 static void 2797 urtwn_mac_init(struct urtwn_softc *sc) 2798 { 2799 int i; 2800 2801 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2802 2803 /* Write MAC initialization values. */ 2804 for (i = 0; i < (int)__arraycount(rtl8192cu_mac); i++) 2805 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2806 } 2807 2808 static void 2809 urtwn_bb_init(struct urtwn_softc *sc) 2810 { 2811 const struct urtwn_bb_prog *prog; 2812 uint32_t reg; 2813 int i; 2814 2815 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2816 2817 /* Enable BB and RF. */ 2818 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2819 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2820 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2821 R92C_SYS_FUNC_EN_DIO_RF); 2822 2823 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2824 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2825 2826 urtwn_write_1(sc, R92C_RF_CTRL, 2827 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2828 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2829 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2830 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2831 2832 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2833 urtwn_write_1(sc, 0x15, 0xe9); 2834 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2835 2836 /* Select BB programming based on board type. */ 2837 if (!(sc->chip & URTWN_CHIP_92C)) { 2838 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2839 prog = &rtl8188ce_bb_prog; 2840 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2841 prog = &rtl8188ru_bb_prog; 2842 } else { 2843 prog = &rtl8188cu_bb_prog; 2844 } 2845 } else { 2846 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2847 prog = &rtl8192ce_bb_prog; 2848 } else { 2849 prog = &rtl8192cu_bb_prog; 2850 } 2851 } 2852 /* Write BB initialization values. */ 2853 for (i = 0; i < prog->count; i++) { 2854 /* additional delay depend on registers */ 2855 switch (prog->regs[i]) { 2856 case 0xfe: 2857 usbd_delay_ms(sc->sc_udev, 50); 2858 break; 2859 case 0xfd: 2860 usbd_delay_ms(sc->sc_udev, 5); 2861 break; 2862 case 0xfc: 2863 usbd_delay_ms(sc->sc_udev, 1); 2864 break; 2865 case 0xfb: 2866 DELAY(50); 2867 break; 2868 case 0xfa: 2869 DELAY(5); 2870 break; 2871 case 0xf9: 2872 DELAY(1); 2873 break; 2874 } 2875 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2876 DELAY(1); 2877 } 2878 2879 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2880 /* 8192C 1T only configuration. */ 2881 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2882 reg = (reg & ~0x00000003) | 0x2; 2883 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2884 2885 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2886 reg = (reg & ~0x00300033) | 0x00200022; 2887 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2888 2889 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2890 reg = (reg & ~0xff000000) | (0x45 << 24); 2891 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2892 2893 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2894 reg = (reg & ~0x000000ff) | 0x23; 2895 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2896 2897 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2898 reg = (reg & ~0x00000030) | (1 << 4); 2899 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2900 2901 reg = urtwn_bb_read(sc, 0xe74); 2902 reg = (reg & ~0x0c000000) | (2 << 26); 2903 urtwn_bb_write(sc, 0xe74, reg); 2904 reg = urtwn_bb_read(sc, 0xe78); 2905 reg = (reg & ~0x0c000000) | (2 << 26); 2906 urtwn_bb_write(sc, 0xe78, reg); 2907 reg = urtwn_bb_read(sc, 0xe7c); 2908 reg = (reg & ~0x0c000000) | (2 << 26); 2909 urtwn_bb_write(sc, 0xe7c, reg); 2910 reg = urtwn_bb_read(sc, 0xe80); 2911 reg = (reg & ~0x0c000000) | (2 << 26); 2912 urtwn_bb_write(sc, 0xe80, reg); 2913 reg = urtwn_bb_read(sc, 0xe88); 2914 reg = (reg & ~0x0c000000) | (2 << 26); 2915 urtwn_bb_write(sc, 0xe88, reg); 2916 } 2917 2918 /* Write AGC values. */ 2919 for (i = 0; i < prog->agccount; i++) { 2920 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 2921 DELAY(1); 2922 } 2923 2924 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2925 R92C_HSSI_PARAM2_CCK_HIPWR) { 2926 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 2927 } 2928 } 2929 2930 static void 2931 urtwn_rf_init(struct urtwn_softc *sc) 2932 { 2933 const struct urtwn_rf_prog *prog; 2934 uint32_t reg, mask, saved; 2935 int i, j, idx; 2936 2937 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2938 2939 /* Select RF programming based on board type. */ 2940 if (!(sc->chip & URTWN_CHIP_92C)) { 2941 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2942 prog = rtl8188ce_rf_prog; 2943 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2944 prog = rtl8188ru_rf_prog; 2945 } else { 2946 prog = rtl8188cu_rf_prog; 2947 } 2948 } else { 2949 prog = rtl8192ce_rf_prog; 2950 } 2951 2952 for (i = 0; i < sc->nrxchains; i++) { 2953 /* Save RF_ENV control type. */ 2954 idx = i / 2; 2955 mask = 0xffffU << ((i % 2) * 16); 2956 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 2957 2958 /* Set RF_ENV enable. */ 2959 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2960 reg |= 0x100000; 2961 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2962 DELAY(1); 2963 2964 /* Set RF_ENV output high. */ 2965 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2966 reg |= 0x10; 2967 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2968 DELAY(1); 2969 2970 /* Set address and data lengths of RF registers. */ 2971 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2972 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2973 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2974 DELAY(1); 2975 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2976 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2977 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2978 DELAY(1); 2979 2980 /* Write RF initialization values for this chain. */ 2981 for (j = 0; j < prog[i].count; j++) { 2982 if (prog[i].regs[j] >= 0xf9 && 2983 prog[i].regs[j] <= 0xfe) { 2984 /* 2985 * These are fake RF registers offsets that 2986 * indicate a delay is required. 2987 */ 2988 usbd_delay_ms(sc->sc_udev, 50); 2989 continue; 2990 } 2991 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 2992 DELAY(1); 2993 } 2994 2995 /* Restore RF_ENV control type. */ 2996 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 2997 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 2998 } 2999 3000 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3001 URTWN_CHIP_UMC_A_CUT) { 3002 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3003 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3004 } 3005 3006 /* Cache RF register CHNLBW. */ 3007 for (i = 0; i < 2; i++) { 3008 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3009 } 3010 } 3011 3012 static void 3013 urtwn_cam_init(struct urtwn_softc *sc) 3014 { 3015 uint32_t content, command; 3016 uint8_t idx; 3017 int i; 3018 3019 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3020 3021 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3022 content = (idx & 3) 3023 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3024 | R92C_CAM_VALID; 3025 3026 command = R92C_CAMCMD_POLLING 3027 | R92C_CAMCMD_WRITE 3028 | R92C_CAM_CTL0(idx); 3029 3030 urtwn_write_4(sc, R92C_CAMWRITE, content); 3031 urtwn_write_4(sc, R92C_CAMCMD, command); 3032 } 3033 3034 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3035 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3036 if (i == 0) { 3037 content = (idx & 3) 3038 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3039 | R92C_CAM_VALID; 3040 } else { 3041 content = 0; 3042 } 3043 3044 command = R92C_CAMCMD_POLLING 3045 | R92C_CAMCMD_WRITE 3046 | R92C_CAM_CTL0(idx) 3047 | (u_int)i; 3048 3049 urtwn_write_4(sc, R92C_CAMWRITE, content); 3050 urtwn_write_4(sc, R92C_CAMCMD, command); 3051 } 3052 } 3053 3054 /* Invalidate all CAM entries. */ 3055 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3056 } 3057 3058 static void 3059 urtwn_pa_bias_init(struct urtwn_softc *sc) 3060 { 3061 uint8_t reg; 3062 int i; 3063 3064 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3065 3066 for (i = 0; i < sc->nrxchains; i++) { 3067 if (sc->pa_setting & (1U << i)) 3068 continue; 3069 3070 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3071 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3072 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3073 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3074 } 3075 if (!(sc->pa_setting & 0x10)) { 3076 reg = urtwn_read_1(sc, 0x16); 3077 reg = (reg & ~0xf0) | 0x90; 3078 urtwn_write_1(sc, 0x16, reg); 3079 } 3080 } 3081 3082 static void 3083 urtwn_rxfilter_init(struct urtwn_softc *sc) 3084 { 3085 3086 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3087 3088 /* Initialize Rx filter. */ 3089 /* TODO: use better filter for monitor mode. */ 3090 urtwn_write_4(sc, R92C_RCR, 3091 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3092 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3093 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3094 /* Accept all multicast frames. */ 3095 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3096 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3097 /* Accept all management frames. */ 3098 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3099 /* Reject all control frames. */ 3100 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3101 /* Accept all data frames. */ 3102 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3103 } 3104 3105 static void 3106 urtwn_edca_init(struct urtwn_softc *sc) 3107 { 3108 3109 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3110 3111 /* set spec SIFS (used in NAV) */ 3112 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3113 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3114 3115 /* set SIFS CCK/OFDM */ 3116 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3117 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3118 3119 /* TXOP */ 3120 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3121 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3122 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3123 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3124 } 3125 3126 static void 3127 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3128 uint16_t power[URTWN_RIDX_COUNT]) 3129 { 3130 uint32_t reg; 3131 3132 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3133 __func__, chain)); 3134 3135 /* Write per-CCK rate Tx power. */ 3136 if (chain == 0) { 3137 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3138 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3139 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3140 3141 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3142 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3143 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3144 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3145 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3146 } else { 3147 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3148 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3149 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3150 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3151 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3152 3153 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3154 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3155 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3156 } 3157 /* Write per-OFDM rate Tx power. */ 3158 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3159 SM(R92C_TXAGC_RATE06, power[ 4]) | 3160 SM(R92C_TXAGC_RATE09, power[ 5]) | 3161 SM(R92C_TXAGC_RATE12, power[ 6]) | 3162 SM(R92C_TXAGC_RATE18, power[ 7])); 3163 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3164 SM(R92C_TXAGC_RATE24, power[ 8]) | 3165 SM(R92C_TXAGC_RATE36, power[ 9]) | 3166 SM(R92C_TXAGC_RATE48, power[10]) | 3167 SM(R92C_TXAGC_RATE54, power[11])); 3168 /* Write per-MCS Tx power. */ 3169 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3170 SM(R92C_TXAGC_MCS00, power[12]) | 3171 SM(R92C_TXAGC_MCS01, power[13]) | 3172 SM(R92C_TXAGC_MCS02, power[14]) | 3173 SM(R92C_TXAGC_MCS03, power[15])); 3174 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3175 SM(R92C_TXAGC_MCS04, power[16]) | 3176 SM(R92C_TXAGC_MCS05, power[17]) | 3177 SM(R92C_TXAGC_MCS06, power[18]) | 3178 SM(R92C_TXAGC_MCS07, power[19])); 3179 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3180 SM(R92C_TXAGC_MCS08, power[20]) | 3181 SM(R92C_TXAGC_MCS09, power[21]) | 3182 SM(R92C_TXAGC_MCS10, power[22]) | 3183 SM(R92C_TXAGC_MCS11, power[23])); 3184 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3185 SM(R92C_TXAGC_MCS12, power[24]) | 3186 SM(R92C_TXAGC_MCS13, power[25]) | 3187 SM(R92C_TXAGC_MCS14, power[26]) | 3188 SM(R92C_TXAGC_MCS15, power[27])); 3189 } 3190 3191 static void 3192 urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, 3193 uint16_t power[URTWN_RIDX_COUNT]) 3194 { 3195 struct r92c_rom *rom = &sc->rom; 3196 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3197 const struct urtwn_txpwr *base; 3198 int ridx, group; 3199 3200 DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", 3201 device_xname(sc->sc_dev), __func__, chain, chan)); 3202 3203 /* Determine channel group. */ 3204 if (chan <= 3) { 3205 group = 0; 3206 } else if (chan <= 9) { 3207 group = 1; 3208 } else { 3209 group = 2; 3210 } 3211 3212 /* Get original Tx power based on board type and RF chain. */ 3213 if (!(sc->chip & URTWN_CHIP_92C)) { 3214 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3215 base = &rtl8188ru_txagc[chain]; 3216 } else { 3217 base = &rtl8192cu_txagc[chain]; 3218 } 3219 } else { 3220 base = &rtl8192cu_txagc[chain]; 3221 } 3222 3223 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3224 if (sc->regulatory == 0) { 3225 for (ridx = 0; ridx <= 3; ridx++) { 3226 power[ridx] = base->pwr[0][ridx]; 3227 } 3228 } 3229 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3230 if (sc->regulatory == 3) { 3231 power[ridx] = base->pwr[0][ridx]; 3232 /* Apply vendor limits. */ 3233 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3234 maxpow = rom->ht40_max_pwr[group]; 3235 } else { 3236 maxpow = rom->ht20_max_pwr[group]; 3237 } 3238 maxpow = (maxpow >> (chain * 4)) & 0xf; 3239 if (power[ridx] > maxpow) { 3240 power[ridx] = maxpow; 3241 } 3242 } else if (sc->regulatory == 1) { 3243 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3244 power[ridx] = base->pwr[group][ridx]; 3245 } 3246 } else if (sc->regulatory != 2) { 3247 power[ridx] = base->pwr[0][ridx]; 3248 } 3249 } 3250 3251 /* Compute per-CCK rate Tx power. */ 3252 cckpow = rom->cck_tx_pwr[chain][group]; 3253 for (ridx = 0; ridx <= 3; ridx++) { 3254 power[ridx] += cckpow; 3255 if (power[ridx] > R92C_MAX_TX_PWR) { 3256 power[ridx] = R92C_MAX_TX_PWR; 3257 } 3258 } 3259 3260 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3261 if (sc->ntxchains > 1) { 3262 /* Apply reduction for 2 spatial streams. */ 3263 diff = rom->ht40_2s_tx_pwr_diff[group]; 3264 diff = (diff >> (chain * 4)) & 0xf; 3265 htpow = (htpow > diff) ? htpow - diff : 0; 3266 } 3267 3268 /* Compute per-OFDM rate Tx power. */ 3269 diff = rom->ofdm_tx_pwr_diff[group]; 3270 diff = (diff >> (chain * 4)) & 0xf; 3271 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3272 for (ridx = 4; ridx <= 11; ridx++) { 3273 power[ridx] += ofdmpow; 3274 if (power[ridx] > R92C_MAX_TX_PWR) { 3275 power[ridx] = R92C_MAX_TX_PWR; 3276 } 3277 } 3278 3279 /* Compute per-MCS Tx power. */ 3280 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3281 diff = rom->ht20_tx_pwr_diff[group]; 3282 diff = (diff >> (chain * 4)) & 0xf; 3283 htpow += diff; /* HT40->HT20 correction. */ 3284 } 3285 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3286 power[ridx] += htpow; 3287 if (power[ridx] > R92C_MAX_TX_PWR) { 3288 power[ridx] = R92C_MAX_TX_PWR; 3289 } 3290 } 3291 #ifdef URTWN_DEBUG 3292 if (urtwn_debug & DBG_RF) { 3293 /* Dump per-rate Tx power values. */ 3294 printf("%s: %s: Tx power for chain %d:\n", 3295 device_xname(sc->sc_dev), __func__, chain); 3296 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3297 printf("%s: %s: Rate %d = %u\n", 3298 device_xname(sc->sc_dev), __func__, ridx, 3299 power[ridx]); 3300 } 3301 } 3302 #endif 3303 } 3304 3305 static void 3306 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3307 { 3308 uint16_t power[URTWN_RIDX_COUNT]; 3309 int i; 3310 3311 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3312 3313 for (i = 0; i < sc->ntxchains; i++) { 3314 /* Compute per-rate Tx power values. */ 3315 urtwn_get_txpower(sc, i, chan, ht40m, power); 3316 /* Write per-rate Tx power values to hardware. */ 3317 urtwn_write_txpower(sc, i, power); 3318 } 3319 } 3320 3321 static void 3322 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3323 { 3324 struct ieee80211com *ic = &sc->sc_ic; 3325 u_int chan; 3326 int i; 3327 3328 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3329 3330 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3331 __func__, chan)); 3332 3333 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3334 chan += 2; 3335 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3336 chan -= 2; 3337 } 3338 3339 /* Set Tx power for this new channel. */ 3340 urtwn_set_txpower(sc, chan, ht40m); 3341 3342 for (i = 0; i < sc->nrxchains; i++) { 3343 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3344 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3345 } 3346 3347 if (ht40m) { 3348 /* Is secondary channel below or above primary? */ 3349 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3350 uint32_t reg; 3351 3352 urtwn_write_1(sc, R92C_BWOPMODE, 3353 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3354 3355 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3356 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3357 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3358 3359 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3360 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3361 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3362 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3363 3364 /* Set CCK side band. */ 3365 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3366 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3367 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3368 3369 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3370 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3371 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3372 3373 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3374 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3375 ~R92C_FPGA0_ANAPARAM2_CBW20); 3376 3377 reg = urtwn_bb_read(sc, 0x818); 3378 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3379 urtwn_bb_write(sc, 0x818, reg); 3380 3381 /* Select 40MHz bandwidth. */ 3382 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3383 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3384 } else { 3385 urtwn_write_1(sc, R92C_BWOPMODE, 3386 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3387 3388 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3389 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3390 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3391 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3392 3393 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3394 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3395 R92C_FPGA0_ANAPARAM2_CBW20); 3396 3397 /* Select 20MHz bandwidth. */ 3398 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3399 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3400 } 3401 } 3402 3403 static void 3404 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3405 { 3406 3407 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3408 __func__, inited)); 3409 3410 /* TODO */ 3411 } 3412 3413 static void 3414 urtwn_lc_calib(struct urtwn_softc *sc) 3415 { 3416 uint32_t rf_ac[2]; 3417 uint8_t txmode; 3418 int i; 3419 3420 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3421 3422 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3423 if ((txmode & 0x70) != 0) { 3424 /* Disable all continuous Tx. */ 3425 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3426 3427 /* Set RF mode to standby mode. */ 3428 for (i = 0; i < sc->nrxchains; i++) { 3429 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3430 urtwn_rf_write(sc, i, R92C_RF_AC, 3431 RW(rf_ac[i], R92C_RF_AC_MODE, 3432 R92C_RF_AC_MODE_STANDBY)); 3433 } 3434 } else { 3435 /* Block all Tx queues. */ 3436 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3437 } 3438 /* Start calibration. */ 3439 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3440 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3441 3442 /* Give calibration the time to complete. */ 3443 usbd_delay_ms(sc->sc_udev, 100); 3444 3445 /* Restore configuration. */ 3446 if ((txmode & 0x70) != 0) { 3447 /* Restore Tx mode. */ 3448 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3449 /* Restore RF mode. */ 3450 for (i = 0; i < sc->nrxchains; i++) { 3451 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3452 } 3453 } else { 3454 /* Unblock all Tx queues. */ 3455 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3456 } 3457 } 3458 3459 static void 3460 urtwn_temp_calib(struct urtwn_softc *sc) 3461 { 3462 int temp; 3463 3464 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3465 3466 if (sc->thcal_state == 0) { 3467 /* Start measuring temperature. */ 3468 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3469 device_xname(sc->sc_dev), __func__)); 3470 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3471 sc->thcal_state = 1; 3472 return; 3473 } 3474 sc->thcal_state = 0; 3475 3476 /* Read measured temperature. */ 3477 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3478 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3479 __func__, temp)); 3480 if (temp == 0) /* Read failed, skip. */ 3481 return; 3482 3483 /* 3484 * Redo LC calibration if temperature changed significantly since 3485 * last calibration. 3486 */ 3487 if (sc->thcal_lctemp == 0) { 3488 /* First LC calibration is performed in urtwn_init(). */ 3489 sc->thcal_lctemp = temp; 3490 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3491 DPRINTFN(DBG_RF, 3492 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3493 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3494 temp)); 3495 urtwn_lc_calib(sc); 3496 /* Record temperature of last LC calibration. */ 3497 sc->thcal_lctemp = temp; 3498 } 3499 } 3500 3501 static int 3502 urtwn_init(struct ifnet *ifp) 3503 { 3504 struct urtwn_softc *sc = ifp->if_softc; 3505 struct ieee80211com *ic = &sc->sc_ic; 3506 struct urtwn_rx_data *data; 3507 uint32_t reg; 3508 int i, error; 3509 3510 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3511 3512 urtwn_stop(ifp, 0); 3513 3514 mutex_enter(&sc->sc_task_mtx); 3515 /* Init host async commands ring. */ 3516 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3517 mutex_exit(&sc->sc_task_mtx); 3518 3519 mutex_enter(&sc->sc_fwcmd_mtx); 3520 /* Init firmware commands ring. */ 3521 sc->fwcur = 0; 3522 mutex_exit(&sc->sc_fwcmd_mtx); 3523 3524 if (!(sc->sc_flags & URTWN_FLAG_INIT_ONCE)) { 3525 /* Allocate Tx/Rx buffers. */ 3526 error = urtwn_alloc_rx_list(sc); 3527 if (error != 0) { 3528 aprint_error_dev(sc->sc_dev, 3529 "could not allocate Rx buffers\n"); 3530 goto fail; 3531 } 3532 error = urtwn_alloc_tx_list(sc); 3533 if (error != 0) { 3534 aprint_error_dev(sc->sc_dev, 3535 "could not allocate Tx buffers\n"); 3536 goto fail; 3537 } 3538 sc->sc_flags |= URTWN_FLAG_INIT_ONCE; 3539 } 3540 3541 /* Power on adapter. */ 3542 error = urtwn_power_on(sc); 3543 if (error != 0) 3544 goto fail; 3545 3546 /* Initialize DMA. */ 3547 error = urtwn_dma_init(sc); 3548 if (error != 0) 3549 goto fail; 3550 3551 /* Set info size in Rx descriptors (in 64-bit words). */ 3552 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3553 3554 /* Init interrupts. */ 3555 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3556 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3557 3558 /* Set MAC address. */ 3559 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3560 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3561 3562 /* Set initial network type. */ 3563 reg = urtwn_read_4(sc, R92C_CR); 3564 switch (ic->ic_opmode) { 3565 case IEEE80211_M_STA: 3566 default: 3567 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3568 break; 3569 3570 case IEEE80211_M_IBSS: 3571 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3572 break; 3573 } 3574 urtwn_write_4(sc, R92C_CR, reg); 3575 3576 urtwn_rxfilter_init(sc); 3577 3578 /* Set response rate */ 3579 reg = urtwn_read_4(sc, R92C_RRSR); 3580 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3581 urtwn_write_4(sc, R92C_RRSR, reg); 3582 3583 /* SIFS (used in NAV) */ 3584 urtwn_write_2(sc, R92C_SPEC_SIFS, 3585 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3586 3587 /* Set short/long retry limits. */ 3588 urtwn_write_2(sc, R92C_RL, 3589 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3590 3591 /* Initialize EDCA parameters. */ 3592 urtwn_edca_init(sc); 3593 3594 /* Setup rate fallback. */ 3595 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3596 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3597 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3598 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3599 3600 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3601 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3602 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3603 /* Set ACK timeout. */ 3604 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3605 3606 /* Setup USB aggregation. */ 3607 /* Tx */ 3608 reg = urtwn_read_4(sc, R92C_TDECTRL); 3609 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3610 urtwn_write_4(sc, R92C_TDECTRL, reg); 3611 /* Rx */ 3612 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3613 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3614 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3615 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3616 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3617 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3618 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3619 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3620 3621 /* Initialize beacon parameters. */ 3622 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3623 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3624 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3625 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3626 3627 /* Setup AMPDU aggregation. */ 3628 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3629 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3630 urtwn_write_2(sc, 0x4ca, 0x0708); 3631 3632 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3633 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3634 3635 /* Load 8051 microcode. */ 3636 error = urtwn_load_firmware(sc); 3637 if (error != 0) 3638 goto fail; 3639 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3640 3641 /* Initialize MAC/BB/RF blocks. */ 3642 urtwn_mac_init(sc); 3643 urtwn_write_4(sc, R92C_RCR, 3644 urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); 3645 urtwn_bb_init(sc); 3646 urtwn_rf_init(sc); 3647 3648 /* Turn CCK and OFDM blocks on. */ 3649 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3650 reg |= R92C_RFMOD_CCK_EN; 3651 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3652 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3653 reg |= R92C_RFMOD_OFDM_EN; 3654 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3655 3656 /* Clear per-station keys table. */ 3657 urtwn_cam_init(sc); 3658 3659 /* Enable hardware sequence numbering. */ 3660 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3661 3662 /* Perform LO and IQ calibrations. */ 3663 urtwn_iq_calib(sc, sc->iqk_inited); 3664 sc->iqk_inited = true; 3665 3666 /* Perform LC calibration. */ 3667 urtwn_lc_calib(sc); 3668 3669 /* Fix USB interference issue. */ 3670 urtwn_write_1(sc, 0xfe40, 0xe0); 3671 urtwn_write_1(sc, 0xfe41, 0x8d); 3672 urtwn_write_1(sc, 0xfe42, 0x80); 3673 urtwn_write_4(sc, 0x20c, 0xfd0320); 3674 3675 urtwn_pa_bias_init(sc); 3676 3677 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3678 /* 1T1R */ 3679 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3680 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3681 } 3682 3683 /* Initialize GPIO setting. */ 3684 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3685 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3686 3687 /* Fix for lower temperature. */ 3688 urtwn_write_1(sc, 0x15, 0xe9); 3689 3690 /* Set default channel. */ 3691 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3692 urtwn_set_chan(sc, ic->ic_ibss_chan, IEEE80211_HTINFO_2NDCHAN_NONE); 3693 3694 /* Queue Rx xfers. */ 3695 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3696 data = &sc->rx_data[i]; 3697 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3698 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3699 USBD_NO_TIMEOUT, urtwn_rxeof); 3700 error = usbd_transfer(data->xfer); 3701 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3702 error != USBD_IN_PROGRESS)) 3703 goto fail; 3704 } 3705 3706 /* We're ready to go. */ 3707 ifp->if_flags &= ~IFF_OACTIVE; 3708 ifp->if_flags |= IFF_RUNNING; 3709 3710 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3711 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3712 else 3713 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3714 return (0); 3715 3716 fail: 3717 urtwn_stop(ifp, 1); 3718 return (error); 3719 } 3720 3721 static void 3722 urtwn_stop(struct ifnet *ifp, int disable) 3723 { 3724 struct urtwn_softc *sc = ifp->if_softc; 3725 struct ieee80211com *ic = &sc->sc_ic; 3726 int i, s; 3727 3728 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3729 3730 sc->tx_timer = 0; 3731 ifp->if_timer = 0; 3732 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3733 3734 s = splusb(); 3735 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3736 urtwn_wait_async(sc); 3737 splx(s); 3738 3739 callout_stop(&sc->sc_scan_to); 3740 callout_stop(&sc->sc_calib_to); 3741 3742 /* Abort Tx. */ 3743 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3744 if (sc->tx_pipe[i] != NULL) 3745 usbd_abort_pipe(sc->tx_pipe[i]); 3746 } 3747 3748 /* Stop Rx pipe. */ 3749 usbd_abort_pipe(sc->rx_pipe); 3750 3751 if (disable) 3752 urtwn_chip_stop(sc); 3753 } 3754 3755 static void 3756 urtwn_chip_stop(struct urtwn_softc *sc) 3757 { 3758 uint32_t reg; 3759 bool disabled = true; 3760 3761 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3762 3763 /* 3764 * RF Off Sequence 3765 */ 3766 /* Pause MAC TX queue */ 3767 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3768 3769 /* Disable RF */ 3770 urtwn_rf_write(sc, 0, 0, 0); 3771 3772 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3773 3774 /* Reset BB state machine */ 3775 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3776 R92C_SYS_FUNC_EN_USBD | 3777 R92C_SYS_FUNC_EN_USBA | 3778 R92C_SYS_FUNC_EN_BB_GLB_RST); 3779 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3780 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3781 3782 /* 3783 * Reset digital sequence 3784 */ 3785 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3786 /* Reset MCU ready status */ 3787 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3788 /* If firmware in ram code, do reset */ 3789 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3790 urtwn_fw_reset(sc); 3791 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3792 } 3793 } 3794 3795 /* Reset MAC and Enable 8051 */ 3796 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3797 3798 /* Reset MCU ready status */ 3799 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3800 3801 if (disabled) { 3802 /* Disable MAC clock */ 3803 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3804 /* Disable AFE PLL */ 3805 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3806 /* Gated AFE DIG_CLOCK */ 3807 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3808 /* Isolated digital to PON */ 3809 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3810 } 3811 3812 /* 3813 * Pull GPIO PIN to balance level and LED control 3814 */ 3815 /* 1. Disable GPIO[7:0] */ 3816 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3817 3818 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3819 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3820 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3821 3822 /* Disable GPIO[10:8] */ 3823 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3824 3825 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3826 reg |= (((reg & 0x000f) << 4) | 0x0780); 3827 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3828 3829 /* Disable LED0 & 1 */ 3830 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3831 3832 /* 3833 * Reset digital sequence 3834 */ 3835 if (disabled) { 3836 /* Disable ELDR clock */ 3837 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3838 /* Isolated ELDR to PON */ 3839 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3840 } 3841 3842 /* 3843 * Disable analog sequence 3844 */ 3845 if (disabled) { 3846 /* Disable A15 power */ 3847 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3848 /* Disable digital core power */ 3849 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3850 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3851 ~R92C_LDOV12D_CTRL_LDV12_EN); 3852 } 3853 3854 /* Enter PFM mode */ 3855 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3856 3857 /* Set USB suspend */ 3858 urtwn_write_2(sc, R92C_APS_FSMCO, 3859 R92C_APS_FSMCO_APDM_HOST | 3860 R92C_APS_FSMCO_AFSM_HSUS | 3861 R92C_APS_FSMCO_PFM_ALDN); 3862 3863 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3864 } 3865 3866 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 3867 3868 #ifdef _MODULE 3869 #include "ioconf.c" 3870 #endif 3871 3872 static int 3873 if_urtwn_modcmd(modcmd_t cmd, void *aux) 3874 { 3875 int error = 0; 3876 3877 switch (cmd) { 3878 case MODULE_CMD_INIT: 3879 #ifdef _MODULE 3880 error = config_init_component(cfdriver_ioconf_urtwn, 3881 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3882 #endif 3883 return (error); 3884 case MODULE_CMD_FINI: 3885 #ifdef _MODULE 3886 error = config_fini_component(cfdriver_ioconf_urtwn, 3887 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3888 #endif 3889 return (error); 3890 default: 3891 return (ENOTTY); 3892 } 3893 } 3894
Indexes created Tue Sep 30 06:09:59 GMT 2025