if_urtwn.c revision 1.120
1 /* $NetBSD: if_urtwn.c,v 1.120 2025/08/24 09:45:29 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.120 2025/08/24 09:45:29 nat Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 99 #ifndef URTWN_DEBUG_DEFAULT 100 #define URTWN_DEBUG_DEFAULT 0 101 #endif 102 103 u_int urtwn_debug = URTWN_DEBUG_DEFAULT; 104 105 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 106 if (urtwn_debug & (n)) { \ 107 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 108 } \ 109 } while (/*CONSTCOND*/0) 110 #define URTWNHIST_FUNC() USBHIST_FUNC() 111 #define URTWNHIST_CALLED() do { \ 112 if (urtwn_debug & DBG_FN) { \ 113 KERNHIST_CALLED(usbhist); \ 114 } \ 115 } while(/*CONSTCOND*/0) 116 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 117 if (urtwn_debug & DBG_FN) { \ 118 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 119 } \ 120 } while(/*CONSTCOND*/0) 121 #else 122 #define DPRINTFN(n, fmt, a, b, c, d) 123 #define URTWNHIST_FUNC() 124 #define URTWNHIST_CALLED() 125 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 126 #endif 127 128 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 129 #define URTWN_RTL8188E_DEV(v,p) \ 130 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 131 #define URTWN_RTL8192EU_DEV(v,p) \ 132 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 133 static const struct urtwn_dev { 134 struct usb_devno dev; 135 uint32_t flags; 136 #define FLAG_RTL8188E __BIT(0) 137 #define FLAG_RTL8192E __BIT(1) 138 } urtwn_devs[] = { 139 URTWN_DEV(ABOCOM, RTL8188CU_1), 140 URTWN_DEV(ABOCOM, RTL8188CU_2), 141 URTWN_DEV(ABOCOM, RTL8192CU), 142 URTWN_DEV(ASUSTEK, RTL8192CU), 143 URTWN_DEV(ASUSTEK, RTL8192CU_3), 144 URTWN_DEV(ASUSTEK, USBN10NANO), 145 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 146 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 147 URTWN_DEV(AZUREWAVE, RTL8188CU), 148 URTWN_DEV(BELKIN, F7D2102), 149 URTWN_DEV(BELKIN, RTL8188CU), 150 URTWN_DEV(BELKIN, RTL8188CUS), 151 URTWN_DEV(BELKIN, RTL8192CU), 152 URTWN_DEV(BELKIN, RTL8192CU_1), 153 URTWN_DEV(BELKIN, RTL8192CU_2), 154 URTWN_DEV(CHICONY, RTL8188CUS_1), 155 URTWN_DEV(CHICONY, RTL8188CUS_2), 156 URTWN_DEV(CHICONY, RTL8188CUS_3), 157 URTWN_DEV(CHICONY, RTL8188CUS_4), 158 URTWN_DEV(CHICONY, RTL8188CUS_5), 159 URTWN_DEV(CHICONY, RTL8188CUS_6), 160 URTWN_DEV(COMPARE, RTL8192CU), 161 URTWN_DEV(COREGA, RTL8192CU), 162 URTWN_DEV(DLINK, DWA131B), 163 URTWN_DEV(DLINK, RTL8188CU), 164 URTWN_DEV(DLINK, RTL8192CU_1), 165 URTWN_DEV(DLINK, RTL8192CU_2), 166 URTWN_DEV(DLINK, RTL8192CU_3), 167 URTWN_DEV(DLINK, RTL8192CU_4), 168 URTWN_DEV(EDIMAX, RTL8188CU), 169 URTWN_DEV(EDIMAX, RTL8192CU), 170 URTWN_DEV(FEIXUN, RTL8188CU), 171 URTWN_DEV(FEIXUN, RTL8192CU), 172 URTWN_DEV(GUILLEMOT, HWNUP150), 173 URTWN_DEV(GUILLEMOT, RTL8192CU), 174 URTWN_DEV(HAWKING, RTL8192CU), 175 URTWN_DEV(HAWKING, RTL8192CU_2), 176 URTWN_DEV(HP3, RTL8188CU), 177 URTWN_DEV(IODATA, WNG150UM), 178 URTWN_DEV(IODATA, RTL8192CU), 179 URTWN_DEV(NETGEAR, WNA1000M), 180 URTWN_DEV(NETGEAR, RTL8192CU), 181 URTWN_DEV(NETGEAR4, RTL8188CU), 182 URTWN_DEV(NOVATECH, RTL8188CU), 183 URTWN_DEV(PLANEX2, RTL8188CU_1), 184 URTWN_DEV(PLANEX2, RTL8188CU_2), 185 URTWN_DEV(PLANEX2, RTL8192CU), 186 URTWN_DEV(PLANEX2, RTL8188CU_3), 187 URTWN_DEV(PLANEX2, RTL8188CU_4), 188 URTWN_DEV(PLANEX2, RTL8188CUS), 189 URTWN_DEV(REALTEK, RTL8188CE_0), 190 URTWN_DEV(REALTEK, RTL8188CE_1), 191 URTWN_DEV(REALTEK, RTL8188CTV), 192 URTWN_DEV(REALTEK, RTL8188CU_0), 193 URTWN_DEV(REALTEK, RTL8188CU_1), 194 URTWN_DEV(REALTEK, RTL8188CU_2), 195 URTWN_DEV(REALTEK, RTL8188CU_3), 196 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 197 URTWN_DEV(REALTEK, RTL8188CUS), 198 URTWN_DEV(REALTEK, RTL8188RU), 199 URTWN_DEV(REALTEK, RTL8188RU_2), 200 URTWN_DEV(REALTEK, RTL8188RU_3), 201 URTWN_DEV(REALTEK, RTL8191CU), 202 URTWN_DEV(REALTEK, RTL8192CE), 203 URTWN_DEV(REALTEK, RTL8192CU), 204 URTWN_DEV(SITECOMEU, RTL8188CU), 205 URTWN_DEV(SITECOMEU, RTL8188CU_2), 206 URTWN_DEV(SITECOMEU, RTL8192CU), 207 URTWN_DEV(SITECOMEU, RTL8192CUR2), 208 URTWN_DEV(TPLINK, RTL8192CU), 209 URTWN_DEV(TRENDNET, RTL8188CU), 210 URTWN_DEV(TRENDNET, RTL8192CU), 211 URTWN_DEV(TRENDNET, TEW648UBM), 212 URTWN_DEV(ZYXEL, RTL8192CU), 213 214 /* URTWN_RTL8188E */ 215 URTWN_RTL8188E_DEV(ASUSTEK, USBN10NANO_B1), 216 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 217 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 218 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 219 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 220 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 221 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 222 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 223 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 224 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 225 226 /* URTWN_RTL8192EU */ 227 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 228 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 229 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 230 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 231 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 232 }; 233 #undef URTWN_DEV 234 #undef URTWN_RTL8188E_DEV 235 #undef URTWN_RTL8192EU_DEV 236 237 static int urtwn_match(device_t, cfdata_t, void *); 238 static void urtwn_attach(device_t, device_t, void *); 239 static int urtwn_detach(device_t, int); 240 static int urtwn_activate(device_t, enum devact); 241 242 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 243 urtwn_attach, urtwn_detach, urtwn_activate); 244 245 static int urtwn_open_pipes(struct urtwn_softc *); 246 static void urtwn_close_pipes(struct urtwn_softc *); 247 static int urtwn_alloc_rx_list(struct urtwn_softc *); 248 static void urtwn_free_rx_list(struct urtwn_softc *); 249 static int urtwn_alloc_tx_list(struct urtwn_softc *); 250 static void urtwn_free_tx_list(struct urtwn_softc *); 251 static void urtwn_task(void *); 252 static void urtwn_do_async(struct urtwn_softc *, 253 void (*)(struct urtwn_softc *, void *), void *, int); 254 static void urtwn_wait_async(struct urtwn_softc *); 255 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 256 int); 257 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 258 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 259 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 260 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 261 int); 262 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 263 int); 264 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 265 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 266 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 267 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 268 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 269 uint32_t); 270 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 271 uint32_t); 272 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 273 uint32_t); 274 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 275 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 276 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 277 static void urtwn_efuse_read(struct urtwn_softc *); 278 static void urtwn_efuse_switch_power(struct urtwn_softc *); 279 static int urtwn_read_chipid(struct urtwn_softc *); 280 #ifdef URTWN_DEBUG 281 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 282 #endif 283 static void urtwn_read_rom(struct urtwn_softc *); 284 static void urtwn_r88e_read_rom(struct urtwn_softc *); 285 static int urtwn_media_change(struct ifnet *); 286 static int urtwn_ra_init(struct urtwn_softc *); 287 static int urtwn_get_nettype(struct urtwn_softc *); 288 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 289 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 290 static void urtwn_set_led(struct urtwn_softc *, int, int); 291 static void urtwn_calib_to(void *); 292 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 293 static void urtwn_next_scan(void *); 294 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 295 int); 296 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 297 static int urtwn_wme_update(struct ieee80211com *); 298 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 299 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 300 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 301 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 302 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 303 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 304 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 305 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 306 struct ieee80211_node *, struct urtwn_tx_data *); 307 static struct urtwn_tx_data * 308 urtwn_get_tx_data(struct urtwn_softc *, size_t); 309 static void urtwn_start(struct ifnet *); 310 static void urtwn_watchdog(struct ifnet *); 311 static int urtwn_ioctl(struct ifnet *, u_long, void *); 312 static int urtwn_r92c_power_on(struct urtwn_softc *); 313 static int urtwn_r92e_power_on(struct urtwn_softc *); 314 static int urtwn_r88e_power_on(struct urtwn_softc *); 315 static int urtwn_llt_init(struct urtwn_softc *); 316 static void urtwn_fw_reset(struct urtwn_softc *); 317 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 318 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 319 static int urtwn_load_firmware(struct urtwn_softc *); 320 static int urtwn_r92c_dma_init(struct urtwn_softc *); 321 static int urtwn_r88e_dma_init(struct urtwn_softc *); 322 static void urtwn_mac_init(struct urtwn_softc *); 323 static void urtwn_bb_init(struct urtwn_softc *); 324 static void urtwn_rf_init(struct urtwn_softc *); 325 static void urtwn_cam_init(struct urtwn_softc *); 326 static void urtwn_pa_bias_init(struct urtwn_softc *); 327 static void urtwn_rxfilter_init(struct urtwn_softc *); 328 static void urtwn_edca_init(struct urtwn_softc *); 329 static void urtwn_write_txpower(struct urtwn_softc *, int, 330 uint16_t[URTWN_RIDX_COUNT]); 331 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 332 uint16_t[URTWN_RIDX_COUNT]); 333 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 334 u_int, uint16_t[URTWN_RIDX_COUNT]); 335 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 336 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 337 u_int); 338 static void urtwn_iq_calib(struct urtwn_softc *, bool); 339 static void urtwn_lc_calib(struct urtwn_softc *); 340 static void urtwn_temp_calib(struct urtwn_softc *); 341 static int urtwn_init(struct ifnet *); 342 static void urtwn_stop(struct ifnet *, int); 343 static int urtwn_reset(struct ifnet *); 344 static void urtwn_chip_stop(struct urtwn_softc *); 345 static void urtwn_newassoc(struct ieee80211_node *, int); 346 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 347 348 /* Aliases. */ 349 #define urtwn_bb_write urtwn_write_4 350 #define urtwn_bb_read urtwn_read_4 351 352 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 353 354 static const uint16_t addaReg[] = { 355 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 356 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 357 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 358 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 359 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 360 }; 361 362 static int 363 urtwn_match(device_t parent, cfdata_t match, void *aux) 364 { 365 struct usb_attach_arg *uaa = aux; 366 367 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 368 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 369 } 370 371 static void 372 urtwn_attach(device_t parent, device_t self, void *aux) 373 { 374 struct urtwn_softc *sc = device_private(self); 375 struct ieee80211com *ic = &sc->sc_ic; 376 struct ifnet *ifp = &sc->sc_if; 377 struct usb_attach_arg *uaa = aux; 378 char *devinfop; 379 const struct urtwn_dev *dev; 380 usb_device_request_t req; 381 size_t i; 382 int error; 383 384 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 385 386 sc->sc_dev = self; 387 sc->sc_udev = uaa->uaa_device; 388 389 sc->chip = 0; 390 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 391 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 392 SET(sc->chip, URTWN_CHIP_88E); 393 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 394 SET(sc->chip, URTWN_CHIP_92EU); 395 396 aprint_naive("\n"); 397 aprint_normal("\n"); 398 399 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 400 aprint_normal_dev(self, "%s\n", devinfop); 401 usbd_devinfo_free(devinfop); 402 403 req.bmRequestType = UT_WRITE_DEVICE; 404 req.bRequest = UR_SET_FEATURE; 405 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 406 USETW(req.wIndex, UHF_PORT_SUSPEND); 407 USETW(req.wLength, 0); 408 409 (void) usbd_do_request(sc->sc_udev, &req, 0); 410 411 cv_init(&sc->sc_task_cv, "urtwntsk"); 412 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 413 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 414 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 415 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 416 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 417 418 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 419 420 callout_init(&sc->sc_scan_to, 0); 421 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 422 callout_init(&sc->sc_calib_to, 0); 423 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 424 425 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 426 RND_TYPE_NET, RND_FLAG_DEFAULT); 427 428 error = usbd_set_config_no(sc->sc_udev, 1, 0); 429 if (error != 0) { 430 aprint_error_dev(self, "failed to set configuration" 431 ", err=%s\n", usbd_errstr(error)); 432 goto fail; 433 } 434 435 /* Get the first interface handle. */ 436 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 437 if (error != 0) { 438 aprint_error_dev(self, "could not get interface handle\n"); 439 goto fail; 440 } 441 442 error = urtwn_read_chipid(sc); 443 if (error != 0) { 444 aprint_error_dev(self, "unsupported test chip\n"); 445 goto fail; 446 } 447 448 /* Determine number of Tx/Rx chains. */ 449 if (sc->chip & URTWN_CHIP_92C) { 450 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 451 sc->nrxchains = 2; 452 } else if (sc->chip & URTWN_CHIP_92EU) { 453 sc->ntxchains = 2; 454 sc->nrxchains = 2; 455 } else { 456 sc->ntxchains = 1; 457 sc->nrxchains = 1; 458 } 459 460 if (ISSET(sc->chip, URTWN_CHIP_88E) || 461 ISSET(sc->chip, URTWN_CHIP_92EU)) 462 urtwn_r88e_read_rom(sc); 463 else 464 urtwn_read_rom(sc); 465 466 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 467 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 468 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 469 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 470 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 471 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 472 "8188CUS", sc->ntxchains, sc->nrxchains, 473 ether_sprintf(ic->ic_myaddr)); 474 475 error = urtwn_open_pipes(sc); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 478 goto fail; 479 } 480 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 481 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 482 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 483 484 /* 485 * Setup the 802.11 device. 486 */ 487 ic->ic_ifp = ifp; 488 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 489 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 490 ic->ic_state = IEEE80211_S_INIT; 491 492 /* Set device capabilities. */ 493 ic->ic_caps = 494 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 495 IEEE80211_C_IBSS | /* IBSS mode supported */ 496 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 497 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 498 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 499 IEEE80211_C_WME | /* 802.11e */ 500 IEEE80211_C_WPA; /* 802.11i */ 501 502 /* Set supported .11b and .11g rates. */ 503 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 504 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 505 506 /* Set supported .11b and .11g channels (1 through 14). */ 507 for (i = 1; i <= 14; i++) { 508 ic->ic_channels[i].ic_freq = 509 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 510 ic->ic_channels[i].ic_flags = 511 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 512 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 513 } 514 515 ifp->if_softc = sc; 516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 517 ifp->if_init = urtwn_init; 518 ifp->if_ioctl = urtwn_ioctl; 519 ifp->if_start = urtwn_start; 520 ifp->if_watchdog = urtwn_watchdog; 521 IFQ_SET_READY(&ifp->if_snd); 522 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 523 524 if_initialize(ifp); 525 ieee80211_ifattach(ic); 526 527 /* override default methods */ 528 ic->ic_newassoc = urtwn_newassoc; 529 ic->ic_reset = urtwn_reset; 530 ic->ic_wme.wme_update = urtwn_wme_update; 531 532 /* Override state transition machine. */ 533 sc->sc_newstate = ic->ic_newstate; 534 ic->ic_newstate = urtwn_newstate; 535 536 /* XXX media locking needs revisiting */ 537 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 538 ieee80211_media_init_with_lock(ic, 539 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 540 541 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 542 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 543 &sc->sc_drvbpf); 544 545 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 546 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 547 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 548 549 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 550 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 551 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 552 553 ifp->if_percpuq = if_percpuq_create(ifp); 554 if_register(ifp); 555 556 ieee80211_announce(ic); 557 558 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 559 560 if (!pmf_device_register(self, NULL, NULL)) 561 aprint_error_dev(self, "couldn't establish power handler\n"); 562 563 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 564 return; 565 566 fail: 567 sc->sc_dying = 1; 568 aprint_error_dev(self, "attach failed\n"); 569 } 570 571 static int 572 urtwn_detach(device_t self, int flags) 573 { 574 struct urtwn_softc *sc = device_private(self); 575 struct ifnet *ifp = &sc->sc_if; 576 int s; 577 578 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 579 580 pmf_device_deregister(self); 581 582 s = splusb(); 583 584 sc->sc_dying = 1; 585 586 callout_halt(&sc->sc_scan_to, NULL); 587 callout_halt(&sc->sc_calib_to, NULL); 588 589 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 590 urtwn_stop(ifp, 0); 591 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 592 NULL); 593 594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 595 bpf_detach(ifp); 596 ieee80211_ifdetach(&sc->sc_ic); 597 if_detach(ifp); 598 599 mutex_destroy(&sc->sc_media_mtx); 600 601 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 602 urtwn_close_pipes(sc); 603 } 604 605 splx(s); 606 607 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 608 609 rnd_detach_source(&sc->rnd_source); 610 611 callout_destroy(&sc->sc_scan_to); 612 callout_destroy(&sc->sc_calib_to); 613 614 cv_destroy(&sc->sc_task_cv); 615 mutex_destroy(&sc->sc_write_mtx); 616 mutex_destroy(&sc->sc_fwcmd_mtx); 617 mutex_destroy(&sc->sc_tx_mtx); 618 mutex_destroy(&sc->sc_rx_mtx); 619 mutex_destroy(&sc->sc_task_mtx); 620 621 return 0; 622 } 623 624 static int 625 urtwn_activate(device_t self, enum devact act) 626 { 627 struct urtwn_softc *sc = device_private(self); 628 629 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 630 631 switch (act) { 632 case DVACT_DEACTIVATE: 633 if_deactivate(sc->sc_ic.ic_ifp); 634 return 0; 635 default: 636 return EOPNOTSUPP; 637 } 638 } 639 640 static int 641 urtwn_open_pipes(struct urtwn_softc *sc) 642 { 643 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 644 static uint8_t epaddr[R92C_MAX_EPOUT]; 645 static uint8_t rxepaddr[R92C_MAX_EPIN]; 646 usb_interface_descriptor_t *id; 647 usb_endpoint_descriptor_t *ed; 648 size_t i, ntx = 0, nrx = 0; 649 int error; 650 651 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 652 653 /* Determine the number of bulk-out pipes. */ 654 id = usbd_get_interface_descriptor(sc->sc_iface); 655 for (i = 0; i < id->bNumEndpoints; i++) { 656 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 657 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 658 continue; 659 } 660 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 661 if (ntx < sizeof(epaddr)) 662 epaddr[ntx] = ed->bEndpointAddress; 663 ntx++; 664 } 665 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 666 if (nrx < sizeof(rxepaddr)) 667 rxepaddr[nrx] = ed->bEndpointAddress; 668 nrx++; 669 } 670 } 671 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 672 aprint_error_dev(sc->sc_dev, 673 "%zd: invalid number of Rx bulk pipes\n", nrx); 674 return EIO; 675 } 676 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 677 aprint_error_dev(sc->sc_dev, 678 "%zd: invalid number of Tx bulk pipes\n", ntx); 679 return EIO; 680 } 681 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 682 nrx, ntx, 0, 0); 683 sc->rx_npipe = nrx; 684 sc->tx_npipe = ntx; 685 686 /* Open bulk-in pipe at address 0x81. */ 687 for (i = 0; i < nrx; i++) { 688 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 689 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 690 if (error != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "could not open Rx bulk pipe 0x%02x: %d\n", 693 rxepaddr[i], error); 694 goto fail; 695 } 696 } 697 698 /* Open bulk-out pipes (up to 3). */ 699 for (i = 0; i < ntx; i++) { 700 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 701 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 702 if (error != 0) { 703 aprint_error_dev(sc->sc_dev, 704 "could not open Tx bulk pipe 0x%02x: %d\n", 705 epaddr[i], error); 706 goto fail; 707 } 708 } 709 710 /* Map 802.11 access categories to USB pipes. */ 711 sc->ac2idx[WME_AC_BK] = 712 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 713 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 714 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 715 716 fail: 717 if (error != 0) 718 urtwn_close_pipes(sc); 719 return error; 720 } 721 722 static void 723 urtwn_close_pipes(struct urtwn_softc *sc) 724 { 725 struct usbd_pipe *pipe; 726 size_t i; 727 728 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 729 730 /* Close Rx pipes. */ 731 CTASSERT(sizeof(pipe) == sizeof(void *)); 732 for (i = 0; i < sc->rx_npipe; i++) { 733 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 734 if (pipe != NULL) { 735 usbd_close_pipe(pipe); 736 } 737 } 738 739 /* Close Tx pipes. */ 740 for (i = 0; i < sc->tx_npipe; i++) { 741 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 742 if (pipe != NULL) { 743 usbd_close_pipe(pipe); 744 } 745 } 746 } 747 748 static int __noinline 749 urtwn_alloc_rx_list(struct urtwn_softc *sc) 750 { 751 struct urtwn_rx_data *data; 752 size_t i; 753 int error = 0; 754 755 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 756 757 for (size_t j = 0; j < sc->rx_npipe; j++) { 758 TAILQ_INIT(&sc->rx_free_list[j]); 759 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 760 data = &sc->rx_data[j][i]; 761 762 data->sc = sc; /* Backpointer for callbacks. */ 763 data->pidx = j; 764 765 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 766 0, 0, &data->xfer); 767 if (error) { 768 aprint_error_dev(sc->sc_dev, 769 "could not allocate xfer\n"); 770 break; 771 } 772 773 data->buf = usbd_get_buffer(data->xfer); 774 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 775 } 776 } 777 if (error != 0) 778 urtwn_free_rx_list(sc); 779 return error; 780 } 781 782 static void 783 urtwn_free_rx_list(struct urtwn_softc *sc) 784 { 785 struct usbd_xfer *xfer; 786 size_t i; 787 788 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 789 790 /* NB: Caller must abort pipe first. */ 791 for (size_t j = 0; j < sc->rx_npipe; j++) { 792 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 793 CTASSERT(sizeof(xfer) == sizeof(void *)); 794 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 795 if (xfer != NULL) 796 usbd_destroy_xfer(xfer); 797 } 798 } 799 } 800 801 static int __noinline 802 urtwn_alloc_tx_list(struct urtwn_softc *sc) 803 { 804 struct urtwn_tx_data *data; 805 size_t i; 806 int error = 0; 807 808 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 809 810 mutex_enter(&sc->sc_tx_mtx); 811 for (size_t j = 0; j < sc->tx_npipe; j++) { 812 TAILQ_INIT(&sc->tx_free_list[j]); 813 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 814 data = &sc->tx_data[j][i]; 815 816 data->sc = sc; /* Backpointer for callbacks. */ 817 data->pidx = j; 818 819 error = usbd_create_xfer(sc->tx_pipe[j], 820 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 821 &data->xfer); 822 if (error) { 823 aprint_error_dev(sc->sc_dev, 824 "could not allocate xfer\n"); 825 goto fail; 826 } 827 828 data->buf = usbd_get_buffer(data->xfer); 829 830 /* Append this Tx buffer to our free list. */ 831 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 832 } 833 } 834 mutex_exit(&sc->sc_tx_mtx); 835 return 0; 836 837 fail: 838 urtwn_free_tx_list(sc); 839 mutex_exit(&sc->sc_tx_mtx); 840 return error; 841 } 842 843 static void 844 urtwn_free_tx_list(struct urtwn_softc *sc) 845 { 846 struct usbd_xfer *xfer; 847 size_t i; 848 849 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 850 851 /* NB: Caller must abort pipe first. */ 852 for (size_t j = 0; j < sc->tx_npipe; j++) { 853 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 854 CTASSERT(sizeof(xfer) == sizeof(void *)); 855 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 856 if (xfer != NULL) 857 usbd_destroy_xfer(xfer); 858 } 859 } 860 } 861 862 static int 863 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 864 struct ieee80211_node *ni) 865 { 866 struct urtwn_tx_data *data = 867 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 868 869 if (data == NULL) 870 return ENOBUFS; 871 872 return urtwn_tx(sc, m, ni, data); 873 } 874 875 static void 876 urtwn_cmdq_invariants(struct urtwn_softc *sc) 877 { 878 struct urtwn_host_cmd_ring *const ring = &sc->cmdq; 879 880 KASSERT(mutex_owned(&sc->sc_task_mtx)); 881 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 882 "%s: cur=%d next=%d queued=%d", 883 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 884 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 885 "%s: cur=%d next=%d queued=%d", 886 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 887 KASSERTMSG((ring->queued >= 0 && 888 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 889 "%s: %d commands queued", 890 device_xname(sc->sc_dev), ring->queued); 891 } 892 893 static void 894 urtwn_task(void *arg) 895 { 896 struct urtwn_softc *sc = arg; 897 struct ieee80211com *ic = &sc->sc_ic; 898 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 899 struct urtwn_host_cmd *cmd; 900 int s; 901 902 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 903 if (ic->ic_state == IEEE80211_S_RUN && 904 (ic->ic_opmode == IEEE80211_M_HOSTAP || 905 ic->ic_opmode == IEEE80211_M_IBSS)) { 906 907 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 908 &sc->sc_bo); 909 if (m == NULL) { 910 aprint_error_dev(sc->sc_dev, 911 "could not allocate beacon"); 912 } 913 914 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 915 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 916 } 917 918 /* beacon is no longer needed */ 919 m_freem(m); 920 } 921 922 /* Process host commands. */ 923 s = splusb(); 924 mutex_spin_enter(&sc->sc_task_mtx); 925 urtwn_cmdq_invariants(sc); 926 while (ring->next != ring->cur) { 927 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 928 device_xname(sc->sc_dev), 929 ring->cur, ring->next, ring->queued); 930 cmd = &ring->cmd[ring->next]; 931 mutex_spin_exit(&sc->sc_task_mtx); 932 splx(s); 933 /* Invoke callback with kernel lock held. */ 934 cmd->cb(sc, cmd->data); 935 s = splusb(); 936 mutex_spin_enter(&sc->sc_task_mtx); 937 urtwn_cmdq_invariants(sc); 938 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 939 device_xname(sc->sc_dev), 940 ring->cur, ring->next, ring->queued); 941 ring->queued--; 942 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 943 } 944 cv_broadcast(&sc->sc_task_cv); 945 mutex_spin_exit(&sc->sc_task_mtx); 946 splx(s); 947 } 948 949 static void 950 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 951 void *arg, int len) 952 { 953 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 954 struct urtwn_host_cmd *cmd; 955 bool schedtask = false; 956 int s; 957 958 URTWNHIST_FUNC(); 959 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 960 (uintptr_t)cb, (uintptr_t)arg, len, 0); 961 962 s = splusb(); 963 mutex_spin_enter(&sc->sc_task_mtx); 964 urtwn_cmdq_invariants(sc); 965 cmd = &ring->cmd[ring->cur]; 966 cmd->cb = cb; 967 KASSERT(len <= sizeof(cmd->data)); 968 memcpy(cmd->data, arg, len); 969 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 970 971 /* 972 * Schedule a task to process the command if need be. 973 */ 974 if (!sc->sc_dying) { 975 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 976 device_printf(sc->sc_dev, "command queue overflow\n"); 977 else if (ring->queued++ == 0) 978 schedtask = true; 979 } 980 mutex_spin_exit(&sc->sc_task_mtx); 981 splx(s); 982 983 if (schedtask) 984 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 985 } 986 987 static void 988 urtwn_wait_async(struct urtwn_softc *sc) 989 { 990 991 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 992 993 /* Wait for all queued asynchronous commands to complete. */ 994 mutex_spin_enter(&sc->sc_task_mtx); 995 while (sc->cmdq.queued > 0) 996 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 997 mutex_spin_exit(&sc->sc_task_mtx); 998 } 999 1000 static int 1001 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1002 int len) 1003 { 1004 usb_device_request_t req; 1005 usbd_status error; 1006 1007 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1008 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1009 1010 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1011 req.bRequest = R92C_REQ_REGS; 1012 USETW(req.wValue, addr); 1013 USETW(req.wIndex, 0); 1014 USETW(req.wLength, len); 1015 error = usbd_do_request(sc->sc_udev, &req, buf); 1016 if (error != USBD_NORMAL_COMPLETION) { 1017 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1018 error, addr, len, 0); 1019 } 1020 return error; 1021 } 1022 1023 static void 1024 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1025 { 1026 1027 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1028 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1029 1030 urtwn_write_region_1(sc, addr, &val, 1); 1031 } 1032 1033 static void 1034 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1035 { 1036 uint8_t buf[2]; 1037 1038 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1039 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1040 1041 buf[0] = (uint8_t)val; 1042 buf[1] = (uint8_t)(val >> 8); 1043 urtwn_write_region_1(sc, addr, buf, 2); 1044 } 1045 1046 static void 1047 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1048 { 1049 uint8_t buf[4]; 1050 1051 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1052 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1053 1054 buf[0] = (uint8_t)val; 1055 buf[1] = (uint8_t)(val >> 8); 1056 buf[2] = (uint8_t)(val >> 16); 1057 buf[3] = (uint8_t)(val >> 24); 1058 urtwn_write_region_1(sc, addr, buf, 4); 1059 } 1060 1061 static int 1062 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1063 { 1064 1065 URTWNHIST_FUNC(); 1066 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1067 1068 return urtwn_write_region_1(sc, addr, buf, len); 1069 } 1070 1071 static int 1072 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1073 int len) 1074 { 1075 usb_device_request_t req; 1076 usbd_status error; 1077 1078 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1079 1080 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1081 req.bRequest = R92C_REQ_REGS; 1082 USETW(req.wValue, addr); 1083 USETW(req.wIndex, 0); 1084 USETW(req.wLength, len); 1085 error = usbd_do_request(sc->sc_udev, &req, buf); 1086 if (error != USBD_NORMAL_COMPLETION) { 1087 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1088 error, addr, len, 0); 1089 } 1090 return error; 1091 } 1092 1093 static uint8_t 1094 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1095 { 1096 uint8_t val; 1097 1098 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1099 1100 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1101 return 0xff; 1102 1103 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1104 return val; 1105 } 1106 1107 static uint16_t 1108 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1109 { 1110 uint8_t buf[2]; 1111 uint16_t val; 1112 1113 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1114 1115 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1116 return 0xffff; 1117 1118 val = LE_READ_2(&buf[0]); 1119 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1120 return val; 1121 } 1122 1123 static uint32_t 1124 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1125 { 1126 uint8_t buf[4]; 1127 uint32_t val; 1128 1129 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1130 1131 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1132 return 0xffffffff; 1133 1134 val = LE_READ_4(&buf[0]); 1135 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1136 return val; 1137 } 1138 1139 static int 1140 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1141 { 1142 struct r92c_fw_cmd cmd; 1143 uint8_t *cp; 1144 int fwcur; 1145 int ntries; 1146 1147 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1148 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1149 1150 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1151 1152 mutex_enter(&sc->sc_fwcmd_mtx); 1153 fwcur = sc->fwcur; 1154 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1155 1156 /* Wait for current FW box to be empty. */ 1157 for (ntries = 0; ntries < 100; ntries++) { 1158 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1159 break; 1160 urtwn_delay_ms(sc, 2); 1161 } 1162 if (ntries == 100) { 1163 aprint_error_dev(sc->sc_dev, 1164 "could not send firmware command %d\n", id); 1165 mutex_exit(&sc->sc_fwcmd_mtx); 1166 return ETIMEDOUT; 1167 } 1168 1169 memset(&cmd, 0, sizeof(cmd)); 1170 KASSERT(len <= sizeof(cmd.msg)); 1171 memcpy(cmd.msg, buf, len); 1172 1173 /* Write the first word last since that will trigger the FW. */ 1174 cp = (uint8_t *)&cmd; 1175 cmd.id = id; 1176 if (len >= 4) { 1177 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1178 cmd.id |= R92C_CMD_FLAG_EXT; 1179 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1180 &cp[1], 2); 1181 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1182 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1183 ((uint32_t)cp[5] << 24)); 1184 } else { 1185 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1186 &cp[4], 2); 1187 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1188 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1189 ((uint32_t)cp[3] << 24)); 1190 } 1191 } else { 1192 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1193 } 1194 mutex_exit(&sc->sc_fwcmd_mtx); 1195 1196 return 0; 1197 } 1198 1199 static __inline void 1200 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1201 { 1202 1203 sc->sc_rf_write(sc, chain, addr, val); 1204 } 1205 1206 static void 1207 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1208 uint32_t val) 1209 { 1210 1211 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1212 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1213 } 1214 1215 static void 1216 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1217 uint32_t val) 1218 { 1219 1220 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1221 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1222 } 1223 1224 static void 1225 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1226 uint32_t val) 1227 { 1228 1229 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1230 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1231 } 1232 1233 static uint32_t 1234 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1235 { 1236 uint32_t reg[R92C_MAX_CHAINS], val; 1237 1238 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1239 if (chain != 0) { 1240 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1241 } 1242 1243 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1244 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1245 urtwn_delay_ms(sc, 1); 1246 1247 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1248 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1249 R92C_HSSI_PARAM2_READ_EDGE); 1250 urtwn_delay_ms(sc, 1); 1251 1252 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1253 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1254 urtwn_delay_ms(sc, 1); 1255 1256 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1257 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1258 } else { 1259 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1260 } 1261 return MS(val, R92C_LSSI_READBACK_DATA); 1262 } 1263 1264 static int 1265 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1266 { 1267 int ntries; 1268 1269 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1270 1271 urtwn_write_4(sc, R92C_LLT_INIT, 1272 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1273 SM(R92C_LLT_INIT_ADDR, addr) | 1274 SM(R92C_LLT_INIT_DATA, data)); 1275 /* Wait for write operation to complete. */ 1276 for (ntries = 0; ntries < 20; ntries++) { 1277 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1278 R92C_LLT_INIT_OP_NO_ACTIVE) { 1279 /* Done */ 1280 return 0; 1281 } 1282 DELAY(5); 1283 } 1284 return ETIMEDOUT; 1285 } 1286 1287 static uint8_t 1288 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1289 { 1290 uint32_t reg; 1291 int ntries; 1292 1293 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1294 1295 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1296 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1297 reg &= ~R92C_EFUSE_CTRL_VALID; 1298 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1299 1300 /* Wait for read operation to complete. */ 1301 for (ntries = 0; ntries < 100; ntries++) { 1302 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1303 if (reg & R92C_EFUSE_CTRL_VALID) { 1304 /* Done */ 1305 return MS(reg, R92C_EFUSE_CTRL_DATA); 1306 } 1307 DELAY(5); 1308 } 1309 aprint_error_dev(sc->sc_dev, 1310 "could not read efuse byte at address 0x%04x\n", addr); 1311 return 0xff; 1312 } 1313 1314 static void 1315 urtwn_efuse_read(struct urtwn_softc *sc) 1316 { 1317 uint8_t *rom = (uint8_t *)&sc->rom; 1318 uint32_t reg; 1319 uint16_t addr = 0; 1320 uint8_t off, msk; 1321 size_t i; 1322 1323 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1324 1325 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1326 1327 urtwn_efuse_switch_power(sc); 1328 1329 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1330 while (addr < 512) { 1331 reg = urtwn_efuse_read_1(sc, addr); 1332 if (reg == 0xff) 1333 break; 1334 addr++; 1335 off = reg >> 4; 1336 msk = reg & 0xf; 1337 for (i = 0; i < 4; i++) { 1338 if (msk & (1U << i)) 1339 continue; 1340 1341 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1342 addr++; 1343 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1344 addr++; 1345 } 1346 } 1347 #ifdef URTWN_DEBUG 1348 /* Dump ROM content. */ 1349 for (i = 0; i < (int)sizeof(sc->rom); i++) 1350 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1351 #endif 1352 } 1353 1354 static void 1355 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1356 { 1357 uint32_t reg; 1358 1359 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1360 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1361 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1362 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1363 } 1364 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1365 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1366 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1367 reg | R92C_SYS_FUNC_EN_ELDR); 1368 } 1369 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1370 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1371 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1372 urtwn_write_2(sc, R92C_SYS_CLKR, 1373 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1374 } 1375 } 1376 1377 static int 1378 urtwn_read_chipid(struct urtwn_softc *sc) 1379 { 1380 uint32_t reg; 1381 1382 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1383 1384 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1385 ISSET(sc->chip, URTWN_CHIP_92EU)) 1386 return 0; 1387 1388 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1389 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1390 /* test chip, not supported */ 1391 return EIO; 1392 } 1393 if (reg & R92C_SYS_CFG_TYPE_92C) { 1394 sc->chip |= URTWN_CHIP_92C; 1395 /* Check if it is a castrated 8192C. */ 1396 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1397 R92C_HPON_FSM_CHIP_BONDING_ID) == 1398 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1399 sc->chip |= URTWN_CHIP_92C_1T2R; 1400 } 1401 } 1402 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1403 sc->chip |= URTWN_CHIP_UMC; 1404 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1405 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1406 } 1407 } 1408 return 0; 1409 } 1410 1411 #ifdef URTWN_DEBUG 1412 static void 1413 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1414 { 1415 1416 aprint_normal_dev(sc->sc_dev, 1417 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1418 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1419 1420 aprint_normal_dev(sc->sc_dev, 1421 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1422 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1423 1424 aprint_normal_dev(sc->sc_dev, 1425 "macaddr %s\n", 1426 ether_sprintf(rp->macaddr)); 1427 1428 aprint_normal_dev(sc->sc_dev, 1429 "string %s, subcustomer_id %#x\n", 1430 rp->string, rp->subcustomer_id); 1431 1432 aprint_normal_dev(sc->sc_dev, 1433 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1434 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1435 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1436 1437 aprint_normal_dev(sc->sc_dev, 1438 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1439 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1440 rp->ht40_1s_tx_pwr[0][2], 1441 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1442 rp->ht40_1s_tx_pwr[1][2]); 1443 1444 aprint_normal_dev(sc->sc_dev, 1445 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1446 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1447 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1448 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1449 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1450 1451 aprint_normal_dev(sc->sc_dev, 1452 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1453 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1454 rp->ht20_tx_pwr_diff[2] & 0xf, 1455 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1456 rp->ht20_tx_pwr_diff[2] >> 4); 1457 1458 aprint_normal_dev(sc->sc_dev, 1459 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1460 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1461 rp->ofdm_tx_pwr_diff[2] & 0xf, 1462 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1463 rp->ofdm_tx_pwr_diff[2] >> 4); 1464 1465 aprint_normal_dev(sc->sc_dev, 1466 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1467 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1468 rp->ht40_max_pwr[2] & 0xf, 1469 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1470 rp->ht40_max_pwr[2] >> 4); 1471 1472 aprint_normal_dev(sc->sc_dev, 1473 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1474 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1475 rp->ht20_max_pwr[2] & 0xf, 1476 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1477 rp->ht20_max_pwr[2] >> 4); 1478 1479 aprint_normal_dev(sc->sc_dev, 1480 "xtal_calib %d, tssi %d %d, thermal %d\n", 1481 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1482 1483 aprint_normal_dev(sc->sc_dev, 1484 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1485 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1486 1487 aprint_normal_dev(sc->sc_dev, 1488 "channnel_plan %d, version %d customer_id %#x\n", 1489 rp->channel_plan, rp->version, rp->curstomer_id); 1490 } 1491 #endif 1492 1493 static void 1494 urtwn_read_rom(struct urtwn_softc *sc) 1495 { 1496 struct ieee80211com *ic = &sc->sc_ic; 1497 struct r92c_rom *rom = &sc->rom; 1498 1499 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1500 1501 mutex_enter(&sc->sc_write_mtx); 1502 1503 /* Read full ROM image. */ 1504 urtwn_efuse_read(sc); 1505 #ifdef URTWN_DEBUG 1506 if (urtwn_debug & DBG_REG) 1507 urtwn_dump_rom(sc, rom); 1508 #endif 1509 1510 /* XXX Weird but this is what the vendor driver does. */ 1511 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1512 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1513 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1514 1515 DPRINTFN(DBG_INIT, 1516 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1517 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1518 1519 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1520 1521 sc->sc_rf_write = urtwn_r92c_rf_write; 1522 sc->sc_power_on = urtwn_r92c_power_on; 1523 sc->sc_dma_init = urtwn_r92c_dma_init; 1524 1525 mutex_exit(&sc->sc_write_mtx); 1526 } 1527 1528 static void 1529 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1530 { 1531 struct ieee80211com *ic = &sc->sc_ic; 1532 uint8_t *rom = sc->r88e_rom; 1533 uint32_t reg; 1534 uint16_t addr = 0; 1535 uint8_t off, msk, tmp; 1536 int i; 1537 1538 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1539 1540 mutex_enter(&sc->sc_write_mtx); 1541 1542 off = 0; 1543 urtwn_efuse_switch_power(sc); 1544 1545 /* Read full ROM image. */ 1546 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1547 while (addr < 4096) { 1548 reg = urtwn_efuse_read_1(sc, addr); 1549 if (reg == 0xff) 1550 break; 1551 addr++; 1552 if ((reg & 0x1f) == 0x0f) { 1553 tmp = (reg & 0xe0) >> 5; 1554 reg = urtwn_efuse_read_1(sc, addr); 1555 if ((reg & 0x0f) != 0x0f) 1556 off = ((reg & 0xf0) >> 1) | tmp; 1557 addr++; 1558 } else 1559 off = reg >> 4; 1560 msk = reg & 0xf; 1561 for (i = 0; i < 4; i++) { 1562 if (msk & (1 << i)) 1563 continue; 1564 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1565 addr++; 1566 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1567 addr++; 1568 } 1569 } 1570 #ifdef URTWN_DEBUG 1571 if (urtwn_debug & DBG_REG) { 1572 } 1573 #endif 1574 1575 addr = 0x10; 1576 for (i = 0; i < 6; i++) 1577 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1578 for (i = 0; i < 5; i++) 1579 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1580 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1581 if (sc->bw20_tx_pwr_diff & 0x08) 1582 sc->bw20_tx_pwr_diff |= 0xf0; 1583 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1584 if (sc->ofdm_tx_pwr_diff & 0x08) 1585 sc->ofdm_tx_pwr_diff |= 0xf0; 1586 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1587 1588 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1589 1590 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1591 sc->sc_power_on = urtwn_r92e_power_on; 1592 sc->sc_rf_write = urtwn_r92e_rf_write; 1593 } else { 1594 sc->sc_power_on = urtwn_r88e_power_on; 1595 sc->sc_rf_write = urtwn_r88e_rf_write; 1596 } 1597 sc->sc_dma_init = urtwn_r88e_dma_init; 1598 1599 mutex_exit(&sc->sc_write_mtx); 1600 } 1601 1602 static int 1603 urtwn_media_change(struct ifnet *ifp) 1604 { 1605 int error; 1606 1607 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1608 1609 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1610 return error; 1611 1612 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1613 (IFF_UP | IFF_RUNNING)) { 1614 urtwn_init(ifp); 1615 } 1616 return 0; 1617 } 1618 1619 /* 1620 * Initialize rate adaptation in firmware. 1621 */ 1622 static int __noinline 1623 urtwn_ra_init(struct urtwn_softc *sc) 1624 { 1625 static const uint8_t map[] = { 1626 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1627 }; 1628 struct ieee80211com *ic = &sc->sc_ic; 1629 struct ieee80211_node *ni = ic->ic_bss; 1630 struct ieee80211_rateset *rs = &ni->ni_rates; 1631 struct r92c_fw_cmd_macid_cfg cmd; 1632 uint32_t rates, basicrates; 1633 uint32_t rrsr_mask, rrsr_rate; 1634 uint8_t mode; 1635 size_t maxrate, maxbasicrate, i, j; 1636 int error; 1637 1638 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1639 1640 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1641 1642 /* Get normal and basic rates mask. */ 1643 rates = basicrates = 1; 1644 maxrate = maxbasicrate = 0; 1645 for (i = 0; i < rs->rs_nrates; i++) { 1646 /* Convert 802.11 rate to HW rate index. */ 1647 for (j = 0; j < __arraycount(map); j++) { 1648 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1649 break; 1650 } 1651 } 1652 if (j == __arraycount(map)) { 1653 /* Unknown rate, skip. */ 1654 continue; 1655 } 1656 1657 rates |= 1U << j; 1658 if (j > maxrate) { 1659 maxrate = j; 1660 } 1661 1662 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1663 basicrates |= 1U << j; 1664 if (j > maxbasicrate) { 1665 maxbasicrate = j; 1666 } 1667 } 1668 } 1669 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1670 mode = R92C_RAID_11B; 1671 } else { 1672 mode = R92C_RAID_11BG; 1673 } 1674 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1675 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1676 "maxrate=%jx, maxbasicrate=%jx", 1677 rates, basicrates, maxrate, maxbasicrate); 1678 1679 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1680 maxbasicrate |= R92C_RATE_SHORTGI; 1681 maxrate |= R92C_RATE_SHORTGI; 1682 } 1683 1684 /* Set rates mask for group addressed frames. */ 1685 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1686 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1687 cmd.macid |= RTWN_MACID_SHORTGI; 1688 cmd.mask = htole32((mode << 28) | basicrates); 1689 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1690 if (error != 0) { 1691 aprint_error_dev(sc->sc_dev, 1692 "could not add broadcast station\n"); 1693 return error; 1694 } 1695 /* Set initial MRR rate. */ 1696 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1697 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1698 1699 /* Set rates mask for unicast frames. */ 1700 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1701 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1702 cmd.macid |= RTWN_MACID_SHORTGI; 1703 cmd.mask = htole32((mode << 28) | rates); 1704 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1705 if (error != 0) { 1706 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1707 return error; 1708 } 1709 /* Set initial MRR rate. */ 1710 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1711 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1712 1713 rrsr_rate = ic->ic_fixed_rate; 1714 if (rrsr_rate == -1) 1715 rrsr_rate = 11; 1716 1717 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1718 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1719 1720 /* Indicate highest supported rate. */ 1721 ni->ni_txrate = rs->rs_nrates - 1; 1722 1723 return 0; 1724 } 1725 1726 static int 1727 urtwn_get_nettype(struct urtwn_softc *sc) 1728 { 1729 struct ieee80211com *ic = &sc->sc_ic; 1730 int type; 1731 1732 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1733 1734 switch (ic->ic_opmode) { 1735 case IEEE80211_M_STA: 1736 type = R92C_CR_NETTYPE_INFRA; 1737 break; 1738 1739 case IEEE80211_M_IBSS: 1740 type = R92C_CR_NETTYPE_ADHOC; 1741 break; 1742 1743 default: 1744 type = R92C_CR_NETTYPE_NOLINK; 1745 break; 1746 } 1747 1748 return type; 1749 } 1750 1751 static void 1752 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1753 { 1754 uint8_t reg; 1755 1756 URTWNHIST_FUNC(); 1757 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1758 1759 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1760 1761 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1762 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1763 } 1764 1765 static void 1766 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1767 { 1768 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1769 uint64_t tsf; 1770 1771 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1772 1773 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1774 1775 /* Enable TSF synchronization. */ 1776 urtwn_write_1(sc, R92C_BCN_CTRL, 1777 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1778 1779 /* Correct TSF */ 1780 urtwn_write_1(sc, R92C_BCN_CTRL, 1781 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1782 1783 /* Set initial TSF. */ 1784 tsf = ni->ni_tstamp.tsf; 1785 tsf = le64toh(tsf); 1786 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1787 tsf -= IEEE80211_DUR_TU; 1788 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1789 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1790 1791 urtwn_write_1(sc, R92C_BCN_CTRL, 1792 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1793 } 1794 1795 static void 1796 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1797 { 1798 uint8_t reg; 1799 1800 URTWNHIST_FUNC(); 1801 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1802 1803 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1804 1805 if (led == URTWN_LED_LINK) { 1806 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1807 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1808 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1809 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1810 (R92C_LEDCFG0_DIS << 1)); 1811 if (on) { 1812 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1813 R92E_LEDSON; 1814 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1815 } 1816 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1817 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1818 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1819 if (!on) { 1820 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1821 urtwn_write_1(sc, R92C_LEDCFG2, 1822 reg | R92C_LEDCFG0_DIS); 1823 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1824 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1825 reg & 0xfe); 1826 } 1827 } else { 1828 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1829 if (!on) { 1830 reg |= R92C_LEDCFG0_DIS; 1831 } 1832 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1833 } 1834 sc->ledlink = on; /* Save LED state. */ 1835 } 1836 } 1837 1838 static void 1839 urtwn_calib_to(void *arg) 1840 { 1841 struct urtwn_softc *sc = arg; 1842 1843 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1844 1845 if (sc->sc_dying) 1846 return; 1847 1848 /* Do it in a process context. */ 1849 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1850 } 1851 1852 /* ARGSUSED */ 1853 static void 1854 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1855 { 1856 struct r92c_fw_cmd_rssi cmd; 1857 struct r92e_fw_cmd_rssi cmde; 1858 1859 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1860 1861 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1862 goto restart_timer; 1863 1864 mutex_enter(&sc->sc_write_mtx); 1865 if (sc->avg_pwdb != -1) { 1866 /* Indicate Rx signal strength to FW for rate adaptation. */ 1867 memset(&cmd, 0, sizeof(cmd)); 1868 memset(&cmde, 0, sizeof(cmde)); 1869 cmd.macid = 0; /* BSS. */ 1870 cmde.macid = 0; /* BSS. */ 1871 cmd.pwdb = sc->avg_pwdb; 1872 cmde.pwdb = sc->avg_pwdb; 1873 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1874 sc->avg_pwdb, 0, 0, 0); 1875 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1876 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1877 sizeof(cmd)); 1878 } else { 1879 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1880 sizeof(cmde)); 1881 } 1882 } 1883 1884 /* Do temperature compensation. */ 1885 urtwn_temp_calib(sc); 1886 mutex_exit(&sc->sc_write_mtx); 1887 1888 restart_timer: 1889 if (!sc->sc_dying) { 1890 /* Restart calibration timer. */ 1891 callout_schedule(&sc->sc_calib_to, hz); 1892 } 1893 } 1894 1895 static void 1896 urtwn_next_scan(void *arg) 1897 { 1898 struct urtwn_softc *sc = arg; 1899 int s; 1900 1901 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1902 1903 if (sc->sc_dying) 1904 return; 1905 1906 s = splnet(); 1907 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1908 ieee80211_next_scan(&sc->sc_ic); 1909 splx(s); 1910 } 1911 1912 static void 1913 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1914 { 1915 URTWNHIST_FUNC(); 1916 URTWNHIST_CALLARGS("new node %06jx%06jx", 1917 ni->ni_macaddr[0] << 2 | 1918 ni->ni_macaddr[1] << 1 | 1919 ni->ni_macaddr[2], 1920 ni->ni_macaddr[3] << 2 | 1921 ni->ni_macaddr[4] << 1 | 1922 ni->ni_macaddr[5], 1923 0, 0); 1924 /* start with lowest Tx rate */ 1925 ni->ni_txrate = 0; 1926 } 1927 1928 static int 1929 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1930 { 1931 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1932 struct urtwn_cmd_newstate cmd; 1933 1934 URTWNHIST_FUNC(); 1935 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1936 1937 callout_stop(&sc->sc_scan_to); 1938 callout_stop(&sc->sc_calib_to); 1939 1940 /* Do it in a process context. */ 1941 cmd.state = nstate; 1942 cmd.arg = arg; 1943 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1944 return 0; 1945 } 1946 1947 static void 1948 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1949 { 1950 struct urtwn_cmd_newstate *cmd = arg; 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 struct ieee80211_node *ni; 1953 enum ieee80211_state ostate = ic->ic_state; 1954 enum ieee80211_state nstate = cmd->state; 1955 uint32_t reg; 1956 uint8_t sifs_time, msr; 1957 int s; 1958 1959 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1960 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1961 1962 s = splnet(); 1963 mutex_enter(&sc->sc_write_mtx); 1964 1965 callout_stop(&sc->sc_scan_to); 1966 callout_stop(&sc->sc_calib_to); 1967 1968 switch (ostate) { 1969 case IEEE80211_S_INIT: 1970 break; 1971 1972 case IEEE80211_S_SCAN: 1973 if (nstate != IEEE80211_S_SCAN) { 1974 /* 1975 * End of scanning 1976 */ 1977 /* flush 4-AC Queue after site_survey */ 1978 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1979 1980 /* Allow Rx from our BSSID only. */ 1981 urtwn_write_4(sc, R92C_RCR, 1982 urtwn_read_4(sc, R92C_RCR) | 1983 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1984 } 1985 break; 1986 1987 case IEEE80211_S_AUTH: 1988 case IEEE80211_S_ASSOC: 1989 break; 1990 1991 case IEEE80211_S_RUN: 1992 /* Turn link LED off. */ 1993 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1994 1995 /* Set media status to 'No Link'. */ 1996 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1997 1998 /* Stop Rx of data frames. */ 1999 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2000 2001 /* Reset TSF. */ 2002 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2003 2004 /* Disable TSF synchronization. */ 2005 urtwn_write_1(sc, R92C_BCN_CTRL, 2006 urtwn_read_1(sc, R92C_BCN_CTRL) | 2007 R92C_BCN_CTRL_DIS_TSF_UDT0); 2008 2009 /* Back to 20MHz mode */ 2010 urtwn_set_chan(sc, ic->ic_curchan, 2011 IEEE80211_HTINFO_2NDCHAN_NONE); 2012 2013 if (ic->ic_opmode == IEEE80211_M_IBSS || 2014 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2015 /* Stop BCN */ 2016 urtwn_write_1(sc, R92C_BCN_CTRL, 2017 urtwn_read_1(sc, R92C_BCN_CTRL) & 2018 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2019 } 2020 2021 /* Reset EDCA parameters. */ 2022 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2023 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2024 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2025 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2026 2027 /* flush all cam entries */ 2028 urtwn_cam_init(sc); 2029 break; 2030 } 2031 2032 switch (nstate) { 2033 case IEEE80211_S_INIT: 2034 /* Turn link LED off. */ 2035 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2036 break; 2037 2038 case IEEE80211_S_SCAN: 2039 if (ostate != IEEE80211_S_SCAN) { 2040 /* 2041 * Begin of scanning 2042 */ 2043 2044 /* Set gain for scanning. */ 2045 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2046 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2047 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2048 2049 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2050 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2051 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2052 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2053 } 2054 2055 /* Set media status to 'No Link'. */ 2056 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2057 2058 /* Allow Rx from any BSSID. */ 2059 urtwn_write_4(sc, R92C_RCR, 2060 urtwn_read_4(sc, R92C_RCR) & 2061 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2062 2063 /* Stop Rx of data frames. */ 2064 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2065 2066 /* Disable update TSF */ 2067 urtwn_write_1(sc, R92C_BCN_CTRL, 2068 urtwn_read_1(sc, R92C_BCN_CTRL) | 2069 R92C_BCN_CTRL_DIS_TSF_UDT0); 2070 } 2071 2072 /* Make link LED blink during scan. */ 2073 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2074 2075 /* Pause AC Tx queues. */ 2076 urtwn_write_1(sc, R92C_TXPAUSE, 2077 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2078 2079 urtwn_set_chan(sc, ic->ic_curchan, 2080 IEEE80211_HTINFO_2NDCHAN_NONE); 2081 2082 /* Start periodic scan. */ 2083 if (!sc->sc_dying) 2084 callout_schedule(&sc->sc_scan_to, hz / 5); 2085 break; 2086 2087 case IEEE80211_S_AUTH: 2088 /* Set initial gain under link. */ 2089 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2090 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2091 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2092 2093 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2094 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2095 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2096 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2097 } 2098 2099 /* Set media status to 'No Link'. */ 2100 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2101 2102 /* Allow Rx from any BSSID. */ 2103 urtwn_write_4(sc, R92C_RCR, 2104 urtwn_read_4(sc, R92C_RCR) & 2105 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2106 2107 urtwn_set_chan(sc, ic->ic_curchan, 2108 IEEE80211_HTINFO_2NDCHAN_NONE); 2109 break; 2110 2111 case IEEE80211_S_ASSOC: 2112 break; 2113 2114 case IEEE80211_S_RUN: 2115 ni = ic->ic_bss; 2116 2117 /* XXX: Set 20MHz mode */ 2118 urtwn_set_chan(sc, ic->ic_curchan, 2119 IEEE80211_HTINFO_2NDCHAN_NONE); 2120 2121 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2122 /* Back to 20MHz mode */ 2123 urtwn_set_chan(sc, ic->ic_curchan, 2124 IEEE80211_HTINFO_2NDCHAN_NONE); 2125 2126 /* Set media status to 'No Link'. */ 2127 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2128 2129 /* Enable Rx of data frames. */ 2130 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2131 2132 /* Allow Rx from any BSSID. */ 2133 urtwn_write_4(sc, R92C_RCR, 2134 urtwn_read_4(sc, R92C_RCR) & 2135 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2136 2137 /* Accept Rx data/control/management frames */ 2138 urtwn_write_4(sc, R92C_RCR, 2139 urtwn_read_4(sc, R92C_RCR) | 2140 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2141 2142 /* Turn link LED on. */ 2143 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2144 break; 2145 } 2146 2147 /* Set media status to 'Associated'. */ 2148 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2149 2150 /* Set BSSID. */ 2151 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2152 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2153 2154 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2155 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2156 } else { 2157 /* 802.11b/g */ 2158 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2159 } 2160 2161 /* Enable Rx of data frames. */ 2162 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2163 2164 /* Set beacon interval. */ 2165 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2166 2167 msr = urtwn_read_1(sc, R92C_MSR); 2168 msr &= R92C_MSR_MASK; 2169 switch (ic->ic_opmode) { 2170 case IEEE80211_M_STA: 2171 /* Allow Rx from our BSSID only. */ 2172 urtwn_write_4(sc, R92C_RCR, 2173 urtwn_read_4(sc, R92C_RCR) | 2174 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2175 2176 /* Enable TSF synchronization. */ 2177 urtwn_tsf_sync_enable(sc); 2178 2179 msr |= R92C_MSR_INFRA; 2180 break; 2181 case IEEE80211_M_HOSTAP: 2182 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2183 2184 /* Allow Rx from any BSSID. */ 2185 urtwn_write_4(sc, R92C_RCR, 2186 urtwn_read_4(sc, R92C_RCR) & 2187 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2188 2189 /* Reset TSF timer to zero. */ 2190 reg = urtwn_read_4(sc, R92C_TCR); 2191 reg &= ~0x01; 2192 urtwn_write_4(sc, R92C_TCR, reg); 2193 reg |= 0x01; 2194 urtwn_write_4(sc, R92C_TCR, reg); 2195 2196 msr |= R92C_MSR_AP; 2197 break; 2198 default: 2199 msr |= R92C_MSR_ADHOC; 2200 break; 2201 } 2202 urtwn_write_1(sc, R92C_MSR, msr); 2203 2204 sifs_time = 10; 2205 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2206 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2207 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2208 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2209 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2210 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2211 2212 /* Initialize rate adaptation. */ 2213 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2214 ISSET(sc->chip, URTWN_CHIP_92EU)) 2215 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2216 else 2217 urtwn_ra_init(sc); 2218 2219 /* Turn link LED on. */ 2220 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2221 2222 /* Reset average RSSI. */ 2223 sc->avg_pwdb = -1; 2224 2225 /* Reset temperature calibration state machine. */ 2226 sc->thcal_state = 0; 2227 sc->thcal_lctemp = 0; 2228 2229 /* Start periodic calibration. */ 2230 if (!sc->sc_dying) 2231 callout_schedule(&sc->sc_calib_to, hz); 2232 break; 2233 } 2234 2235 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2236 2237 mutex_exit(&sc->sc_write_mtx); 2238 splx(s); 2239 } 2240 2241 static int 2242 urtwn_wme_update(struct ieee80211com *ic) 2243 { 2244 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2245 2246 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2247 2248 /* don't override default WME values if WME is not actually enabled */ 2249 if (!(ic->ic_flags & IEEE80211_F_WME)) 2250 return 0; 2251 2252 /* Do it in a process context. */ 2253 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2254 return 0; 2255 } 2256 2257 static void 2258 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2259 { 2260 static const uint16_t ac2reg[WME_NUM_AC] = { 2261 R92C_EDCA_BE_PARAM, 2262 R92C_EDCA_BK_PARAM, 2263 R92C_EDCA_VI_PARAM, 2264 R92C_EDCA_VO_PARAM 2265 }; 2266 struct ieee80211com *ic = &sc->sc_ic; 2267 const struct wmeParams *wmep; 2268 int ac, aifs, slottime; 2269 int s; 2270 2271 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2272 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2273 2274 s = splnet(); 2275 mutex_enter(&sc->sc_write_mtx); 2276 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2277 for (ac = 0; ac < WME_NUM_AC; ac++) { 2278 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2279 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2280 aifs = wmep->wmep_aifsn * slottime + 10; 2281 urtwn_write_4(sc, ac2reg[ac], 2282 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2283 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2284 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2285 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2286 } 2287 mutex_exit(&sc->sc_write_mtx); 2288 splx(s); 2289 } 2290 2291 static void 2292 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2293 { 2294 int pwdb; 2295 2296 URTWNHIST_FUNC(); 2297 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2298 2299 /* Convert antenna signal to percentage. */ 2300 if (rssi <= -100 || rssi >= 20) 2301 pwdb = 0; 2302 else if (rssi >= 0) 2303 pwdb = 100; 2304 else 2305 pwdb = 100 + rssi; 2306 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2307 if (rate <= 3) { 2308 /* CCK gain is smaller than OFDM/MCS gain. */ 2309 pwdb += 6; 2310 if (pwdb > 100) 2311 pwdb = 100; 2312 if (pwdb <= 14) 2313 pwdb -= 4; 2314 else if (pwdb <= 26) 2315 pwdb -= 8; 2316 else if (pwdb <= 34) 2317 pwdb -= 6; 2318 else if (pwdb <= 42) 2319 pwdb -= 2; 2320 } 2321 } 2322 if (sc->avg_pwdb == -1) /* Init. */ 2323 sc->avg_pwdb = pwdb; 2324 else if (sc->avg_pwdb < pwdb) 2325 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2326 else 2327 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2328 2329 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2330 rate, rssi, pwdb, sc->avg_pwdb); 2331 } 2332 2333 static int8_t 2334 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2335 { 2336 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2337 struct r92c_rx_phystat *phy; 2338 struct r92c_rx_cck *cck; 2339 uint8_t rpt; 2340 int8_t rssi; 2341 2342 URTWNHIST_FUNC(); 2343 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2344 2345 if (rate <= 3) { 2346 cck = (struct r92c_rx_cck *)physt; 2347 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2348 rpt = (cck->agc_rpt >> 5) & 0x3; 2349 rssi = (cck->agc_rpt & 0x1f) << 1; 2350 } else { 2351 rpt = (cck->agc_rpt >> 6) & 0x3; 2352 rssi = cck->agc_rpt & 0x3e; 2353 } 2354 rssi = cckoff[rpt] - rssi; 2355 } else { /* OFDM/HT. */ 2356 phy = (struct r92c_rx_phystat *)physt; 2357 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2358 } 2359 return rssi; 2360 } 2361 2362 static int8_t 2363 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2364 { 2365 struct r92c_rx_phystat *phy; 2366 struct r88e_rx_cck *cck; 2367 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2368 int8_t rssi; 2369 2370 URTWNHIST_FUNC(); 2371 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2372 2373 rssi = 0; 2374 if (rate <= 3) { 2375 cck = (struct r88e_rx_cck *)physt; 2376 cck_agc_rpt = cck->agc_rpt; 2377 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2378 vga_idx = cck_agc_rpt & 0x1f; 2379 switch (lna_idx) { 2380 case 7: 2381 if (vga_idx <= 27) 2382 rssi = -100 + 2* (27 - vga_idx); 2383 else 2384 rssi = -100; 2385 break; 2386 case 6: 2387 rssi = -48 + 2 * (2 - vga_idx); 2388 break; 2389 case 5: 2390 rssi = -42 + 2 * (7 - vga_idx); 2391 break; 2392 case 4: 2393 rssi = -36 + 2 * (7 - vga_idx); 2394 break; 2395 case 3: 2396 rssi = -24 + 2 * (7 - vga_idx); 2397 break; 2398 case 2: 2399 rssi = -12 + 2 * (5 - vga_idx); 2400 break; 2401 case 1: 2402 rssi = 8 - (2 * vga_idx); 2403 break; 2404 case 0: 2405 rssi = 14 - (2 * vga_idx); 2406 break; 2407 } 2408 rssi += 6; 2409 } else { /* OFDM/HT. */ 2410 phy = (struct r92c_rx_phystat *)physt; 2411 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2412 } 2413 return rssi; 2414 } 2415 2416 static void 2417 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2418 { 2419 struct ieee80211com *ic = &sc->sc_ic; 2420 struct ifnet *ifp = ic->ic_ifp; 2421 struct ieee80211_frame *wh; 2422 struct ieee80211_node *ni; 2423 struct r92c_rx_desc_usb *stat; 2424 uint32_t rxdw0, rxdw3; 2425 struct mbuf *m; 2426 uint8_t rate; 2427 int8_t rssi = 0; 2428 int s, infosz; 2429 2430 URTWNHIST_FUNC(); 2431 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2432 2433 stat = (struct r92c_rx_desc_usb *)buf; 2434 rxdw0 = le32toh(stat->rxdw0); 2435 rxdw3 = le32toh(stat->rxdw3); 2436 2437 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2438 /* 2439 * This should not happen since we setup our Rx filter 2440 * to not receive these frames. 2441 */ 2442 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2443 if_statinc(ifp, if_ierrors); 2444 return; 2445 } 2446 /* 2447 * XXX: This will drop most control packets. Do we really 2448 * want this in IEEE80211_M_MONITOR mode? 2449 */ 2450 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2451 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2452 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2453 ic->ic_stats.is_rx_tooshort++; 2454 if_statinc(ifp, if_ierrors); 2455 return; 2456 } 2457 if (__predict_false(pktlen > MCLBYTES)) { 2458 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2459 if_statinc(ifp, if_ierrors); 2460 return; 2461 } 2462 2463 rate = MS(rxdw3, R92C_RXDW3_RATE); 2464 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2465 2466 /* Get RSSI from PHY status descriptor if present. */ 2467 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2468 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2469 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2470 else 2471 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2472 /* Update our average RSSI. */ 2473 urtwn_update_avgrssi(sc, rate, rssi); 2474 } 2475 2476 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2477 pktlen, rate, infosz, rssi); 2478 2479 MGETHDR(m, M_DONTWAIT, MT_DATA); 2480 if (__predict_false(m == NULL)) { 2481 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2482 ic->ic_stats.is_rx_nobuf++; 2483 if_statinc(ifp, if_ierrors); 2484 return; 2485 } 2486 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 2487 if (pktlen > (int)MHLEN) { 2488 MCLGET(m, M_DONTWAIT); 2489 if (__predict_false(!(m->m_flags & M_EXT))) { 2490 aprint_error_dev(sc->sc_dev, 2491 "couldn't allocate rx mbuf cluster\n"); 2492 m_freem(m); 2493 ic->ic_stats.is_rx_nobuf++; 2494 if_statinc(ifp, if_ierrors); 2495 return; 2496 } 2497 } 2498 2499 /* Finalize mbuf. */ 2500 m_set_rcvif(m, ifp); 2501 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2502 memcpy(mtod(m, uint8_t *), wh, pktlen); 2503 m->m_pkthdr.len = m->m_len = pktlen; 2504 2505 s = splnet(); 2506 if (__predict_false(sc->sc_drvbpf != NULL)) { 2507 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2508 2509 tap->wr_flags = 0; 2510 if (!(rxdw3 & R92C_RXDW3_HT)) { 2511 switch (rate) { 2512 /* CCK. */ 2513 case 0: tap->wr_rate = 2; break; 2514 case 1: tap->wr_rate = 4; break; 2515 case 2: tap->wr_rate = 11; break; 2516 case 3: tap->wr_rate = 22; break; 2517 /* OFDM. */ 2518 case 4: tap->wr_rate = 12; break; 2519 case 5: tap->wr_rate = 18; break; 2520 case 6: tap->wr_rate = 24; break; 2521 case 7: tap->wr_rate = 36; break; 2522 case 8: tap->wr_rate = 48; break; 2523 case 9: tap->wr_rate = 72; break; 2524 case 10: tap->wr_rate = 96; break; 2525 case 11: tap->wr_rate = 108; break; 2526 } 2527 } else if (rate >= 12) { /* MCS0~15. */ 2528 /* Bit 7 set means HT MCS instead of rate. */ 2529 tap->wr_rate = 0x80 | (rate - 12); 2530 } 2531 tap->wr_dbm_antsignal = rssi; 2532 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2533 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2534 2535 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2536 } 2537 2538 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2539 2540 /* push the frame up to the 802.11 stack */ 2541 ieee80211_input(ic, m, ni, rssi, 0); 2542 2543 /* Node is no longer needed. */ 2544 ieee80211_free_node(ni); 2545 2546 splx(s); 2547 } 2548 2549 static void 2550 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2551 { 2552 struct urtwn_rx_data *data = priv; 2553 struct urtwn_softc *sc = data->sc; 2554 struct r92c_rx_desc_usb *stat; 2555 size_t pidx = data->pidx; 2556 uint32_t rxdw0; 2557 uint8_t *buf; 2558 int len, totlen, pktlen, infosz, npkts, pktspacing; 2559 2560 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2561 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2562 2563 mutex_enter(&sc->sc_rx_mtx); 2564 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2565 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2566 /* Put this Rx buffer back to our free list. */ 2567 mutex_exit(&sc->sc_rx_mtx); 2568 2569 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2570 if (status == USBD_STALLED) 2571 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2572 else if (status != USBD_CANCELLED) 2573 goto resubmit; 2574 return; 2575 } 2576 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2577 2578 if (__predict_false(len < (int)sizeof(*stat))) { 2579 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2580 goto resubmit; 2581 } 2582 buf = data->buf; 2583 2584 /* Get the number of encapsulated frames. */ 2585 stat = (struct r92c_rx_desc_usb *)buf; 2586 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2587 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2588 else 2589 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2590 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2591 2592 if (npkts != 0) 2593 rnd_add_uint32(&sc->rnd_source, npkts); 2594 2595 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2596 pktspacing = 8; 2597 else 2598 pktspacing = 128; 2599 2600 /* Process all of them. */ 2601 while (npkts-- > 0 && len > 0) { 2602 if (__predict_false(len < (int)sizeof(*stat))) { 2603 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2604 len, 0, 0, 0); 2605 break; 2606 } 2607 stat = (struct r92c_rx_desc_usb *)buf; 2608 rxdw0 = le32toh(stat->rxdw0); 2609 2610 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2611 if (__predict_false(pktlen == 0)) { 2612 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2613 break; 2614 } 2615 2616 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2617 2618 /* Make sure everything fits in xfer. */ 2619 totlen = sizeof(*stat) + infosz + pktlen; 2620 if (__predict_false(totlen > len)) { 2621 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2622 (int)sizeof(*stat), infosz, pktlen, len); 2623 break; 2624 } 2625 2626 /* Process 802.11 frame. */ 2627 urtwn_rx_frame(sc, buf, pktlen); 2628 2629 totlen = roundup2(totlen, pktspacing); 2630 buf += totlen; 2631 len -= totlen; 2632 } 2633 2634 resubmit: 2635 /* Setup a new transfer. */ 2636 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2637 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2638 (void)usbd_transfer(xfer); 2639 } 2640 2641 static void 2642 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2643 { 2644 size_t pidx = data->pidx; 2645 2646 mutex_enter(&sc->sc_tx_mtx); 2647 /* Put this Tx buffer back to our free list. */ 2648 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2649 mutex_exit(&sc->sc_tx_mtx); 2650 } 2651 2652 static void 2653 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2654 { 2655 struct urtwn_tx_data *data = priv; 2656 struct urtwn_softc *sc = data->sc; 2657 struct ifnet *ifp = &sc->sc_if; 2658 size_t pidx = data->pidx; 2659 int s; 2660 2661 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2662 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2663 2664 urtwn_put_tx_data(sc, data); 2665 2666 s = splnet(); 2667 sc->tx_timer = 0; 2668 ifp->if_flags &= ~IFF_OACTIVE; 2669 2670 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2671 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2672 if (status == USBD_STALLED) { 2673 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2674 usbd_clear_endpoint_stall_async(pipe); 2675 } 2676 device_printf(sc->sc_dev, "transmit failed, %s\n", 2677 usbd_errstr(status)); 2678 if_statinc(ifp, if_oerrors); 2679 } 2680 splx(s); 2681 return; 2682 } 2683 2684 if_statinc(ifp, if_opackets); 2685 urtwn_start(ifp); 2686 splx(s); 2687 2688 } 2689 2690 static int 2691 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2692 struct urtwn_tx_data *data) 2693 { 2694 struct ieee80211com *ic = &sc->sc_ic; 2695 struct ieee80211_frame *wh; 2696 struct ieee80211_key *k = NULL; 2697 struct r92c_tx_desc_usb *txd; 2698 size_t i, padsize, xferlen, txd_len; 2699 uint16_t seq, sum; 2700 uint8_t raid, type, tid; 2701 int s, hasqos, error; 2702 2703 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2704 2705 wh = mtod(m, struct ieee80211_frame *); 2706 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2707 txd_len = sizeof(*txd); 2708 2709 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2710 txd_len = 32; 2711 2712 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2713 k = ieee80211_crypto_encap(ic, ni, m); 2714 if (k == NULL) { 2715 urtwn_put_tx_data(sc, data); 2716 m_free(m); 2717 return ENOBUFS; 2718 } 2719 2720 /* packet header may have moved, reset our local pointer */ 2721 wh = mtod(m, struct ieee80211_frame *); 2722 } 2723 2724 if (__predict_false(sc->sc_drvbpf != NULL)) { 2725 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2726 2727 tap->wt_flags = 0; 2728 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2729 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2730 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2731 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2732 2733 /* XXX: set tap->wt_rate? */ 2734 2735 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2736 } 2737 2738 /* non-qos data frames */ 2739 tid = R92C_TXDW1_QSEL_BE; 2740 if ((hasqos = ieee80211_has_qos(wh))) { 2741 /* data frames in 11n mode */ 2742 struct ieee80211_qosframe *qwh = (void *)wh; 2743 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2744 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2745 tid = R92C_TXDW1_QSEL_MGNT; 2746 } 2747 2748 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2749 padsize = 8; 2750 else 2751 padsize = 0; 2752 2753 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2754 padsize = 0; 2755 2756 /* Fill Tx descriptor. */ 2757 txd = (struct r92c_tx_desc_usb *)data->buf; 2758 memset(txd, 0, txd_len + padsize); 2759 2760 txd->txdw0 |= htole32( 2761 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2762 SM(R92C_TXDW0_OFFSET, txd_len)); 2763 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2764 txd->txdw0 |= htole32( 2765 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2766 } 2767 2768 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2769 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2770 2771 /* fix pad field */ 2772 if (padsize > 0) { 2773 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2774 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2775 } 2776 2777 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2778 type == IEEE80211_FC0_TYPE_DATA) { 2779 if (ic->ic_curmode == IEEE80211_MODE_11B) 2780 raid = R92C_RAID_11B; 2781 else 2782 raid = R92C_RAID_11BG; 2783 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2784 tid, raid, 0, 0); 2785 2786 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2787 txd->txdw1 |= htole32( 2788 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2789 SM(R92C_TXDW1_QSEL, tid) | 2790 SM(R92C_TXDW1_RAID, raid) | 2791 R92C_TXDW1_AGGBK); 2792 } else 2793 txd->txdw1 |= htole32( 2794 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2795 SM(R92C_TXDW1_QSEL, tid) | 2796 SM(R92C_TXDW1_RAID, raid) | 2797 R92C_TXDW1_AGGBK); 2798 2799 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2800 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2801 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2802 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2803 2804 if (hasqos) { 2805 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2806 } 2807 2808 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2809 /* for 11g */ 2810 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2811 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2812 R92C_TXDW4_HWRTSEN); 2813 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2814 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2815 R92C_TXDW4_HWRTSEN); 2816 } 2817 } 2818 /* Send RTS at OFDM24. */ 2819 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2820 txd->txdw5 |= htole32(0x0001ff00); 2821 /* Send data at OFDM54. */ 2822 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2823 txd->txdw5 |= htole32(0x13 & 0x3f); 2824 else 2825 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2826 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2827 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2828 txd->txdw1 |= htole32( 2829 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2830 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2831 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2832 2833 /* Force CCK1. */ 2834 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2835 /* Use 1Mbps */ 2836 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2837 } else { 2838 /* broadcast or multicast packets */ 2839 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2840 txd->txdw1 |= htole32( 2841 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2842 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2843 2844 /* Force CCK1. */ 2845 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2846 /* Use 1Mbps */ 2847 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2848 } 2849 /* Set sequence number */ 2850 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2851 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2852 txd->txdseq |= htole16(seq); 2853 2854 if (!hasqos) { 2855 /* Use HW sequence numbering for non-QoS frames. */ 2856 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2857 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2858 } 2859 } else { 2860 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2861 R92E_HWSEQ_SHIFT); 2862 if (!hasqos) { 2863 /* Use HW sequence numbering for non-QoS frames. */ 2864 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2865 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2866 } 2867 } 2868 2869 /* Compute Tx descriptor checksum. */ 2870 sum = 0; 2871 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2872 sum ^= ((uint16_t *)txd)[i]; 2873 txd->txdsum = sum; /* NB: already little endian. */ 2874 2875 xferlen = txd_len + m->m_pkthdr.len + padsize; 2876 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2877 2878 s = splnet(); 2879 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2880 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2881 urtwn_txeof); 2882 error = usbd_transfer(data->xfer); 2883 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2884 error != USBD_IN_PROGRESS)) { 2885 splx(s); 2886 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2887 return error; 2888 } 2889 splx(s); 2890 return 0; 2891 } 2892 2893 struct urtwn_tx_data * 2894 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2895 { 2896 struct urtwn_tx_data *data = NULL; 2897 2898 mutex_enter(&sc->sc_tx_mtx); 2899 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2900 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2901 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2902 } 2903 mutex_exit(&sc->sc_tx_mtx); 2904 2905 return data; 2906 } 2907 2908 static void 2909 urtwn_start(struct ifnet *ifp) 2910 { 2911 struct urtwn_softc *sc = ifp->if_softc; 2912 struct ieee80211com *ic = &sc->sc_ic; 2913 struct urtwn_tx_data *data; 2914 struct ether_header *eh; 2915 struct ieee80211_node *ni; 2916 struct mbuf *m; 2917 2918 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2919 2920 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2921 return; 2922 2923 data = NULL; 2924 for (;;) { 2925 /* Send pending management frames first. */ 2926 IF_POLL(&ic->ic_mgtq, m); 2927 if (m != NULL) { 2928 /* Use AC_VO for management frames. */ 2929 2930 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2931 2932 if (data == NULL) { 2933 ifp->if_flags |= IFF_OACTIVE; 2934 DPRINTFN(DBG_TX, "empty tx_free_list", 2935 0, 0, 0, 0); 2936 return; 2937 } 2938 IF_DEQUEUE(&ic->ic_mgtq, m); 2939 ni = M_GETCTX(m, struct ieee80211_node *); 2940 M_CLEARCTX(m); 2941 goto sendit; 2942 } 2943 if (ic->ic_state != IEEE80211_S_RUN) 2944 break; 2945 2946 /* Encapsulate and send data frames. */ 2947 IFQ_POLL(&ifp->if_snd, m); 2948 if (m == NULL) 2949 break; 2950 2951 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2952 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2953 uint8_t qid = WME_AC_BE; 2954 if (ieee80211_has_qos(wh)) { 2955 /* data frames in 11n mode */ 2956 struct ieee80211_qosframe *qwh = (void *)wh; 2957 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2958 qid = TID_TO_WME_AC(tid); 2959 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2960 qid = WME_AC_VO; 2961 } 2962 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2963 2964 if (data == NULL) { 2965 ifp->if_flags |= IFF_OACTIVE; 2966 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2967 return; 2968 } 2969 IFQ_DEQUEUE(&ifp->if_snd, m); 2970 2971 if (m->m_len < (int)sizeof(*eh) && 2972 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2973 device_printf(sc->sc_dev, "m_pullup failed\n"); 2974 if_statinc(ifp, if_oerrors); 2975 urtwn_put_tx_data(sc, data); 2976 m_freem(m); 2977 continue; 2978 } 2979 eh = mtod(m, struct ether_header *); 2980 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2981 if (ni == NULL) { 2982 device_printf(sc->sc_dev, 2983 "unable to find transmit node\n"); 2984 if_statinc(ifp, if_oerrors); 2985 urtwn_put_tx_data(sc, data); 2986 m_freem(m); 2987 continue; 2988 } 2989 2990 bpf_mtap(ifp, m, BPF_D_OUT); 2991 2992 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2993 ieee80211_free_node(ni); 2994 device_printf(sc->sc_dev, 2995 "unable to encapsulate packet\n"); 2996 if_statinc(ifp, if_oerrors); 2997 urtwn_put_tx_data(sc, data); 2998 m_freem(m); 2999 continue; 3000 } 3001 sendit: 3002 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 3003 3004 if (urtwn_tx(sc, m, ni, data) != 0) { 3005 m_freem(m); 3006 ieee80211_free_node(ni); 3007 device_printf(sc->sc_dev, 3008 "unable to transmit packet\n"); 3009 if_statinc(ifp, if_oerrors); 3010 urtwn_put_tx_data(sc, data); 3011 continue; 3012 } 3013 m_freem(m); 3014 ieee80211_free_node(ni); 3015 sc->tx_timer = 5; 3016 ifp->if_timer = 1; 3017 } 3018 } 3019 3020 static void 3021 urtwn_watchdog(struct ifnet *ifp) 3022 { 3023 struct urtwn_softc *sc = ifp->if_softc; 3024 3025 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3026 3027 ifp->if_timer = 0; 3028 3029 if (sc->tx_timer > 0) { 3030 if (--sc->tx_timer == 0) { 3031 device_printf(sc->sc_dev, "device timeout\n"); 3032 /* urtwn_init(ifp); XXX needs a process context! */ 3033 if_statinc(ifp, if_oerrors); 3034 return; 3035 } 3036 ifp->if_timer = 1; 3037 } 3038 ieee80211_watchdog(&sc->sc_ic); 3039 } 3040 3041 static int 3042 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3043 { 3044 struct urtwn_softc *sc = ifp->if_softc; 3045 struct ieee80211com *ic = &sc->sc_ic; 3046 int s, error = 0; 3047 3048 URTWNHIST_FUNC(); 3049 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3050 0, 0); 3051 3052 s = splnet(); 3053 3054 switch (cmd) { 3055 case SIOCSIFFLAGS: 3056 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3057 break; 3058 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3059 case IFF_UP | IFF_RUNNING: 3060 break; 3061 case IFF_UP: 3062 urtwn_init(ifp); 3063 break; 3064 case IFF_RUNNING: 3065 urtwn_stop(ifp, 1); 3066 break; 3067 case 0: 3068 break; 3069 } 3070 break; 3071 3072 case SIOCADDMULTI: 3073 case SIOCDELMULTI: 3074 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3075 /* setup multicast filter, etc */ 3076 error = 0; 3077 } 3078 break; 3079 3080 case SIOCS80211CHANNEL: 3081 /* 3082 * This allows for fast channel switching in monitor mode 3083 * (used by kismet). In IBSS mode, we must explicitly reset 3084 * the interface to generate a new beacon frame. 3085 */ 3086 error = ieee80211_ioctl(ic, cmd, data); 3087 if (error == ENETRESET && 3088 ic->ic_opmode == IEEE80211_M_MONITOR) { 3089 urtwn_set_chan(sc, ic->ic_curchan, 3090 IEEE80211_HTINFO_2NDCHAN_NONE); 3091 error = 0; 3092 } 3093 break; 3094 3095 default: 3096 error = ieee80211_ioctl(ic, cmd, data); 3097 break; 3098 } 3099 if (error == ENETRESET) { 3100 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3101 (IFF_UP | IFF_RUNNING) && 3102 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3103 urtwn_init(ifp); 3104 } 3105 error = 0; 3106 } 3107 3108 splx(s); 3109 3110 return error; 3111 } 3112 3113 static __inline int 3114 urtwn_power_on(struct urtwn_softc *sc) 3115 { 3116 3117 return sc->sc_power_on(sc); 3118 } 3119 3120 static int 3121 urtwn_r92c_power_on(struct urtwn_softc *sc) 3122 { 3123 uint32_t reg; 3124 int ntries; 3125 3126 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3127 3128 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3129 3130 /* Wait for autoload done bit. */ 3131 for (ntries = 0; ntries < 1000; ntries++) { 3132 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3133 break; 3134 DELAY(5); 3135 } 3136 if (ntries == 1000) { 3137 aprint_error_dev(sc->sc_dev, 3138 "timeout waiting for chip autoload\n"); 3139 return ETIMEDOUT; 3140 } 3141 3142 /* Unlock ISO/CLK/Power control register. */ 3143 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3144 DELAY(5); 3145 /* Move SPS into PWM mode. */ 3146 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3147 DELAY(5); 3148 3149 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3150 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3151 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3152 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3153 DELAY(100); 3154 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3155 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3156 ~R92C_SYS_ISO_CTRL_MD2PP); 3157 } 3158 3159 /* Auto enable WLAN. */ 3160 urtwn_write_2(sc, R92C_APS_FSMCO, 3161 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3162 for (ntries = 0; ntries < 1000; ntries++) { 3163 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3164 R92C_APS_FSMCO_APFM_ONMAC)) 3165 break; 3166 DELAY(100); 3167 } 3168 if (ntries == 1000) { 3169 aprint_error_dev(sc->sc_dev, 3170 "timeout waiting for MAC auto ON\n"); 3171 return ETIMEDOUT; 3172 } 3173 3174 /* Enable radio, GPIO and LED functions. */ 3175 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3176 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3177 urtwn_write_2(sc, R92C_APS_FSMCO, 3178 R92C_APS_FSMCO_AFSM_HSUS | 3179 R92C_APS_FSMCO_PDN_EN | 3180 R92C_APS_FSMCO_PFM_ALDN); 3181 3182 /* Release RF digital isolation. */ 3183 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3184 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3185 3186 /* Initialize MAC. */ 3187 urtwn_write_1(sc, R92C_APSD_CTRL, 3188 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3189 for (ntries = 0; ntries < 200; ntries++) { 3190 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3191 R92C_APSD_CTRL_OFF_STATUS)) 3192 break; 3193 DELAY(5); 3194 } 3195 if (ntries == 200) { 3196 aprint_error_dev(sc->sc_dev, 3197 "timeout waiting for MAC initialization\n"); 3198 return ETIMEDOUT; 3199 } 3200 3201 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3202 reg = urtwn_read_2(sc, R92C_CR); 3203 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3204 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3205 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3206 R92C_CR_ENSEC; 3207 urtwn_write_2(sc, R92C_CR, reg); 3208 3209 urtwn_write_1(sc, 0xfe10, 0x19); 3210 3211 urtwn_delay_ms(sc, 1); 3212 3213 return 0; 3214 } 3215 3216 static int 3217 urtwn_r92e_power_on(struct urtwn_softc *sc) 3218 { 3219 uint32_t reg; 3220 uint32_t val; 3221 int ntries; 3222 3223 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3224 3225 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3226 3227 /* Enable radio, GPIO and LED functions. */ 3228 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3229 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3230 urtwn_write_2(sc, R92C_APS_FSMCO, 3231 R92C_APS_FSMCO_AFSM_HSUS | 3232 R92C_APS_FSMCO_PDN_EN | 3233 R92C_APS_FSMCO_PFM_ALDN); 3234 3235 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3236 /* LDO. */ 3237 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3238 } 3239 else { 3240 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3241 R92C_SYS_SWR_CTRL2) & 0xffff); 3242 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3243 } 3244 3245 for (ntries = 0; ntries < 2; ntries++) { 3246 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3247 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3248 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3249 R92C_AFE_CTRL4)); 3250 } 3251 3252 /* Reset BB. */ 3253 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3254 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3255 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3256 3257 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3258 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3259 3260 /* Disable HWPDN. */ 3261 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3262 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3263 3264 /* Disable WL suspend. */ 3265 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3266 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3267 R92C_APS_FSMCO_AFSM_HSUS)); 3268 3269 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3270 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3271 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3272 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3273 for (ntries = 0; ntries < 10000; ntries++) { 3274 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3275 R92C_APS_FSMCO_APFM_ONMAC; 3276 if (val == 0x0) 3277 break; 3278 DELAY(10); 3279 } 3280 if (ntries == 10000) { 3281 aprint_error_dev(sc->sc_dev, 3282 "timeout waiting for chip power up\n"); 3283 return ETIMEDOUT; 3284 } 3285 3286 urtwn_write_2(sc, R92C_CR, 0x00); 3287 reg = urtwn_read_2(sc, R92C_CR); 3288 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3289 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3290 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3291 urtwn_write_2(sc, R92C_CR, reg); 3292 3293 return 0; 3294 } 3295 3296 static int 3297 urtwn_r88e_power_on(struct urtwn_softc *sc) 3298 { 3299 uint32_t reg; 3300 uint8_t val; 3301 int ntries; 3302 3303 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3304 3305 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3306 3307 /* Wait for power ready bit. */ 3308 for (ntries = 0; ntries < 5000; ntries++) { 3309 val = urtwn_read_1(sc, 0x6) & 0x2; 3310 if (val == 0x2) 3311 break; 3312 DELAY(10); 3313 } 3314 if (ntries == 5000) { 3315 aprint_error_dev(sc->sc_dev, 3316 "timeout waiting for chip power up\n"); 3317 return ETIMEDOUT; 3318 } 3319 3320 /* Reset BB. */ 3321 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3322 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3323 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3324 3325 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3326 3327 /* Disable HWPDN. */ 3328 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3329 3330 /* Disable WL suspend. */ 3331 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3332 3333 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3334 for (ntries = 0; ntries < 5000; ntries++) { 3335 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3336 break; 3337 DELAY(10); 3338 } 3339 if (ntries == 5000) 3340 return ETIMEDOUT; 3341 3342 /* Enable LDO normal mode. */ 3343 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3344 3345 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3346 urtwn_write_2(sc, R92C_CR, 0); 3347 reg = urtwn_read_2(sc, R92C_CR); 3348 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3349 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3350 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3351 urtwn_write_2(sc, R92C_CR, reg); 3352 3353 return 0; 3354 } 3355 3356 static int __noinline 3357 urtwn_llt_init(struct urtwn_softc *sc) 3358 { 3359 size_t i, page_count, pktbuf_count; 3360 uint32_t val; 3361 int error; 3362 3363 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3364 3365 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3366 3367 if (sc->chip & URTWN_CHIP_88E) 3368 page_count = R88E_TX_PAGE_COUNT; 3369 else if (sc->chip & URTWN_CHIP_92EU) 3370 page_count = R92E_TX_PAGE_COUNT; 3371 else 3372 page_count = R92C_TX_PAGE_COUNT; 3373 if (sc->chip & URTWN_CHIP_88E) 3374 pktbuf_count = R88E_TXPKTBUF_COUNT; 3375 else if (sc->chip & URTWN_CHIP_92EU) 3376 pktbuf_count = R92E_TXPKTBUF_COUNT; 3377 else 3378 pktbuf_count = R92C_TXPKTBUF_COUNT; 3379 3380 if (sc->chip & URTWN_CHIP_92EU) { 3381 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3382 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3383 DELAY(100); 3384 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3385 if (val & R92E_AUTO_LLT_EN) 3386 return EIO; 3387 return 0; 3388 } 3389 3390 /* Reserve pages [0; page_count]. */ 3391 for (i = 0; i < page_count; i++) { 3392 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3393 return error; 3394 } 3395 /* NB: 0xff indicates end-of-list. */ 3396 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3397 return error; 3398 /* 3399 * Use pages [page_count + 1; pktbuf_count - 1] 3400 * as ring buffer. 3401 */ 3402 for (++i; i < pktbuf_count - 1; i++) { 3403 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3404 return error; 3405 } 3406 /* Make the last page point to the beginning of the ring buffer. */ 3407 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3408 return error; 3409 } 3410 3411 static void 3412 urtwn_fw_reset(struct urtwn_softc *sc) 3413 { 3414 uint16_t reg; 3415 int ntries; 3416 3417 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3418 3419 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3420 3421 /* Tell 8051 to reset itself. */ 3422 mutex_enter(&sc->sc_fwcmd_mtx); 3423 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3424 sc->fwcur = 0; 3425 mutex_exit(&sc->sc_fwcmd_mtx); 3426 3427 /* Wait until 8051 resets by itself. */ 3428 for (ntries = 0; ntries < 100; ntries++) { 3429 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3430 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3431 return; 3432 DELAY(50); 3433 } 3434 /* Force 8051 reset. */ 3435 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3436 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3437 } 3438 3439 static void 3440 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3441 { 3442 uint16_t reg; 3443 3444 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3445 3446 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3447 3448 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3449 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3450 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3451 } 3452 DELAY(50); 3453 3454 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3455 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3456 DELAY(50); 3457 3458 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3459 DELAY(50); 3460 3461 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3462 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3463 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3464 } 3465 DELAY(50); 3466 3467 mutex_enter(&sc->sc_fwcmd_mtx); 3468 /* Init firmware commands ring. */ 3469 sc->fwcur = 0; 3470 mutex_exit(&sc->sc_fwcmd_mtx); 3471 3472 } 3473 3474 static int 3475 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3476 { 3477 uint32_t reg; 3478 int off, mlen, error = 0; 3479 3480 URTWNHIST_FUNC(); 3481 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3482 page, (uintptr_t)buf, len, 0); 3483 3484 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3485 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3486 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3487 3488 off = R92C_FW_START_ADDR; 3489 while (len > 0) { 3490 if (len > 196) 3491 mlen = 196; 3492 else if (len > 4) 3493 mlen = 4; 3494 else 3495 mlen = 1; 3496 error = urtwn_write_region(sc, off, buf, mlen); 3497 if (error != 0) 3498 break; 3499 off += mlen; 3500 buf += mlen; 3501 len -= mlen; 3502 } 3503 return error; 3504 } 3505 3506 static int __noinline 3507 urtwn_load_firmware(struct urtwn_softc *sc) 3508 { 3509 firmware_handle_t fwh; 3510 const struct r92c_fw_hdr *hdr; 3511 const char *name; 3512 u_char *fw, *ptr; 3513 size_t len; 3514 uint32_t reg; 3515 int mlen, ntries, page, error; 3516 3517 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3518 3519 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3520 3521 /* Read firmware image from the filesystem. */ 3522 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3523 name = "rtl8188eufw.bin"; 3524 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3525 name = "rtl8192eefw.bin"; 3526 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3527 URTWN_CHIP_UMC_A_CUT) 3528 name = "rtl8192cfwU.bin"; 3529 else 3530 name = "rtl8192cfw.bin"; 3531 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3532 aprint_error_dev(sc->sc_dev, 3533 "failed load firmware of file %s (error %d)\n", name, 3534 error); 3535 return error; 3536 } 3537 const size_t fwlen = len = firmware_get_size(fwh); 3538 fw = firmware_malloc(len); 3539 if (fw == NULL) { 3540 aprint_error_dev(sc->sc_dev, 3541 "failed to allocate firmware memory\n"); 3542 firmware_close(fwh); 3543 return ENOMEM; 3544 } 3545 error = firmware_read(fwh, 0, fw, len); 3546 firmware_close(fwh); 3547 if (error != 0) { 3548 aprint_error_dev(sc->sc_dev, 3549 "failed to read firmware (error %d)\n", error); 3550 firmware_free(fw, fwlen); 3551 return error; 3552 } 3553 3554 len = fwlen; 3555 ptr = fw; 3556 hdr = (const struct r92c_fw_hdr *)ptr; 3557 /* Check if there is a valid FW header and skip it. */ 3558 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3559 (le16toh(hdr->signature) >> 4) == 0x88e || 3560 (le16toh(hdr->signature) >> 4) == 0x92e || 3561 (le16toh(hdr->signature) >> 4) == 0x92c) { 3562 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3563 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3564 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3565 hdr->month, hdr->date, hdr->hour, hdr->minute); 3566 ptr += sizeof(*hdr); 3567 len -= sizeof(*hdr); 3568 } 3569 3570 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3571 /* Reset MCU ready status */ 3572 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3573 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3574 ISSET(sc->chip, URTWN_CHIP_92EU)) 3575 urtwn_r88e_fw_reset(sc); 3576 else 3577 urtwn_fw_reset(sc); 3578 } 3579 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3580 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3581 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3582 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3583 R92C_SYS_FUNC_EN_CPUEN); 3584 } 3585 3586 /* download enabled */ 3587 urtwn_write_1(sc, R92C_MCUFWDL, 3588 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3589 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3590 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3591 3592 /* Reset the FWDL checksum. */ 3593 urtwn_write_1(sc, R92C_MCUFWDL, 3594 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3595 3596 DELAY(50); 3597 /* download firmware */ 3598 for (page = 0; len > 0; page++) { 3599 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3600 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3601 if (error != 0) { 3602 aprint_error_dev(sc->sc_dev, 3603 "could not load firmware page %d\n", page); 3604 goto fail; 3605 } 3606 ptr += mlen; 3607 len -= mlen; 3608 } 3609 3610 /* download disable */ 3611 urtwn_write_1(sc, R92C_MCUFWDL, 3612 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3613 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3614 3615 /* Wait for checksum report. */ 3616 for (ntries = 0; ntries < 1000; ntries++) { 3617 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3618 break; 3619 DELAY(5); 3620 } 3621 if (ntries == 1000) { 3622 aprint_error_dev(sc->sc_dev, 3623 "timeout waiting for checksum report\n"); 3624 error = ETIMEDOUT; 3625 goto fail; 3626 } 3627 3628 /* Wait for firmware readiness. */ 3629 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3630 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3631 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3632 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3633 ISSET(sc->chip, URTWN_CHIP_92EU)) 3634 urtwn_r88e_fw_reset(sc); 3635 for (ntries = 0; ntries < 6000; ntries++) { 3636 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3637 break; 3638 DELAY(5); 3639 } 3640 if (ntries == 6000) { 3641 aprint_error_dev(sc->sc_dev, 3642 "timeout waiting for firmware readiness\n"); 3643 error = ETIMEDOUT; 3644 goto fail; 3645 } 3646 fail: 3647 firmware_free(fw, fwlen); 3648 return error; 3649 } 3650 3651 static __inline int 3652 urtwn_dma_init(struct urtwn_softc *sc) 3653 { 3654 3655 return sc->sc_dma_init(sc); 3656 } 3657 3658 static int 3659 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3660 { 3661 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3662 uint32_t reg; 3663 int error; 3664 3665 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3666 3667 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3668 3669 /* Initialize LLT table. */ 3670 error = urtwn_llt_init(sc); 3671 if (error != 0) 3672 return error; 3673 3674 /* Get Tx queues to USB endpoints mapping. */ 3675 hashq = hasnq = haslq = 0; 3676 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3677 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3678 if (MS(reg, R92C_USB_EP_HQ) != 0) 3679 hashq = 1; 3680 if (MS(reg, R92C_USB_EP_NQ) != 0) 3681 hasnq = 1; 3682 if (MS(reg, R92C_USB_EP_LQ) != 0) 3683 haslq = 1; 3684 nqueues = hashq + hasnq + haslq; 3685 if (nqueues == 0) 3686 return EIO; 3687 /* Get the number of pages for each queue. */ 3688 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3689 /* The remaining pages are assigned to the high priority queue. */ 3690 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3691 3692 /* Set number of pages for normal priority queue. */ 3693 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3694 urtwn_write_4(sc, R92C_RQPN, 3695 /* Set number of pages for public queue. */ 3696 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3697 /* Set number of pages for high priority queue. */ 3698 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3699 /* Set number of pages for low priority queue. */ 3700 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3701 /* Load values. */ 3702 R92C_RQPN_LD); 3703 3704 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3705 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3706 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3707 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3708 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3709 3710 /* Set queue to USB pipe mapping. */ 3711 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3712 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3713 if (nqueues == 1) { 3714 if (hashq) { 3715 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3716 } else if (hasnq) { 3717 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3718 } else { 3719 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3720 } 3721 } else if (nqueues == 2) { 3722 /* All 2-endpoints configs have a high priority queue. */ 3723 if (!hashq) { 3724 return EIO; 3725 } 3726 if (hasnq) { 3727 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3728 } else { 3729 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3730 } 3731 } else { 3732 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3733 } 3734 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3735 3736 /* Set Tx/Rx transfer page boundary. */ 3737 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3738 3739 /* Set Tx/Rx transfer page size. */ 3740 urtwn_write_1(sc, R92C_PBP, 3741 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3742 return 0; 3743 } 3744 3745 static int 3746 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3747 { 3748 usb_interface_descriptor_t *id; 3749 uint32_t reg; 3750 int nqueues; 3751 int error; 3752 3753 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3754 3755 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3756 3757 /* Initialize LLT table. */ 3758 error = urtwn_llt_init(sc); 3759 if (error != 0) 3760 return error; 3761 3762 /* Get Tx queues to USB endpoints mapping. */ 3763 id = usbd_get_interface_descriptor(sc->sc_iface); 3764 nqueues = id->bNumEndpoints - 1; 3765 if (nqueues == 0) 3766 return EIO; 3767 3768 /* Set number of pages for normal priority queue. */ 3769 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3770 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3771 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3772 3773 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3774 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3775 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3776 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3777 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3778 3779 /* Set queue to USB pipe mapping. */ 3780 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3781 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3782 if (nqueues == 1) 3783 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3784 else if (nqueues == 2) 3785 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3786 else 3787 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3788 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3789 3790 /* Set Tx/Rx transfer page boundary. */ 3791 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3792 3793 /* Set Tx/Rx transfer page size. */ 3794 urtwn_write_1(sc, R92C_PBP, 3795 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3796 3797 return 0; 3798 } 3799 3800 static void __noinline 3801 urtwn_mac_init(struct urtwn_softc *sc) 3802 { 3803 size_t i; 3804 3805 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3806 3807 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3808 3809 /* Write MAC initialization values. */ 3810 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3811 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3812 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3813 rtl8188eu_mac[i].val); 3814 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3815 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3816 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3817 rtl8192eu_mac[i].val); 3818 } else { 3819 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3820 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3821 rtl8192cu_mac[i].val); 3822 } 3823 } 3824 3825 static void __noinline 3826 urtwn_bb_init(struct urtwn_softc *sc) 3827 { 3828 const struct rtwn_bb_prog *prog; 3829 uint32_t reg; 3830 uint8_t crystalcap; 3831 size_t i; 3832 3833 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3834 3835 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3836 3837 /* Enable BB and RF. */ 3838 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3839 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3840 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3841 R92C_SYS_FUNC_EN_DIO_RF); 3842 3843 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3844 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3845 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3846 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3847 } 3848 3849 urtwn_write_1(sc, R92C_RF_CTRL, 3850 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3851 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3852 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3853 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3854 3855 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3856 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3857 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3858 urtwn_write_1(sc, 0x15, 0xe9); 3859 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3860 } 3861 3862 /* Select BB programming based on board type. */ 3863 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3864 prog = &rtl8188eu_bb_prog; 3865 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3866 prog = &rtl8192eu_bb_prog; 3867 else if (!(sc->chip & URTWN_CHIP_92C)) { 3868 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3869 prog = &rtl8188ce_bb_prog; 3870 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3871 prog = &rtl8188ru_bb_prog; 3872 } else { 3873 prog = &rtl8188cu_bb_prog; 3874 } 3875 } else { 3876 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3877 prog = &rtl8192ce_bb_prog; 3878 } else { 3879 prog = &rtl8192cu_bb_prog; 3880 } 3881 } 3882 /* Write BB initialization values. */ 3883 for (i = 0; i < prog->count; i++) { 3884 /* additional delay depend on registers */ 3885 switch (prog->regs[i]) { 3886 case 0xfe: 3887 urtwn_delay_ms(sc, 50); 3888 break; 3889 case 0xfd: 3890 urtwn_delay_ms(sc, 5); 3891 break; 3892 case 0xfc: 3893 urtwn_delay_ms(sc, 1); 3894 break; 3895 case 0xfb: 3896 DELAY(50); 3897 break; 3898 case 0xfa: 3899 DELAY(5); 3900 break; 3901 case 0xf9: 3902 DELAY(1); 3903 break; 3904 } 3905 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3906 DELAY(1); 3907 } 3908 3909 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3910 /* 8192C 1T only configuration. */ 3911 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3912 reg = (reg & ~0x00000003) | 0x2; 3913 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3914 3915 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3916 reg = (reg & ~0x00300033) | 0x00200022; 3917 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3918 3919 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3920 reg = (reg & ~0xff000000) | (0x45 << 24); 3921 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3922 3923 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3924 reg = (reg & ~0x000000ff) | 0x23; 3925 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3926 3927 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3928 reg = (reg & ~0x00000030) | (1 << 4); 3929 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3930 3931 reg = urtwn_bb_read(sc, 0xe74); 3932 reg = (reg & ~0x0c000000) | (2 << 26); 3933 urtwn_bb_write(sc, 0xe74, reg); 3934 reg = urtwn_bb_read(sc, 0xe78); 3935 reg = (reg & ~0x0c000000) | (2 << 26); 3936 urtwn_bb_write(sc, 0xe78, reg); 3937 reg = urtwn_bb_read(sc, 0xe7c); 3938 reg = (reg & ~0x0c000000) | (2 << 26); 3939 urtwn_bb_write(sc, 0xe7c, reg); 3940 reg = urtwn_bb_read(sc, 0xe80); 3941 reg = (reg & ~0x0c000000) | (2 << 26); 3942 urtwn_bb_write(sc, 0xe80, reg); 3943 reg = urtwn_bb_read(sc, 0xe88); 3944 reg = (reg & ~0x0c000000) | (2 << 26); 3945 urtwn_bb_write(sc, 0xe88, reg); 3946 } 3947 3948 /* Write AGC values. */ 3949 for (i = 0; i < prog->agccount; i++) { 3950 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3951 DELAY(1); 3952 } 3953 3954 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3955 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3956 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3957 DELAY(1); 3958 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3959 DELAY(1); 3960 } 3961 3962 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3963 crystalcap = sc->r88e_rom[0xb9]; 3964 if (crystalcap == 0x00) 3965 crystalcap = 0x20; 3966 crystalcap &= 0x3f; 3967 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3968 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3969 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3970 crystalcap | crystalcap << 6)); 3971 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3972 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3973 crystalcap = sc->r88e_rom[0xb9]; 3974 if (crystalcap == 0xff) 3975 crystalcap = 0x20; 3976 crystalcap &= 0x3f; 3977 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3978 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3979 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3980 crystalcap | crystalcap << 6)); 3981 } else { 3982 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3983 R92C_HSSI_PARAM2_CCK_HIPWR) { 3984 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3985 } 3986 } 3987 } 3988 3989 static void __noinline 3990 urtwn_rf_init(struct urtwn_softc *sc) 3991 { 3992 const struct rtwn_rf_prog *prog; 3993 uint32_t reg, mask, saved; 3994 size_t i, j, idx; 3995 3996 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3997 3998 /* Select RF programming based on board type. */ 3999 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4000 prog = rtl8188eu_rf_prog; 4001 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4002 prog = rtl8192eu_rf_prog; 4003 else if (!(sc->chip & URTWN_CHIP_92C)) { 4004 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4005 prog = rtl8188ce_rf_prog; 4006 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4007 prog = rtl8188ru_rf_prog; 4008 } else { 4009 prog = rtl8188cu_rf_prog; 4010 } 4011 } else { 4012 prog = rtl8192ce_rf_prog; 4013 } 4014 4015 for (i = 0; i < sc->nrxchains; i++) { 4016 /* Save RF_ENV control type. */ 4017 idx = i / 2; 4018 mask = 0xffffU << ((i % 2) * 16); 4019 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4020 4021 /* Set RF_ENV enable. */ 4022 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4023 reg |= 0x100000; 4024 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4025 DELAY(50); 4026 4027 /* Set RF_ENV output high. */ 4028 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4029 reg |= 0x10; 4030 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4031 DELAY(50); 4032 4033 /* Set address and data lengths of RF registers. */ 4034 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4035 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4036 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4037 DELAY(50); 4038 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4039 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4040 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4041 DELAY(50); 4042 4043 /* Write RF initialization values for this chain. */ 4044 for (j = 0; j < prog[i].count; j++) { 4045 if (prog[i].regs[j] >= 0xf9 && 4046 prog[i].regs[j] <= 0xfe) { 4047 /* 4048 * These are fake RF registers offsets that 4049 * indicate a delay is required. 4050 */ 4051 urtwn_delay_ms(sc, 50); 4052 continue; 4053 } 4054 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4055 DELAY(5); 4056 } 4057 4058 /* Restore RF_ENV control type. */ 4059 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4060 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4061 } 4062 4063 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4064 URTWN_CHIP_UMC_A_CUT) { 4065 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4066 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4067 } 4068 4069 /* Cache RF register CHNLBW. */ 4070 for (i = 0; i < 2; i++) { 4071 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4072 } 4073 } 4074 4075 static void __noinline 4076 urtwn_cam_init(struct urtwn_softc *sc) 4077 { 4078 uint32_t content, command; 4079 uint8_t idx; 4080 size_t i; 4081 4082 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4083 4084 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4085 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4086 return; 4087 4088 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4089 content = (idx & 3) 4090 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4091 | R92C_CAM_VALID; 4092 4093 command = R92C_CAMCMD_POLLING 4094 | R92C_CAMCMD_WRITE 4095 | R92C_CAM_CTL0(idx); 4096 4097 urtwn_write_4(sc, R92C_CAMWRITE, content); 4098 urtwn_write_4(sc, R92C_CAMCMD, command); 4099 } 4100 4101 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4102 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4103 if (i == 0) { 4104 content = (idx & 3) 4105 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4106 | R92C_CAM_VALID; 4107 } else { 4108 content = 0; 4109 } 4110 4111 command = R92C_CAMCMD_POLLING 4112 | R92C_CAMCMD_WRITE 4113 | R92C_CAM_CTL0(idx) 4114 | i; 4115 4116 urtwn_write_4(sc, R92C_CAMWRITE, content); 4117 urtwn_write_4(sc, R92C_CAMCMD, command); 4118 } 4119 } 4120 4121 /* Invalidate all CAM entries. */ 4122 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4123 } 4124 4125 static void __noinline 4126 urtwn_pa_bias_init(struct urtwn_softc *sc) 4127 { 4128 uint8_t reg; 4129 size_t i; 4130 4131 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4132 4133 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4134 4135 for (i = 0; i < sc->nrxchains; i++) { 4136 if (sc->pa_setting & (1U << i)) 4137 continue; 4138 4139 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4140 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4141 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4142 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4143 } 4144 if (!(sc->pa_setting & 0x10)) { 4145 reg = urtwn_read_1(sc, 0x16); 4146 reg = (reg & ~0xf0) | 0x90; 4147 urtwn_write_1(sc, 0x16, reg); 4148 } 4149 } 4150 4151 static void __noinline 4152 urtwn_rxfilter_init(struct urtwn_softc *sc) 4153 { 4154 4155 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4156 4157 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4158 4159 /* Initialize Rx filter. */ 4160 /* TODO: use better filter for monitor mode. */ 4161 urtwn_write_4(sc, R92C_RCR, 4162 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4163 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4164 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4165 /* Accept all multicast frames. */ 4166 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4167 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4168 /* Accept all management frames. */ 4169 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4170 /* Reject all control frames. */ 4171 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4172 /* Accept all data frames. */ 4173 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4174 } 4175 4176 static void __noinline 4177 urtwn_edca_init(struct urtwn_softc *sc) 4178 { 4179 4180 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4181 4182 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4183 4184 /* set spec SIFS (used in NAV) */ 4185 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4186 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4187 4188 /* set SIFS CCK/OFDM */ 4189 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4190 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4191 4192 /* TXOP */ 4193 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4194 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4195 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4196 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4197 } 4198 4199 static void 4200 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4201 uint16_t power[URTWN_RIDX_COUNT]) 4202 { 4203 uint32_t reg; 4204 4205 URTWNHIST_FUNC(); 4206 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4207 4208 /* Write per-CCK rate Tx power. */ 4209 if (chain == 0) { 4210 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4211 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4212 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4213 4214 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4215 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4216 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4217 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4218 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4219 } else { 4220 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4221 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4222 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4223 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4224 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4225 4226 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4227 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4228 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4229 } 4230 /* Write per-OFDM rate Tx power. */ 4231 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4232 SM(R92C_TXAGC_RATE06, power[ 4]) | 4233 SM(R92C_TXAGC_RATE09, power[ 5]) | 4234 SM(R92C_TXAGC_RATE12, power[ 6]) | 4235 SM(R92C_TXAGC_RATE18, power[ 7])); 4236 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4237 SM(R92C_TXAGC_RATE24, power[ 8]) | 4238 SM(R92C_TXAGC_RATE36, power[ 9]) | 4239 SM(R92C_TXAGC_RATE48, power[10]) | 4240 SM(R92C_TXAGC_RATE54, power[11])); 4241 /* Write per-MCS Tx power. */ 4242 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4243 SM(R92C_TXAGC_MCS00, power[12]) | 4244 SM(R92C_TXAGC_MCS01, power[13]) | 4245 SM(R92C_TXAGC_MCS02, power[14]) | 4246 SM(R92C_TXAGC_MCS03, power[15])); 4247 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4248 SM(R92C_TXAGC_MCS04, power[16]) | 4249 SM(R92C_TXAGC_MCS05, power[17]) | 4250 SM(R92C_TXAGC_MCS06, power[18]) | 4251 SM(R92C_TXAGC_MCS07, power[19])); 4252 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4253 SM(R92C_TXAGC_MCS08, power[20]) | 4254 SM(R92C_TXAGC_MCS09, power[21]) | 4255 SM(R92C_TXAGC_MCS10, power[22]) | 4256 SM(R92C_TXAGC_MCS11, power[23])); 4257 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4258 SM(R92C_TXAGC_MCS12, power[24]) | 4259 SM(R92C_TXAGC_MCS13, power[25]) | 4260 SM(R92C_TXAGC_MCS14, power[26]) | 4261 SM(R92C_TXAGC_MCS15, power[27])); 4262 } 4263 4264 static void 4265 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4266 uint16_t power[URTWN_RIDX_COUNT]) 4267 { 4268 struct r92c_rom *rom = &sc->rom; 4269 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4270 const struct rtwn_txpwr *base; 4271 int ridx, group; 4272 4273 URTWNHIST_FUNC(); 4274 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4275 4276 /* Determine channel group. */ 4277 if (chan <= 3) { 4278 group = 0; 4279 } else if (chan <= 9) { 4280 group = 1; 4281 } else { 4282 group = 2; 4283 } 4284 4285 /* Get original Tx power based on board type and RF chain. */ 4286 if (!(sc->chip & URTWN_CHIP_92C)) { 4287 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4288 base = &rtl8188ru_txagc[chain]; 4289 } else { 4290 base = &rtl8192cu_txagc[chain]; 4291 } 4292 } else { 4293 base = &rtl8192cu_txagc[chain]; 4294 } 4295 4296 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4297 if (sc->regulatory == 0) { 4298 for (ridx = 0; ridx <= 3; ridx++) { 4299 power[ridx] = base->pwr[0][ridx]; 4300 } 4301 } 4302 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4303 if (sc->regulatory == 3) { 4304 power[ridx] = base->pwr[0][ridx]; 4305 /* Apply vendor limits. */ 4306 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4307 maxpow = rom->ht40_max_pwr[group]; 4308 } else { 4309 maxpow = rom->ht20_max_pwr[group]; 4310 } 4311 maxpow = (maxpow >> (chain * 4)) & 0xf; 4312 if (power[ridx] > maxpow) { 4313 power[ridx] = maxpow; 4314 } 4315 } else if (sc->regulatory == 1) { 4316 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4317 power[ridx] = base->pwr[group][ridx]; 4318 } 4319 } else if (sc->regulatory != 2) { 4320 power[ridx] = base->pwr[0][ridx]; 4321 } 4322 } 4323 4324 /* Compute per-CCK rate Tx power. */ 4325 cckpow = rom->cck_tx_pwr[chain][group]; 4326 for (ridx = 0; ridx <= 3; ridx++) { 4327 power[ridx] += cckpow; 4328 if (power[ridx] > R92C_MAX_TX_PWR) { 4329 power[ridx] = R92C_MAX_TX_PWR; 4330 } 4331 } 4332 4333 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4334 if (sc->ntxchains > 1) { 4335 /* Apply reduction for 2 spatial streams. */ 4336 diff = rom->ht40_2s_tx_pwr_diff[group]; 4337 diff = (diff >> (chain * 4)) & 0xf; 4338 htpow = (htpow > diff) ? htpow - diff : 0; 4339 } 4340 4341 /* Compute per-OFDM rate Tx power. */ 4342 diff = rom->ofdm_tx_pwr_diff[group]; 4343 diff = (diff >> (chain * 4)) & 0xf; 4344 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4345 for (ridx = 4; ridx <= 11; ridx++) { 4346 power[ridx] += ofdmpow; 4347 if (power[ridx] > R92C_MAX_TX_PWR) { 4348 power[ridx] = R92C_MAX_TX_PWR; 4349 } 4350 } 4351 4352 /* Compute per-MCS Tx power. */ 4353 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4354 diff = rom->ht20_tx_pwr_diff[group]; 4355 diff = (diff >> (chain * 4)) & 0xf; 4356 htpow += diff; /* HT40->HT20 correction. */ 4357 } 4358 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4359 power[ridx] += htpow; 4360 if (power[ridx] > R92C_MAX_TX_PWR) { 4361 power[ridx] = R92C_MAX_TX_PWR; 4362 } 4363 } 4364 #ifdef URTWN_DEBUG 4365 if (urtwn_debug & DBG_RF) { 4366 /* Dump per-rate Tx power values. */ 4367 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4368 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4369 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4370 } 4371 #endif 4372 } 4373 4374 void 4375 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4376 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4377 { 4378 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4379 const struct rtwn_r88e_txpwr *base; 4380 int ridx, group; 4381 4382 URTWNHIST_FUNC(); 4383 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4384 4385 /* Determine channel group. */ 4386 if (chan <= 2) 4387 group = 0; 4388 else if (chan <= 5) 4389 group = 1; 4390 else if (chan <= 8) 4391 group = 2; 4392 else if (chan <= 11) 4393 group = 3; 4394 else if (chan <= 13) 4395 group = 4; 4396 else 4397 group = 5; 4398 4399 /* Get original Tx power based on board type and RF chain. */ 4400 base = &rtl8188eu_txagc[chain]; 4401 4402 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4403 if (sc->regulatory == 0) { 4404 for (ridx = 0; ridx <= 3; ridx++) 4405 power[ridx] = base->pwr[0][ridx]; 4406 } 4407 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4408 if (sc->regulatory == 3) 4409 power[ridx] = base->pwr[0][ridx]; 4410 else if (sc->regulatory == 1) { 4411 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4412 power[ridx] = base->pwr[group][ridx]; 4413 } else if (sc->regulatory != 2) 4414 power[ridx] = base->pwr[0][ridx]; 4415 } 4416 4417 /* Compute per-CCK rate Tx power. */ 4418 cckpow = sc->cck_tx_pwr[group]; 4419 for (ridx = 0; ridx <= 3; ridx++) { 4420 power[ridx] += cckpow; 4421 if (power[ridx] > R92C_MAX_TX_PWR) 4422 power[ridx] = R92C_MAX_TX_PWR; 4423 } 4424 4425 htpow = sc->ht40_tx_pwr[group]; 4426 4427 /* Compute per-OFDM rate Tx power. */ 4428 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4429 for (ridx = 4; ridx <= 11; ridx++) { 4430 power[ridx] += ofdmpow; 4431 if (power[ridx] > R92C_MAX_TX_PWR) 4432 power[ridx] = R92C_MAX_TX_PWR; 4433 } 4434 4435 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4436 for (ridx = 12; ridx <= 27; ridx++) { 4437 power[ridx] += bw20pow; 4438 if (power[ridx] > R92C_MAX_TX_PWR) 4439 power[ridx] = R92C_MAX_TX_PWR; 4440 } 4441 } 4442 4443 static void 4444 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4445 { 4446 uint16_t power[URTWN_RIDX_COUNT]; 4447 size_t i; 4448 4449 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4450 4451 for (i = 0; i < sc->ntxchains; i++) { 4452 /* Compute per-rate Tx power values. */ 4453 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4454 ISSET(sc->chip, URTWN_CHIP_92EU)) 4455 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4456 else 4457 urtwn_get_txpower(sc, i, chan, ht40m, power); 4458 /* Write per-rate Tx power values to hardware. */ 4459 urtwn_write_txpower(sc, i, power); 4460 } 4461 } 4462 4463 static void __noinline 4464 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4465 { 4466 struct ieee80211com *ic = &sc->sc_ic; 4467 u_int chan; 4468 size_t i; 4469 4470 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4471 4472 URTWNHIST_FUNC(); 4473 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4474 4475 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4476 4477 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4478 chan += 2; 4479 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4480 chan -= 2; 4481 } 4482 4483 /* Set Tx power for this new channel. */ 4484 urtwn_set_txpower(sc, chan, ht40m); 4485 4486 for (i = 0; i < sc->nrxchains; i++) { 4487 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4488 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4489 } 4490 4491 if (ht40m) { 4492 /* Is secondary channel below or above primary? */ 4493 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4494 uint32_t reg; 4495 4496 urtwn_write_1(sc, R92C_BWOPMODE, 4497 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4498 4499 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4500 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4501 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4502 4503 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4504 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4505 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4506 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4507 4508 /* Set CCK side band. */ 4509 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4510 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4511 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4512 4513 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4514 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4515 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4516 4517 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4518 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4519 ~R92C_FPGA0_ANAPARAM2_CBW20); 4520 4521 reg = urtwn_bb_read(sc, 0x818); 4522 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4523 urtwn_bb_write(sc, 0x818, reg); 4524 4525 /* Select 40MHz bandwidth. */ 4526 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4527 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4528 } else { 4529 urtwn_write_1(sc, R92C_BWOPMODE, 4530 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4531 4532 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4533 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4534 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4535 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4536 4537 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4538 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4539 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4540 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4541 R92C_FPGA0_ANAPARAM2_CBW20); 4542 } 4543 4544 /* Select 20MHz bandwidth. */ 4545 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4546 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4547 (ISSET(sc->chip, URTWN_CHIP_88E) || 4548 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4549 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4550 } 4551 } 4552 4553 static void __noinline 4554 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4555 { 4556 4557 URTWNHIST_FUNC(); 4558 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4559 4560 uint32_t addaBackup[16], iqkBackup[4], piMode; 4561 4562 #ifdef notyet 4563 uint32_t odfm0_agccore_regs[3]; 4564 uint32_t ant_regs[3]; 4565 uint32_t rf_regs[8]; 4566 #endif 4567 uint32_t reg0, reg1, reg2; 4568 int i, attempt; 4569 4570 #ifdef notyet 4571 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4572 R92E_STBC_SETTING + 2)); 4573 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4574 /* Save AGCCORE regs. */ 4575 for (i = 0; i < sc->nrxchains; i++) { 4576 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4577 R92C_OFDM0_AGCCORE1(i)); 4578 } 4579 #endif 4580 /* Save BB regs. */ 4581 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4582 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4583 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4584 4585 /* Save adda regs to be restored when finished. */ 4586 for (i = 0; i < __arraycount(addaReg); i++) 4587 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4588 /* Save mac regs. */ 4589 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4590 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4591 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4592 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4593 4594 #ifdef notyet 4595 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4596 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4597 4598 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4599 for (i = 0; i < sc->nrxchains; i++) 4600 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4601 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4602 #endif 4603 4604 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4605 R92C_HSSI_PARAM1_PI); 4606 if (piMode == 0) { 4607 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4608 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4609 R92C_HSSI_PARAM1_PI); 4610 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4611 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4612 R92C_HSSI_PARAM1_PI); 4613 } 4614 4615 attempt = 1; 4616 4617 next_attempt: 4618 4619 /* Set mac regs for calibration. */ 4620 for (i = 0; i < __arraycount(addaReg); i++) { 4621 urtwn_bb_write(sc, addaReg[i], 4622 addaReg[__arraycount(addaReg) - 1]); 4623 } 4624 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4625 R92C_CCK0_AFESETTING)); 4626 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4627 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4628 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4629 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4630 4631 if (sc->ntxchains > 1) 4632 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4633 4634 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4635 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4636 ~R92C_BCN_CTRL_EN_BCN)); 4637 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4638 ~R92C_BCN_CTRL_EN_BCN)); 4639 4640 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4641 ~R92C_GPIO_MUXCFG_ENBT)); 4642 4643 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4644 4645 if (sc->ntxchains > 1) 4646 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4647 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4648 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4649 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4650 4651 /* Restore BB regs. */ 4652 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4653 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4654 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4655 4656 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4657 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4658 if (sc->nrxchains > 1) 4659 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4660 4661 if (attempt-- > 0) 4662 goto next_attempt; 4663 4664 /* Restore mode. */ 4665 if (piMode == 0) { 4666 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4667 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4668 ~R92C_HSSI_PARAM1_PI); 4669 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4670 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4671 ~R92C_HSSI_PARAM1_PI); 4672 } 4673 4674 #ifdef notyet 4675 for (i = 0; i < sc->nrxchains; i++) { 4676 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4677 odfm0_agccore_regs[i]); 4678 } 4679 #endif 4680 4681 /* Restore adda regs. */ 4682 for (i = 0; i < __arraycount(addaReg); i++) 4683 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4684 /* Restore mac regs. */ 4685 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4686 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4687 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4688 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4689 4690 #ifdef notyet 4691 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4692 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4693 4694 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4695 for (i = 0; i < sc->nrxchains; i++) 4696 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4697 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4698 #endif 4699 } 4700 4701 static void 4702 urtwn_lc_calib(struct urtwn_softc *sc) 4703 { 4704 uint32_t rf_ac[2]; 4705 uint8_t txmode; 4706 size_t i; 4707 4708 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4709 4710 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4711 4712 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4713 if ((txmode & 0x70) != 0) { 4714 /* Disable all continuous Tx. */ 4715 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4716 4717 /* Set RF mode to standby mode. */ 4718 for (i = 0; i < sc->nrxchains; i++) { 4719 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4720 urtwn_rf_write(sc, i, R92C_RF_AC, 4721 RW(rf_ac[i], R92C_RF_AC_MODE, 4722 R92C_RF_AC_MODE_STANDBY)); 4723 } 4724 } else { 4725 /* Block all Tx queues. */ 4726 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4727 } 4728 /* Start calibration. */ 4729 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4730 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4731 4732 /* Give calibration the time to complete. */ 4733 urtwn_delay_ms(sc, 100); 4734 4735 /* Restore configuration. */ 4736 if ((txmode & 0x70) != 0) { 4737 /* Restore Tx mode. */ 4738 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4739 /* Restore RF mode. */ 4740 for (i = 0; i < sc->nrxchains; i++) { 4741 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4742 } 4743 } else { 4744 /* Unblock all Tx queues. */ 4745 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4746 } 4747 } 4748 4749 static void 4750 urtwn_temp_calib(struct urtwn_softc *sc) 4751 { 4752 int temp, t_meter_reg; 4753 4754 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4755 4756 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4757 4758 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4759 t_meter_reg = R92C_RF_T_METER; 4760 else 4761 t_meter_reg = R92E_RF_T_METER; 4762 4763 if (sc->thcal_state == 0) { 4764 /* Start measuring temperature. */ 4765 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4766 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4767 sc->thcal_state = 1; 4768 return; 4769 } 4770 sc->thcal_state = 0; 4771 4772 /* Read measured temperature. */ 4773 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4774 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4775 if (temp == 0) /* Read failed, skip. */ 4776 return; 4777 4778 /* 4779 * Redo LC calibration if temperature changed significantly since 4780 * last calibration. 4781 */ 4782 if (sc->thcal_lctemp == 0) { 4783 /* First LC calibration is performed in urtwn_init(). */ 4784 sc->thcal_lctemp = temp; 4785 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4786 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4787 sc->thcal_lctemp, temp, 0, 0); 4788 urtwn_lc_calib(sc); 4789 /* Record temperature of last LC calibration. */ 4790 sc->thcal_lctemp = temp; 4791 } 4792 } 4793 4794 static int 4795 urtwn_init(struct ifnet *ifp) 4796 { 4797 struct urtwn_softc *sc = ifp->if_softc; 4798 struct ieee80211com *ic = &sc->sc_ic; 4799 struct urtwn_rx_data *data; 4800 uint32_t reg; 4801 size_t i; 4802 int error; 4803 4804 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4805 4806 urtwn_stop(ifp, 0); 4807 4808 mutex_enter(&sc->sc_write_mtx); 4809 4810 mutex_enter(&sc->sc_task_mtx); 4811 /* Init host async commands ring. */ 4812 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4813 mutex_exit(&sc->sc_task_mtx); 4814 4815 mutex_enter(&sc->sc_fwcmd_mtx); 4816 /* Init firmware commands ring. */ 4817 sc->fwcur = 0; 4818 mutex_exit(&sc->sc_fwcmd_mtx); 4819 4820 /* Allocate Tx/Rx buffers. */ 4821 error = urtwn_alloc_rx_list(sc); 4822 if (error != 0) { 4823 aprint_error_dev(sc->sc_dev, 4824 "could not allocate Rx buffers\n"); 4825 goto fail; 4826 } 4827 error = urtwn_alloc_tx_list(sc); 4828 if (error != 0) { 4829 aprint_error_dev(sc->sc_dev, 4830 "could not allocate Tx buffers\n"); 4831 goto fail; 4832 } 4833 4834 /* Power on adapter. */ 4835 error = urtwn_power_on(sc); 4836 if (error != 0) 4837 goto fail; 4838 4839 /* Initialize DMA. */ 4840 error = urtwn_dma_init(sc); 4841 if (error != 0) 4842 goto fail; 4843 4844 /* Set info size in Rx descriptors (in 64-bit words). */ 4845 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4846 4847 /* Init interrupts. */ 4848 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4849 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4850 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4851 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4852 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4853 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4854 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4855 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4856 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4857 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4858 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4859 } 4860 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4861 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4862 } else { 4863 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4864 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4865 } 4866 4867 /* Set MAC address. */ 4868 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4869 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4870 4871 /* Set initial network type. */ 4872 reg = urtwn_read_4(sc, R92C_CR); 4873 switch (ic->ic_opmode) { 4874 case IEEE80211_M_STA: 4875 default: 4876 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4877 break; 4878 4879 case IEEE80211_M_IBSS: 4880 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4881 break; 4882 } 4883 urtwn_write_4(sc, R92C_CR, reg); 4884 4885 /* Set response rate */ 4886 reg = urtwn_read_4(sc, R92C_RRSR); 4887 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4888 urtwn_write_4(sc, R92C_RRSR, reg); 4889 4890 /* SIFS (used in NAV) */ 4891 urtwn_write_2(sc, R92C_SPEC_SIFS, 4892 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4893 4894 /* Set short/long retry limits. */ 4895 urtwn_write_2(sc, R92C_RL, 4896 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4897 4898 /* Initialize EDCA parameters. */ 4899 urtwn_edca_init(sc); 4900 4901 /* Setup rate fallback. */ 4902 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4903 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4904 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4905 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4906 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4907 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4908 } 4909 4910 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4911 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4912 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4913 /* Set ACK timeout. */ 4914 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4915 4916 /* Setup USB aggregation. */ 4917 /* Tx */ 4918 reg = urtwn_read_4(sc, R92C_TDECTRL); 4919 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4920 urtwn_write_4(sc, R92C_TDECTRL, reg); 4921 /* Rx */ 4922 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4923 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4924 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4925 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4926 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4927 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4928 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4929 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4930 ISSET(sc->chip, URTWN_CHIP_92EU)) 4931 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4932 else 4933 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4934 4935 /* Initialize beacon parameters. */ 4936 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4937 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4938 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4939 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4940 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4941 4942 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4943 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4944 /* Setup AMPDU aggregation. */ 4945 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4946 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4947 urtwn_write_2(sc, 0x4ca, 0x0708); 4948 4949 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4950 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4951 } 4952 4953 /* Load 8051 microcode. */ 4954 error = urtwn_load_firmware(sc); 4955 if (error != 0) 4956 goto fail; 4957 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4958 4959 /* Initialize MAC/BB/RF blocks. */ 4960 /* 4961 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4962 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4963 * XXX: This setting should be removed from rtl8192cu_mac[]. 4964 */ 4965 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4966 urtwn_rxfilter_init(sc); // reset R92C_RCR 4967 urtwn_bb_init(sc); 4968 urtwn_rf_init(sc); 4969 4970 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4971 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4972 urtwn_write_2(sc, R92C_CR, 4973 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4974 R92C_CR_MACRXEN); 4975 } 4976 4977 /* Turn CCK and OFDM blocks on. */ 4978 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4979 reg |= R92C_RFMOD_CCK_EN; 4980 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4981 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4982 reg |= R92C_RFMOD_OFDM_EN; 4983 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4984 4985 /* Clear per-station keys table. */ 4986 urtwn_cam_init(sc); 4987 4988 /* Enable hardware sequence numbering. */ 4989 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4990 4991 /* Perform LO and IQ calibrations. */ 4992 urtwn_iq_calib(sc, sc->iqk_inited); 4993 sc->iqk_inited = true; 4994 4995 /* Perform LC calibration. */ 4996 urtwn_lc_calib(sc); 4997 4998 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4999 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5000 /* Fix USB interference issue. */ 5001 urtwn_write_1(sc, 0xfe40, 0xe0); 5002 urtwn_write_1(sc, 0xfe41, 0x8d); 5003 urtwn_write_1(sc, 0xfe42, 0x80); 5004 urtwn_write_4(sc, 0x20c, 0xfd0320); 5005 5006 urtwn_pa_bias_init(sc); 5007 } 5008 5009 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5010 !(sc->chip & URTWN_CHIP_92EU)) { 5011 /* 1T1R */ 5012 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5013 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5014 } 5015 5016 /* Initialize GPIO setting. */ 5017 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5018 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5019 5020 /* Fix for lower temperature. */ 5021 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5022 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5023 urtwn_write_1(sc, 0x15, 0xe9); 5024 5025 /* Set default channel. */ 5026 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5027 5028 /* Queue Rx xfers. */ 5029 for (size_t j = 0; j < sc->rx_npipe; j++) { 5030 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5031 data = &sc->rx_data[j][i]; 5032 usbd_setup_xfer(data->xfer, data, data->buf, 5033 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5034 urtwn_rxeof); 5035 error = usbd_transfer(data->xfer); 5036 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5037 error != USBD_IN_PROGRESS)) 5038 goto fail; 5039 } 5040 } 5041 5042 /* We're ready to go. */ 5043 ifp->if_flags &= ~IFF_OACTIVE; 5044 ifp->if_flags |= IFF_RUNNING; 5045 sc->sc_running = true; 5046 5047 mutex_exit(&sc->sc_write_mtx); 5048 5049 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5050 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5051 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5052 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5053 urtwn_wait_async(sc); 5054 5055 return 0; 5056 5057 fail: 5058 mutex_exit(&sc->sc_write_mtx); 5059 5060 urtwn_stop(ifp, 1); 5061 return error; 5062 } 5063 5064 static void __noinline 5065 urtwn_stop(struct ifnet *ifp, int disable) 5066 { 5067 struct urtwn_softc *sc = ifp->if_softc; 5068 struct ieee80211com *ic = &sc->sc_ic; 5069 size_t i; 5070 int s; 5071 5072 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5073 5074 s = splusb(); 5075 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5076 urtwn_wait_async(sc); 5077 splx(s); 5078 5079 sc->tx_timer = 0; 5080 ifp->if_timer = 0; 5081 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5082 5083 callout_stop(&sc->sc_scan_to); 5084 callout_stop(&sc->sc_calib_to); 5085 5086 /* Abort Tx. */ 5087 for (i = 0; i < sc->tx_npipe; i++) { 5088 if (sc->tx_pipe[i] != NULL) 5089 usbd_abort_pipe(sc->tx_pipe[i]); 5090 } 5091 5092 /* Stop Rx pipe. */ 5093 for (i = 0; i < sc->rx_npipe; i++) { 5094 if (sc->rx_pipe[i] != NULL) 5095 usbd_abort_pipe(sc->rx_pipe[i]); 5096 } 5097 5098 /* Free Tx/Rx buffers. */ 5099 urtwn_free_tx_list(sc); 5100 urtwn_free_rx_list(sc); 5101 5102 sc->sc_running = false; 5103 if (disable) 5104 urtwn_chip_stop(sc); 5105 } 5106 5107 static int 5108 urtwn_reset(struct ifnet *ifp) 5109 { 5110 struct urtwn_softc *sc = ifp->if_softc; 5111 struct ieee80211com *ic = &sc->sc_ic; 5112 5113 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5114 return ENETRESET; 5115 5116 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5117 5118 return 0; 5119 } 5120 5121 static void 5122 urtwn_chip_stop(struct urtwn_softc *sc) 5123 { 5124 uint32_t reg; 5125 bool disabled = true; 5126 5127 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5128 5129 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5130 ISSET(sc->chip, URTWN_CHIP_92EU)) 5131 return; 5132 5133 mutex_enter(&sc->sc_write_mtx); 5134 5135 /* 5136 * RF Off Sequence 5137 */ 5138 /* Pause MAC TX queue */ 5139 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5140 5141 /* Disable RF */ 5142 urtwn_rf_write(sc, 0, 0, 0); 5143 5144 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5145 5146 /* Reset BB state machine */ 5147 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5148 R92C_SYS_FUNC_EN_USBD | 5149 R92C_SYS_FUNC_EN_USBA | 5150 R92C_SYS_FUNC_EN_BB_GLB_RST); 5151 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5152 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5153 5154 /* 5155 * Reset digital sequence 5156 */ 5157 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5158 /* Reset MCU ready status */ 5159 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5160 /* If firmware in ram code, do reset */ 5161 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5162 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5163 ISSET(sc->chip, URTWN_CHIP_92EU)) 5164 urtwn_r88e_fw_reset(sc); 5165 else 5166 urtwn_fw_reset(sc); 5167 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5168 } 5169 } 5170 5171 /* Reset MAC and Enable 8051 */ 5172 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5173 5174 /* Reset MCU ready status */ 5175 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5176 5177 if (disabled) { 5178 /* Disable MAC clock */ 5179 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5180 /* Disable AFE PLL */ 5181 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5182 /* Gated AFE DIG_CLOCK */ 5183 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5184 /* Isolated digital to PON */ 5185 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5186 } 5187 5188 /* 5189 * Pull GPIO PIN to balance level and LED control 5190 */ 5191 /* 1. Disable GPIO[7:0] */ 5192 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5193 5194 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5195 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5196 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5197 5198 /* Disable GPIO[10:8] */ 5199 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5200 5201 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5202 reg |= (((reg & 0x000f) << 4) | 0x0780); 5203 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5204 5205 /* Disable LED0 & 1 */ 5206 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5207 5208 /* 5209 * Reset digital sequence 5210 */ 5211 if (disabled) { 5212 /* Disable ELDR clock */ 5213 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5214 /* Isolated ELDR to PON */ 5215 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5216 } 5217 5218 /* 5219 * Disable analog sequence 5220 */ 5221 if (disabled) { 5222 /* Disable A15 power */ 5223 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5224 /* Disable digital core power */ 5225 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5226 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5227 ~R92C_LDOV12D_CTRL_LDV12_EN); 5228 } 5229 5230 /* Enter PFM mode */ 5231 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5232 5233 /* Set USB suspend */ 5234 urtwn_write_2(sc, R92C_APS_FSMCO, 5235 R92C_APS_FSMCO_APDM_HOST | 5236 R92C_APS_FSMCO_AFSM_HSUS | 5237 R92C_APS_FSMCO_PFM_ALDN); 5238 5239 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5240 5241 mutex_exit(&sc->sc_write_mtx); 5242 } 5243 5244 static void 5245 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5246 { 5247 if (sc->sc_running == false) 5248 DELAY(ms * 1000); 5249 else 5250 usbd_delay_ms(sc->sc_udev, ms); 5251 } 5252 5253 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5254 5255 #ifdef _MODULE 5256 #include "ioconf.c" 5257 #endif 5258 5259 static int 5260 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5261 { 5262 int error = 0; 5263 5264 switch (cmd) { 5265 case MODULE_CMD_INIT: 5266 #ifdef _MODULE 5267 error = config_init_component(cfdriver_ioconf_urtwn, 5268 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5269 #endif 5270 return error; 5271 case MODULE_CMD_FINI: 5272 #ifdef _MODULE 5273 error = config_fini_component(cfdriver_ioconf_urtwn, 5274 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5275 #endif 5276 return error; 5277 default: 5278 return ENOTTY; 5279 } 5280 } 5281
Indexes created Tue Sep 30 17:09:57 GMT 2025