if_urtwn.c revision 1.14
1 /* $NetBSD: if_urtwn.c,v 1.14 2013/01/21 00:02:11 jmcneill Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.14 2013/01/21 00:02:11 jmcneill Exp $"); 26 27 #ifdef _KERNEL_OPT 28 #include "opt_inet.h" 29 #endif 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 /* 78 * The sc_write_mtx locking is to prevent sequences of writes from 79 * being intermingled with each other. I don't know if this is really 80 * needed. I have added it just to be on the safe side. 81 */ 82 83 #ifdef URTWN_DEBUG 84 #define DBG_INIT __BIT(0) 85 #define DBG_FN __BIT(1) 86 #define DBG_TX __BIT(2) 87 #define DBG_RX __BIT(3) 88 #define DBG_STM __BIT(4) 89 #define DBG_RF __BIT(5) 90 #define DBG_REG __BIT(6) 91 #define DBG_ALL 0xffffffffU 92 u_int urtwn_debug = 0; 93 #define DPRINTFN(n, s) \ 94 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 95 #else 96 #define DPRINTFN(n, s) 97 #endif 98 99 static const struct usb_devno urtwn_devs[] = { 100 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 101 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 102 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 103 { USB_VENDOR_ASUSTEK, USB_PRODUCT_ASUSTEK_RTL8192CU }, 104 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 105 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 106 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 107 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 108 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 109 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 110 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 111 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 112 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 113 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 114 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 115 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 116 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 117 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 118 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 119 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 120 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 121 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 122 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 123 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 124 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 125 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 126 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 127 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 128 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 129 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 130 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 131 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 132 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 133 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 134 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 135 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 136 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 137 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 138 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 139 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 140 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 141 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 142 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 143 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 144 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 145 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 146 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 147 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 148 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 149 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 150 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 151 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 152 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 153 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 154 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 155 }; 156 157 static int urtwn_match(device_t, cfdata_t, void *); 158 static void urtwn_attach(device_t, device_t, void *); 159 static int urtwn_detach(device_t, int); 160 static int urtwn_activate(device_t, enum devact); 161 162 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 163 urtwn_attach, urtwn_detach, urtwn_activate); 164 165 static int urtwn_open_pipes(struct urtwn_softc *); 166 static void urtwn_close_pipes(struct urtwn_softc *); 167 static int urtwn_alloc_rx_list(struct urtwn_softc *); 168 static void urtwn_free_rx_list(struct urtwn_softc *); 169 static int urtwn_alloc_tx_list(struct urtwn_softc *); 170 static void urtwn_free_tx_list(struct urtwn_softc *); 171 static void urtwn_task(void *); 172 static void urtwn_do_async(struct urtwn_softc *, 173 void (*)(struct urtwn_softc *, void *), void *, int); 174 static void urtwn_wait_async(struct urtwn_softc *); 175 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 176 int); 177 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 178 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 179 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 180 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 181 int); 182 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 183 int); 184 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 185 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 186 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 187 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 188 static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t, uint32_t); 189 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 190 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 191 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 192 static void urtwn_efuse_read(struct urtwn_softc *); 193 static int urtwn_read_chipid(struct urtwn_softc *); 194 #ifdef URTWN_DEBUG 195 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 196 #endif 197 static void urtwn_read_rom(struct urtwn_softc *); 198 static int urtwn_media_change(struct ifnet *); 199 static int urtwn_ra_init(struct urtwn_softc *); 200 static int urtwn_get_nettype(struct urtwn_softc *); 201 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 202 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 203 static void urtwn_set_led(struct urtwn_softc *, int, int); 204 static void urtwn_calib_to(void *); 205 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 206 static void urtwn_next_scan(void *); 207 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 208 int); 209 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 210 static int urtwn_wme_update(struct ieee80211com *); 211 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 212 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 213 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 214 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 215 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 216 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 217 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 218 struct ieee80211_node *, struct urtwn_tx_data *); 219 static void urtwn_start(struct ifnet *); 220 static void urtwn_watchdog(struct ifnet *); 221 static int urtwn_ioctl(struct ifnet *, u_long, void *); 222 static int urtwn_power_on(struct urtwn_softc *); 223 static int urtwn_llt_init(struct urtwn_softc *); 224 static void urtwn_fw_reset(struct urtwn_softc *); 225 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 226 static int urtwn_load_firmware(struct urtwn_softc *); 227 static int urtwn_dma_init(struct urtwn_softc *); 228 static void urtwn_mac_init(struct urtwn_softc *); 229 static void urtwn_bb_init(struct urtwn_softc *); 230 static void urtwn_rf_init(struct urtwn_softc *); 231 static void urtwn_cam_init(struct urtwn_softc *); 232 static void urtwn_pa_bias_init(struct urtwn_softc *); 233 static void urtwn_rxfilter_init(struct urtwn_softc *); 234 static void urtwn_edca_init(struct urtwn_softc *); 235 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 236 static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, 237 uint16_t[]); 238 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 239 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 240 u_int); 241 static void urtwn_iq_calib(struct urtwn_softc *, bool); 242 static void urtwn_lc_calib(struct urtwn_softc *); 243 static void urtwn_temp_calib(struct urtwn_softc *); 244 static int urtwn_init(struct ifnet *); 245 static void urtwn_stop(struct ifnet *, int); 246 static void urtwn_chip_stop(struct urtwn_softc *); 247 248 /* Aliases. */ 249 #define urtwn_bb_write urtwn_write_4 250 #define urtwn_bb_read urtwn_read_4 251 252 static int 253 urtwn_match(device_t parent, cfdata_t match, void *aux) 254 { 255 struct usb_attach_arg *uaa = aux; 256 257 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 258 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 259 } 260 261 static void 262 urtwn_attach(device_t parent, device_t self, void *aux) 263 { 264 struct urtwn_softc *sc = device_private(self); 265 struct ieee80211com *ic = &sc->sc_ic; 266 struct ifnet *ifp = &sc->sc_if; 267 struct usb_attach_arg *uaa = aux; 268 char *devinfop; 269 int i, error; 270 271 sc->sc_dev = self; 272 sc->sc_udev = uaa->device; 273 274 aprint_naive("\n"); 275 aprint_normal("\n"); 276 277 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 278 279 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 280 aprint_normal_dev(self, "%s\n", devinfop); 281 usbd_devinfo_free(devinfop); 282 283 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 284 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 285 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 286 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 287 288 usb_init_task(&sc->sc_task, urtwn_task, sc); 289 290 callout_init(&sc->sc_scan_to, 0); 291 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 292 callout_init(&sc->sc_calib_to, 0); 293 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 294 295 error = usbd_set_config_no(sc->sc_udev, 1, 0); 296 if (error != 0) { 297 aprint_error_dev(self, "failed to set configuration" 298 ", err=%s\n", usbd_errstr(error)); 299 goto fail; 300 } 301 302 /* Get the first interface handle. */ 303 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 304 if (error != 0) { 305 aprint_error_dev(self, "could not get interface handle\n"); 306 goto fail; 307 } 308 309 error = urtwn_read_chipid(sc); 310 if (error != 0) { 311 aprint_error_dev(self, "unsupported test chip\n"); 312 goto fail; 313 } 314 315 /* Determine number of Tx/Rx chains. */ 316 if (sc->chip & URTWN_CHIP_92C) { 317 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 318 sc->nrxchains = 2; 319 } else { 320 sc->ntxchains = 1; 321 sc->nrxchains = 1; 322 } 323 urtwn_read_rom(sc); 324 325 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 326 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 327 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 328 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 329 "8188CUS", sc->ntxchains, sc->nrxchains, 330 ether_sprintf(ic->ic_myaddr)); 331 332 error = urtwn_open_pipes(sc); 333 if (error != 0) { 334 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 335 goto fail; 336 } 337 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 338 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 339 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 340 341 /* 342 * Setup the 802.11 device. 343 */ 344 ic->ic_ifp = ifp; 345 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 346 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 347 ic->ic_state = IEEE80211_S_INIT; 348 349 /* Set device capabilities. */ 350 ic->ic_caps = 351 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 352 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 353 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 354 IEEE80211_C_WME | /* 802.11e */ 355 IEEE80211_C_WPA; /* 802.11i */ 356 357 /* Set supported .11b and .11g rates. */ 358 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 359 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 360 361 /* Set supported .11b and .11g channels (1 through 14). */ 362 for (i = 1; i <= 14; i++) { 363 ic->ic_channels[i].ic_freq = 364 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 365 ic->ic_channels[i].ic_flags = 366 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 367 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 368 } 369 370 ifp->if_softc = sc; 371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 372 ifp->if_init = urtwn_init; 373 ifp->if_ioctl = urtwn_ioctl; 374 ifp->if_start = urtwn_start; 375 ifp->if_watchdog = urtwn_watchdog; 376 IFQ_SET_READY(&ifp->if_snd); 377 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 378 379 if_attach(ifp); 380 ieee80211_ifattach(ic); 381 /* override default methods */ 382 ic->ic_wme.wme_update = urtwn_wme_update; 383 384 /* Override state transition machine. */ 385 sc->sc_newstate = ic->ic_newstate; 386 ic->ic_newstate = urtwn_newstate; 387 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 388 389 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 390 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 391 &sc->sc_drvbpf); 392 393 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 394 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 395 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 396 397 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 398 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 399 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 400 401 ieee80211_announce(ic); 402 403 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 404 405 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 406 return; 407 408 fail: 409 sc->sc_dying = 1; 410 aprint_error_dev(self, "attach failed\n"); 411 } 412 413 static int 414 urtwn_detach(device_t self, int flags) 415 { 416 struct urtwn_softc *sc = device_private(self); 417 struct ifnet *ifp = &sc->sc_if; 418 int s; 419 420 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 421 422 s = splusb(); 423 424 sc->sc_dying = 1; 425 426 callout_stop(&sc->sc_scan_to); 427 callout_stop(&sc->sc_calib_to); 428 429 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 430 usb_rem_task(sc->sc_udev, &sc->sc_task); 431 urtwn_stop(ifp, 0); 432 433 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 434 bpf_detach(ifp); 435 ieee80211_ifdetach(&sc->sc_ic); 436 if_detach(ifp); 437 438 /* Abort and close Tx/Rx pipes. */ 439 urtwn_close_pipes(sc); 440 } 441 442 splx(s); 443 444 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 445 446 callout_destroy(&sc->sc_scan_to); 447 callout_destroy(&sc->sc_calib_to); 448 449 mutex_destroy(&sc->sc_write_mtx); 450 mutex_destroy(&sc->sc_fwcmd_mtx); 451 mutex_destroy(&sc->sc_tx_mtx); 452 mutex_destroy(&sc->sc_task_mtx); 453 454 return (0); 455 } 456 457 static int 458 urtwn_activate(device_t self, enum devact act) 459 { 460 struct urtwn_softc *sc = device_private(self); 461 462 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 463 464 switch (act) { 465 case DVACT_DEACTIVATE: 466 if_deactivate(sc->sc_ic.ic_ifp); 467 return (0); 468 default: 469 return (EOPNOTSUPP); 470 } 471 } 472 473 static int 474 urtwn_open_pipes(struct urtwn_softc *sc) 475 { 476 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 477 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 478 usb_interface_descriptor_t *id; 479 usb_endpoint_descriptor_t *ed; 480 int i, ntx = 0, error; 481 482 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 483 484 /* Determine the number of bulk-out pipes. */ 485 id = usbd_get_interface_descriptor(sc->sc_iface); 486 for (i = 0; i < id->bNumEndpoints; i++) { 487 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 488 if (ed != NULL && 489 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 490 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 491 ntx++; 492 } 493 DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", 494 device_xname(sc->sc_dev), __func__, ntx)); 495 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 496 aprint_error_dev(sc->sc_dev, 497 "%d: invalid number of Tx bulk pipes\n", ntx); 498 return (EIO); 499 } 500 sc->rx_npipe = 1; 501 sc->tx_npipe = ntx; 502 503 /* Open bulk-in pipe at address 0x81. */ 504 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 505 &sc->rx_pipe); 506 if (error != 0) { 507 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 508 ": %d\n", error); 509 goto fail; 510 } 511 512 /* Open bulk-out pipes (up to 3). */ 513 for (i = 0; i < ntx; i++) { 514 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 515 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 516 if (error != 0) { 517 aprint_error_dev(sc->sc_dev, 518 "could not open Tx bulk pipe 0x%02x: %d\n", 519 epaddr[i], error); 520 goto fail; 521 } 522 } 523 524 /* Map 802.11 access categories to USB pipes. */ 525 sc->ac2idx[WME_AC_BK] = 526 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 527 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 528 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 529 530 fail: 531 if (error != 0) 532 urtwn_close_pipes(sc); 533 return (error); 534 } 535 536 static void 537 urtwn_close_pipes(struct urtwn_softc *sc) 538 { 539 int i; 540 541 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 542 543 /* Close Rx pipe. */ 544 if (sc->rx_pipe != NULL) { 545 usbd_abort_pipe(sc->rx_pipe); 546 usbd_close_pipe(sc->rx_pipe); 547 sc->rx_pipe = NULL; 548 } 549 /* Close Tx pipes. */ 550 for (i = 0; i < R92C_MAX_EPOUT; i++) { 551 if (sc->tx_pipe[i] == NULL) 552 continue; 553 usbd_abort_pipe(sc->tx_pipe[i]); 554 usbd_close_pipe(sc->tx_pipe[i]); 555 sc->tx_pipe[i] = NULL; 556 } 557 } 558 559 static int 560 urtwn_alloc_rx_list(struct urtwn_softc *sc) 561 { 562 struct urtwn_rx_data *data; 563 int i, error = 0; 564 565 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 566 567 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 568 data = &sc->rx_data[i]; 569 570 data->sc = sc; /* Backpointer for callbacks. */ 571 572 data->xfer = usbd_alloc_xfer(sc->sc_udev); 573 if (data->xfer == NULL) { 574 aprint_error_dev(sc->sc_dev, 575 "could not allocate xfer\n"); 576 error = ENOMEM; 577 break; 578 } 579 580 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 581 if (data->buf == NULL) { 582 aprint_error_dev(sc->sc_dev, 583 "could not allocate xfer buffer\n"); 584 error = ENOMEM; 585 break; 586 } 587 } 588 if (error != 0) 589 urtwn_free_rx_list(sc); 590 return (error); 591 } 592 593 static void 594 urtwn_free_rx_list(struct urtwn_softc *sc) 595 { 596 int i; 597 598 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 599 600 /* NB: Caller must abort pipe first. */ 601 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 602 if (sc->rx_data[i].xfer != NULL) { 603 usbd_free_xfer(sc->rx_data[i].xfer); 604 sc->rx_data[i].xfer = NULL; 605 } 606 } 607 } 608 609 static int 610 urtwn_alloc_tx_list(struct urtwn_softc *sc) 611 { 612 struct urtwn_tx_data *data; 613 int i, error = 0; 614 615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 616 617 mutex_enter(&sc->sc_tx_mtx); 618 TAILQ_INIT(&sc->tx_free_list); 619 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 620 data = &sc->tx_data[i]; 621 622 data->sc = sc; /* Backpointer for callbacks. */ 623 624 data->xfer = usbd_alloc_xfer(sc->sc_udev); 625 if (data->xfer == NULL) { 626 aprint_error_dev(sc->sc_dev, 627 "could not allocate xfer\n"); 628 error = ENOMEM; 629 goto fail; 630 } 631 632 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 633 if (data->buf == NULL) { 634 aprint_error_dev(sc->sc_dev, 635 "could not allocate xfer buffer\n"); 636 error = ENOMEM; 637 goto fail; 638 } 639 640 /* Append this Tx buffer to our free list. */ 641 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 642 } 643 mutex_exit(&sc->sc_tx_mtx); 644 return (0); 645 646 fail: 647 urtwn_free_tx_list(sc); 648 mutex_exit(&sc->sc_tx_mtx); 649 return (error); 650 } 651 652 static void 653 urtwn_free_tx_list(struct urtwn_softc *sc) 654 { 655 struct urtwn_tx_data *data; 656 int i; 657 658 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 659 660 /* NB: Caller must abort pipe first. */ 661 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 662 data = &sc->tx_data[i]; 663 664 if (data->xfer != NULL) { 665 usbd_free_xfer(data->xfer); 666 data->xfer = NULL; 667 } 668 } 669 } 670 671 static void 672 urtwn_task(void *arg) 673 { 674 struct urtwn_softc *sc = arg; 675 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 676 struct urtwn_host_cmd *cmd; 677 int s; 678 679 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 680 681 /* Process host commands. */ 682 s = splusb(); 683 mutex_spin_enter(&sc->sc_task_mtx); 684 while (ring->next != ring->cur) { 685 cmd = &ring->cmd[ring->next]; 686 mutex_spin_exit(&sc->sc_task_mtx); 687 splx(s); 688 /* Invoke callback. */ 689 cmd->cb(sc, cmd->data); 690 s = splusb(); 691 mutex_spin_enter(&sc->sc_task_mtx); 692 ring->queued--; 693 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 694 } 695 mutex_spin_exit(&sc->sc_task_mtx); 696 wakeup(&sc->cmdq); 697 splx(s); 698 } 699 700 static void 701 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 702 void *arg, int len) 703 { 704 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 705 struct urtwn_host_cmd *cmd; 706 int s; 707 708 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 709 device_xname(sc->sc_dev), __func__, cb, arg, len)); 710 711 s = splusb(); 712 mutex_spin_enter(&sc->sc_task_mtx); 713 cmd = &ring->cmd[ring->cur]; 714 cmd->cb = cb; 715 KASSERT(len <= sizeof(cmd->data)); 716 memcpy(cmd->data, arg, len); 717 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 718 719 /* If there is no pending command already, schedule a task. */ 720 if (!sc->sc_dying && ++ring->queued == 1) { 721 mutex_spin_exit(&sc->sc_task_mtx); 722 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 723 } else 724 mutex_spin_exit(&sc->sc_task_mtx); 725 splx(s); 726 } 727 728 static void 729 urtwn_wait_async(struct urtwn_softc *sc) 730 { 731 732 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 733 734 /* Wait for all queued asynchronous commands to complete. */ 735 while (sc->cmdq.queued > 0) 736 tsleep(&sc->cmdq, 0, "endtask", 0); 737 } 738 739 static int 740 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 741 int len) 742 { 743 usb_device_request_t req; 744 usbd_status error; 745 746 KASSERT(mutex_owned(&sc->sc_write_mtx)); 747 748 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 749 req.bRequest = R92C_REQ_REGS; 750 USETW(req.wValue, addr); 751 USETW(req.wIndex, 0); 752 USETW(req.wLength, len); 753 error = usbd_do_request(sc->sc_udev, &req, buf); 754 if (error != USBD_NORMAL_COMPLETION) { 755 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 756 device_xname(sc->sc_dev), __func__, error, addr, len)); 757 } 758 return (error); 759 } 760 761 static void 762 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 763 { 764 765 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 766 device_xname(sc->sc_dev), __func__, addr, val)); 767 768 urtwn_write_region_1(sc, addr, &val, 1); 769 } 770 771 static void 772 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 773 { 774 uint8_t buf[2]; 775 776 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 777 device_xname(sc->sc_dev), __func__, addr, val)); 778 779 buf[0] = (uint8_t)val; 780 buf[1] = (uint8_t)(val >> 8); 781 urtwn_write_region_1(sc, addr, buf, 2); 782 } 783 784 static void 785 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 786 { 787 uint8_t buf[4]; 788 789 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 790 device_xname(sc->sc_dev), __func__, addr, val)); 791 792 buf[0] = (uint8_t)val; 793 buf[1] = (uint8_t)(val >> 8); 794 buf[2] = (uint8_t)(val >> 16); 795 buf[3] = (uint8_t)(val >> 24); 796 urtwn_write_region_1(sc, addr, buf, 4); 797 } 798 799 static int 800 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 801 { 802 803 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 804 device_xname(sc->sc_dev), __func__, addr, len)); 805 806 return urtwn_write_region_1(sc, addr, buf, len); 807 } 808 809 static int 810 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 811 int len) 812 { 813 usb_device_request_t req; 814 usbd_status error; 815 816 req.bmRequestType = UT_READ_VENDOR_DEVICE; 817 req.bRequest = R92C_REQ_REGS; 818 USETW(req.wValue, addr); 819 USETW(req.wIndex, 0); 820 USETW(req.wLength, len); 821 error = usbd_do_request(sc->sc_udev, &req, buf); 822 if (error != USBD_NORMAL_COMPLETION) { 823 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 824 device_xname(sc->sc_dev), __func__, error, addr, len)); 825 } 826 return (error); 827 } 828 829 static uint8_t 830 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 831 { 832 uint8_t val; 833 834 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 835 return (0xff); 836 837 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 838 device_xname(sc->sc_dev), __func__, addr, val)); 839 return (val); 840 } 841 842 static uint16_t 843 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 844 { 845 uint8_t buf[2]; 846 uint16_t val; 847 848 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 849 return (0xffff); 850 851 val = LE_READ_2(&buf[0]); 852 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 853 device_xname(sc->sc_dev), __func__, addr, val)); 854 return (val); 855 } 856 857 static uint32_t 858 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 859 { 860 uint8_t buf[4]; 861 uint32_t val; 862 863 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 864 return (0xffffffff); 865 866 val = LE_READ_4(&buf[0]); 867 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 868 device_xname(sc->sc_dev), __func__, addr, val)); 869 return (val); 870 } 871 872 static int 873 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 874 { 875 struct r92c_fw_cmd cmd; 876 uint8_t *cp; 877 int fwcur; 878 int ntries; 879 880 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 881 device_xname(sc->sc_dev), __func__, id, buf, len)); 882 883 KASSERT(mutex_owned(&sc->sc_write_mtx)); 884 885 mutex_enter(&sc->sc_fwcmd_mtx); 886 fwcur = sc->fwcur; 887 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 888 mutex_exit(&sc->sc_fwcmd_mtx); 889 890 /* Wait for current FW box to be empty. */ 891 for (ntries = 0; ntries < 100; ntries++) { 892 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 893 break; 894 DELAY(1); 895 } 896 if (ntries == 100) { 897 aprint_error_dev(sc->sc_dev, 898 "could not send firmware command %d\n", id); 899 return (ETIMEDOUT); 900 } 901 902 memset(&cmd, 0, sizeof(cmd)); 903 KASSERT(len <= sizeof(cmd.msg)); 904 memcpy(cmd.msg, buf, len); 905 906 /* Write the first word last since that will trigger the FW. */ 907 cp = (uint8_t *)&cmd; 908 if (len >= 4) { 909 cmd.id = id | R92C_CMD_FLAG_EXT; 910 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 911 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 912 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 913 } else { 914 cmd.id = id; 915 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 916 } 917 918 return (0); 919 } 920 921 static void 922 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 923 { 924 925 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 926 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 927 } 928 929 static uint32_t 930 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 931 { 932 uint32_t reg[R92C_MAX_CHAINS], val; 933 934 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 935 if (chain != 0) { 936 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 937 } 938 939 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 940 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 941 DELAY(1000); 942 943 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 944 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 945 R92C_HSSI_PARAM2_READ_EDGE); 946 DELAY(1000); 947 948 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 949 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 950 DELAY(1000); 951 952 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 953 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 954 } else { 955 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 956 } 957 return (MS(val, R92C_LSSI_READBACK_DATA)); 958 } 959 960 static int 961 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 962 { 963 int ntries; 964 965 KASSERT(mutex_owned(&sc->sc_write_mtx)); 966 967 urtwn_write_4(sc, R92C_LLT_INIT, 968 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 969 SM(R92C_LLT_INIT_ADDR, addr) | 970 SM(R92C_LLT_INIT_DATA, data)); 971 /* Wait for write operation to complete. */ 972 for (ntries = 0; ntries < 20; ntries++) { 973 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 974 R92C_LLT_INIT_OP_NO_ACTIVE) { 975 /* Done */ 976 return (0); 977 } 978 DELAY(5); 979 } 980 return (ETIMEDOUT); 981 } 982 983 static uint8_t 984 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 985 { 986 uint32_t reg; 987 int ntries; 988 989 KASSERT(mutex_owned(&sc->sc_write_mtx)); 990 991 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 992 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 993 reg &= ~R92C_EFUSE_CTRL_VALID; 994 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 995 996 /* Wait for read operation to complete. */ 997 for (ntries = 0; ntries < 100; ntries++) { 998 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 999 if (reg & R92C_EFUSE_CTRL_VALID) { 1000 /* Done */ 1001 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1002 } 1003 DELAY(5); 1004 } 1005 aprint_error_dev(sc->sc_dev, 1006 "could not read efuse byte at address 0x%04x\n", addr); 1007 return (0xff); 1008 } 1009 1010 static void 1011 urtwn_efuse_read(struct urtwn_softc *sc) 1012 { 1013 uint8_t *rom = (uint8_t *)&sc->rom; 1014 uint32_t reg; 1015 uint16_t addr = 0; 1016 uint8_t off, msk; 1017 int i; 1018 1019 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1020 1021 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1022 1023 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1024 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1025 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1026 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1027 } 1028 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1029 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1030 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1031 reg | R92C_SYS_FUNC_EN_ELDR); 1032 } 1033 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1034 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1035 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1036 urtwn_write_2(sc, R92C_SYS_CLKR, 1037 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1038 } 1039 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1040 while (addr < 512) { 1041 reg = urtwn_efuse_read_1(sc, addr); 1042 if (reg == 0xff) 1043 break; 1044 addr++; 1045 off = reg >> 4; 1046 msk = reg & 0xf; 1047 for (i = 0; i < 4; i++) { 1048 if (msk & (1U << i)) 1049 continue; 1050 1051 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1052 addr++; 1053 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1054 addr++; 1055 } 1056 } 1057 #ifdef URTWN_DEBUG 1058 if (urtwn_debug & DBG_INIT) { 1059 /* Dump ROM content. */ 1060 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1061 for (i = 0; i < (int)sizeof(sc->rom); i++) 1062 printf(":%02x", rom[i]); 1063 printf("\n"); 1064 } 1065 #endif 1066 } 1067 1068 static int 1069 urtwn_read_chipid(struct urtwn_softc *sc) 1070 { 1071 uint32_t reg; 1072 1073 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1074 1075 sc->chip = 0; 1076 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1077 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1078 /* test chip, not supported */ 1079 return (EIO); 1080 } 1081 if (reg & R92C_SYS_CFG_TYPE_92C) { 1082 sc->chip |= URTWN_CHIP_92C; 1083 /* Check if it is a castrated 8192C. */ 1084 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1085 R92C_HPON_FSM_CHIP_BONDING_ID) == 1086 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1087 sc->chip |= URTWN_CHIP_92C_1T2R; 1088 } 1089 } 1090 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1091 sc->chip |= URTWN_CHIP_UMC; 1092 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1093 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1094 } 1095 } 1096 return (0); 1097 } 1098 1099 #ifdef URTWN_DEBUG 1100 static void 1101 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1102 { 1103 1104 aprint_normal_dev(sc->sc_dev, 1105 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1106 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1107 1108 aprint_normal_dev(sc->sc_dev, 1109 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1110 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1111 1112 aprint_normal_dev(sc->sc_dev, 1113 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1114 rp->macaddr[0], rp->macaddr[1], 1115 rp->macaddr[2], rp->macaddr[3], 1116 rp->macaddr[4], rp->macaddr[5]); 1117 1118 aprint_normal_dev(sc->sc_dev, 1119 "string %s, subcustomer_id 0x%x\n", 1120 rp->string, rp->subcustomer_id); 1121 1122 aprint_normal_dev(sc->sc_dev, 1123 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1124 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1125 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1126 1127 aprint_normal_dev(sc->sc_dev, 1128 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1129 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1130 rp->ht40_1s_tx_pwr[0][2], 1131 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1132 rp->ht40_1s_tx_pwr[1][2]); 1133 1134 aprint_normal_dev(sc->sc_dev, 1135 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1136 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1137 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1138 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1139 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1140 1141 aprint_normal_dev(sc->sc_dev, 1142 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1143 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1144 rp->ht20_tx_pwr_diff[2] & 0xf, 1145 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1146 rp->ht20_tx_pwr_diff[2] >> 4); 1147 1148 aprint_normal_dev(sc->sc_dev, 1149 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1150 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1151 rp->ofdm_tx_pwr_diff[2] & 0xf, 1152 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1153 rp->ofdm_tx_pwr_diff[2] >> 4); 1154 1155 aprint_normal_dev(sc->sc_dev, 1156 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1157 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1158 rp->ht40_max_pwr[2] & 0xf, 1159 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1160 rp->ht40_max_pwr[2] >> 4); 1161 1162 aprint_normal_dev(sc->sc_dev, 1163 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1164 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1165 rp->ht20_max_pwr[2] & 0xf, 1166 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1167 rp->ht20_max_pwr[2] >> 4); 1168 1169 aprint_normal_dev(sc->sc_dev, 1170 "xtal_calib %d, tssi %d %d, thermal %d\n", 1171 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1172 1173 aprint_normal_dev(sc->sc_dev, 1174 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1175 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1176 1177 aprint_normal_dev(sc->sc_dev, 1178 "channnel_plan %d, version %d customer_id 0x%x\n", 1179 rp->channel_plan, rp->version, rp->curstomer_id); 1180 } 1181 #endif 1182 1183 static void 1184 urtwn_read_rom(struct urtwn_softc *sc) 1185 { 1186 struct ieee80211com *ic = &sc->sc_ic; 1187 struct r92c_rom *rom = &sc->rom; 1188 1189 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1190 1191 mutex_enter(&sc->sc_write_mtx); 1192 1193 /* Read full ROM image. */ 1194 urtwn_efuse_read(sc); 1195 #ifdef URTWN_DEBUG 1196 if (urtwn_debug & DBG_REG) 1197 urtwn_dump_rom(sc, rom); 1198 #endif 1199 1200 /* XXX Weird but this is what the vendor driver does. */ 1201 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1202 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1203 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1204 1205 DPRINTFN(DBG_INIT, 1206 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1207 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1208 sc->board_type, sc->regulatory)); 1209 1210 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1211 1212 mutex_exit(&sc->sc_write_mtx); 1213 } 1214 1215 static int 1216 urtwn_media_change(struct ifnet *ifp) 1217 { 1218 #ifdef URTWN_DEBUG 1219 struct urtwn_softc *sc = ifp->if_softc; 1220 #endif 1221 int error; 1222 1223 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1224 1225 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1226 return (error); 1227 1228 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1229 (IFF_UP | IFF_RUNNING)) { 1230 urtwn_init(ifp); 1231 } 1232 return (0); 1233 } 1234 1235 /* 1236 * Initialize rate adaptation in firmware. 1237 */ 1238 static int 1239 urtwn_ra_init(struct urtwn_softc *sc) 1240 { 1241 static const uint8_t map[] = { 1242 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1243 }; 1244 struct ieee80211com *ic = &sc->sc_ic; 1245 struct ieee80211_node *ni = ic->ic_bss; 1246 struct ieee80211_rateset *rs = &ni->ni_rates; 1247 struct r92c_fw_cmd_macid_cfg cmd; 1248 uint32_t rates, basicrates; 1249 uint32_t mask; 1250 uint8_t mode; 1251 int maxrate, maxbasicrate, error, i, j; 1252 1253 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1254 1255 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1256 1257 /* Get normal and basic rates mask. */ 1258 rates = basicrates = 0; 1259 maxrate = maxbasicrate = 0; 1260 for (i = 0; i < rs->rs_nrates; i++) { 1261 /* Convert 802.11 rate to HW rate index. */ 1262 for (j = 0; j < (int)__arraycount(map); j++) { 1263 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1264 break; 1265 } 1266 } 1267 if (j == __arraycount(map)) { 1268 /* Unknown rate, skip. */ 1269 continue; 1270 } 1271 1272 rates |= 1U << j; 1273 if (j > maxrate) { 1274 maxrate = j; 1275 } 1276 1277 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1278 basicrates |= 1U << j; 1279 if (j > maxbasicrate) { 1280 maxbasicrate = j; 1281 } 1282 } 1283 } 1284 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1285 mode = R92C_RAID_11B; 1286 } else { 1287 mode = R92C_RAID_11BG; 1288 } 1289 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1290 "maxrate=%x, maxbasicrate=%x\n", 1291 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1292 maxrate, maxbasicrate)); 1293 if (basicrates == 0) { 1294 basicrates |= 1; /* add 1Mbps */ 1295 } 1296 1297 /* Set rates mask for group addressed frames. */ 1298 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1299 mask = (mode << 28) | basicrates; 1300 cmd.mask[0] = (uint8_t)mask; 1301 cmd.mask[1] = (uint8_t)(mask >> 8); 1302 cmd.mask[2] = (uint8_t)(mask >> 16); 1303 cmd.mask[3] = (uint8_t)(mask >> 24); 1304 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1305 if (error != 0) { 1306 aprint_error_dev(sc->sc_dev, 1307 "could not add broadcast station\n"); 1308 return (error); 1309 } 1310 /* Set initial MRR rate. */ 1311 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", 1312 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1313 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1314 1315 /* Set rates mask for unicast frames. */ 1316 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1317 mask = (mode << 28) | rates; 1318 cmd.mask[0] = (uint8_t)mask; 1319 cmd.mask[1] = (uint8_t)(mask >> 8); 1320 cmd.mask[2] = (uint8_t)(mask >> 16); 1321 cmd.mask[3] = (uint8_t)(mask >> 24); 1322 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1323 if (error != 0) { 1324 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1325 return (error); 1326 } 1327 /* Set initial MRR rate. */ 1328 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), 1329 __func__, maxrate)); 1330 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1331 1332 /* Indicate highest supported rate. */ 1333 ni->ni_txrate = rs->rs_nrates - 1; 1334 1335 return (0); 1336 } 1337 1338 static int 1339 urtwn_get_nettype(struct urtwn_softc *sc) 1340 { 1341 struct ieee80211com *ic = &sc->sc_ic; 1342 int type; 1343 1344 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1345 1346 switch (ic->ic_opmode) { 1347 case IEEE80211_M_STA: 1348 type = R92C_CR_NETTYPE_INFRA; 1349 break; 1350 1351 case IEEE80211_M_IBSS: 1352 type = R92C_CR_NETTYPE_ADHOC; 1353 break; 1354 1355 default: 1356 type = R92C_CR_NETTYPE_NOLINK; 1357 break; 1358 } 1359 1360 return (type); 1361 } 1362 1363 static void 1364 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1365 { 1366 uint8_t reg; 1367 1368 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1369 __func__, type)); 1370 1371 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1372 1373 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1374 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1375 } 1376 1377 static void 1378 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1379 { 1380 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1381 uint64_t tsf; 1382 1383 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1384 1385 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1386 1387 /* Enable TSF synchronization. */ 1388 urtwn_write_1(sc, R92C_BCN_CTRL, 1389 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1390 1391 /* Correct TSF */ 1392 urtwn_write_1(sc, R92C_BCN_CTRL, 1393 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1394 1395 /* Set initial TSF. */ 1396 tsf = ni->ni_tstamp.tsf; 1397 tsf = le64toh(tsf); 1398 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1399 tsf -= IEEE80211_DUR_TU; 1400 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1401 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1402 1403 urtwn_write_1(sc, R92C_BCN_CTRL, 1404 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1405 } 1406 1407 static void 1408 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1409 { 1410 uint8_t reg; 1411 1412 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1413 __func__, led, on)); 1414 1415 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1416 1417 if (led == URTWN_LED_LINK) { 1418 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1419 if (!on) { 1420 reg |= R92C_LEDCFG0_DIS; 1421 } 1422 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1423 sc->ledlink = on; /* Save LED state. */ 1424 } 1425 } 1426 1427 static void 1428 urtwn_calib_to(void *arg) 1429 { 1430 struct urtwn_softc *sc = arg; 1431 1432 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1433 1434 if (sc->sc_dying) 1435 return; 1436 1437 /* Do it in a process context. */ 1438 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1439 } 1440 1441 /* ARGSUSED */ 1442 static void 1443 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1444 { 1445 struct r92c_fw_cmd_rssi cmd; 1446 1447 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1448 1449 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1450 goto restart_timer; 1451 1452 mutex_enter(&sc->sc_write_mtx); 1453 if (sc->avg_pwdb != -1) { 1454 /* Indicate Rx signal strength to FW for rate adaptation. */ 1455 memset(&cmd, 0, sizeof(cmd)); 1456 cmd.macid = 0; /* BSS. */ 1457 cmd.pwdb = sc->avg_pwdb; 1458 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1459 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1460 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1461 } 1462 1463 /* Do temperature compensation. */ 1464 urtwn_temp_calib(sc); 1465 mutex_exit(&sc->sc_write_mtx); 1466 1467 restart_timer: 1468 if (!sc->sc_dying) { 1469 /* Restart calibration timer. */ 1470 callout_schedule(&sc->sc_calib_to, hz); 1471 } 1472 } 1473 1474 static void 1475 urtwn_next_scan(void *arg) 1476 { 1477 struct urtwn_softc *sc = arg; 1478 1479 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1480 1481 if (sc->sc_dying) 1482 return; 1483 1484 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1485 ieee80211_next_scan(&sc->sc_ic); 1486 } 1487 1488 static int 1489 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1490 { 1491 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1492 struct urtwn_cmd_newstate cmd; 1493 1494 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1495 device_xname(sc->sc_dev), __func__, 1496 ieee80211_state_name[nstate], nstate, arg)); 1497 1498 callout_stop(&sc->sc_scan_to); 1499 callout_stop(&sc->sc_calib_to); 1500 1501 /* Do it in a process context. */ 1502 cmd.state = nstate; 1503 cmd.arg = arg; 1504 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1505 return (0); 1506 } 1507 1508 static void 1509 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1510 { 1511 struct urtwn_cmd_newstate *cmd = arg; 1512 struct ieee80211com *ic = &sc->sc_ic; 1513 struct ieee80211_node *ni; 1514 enum ieee80211_state ostate = ic->ic_state; 1515 enum ieee80211_state nstate = cmd->state; 1516 uint32_t reg; 1517 uint8_t sifs_time; 1518 int s; 1519 1520 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1521 device_xname(sc->sc_dev), __func__, 1522 ieee80211_state_name[ostate], ostate, 1523 ieee80211_state_name[nstate], nstate)); 1524 1525 s = splnet(); 1526 mutex_enter(&sc->sc_write_mtx); 1527 1528 callout_stop(&sc->sc_scan_to); 1529 callout_stop(&sc->sc_calib_to); 1530 1531 switch (ostate) { 1532 case IEEE80211_S_INIT: 1533 break; 1534 1535 case IEEE80211_S_SCAN: 1536 if (nstate != IEEE80211_S_SCAN) { 1537 /* 1538 * End of scanning 1539 */ 1540 /* flush 4-AC Queue after site_survey */ 1541 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1542 1543 /* Allow Rx from our BSSID only. */ 1544 urtwn_write_4(sc, R92C_RCR, 1545 urtwn_read_4(sc, R92C_RCR) | 1546 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1547 } 1548 break; 1549 1550 case IEEE80211_S_AUTH: 1551 case IEEE80211_S_ASSOC: 1552 break; 1553 1554 case IEEE80211_S_RUN: 1555 /* Turn link LED off. */ 1556 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1557 1558 /* Set media status to 'No Link'. */ 1559 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1560 1561 /* Stop Rx of data frames. */ 1562 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1563 1564 /* Reset TSF. */ 1565 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1566 1567 /* Disable TSF synchronization. */ 1568 urtwn_write_1(sc, R92C_BCN_CTRL, 1569 urtwn_read_1(sc, R92C_BCN_CTRL) | 1570 R92C_BCN_CTRL_DIS_TSF_UDT0); 1571 1572 /* Back to 20MHz mode */ 1573 urtwn_set_chan(sc, ic->ic_curchan, 1574 IEEE80211_HTINFO_2NDCHAN_NONE); 1575 1576 if (ic->ic_opmode == IEEE80211_M_IBSS || 1577 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1578 /* Stop BCN */ 1579 urtwn_write_1(sc, R92C_BCN_CTRL, 1580 urtwn_read_1(sc, R92C_BCN_CTRL) & 1581 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1582 } 1583 1584 /* Reset EDCA parameters. */ 1585 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1586 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1587 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1588 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1589 1590 /* flush all cam entries */ 1591 urtwn_cam_init(sc); 1592 break; 1593 } 1594 1595 switch (nstate) { 1596 case IEEE80211_S_INIT: 1597 /* Turn link LED off. */ 1598 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1599 break; 1600 1601 case IEEE80211_S_SCAN: 1602 if (ostate != IEEE80211_S_SCAN) { 1603 /* 1604 * Begin of scanning 1605 */ 1606 1607 /* Set gain for scanning. */ 1608 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1609 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1610 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1611 1612 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1613 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1614 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1615 1616 /* Set media status to 'No Link'. */ 1617 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1618 1619 /* Allow Rx from any BSSID. */ 1620 urtwn_write_4(sc, R92C_RCR, 1621 urtwn_read_4(sc, R92C_RCR) & 1622 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1623 1624 /* Stop Rx of data frames. */ 1625 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1626 1627 /* Disable update TSF */ 1628 urtwn_write_1(sc, R92C_BCN_CTRL, 1629 urtwn_read_1(sc, R92C_BCN_CTRL) | 1630 R92C_BCN_CTRL_DIS_TSF_UDT0); 1631 } 1632 1633 /* Make link LED blink during scan. */ 1634 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1635 1636 /* Pause AC Tx queues. */ 1637 urtwn_write_1(sc, R92C_TXPAUSE, 1638 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1639 1640 urtwn_set_chan(sc, ic->ic_curchan, 1641 IEEE80211_HTINFO_2NDCHAN_NONE); 1642 1643 /* Start periodic scan. */ 1644 if (!sc->sc_dying) 1645 callout_schedule(&sc->sc_scan_to, hz / 5); 1646 break; 1647 1648 case IEEE80211_S_AUTH: 1649 /* Set initial gain under link. */ 1650 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1651 #ifdef doaslinux 1652 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1653 #else 1654 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1655 #endif 1656 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1657 1658 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1659 #ifdef doaslinux 1660 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1661 #else 1662 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1663 #endif 1664 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1665 1666 /* Set media status to 'No Link'. */ 1667 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1668 1669 /* Allow Rx from any BSSID. */ 1670 urtwn_write_4(sc, R92C_RCR, 1671 urtwn_read_4(sc, R92C_RCR) & 1672 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1673 1674 urtwn_set_chan(sc, ic->ic_curchan, 1675 IEEE80211_HTINFO_2NDCHAN_NONE); 1676 break; 1677 1678 case IEEE80211_S_ASSOC: 1679 break; 1680 1681 case IEEE80211_S_RUN: 1682 ni = ic->ic_bss; 1683 1684 /* XXX: Set 20MHz mode */ 1685 urtwn_set_chan(sc, ic->ic_curchan, 1686 IEEE80211_HTINFO_2NDCHAN_NONE); 1687 1688 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1689 /* Back to 20MHz mode */ 1690 urtwn_set_chan(sc, ic->ic_curchan, 1691 IEEE80211_HTINFO_2NDCHAN_NONE); 1692 1693 /* Enable Rx of data frames. */ 1694 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1695 1696 /* Turn link LED on. */ 1697 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1698 break; 1699 } 1700 1701 /* Set media status to 'Associated'. */ 1702 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1703 1704 /* Set BSSID. */ 1705 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1706 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1707 1708 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1709 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1710 } else { 1711 /* 802.11b/g */ 1712 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1713 } 1714 1715 /* Enable Rx of data frames. */ 1716 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1717 1718 /* Set beacon interval. */ 1719 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1720 1721 if (ic->ic_opmode == IEEE80211_M_STA) { 1722 /* Allow Rx from our BSSID only. */ 1723 urtwn_write_4(sc, R92C_RCR, 1724 urtwn_read_4(sc, R92C_RCR) | 1725 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1726 1727 /* Enable TSF synchronization. */ 1728 urtwn_tsf_sync_enable(sc); 1729 } 1730 1731 sifs_time = 10; 1732 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1733 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1734 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1735 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1736 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1737 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1738 1739 /* Intialize rate adaptation. */ 1740 urtwn_ra_init(sc); 1741 1742 /* Turn link LED on. */ 1743 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1744 1745 /* Reset average RSSI. */ 1746 sc->avg_pwdb = -1; 1747 1748 /* Reset temperature calibration state machine. */ 1749 sc->thcal_state = 0; 1750 sc->thcal_lctemp = 0; 1751 1752 /* Start periodic calibration. */ 1753 if (!sc->sc_dying) 1754 callout_schedule(&sc->sc_calib_to, hz); 1755 break; 1756 } 1757 1758 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1759 1760 mutex_exit(&sc->sc_write_mtx); 1761 splx(s); 1762 } 1763 1764 static int 1765 urtwn_wme_update(struct ieee80211com *ic) 1766 { 1767 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1768 1769 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1770 1771 /* don't override default WME values if WME is not actually enabled */ 1772 if (!(ic->ic_flags & IEEE80211_F_WME)) 1773 return (0); 1774 1775 /* Do it in a process context. */ 1776 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1777 return (0); 1778 } 1779 1780 static void 1781 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1782 { 1783 static const uint16_t ac2reg[WME_NUM_AC] = { 1784 R92C_EDCA_BE_PARAM, 1785 R92C_EDCA_BK_PARAM, 1786 R92C_EDCA_VI_PARAM, 1787 R92C_EDCA_VO_PARAM 1788 }; 1789 struct ieee80211com *ic = &sc->sc_ic; 1790 const struct wmeParams *wmep; 1791 int ac, aifs, slottime; 1792 int s; 1793 1794 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1795 __func__)); 1796 1797 s = splnet(); 1798 mutex_enter(&sc->sc_write_mtx); 1799 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1800 for (ac = 0; ac < WME_NUM_AC; ac++) { 1801 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1802 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1803 aifs = wmep->wmep_aifsn * slottime + 10; 1804 urtwn_write_4(sc, ac2reg[ac], 1805 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1806 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1807 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1808 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1809 } 1810 mutex_exit(&sc->sc_write_mtx); 1811 splx(s); 1812 } 1813 1814 static void 1815 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1816 { 1817 int pwdb; 1818 1819 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1820 device_xname(sc->sc_dev), __func__, rate, rssi)); 1821 1822 /* Convert antenna signal to percentage. */ 1823 if (rssi <= -100 || rssi >= 20) 1824 pwdb = 0; 1825 else if (rssi >= 0) 1826 pwdb = 100; 1827 else 1828 pwdb = 100 + rssi; 1829 if (rate <= 3) { 1830 /* CCK gain is smaller than OFDM/MCS gain. */ 1831 pwdb += 6; 1832 if (pwdb > 100) 1833 pwdb = 100; 1834 if (pwdb <= 14) 1835 pwdb -= 4; 1836 else if (pwdb <= 26) 1837 pwdb -= 8; 1838 else if (pwdb <= 34) 1839 pwdb -= 6; 1840 else if (pwdb <= 42) 1841 pwdb -= 2; 1842 } 1843 if (sc->avg_pwdb == -1) /* Init. */ 1844 sc->avg_pwdb = pwdb; 1845 else if (sc->avg_pwdb < pwdb) 1846 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1847 else 1848 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1849 1850 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 1851 device_xname(sc->sc_dev), __func__, 1852 rate, rssi, pwdb, sc->avg_pwdb)); 1853 } 1854 1855 static int8_t 1856 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1857 { 1858 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1859 struct r92c_rx_phystat *phy; 1860 struct r92c_rx_cck *cck; 1861 uint8_t rpt; 1862 int8_t rssi; 1863 1864 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1865 __func__, rate)); 1866 1867 if (rate <= 3) { 1868 cck = (struct r92c_rx_cck *)physt; 1869 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1870 rpt = (cck->agc_rpt >> 5) & 0x3; 1871 rssi = (cck->agc_rpt & 0x1f) << 1; 1872 } else { 1873 rpt = (cck->agc_rpt >> 6) & 0x3; 1874 rssi = cck->agc_rpt & 0x3e; 1875 } 1876 rssi = cckoff[rpt] - rssi; 1877 } else { /* OFDM/HT. */ 1878 phy = (struct r92c_rx_phystat *)physt; 1879 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1880 } 1881 return (rssi); 1882 } 1883 1884 static void 1885 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1886 { 1887 struct ieee80211com *ic = &sc->sc_ic; 1888 struct ifnet *ifp = ic->ic_ifp; 1889 struct ieee80211_frame *wh; 1890 struct ieee80211_node *ni; 1891 struct r92c_rx_stat *stat; 1892 uint32_t rxdw0, rxdw3; 1893 struct mbuf *m; 1894 uint8_t rate; 1895 int8_t rssi = 0; 1896 int s, infosz; 1897 1898 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1899 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1900 1901 stat = (struct r92c_rx_stat *)buf; 1902 rxdw0 = le32toh(stat->rxdw0); 1903 rxdw3 = le32toh(stat->rxdw3); 1904 1905 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1906 /* 1907 * This should not happen since we setup our Rx filter 1908 * to not receive these frames. 1909 */ 1910 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1911 device_xname(sc->sc_dev), __func__)); 1912 ifp->if_ierrors++; 1913 return; 1914 } 1915 if (__predict_false(pktlen < (int)sizeof(*wh))) { 1916 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1917 device_xname(sc->sc_dev), __func__, pktlen)); 1918 ic->ic_stats.is_rx_tooshort++; 1919 ifp->if_ierrors++; 1920 return; 1921 } 1922 if (__predict_false(pktlen > MCLBYTES)) { 1923 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1924 device_xname(sc->sc_dev), __func__, pktlen)); 1925 ifp->if_ierrors++; 1926 return; 1927 } 1928 1929 rate = MS(rxdw3, R92C_RXDW3_RATE); 1930 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1931 1932 /* Get RSSI from PHY status descriptor if present. */ 1933 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1934 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1935 /* Update our average RSSI. */ 1936 urtwn_update_avgrssi(sc, rate, rssi); 1937 } 1938 1939 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1940 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1941 1942 MGETHDR(m, M_DONTWAIT, MT_DATA); 1943 if (__predict_false(m == NULL)) { 1944 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1945 ic->ic_stats.is_rx_nobuf++; 1946 ifp->if_ierrors++; 1947 return; 1948 } 1949 if (pktlen > (int)MHLEN) { 1950 MCLGET(m, M_DONTWAIT); 1951 if (__predict_false(!(m->m_flags & M_EXT))) { 1952 aprint_error_dev(sc->sc_dev, 1953 "couldn't allocate rx mbuf cluster\n"); 1954 m_freem(m); 1955 ic->ic_stats.is_rx_nobuf++; 1956 ifp->if_ierrors++; 1957 return; 1958 } 1959 } 1960 1961 /* Finalize mbuf. */ 1962 m->m_pkthdr.rcvif = ifp; 1963 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1964 memcpy(mtod(m, uint8_t *), wh, pktlen); 1965 m->m_pkthdr.len = m->m_len = pktlen; 1966 1967 s = splnet(); 1968 if (__predict_false(sc->sc_drvbpf != NULL)) { 1969 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1970 1971 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1972 if (!(rxdw3 & R92C_RXDW3_HT)) { 1973 switch (rate) { 1974 /* CCK. */ 1975 case 0: tap->wr_rate = 2; break; 1976 case 1: tap->wr_rate = 4; break; 1977 case 2: tap->wr_rate = 11; break; 1978 case 3: tap->wr_rate = 22; break; 1979 /* OFDM. */ 1980 case 4: tap->wr_rate = 12; break; 1981 case 5: tap->wr_rate = 18; break; 1982 case 6: tap->wr_rate = 24; break; 1983 case 7: tap->wr_rate = 36; break; 1984 case 8: tap->wr_rate = 48; break; 1985 case 9: tap->wr_rate = 72; break; 1986 case 10: tap->wr_rate = 96; break; 1987 case 11: tap->wr_rate = 108; break; 1988 } 1989 } else if (rate >= 12) { /* MCS0~15. */ 1990 /* Bit 7 set means HT MCS instead of rate. */ 1991 tap->wr_rate = 0x80 | (rate - 12); 1992 } 1993 tap->wr_dbm_antsignal = rssi; 1994 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1995 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1996 1997 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1998 } 1999 2000 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2001 2002 /* push the frame up to the 802.11 stack */ 2003 ieee80211_input(ic, m, ni, rssi, 0); 2004 2005 /* Node is no longer needed. */ 2006 ieee80211_free_node(ni); 2007 2008 splx(s); 2009 } 2010 2011 static void 2012 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2013 { 2014 struct urtwn_rx_data *data = priv; 2015 struct urtwn_softc *sc = data->sc; 2016 struct r92c_rx_stat *stat; 2017 uint32_t rxdw0; 2018 uint8_t *buf; 2019 int len, totlen, pktlen, infosz, npkts; 2020 2021 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2022 device_xname(sc->sc_dev), __func__, status)); 2023 2024 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2025 if (status == USBD_STALLED) 2026 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2027 else if (status != USBD_CANCELLED) 2028 goto resubmit; 2029 return; 2030 } 2031 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2032 2033 if (__predict_false(len < (int)sizeof(*stat))) { 2034 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2035 device_xname(sc->sc_dev), __func__, len)); 2036 goto resubmit; 2037 } 2038 buf = data->buf; 2039 2040 /* Get the number of encapsulated frames. */ 2041 stat = (struct r92c_rx_stat *)buf; 2042 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2043 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2044 device_xname(sc->sc_dev), __func__, npkts)); 2045 2046 /* Process all of them. */ 2047 while (npkts-- > 0) { 2048 if (__predict_false(len < (int)sizeof(*stat))) { 2049 DPRINTFN(DBG_RX, 2050 ("%s: %s: len(%d) is short than header\n", 2051 device_xname(sc->sc_dev), __func__, len)); 2052 break; 2053 } 2054 stat = (struct r92c_rx_stat *)buf; 2055 rxdw0 = le32toh(stat->rxdw0); 2056 2057 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2058 if (__predict_false(pktlen == 0)) { 2059 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2060 device_xname(sc->sc_dev), __func__)); 2061 } 2062 2063 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2064 2065 /* Make sure everything fits in xfer. */ 2066 totlen = sizeof(*stat) + infosz + pktlen; 2067 if (__predict_false(totlen > len)) { 2068 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2069 device_xname(sc->sc_dev), __func__, totlen, 2070 (int)sizeof(*stat), infosz, pktlen, len)); 2071 break; 2072 } 2073 2074 /* Process 802.11 frame. */ 2075 urtwn_rx_frame(sc, buf, pktlen); 2076 2077 /* Next chunk is 128-byte aligned. */ 2078 totlen = roundup2(totlen, 128); 2079 buf += totlen; 2080 len -= totlen; 2081 } 2082 2083 resubmit: 2084 /* Setup a new transfer. */ 2085 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 2086 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 2087 (void)usbd_transfer(xfer); 2088 } 2089 2090 static void 2091 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2092 { 2093 struct urtwn_tx_data *data = priv; 2094 struct urtwn_softc *sc = data->sc; 2095 struct ifnet *ifp = &sc->sc_if; 2096 int s; 2097 2098 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2099 device_xname(sc->sc_dev), __func__, status)); 2100 2101 mutex_enter(&sc->sc_tx_mtx); 2102 /* Put this Tx buffer back to our free list. */ 2103 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2104 mutex_exit(&sc->sc_tx_mtx); 2105 2106 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2107 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2108 if (status == USBD_STALLED) 2109 usbd_clear_endpoint_stall_async(data->pipe); 2110 ifp->if_oerrors++; 2111 } 2112 return; 2113 } 2114 2115 ifp->if_opackets++; 2116 2117 s = splnet(); 2118 sc->tx_timer = 0; 2119 ifp->if_flags &= ~IFF_OACTIVE; 2120 splx(s); 2121 2122 urtwn_start(ifp); 2123 } 2124 2125 static int 2126 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2127 struct urtwn_tx_data *data) 2128 { 2129 struct ieee80211com *ic = &sc->sc_ic; 2130 struct ieee80211_frame *wh; 2131 struct ieee80211_key *k = NULL; 2132 struct r92c_tx_desc *txd; 2133 usbd_pipe_handle pipe; 2134 uint16_t seq, sum; 2135 uint8_t raid, type, tid, qid; 2136 int i, s, hasqos, xferlen, padsize, error; 2137 2138 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2139 2140 wh = mtod(m, struct ieee80211_frame *); 2141 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2142 2143 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2144 k = ieee80211_crypto_encap(ic, ni, m); 2145 if (k == NULL) 2146 return ENOBUFS; 2147 2148 /* packet header may have moved, reset our local pointer */ 2149 wh = mtod(m, struct ieee80211_frame *); 2150 } 2151 2152 if (__predict_false(sc->sc_drvbpf != NULL)) { 2153 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2154 2155 tap->wt_flags = 0; 2156 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2157 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2158 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2159 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2160 2161 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2162 } 2163 2164 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2165 /* data frames in 11n mode */ 2166 struct ieee80211_qosframe *qwh = (void *)wh; 2167 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2168 qid = TID_TO_WME_AC(tid); 2169 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2170 /* Use AC_VO for management frames. */ 2171 qid = WME_AC_VO; 2172 tid = 0; /* compiler happy */ 2173 } else { 2174 /* non-qos data frames */ 2175 tid = R92C_TXDW1_QSEL_BE; 2176 qid = WME_AC_BE; 2177 } 2178 2179 /* Get the USB pipe to use for this AC. */ 2180 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2181 2182 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2183 padsize = 8; 2184 else 2185 padsize = 0; 2186 2187 /* Fill Tx descriptor. */ 2188 txd = (struct r92c_tx_desc *)data->buf; 2189 memset(txd, 0, sizeof(*txd) + padsize); 2190 2191 txd->txdw0 |= htole32( 2192 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2193 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2194 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2195 2196 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2197 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2198 2199 /* fix pad field */ 2200 if (padsize > 0) { 2201 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", 2202 device_xname(sc->sc_dev), __func__, padsize)); 2203 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2204 } 2205 2206 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2207 type == IEEE80211_FC0_TYPE_DATA) { 2208 if (ic->ic_curmode == IEEE80211_MODE_11B) 2209 raid = R92C_RAID_11B; 2210 else 2211 raid = R92C_RAID_11BG; 2212 DPRINTFN(DBG_TX, 2213 ("%s: %s: data packet: tid=%d, raid=%d\n", 2214 device_xname(sc->sc_dev), __func__, tid, raid)); 2215 2216 txd->txdw1 |= htole32( 2217 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2218 SM(R92C_TXDW1_QSEL, tid) | 2219 SM(R92C_TXDW1_RAID, raid) | 2220 R92C_TXDW1_AGGBK); 2221 2222 if (hasqos) { 2223 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2224 } 2225 2226 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2227 /* for 11g */ 2228 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2229 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2230 R92C_TXDW4_HWRTSEN); 2231 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2232 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2233 R92C_TXDW4_HWRTSEN); 2234 } 2235 } 2236 /* Send RTS at OFDM24. */ 2237 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2238 txd->txdw5 |= htole32(0x0001ff00); 2239 /* Send data at OFDM54. */ 2240 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2241 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2242 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2243 device_xname(sc->sc_dev), __func__)); 2244 txd->txdw1 |= htole32( 2245 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2246 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2247 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2248 2249 /* Force CCK1. */ 2250 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2251 /* Use 1Mbps */ 2252 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2253 } else { 2254 /* broadcast or multicast packets */ 2255 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2256 device_xname(sc->sc_dev), __func__)); 2257 txd->txdw1 |= htole32( 2258 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2259 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2260 2261 /* Force CCK1. */ 2262 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2263 /* Use 1Mbps */ 2264 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2265 } 2266 2267 /* Set sequence number */ 2268 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2269 txd->txdseq |= htole16(seq); 2270 2271 if (!hasqos) { 2272 /* Use HW sequence numbering for non-QoS frames. */ 2273 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2274 txd->txdseq |= htole16(0x8000); /* WTF? */ 2275 } 2276 2277 /* Compute Tx descriptor checksum. */ 2278 sum = 0; 2279 for (i = 0; i < (int)sizeof(*txd) / 2; i++) 2280 sum ^= ((uint16_t *)txd)[i]; 2281 txd->txdsum = sum; /* NB: already little endian. */ 2282 2283 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2284 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2285 2286 s = splnet(); 2287 data->pipe = pipe; 2288 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2289 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2290 urtwn_txeof); 2291 error = usbd_transfer(data->xfer); 2292 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2293 error != USBD_IN_PROGRESS)) { 2294 splx(s); 2295 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2296 device_xname(sc->sc_dev), __func__, error)); 2297 return error; 2298 } 2299 splx(s); 2300 return 0; 2301 } 2302 2303 static void 2304 urtwn_start(struct ifnet *ifp) 2305 { 2306 struct urtwn_softc *sc = ifp->if_softc; 2307 struct ieee80211com *ic = &sc->sc_ic; 2308 struct urtwn_tx_data *data; 2309 struct ether_header *eh; 2310 struct ieee80211_node *ni; 2311 struct mbuf *m; 2312 2313 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2314 2315 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2316 return; 2317 2318 data = NULL; 2319 for (;;) { 2320 mutex_enter(&sc->sc_tx_mtx); 2321 if (data == NULL) { 2322 data = TAILQ_FIRST(&sc->tx_free_list); 2323 if (data == NULL) { 2324 mutex_exit(&sc->sc_tx_mtx); 2325 ifp->if_flags |= IFF_OACTIVE; 2326 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2327 device_xname(sc->sc_dev))); 2328 return; 2329 } 2330 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2331 } 2332 2333 /* Send pending management frames first. */ 2334 IF_DEQUEUE(&ic->ic_mgtq, m); 2335 if (m != NULL) { 2336 mutex_exit(&sc->sc_tx_mtx); 2337 ni = (void *)m->m_pkthdr.rcvif; 2338 m->m_pkthdr.rcvif = NULL; 2339 goto sendit; 2340 } 2341 if (ic->ic_state != IEEE80211_S_RUN) 2342 break; 2343 2344 /* Encapsulate and send data frames. */ 2345 IFQ_DEQUEUE(&ifp->if_snd, m); 2346 if (m == NULL) 2347 break; 2348 2349 mutex_exit(&sc->sc_tx_mtx); 2350 2351 if (m->m_len < (int)sizeof(*eh) && 2352 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2353 ifp->if_oerrors++; 2354 continue; 2355 } 2356 eh = mtod(m, struct ether_header *); 2357 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2358 if (ni == NULL) { 2359 m_freem(m); 2360 ifp->if_oerrors++; 2361 continue; 2362 } 2363 2364 bpf_mtap(ifp, m); 2365 2366 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2367 ieee80211_free_node(ni); 2368 ifp->if_oerrors++; 2369 continue; 2370 } 2371 sendit: 2372 bpf_mtap3(ic->ic_rawbpf, m); 2373 2374 if (urtwn_tx(sc, m, ni, data) != 0) { 2375 m_freem(m); 2376 ieee80211_free_node(ni); 2377 ifp->if_oerrors++; 2378 continue; 2379 } 2380 data = NULL; 2381 m_freem(m); 2382 ieee80211_free_node(ni); 2383 sc->tx_timer = 5; 2384 ifp->if_timer = 1; 2385 } 2386 2387 /* Return the Tx buffer to the free list */ 2388 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2389 mutex_exit(&sc->sc_tx_mtx); 2390 } 2391 2392 static void 2393 urtwn_watchdog(struct ifnet *ifp) 2394 { 2395 struct urtwn_softc *sc = ifp->if_softc; 2396 2397 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2398 2399 ifp->if_timer = 0; 2400 2401 if (sc->tx_timer > 0) { 2402 if (--sc->tx_timer == 0) { 2403 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2404 /* urtwn_init(ifp); XXX needs a process context! */ 2405 ifp->if_oerrors++; 2406 return; 2407 } 2408 ifp->if_timer = 1; 2409 } 2410 ieee80211_watchdog(&sc->sc_ic); 2411 } 2412 2413 static int 2414 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2415 { 2416 struct urtwn_softc *sc = ifp->if_softc; 2417 struct ieee80211com *ic = &sc->sc_ic; 2418 struct ifaddr *ifa; 2419 int s, error = 0; 2420 2421 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2422 device_xname(sc->sc_dev), __func__, cmd, data)); 2423 2424 s = splnet(); 2425 2426 switch (cmd) { 2427 case SIOCSIFADDR: 2428 ifa = (struct ifaddr *)data; 2429 ifp->if_flags |= IFF_UP; 2430 #ifdef INET 2431 if (ifa->ifa_addr->sa_family == AF_INET) 2432 arp_ifinit(ifp, ifa); 2433 #endif 2434 /*FALLTHROUGH*/ 2435 case SIOCSIFFLAGS: 2436 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2437 break; 2438 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2439 case IFF_UP | IFF_RUNNING: 2440 break; 2441 case IFF_UP: 2442 urtwn_init(ifp); 2443 break; 2444 case IFF_RUNNING: 2445 urtwn_stop(ifp, 1); 2446 break; 2447 case 0: 2448 break; 2449 } 2450 break; 2451 2452 case SIOCADDMULTI: 2453 case SIOCDELMULTI: 2454 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2455 /* setup multicast filter, etc */ 2456 error = 0; 2457 } 2458 break; 2459 2460 case SIOCS80211CHANNEL: 2461 error = ieee80211_ioctl(ic, cmd, data); 2462 if (error == ENETRESET && 2463 ic->ic_opmode == IEEE80211_M_MONITOR) { 2464 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2465 (IFF_UP | IFF_RUNNING)) { 2466 mutex_enter(&sc->sc_write_mtx); 2467 urtwn_set_chan(sc, ic->ic_curchan, 2468 IEEE80211_HTINFO_2NDCHAN_NONE); 2469 mutex_exit(&sc->sc_write_mtx); 2470 } 2471 error = 0; 2472 } 2473 break; 2474 2475 default: 2476 error = ieee80211_ioctl(ic, cmd, data); 2477 break; 2478 } 2479 if (error == ENETRESET) { 2480 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2481 (IFF_UP | IFF_RUNNING)) { 2482 urtwn_init(ifp); 2483 } 2484 error = 0; 2485 } 2486 2487 splx(s); 2488 2489 return (error); 2490 } 2491 2492 static int 2493 urtwn_power_on(struct urtwn_softc *sc) 2494 { 2495 uint32_t reg; 2496 int ntries; 2497 2498 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2499 2500 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2501 2502 /* Wait for autoload done bit. */ 2503 for (ntries = 0; ntries < 1000; ntries++) { 2504 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2505 break; 2506 DELAY(5); 2507 } 2508 if (ntries == 1000) { 2509 aprint_error_dev(sc->sc_dev, 2510 "timeout waiting for chip autoload\n"); 2511 return (ETIMEDOUT); 2512 } 2513 2514 /* Unlock ISO/CLK/Power control register. */ 2515 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2516 /* Move SPS into PWM mode. */ 2517 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2518 DELAY(100); 2519 2520 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2521 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2522 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2523 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2524 DELAY(100); 2525 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2526 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2527 ~R92C_SYS_ISO_CTRL_MD2PP); 2528 } 2529 2530 /* Auto enable WLAN. */ 2531 urtwn_write_2(sc, R92C_APS_FSMCO, 2532 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2533 for (ntries = 0; ntries < 1000; ntries++) { 2534 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2535 R92C_APS_FSMCO_APFM_ONMAC)) 2536 break; 2537 DELAY(5); 2538 } 2539 if (ntries == 1000) { 2540 aprint_error_dev(sc->sc_dev, 2541 "timeout waiting for MAC auto ON\n"); 2542 return (ETIMEDOUT); 2543 } 2544 2545 /* Enable radio, GPIO and LED functions. */ 2546 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2547 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2548 urtwn_write_2(sc, R92C_APS_FSMCO, 2549 R92C_APS_FSMCO_AFSM_HSUS | 2550 R92C_APS_FSMCO_PDN_EN | 2551 R92C_APS_FSMCO_PFM_ALDN); 2552 2553 /* Release RF digital isolation. */ 2554 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2555 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2556 2557 /* Initialize MAC. */ 2558 urtwn_write_1(sc, R92C_APSD_CTRL, 2559 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2560 for (ntries = 0; ntries < 200; ntries++) { 2561 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2562 R92C_APSD_CTRL_OFF_STATUS)) 2563 break; 2564 DELAY(5); 2565 } 2566 if (ntries == 200) { 2567 aprint_error_dev(sc->sc_dev, 2568 "timeout waiting for MAC initialization\n"); 2569 return (ETIMEDOUT); 2570 } 2571 2572 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2573 reg = urtwn_read_2(sc, R92C_CR); 2574 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2575 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2576 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2577 R92C_CR_ENSEC; 2578 urtwn_write_2(sc, R92C_CR, reg); 2579 2580 urtwn_write_1(sc, 0xfe10, 0x19); 2581 return (0); 2582 } 2583 2584 static int 2585 urtwn_llt_init(struct urtwn_softc *sc) 2586 { 2587 int i, error; 2588 2589 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2590 2591 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2592 2593 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2594 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2595 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2596 return (error); 2597 } 2598 /* NB: 0xff indicates end-of-list. */ 2599 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2600 return (error); 2601 /* 2602 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2603 * as ring buffer. 2604 */ 2605 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2606 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2607 return (error); 2608 } 2609 /* Make the last page point to the beginning of the ring buffer. */ 2610 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2611 return (error); 2612 } 2613 2614 static void 2615 urtwn_fw_reset(struct urtwn_softc *sc) 2616 { 2617 uint16_t reg; 2618 int ntries; 2619 2620 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2621 2622 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2623 2624 /* Tell 8051 to reset itself. */ 2625 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2626 2627 /* Wait until 8051 resets by itself. */ 2628 for (ntries = 0; ntries < 100; ntries++) { 2629 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2630 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2631 return; 2632 DELAY(50); 2633 } 2634 /* Force 8051 reset. */ 2635 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2636 } 2637 2638 static int 2639 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2640 { 2641 uint32_t reg; 2642 int off, mlen, error = 0; 2643 2644 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2645 device_xname(sc->sc_dev), __func__, page, buf, len)); 2646 2647 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2648 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2649 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2650 2651 off = R92C_FW_START_ADDR; 2652 while (len > 0) { 2653 if (len > 196) 2654 mlen = 196; 2655 else if (len > 4) 2656 mlen = 4; 2657 else 2658 mlen = 1; 2659 error = urtwn_write_region(sc, off, buf, mlen); 2660 if (error != 0) 2661 break; 2662 off += mlen; 2663 buf += mlen; 2664 len -= mlen; 2665 } 2666 return (error); 2667 } 2668 2669 static int 2670 urtwn_load_firmware(struct urtwn_softc *sc) 2671 { 2672 firmware_handle_t fwh; 2673 const struct r92c_fw_hdr *hdr; 2674 const char *name; 2675 u_char *fw, *ptr; 2676 size_t len; 2677 uint32_t reg; 2678 int mlen, ntries, page, error; 2679 2680 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2681 2682 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2683 2684 /* Read firmware image from the filesystem. */ 2685 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2686 URTWN_CHIP_UMC_A_CUT) 2687 name = "rtl8192cfwU.bin"; 2688 else 2689 name = "rtl8192cfw.bin"; 2690 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 2691 aprint_error_dev(sc->sc_dev, 2692 "failed loadfirmware of file %s (error %d)\n", name, error); 2693 return (error); 2694 } 2695 len = firmware_get_size(fwh); 2696 fw = firmware_malloc(len); 2697 if (fw == NULL) { 2698 aprint_error_dev(sc->sc_dev, 2699 "failed to allocate firmware memory\n"); 2700 firmware_close(fwh); 2701 return (ENOMEM); 2702 } 2703 error = firmware_read(fwh, 0, fw, len); 2704 firmware_close(fwh); 2705 if (error != 0) { 2706 aprint_error_dev(sc->sc_dev, 2707 "failed to read firmware (error %d)\n", error); 2708 firmware_free(fw, 0); 2709 return (error); 2710 } 2711 2712 ptr = fw; 2713 hdr = (const struct r92c_fw_hdr *)ptr; 2714 /* Check if there is a valid FW header and skip it. */ 2715 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2716 (le16toh(hdr->signature) >> 4) == 0x92c) { 2717 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2718 device_xname(sc->sc_dev), __func__, 2719 le16toh(hdr->version), le16toh(hdr->subversion), 2720 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2721 ptr += sizeof(*hdr); 2722 len -= sizeof(*hdr); 2723 } 2724 2725 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2726 urtwn_fw_reset(sc); 2727 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2728 } 2729 2730 /* download enabled */ 2731 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2732 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2733 R92C_SYS_FUNC_EN_CPUEN); 2734 urtwn_write_1(sc, R92C_MCUFWDL, 2735 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2736 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2737 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2738 2739 /* download firmware */ 2740 for (page = 0; len > 0; page++) { 2741 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2742 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2743 if (error != 0) { 2744 aprint_error_dev(sc->sc_dev, 2745 "could not load firmware page %d\n", page); 2746 goto fail; 2747 } 2748 ptr += mlen; 2749 len -= mlen; 2750 } 2751 2752 /* download disable */ 2753 urtwn_write_1(sc, R92C_MCUFWDL, 2754 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2755 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2756 2757 /* Wait for checksum report. */ 2758 for (ntries = 0; ntries < 1000; ntries++) { 2759 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2760 break; 2761 DELAY(5); 2762 } 2763 if (ntries == 1000) { 2764 aprint_error_dev(sc->sc_dev, 2765 "timeout waiting for checksum report\n"); 2766 error = ETIMEDOUT; 2767 goto fail; 2768 } 2769 2770 /* Wait for firmware readiness. */ 2771 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2772 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2773 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2774 for (ntries = 0; ntries < 1000; ntries++) { 2775 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2776 break; 2777 DELAY(5); 2778 } 2779 if (ntries == 1000) { 2780 aprint_error_dev(sc->sc_dev, 2781 "timeout waiting for firmware readiness\n"); 2782 error = ETIMEDOUT; 2783 goto fail; 2784 } 2785 fail: 2786 firmware_free(fw, 0); 2787 return (error); 2788 } 2789 2790 static int 2791 urtwn_dma_init(struct urtwn_softc *sc) 2792 { 2793 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2794 uint32_t reg; 2795 int error; 2796 2797 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2798 2799 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2800 2801 /* Initialize LLT table. */ 2802 error = urtwn_llt_init(sc); 2803 if (error != 0) 2804 return (error); 2805 2806 /* Get Tx queues to USB endpoints mapping. */ 2807 hashq = hasnq = haslq = 0; 2808 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2809 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2810 device_xname(sc->sc_dev), __func__, reg)); 2811 if (MS(reg, R92C_USB_EP_HQ) != 0) 2812 hashq = 1; 2813 if (MS(reg, R92C_USB_EP_NQ) != 0) 2814 hasnq = 1; 2815 if (MS(reg, R92C_USB_EP_LQ) != 0) 2816 haslq = 1; 2817 nqueues = hashq + hasnq + haslq; 2818 if (nqueues == 0) 2819 return (EIO); 2820 /* Get the number of pages for each queue. */ 2821 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2822 /* The remaining pages are assigned to the high priority queue. */ 2823 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2824 2825 /* Set number of pages for normal priority queue. */ 2826 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2827 urtwn_write_4(sc, R92C_RQPN, 2828 /* Set number of pages for public queue. */ 2829 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2830 /* Set number of pages for high priority queue. */ 2831 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2832 /* Set number of pages for low priority queue. */ 2833 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2834 /* Load values. */ 2835 R92C_RQPN_LD); 2836 2837 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2838 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2839 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2840 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2841 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2842 2843 /* Set queue to USB pipe mapping. */ 2844 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2845 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2846 if (nqueues == 1) { 2847 if (hashq) { 2848 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2849 } else if (hasnq) { 2850 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2851 } else { 2852 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2853 } 2854 } else if (nqueues == 2) { 2855 /* All 2-endpoints configs have a high priority queue. */ 2856 if (!hashq) { 2857 return (EIO); 2858 } 2859 if (hasnq) { 2860 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2861 } else { 2862 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2863 } 2864 } else { 2865 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2866 } 2867 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2868 2869 /* Set Tx/Rx transfer page boundary. */ 2870 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2871 2872 /* Set Tx/Rx transfer page size. */ 2873 urtwn_write_1(sc, R92C_PBP, 2874 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2875 return (0); 2876 } 2877 2878 static void 2879 urtwn_mac_init(struct urtwn_softc *sc) 2880 { 2881 int i; 2882 2883 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2884 2885 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2886 2887 /* Write MAC initialization values. */ 2888 for (i = 0; i < (int)__arraycount(rtl8192cu_mac); i++) 2889 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2890 } 2891 2892 static void 2893 urtwn_bb_init(struct urtwn_softc *sc) 2894 { 2895 const struct urtwn_bb_prog *prog; 2896 uint32_t reg; 2897 int i; 2898 2899 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2900 2901 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2902 2903 /* Enable BB and RF. */ 2904 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2905 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2906 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2907 R92C_SYS_FUNC_EN_DIO_RF); 2908 2909 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2910 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2911 2912 urtwn_write_1(sc, R92C_RF_CTRL, 2913 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2914 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2915 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2916 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2917 2918 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2919 urtwn_write_1(sc, 0x15, 0xe9); 2920 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2921 2922 /* Select BB programming based on board type. */ 2923 if (!(sc->chip & URTWN_CHIP_92C)) { 2924 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2925 prog = &rtl8188ce_bb_prog; 2926 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2927 prog = &rtl8188ru_bb_prog; 2928 } else { 2929 prog = &rtl8188cu_bb_prog; 2930 } 2931 } else { 2932 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2933 prog = &rtl8192ce_bb_prog; 2934 } else { 2935 prog = &rtl8192cu_bb_prog; 2936 } 2937 } 2938 /* Write BB initialization values. */ 2939 for (i = 0; i < prog->count; i++) { 2940 /* additional delay depend on registers */ 2941 switch (prog->regs[i]) { 2942 case 0xfe: 2943 usbd_delay_ms(sc->sc_udev, 50); 2944 break; 2945 case 0xfd: 2946 usbd_delay_ms(sc->sc_udev, 5); 2947 break; 2948 case 0xfc: 2949 usbd_delay_ms(sc->sc_udev, 1); 2950 break; 2951 case 0xfb: 2952 DELAY(50); 2953 break; 2954 case 0xfa: 2955 DELAY(5); 2956 break; 2957 case 0xf9: 2958 DELAY(1); 2959 break; 2960 } 2961 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2962 DELAY(1); 2963 } 2964 2965 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2966 /* 8192C 1T only configuration. */ 2967 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2968 reg = (reg & ~0x00000003) | 0x2; 2969 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2970 2971 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2972 reg = (reg & ~0x00300033) | 0x00200022; 2973 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2974 2975 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2976 reg = (reg & ~0xff000000) | (0x45 << 24); 2977 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2978 2979 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2980 reg = (reg & ~0x000000ff) | 0x23; 2981 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2982 2983 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2984 reg = (reg & ~0x00000030) | (1 << 4); 2985 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2986 2987 reg = urtwn_bb_read(sc, 0xe74); 2988 reg = (reg & ~0x0c000000) | (2 << 26); 2989 urtwn_bb_write(sc, 0xe74, reg); 2990 reg = urtwn_bb_read(sc, 0xe78); 2991 reg = (reg & ~0x0c000000) | (2 << 26); 2992 urtwn_bb_write(sc, 0xe78, reg); 2993 reg = urtwn_bb_read(sc, 0xe7c); 2994 reg = (reg & ~0x0c000000) | (2 << 26); 2995 urtwn_bb_write(sc, 0xe7c, reg); 2996 reg = urtwn_bb_read(sc, 0xe80); 2997 reg = (reg & ~0x0c000000) | (2 << 26); 2998 urtwn_bb_write(sc, 0xe80, reg); 2999 reg = urtwn_bb_read(sc, 0xe88); 3000 reg = (reg & ~0x0c000000) | (2 << 26); 3001 urtwn_bb_write(sc, 0xe88, reg); 3002 } 3003 3004 /* Write AGC values. */ 3005 for (i = 0; i < prog->agccount; i++) { 3006 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3007 DELAY(1); 3008 } 3009 3010 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3011 R92C_HSSI_PARAM2_CCK_HIPWR) { 3012 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3013 } 3014 } 3015 3016 static void 3017 urtwn_rf_init(struct urtwn_softc *sc) 3018 { 3019 const struct urtwn_rf_prog *prog; 3020 uint32_t reg, mask, saved; 3021 int i, j, idx; 3022 3023 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3024 3025 /* Select RF programming based on board type. */ 3026 if (!(sc->chip & URTWN_CHIP_92C)) { 3027 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3028 prog = rtl8188ce_rf_prog; 3029 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3030 prog = rtl8188ru_rf_prog; 3031 } else { 3032 prog = rtl8188cu_rf_prog; 3033 } 3034 } else { 3035 prog = rtl8192ce_rf_prog; 3036 } 3037 3038 for (i = 0; i < sc->nrxchains; i++) { 3039 /* Save RF_ENV control type. */ 3040 idx = i / 2; 3041 mask = 0xffffU << ((i % 2) * 16); 3042 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3043 3044 /* Set RF_ENV enable. */ 3045 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3046 reg |= 0x100000; 3047 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3048 DELAY(1); 3049 3050 /* Set RF_ENV output high. */ 3051 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3052 reg |= 0x10; 3053 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3054 DELAY(1); 3055 3056 /* Set address and data lengths of RF registers. */ 3057 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3058 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3059 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3060 DELAY(1); 3061 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3062 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3063 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3064 DELAY(1); 3065 3066 /* Write RF initialization values for this chain. */ 3067 for (j = 0; j < prog[i].count; j++) { 3068 if (prog[i].regs[j] >= 0xf9 && 3069 prog[i].regs[j] <= 0xfe) { 3070 /* 3071 * These are fake RF registers offsets that 3072 * indicate a delay is required. 3073 */ 3074 usbd_delay_ms(sc->sc_udev, 50); 3075 continue; 3076 } 3077 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3078 DELAY(1); 3079 } 3080 3081 /* Restore RF_ENV control type. */ 3082 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3083 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3084 } 3085 3086 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3087 URTWN_CHIP_UMC_A_CUT) { 3088 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3089 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3090 } 3091 3092 /* Cache RF register CHNLBW. */ 3093 for (i = 0; i < 2; i++) { 3094 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3095 } 3096 } 3097 3098 static void 3099 urtwn_cam_init(struct urtwn_softc *sc) 3100 { 3101 uint32_t content, command; 3102 uint8_t idx; 3103 int i; 3104 3105 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3106 3107 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3108 3109 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3110 content = (idx & 3) 3111 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3112 | R92C_CAM_VALID; 3113 3114 command = R92C_CAMCMD_POLLING 3115 | R92C_CAMCMD_WRITE 3116 | R92C_CAM_CTL0(idx); 3117 3118 urtwn_write_4(sc, R92C_CAMWRITE, content); 3119 urtwn_write_4(sc, R92C_CAMCMD, command); 3120 } 3121 3122 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3123 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3124 if (i == 0) { 3125 content = (idx & 3) 3126 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3127 | R92C_CAM_VALID; 3128 } else { 3129 content = 0; 3130 } 3131 3132 command = R92C_CAMCMD_POLLING 3133 | R92C_CAMCMD_WRITE 3134 | R92C_CAM_CTL0(idx) 3135 | (u_int)i; 3136 3137 urtwn_write_4(sc, R92C_CAMWRITE, content); 3138 urtwn_write_4(sc, R92C_CAMCMD, command); 3139 } 3140 } 3141 3142 /* Invalidate all CAM entries. */ 3143 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3144 } 3145 3146 static void 3147 urtwn_pa_bias_init(struct urtwn_softc *sc) 3148 { 3149 uint8_t reg; 3150 int i; 3151 3152 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3153 3154 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3155 3156 for (i = 0; i < sc->nrxchains; i++) { 3157 if (sc->pa_setting & (1U << i)) 3158 continue; 3159 3160 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3161 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3162 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3163 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3164 } 3165 if (!(sc->pa_setting & 0x10)) { 3166 reg = urtwn_read_1(sc, 0x16); 3167 reg = (reg & ~0xf0) | 0x90; 3168 urtwn_write_1(sc, 0x16, reg); 3169 } 3170 } 3171 3172 static void 3173 urtwn_rxfilter_init(struct urtwn_softc *sc) 3174 { 3175 3176 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3177 3178 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3179 3180 /* Initialize Rx filter. */ 3181 /* TODO: use better filter for monitor mode. */ 3182 urtwn_write_4(sc, R92C_RCR, 3183 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3184 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3185 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3186 /* Accept all multicast frames. */ 3187 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3188 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3189 /* Accept all management frames. */ 3190 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3191 /* Reject all control frames. */ 3192 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3193 /* Accept all data frames. */ 3194 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3195 } 3196 3197 static void 3198 urtwn_edca_init(struct urtwn_softc *sc) 3199 { 3200 3201 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3202 3203 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3204 3205 /* set spec SIFS (used in NAV) */ 3206 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3207 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3208 3209 /* set SIFS CCK/OFDM */ 3210 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3211 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3212 3213 /* TXOP */ 3214 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3215 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3216 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3217 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3218 } 3219 3220 static void 3221 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3222 uint16_t power[URTWN_RIDX_COUNT]) 3223 { 3224 uint32_t reg; 3225 3226 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3227 __func__, chain)); 3228 3229 /* Write per-CCK rate Tx power. */ 3230 if (chain == 0) { 3231 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3232 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3233 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3234 3235 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3236 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3237 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3238 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3239 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3240 } else { 3241 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3242 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3243 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3244 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3245 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3246 3247 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3248 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3249 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3250 } 3251 /* Write per-OFDM rate Tx power. */ 3252 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3253 SM(R92C_TXAGC_RATE06, power[ 4]) | 3254 SM(R92C_TXAGC_RATE09, power[ 5]) | 3255 SM(R92C_TXAGC_RATE12, power[ 6]) | 3256 SM(R92C_TXAGC_RATE18, power[ 7])); 3257 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3258 SM(R92C_TXAGC_RATE24, power[ 8]) | 3259 SM(R92C_TXAGC_RATE36, power[ 9]) | 3260 SM(R92C_TXAGC_RATE48, power[10]) | 3261 SM(R92C_TXAGC_RATE54, power[11])); 3262 /* Write per-MCS Tx power. */ 3263 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3264 SM(R92C_TXAGC_MCS00, power[12]) | 3265 SM(R92C_TXAGC_MCS01, power[13]) | 3266 SM(R92C_TXAGC_MCS02, power[14]) | 3267 SM(R92C_TXAGC_MCS03, power[15])); 3268 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3269 SM(R92C_TXAGC_MCS04, power[16]) | 3270 SM(R92C_TXAGC_MCS05, power[17]) | 3271 SM(R92C_TXAGC_MCS06, power[18]) | 3272 SM(R92C_TXAGC_MCS07, power[19])); 3273 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3274 SM(R92C_TXAGC_MCS08, power[20]) | 3275 SM(R92C_TXAGC_MCS09, power[21]) | 3276 SM(R92C_TXAGC_MCS10, power[22]) | 3277 SM(R92C_TXAGC_MCS11, power[23])); 3278 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3279 SM(R92C_TXAGC_MCS12, power[24]) | 3280 SM(R92C_TXAGC_MCS13, power[25]) | 3281 SM(R92C_TXAGC_MCS14, power[26]) | 3282 SM(R92C_TXAGC_MCS15, power[27])); 3283 } 3284 3285 static void 3286 urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, 3287 uint16_t power[URTWN_RIDX_COUNT]) 3288 { 3289 struct r92c_rom *rom = &sc->rom; 3290 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3291 const struct urtwn_txpwr *base; 3292 int ridx, group; 3293 3294 DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", 3295 device_xname(sc->sc_dev), __func__, chain, chan)); 3296 3297 /* Determine channel group. */ 3298 if (chan <= 3) { 3299 group = 0; 3300 } else if (chan <= 9) { 3301 group = 1; 3302 } else { 3303 group = 2; 3304 } 3305 3306 /* Get original Tx power based on board type and RF chain. */ 3307 if (!(sc->chip & URTWN_CHIP_92C)) { 3308 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3309 base = &rtl8188ru_txagc[chain]; 3310 } else { 3311 base = &rtl8192cu_txagc[chain]; 3312 } 3313 } else { 3314 base = &rtl8192cu_txagc[chain]; 3315 } 3316 3317 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3318 if (sc->regulatory == 0) { 3319 for (ridx = 0; ridx <= 3; ridx++) { 3320 power[ridx] = base->pwr[0][ridx]; 3321 } 3322 } 3323 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3324 if (sc->regulatory == 3) { 3325 power[ridx] = base->pwr[0][ridx]; 3326 /* Apply vendor limits. */ 3327 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3328 maxpow = rom->ht40_max_pwr[group]; 3329 } else { 3330 maxpow = rom->ht20_max_pwr[group]; 3331 } 3332 maxpow = (maxpow >> (chain * 4)) & 0xf; 3333 if (power[ridx] > maxpow) { 3334 power[ridx] = maxpow; 3335 } 3336 } else if (sc->regulatory == 1) { 3337 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3338 power[ridx] = base->pwr[group][ridx]; 3339 } 3340 } else if (sc->regulatory != 2) { 3341 power[ridx] = base->pwr[0][ridx]; 3342 } 3343 } 3344 3345 /* Compute per-CCK rate Tx power. */ 3346 cckpow = rom->cck_tx_pwr[chain][group]; 3347 for (ridx = 0; ridx <= 3; ridx++) { 3348 power[ridx] += cckpow; 3349 if (power[ridx] > R92C_MAX_TX_PWR) { 3350 power[ridx] = R92C_MAX_TX_PWR; 3351 } 3352 } 3353 3354 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3355 if (sc->ntxchains > 1) { 3356 /* Apply reduction for 2 spatial streams. */ 3357 diff = rom->ht40_2s_tx_pwr_diff[group]; 3358 diff = (diff >> (chain * 4)) & 0xf; 3359 htpow = (htpow > diff) ? htpow - diff : 0; 3360 } 3361 3362 /* Compute per-OFDM rate Tx power. */ 3363 diff = rom->ofdm_tx_pwr_diff[group]; 3364 diff = (diff >> (chain * 4)) & 0xf; 3365 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3366 for (ridx = 4; ridx <= 11; ridx++) { 3367 power[ridx] += ofdmpow; 3368 if (power[ridx] > R92C_MAX_TX_PWR) { 3369 power[ridx] = R92C_MAX_TX_PWR; 3370 } 3371 } 3372 3373 /* Compute per-MCS Tx power. */ 3374 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3375 diff = rom->ht20_tx_pwr_diff[group]; 3376 diff = (diff >> (chain * 4)) & 0xf; 3377 htpow += diff; /* HT40->HT20 correction. */ 3378 } 3379 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3380 power[ridx] += htpow; 3381 if (power[ridx] > R92C_MAX_TX_PWR) { 3382 power[ridx] = R92C_MAX_TX_PWR; 3383 } 3384 } 3385 #ifdef URTWN_DEBUG 3386 if (urtwn_debug & DBG_RF) { 3387 /* Dump per-rate Tx power values. */ 3388 printf("%s: %s: Tx power for chain %d:\n", 3389 device_xname(sc->sc_dev), __func__, chain); 3390 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3391 printf("%s: %s: Rate %d = %u\n", 3392 device_xname(sc->sc_dev), __func__, ridx, 3393 power[ridx]); 3394 } 3395 } 3396 #endif 3397 } 3398 3399 static void 3400 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3401 { 3402 uint16_t power[URTWN_RIDX_COUNT]; 3403 int i; 3404 3405 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3406 3407 for (i = 0; i < sc->ntxchains; i++) { 3408 /* Compute per-rate Tx power values. */ 3409 urtwn_get_txpower(sc, i, chan, ht40m, power); 3410 /* Write per-rate Tx power values to hardware. */ 3411 urtwn_write_txpower(sc, i, power); 3412 } 3413 } 3414 3415 static void 3416 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3417 { 3418 struct ieee80211com *ic = &sc->sc_ic; 3419 u_int chan; 3420 int i; 3421 3422 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3423 3424 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3425 __func__, chan)); 3426 3427 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3428 3429 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3430 chan += 2; 3431 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3432 chan -= 2; 3433 } 3434 3435 /* Set Tx power for this new channel. */ 3436 urtwn_set_txpower(sc, chan, ht40m); 3437 3438 for (i = 0; i < sc->nrxchains; i++) { 3439 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3440 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3441 } 3442 3443 if (ht40m) { 3444 /* Is secondary channel below or above primary? */ 3445 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3446 uint32_t reg; 3447 3448 urtwn_write_1(sc, R92C_BWOPMODE, 3449 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3450 3451 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3452 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3453 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3454 3455 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3456 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3457 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3458 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3459 3460 /* Set CCK side band. */ 3461 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3462 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3463 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3464 3465 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3466 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3467 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3468 3469 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3470 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3471 ~R92C_FPGA0_ANAPARAM2_CBW20); 3472 3473 reg = urtwn_bb_read(sc, 0x818); 3474 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3475 urtwn_bb_write(sc, 0x818, reg); 3476 3477 /* Select 40MHz bandwidth. */ 3478 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3479 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3480 } else { 3481 urtwn_write_1(sc, R92C_BWOPMODE, 3482 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3483 3484 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3485 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3486 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3487 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3488 3489 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3490 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3491 R92C_FPGA0_ANAPARAM2_CBW20); 3492 3493 /* Select 20MHz bandwidth. */ 3494 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3495 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3496 } 3497 } 3498 3499 static void 3500 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3501 { 3502 3503 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3504 __func__, inited)); 3505 3506 /* TODO */ 3507 } 3508 3509 static void 3510 urtwn_lc_calib(struct urtwn_softc *sc) 3511 { 3512 uint32_t rf_ac[2]; 3513 uint8_t txmode; 3514 int i; 3515 3516 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3517 3518 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3519 3520 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3521 if ((txmode & 0x70) != 0) { 3522 /* Disable all continuous Tx. */ 3523 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3524 3525 /* Set RF mode to standby mode. */ 3526 for (i = 0; i < sc->nrxchains; i++) { 3527 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3528 urtwn_rf_write(sc, i, R92C_RF_AC, 3529 RW(rf_ac[i], R92C_RF_AC_MODE, 3530 R92C_RF_AC_MODE_STANDBY)); 3531 } 3532 } else { 3533 /* Block all Tx queues. */ 3534 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3535 } 3536 /* Start calibration. */ 3537 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3538 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3539 3540 /* Give calibration the time to complete. */ 3541 usbd_delay_ms(sc->sc_udev, 100); 3542 3543 /* Restore configuration. */ 3544 if ((txmode & 0x70) != 0) { 3545 /* Restore Tx mode. */ 3546 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3547 /* Restore RF mode. */ 3548 for (i = 0; i < sc->nrxchains; i++) { 3549 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3550 } 3551 } else { 3552 /* Unblock all Tx queues. */ 3553 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3554 } 3555 } 3556 3557 static void 3558 urtwn_temp_calib(struct urtwn_softc *sc) 3559 { 3560 int temp; 3561 3562 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3563 3564 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3565 3566 if (sc->thcal_state == 0) { 3567 /* Start measuring temperature. */ 3568 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3569 device_xname(sc->sc_dev), __func__)); 3570 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3571 sc->thcal_state = 1; 3572 return; 3573 } 3574 sc->thcal_state = 0; 3575 3576 /* Read measured temperature. */ 3577 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3578 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3579 __func__, temp)); 3580 if (temp == 0) /* Read failed, skip. */ 3581 return; 3582 3583 /* 3584 * Redo LC calibration if temperature changed significantly since 3585 * last calibration. 3586 */ 3587 if (sc->thcal_lctemp == 0) { 3588 /* First LC calibration is performed in urtwn_init(). */ 3589 sc->thcal_lctemp = temp; 3590 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3591 DPRINTFN(DBG_RF, 3592 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3593 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3594 temp)); 3595 urtwn_lc_calib(sc); 3596 /* Record temperature of last LC calibration. */ 3597 sc->thcal_lctemp = temp; 3598 } 3599 } 3600 3601 static int 3602 urtwn_init(struct ifnet *ifp) 3603 { 3604 struct urtwn_softc *sc = ifp->if_softc; 3605 struct ieee80211com *ic = &sc->sc_ic; 3606 struct urtwn_rx_data *data; 3607 uint32_t reg; 3608 int i, error; 3609 3610 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3611 3612 urtwn_stop(ifp, 0); 3613 3614 mutex_enter(&sc->sc_write_mtx); 3615 3616 mutex_enter(&sc->sc_task_mtx); 3617 /* Init host async commands ring. */ 3618 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3619 mutex_exit(&sc->sc_task_mtx); 3620 3621 mutex_enter(&sc->sc_fwcmd_mtx); 3622 /* Init firmware commands ring. */ 3623 sc->fwcur = 0; 3624 mutex_exit(&sc->sc_fwcmd_mtx); 3625 3626 /* Allocate Tx/Rx buffers. */ 3627 error = urtwn_alloc_rx_list(sc); 3628 if (error != 0) { 3629 aprint_error_dev(sc->sc_dev, 3630 "could not allocate Rx buffers\n"); 3631 goto fail; 3632 } 3633 error = urtwn_alloc_tx_list(sc); 3634 if (error != 0) { 3635 aprint_error_dev(sc->sc_dev, 3636 "could not allocate Tx buffers\n"); 3637 goto fail; 3638 } 3639 3640 /* Power on adapter. */ 3641 error = urtwn_power_on(sc); 3642 if (error != 0) 3643 goto fail; 3644 3645 /* Initialize DMA. */ 3646 error = urtwn_dma_init(sc); 3647 if (error != 0) 3648 goto fail; 3649 3650 /* Set info size in Rx descriptors (in 64-bit words). */ 3651 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3652 3653 /* Init interrupts. */ 3654 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3655 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3656 3657 /* Set MAC address. */ 3658 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3659 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3660 3661 /* Set initial network type. */ 3662 reg = urtwn_read_4(sc, R92C_CR); 3663 switch (ic->ic_opmode) { 3664 case IEEE80211_M_STA: 3665 default: 3666 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3667 break; 3668 3669 case IEEE80211_M_IBSS: 3670 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3671 break; 3672 } 3673 urtwn_write_4(sc, R92C_CR, reg); 3674 3675 urtwn_rxfilter_init(sc); 3676 3677 /* Set response rate */ 3678 reg = urtwn_read_4(sc, R92C_RRSR); 3679 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3680 urtwn_write_4(sc, R92C_RRSR, reg); 3681 3682 /* SIFS (used in NAV) */ 3683 urtwn_write_2(sc, R92C_SPEC_SIFS, 3684 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3685 3686 /* Set short/long retry limits. */ 3687 urtwn_write_2(sc, R92C_RL, 3688 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3689 3690 /* Initialize EDCA parameters. */ 3691 urtwn_edca_init(sc); 3692 3693 /* Setup rate fallback. */ 3694 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3695 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3696 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3697 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3698 3699 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3700 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3701 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3702 /* Set ACK timeout. */ 3703 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3704 3705 /* Setup USB aggregation. */ 3706 /* Tx */ 3707 reg = urtwn_read_4(sc, R92C_TDECTRL); 3708 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3709 urtwn_write_4(sc, R92C_TDECTRL, reg); 3710 /* Rx */ 3711 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3712 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3713 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3714 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3715 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3716 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3717 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3718 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3719 3720 /* Initialize beacon parameters. */ 3721 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3722 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3723 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3724 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3725 3726 /* Setup AMPDU aggregation. */ 3727 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3728 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3729 urtwn_write_2(sc, 0x4ca, 0x0708); 3730 3731 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3732 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3733 3734 /* Load 8051 microcode. */ 3735 error = urtwn_load_firmware(sc); 3736 if (error != 0) 3737 goto fail; 3738 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3739 3740 /* Initialize MAC/BB/RF blocks. */ 3741 urtwn_mac_init(sc); 3742 urtwn_write_4(sc, R92C_RCR, 3743 urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); 3744 urtwn_bb_init(sc); 3745 urtwn_rf_init(sc); 3746 3747 /* Turn CCK and OFDM blocks on. */ 3748 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3749 reg |= R92C_RFMOD_CCK_EN; 3750 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3751 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3752 reg |= R92C_RFMOD_OFDM_EN; 3753 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3754 3755 /* Clear per-station keys table. */ 3756 urtwn_cam_init(sc); 3757 3758 /* Enable hardware sequence numbering. */ 3759 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3760 3761 /* Perform LO and IQ calibrations. */ 3762 urtwn_iq_calib(sc, sc->iqk_inited); 3763 sc->iqk_inited = true; 3764 3765 /* Perform LC calibration. */ 3766 urtwn_lc_calib(sc); 3767 3768 /* Fix USB interference issue. */ 3769 urtwn_write_1(sc, 0xfe40, 0xe0); 3770 urtwn_write_1(sc, 0xfe41, 0x8d); 3771 urtwn_write_1(sc, 0xfe42, 0x80); 3772 urtwn_write_4(sc, 0x20c, 0xfd0320); 3773 3774 urtwn_pa_bias_init(sc); 3775 3776 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3777 /* 1T1R */ 3778 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3779 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3780 } 3781 3782 /* Initialize GPIO setting. */ 3783 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3784 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3785 3786 /* Fix for lower temperature. */ 3787 urtwn_write_1(sc, 0x15, 0xe9); 3788 3789 /* Set default channel. */ 3790 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3791 3792 /* Queue Rx xfers. */ 3793 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3794 data = &sc->rx_data[i]; 3795 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3796 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3797 USBD_NO_TIMEOUT, urtwn_rxeof); 3798 error = usbd_transfer(data->xfer); 3799 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3800 error != USBD_IN_PROGRESS)) 3801 goto fail; 3802 } 3803 3804 /* We're ready to go. */ 3805 ifp->if_flags &= ~IFF_OACTIVE; 3806 ifp->if_flags |= IFF_RUNNING; 3807 3808 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3809 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3810 else 3811 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3812 3813 mutex_exit(&sc->sc_write_mtx); 3814 return (0); 3815 3816 fail: 3817 mutex_exit(&sc->sc_write_mtx); 3818 3819 urtwn_stop(ifp, 1); 3820 return (error); 3821 } 3822 3823 static void 3824 urtwn_stop(struct ifnet *ifp, int disable) 3825 { 3826 struct urtwn_softc *sc = ifp->if_softc; 3827 struct ieee80211com *ic = &sc->sc_ic; 3828 int i, s; 3829 3830 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3831 3832 sc->tx_timer = 0; 3833 ifp->if_timer = 0; 3834 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3835 3836 s = splusb(); 3837 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3838 urtwn_wait_async(sc); 3839 splx(s); 3840 3841 callout_stop(&sc->sc_scan_to); 3842 callout_stop(&sc->sc_calib_to); 3843 3844 /* Abort Tx. */ 3845 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3846 if (sc->tx_pipe[i] != NULL) 3847 usbd_abort_pipe(sc->tx_pipe[i]); 3848 } 3849 3850 /* Stop Rx pipe. */ 3851 usbd_abort_pipe(sc->rx_pipe); 3852 3853 /* Free Tx/Rx buffers. */ 3854 urtwn_free_tx_list(sc); 3855 urtwn_free_rx_list(sc); 3856 3857 if (disable) 3858 urtwn_chip_stop(sc); 3859 } 3860 3861 static void 3862 urtwn_chip_stop(struct urtwn_softc *sc) 3863 { 3864 uint32_t reg; 3865 bool disabled = true; 3866 3867 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3868 3869 mutex_enter(&sc->sc_write_mtx); 3870 3871 /* 3872 * RF Off Sequence 3873 */ 3874 /* Pause MAC TX queue */ 3875 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3876 3877 /* Disable RF */ 3878 urtwn_rf_write(sc, 0, 0, 0); 3879 3880 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3881 3882 /* Reset BB state machine */ 3883 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3884 R92C_SYS_FUNC_EN_USBD | 3885 R92C_SYS_FUNC_EN_USBA | 3886 R92C_SYS_FUNC_EN_BB_GLB_RST); 3887 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3888 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3889 3890 /* 3891 * Reset digital sequence 3892 */ 3893 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3894 /* Reset MCU ready status */ 3895 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3896 /* If firmware in ram code, do reset */ 3897 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3898 urtwn_fw_reset(sc); 3899 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3900 } 3901 } 3902 3903 /* Reset MAC and Enable 8051 */ 3904 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3905 3906 /* Reset MCU ready status */ 3907 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3908 3909 if (disabled) { 3910 /* Disable MAC clock */ 3911 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3912 /* Disable AFE PLL */ 3913 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3914 /* Gated AFE DIG_CLOCK */ 3915 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3916 /* Isolated digital to PON */ 3917 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3918 } 3919 3920 /* 3921 * Pull GPIO PIN to balance level and LED control 3922 */ 3923 /* 1. Disable GPIO[7:0] */ 3924 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3925 3926 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3927 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3928 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3929 3930 /* Disable GPIO[10:8] */ 3931 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3932 3933 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3934 reg |= (((reg & 0x000f) << 4) | 0x0780); 3935 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3936 3937 /* Disable LED0 & 1 */ 3938 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3939 3940 /* 3941 * Reset digital sequence 3942 */ 3943 if (disabled) { 3944 /* Disable ELDR clock */ 3945 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3946 /* Isolated ELDR to PON */ 3947 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3948 } 3949 3950 /* 3951 * Disable analog sequence 3952 */ 3953 if (disabled) { 3954 /* Disable A15 power */ 3955 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3956 /* Disable digital core power */ 3957 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3958 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3959 ~R92C_LDOV12D_CTRL_LDV12_EN); 3960 } 3961 3962 /* Enter PFM mode */ 3963 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3964 3965 /* Set USB suspend */ 3966 urtwn_write_2(sc, R92C_APS_FSMCO, 3967 R92C_APS_FSMCO_APDM_HOST | 3968 R92C_APS_FSMCO_AFSM_HSUS | 3969 R92C_APS_FSMCO_PFM_ALDN); 3970 3971 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3972 3973 mutex_exit(&sc->sc_write_mtx); 3974 } 3975 3976 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 3977 3978 #ifdef _MODULE 3979 #include "ioconf.c" 3980 #endif 3981 3982 static int 3983 if_urtwn_modcmd(modcmd_t cmd, void *aux) 3984 { 3985 int error = 0; 3986 3987 switch (cmd) { 3988 case MODULE_CMD_INIT: 3989 #ifdef _MODULE 3990 error = config_init_component(cfdriver_ioconf_urtwn, 3991 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3992 #endif 3993 return (error); 3994 case MODULE_CMD_FINI: 3995 #ifdef _MODULE 3996 error = config_fini_component(cfdriver_ioconf_urtwn, 3997 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3998 #endif 3999 return (error); 4000 default: 4001 return (ENOTTY); 4002 } 4003 } 4004 4005
Indexes created Tue Sep 30 07:10:03 GMT 2025