if_urtwn.c revision 1.2
1 /* $NetBSD: if_urtwn.c,v 1.2 2012/05/30 11:41:08 skrll Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.2 2012/05/30 11:41:08 skrll Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/sysctl.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 #include <machine/endian.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_netbsd.h> 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/firmload.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usbdi_util.h> 66 #include <dev/usb/usbdevs.h> 67 68 #include <dev/usb/if_urtwnreg.h> 69 #include <dev/usb/if_urtwnvar.h> 70 #include <dev/usb/if_urtwn_data.h> 71 72 #ifdef USB_DEBUG 73 #define URTWN_DEBUG 74 #endif 75 76 #ifdef URTWN_DEBUG 77 #define DBG_INIT __BIT(0) 78 #define DBG_FN __BIT(1) 79 #define DBG_TX __BIT(2) 80 #define DBG_RX __BIT(3) 81 #define DBG_STM __BIT(4) 82 #define DBG_RF __BIT(5) 83 #define DBG_REG __BIT(6) 84 #define DBG_ALL 0xffffffffU 85 u_int urtwn_debug = DBG_TX|DBG_RX|DBG_STM; 86 #define DPRINTFN(n, s) \ 87 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 88 #else 89 #define DPRINTFN(n, s) 90 #endif 91 92 static const struct usb_devno urtwn_devs[] = { 93 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 94 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 95 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 96 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 97 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 98 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 99 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 100 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 101 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 102 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 103 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 104 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 105 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 106 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 107 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 108 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 109 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 110 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 111 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 112 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 113 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 114 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 115 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 116 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 117 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 118 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 123 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 124 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 125 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 126 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 127 }; 128 129 static int urtwn_match(device_t, cfdata_t, void *); 130 static void urtwn_attach(device_t, device_t, void *); 131 static int urtwn_detach(device_t, int); 132 static int urtwn_activate(device_t, enum devact); 133 134 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 135 urtwn_attach, urtwn_detach, urtwn_activate); 136 137 static int urtwn_open_pipes(struct urtwn_softc *); 138 static void urtwn_close_pipes(struct urtwn_softc *); 139 static int urtwn_alloc_rx_list(struct urtwn_softc *); 140 static void urtwn_free_rx_list(struct urtwn_softc *); 141 static int urtwn_alloc_tx_list(struct urtwn_softc *); 142 static void urtwn_free_tx_list(struct urtwn_softc *); 143 static void urtwn_task(void *); 144 static void urtwn_do_async(struct urtwn_softc *, 145 void (*)(struct urtwn_softc *, void *), void *, int); 146 static void urtwn_wait_async(struct urtwn_softc *); 147 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 148 int); 149 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 150 int); 151 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 152 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 153 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 154 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 155 static void urtwn_efuse_read(struct urtwn_softc *); 156 static int urtwn_read_chipid(struct urtwn_softc *); 157 static void urtwn_read_rom(struct urtwn_softc *); 158 static int urtwn_media_change(struct ifnet *); 159 static int urtwn_ra_init(struct urtwn_softc *); 160 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 161 static void urtwn_set_led(struct urtwn_softc *, int, int); 162 static void urtwn_calib_to(void *); 163 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 164 static void urtwn_next_scan(void *); 165 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 166 int); 167 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 168 static int urtwn_wme_update(struct ieee80211com *); 169 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 170 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 171 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 172 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 173 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 174 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 175 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 176 struct ieee80211_node *); 177 static void urtwn_start(struct ifnet *); 178 static void urtwn_watchdog(struct ifnet *); 179 static int urtwn_ioctl(struct ifnet *, u_long, void *); 180 static int urtwn_power_on(struct urtwn_softc *); 181 static int urtwn_llt_init(struct urtwn_softc *); 182 static void urtwn_fw_reset(struct urtwn_softc *); 183 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 184 static int urtwn_load_firmware(struct urtwn_softc *); 185 static int urtwn_dma_init(struct urtwn_softc *); 186 static void urtwn_mac_init(struct urtwn_softc *); 187 static void urtwn_bb_init(struct urtwn_softc *); 188 static void urtwn_rf_init(struct urtwn_softc *); 189 static void urtwn_cam_init(struct urtwn_softc *); 190 static void urtwn_pa_bias_init(struct urtwn_softc *); 191 static void urtwn_rxfilter_init(struct urtwn_softc *); 192 static void urtwn_edca_init(struct urtwn_softc *); 193 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 194 static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, 195 uint16_t[]); 196 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 197 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 198 u_int); 199 static void urtwn_iq_calib(struct urtwn_softc *, bool); 200 static void urtwn_lc_calib(struct urtwn_softc *); 201 static void urtwn_temp_calib(struct urtwn_softc *); 202 static int urtwn_init(struct ifnet *); 203 static void urtwn_stop(struct ifnet *, int); 204 static void urtwn_chip_stop(struct urtwn_softc *); 205 206 /* Aliases. */ 207 #define urtwn_bb_write urtwn_write_4 208 #define urtwn_bb_read urtwn_read_4 209 210 static int 211 urtwn_match(device_t parent, cfdata_t match, void *aux) 212 { 213 struct usb_attach_arg *uaa = aux; 214 215 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 216 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 217 } 218 219 static void 220 urtwn_attach(device_t parent, device_t self, void *aux) 221 { 222 struct urtwn_softc *sc = device_private(self); 223 struct ieee80211com *ic = &sc->sc_ic; 224 struct ifnet *ifp = &sc->sc_if; 225 struct usb_attach_arg *uaa = aux; 226 char *devinfop; 227 int i, error; 228 229 sc->sc_dev = self; 230 sc->sc_udev = uaa->device; 231 232 aprint_naive("\n"); 233 aprint_normal("\n"); 234 235 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 236 aprint_normal_dev(self, "%s\n", devinfop); 237 usbd_devinfo_free(devinfop); 238 239 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 240 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NET); 241 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 242 243 usb_init_task(&sc->sc_task, urtwn_task, sc); 244 245 callout_init(&sc->sc_scan_to, 0); 246 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 247 callout_init(&sc->sc_calib_to, 0); 248 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 249 250 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 251 aprint_error_dev(self, "could not set configuration no\n"); 252 goto fail; 253 } 254 255 /* Get the first interface handle. */ 256 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 257 if (error != 0) { 258 aprint_error_dev(self, "could not get interface handle\n"); 259 goto fail; 260 } 261 262 error = urtwn_read_chipid(sc); 263 if (error != 0) { 264 aprint_error_dev(self, "unsupported test chip\n"); 265 goto fail; 266 } 267 268 /* Determine number of Tx/Rx chains. */ 269 if (sc->chip & URTWN_CHIP_92C) { 270 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 271 sc->nrxchains = 2; 272 } else { 273 sc->ntxchains = 1; 274 sc->nrxchains = 1; 275 } 276 urtwn_read_rom(sc); 277 278 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 279 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 280 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 281 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 282 "8188CUS", sc->ntxchains, sc->nrxchains, 283 ether_sprintf(ic->ic_myaddr)); 284 285 error = urtwn_open_pipes(sc); 286 if (error != 0) { 287 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 288 goto fail; 289 } 290 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 291 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 292 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 293 294 /* 295 * Setup the 802.11 device. 296 */ 297 ic->ic_ifp = ifp; 298 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 299 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 300 ic->ic_state = IEEE80211_S_INIT; 301 302 /* Set device capabilities. */ 303 ic->ic_caps = 304 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 305 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 306 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 307 IEEE80211_C_WME | /* 802.11e */ 308 IEEE80211_C_WPA; /* 802.11i */ 309 310 /* Set supported .11b and .11g rates. */ 311 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 312 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 313 314 /* Set supported .11b and .11g channels (1 through 14). */ 315 for (i = 1; i <= 14; i++) { 316 ic->ic_channels[i].ic_freq = 317 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 318 ic->ic_channels[i].ic_flags = 319 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 320 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 321 } 322 323 ifp->if_softc = sc; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_init = urtwn_init; 326 ifp->if_ioctl = urtwn_ioctl; 327 ifp->if_start = urtwn_start; 328 ifp->if_watchdog = urtwn_watchdog; 329 IFQ_SET_READY(&ifp->if_snd); 330 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 331 332 if_attach(ifp); 333 ieee80211_ifattach(ic); 334 /* override default methods */ 335 ic->ic_wme.wme_update = urtwn_wme_update; 336 337 /* Override state transition machine. */ 338 sc->sc_newstate = ic->ic_newstate; 339 ic->ic_newstate = urtwn_newstate; 340 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 341 342 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 343 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 344 &sc->sc_drvbpf); 345 346 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 347 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 348 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 349 350 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 351 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 352 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 353 354 ieee80211_announce(ic); 355 356 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 357 358 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 359 return; 360 361 fail: 362 sc->sc_dying = 1; 363 aprint_error_dev(self, "attach failed\n"); 364 } 365 366 static int 367 urtwn_detach(device_t self, int flags) 368 { 369 struct urtwn_softc *sc = device_private(self); 370 struct ifnet *ifp = &sc->sc_if; 371 int s; 372 373 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 374 375 s = splusb(); 376 377 sc->sc_dying = 1; 378 379 callout_stop(&sc->sc_scan_to); 380 callout_stop(&sc->sc_calib_to); 381 382 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 383 usb_rem_task(sc->sc_udev, &sc->sc_task); 384 urtwn_stop(ifp, 0); 385 386 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 387 bpf_detach(ifp); 388 ieee80211_ifdetach(&sc->sc_ic); 389 if_detach(ifp); 390 391 /* Abort and close Tx/Rx pipes. */ 392 urtwn_close_pipes(sc); 393 } 394 395 splx(s); 396 397 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 398 399 callout_destroy(&sc->sc_scan_to); 400 callout_destroy(&sc->sc_calib_to); 401 mutex_destroy(&sc->sc_fwcmd_mtx); 402 mutex_destroy(&sc->sc_tx_mtx); 403 mutex_destroy(&sc->sc_task_mtx); 404 405 return (0); 406 } 407 408 static int 409 urtwn_activate(device_t self, enum devact act) 410 { 411 struct urtwn_softc *sc = device_private(self); 412 413 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 414 415 switch (act) { 416 case DVACT_DEACTIVATE: 417 if_deactivate(sc->sc_ic.ic_ifp); 418 return (0); 419 default: 420 return (EOPNOTSUPP); 421 } 422 } 423 424 static int 425 urtwn_open_pipes(struct urtwn_softc *sc) 426 { 427 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 428 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 429 usb_interface_descriptor_t *id; 430 usb_endpoint_descriptor_t *ed; 431 int i, ntx = 0, error; 432 433 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 434 435 /* Determine the number of bulk-out pipes. */ 436 id = usbd_get_interface_descriptor(sc->sc_iface); 437 for (i = 0; i < id->bNumEndpoints; i++) { 438 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 439 if (ed != NULL && 440 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 441 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 442 ntx++; 443 } 444 DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", 445 device_xname(sc->sc_dev), __func__, ntx)); 446 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 447 aprint_error_dev(sc->sc_dev, 448 "%d: invalid number of Tx bulk pipes\n", ntx); 449 return (EIO); 450 } 451 sc->rx_npipe = 1; 452 sc->tx_npipe = ntx; 453 454 /* Open bulk-in pipe at address 0x81. */ 455 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 456 &sc->rx_pipe); 457 if (error != 0) { 458 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe\n"); 459 goto fail; 460 } 461 462 /* Open bulk-out pipes (up to 3). */ 463 for (i = 0; i < ntx; i++) { 464 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 465 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, 468 "could not open Tx bulk pipe 0x%02x\n", epaddr[i]); 469 goto fail; 470 } 471 } 472 473 /* Map 802.11 access categories to USB pipes. */ 474 sc->ac2idx[WME_AC_BK] = 475 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 476 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 477 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 478 479 fail: 480 if (error != 0) 481 urtwn_close_pipes(sc); 482 return (error); 483 } 484 485 static void 486 urtwn_close_pipes(struct urtwn_softc *sc) 487 { 488 int i; 489 490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 491 492 /* Close Rx pipe. */ 493 if (sc->rx_pipe != NULL) { 494 usbd_abort_pipe(sc->rx_pipe); 495 usbd_close_pipe(sc->rx_pipe); 496 sc->rx_pipe = NULL; 497 } 498 /* Close Tx pipes. */ 499 for (i = 0; i < R92C_MAX_EPOUT; i++) { 500 if (sc->tx_pipe[i] == NULL) 501 continue; 502 usbd_abort_pipe(sc->tx_pipe[i]); 503 usbd_close_pipe(sc->tx_pipe[i]); 504 sc->tx_pipe[i] = NULL; 505 } 506 } 507 508 static int 509 urtwn_alloc_rx_list(struct urtwn_softc *sc) 510 { 511 struct urtwn_rx_data *data; 512 int i, error = 0; 513 514 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 515 516 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 517 data = &sc->rx_data[i]; 518 519 data->sc = sc; /* Backpointer for callbacks. */ 520 521 data->xfer = usbd_alloc_xfer(sc->sc_udev); 522 if (data->xfer == NULL) { 523 aprint_error_dev(sc->sc_dev, 524 "could not allocate xfer\n"); 525 error = ENOMEM; 526 break; 527 } 528 529 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 530 if (data->buf == NULL) { 531 aprint_error_dev(sc->sc_dev, 532 "could not allocate xfer buffer\n"); 533 error = ENOMEM; 534 break; 535 } 536 } 537 if (error != 0) 538 urtwn_free_rx_list(sc); 539 return (error); 540 } 541 542 static void 543 urtwn_free_rx_list(struct urtwn_softc *sc) 544 { 545 int i; 546 547 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 548 549 /* NB: Caller must abort pipe first. */ 550 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 551 if (sc->rx_data[i].xfer != NULL) { 552 usbd_free_xfer(sc->rx_data[i].xfer); 553 sc->rx_data[i].xfer = NULL; 554 } 555 } 556 } 557 558 static int 559 urtwn_alloc_tx_list(struct urtwn_softc *sc) 560 { 561 struct urtwn_tx_data *data; 562 int i, error = 0; 563 564 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 565 566 mutex_enter(&sc->sc_tx_mtx); 567 TAILQ_INIT(&sc->tx_free_list); 568 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 569 data = &sc->tx_data[i]; 570 571 data->sc = sc; /* Backpointer for callbacks. */ 572 573 data->xfer = usbd_alloc_xfer(sc->sc_udev); 574 if (data->xfer == NULL) { 575 aprint_error_dev(sc->sc_dev, 576 "could not allocate xfer\n"); 577 error = ENOMEM; 578 goto fail; 579 } 580 581 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 582 if (data->buf == NULL) { 583 aprint_error_dev(sc->sc_dev, 584 "could not allocate xfer buffer\n"); 585 error = ENOMEM; 586 goto fail; 587 } 588 589 /* Append this Tx buffer to our free list. */ 590 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 591 } 592 mutex_exit(&sc->sc_tx_mtx); 593 return (0); 594 595 fail: 596 urtwn_free_tx_list(sc); 597 mutex_exit(&sc->sc_tx_mtx); 598 return (error); 599 } 600 601 static void 602 urtwn_free_tx_list(struct urtwn_softc *sc) 603 { 604 struct urtwn_tx_data *data; 605 int i; 606 607 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 608 609 /* NB: Caller must abort pipe first. */ 610 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 611 data = &sc->tx_data[i]; 612 613 if (data->xfer != NULL) { 614 usbd_free_xfer(data->xfer); 615 data->xfer = NULL; 616 } 617 } 618 } 619 620 static void 621 urtwn_task(void *arg) 622 { 623 struct urtwn_softc *sc = arg; 624 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 625 struct urtwn_host_cmd *cmd; 626 int s; 627 628 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 629 630 /* Process host commands. */ 631 s = splusb(); 632 mutex_spin_enter(&sc->sc_task_mtx); 633 while (ring->next != ring->cur) { 634 cmd = &ring->cmd[ring->next]; 635 mutex_spin_exit(&sc->sc_task_mtx); 636 splx(s); 637 /* Invoke callback. */ 638 cmd->cb(sc, cmd->data); 639 s = splusb(); 640 mutex_spin_enter(&sc->sc_task_mtx); 641 ring->queued--; 642 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 643 } 644 mutex_spin_exit(&sc->sc_task_mtx); 645 wakeup(&sc->cmdq); 646 splx(s); 647 } 648 649 static void 650 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 651 void *arg, int len) 652 { 653 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 654 struct urtwn_host_cmd *cmd; 655 int s; 656 657 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 658 device_xname(sc->sc_dev), __func__, cb, arg, len)); 659 660 s = splusb(); 661 mutex_spin_enter(&sc->sc_task_mtx); 662 cmd = &ring->cmd[ring->cur]; 663 cmd->cb = cb; 664 KASSERT(len <= sizeof(cmd->data)); 665 memcpy(cmd->data, arg, len); 666 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 667 668 /* If there is no pending command already, schedule a task. */ 669 if (!sc->sc_dying && ++ring->queued == 1) { 670 mutex_spin_exit(&sc->sc_task_mtx); 671 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 672 } else 673 mutex_spin_exit(&sc->sc_task_mtx); 674 splx(s); 675 } 676 677 static void 678 urtwn_wait_async(struct urtwn_softc *sc) 679 { 680 681 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 682 683 /* Wait for all queued asynchronous commands to complete. */ 684 while (sc->cmdq.queued > 0) 685 tsleep(&sc->cmdq, 0, "endtask", 0); 686 } 687 688 static int 689 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 690 int len) 691 { 692 usb_device_request_t req; 693 usbd_status error; 694 695 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 696 req.bRequest = R92C_REQ_REGS; 697 USETW(req.wValue, addr); 698 USETW(req.wIndex, 0); 699 USETW(req.wLength, len); 700 error = usbd_do_request(sc->sc_udev, &req, buf); 701 if (error != USBD_NORMAL_COMPLETION) { 702 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 703 device_xname(sc->sc_dev), __func__, error, addr, len)); 704 } 705 return (error); 706 } 707 708 static void 709 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 710 { 711 712 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 713 device_xname(sc->sc_dev), __func__, addr, val)); 714 715 urtwn_write_region_1(sc, addr, &val, 1); 716 } 717 718 static void 719 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 720 { 721 uint8_t buf[2]; 722 723 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 724 device_xname(sc->sc_dev), __func__, addr, val)); 725 726 buf[0] = (uint8_t)val; 727 buf[1] = (uint8_t)(val >> 8); 728 urtwn_write_region_1(sc, addr, buf, 2); 729 } 730 731 static void 732 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 733 { 734 uint8_t buf[4]; 735 736 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 737 device_xname(sc->sc_dev), __func__, addr, val)); 738 739 buf[0] = (uint8_t)val; 740 buf[1] = (uint8_t)(val >> 8); 741 buf[2] = (uint8_t)(val >> 16); 742 buf[3] = (uint8_t)(val >> 24); 743 urtwn_write_region_1(sc, addr, buf, 4); 744 } 745 746 static int 747 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 748 { 749 750 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 751 device_xname(sc->sc_dev), __func__, addr, len)); 752 753 return urtwn_write_region_1(sc, addr, buf, len); 754 } 755 756 static int 757 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 758 int len) 759 { 760 usb_device_request_t req; 761 usbd_status error; 762 763 req.bmRequestType = UT_READ_VENDOR_DEVICE; 764 req.bRequest = R92C_REQ_REGS; 765 USETW(req.wValue, addr); 766 USETW(req.wIndex, 0); 767 USETW(req.wLength, len); 768 error = usbd_do_request(sc->sc_udev, &req, buf); 769 if (error != USBD_NORMAL_COMPLETION) { 770 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 771 device_xname(sc->sc_dev), __func__, error, addr, len)); 772 } 773 return (error); 774 } 775 776 static uint8_t 777 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 778 { 779 uint8_t val; 780 781 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 782 return (0xff); 783 784 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 785 device_xname(sc->sc_dev), __func__, addr, val)); 786 return (val); 787 } 788 789 static uint16_t 790 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 791 { 792 uint8_t buf[2]; 793 uint16_t val; 794 795 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 796 return (0xffff); 797 798 val = LE_READ_2(&buf[0]); 799 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 800 device_xname(sc->sc_dev), __func__, addr, val)); 801 return (val); 802 } 803 804 static uint32_t 805 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 806 { 807 uint8_t buf[4]; 808 uint32_t val; 809 810 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 811 return (0xffffffff); 812 813 val = LE_READ_4(&buf[0]); 814 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 815 device_xname(sc->sc_dev), __func__, addr, val)); 816 return (val); 817 } 818 819 static int 820 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 821 { 822 struct r92c_fw_cmd cmd; 823 uint8_t *cp; 824 int fwcur; 825 int ntries; 826 827 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 828 device_xname(sc->sc_dev), __func__, id, buf, len)); 829 830 mutex_enter(&sc->sc_fwcmd_mtx); 831 fwcur = sc->fwcur; 832 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 833 mutex_exit(&sc->sc_fwcmd_mtx); 834 835 /* Wait for current FW box to be empty. */ 836 for (ntries = 0; ntries < 100; ntries++) { 837 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 838 break; 839 DELAY(1); 840 } 841 if (ntries == 100) { 842 aprint_error_dev(sc->sc_dev, 843 "could not send firmware command %d\n", id); 844 return (ETIMEDOUT); 845 } 846 847 memset(&cmd, 0, sizeof(cmd)); 848 KASSERT(len <= sizeof(cmd.msg)); 849 memcpy(cmd.msg, buf, len); 850 851 /* Write the first word last since that will trigger the FW. */ 852 cp = (uint8_t *)&cmd; 853 if (len >= 4) { 854 cmd.id = id | R92C_CMD_FLAG_EXT; 855 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 856 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 857 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 858 } else { 859 cmd.id = id; 860 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 861 } 862 863 return (0); 864 } 865 866 static void 867 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 868 { 869 870 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 871 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 872 } 873 874 static uint32_t 875 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 876 { 877 uint32_t reg[R92C_MAX_CHAINS], val; 878 879 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 880 if (chain != 0) { 881 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 882 } 883 884 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 885 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 886 DELAY(1000); 887 888 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 889 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 890 R92C_HSSI_PARAM2_READ_EDGE); 891 DELAY(1000); 892 893 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 894 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 895 DELAY(1000); 896 897 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 898 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 899 } else { 900 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 901 } 902 return (MS(val, R92C_LSSI_READBACK_DATA)); 903 } 904 905 static int 906 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 907 { 908 int ntries; 909 910 urtwn_write_4(sc, R92C_LLT_INIT, 911 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 912 SM(R92C_LLT_INIT_ADDR, addr) | 913 SM(R92C_LLT_INIT_DATA, data)); 914 /* Wait for write operation to complete. */ 915 for (ntries = 0; ntries < 20; ntries++) { 916 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 917 R92C_LLT_INIT_OP_NO_ACTIVE) { 918 /* Done */ 919 return (0); 920 } 921 DELAY(5); 922 } 923 return (ETIMEDOUT); 924 } 925 926 static uint8_t 927 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 928 { 929 uint32_t reg; 930 int ntries; 931 932 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 933 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 934 reg &= ~R92C_EFUSE_CTRL_VALID; 935 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 936 937 /* Wait for read operation to complete. */ 938 for (ntries = 0; ntries < 100; ntries++) { 939 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 940 if (reg & R92C_EFUSE_CTRL_VALID) { 941 /* Done */ 942 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 943 } 944 DELAY(5); 945 } 946 aprint_error_dev(sc->sc_dev, 947 "could not read efuse byte at address 0x%04x\n", addr); 948 return (0xff); 949 } 950 951 static void 952 urtwn_efuse_read(struct urtwn_softc *sc) 953 { 954 uint8_t *rom = (uint8_t *)&sc->rom; 955 uint32_t reg; 956 uint16_t addr = 0; 957 uint8_t off, msk; 958 int i; 959 960 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 961 962 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 963 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 964 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 965 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 966 } 967 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 968 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 969 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 970 reg | R92C_SYS_FUNC_EN_ELDR); 971 } 972 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 973 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 974 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 975 urtwn_write_2(sc, R92C_SYS_CLKR, 976 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 977 } 978 memset(&sc->rom, 0xff, sizeof(sc->rom)); 979 while (addr < 512) { 980 reg = urtwn_efuse_read_1(sc, addr); 981 if (reg == 0xff) 982 break; 983 addr++; 984 off = reg >> 4; 985 msk = reg & 0xf; 986 for (i = 0; i < 4; i++) { 987 if (msk & (1U << i)) 988 continue; 989 990 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 991 addr++; 992 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 993 addr++; 994 } 995 } 996 #ifdef URTWN_DEBUG 997 if (urtwn_debug & DBG_INIT) { 998 /* Dump ROM content. */ 999 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1000 for (i = 0; i < (int)sizeof(sc->rom); i++) 1001 printf(":%02x", rom[i]); 1002 printf("\n"); 1003 } 1004 #endif 1005 } 1006 1007 static int 1008 urtwn_read_chipid(struct urtwn_softc *sc) 1009 { 1010 uint32_t reg; 1011 1012 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1013 1014 sc->chip = 0; 1015 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1016 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1017 /* test chip, not supported */ 1018 return (EIO); 1019 } 1020 if (reg & R92C_SYS_CFG_TYPE_92C) { 1021 sc->chip |= URTWN_CHIP_92C; 1022 /* Check if it is a castrated 8192C. */ 1023 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1024 R92C_HPON_FSM_CHIP_BONDING_ID) == 1025 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1026 sc->chip |= URTWN_CHIP_92C_1T2R; 1027 } 1028 } 1029 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1030 sc->chip |= URTWN_CHIP_UMC; 1031 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1032 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1033 } 1034 } 1035 return (0); 1036 } 1037 1038 #ifdef URTWN_DEBUG 1039 static void 1040 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1041 { 1042 1043 aprint_normal_dev(sc->sc_dev, 1044 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1045 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1046 1047 aprint_normal_dev(sc->sc_dev, 1048 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1049 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1050 1051 aprint_normal_dev(sc->sc_dev, 1052 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1053 rp->macaddr[0], rp->macaddr[1], 1054 rp->macaddr[2], rp->macaddr[3], 1055 rp->macaddr[4], rp->macaddr[5]); 1056 1057 aprint_normal_dev(sc->sc_dev, 1058 "string %s, subcustomer_id 0x%x\n", 1059 rp->string, rp->subcustomer_id); 1060 1061 aprint_normal_dev(sc->sc_dev, 1062 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1063 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1064 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1065 1066 aprint_normal_dev(sc->sc_dev, 1067 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1068 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1069 rp->ht40_1s_tx_pwr[0][2], 1070 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1071 rp->ht40_1s_tx_pwr[1][2]); 1072 1073 aprint_normal_dev(sc->sc_dev, 1074 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1075 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1076 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1077 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1078 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1079 1080 aprint_normal_dev(sc->sc_dev, 1081 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1082 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1083 rp->ht20_tx_pwr_diff[2] & 0xf, 1084 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1085 rp->ht20_tx_pwr_diff[2] >> 4); 1086 1087 aprint_normal_dev(sc->sc_dev, 1088 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1089 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1090 rp->ofdm_tx_pwr_diff[2] & 0xf, 1091 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1092 rp->ofdm_tx_pwr_diff[2] >> 4); 1093 1094 aprint_normal_dev(sc->sc_dev, 1095 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1096 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1097 rp->ht40_max_pwr[2] & 0xf, 1098 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1099 rp->ht40_max_pwr[2] >> 4); 1100 1101 aprint_normal_dev(sc->sc_dev, 1102 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1103 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1104 rp->ht20_max_pwr[2] & 0xf, 1105 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1106 rp->ht20_max_pwr[2] >> 4); 1107 1108 aprint_normal_dev(sc->sc_dev, 1109 "xtal_calib %d, tssi %d %d, thermal %d\n", 1110 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1111 1112 aprint_normal_dev(sc->sc_dev, 1113 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1114 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1115 1116 aprint_normal_dev(sc->sc_dev, 1117 "channnel_plan %d, version %d customer_id 0x%x\n", 1118 rp->channel_plan, rp->version, rp->curstomer_id); 1119 } 1120 #endif 1121 1122 static void 1123 urtwn_read_rom(struct urtwn_softc *sc) 1124 { 1125 struct ieee80211com *ic = &sc->sc_ic; 1126 struct r92c_rom *rom = &sc->rom; 1127 1128 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1129 1130 /* Read full ROM image. */ 1131 urtwn_efuse_read(sc); 1132 #ifdef URTWN_DEBUG 1133 if (urtwn_debug & DBG_REG) 1134 urtwn_dump_rom(sc, rom); 1135 #endif 1136 1137 /* XXX Weird but this is what the vendor driver does. */ 1138 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1139 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1140 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1141 1142 DPRINTFN(DBG_INIT, 1143 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1144 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1145 sc->board_type, sc->regulatory)); 1146 1147 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1148 } 1149 1150 static int 1151 urtwn_media_change(struct ifnet *ifp) 1152 { 1153 #ifdef URTWN_DEBUG 1154 struct urtwn_softc *sc = ifp->if_softc; 1155 #endif 1156 int error; 1157 1158 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1159 1160 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1161 return (error); 1162 1163 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1164 (IFF_UP | IFF_RUNNING)) { 1165 urtwn_init(ifp); 1166 } 1167 return (0); 1168 } 1169 1170 /* 1171 * Initialize rate adaptation in firmware. 1172 */ 1173 static int 1174 urtwn_ra_init(struct urtwn_softc *sc) 1175 { 1176 static const uint8_t map[] = { 1177 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1178 }; 1179 struct ieee80211com *ic = &sc->sc_ic; 1180 struct ieee80211_node *ni = ic->ic_bss; 1181 struct ieee80211_rateset *rs = &ni->ni_rates; 1182 struct r92c_fw_cmd_macid_cfg cmd; 1183 uint32_t rates, basicrates; 1184 uint32_t mask; 1185 uint8_t mode; 1186 int maxrate, maxbasicrate, error, i, j; 1187 1188 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1189 1190 /* Get normal and basic rates mask. */ 1191 rates = basicrates = 0; 1192 maxrate = maxbasicrate = 0; 1193 for (i = 0; i < rs->rs_nrates; i++) { 1194 /* Convert 802.11 rate to HW rate index. */ 1195 for (j = 0; j < (int)__arraycount(map); j++) { 1196 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1197 break; 1198 } 1199 } 1200 if (j == __arraycount(map)) { 1201 /* Unknown rate, skip. */ 1202 continue; 1203 } 1204 1205 rates |= 1U << j; 1206 if (j > maxrate) { 1207 maxrate = j; 1208 } 1209 1210 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1211 basicrates |= 1U << j; 1212 if (j > maxbasicrate) { 1213 maxbasicrate = j; 1214 } 1215 } 1216 } 1217 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1218 mode = R92C_RAID_11B; 1219 } else { 1220 mode = R92C_RAID_11BG; 1221 } 1222 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1223 "maxrate=%x, maxbasicrate=%x\n", 1224 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1225 maxrate, maxbasicrate)); 1226 if (basicrates == 0) { 1227 basicrates |= 1; /* add 1Mbps */ 1228 } 1229 1230 /* Set rates mask for group addressed frames. */ 1231 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1232 mask = (mode << 28) | basicrates; 1233 cmd.mask[0] = (uint8_t)mask; 1234 cmd.mask[1] = (uint8_t)(mask >> 8); 1235 cmd.mask[2] = (uint8_t)(mask >> 16); 1236 cmd.mask[3] = (uint8_t)(mask >> 24); 1237 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1238 if (error != 0) { 1239 aprint_error_dev(sc->sc_dev, 1240 "could not add broadcast station\n"); 1241 return (error); 1242 } 1243 /* Set initial MRR rate. */ 1244 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", 1245 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1246 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1247 1248 /* Set rates mask for unicast frames. */ 1249 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1250 mask = (mode << 28) | rates; 1251 cmd.mask[0] = (uint8_t)mask; 1252 cmd.mask[1] = (uint8_t)(mask >> 8); 1253 cmd.mask[2] = (uint8_t)(mask >> 16); 1254 cmd.mask[3] = (uint8_t)(mask >> 24); 1255 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1256 if (error != 0) { 1257 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1258 return (error); 1259 } 1260 /* Set initial MRR rate. */ 1261 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), 1262 __func__, maxrate)); 1263 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1264 1265 /* Indicate highest supported rate. */ 1266 ni->ni_txrate = rs->rs_nrates - 1; 1267 1268 return (0); 1269 } 1270 1271 static int 1272 urtwn_get_nettype(struct urtwn_softc *sc) 1273 { 1274 struct ieee80211com *ic = &sc->sc_ic; 1275 int type; 1276 1277 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1278 1279 switch (ic->ic_opmode) { 1280 case IEEE80211_M_STA: 1281 type = R92C_CR_NETTYPE_INFRA; 1282 break; 1283 1284 case IEEE80211_M_IBSS: 1285 type = R92C_CR_NETTYPE_ADHOC; 1286 break; 1287 1288 default: 1289 type = R92C_CR_NETTYPE_NOLINK; 1290 break; 1291 } 1292 1293 return (type); 1294 } 1295 1296 static void 1297 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1298 { 1299 uint8_t reg; 1300 1301 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1302 __func__, type)); 1303 1304 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1305 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1306 } 1307 1308 static void 1309 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1310 { 1311 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1312 uint64_t tsf; 1313 1314 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1315 1316 /* Enable TSF synchronization. */ 1317 urtwn_write_1(sc, R92C_BCN_CTRL, 1318 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1319 1320 /* Correct TSF */ 1321 urtwn_write_1(sc, R92C_BCN_CTRL, 1322 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1323 1324 /* Set initial TSF. */ 1325 tsf = ni->ni_tstamp.tsf; 1326 tsf = le64toh(tsf); 1327 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1328 tsf -= IEEE80211_DUR_TU; 1329 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1330 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1331 1332 urtwn_write_1(sc, R92C_BCN_CTRL, 1333 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1334 } 1335 1336 static void 1337 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1338 { 1339 uint8_t reg; 1340 1341 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1342 __func__, led, on)); 1343 1344 if (led == URTWN_LED_LINK) { 1345 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1346 if (!on) { 1347 reg |= R92C_LEDCFG0_DIS; 1348 } 1349 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1350 sc->ledlink = on; /* Save LED state. */ 1351 } 1352 } 1353 1354 static void 1355 urtwn_calib_to(void *arg) 1356 { 1357 struct urtwn_softc *sc = arg; 1358 1359 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1360 1361 if (sc->sc_dying) 1362 return; 1363 1364 /* Do it in a process context. */ 1365 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1366 } 1367 1368 /* ARGSUSED */ 1369 static void 1370 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1371 { 1372 struct r92c_fw_cmd_rssi cmd; 1373 1374 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1375 1376 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1377 goto restart_timer; 1378 1379 if (sc->avg_pwdb != -1) { 1380 /* Indicate Rx signal strength to FW for rate adaptation. */ 1381 memset(&cmd, 0, sizeof(cmd)); 1382 cmd.macid = 0; /* BSS. */ 1383 cmd.pwdb = sc->avg_pwdb; 1384 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1385 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1386 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1387 } 1388 1389 /* Do temperature compensation. */ 1390 urtwn_temp_calib(sc); 1391 1392 restart_timer: 1393 if (!sc->sc_dying) { 1394 /* Restart calibration timer. */ 1395 callout_schedule(&sc->sc_calib_to, hz); 1396 } 1397 } 1398 1399 static void 1400 urtwn_next_scan(void *arg) 1401 { 1402 struct urtwn_softc *sc = arg; 1403 1404 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1405 1406 if (sc->sc_dying) 1407 return; 1408 1409 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1410 ieee80211_next_scan(&sc->sc_ic); 1411 } 1412 1413 static int 1414 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1415 { 1416 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1417 struct urtwn_cmd_newstate cmd; 1418 1419 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1420 device_xname(sc->sc_dev), __func__, 1421 ieee80211_state_name[nstate], nstate, arg)); 1422 1423 callout_stop(&sc->sc_scan_to); 1424 callout_stop(&sc->sc_calib_to); 1425 1426 /* Do it in a process context. */ 1427 cmd.state = nstate; 1428 cmd.arg = arg; 1429 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1430 return (0); 1431 } 1432 1433 static void 1434 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1435 { 1436 struct urtwn_cmd_newstate *cmd = arg; 1437 struct ieee80211com *ic = &sc->sc_ic; 1438 struct ieee80211_node *ni; 1439 enum ieee80211_state ostate = ic->ic_state; 1440 enum ieee80211_state nstate = cmd->state; 1441 uint32_t reg; 1442 uint8_t sifs_time; 1443 int s; 1444 1445 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1446 device_xname(sc->sc_dev), __func__, 1447 ieee80211_state_name[ostate], ostate, 1448 ieee80211_state_name[nstate], nstate)); 1449 1450 s = splnet(); 1451 1452 switch (ostate) { 1453 case IEEE80211_S_INIT: 1454 break; 1455 1456 case IEEE80211_S_SCAN: 1457 if (nstate != IEEE80211_S_SCAN) { 1458 /* 1459 * End of scanning 1460 */ 1461 /* flush 4-AC Queue after site_survey */ 1462 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1463 1464 /* Allow Rx from our BSSID only. */ 1465 urtwn_write_4(sc, R92C_RCR, 1466 urtwn_read_4(sc, R92C_RCR) | 1467 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1468 } 1469 break; 1470 1471 case IEEE80211_S_AUTH: 1472 case IEEE80211_S_ASSOC: 1473 break; 1474 1475 case IEEE80211_S_RUN: 1476 /* Turn link LED off. */ 1477 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1478 1479 /* Set media status to 'No Link'. */ 1480 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1481 1482 /* Stop Rx of data frames. */ 1483 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1484 1485 /* Reset TSF. */ 1486 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1487 1488 /* Disable TSF synchronization. */ 1489 urtwn_write_1(sc, R92C_BCN_CTRL, 1490 urtwn_read_1(sc, R92C_BCN_CTRL) | 1491 R92C_BCN_CTRL_DIS_TSF_UDT0); 1492 1493 /* Back to 20MHz mode */ 1494 urtwn_set_chan(sc, ic->ic_bss->ni_chan, 1495 IEEE80211_HTINFO_2NDCHAN_NONE); 1496 1497 if (ic->ic_opmode == IEEE80211_M_IBSS || 1498 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1499 /* Stop BCN */ 1500 urtwn_write_1(sc, R92C_BCN_CTRL, 1501 urtwn_read_1(sc, R92C_BCN_CTRL) & 1502 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1503 } 1504 1505 /* Reset EDCA parameters. */ 1506 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1507 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1508 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1509 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1510 1511 /* flush all cam entries */ 1512 urtwn_cam_init(sc); 1513 break; 1514 } 1515 1516 switch (nstate) { 1517 case IEEE80211_S_INIT: 1518 /* Turn link LED off. */ 1519 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1520 break; 1521 1522 case IEEE80211_S_SCAN: 1523 if (ostate != IEEE80211_S_SCAN) { 1524 /* 1525 * Begin of scanning 1526 */ 1527 1528 /* Set gain for scanning. */ 1529 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1530 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1531 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1532 1533 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1534 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1535 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1536 1537 /* Set media status to 'No Link'. */ 1538 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1539 1540 /* Allow Rx from any BSSID. */ 1541 urtwn_write_4(sc, R92C_RCR, 1542 urtwn_read_4(sc, R92C_RCR) & 1543 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1544 1545 /* Stop Rx of data frames. */ 1546 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1547 1548 /* Disable update TSF */ 1549 urtwn_write_1(sc, R92C_BCN_CTRL, 1550 urtwn_read_1(sc, R92C_BCN_CTRL) | 1551 R92C_BCN_CTRL_DIS_TSF_UDT0); 1552 } 1553 1554 /* Make link LED blink during scan. */ 1555 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1556 1557 /* Pause AC Tx queues. */ 1558 urtwn_write_1(sc, R92C_TXPAUSE, 1559 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1560 1561 urtwn_set_chan(sc, ic->ic_curchan, 1562 IEEE80211_HTINFO_2NDCHAN_NONE); 1563 1564 /* Start periodic scan. */ 1565 if (!sc->sc_dying) 1566 callout_schedule(&sc->sc_scan_to, hz / 5); 1567 break; 1568 1569 case IEEE80211_S_AUTH: 1570 /* Set initial gain under link. */ 1571 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1572 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1573 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1574 1575 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1576 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1577 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1578 1579 /* Set media status to 'No Link'. */ 1580 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1581 1582 /* Allow Rx from any BSSID. */ 1583 urtwn_write_4(sc, R92C_RCR, 1584 urtwn_read_4(sc, R92C_RCR) & 1585 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1586 1587 urtwn_set_chan(sc, ic->ic_curchan, 1588 IEEE80211_HTINFO_2NDCHAN_NONE); 1589 break; 1590 1591 case IEEE80211_S_ASSOC: 1592 break; 1593 1594 case IEEE80211_S_RUN: 1595 ni = ic->ic_bss; 1596 1597 /* XXX: Set 20MHz mode */ 1598 urtwn_set_chan(sc, ic->ic_curchan, 1599 IEEE80211_HTINFO_2NDCHAN_NONE); 1600 1601 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1602 /* Back to 20MHz mode */ 1603 urtwn_set_chan(sc, ic->ic_ibss_chan, 1604 IEEE80211_HTINFO_2NDCHAN_NONE); 1605 1606 /* Enable Rx of data frames. */ 1607 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1608 1609 /* Turn link LED on. */ 1610 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1611 break; 1612 } 1613 1614 /* Set media status to 'Associated'. */ 1615 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1616 1617 /* Set BSSID. */ 1618 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1619 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1620 1621 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1622 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1623 } else { 1624 /* 802.11b/g */ 1625 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1626 } 1627 1628 /* Enable Rx of data frames. */ 1629 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1630 1631 /* Set beacon interval. */ 1632 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1633 1634 if (ic->ic_opmode == IEEE80211_M_STA) { 1635 /* Allow Rx from our BSSID only. */ 1636 urtwn_write_4(sc, R92C_RCR, 1637 urtwn_read_4(sc, R92C_RCR) | 1638 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1639 1640 /* Enable TSF synchronization. */ 1641 urtwn_tsf_sync_enable(sc); 1642 } 1643 1644 sifs_time = 10; 1645 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1646 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1647 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1648 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1649 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1650 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1651 1652 /* Intialize rate adaptation. */ 1653 urtwn_ra_init(sc); 1654 1655 /* Turn link LED on. */ 1656 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1657 1658 /* Reset average RSSI. */ 1659 sc->avg_pwdb = -1; 1660 1661 /* Reset temperature calibration state machine. */ 1662 sc->thcal_state = 0; 1663 sc->thcal_lctemp = 0; 1664 1665 /* Start periodic calibration. */ 1666 if (!sc->sc_dying) 1667 callout_schedule(&sc->sc_calib_to, hz); 1668 break; 1669 } 1670 1671 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1672 1673 splx(s); 1674 } 1675 1676 static int 1677 urtwn_wme_update(struct ieee80211com *ic) 1678 { 1679 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1680 1681 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1682 1683 /* don't override default WME values if WME is not actually enabled */ 1684 if (!(ic->ic_flags & IEEE80211_F_WME)) 1685 return (0); 1686 1687 /* Do it in a process context. */ 1688 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1689 return (0); 1690 } 1691 1692 static void 1693 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1694 { 1695 static const uint16_t ac2reg[WME_NUM_AC] = { 1696 R92C_EDCA_BE_PARAM, 1697 R92C_EDCA_BK_PARAM, 1698 R92C_EDCA_VI_PARAM, 1699 R92C_EDCA_VO_PARAM 1700 }; 1701 struct ieee80211com *ic = &sc->sc_ic; 1702 const struct wmeParams *wmep; 1703 int ac, aifs, slottime; 1704 int s; 1705 1706 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1707 __func__)); 1708 1709 s = splnet(); 1710 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1711 for (ac = 0; ac < WME_NUM_AC; ac++) { 1712 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1713 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1714 aifs = wmep->wmep_aifsn * slottime + 10; 1715 urtwn_write_4(sc, ac2reg[ac], 1716 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1717 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1718 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1719 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1720 } 1721 splx(s); 1722 } 1723 1724 static void 1725 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1726 { 1727 int pwdb; 1728 1729 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1730 device_xname(sc->sc_dev), __func__, rate, rssi)); 1731 1732 /* Convert antenna signal to percentage. */ 1733 if (rssi <= -100 || rssi >= 20) 1734 pwdb = 0; 1735 else if (rssi >= 0) 1736 pwdb = 100; 1737 else 1738 pwdb = 100 + rssi; 1739 if (rate <= 3) { 1740 /* CCK gain is smaller than OFDM/MCS gain. */ 1741 pwdb += 6; 1742 if (pwdb > 100) 1743 pwdb = 100; 1744 if (pwdb <= 14) 1745 pwdb -= 4; 1746 else if (pwdb <= 26) 1747 pwdb -= 8; 1748 else if (pwdb <= 34) 1749 pwdb -= 6; 1750 else if (pwdb <= 42) 1751 pwdb -= 2; 1752 } 1753 if (sc->avg_pwdb == -1) /* Init. */ 1754 sc->avg_pwdb = pwdb; 1755 else if (sc->avg_pwdb < pwdb) 1756 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1757 else 1758 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1759 1760 DPRINTFN(DBG_RF, ("%s: %s: PWDB=%d EMA=%d\n", device_xname(sc->sc_dev), 1761 __func__, pwdb, sc->avg_pwdb)); 1762 } 1763 1764 static int8_t 1765 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1766 { 1767 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1768 struct r92c_rx_phystat *phy; 1769 struct r92c_rx_cck *cck; 1770 uint8_t rpt; 1771 int8_t rssi; 1772 1773 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1774 __func__, rate)); 1775 1776 if (rate <= 3) { 1777 cck = (struct r92c_rx_cck *)physt; 1778 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1779 rpt = (cck->agc_rpt >> 5) & 0x3; 1780 rssi = (cck->agc_rpt & 0x1f) << 1; 1781 } else { 1782 rpt = (cck->agc_rpt >> 6) & 0x3; 1783 rssi = cck->agc_rpt & 0x3e; 1784 } 1785 rssi = cckoff[rpt] - rssi; 1786 } else { /* OFDM/HT. */ 1787 phy = (struct r92c_rx_phystat *)physt; 1788 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1789 } 1790 return (rssi); 1791 } 1792 1793 static void 1794 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1795 { 1796 struct ieee80211com *ic = &sc->sc_ic; 1797 struct ifnet *ifp = ic->ic_ifp; 1798 struct ieee80211_frame *wh; 1799 struct ieee80211_node *ni; 1800 struct r92c_rx_stat *stat; 1801 uint32_t rxdw0, rxdw3; 1802 struct mbuf *m; 1803 uint8_t rate; 1804 int8_t rssi = 0; 1805 int s, infosz; 1806 1807 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1808 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1809 1810 stat = (struct r92c_rx_stat *)buf; 1811 rxdw0 = le32toh(stat->rxdw0); 1812 rxdw3 = le32toh(stat->rxdw3); 1813 1814 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1815 /* 1816 * This should not happen since we setup our Rx filter 1817 * to not receive these frames. 1818 */ 1819 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1820 device_xname(sc->sc_dev), __func__)); 1821 ifp->if_ierrors++; 1822 return; 1823 } 1824 if (__predict_false(pktlen < (int)sizeof(*wh))) { 1825 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1826 device_xname(sc->sc_dev), __func__, pktlen)); 1827 ic->ic_stats.is_rx_tooshort++; 1828 ifp->if_ierrors++; 1829 return; 1830 } 1831 if (__predict_false(pktlen > MCLBYTES)) { 1832 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1833 device_xname(sc->sc_dev), __func__, pktlen)); 1834 ifp->if_ierrors++; 1835 return; 1836 } 1837 1838 rate = MS(rxdw3, R92C_RXDW3_RATE); 1839 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1840 1841 /* Get RSSI from PHY status descriptor if present. */ 1842 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1843 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1844 /* Update our average RSSI. */ 1845 urtwn_update_avgrssi(sc, rate, rssi); 1846 } 1847 1848 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1849 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1850 1851 MGETHDR(m, M_DONTWAIT, MT_DATA); 1852 if (__predict_false(m == NULL)) { 1853 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1854 ic->ic_stats.is_rx_nobuf++; 1855 ifp->if_ierrors++; 1856 return; 1857 } 1858 if (pktlen > (int)MHLEN) { 1859 MCLGET(m, M_DONTWAIT); 1860 if (__predict_false(!(m->m_flags & M_EXT))) { 1861 aprint_error_dev(sc->sc_dev, 1862 "couldn't allocate rx mbuf cluster\n"); 1863 m_freem(m); 1864 ic->ic_stats.is_rx_nobuf++; 1865 ifp->if_ierrors++; 1866 return; 1867 } 1868 } 1869 1870 /* Finalize mbuf. */ 1871 m->m_pkthdr.rcvif = ifp; 1872 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1873 memcpy(mtod(m, uint8_t *), wh, pktlen); 1874 m->m_pkthdr.len = m->m_len = pktlen; 1875 1876 s = splnet(); 1877 if (__predict_false(sc->sc_drvbpf != NULL)) { 1878 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1879 1880 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1881 if (!(rxdw3 & R92C_RXDW3_HT)) { 1882 switch (rate) { 1883 /* CCK. */ 1884 case 0: tap->wr_rate = 2; break; 1885 case 1: tap->wr_rate = 4; break; 1886 case 2: tap->wr_rate = 11; break; 1887 case 3: tap->wr_rate = 22; break; 1888 /* OFDM. */ 1889 case 4: tap->wr_rate = 12; break; 1890 case 5: tap->wr_rate = 18; break; 1891 case 6: tap->wr_rate = 24; break; 1892 case 7: tap->wr_rate = 36; break; 1893 case 8: tap->wr_rate = 48; break; 1894 case 9: tap->wr_rate = 72; break; 1895 case 10: tap->wr_rate = 96; break; 1896 case 11: tap->wr_rate = 108; break; 1897 } 1898 } else if (rate >= 12) { /* MCS0~15. */ 1899 /* Bit 7 set means HT MCS instead of rate. */ 1900 tap->wr_rate = 0x80 | (rate - 12); 1901 } 1902 tap->wr_dbm_antsignal = rssi; 1903 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1904 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1905 1906 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1907 } 1908 1909 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1910 1911 /* push the frame up to the 802.11 stack */ 1912 ieee80211_input(ic, m, ni, rssi, 0); 1913 1914 /* Node is no longer needed. */ 1915 ieee80211_free_node(ni); 1916 1917 splx(s); 1918 } 1919 1920 static void 1921 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1922 { 1923 struct urtwn_rx_data *data = priv; 1924 struct urtwn_softc *sc = data->sc; 1925 struct r92c_rx_stat *stat; 1926 uint32_t rxdw0; 1927 uint8_t *buf; 1928 int len, totlen, pktlen, infosz, npkts; 1929 1930 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 1931 device_xname(sc->sc_dev), __func__, status)); 1932 1933 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1934 if (status == USBD_STALLED) 1935 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1936 else if (status != USBD_CANCELLED) 1937 goto resubmit; 1938 return; 1939 } 1940 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1941 1942 if (__predict_false(len < (int)sizeof(*stat))) { 1943 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 1944 device_xname(sc->sc_dev), __func__, len)); 1945 goto resubmit; 1946 } 1947 buf = data->buf; 1948 1949 /* Get the number of encapsulated frames. */ 1950 stat = (struct r92c_rx_stat *)buf; 1951 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 1952 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 1953 device_xname(sc->sc_dev), __func__, npkts)); 1954 1955 /* Process all of them. */ 1956 while (npkts-- > 0) { 1957 if (__predict_false(len < (int)sizeof(*stat))) { 1958 DPRINTFN(DBG_RX, 1959 ("%s: %s: len(%d) is short than header\n", 1960 device_xname(sc->sc_dev), __func__, len)); 1961 break; 1962 } 1963 stat = (struct r92c_rx_stat *)buf; 1964 rxdw0 = le32toh(stat->rxdw0); 1965 1966 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1967 if (__predict_false(pktlen == 0)) { 1968 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 1969 device_xname(sc->sc_dev), __func__)); 1970 break; 1971 } 1972 1973 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1974 1975 /* Make sure everything fits in xfer. */ 1976 totlen = sizeof(*stat) + infosz + pktlen; 1977 if (__predict_false(totlen > len)) { 1978 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 1979 device_xname(sc->sc_dev), __func__, totlen, 1980 (int)sizeof(*stat), infosz, pktlen, len)); 1981 break; 1982 } 1983 1984 /* Process 802.11 frame. */ 1985 urtwn_rx_frame(sc, buf, pktlen); 1986 1987 /* Next chunk is 128-byte aligned. */ 1988 totlen = roundup2(totlen, 128); 1989 buf += totlen; 1990 len -= totlen; 1991 } 1992 1993 resubmit: 1994 /* Setup a new transfer. */ 1995 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1996 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1997 (void)usbd_transfer(xfer); 1998 } 1999 2000 static void 2001 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2002 { 2003 struct urtwn_tx_data *data = priv; 2004 struct urtwn_softc *sc = data->sc; 2005 struct ifnet *ifp = &sc->sc_if; 2006 int s; 2007 2008 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2009 device_xname(sc->sc_dev), __func__, status)); 2010 2011 mutex_enter(&sc->sc_tx_mtx); 2012 /* Put this Tx buffer back to our free list. */ 2013 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2014 mutex_exit(&sc->sc_tx_mtx); 2015 2016 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2017 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2018 if (status == USBD_STALLED) 2019 usbd_clear_endpoint_stall_async(data->pipe); 2020 ifp->if_oerrors++; 2021 } 2022 return; 2023 } 2024 2025 ifp->if_opackets++; 2026 2027 s = splnet(); 2028 sc->tx_timer = 0; 2029 ifp->if_flags &= ~IFF_OACTIVE; 2030 splx(s); 2031 2032 urtwn_start(ifp); 2033 } 2034 2035 static int 2036 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2037 { 2038 struct ieee80211com *ic = &sc->sc_ic; 2039 struct ieee80211_frame *wh; 2040 struct ieee80211_key *k = NULL; 2041 struct urtwn_tx_data *data; 2042 struct r92c_tx_desc *txd; 2043 usbd_pipe_handle pipe; 2044 uint16_t seq, sum; 2045 uint8_t raid, type, tid, qid; 2046 int i, s, hasqos, xferlen, padsize, error; 2047 2048 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2049 2050 wh = mtod(m, struct ieee80211_frame *); 2051 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2052 2053 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2054 k = ieee80211_crypto_encap(ic, ni, m); 2055 if (k == NULL) { 2056 m_freem(m); 2057 return (ENOBUFS); 2058 } 2059 /* packet header may have moved, reset our local pointer */ 2060 wh = mtod(m, struct ieee80211_frame *); 2061 } 2062 2063 if (__predict_false(sc->sc_drvbpf != NULL)) { 2064 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2065 2066 tap->wt_flags = 0; 2067 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2068 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2069 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2070 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2071 2072 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2073 } 2074 2075 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2076 /* data frames in 11n mode */ 2077 struct ieee80211_qosframe *qwh = (void *)wh; 2078 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2079 qid = TID_TO_WME_AC(tid); 2080 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2081 /* Use AC_VO for management frames. */ 2082 qid = WME_AC_VO; 2083 tid = 0; /* compiler happy */ 2084 } else { 2085 /* non-qos data frames */ 2086 tid = R92C_TXDW1_QSEL_BE; 2087 qid = WME_AC_BE; 2088 } 2089 2090 /* Get the USB pipe to use for this AC. */ 2091 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2092 2093 /* Grab a Tx buffer from our free list. */ 2094 mutex_enter(&sc->sc_tx_mtx); 2095 data = TAILQ_FIRST(&sc->tx_free_list); 2096 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2097 mutex_exit(&sc->sc_tx_mtx); 2098 2099 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2100 padsize = 8; 2101 else 2102 padsize = 0; 2103 2104 /* Fill Tx descriptor. */ 2105 txd = (struct r92c_tx_desc *)data->buf; 2106 memset(txd, 0, sizeof(*txd) + padsize); 2107 2108 txd->txdw0 |= htole32( 2109 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2110 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2111 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2112 2113 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2114 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2115 2116 /* fix pad field */ 2117 if (padsize > 0) { 2118 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", 2119 device_xname(sc->sc_dev), __func__, padsize)); 2120 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2121 } 2122 2123 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2124 type == IEEE80211_FC0_TYPE_DATA) { 2125 if (ic->ic_curmode == IEEE80211_MODE_11B) 2126 raid = R92C_RAID_11B; 2127 else 2128 raid = R92C_RAID_11BG; 2129 DPRINTFN(DBG_TX, 2130 ("%s: %s: data packet: tid=%d, raid=%d\n", 2131 device_xname(sc->sc_dev), __func__, tid, raid)); 2132 2133 txd->txdw1 |= htole32( 2134 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2135 SM(R92C_TXDW1_QSEL, tid) | 2136 SM(R92C_TXDW1_RAID, raid) | 2137 R92C_TXDW1_AGGBK); 2138 2139 if (hasqos) { 2140 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2141 } 2142 2143 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2144 /* for 11g */ 2145 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2146 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2147 R92C_TXDW4_HWRTSEN); 2148 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2149 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2150 R92C_TXDW4_HWRTSEN); 2151 } 2152 } 2153 /* Send RTS at OFDM24. */ 2154 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2155 txd->txdw5 |= htole32(0x0001ff00); 2156 /* Send data at OFDM54. */ 2157 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2158 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2159 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2160 device_xname(sc->sc_dev), __func__)); 2161 txd->txdw1 |= htole32( 2162 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2163 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2164 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2165 2166 /* Force CCK1. */ 2167 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2168 /* Use 1Mbps */ 2169 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2170 } else { 2171 /* broadcast or multicast packets */ 2172 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2173 device_xname(sc->sc_dev), __func__)); 2174 txd->txdw1 |= htole32( 2175 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2176 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2177 2178 /* Force CCK1. */ 2179 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2180 /* Use 1Mbps */ 2181 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2182 } 2183 2184 /* Set sequence number */ 2185 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2186 txd->txdseq |= htole16(seq); 2187 2188 if (!hasqos) { 2189 /* Use HW sequence numbering for non-QoS frames. */ 2190 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2191 txd->txdseq |= htole16(0x8000); /* WTF? */ 2192 } 2193 2194 /* Compute Tx descriptor checksum. */ 2195 sum = 0; 2196 for (i = 0; i < (int)sizeof(*txd) / 2; i++) 2197 sum ^= ((uint16_t *)txd)[i]; 2198 txd->txdsum = sum; /* NB: already little endian. */ 2199 2200 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2201 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2202 m_freem(m); 2203 2204 s = splnet(); 2205 data->pipe = pipe; 2206 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2207 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2208 urtwn_txeof); 2209 error = usbd_transfer(data->xfer); 2210 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2211 error != USBD_IN_PROGRESS)) { 2212 splx(s); 2213 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2214 device_xname(sc->sc_dev), __func__, error)); 2215 mutex_enter(&sc->sc_tx_mtx); 2216 /* Put this Tx buffer back to our free list. */ 2217 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2218 mutex_exit(&sc->sc_tx_mtx); 2219 return (error); 2220 } 2221 splx(s); 2222 ieee80211_free_node(ni); 2223 return (0); 2224 } 2225 2226 static void 2227 urtwn_start(struct ifnet *ifp) 2228 { 2229 struct urtwn_softc *sc = ifp->if_softc; 2230 struct ieee80211com *ic = &sc->sc_ic; 2231 struct ether_header *eh; 2232 struct ieee80211_node *ni; 2233 struct mbuf *m; 2234 2235 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2236 2237 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2238 return; 2239 2240 for (;;) { 2241 mutex_enter(&sc->sc_tx_mtx); 2242 if (TAILQ_EMPTY(&sc->tx_free_list)) { 2243 mutex_exit(&sc->sc_tx_mtx); 2244 ifp->if_flags |= IFF_OACTIVE; 2245 break; 2246 } 2247 mutex_exit(&sc->sc_tx_mtx); 2248 2249 /* Send pending management frames first. */ 2250 IF_DEQUEUE(&ic->ic_mgtq, m); 2251 if (m != NULL) { 2252 ni = (void *)m->m_pkthdr.rcvif; 2253 m->m_pkthdr.rcvif = NULL; 2254 goto sendit; 2255 } 2256 if (ic->ic_state != IEEE80211_S_RUN) 2257 break; 2258 2259 /* Encapsulate and send data frames. */ 2260 IFQ_DEQUEUE(&ifp->if_snd, m); 2261 if (m == NULL) 2262 break; 2263 if (m->m_len < (int)sizeof(*eh) && 2264 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2265 ifp->if_oerrors++; 2266 continue; 2267 } 2268 eh = mtod(m, struct ether_header *); 2269 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2270 if (ni == NULL) { 2271 m_freem(m); 2272 ifp->if_oerrors++; 2273 continue; 2274 } 2275 2276 bpf_mtap(ifp, m); 2277 2278 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2279 ieee80211_free_node(ni); 2280 ifp->if_oerrors++; 2281 continue; 2282 } 2283 sendit: 2284 bpf_mtap3(ic->ic_rawbpf, m); 2285 2286 if (urtwn_tx(sc, m, ni) != 0) { 2287 ieee80211_free_node(ni); 2288 ifp->if_oerrors++; 2289 continue; 2290 } 2291 2292 sc->tx_timer = 5; 2293 ifp->if_timer = 1; 2294 } 2295 } 2296 2297 static void 2298 urtwn_watchdog(struct ifnet *ifp) 2299 { 2300 struct urtwn_softc *sc = ifp->if_softc; 2301 2302 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2303 2304 ifp->if_timer = 0; 2305 2306 if (sc->tx_timer > 0) { 2307 if (--sc->tx_timer == 0) { 2308 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2309 /* urtwn_init(ifp); XXX needs a process context! */ 2310 ifp->if_oerrors++; 2311 return; 2312 } 2313 ifp->if_timer = 1; 2314 } 2315 ieee80211_watchdog(&sc->sc_ic); 2316 } 2317 2318 static int 2319 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2320 { 2321 struct urtwn_softc *sc = ifp->if_softc; 2322 struct ieee80211com *ic = &sc->sc_ic; 2323 struct ifaddr *ifa; 2324 int s, error = 0; 2325 2326 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2327 device_xname(sc->sc_dev), __func__, cmd, data)); 2328 2329 s = splnet(); 2330 2331 switch (cmd) { 2332 case SIOCSIFADDR: 2333 ifa = (struct ifaddr *)data; 2334 ifp->if_flags |= IFF_UP; 2335 #ifdef INET 2336 if (ifa->ifa_addr->sa_family == AF_INET) 2337 arp_ifinit(&ic->ic_ac, ifa); 2338 #endif 2339 /*FALLTHROUGH*/ 2340 case SIOCSIFFLAGS: 2341 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2342 break; 2343 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2344 case IFF_UP|IFF_RUNNING: 2345 break; 2346 case IFF_UP: 2347 urtwn_init(ifp); 2348 break; 2349 case IFF_RUNNING: 2350 urtwn_stop(ifp, 1); 2351 break; 2352 case 0: 2353 break; 2354 } 2355 break; 2356 2357 case SIOCADDMULTI: 2358 case SIOCDELMULTI: 2359 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2360 /* setup multicast filter, etc */ 2361 error = 0; 2362 } 2363 break; 2364 2365 case SIOCS80211CHANNEL: 2366 error = ieee80211_ioctl(ic, cmd, data); 2367 if (error == ENETRESET && 2368 ic->ic_opmode == IEEE80211_M_MONITOR) { 2369 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2370 (IFF_UP | IFF_RUNNING)) { 2371 urtwn_set_chan(sc, ic->ic_ibss_chan, 2372 IEEE80211_HTINFO_2NDCHAN_NONE); 2373 } 2374 error = 0; 2375 } 2376 break; 2377 2378 default: 2379 error = ieee80211_ioctl(ic, cmd, data); 2380 break; 2381 } 2382 if (error == ENETRESET) { 2383 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2384 (IFF_UP | IFF_RUNNING)) { 2385 urtwn_init(ifp); 2386 } 2387 error = 0; 2388 } 2389 2390 splx(s); 2391 2392 return (error); 2393 } 2394 2395 static int 2396 urtwn_power_on(struct urtwn_softc *sc) 2397 { 2398 uint32_t reg; 2399 int ntries; 2400 2401 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2402 2403 /* Wait for autoload done bit. */ 2404 for (ntries = 0; ntries < 1000; ntries++) { 2405 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2406 break; 2407 DELAY(5); 2408 } 2409 if (ntries == 1000) { 2410 aprint_error_dev(sc->sc_dev, 2411 "timeout waiting for chip autoload\n"); 2412 return (ETIMEDOUT); 2413 } 2414 2415 /* Unlock ISO/CLK/Power control register. */ 2416 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2417 /* Move SPS into PWM mode. */ 2418 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2419 DELAY(100); 2420 2421 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2422 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2423 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2424 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2425 DELAY(100); 2426 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2427 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2428 ~R92C_SYS_ISO_CTRL_MD2PP); 2429 } 2430 2431 /* Auto enable WLAN. */ 2432 urtwn_write_2(sc, R92C_APS_FSMCO, 2433 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2434 for (ntries = 0; ntries < 1000; ntries++) { 2435 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2436 R92C_APS_FSMCO_APFM_ONMAC)) 2437 break; 2438 DELAY(5); 2439 } 2440 if (ntries == 1000) { 2441 aprint_error_dev(sc->sc_dev, 2442 "timeout waiting for MAC auto ON\n"); 2443 return (ETIMEDOUT); 2444 } 2445 2446 /* Enable radio, GPIO and LED functions. */ 2447 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2448 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2449 urtwn_write_2(sc, R92C_APS_FSMCO, 2450 R92C_APS_FSMCO_AFSM_HSUS | 2451 R92C_APS_FSMCO_PDN_EN | 2452 R92C_APS_FSMCO_PFM_ALDN); 2453 2454 /* Release RF digital isolation. */ 2455 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2456 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2457 2458 /* Initialize MAC. */ 2459 urtwn_write_1(sc, R92C_APSD_CTRL, 2460 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2461 for (ntries = 0; ntries < 200; ntries++) { 2462 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2463 R92C_APSD_CTRL_OFF_STATUS)) 2464 break; 2465 DELAY(5); 2466 } 2467 if (ntries == 200) { 2468 aprint_error_dev(sc->sc_dev, 2469 "timeout waiting for MAC initialization\n"); 2470 return (ETIMEDOUT); 2471 } 2472 2473 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2474 reg = urtwn_read_2(sc, R92C_CR); 2475 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2476 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2477 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2478 R92C_CR_ENSEC; 2479 urtwn_write_2(sc, R92C_CR, reg); 2480 2481 urtwn_write_1(sc, 0xfe10, 0x19); 2482 return (0); 2483 } 2484 2485 static int 2486 urtwn_llt_init(struct urtwn_softc *sc) 2487 { 2488 int i, error; 2489 2490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2491 2492 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2493 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2494 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2495 return (error); 2496 } 2497 /* NB: 0xff indicates end-of-list. */ 2498 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2499 return (error); 2500 /* 2501 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2502 * as ring buffer. 2503 */ 2504 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2505 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2506 return (error); 2507 } 2508 /* Make the last page point to the beginning of the ring buffer. */ 2509 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2510 return (error); 2511 } 2512 2513 static void 2514 urtwn_fw_reset(struct urtwn_softc *sc) 2515 { 2516 uint16_t reg; 2517 int ntries; 2518 2519 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2520 2521 /* Tell 8051 to reset itself. */ 2522 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2523 2524 /* Wait until 8051 resets by itself. */ 2525 for (ntries = 0; ntries < 100; ntries++) { 2526 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2527 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2528 return; 2529 DELAY(50); 2530 } 2531 /* Force 8051 reset. */ 2532 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2533 } 2534 2535 static int 2536 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2537 { 2538 uint32_t reg; 2539 int off, mlen, error = 0; 2540 2541 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2542 device_xname(sc->sc_dev), __func__, page, buf, len)); 2543 2544 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2545 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2546 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2547 2548 off = R92C_FW_START_ADDR; 2549 while (len > 0) { 2550 if (len > 196) 2551 mlen = 196; 2552 else if (len > 4) 2553 mlen = 4; 2554 else 2555 mlen = 1; 2556 error = urtwn_write_region(sc, off, buf, mlen); 2557 if (error != 0) 2558 break; 2559 off += mlen; 2560 buf += mlen; 2561 len -= mlen; 2562 } 2563 return (error); 2564 } 2565 2566 static int 2567 urtwn_load_firmware(struct urtwn_softc *sc) 2568 { 2569 firmware_handle_t fwh; 2570 const struct r92c_fw_hdr *hdr; 2571 const char *name; 2572 u_char *fw, *ptr; 2573 size_t len; 2574 uint32_t reg; 2575 int mlen, ntries, page, error; 2576 2577 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2578 2579 /* Read firmware image from the filesystem. */ 2580 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2581 URTWN_CHIP_UMC_A_CUT) 2582 name = "urtwn-rtl8192cfwU"; 2583 else 2584 name = "urtwn-rtl8192cfwT"; 2585 if ((error = firmware_open("urtwn", name, &fwh)) != 0) { 2586 aprint_error_dev(sc->sc_dev, 2587 "failed loadfirmware of file %s (error %d)\n", name, error); 2588 return (error); 2589 } 2590 len = firmware_get_size(fwh); 2591 fw = firmware_malloc(len); 2592 if (fw == NULL) { 2593 aprint_error_dev(sc->sc_dev, 2594 "failed to allocate firmware memory\n"); 2595 firmware_close(fwh); 2596 return (ENOMEM); 2597 } 2598 error = firmware_read(fwh, 0, fw, len); 2599 firmware_close(fwh); 2600 if (error != 0) { 2601 aprint_error_dev(sc->sc_dev, 2602 "failed to read firmware (error %d)\n", error); 2603 firmware_free(fw, 0); 2604 return (error); 2605 } 2606 2607 ptr = fw; 2608 hdr = (const struct r92c_fw_hdr *)ptr; 2609 /* Check if there is a valid FW header and skip it. */ 2610 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2611 (le16toh(hdr->signature) >> 4) == 0x92c) { 2612 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2613 device_xname(sc->sc_dev), __func__, 2614 le16toh(hdr->version), le16toh(hdr->subversion), 2615 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2616 ptr += sizeof(*hdr); 2617 len -= sizeof(*hdr); 2618 } 2619 2620 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2621 urtwn_fw_reset(sc); 2622 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2623 } 2624 2625 /* download enabled */ 2626 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2627 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2628 R92C_SYS_FUNC_EN_CPUEN); 2629 urtwn_write_1(sc, R92C_MCUFWDL, 2630 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2631 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2632 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2633 2634 /* download firmware */ 2635 for (page = 0; len > 0; page++) { 2636 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2637 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2638 if (error != 0) { 2639 aprint_error_dev(sc->sc_dev, 2640 "could not load firmware page %d\n", page); 2641 goto fail; 2642 } 2643 ptr += mlen; 2644 len -= mlen; 2645 } 2646 2647 /* download disable */ 2648 urtwn_write_1(sc, R92C_MCUFWDL, 2649 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2650 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2651 2652 /* Wait for checksum report. */ 2653 for (ntries = 0; ntries < 1000; ntries++) { 2654 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2655 break; 2656 DELAY(5); 2657 } 2658 if (ntries == 1000) { 2659 aprint_error_dev(sc->sc_dev, 2660 "timeout waiting for checksum report\n"); 2661 error = ETIMEDOUT; 2662 goto fail; 2663 } 2664 2665 /* Wait for firmware readiness. */ 2666 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2667 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2668 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2669 for (ntries = 0; ntries < 1000; ntries++) { 2670 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2671 break; 2672 DELAY(5); 2673 } 2674 if (ntries == 1000) { 2675 aprint_error_dev(sc->sc_dev, 2676 "timeout waiting for firmware readiness\n"); 2677 error = ETIMEDOUT; 2678 goto fail; 2679 } 2680 fail: 2681 firmware_free(fw, 0); 2682 return (error); 2683 } 2684 2685 static int 2686 urtwn_dma_init(struct urtwn_softc *sc) 2687 { 2688 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2689 uint32_t reg; 2690 int error; 2691 2692 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2693 2694 /* Initialize LLT table. */ 2695 error = urtwn_llt_init(sc); 2696 if (error != 0) 2697 return (error); 2698 2699 /* Get Tx queues to USB endpoints mapping. */ 2700 hashq = hasnq = haslq = 0; 2701 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2702 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2703 device_xname(sc->sc_dev), __func__, reg)); 2704 if (MS(reg, R92C_USB_EP_HQ) != 0) 2705 hashq = 1; 2706 if (MS(reg, R92C_USB_EP_NQ) != 0) 2707 hasnq = 1; 2708 if (MS(reg, R92C_USB_EP_LQ) != 0) 2709 haslq = 1; 2710 nqueues = hashq + hasnq + haslq; 2711 if (nqueues == 0) 2712 return (EIO); 2713 /* Get the number of pages for each queue. */ 2714 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2715 /* The remaining pages are assigned to the high priority queue. */ 2716 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2717 2718 /* Set number of pages for normal priority queue. */ 2719 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2720 urtwn_write_4(sc, R92C_RQPN, 2721 /* Set number of pages for public queue. */ 2722 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2723 /* Set number of pages for high priority queue. */ 2724 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2725 /* Set number of pages for low priority queue. */ 2726 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2727 /* Load values. */ 2728 R92C_RQPN_LD); 2729 2730 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2731 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2732 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2733 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2734 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2735 2736 /* Set queue to USB pipe mapping. */ 2737 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2738 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2739 if (nqueues == 1) { 2740 if (hashq) { 2741 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2742 } else if (hasnq) { 2743 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2744 } else { 2745 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2746 } 2747 } else if (nqueues == 2) { 2748 /* All 2-endpoints configs have a high priority queue. */ 2749 if (!hashq) { 2750 return (EIO); 2751 } 2752 if (hasnq) { 2753 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2754 } else { 2755 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2756 } 2757 } else { 2758 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2759 } 2760 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2761 2762 /* Set Tx/Rx transfer page boundary. */ 2763 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2764 2765 /* Set Tx/Rx transfer page size. */ 2766 urtwn_write_1(sc, R92C_PBP, 2767 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2768 return (0); 2769 } 2770 2771 static void 2772 urtwn_mac_init(struct urtwn_softc *sc) 2773 { 2774 int i; 2775 2776 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2777 2778 /* Write MAC initialization values. */ 2779 for (i = 0; i < (int)__arraycount(rtl8192cu_mac); i++) 2780 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2781 } 2782 2783 static void 2784 urtwn_bb_init(struct urtwn_softc *sc) 2785 { 2786 const struct urtwn_bb_prog *prog; 2787 uint32_t reg; 2788 int i; 2789 2790 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2791 2792 /* Enable BB and RF. */ 2793 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2794 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2795 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2796 R92C_SYS_FUNC_EN_DIO_RF); 2797 2798 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2799 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2800 2801 urtwn_write_1(sc, R92C_RF_CTRL, 2802 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2803 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2804 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2805 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2806 2807 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2808 urtwn_write_1(sc, 0x15, 0xe9); 2809 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2810 2811 /* Select BB programming based on board type. */ 2812 if (!(sc->chip & URTWN_CHIP_92C)) { 2813 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2814 prog = &rtl8188ce_bb_prog; 2815 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2816 prog = &rtl8188ru_bb_prog; 2817 } else { 2818 prog = &rtl8188cu_bb_prog; 2819 } 2820 } else { 2821 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2822 prog = &rtl8192ce_bb_prog; 2823 } else { 2824 prog = &rtl8192cu_bb_prog; 2825 } 2826 } 2827 /* Write BB initialization values. */ 2828 for (i = 0; i < prog->count; i++) { 2829 /* additional delay depend on registers */ 2830 switch (prog->regs[i]) { 2831 case 0xfe: 2832 usbd_delay_ms(sc->sc_udev, 50); 2833 break; 2834 case 0xfd: 2835 usbd_delay_ms(sc->sc_udev, 5); 2836 break; 2837 case 0xfc: 2838 usbd_delay_ms(sc->sc_udev, 1); 2839 break; 2840 case 0xfb: 2841 DELAY(50); 2842 break; 2843 case 0xfa: 2844 DELAY(5); 2845 break; 2846 case 0xf9: 2847 DELAY(1); 2848 break; 2849 } 2850 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2851 DELAY(1); 2852 } 2853 2854 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2855 /* 8192C 1T only configuration. */ 2856 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2857 reg = (reg & ~0x00000003) | 0x2; 2858 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2859 2860 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2861 reg = (reg & ~0x00300033) | 0x00200022; 2862 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2863 2864 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2865 reg = (reg & ~0xff000000) | (0x45 << 24); 2866 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2867 2868 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2869 reg = (reg & ~0x000000ff) | 0x23; 2870 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2871 2872 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2873 reg = (reg & ~0x00000030) | (1 << 4); 2874 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2875 2876 reg = urtwn_bb_read(sc, 0xe74); 2877 reg = (reg & ~0x0c000000) | (2 << 26); 2878 urtwn_bb_write(sc, 0xe74, reg); 2879 reg = urtwn_bb_read(sc, 0xe78); 2880 reg = (reg & ~0x0c000000) | (2 << 26); 2881 urtwn_bb_write(sc, 0xe78, reg); 2882 reg = urtwn_bb_read(sc, 0xe7c); 2883 reg = (reg & ~0x0c000000) | (2 << 26); 2884 urtwn_bb_write(sc, 0xe7c, reg); 2885 reg = urtwn_bb_read(sc, 0xe80); 2886 reg = (reg & ~0x0c000000) | (2 << 26); 2887 urtwn_bb_write(sc, 0xe80, reg); 2888 reg = urtwn_bb_read(sc, 0xe88); 2889 reg = (reg & ~0x0c000000) | (2 << 26); 2890 urtwn_bb_write(sc, 0xe88, reg); 2891 } 2892 2893 /* Write AGC values. */ 2894 for (i = 0; i < prog->agccount; i++) { 2895 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 2896 DELAY(1); 2897 } 2898 2899 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2900 R92C_HSSI_PARAM2_CCK_HIPWR) { 2901 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 2902 } 2903 } 2904 2905 static void 2906 urtwn_rf_init(struct urtwn_softc *sc) 2907 { 2908 const struct urtwn_rf_prog *prog; 2909 uint32_t reg, mask, saved; 2910 int i, j, idx; 2911 2912 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2913 2914 /* Select RF programming based on board type. */ 2915 if (!(sc->chip & URTWN_CHIP_92C)) { 2916 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2917 prog = rtl8188ce_rf_prog; 2918 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2919 prog = rtl8188ru_rf_prog; 2920 } else { 2921 prog = rtl8188cu_rf_prog; 2922 } 2923 } else { 2924 prog = rtl8192ce_rf_prog; 2925 } 2926 2927 for (i = 0; i < sc->nrxchains; i++) { 2928 /* Save RF_ENV control type. */ 2929 idx = i / 2; 2930 mask = 0xffffU << ((i % 2) * 16); 2931 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 2932 2933 /* Set RF_ENV enable. */ 2934 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2935 reg |= 0x100000; 2936 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2937 DELAY(1); 2938 2939 /* Set RF_ENV output high. */ 2940 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2941 reg |= 0x10; 2942 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2943 DELAY(1); 2944 2945 /* Set address and data lengths of RF registers. */ 2946 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2947 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2948 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2949 DELAY(1); 2950 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2951 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2952 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2953 DELAY(1); 2954 2955 /* Write RF initialization values for this chain. */ 2956 for (j = 0; j < prog[i].count; j++) { 2957 if (prog[i].regs[j] >= 0xf9 && 2958 prog[i].regs[j] <= 0xfe) { 2959 /* 2960 * These are fake RF registers offsets that 2961 * indicate a delay is required. 2962 */ 2963 usbd_delay_ms(sc->sc_udev, 50); 2964 continue; 2965 } 2966 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 2967 DELAY(1); 2968 } 2969 2970 /* Restore RF_ENV control type. */ 2971 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 2972 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 2973 } 2974 2975 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2976 URTWN_CHIP_UMC_A_CUT) { 2977 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2978 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2979 } 2980 2981 /* Cache RF register CHNLBW. */ 2982 for (i = 0; i < 2; i++) { 2983 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2984 } 2985 } 2986 2987 static void 2988 urtwn_cam_init(struct urtwn_softc *sc) 2989 { 2990 uint32_t content, command; 2991 uint8_t idx; 2992 int i; 2993 2994 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2995 2996 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 2997 content = (idx & 3) 2998 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 2999 | R92C_CAM_VALID; 3000 3001 command = R92C_CAMCMD_POLLING 3002 | R92C_CAMCMD_WRITE 3003 | R92C_CAM_CTL0(idx); 3004 3005 urtwn_write_4(sc, R92C_CAMWRITE, content); 3006 urtwn_write_4(sc, R92C_CAMCMD, command); 3007 } 3008 3009 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3010 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3011 if (i == 0) { 3012 content = (idx & 3) 3013 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3014 | R92C_CAM_VALID; 3015 } else { 3016 content = 0; 3017 } 3018 3019 command = R92C_CAMCMD_POLLING 3020 | R92C_CAMCMD_WRITE 3021 | R92C_CAM_CTL0(idx) 3022 | (u_int)i; 3023 3024 urtwn_write_4(sc, R92C_CAMWRITE, content); 3025 urtwn_write_4(sc, R92C_CAMCMD, command); 3026 } 3027 } 3028 3029 /* Invalidate all CAM entries. */ 3030 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3031 } 3032 3033 static void 3034 urtwn_pa_bias_init(struct urtwn_softc *sc) 3035 { 3036 uint8_t reg; 3037 int i; 3038 3039 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3040 3041 for (i = 0; i < sc->nrxchains; i++) { 3042 if (sc->pa_setting & (1U << i)) 3043 continue; 3044 3045 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3046 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3047 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3048 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3049 } 3050 if (!(sc->pa_setting & 0x10)) { 3051 reg = urtwn_read_1(sc, 0x16); 3052 reg = (reg & ~0xf0) | 0x90; 3053 urtwn_write_1(sc, 0x16, reg); 3054 } 3055 } 3056 3057 static void 3058 urtwn_rxfilter_init(struct urtwn_softc *sc) 3059 { 3060 3061 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3062 3063 /* Initialize Rx filter. */ 3064 /* TODO: use better filter for monitor mode. */ 3065 urtwn_write_4(sc, R92C_RCR, 3066 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3067 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3068 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3069 /* Accept all multicast frames. */ 3070 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3071 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3072 /* Accept all management frames. */ 3073 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3074 /* Reject all control frames. */ 3075 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3076 /* Accept all data frames. */ 3077 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3078 } 3079 3080 static void 3081 urtwn_edca_init(struct urtwn_softc *sc) 3082 { 3083 3084 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3085 3086 /* set spec SIFS (used in NAV) */ 3087 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3088 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3089 3090 /* set SIFS CCK/OFDM */ 3091 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3092 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3093 3094 /* TXOP */ 3095 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3096 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3097 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3098 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3099 } 3100 3101 static void 3102 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3103 uint16_t power[URTWN_RIDX_COUNT]) 3104 { 3105 uint32_t reg; 3106 3107 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3108 __func__, chain)); 3109 3110 /* Write per-CCK rate Tx power. */ 3111 if (chain == 0) { 3112 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3113 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3114 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3115 3116 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3117 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3118 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3119 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3120 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3121 } else { 3122 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3123 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3124 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3125 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3126 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3127 3128 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3129 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3130 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3131 } 3132 /* Write per-OFDM rate Tx power. */ 3133 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3134 SM(R92C_TXAGC_RATE06, power[ 4]) | 3135 SM(R92C_TXAGC_RATE09, power[ 5]) | 3136 SM(R92C_TXAGC_RATE12, power[ 6]) | 3137 SM(R92C_TXAGC_RATE18, power[ 7])); 3138 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3139 SM(R92C_TXAGC_RATE24, power[ 8]) | 3140 SM(R92C_TXAGC_RATE36, power[ 9]) | 3141 SM(R92C_TXAGC_RATE48, power[10]) | 3142 SM(R92C_TXAGC_RATE54, power[11])); 3143 /* Write per-MCS Tx power. */ 3144 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3145 SM(R92C_TXAGC_MCS00, power[12]) | 3146 SM(R92C_TXAGC_MCS01, power[13]) | 3147 SM(R92C_TXAGC_MCS02, power[14]) | 3148 SM(R92C_TXAGC_MCS03, power[15])); 3149 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3150 SM(R92C_TXAGC_MCS04, power[16]) | 3151 SM(R92C_TXAGC_MCS05, power[17]) | 3152 SM(R92C_TXAGC_MCS06, power[18]) | 3153 SM(R92C_TXAGC_MCS07, power[19])); 3154 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3155 SM(R92C_TXAGC_MCS08, power[20]) | 3156 SM(R92C_TXAGC_MCS09, power[21]) | 3157 SM(R92C_TXAGC_MCS10, power[22]) | 3158 SM(R92C_TXAGC_MCS11, power[23])); 3159 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3160 SM(R92C_TXAGC_MCS12, power[24]) | 3161 SM(R92C_TXAGC_MCS13, power[25]) | 3162 SM(R92C_TXAGC_MCS14, power[26]) | 3163 SM(R92C_TXAGC_MCS15, power[27])); 3164 } 3165 3166 static void 3167 urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, 3168 uint16_t power[URTWN_RIDX_COUNT]) 3169 { 3170 struct r92c_rom *rom = &sc->rom; 3171 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3172 const struct urtwn_txpwr *base; 3173 int ridx, group; 3174 3175 DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", 3176 device_xname(sc->sc_dev), __func__, chain, chan)); 3177 3178 /* Determine channel group. */ 3179 if (chan <= 3) { 3180 group = 0; 3181 } else if (chan <= 9) { 3182 group = 1; 3183 } else { 3184 group = 2; 3185 } 3186 3187 /* Get original Tx power based on board type and RF chain. */ 3188 if (!(sc->chip & URTWN_CHIP_92C)) { 3189 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3190 base = &rtl8188ru_txagc[chain]; 3191 } else { 3192 base = &rtl8192cu_txagc[chain]; 3193 } 3194 } else { 3195 base = &rtl8192cu_txagc[chain]; 3196 } 3197 3198 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3199 if (sc->regulatory == 0) { 3200 for (ridx = 0; ridx <= 3; ridx++) { 3201 power[ridx] = base->pwr[0][ridx]; 3202 } 3203 } 3204 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3205 if (sc->regulatory == 3) { 3206 power[ridx] = base->pwr[0][ridx]; 3207 /* Apply vendor limits. */ 3208 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3209 maxpow = rom->ht40_max_pwr[group]; 3210 } else { 3211 maxpow = rom->ht20_max_pwr[group]; 3212 } 3213 maxpow = (maxpow >> (chain * 4)) & 0xf; 3214 if (power[ridx] > maxpow) { 3215 power[ridx] = maxpow; 3216 } 3217 } else if (sc->regulatory == 1) { 3218 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3219 power[ridx] = base->pwr[group][ridx]; 3220 } 3221 } else if (sc->regulatory != 2) { 3222 power[ridx] = base->pwr[0][ridx]; 3223 } 3224 } 3225 3226 /* Compute per-CCK rate Tx power. */ 3227 cckpow = rom->cck_tx_pwr[chain][group]; 3228 for (ridx = 0; ridx <= 3; ridx++) { 3229 power[ridx] += cckpow; 3230 if (power[ridx] > R92C_MAX_TX_PWR) { 3231 power[ridx] = R92C_MAX_TX_PWR; 3232 } 3233 } 3234 3235 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3236 if (sc->ntxchains > 1) { 3237 /* Apply reduction for 2 spatial streams. */ 3238 diff = rom->ht40_2s_tx_pwr_diff[group]; 3239 diff = (diff >> (chain * 4)) & 0xf; 3240 htpow = (htpow > diff) ? htpow - diff : 0; 3241 } 3242 3243 /* Compute per-OFDM rate Tx power. */ 3244 diff = rom->ofdm_tx_pwr_diff[group]; 3245 diff = (diff >> (chain * 4)) & 0xf; 3246 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3247 for (ridx = 4; ridx <= 11; ridx++) { 3248 power[ridx] += ofdmpow; 3249 if (power[ridx] > R92C_MAX_TX_PWR) { 3250 power[ridx] = R92C_MAX_TX_PWR; 3251 } 3252 } 3253 3254 /* Compute per-MCS Tx power. */ 3255 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3256 diff = rom->ht20_tx_pwr_diff[group]; 3257 diff = (diff >> (chain * 4)) & 0xf; 3258 htpow += diff; /* HT40->HT20 correction. */ 3259 } 3260 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3261 power[ridx] += htpow; 3262 if (power[ridx] > R92C_MAX_TX_PWR) { 3263 power[ridx] = R92C_MAX_TX_PWR; 3264 } 3265 } 3266 #ifdef URTWN_DEBUG 3267 if (urtwn_debug & DBG_RF) { 3268 /* Dump per-rate Tx power values. */ 3269 printf("%s: %s: Tx power for chain %d:\n", 3270 device_xname(sc->sc_dev), __func__, chain); 3271 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3272 printf("%s: %s: Rate %d = %u\n", 3273 device_xname(sc->sc_dev), __func__, ridx, 3274 power[ridx]); 3275 } 3276 } 3277 #endif 3278 } 3279 3280 static void 3281 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3282 { 3283 uint16_t power[URTWN_RIDX_COUNT]; 3284 int i; 3285 3286 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3287 3288 for (i = 0; i < sc->ntxchains; i++) { 3289 /* Compute per-rate Tx power values. */ 3290 urtwn_get_txpower(sc, i, chan, ht40m, power); 3291 /* Write per-rate Tx power values to hardware. */ 3292 urtwn_write_txpower(sc, i, power); 3293 } 3294 } 3295 3296 static void 3297 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3298 { 3299 struct ieee80211com *ic = &sc->sc_ic; 3300 u_int chan; 3301 int i; 3302 3303 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3304 3305 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3306 __func__, chan)); 3307 3308 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3309 chan += 2; 3310 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3311 chan -= 2; 3312 } 3313 3314 /* Set Tx power for this new channel. */ 3315 urtwn_set_txpower(sc, chan, ht40m); 3316 3317 for (i = 0; i < sc->nrxchains; i++) { 3318 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3319 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3320 } 3321 3322 if (ht40m) { 3323 /* Is secondary channel below or above primary? */ 3324 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3325 uint32_t reg; 3326 3327 urtwn_write_1(sc, R92C_BWOPMODE, 3328 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3329 3330 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3331 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3332 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3333 3334 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3335 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3336 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3337 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3338 3339 /* Set CCK side band. */ 3340 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3341 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3342 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3343 3344 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3345 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3346 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3347 3348 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3349 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3350 ~R92C_FPGA0_ANAPARAM2_CBW20); 3351 3352 reg = urtwn_bb_read(sc, 0x818); 3353 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3354 urtwn_bb_write(sc, 0x818, reg); 3355 3356 /* Select 40MHz bandwidth. */ 3357 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3358 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3359 } else { 3360 urtwn_write_1(sc, R92C_BWOPMODE, 3361 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3362 3363 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3364 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3365 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3366 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3367 3368 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3369 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3370 R92C_FPGA0_ANAPARAM2_CBW20); 3371 3372 /* Select 20MHz bandwidth. */ 3373 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3374 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3375 } 3376 } 3377 3378 static void 3379 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3380 { 3381 3382 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3383 __func__, inited)); 3384 3385 /* TODO */ 3386 } 3387 3388 static void 3389 urtwn_lc_calib(struct urtwn_softc *sc) 3390 { 3391 uint32_t rf_ac[2]; 3392 uint8_t txmode; 3393 int i; 3394 3395 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3396 3397 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3398 if ((txmode & 0x70) != 0) { 3399 /* Disable all continuous Tx. */ 3400 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3401 3402 /* Set RF mode to standby mode. */ 3403 for (i = 0; i < sc->nrxchains; i++) { 3404 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3405 urtwn_rf_write(sc, i, R92C_RF_AC, 3406 RW(rf_ac[i], R92C_RF_AC_MODE, 3407 R92C_RF_AC_MODE_STANDBY)); 3408 } 3409 } else { 3410 /* Block all Tx queues. */ 3411 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3412 } 3413 /* Start calibration. */ 3414 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3415 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3416 3417 /* Give calibration the time to complete. */ 3418 usbd_delay_ms(sc->sc_udev, 100); 3419 3420 /* Restore configuration. */ 3421 if ((txmode & 0x70) != 0) { 3422 /* Restore Tx mode. */ 3423 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3424 /* Restore RF mode. */ 3425 for (i = 0; i < sc->nrxchains; i++) { 3426 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3427 } 3428 } else { 3429 /* Unblock all Tx queues. */ 3430 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3431 } 3432 } 3433 3434 static void 3435 urtwn_temp_calib(struct urtwn_softc *sc) 3436 { 3437 int temp; 3438 3439 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3440 3441 if (sc->thcal_state == 0) { 3442 /* Start measuring temperature. */ 3443 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3444 device_xname(sc->sc_dev), __func__)); 3445 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3446 sc->thcal_state = 1; 3447 return; 3448 } 3449 sc->thcal_state = 0; 3450 3451 /* Read measured temperature. */ 3452 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3453 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3454 __func__, temp)); 3455 if (temp == 0) /* Read failed, skip. */ 3456 return; 3457 3458 /* 3459 * Redo LC calibration if temperature changed significantly since 3460 * last calibration. 3461 */ 3462 if (sc->thcal_lctemp == 0) { 3463 /* First LC calibration is performed in urtwn_init(). */ 3464 sc->thcal_lctemp = temp; 3465 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3466 DPRINTFN(DBG_RF, 3467 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3468 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3469 temp)); 3470 urtwn_lc_calib(sc); 3471 /* Record temperature of last LC calibration. */ 3472 sc->thcal_lctemp = temp; 3473 } 3474 } 3475 3476 static int 3477 urtwn_init(struct ifnet *ifp) 3478 { 3479 struct urtwn_softc *sc = ifp->if_softc; 3480 struct ieee80211com *ic = &sc->sc_ic; 3481 struct urtwn_rx_data *data; 3482 uint32_t reg; 3483 int i, error; 3484 3485 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3486 3487 urtwn_stop(ifp, 0); 3488 3489 mutex_enter(&sc->sc_task_mtx); 3490 /* Init host async commands ring. */ 3491 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3492 mutex_exit(&sc->sc_task_mtx); 3493 3494 mutex_enter(&sc->sc_fwcmd_mtx); 3495 /* Init firmware commands ring. */ 3496 sc->fwcur = 0; 3497 mutex_exit(&sc->sc_fwcmd_mtx); 3498 3499 /* Allocate Tx/Rx buffers. */ 3500 error = urtwn_alloc_rx_list(sc); 3501 if (error != 0) { 3502 aprint_error_dev(sc->sc_dev, 3503 "could not allocate Rx buffers\n"); 3504 goto fail; 3505 } 3506 error = urtwn_alloc_tx_list(sc); 3507 if (error != 0) { 3508 aprint_error_dev(sc->sc_dev, 3509 "could not allocate Tx buffers\n"); 3510 goto fail; 3511 } 3512 3513 /* Power on adapter. */ 3514 error = urtwn_power_on(sc); 3515 if (error != 0) 3516 goto fail; 3517 3518 /* Initialize DMA. */ 3519 error = urtwn_dma_init(sc); 3520 if (error != 0) 3521 goto fail; 3522 3523 /* Set info size in Rx descriptors (in 64-bit words). */ 3524 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3525 3526 /* Init interrupts. */ 3527 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3528 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3529 3530 /* Set MAC address. */ 3531 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3532 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3533 3534 /* Set initial network type. */ 3535 reg = urtwn_read_4(sc, R92C_CR); 3536 switch (ic->ic_opmode) { 3537 case IEEE80211_M_STA: 3538 default: 3539 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3540 break; 3541 3542 case IEEE80211_M_IBSS: 3543 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3544 break; 3545 } 3546 urtwn_write_4(sc, R92C_CR, reg); 3547 3548 urtwn_rxfilter_init(sc); 3549 3550 /* Set response rate */ 3551 reg = urtwn_read_4(sc, R92C_RRSR); 3552 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3553 urtwn_write_4(sc, R92C_RRSR, reg); 3554 3555 /* SIFS (used in NAV) */ 3556 urtwn_write_2(sc, R92C_SPEC_SIFS, 3557 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3558 3559 /* Set short/long retry limits. */ 3560 urtwn_write_2(sc, R92C_RL, 3561 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3562 3563 /* Initialize EDCA parameters. */ 3564 urtwn_edca_init(sc); 3565 3566 /* Setup rate fallback. */ 3567 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3568 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3569 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3570 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3571 3572 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3573 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3574 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3575 /* Set ACK timeout. */ 3576 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3577 3578 /* Setup USB aggregation. */ 3579 /* Tx */ 3580 reg = urtwn_read_4(sc, R92C_TDECTRL); 3581 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3582 urtwn_write_4(sc, R92C_TDECTRL, reg); 3583 /* Rx */ 3584 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3585 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3586 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3587 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3588 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3589 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3590 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3591 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3592 3593 /* Initialize beacon parameters. */ 3594 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3595 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3596 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3597 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3598 3599 /* Setup AMPDU aggregation. */ 3600 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3601 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3602 urtwn_write_2(sc, 0x4ca, 0x0708); 3603 3604 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3605 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3606 3607 /* Load 8051 microcode. */ 3608 error = urtwn_load_firmware(sc); 3609 if (error != 0) 3610 goto fail; 3611 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3612 3613 /* Initialize MAC/BB/RF blocks. */ 3614 urtwn_mac_init(sc); 3615 urtwn_write_4(sc, R92C_RCR, 3616 urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); 3617 urtwn_bb_init(sc); 3618 urtwn_rf_init(sc); 3619 3620 /* Turn CCK and OFDM blocks on. */ 3621 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3622 reg |= R92C_RFMOD_CCK_EN; 3623 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3624 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3625 reg |= R92C_RFMOD_OFDM_EN; 3626 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3627 3628 /* Clear per-station keys table. */ 3629 urtwn_cam_init(sc); 3630 3631 /* Enable hardware sequence numbering. */ 3632 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3633 3634 /* Perform LO and IQ calibrations. */ 3635 urtwn_iq_calib(sc, sc->iqk_inited); 3636 sc->iqk_inited = true; 3637 3638 /* Perform LC calibration. */ 3639 urtwn_lc_calib(sc); 3640 3641 /* Fix USB interference issue. */ 3642 urtwn_write_1(sc, 0xfe40, 0xe0); 3643 urtwn_write_1(sc, 0xfe41, 0x8d); 3644 urtwn_write_1(sc, 0xfe42, 0x80); 3645 urtwn_write_4(sc, 0x20c, 0xfd0320); 3646 3647 urtwn_pa_bias_init(sc); 3648 3649 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3650 /* 1T1R */ 3651 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3652 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3653 } 3654 3655 /* Initialize GPIO setting. */ 3656 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3657 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3658 3659 /* Fix for lower temperature. */ 3660 urtwn_write_1(sc, 0x15, 0xe9); 3661 3662 /* Set default channel. */ 3663 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3664 urtwn_set_chan(sc, ic->ic_ibss_chan, IEEE80211_HTINFO_2NDCHAN_NONE); 3665 3666 /* Queue Rx xfers. */ 3667 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3668 data = &sc->rx_data[i]; 3669 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3670 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3671 USBD_NO_TIMEOUT, urtwn_rxeof); 3672 error = usbd_transfer(data->xfer); 3673 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3674 error != USBD_IN_PROGRESS)) 3675 goto fail; 3676 } 3677 3678 /* We're ready to go. */ 3679 ifp->if_flags &= ~IFF_OACTIVE; 3680 ifp->if_flags |= IFF_RUNNING; 3681 3682 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3683 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3684 else 3685 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3686 return (0); 3687 3688 fail: 3689 urtwn_stop(ifp, 1); 3690 return (error); 3691 } 3692 3693 static void 3694 urtwn_stop(struct ifnet *ifp, int disable) 3695 { 3696 struct urtwn_softc *sc = ifp->if_softc; 3697 struct ieee80211com *ic = &sc->sc_ic; 3698 int i, s; 3699 3700 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3701 3702 sc->tx_timer = 0; 3703 ifp->if_timer = 0; 3704 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3705 3706 s = splusb(); 3707 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3708 urtwn_wait_async(sc); 3709 splx(s); 3710 3711 callout_stop(&sc->sc_scan_to); 3712 callout_stop(&sc->sc_calib_to); 3713 3714 /* Abort Tx. */ 3715 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3716 if (sc->tx_pipe[i] != NULL) 3717 usbd_abort_pipe(sc->tx_pipe[i]); 3718 } 3719 3720 /* Stop Rx pipe. */ 3721 usbd_abort_pipe(sc->rx_pipe); 3722 3723 /* Free Tx/Rx buffers. */ 3724 urtwn_free_tx_list(sc); 3725 urtwn_free_rx_list(sc); 3726 3727 if (disable) 3728 urtwn_chip_stop(sc); 3729 } 3730 3731 static void 3732 urtwn_chip_stop(struct urtwn_softc *sc) 3733 { 3734 uint32_t reg; 3735 bool disabled = true; 3736 3737 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3738 3739 /* 3740 * RF Off Sequence 3741 */ 3742 /* Pause MAC TX queue */ 3743 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3744 3745 /* Disable RF */ 3746 urtwn_rf_write(sc, 0, 0, 0); 3747 3748 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3749 3750 /* Reset BB state machine */ 3751 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3752 R92C_SYS_FUNC_EN_USBD | 3753 R92C_SYS_FUNC_EN_USBA | 3754 R92C_SYS_FUNC_EN_BB_GLB_RST); 3755 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3756 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3757 3758 /* 3759 * Reset digital sequence 3760 */ 3761 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3762 /* Reset MCU ready status */ 3763 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3764 /* If firmware in ram code, do reset */ 3765 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3766 urtwn_fw_reset(sc); 3767 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3768 } 3769 } 3770 3771 /* Reset MAC and Enable 8051 */ 3772 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3773 3774 /* Reset MCU ready status */ 3775 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3776 3777 if (disabled) { 3778 /* Disable MAC clock */ 3779 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3780 /* Disable AFE PLL */ 3781 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3782 /* Gated AFE DIG_CLOCK */ 3783 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3784 /* Isolated digital to PON */ 3785 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3786 } 3787 3788 /* 3789 * Pull GPIO PIN to balance level and LED control 3790 */ 3791 /* 1. Disable GPIO[7:0] */ 3792 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3793 3794 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3795 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3796 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3797 3798 /* Disable GPIO[10:8] */ 3799 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3800 3801 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3802 reg |= (((reg & 0x000f) << 4) | 0x0780); 3803 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3804 3805 /* Disable LED0 & 1 */ 3806 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3807 3808 /* 3809 * Reset digital sequence 3810 */ 3811 if (disabled) { 3812 /* Disable ELDR clock */ 3813 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3814 /* Isolated ELDR to PON */ 3815 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3816 } 3817 3818 /* 3819 * Disable analog sequence 3820 */ 3821 if (disabled) { 3822 /* Disable A15 power */ 3823 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3824 /* Disable digital core power */ 3825 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3826 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3827 ~R92C_LDOV12D_CTRL_LDV12_EN); 3828 } 3829 3830 /* Enter PFM mode */ 3831 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3832 3833 /* Set USB suspend */ 3834 urtwn_write_2(sc, R92C_APS_FSMCO, 3835 R92C_APS_FSMCO_APDM_HOST | 3836 R92C_APS_FSMCO_AFSM_HSUS | 3837 R92C_APS_FSMCO_PFM_ALDN); 3838 3839 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3840 } 3841 3842 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 3843 3844 #ifdef _MODULE 3845 #include "ioconf.c" 3846 #endif 3847 3848 static int 3849 if_urtwn_modcmd(modcmd_t cmd, void *aux) 3850 { 3851 int error = 0; 3852 3853 switch (cmd) { 3854 case MODULE_CMD_INIT: 3855 #ifdef _MODULE 3856 error = config_init_component(cfdriver_ioconf_urtwn, 3857 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3858 #endif 3859 return (error); 3860 case MODULE_CMD_FINI: 3861 #ifdef _MODULE 3862 error = config_fini_component(cfdriver_ioconf_urtwn, 3863 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3864 #endif 3865 return (error); 3866 default: 3867 return (ENOTTY); 3868 } 3869 } 3870
Indexes created Tue Sep 30 07:10:03 GMT 2025