if_urtwn.c revision 1.24.4.1
1 /* $NetBSD: if_urtwn.c,v 1.24.4.1 2013/08/28 23:59:27 rmind Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.24.4.1 2013/08/28 23:59:27 rmind Exp $"); 26 27 #ifdef _KERNEL_OPT 28 #include "opt_inet.h" 29 #endif 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 /* 78 * The sc_write_mtx locking is to prevent sequences of writes from 79 * being intermingled with each other. I don't know if this is really 80 * needed. I have added it just to be on the safe side. 81 */ 82 83 #ifdef URTWN_DEBUG 84 #define DBG_INIT __BIT(0) 85 #define DBG_FN __BIT(1) 86 #define DBG_TX __BIT(2) 87 #define DBG_RX __BIT(3) 88 #define DBG_STM __BIT(4) 89 #define DBG_RF __BIT(5) 90 #define DBG_REG __BIT(6) 91 #define DBG_ALL 0xffffffffU 92 u_int urtwn_debug = 0; 93 #define DPRINTFN(n, s) \ 94 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 95 #else 96 #define DPRINTFN(n, s) 97 #endif 98 99 static const struct usb_devno urtwn_devs[] = { 100 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 101 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 102 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 103 { USB_VENDOR_ASUSTEK, USB_PRODUCT_ASUSTEK_RTL8192CU }, 104 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 105 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 106 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 107 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 108 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 109 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 110 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 111 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 112 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 113 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 114 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 115 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 116 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 117 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 118 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 119 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 120 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 121 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 122 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 123 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 124 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 125 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 126 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 127 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 128 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 129 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 130 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 131 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 132 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 133 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 134 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 135 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 136 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 137 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 138 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 139 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 140 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 141 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 142 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 143 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 144 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 145 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 146 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 147 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 148 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 149 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 150 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 151 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 152 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CUR2 }, 153 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 154 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 155 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 156 }; 157 158 static int urtwn_match(device_t, cfdata_t, void *); 159 static void urtwn_attach(device_t, device_t, void *); 160 static int urtwn_detach(device_t, int); 161 static int urtwn_activate(device_t, enum devact); 162 163 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 164 urtwn_attach, urtwn_detach, urtwn_activate); 165 166 static int urtwn_open_pipes(struct urtwn_softc *); 167 static void urtwn_close_pipes(struct urtwn_softc *); 168 static int urtwn_alloc_rx_list(struct urtwn_softc *); 169 static void urtwn_free_rx_list(struct urtwn_softc *); 170 static int urtwn_alloc_tx_list(struct urtwn_softc *); 171 static void urtwn_free_tx_list(struct urtwn_softc *); 172 static void urtwn_task(void *); 173 static void urtwn_do_async(struct urtwn_softc *, 174 void (*)(struct urtwn_softc *, void *), void *, int); 175 static void urtwn_wait_async(struct urtwn_softc *); 176 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 177 int); 178 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 179 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 180 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 181 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 182 int); 183 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 184 int); 185 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 186 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 187 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 188 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 189 static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t, uint32_t); 190 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 191 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 192 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 193 static void urtwn_efuse_read(struct urtwn_softc *); 194 static int urtwn_read_chipid(struct urtwn_softc *); 195 #ifdef URTWN_DEBUG 196 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 197 #endif 198 static void urtwn_read_rom(struct urtwn_softc *); 199 static int urtwn_media_change(struct ifnet *); 200 static int urtwn_ra_init(struct urtwn_softc *); 201 static int urtwn_get_nettype(struct urtwn_softc *); 202 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 203 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 204 static void urtwn_set_led(struct urtwn_softc *, int, int); 205 static void urtwn_calib_to(void *); 206 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 207 static void urtwn_next_scan(void *); 208 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 209 int); 210 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 211 static int urtwn_wme_update(struct ieee80211com *); 212 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 213 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 214 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 215 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 216 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 217 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 218 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 219 struct ieee80211_node *, struct urtwn_tx_data *); 220 static void urtwn_start(struct ifnet *); 221 static void urtwn_watchdog(struct ifnet *); 222 static int urtwn_ioctl(struct ifnet *, u_long, void *); 223 static int urtwn_power_on(struct urtwn_softc *); 224 static int urtwn_llt_init(struct urtwn_softc *); 225 static void urtwn_fw_reset(struct urtwn_softc *); 226 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 227 static int urtwn_load_firmware(struct urtwn_softc *); 228 static int urtwn_dma_init(struct urtwn_softc *); 229 static void urtwn_mac_init(struct urtwn_softc *); 230 static void urtwn_bb_init(struct urtwn_softc *); 231 static void urtwn_rf_init(struct urtwn_softc *); 232 static void urtwn_cam_init(struct urtwn_softc *); 233 static void urtwn_pa_bias_init(struct urtwn_softc *); 234 static void urtwn_rxfilter_init(struct urtwn_softc *); 235 static void urtwn_edca_init(struct urtwn_softc *); 236 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 237 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 238 uint16_t[]); 239 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 240 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 241 u_int); 242 static void urtwn_iq_calib(struct urtwn_softc *, bool); 243 static void urtwn_lc_calib(struct urtwn_softc *); 244 static void urtwn_temp_calib(struct urtwn_softc *); 245 static int urtwn_init(struct ifnet *); 246 static void urtwn_stop(struct ifnet *, int); 247 static int urtwn_reset(struct ifnet *); 248 static void urtwn_chip_stop(struct urtwn_softc *); 249 250 /* Aliases. */ 251 #define urtwn_bb_write urtwn_write_4 252 #define urtwn_bb_read urtwn_read_4 253 254 static int 255 urtwn_match(device_t parent, cfdata_t match, void *aux) 256 { 257 struct usb_attach_arg *uaa = aux; 258 259 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 260 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 261 } 262 263 static void 264 urtwn_attach(device_t parent, device_t self, void *aux) 265 { 266 struct urtwn_softc *sc = device_private(self); 267 struct ieee80211com *ic = &sc->sc_ic; 268 struct ifnet *ifp = &sc->sc_if; 269 struct usb_attach_arg *uaa = aux; 270 char *devinfop; 271 size_t i; 272 int error; 273 274 sc->sc_dev = self; 275 sc->sc_udev = uaa->device; 276 277 aprint_naive("\n"); 278 aprint_normal("\n"); 279 280 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 281 282 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 283 aprint_normal_dev(self, "%s\n", devinfop); 284 usbd_devinfo_free(devinfop); 285 286 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 287 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 288 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 289 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 290 291 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 292 293 callout_init(&sc->sc_scan_to, 0); 294 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 295 callout_init(&sc->sc_calib_to, 0); 296 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 297 298 error = usbd_set_config_no(sc->sc_udev, 1, 0); 299 if (error != 0) { 300 aprint_error_dev(self, "failed to set configuration" 301 ", err=%s\n", usbd_errstr(error)); 302 goto fail; 303 } 304 305 /* Get the first interface handle. */ 306 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 307 if (error != 0) { 308 aprint_error_dev(self, "could not get interface handle\n"); 309 goto fail; 310 } 311 312 error = urtwn_read_chipid(sc); 313 if (error != 0) { 314 aprint_error_dev(self, "unsupported test chip\n"); 315 goto fail; 316 } 317 318 /* Determine number of Tx/Rx chains. */ 319 if (sc->chip & URTWN_CHIP_92C) { 320 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 321 sc->nrxchains = 2; 322 } else { 323 sc->ntxchains = 1; 324 sc->nrxchains = 1; 325 } 326 urtwn_read_rom(sc); 327 328 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 329 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 330 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 331 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 332 "8188CUS", sc->ntxchains, sc->nrxchains, 333 ether_sprintf(ic->ic_myaddr)); 334 335 error = urtwn_open_pipes(sc); 336 if (error != 0) { 337 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 338 goto fail; 339 } 340 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 341 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 342 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 343 344 /* 345 * Setup the 802.11 device. 346 */ 347 ic->ic_ifp = ifp; 348 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 349 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 350 ic->ic_state = IEEE80211_S_INIT; 351 352 /* Set device capabilities. */ 353 ic->ic_caps = 354 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 355 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 356 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 357 IEEE80211_C_WME | /* 802.11e */ 358 IEEE80211_C_WPA; /* 802.11i */ 359 360 /* Set supported .11b and .11g rates. */ 361 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 362 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 363 364 /* Set supported .11b and .11g channels (1 through 14). */ 365 for (i = 1; i <= 14; i++) { 366 ic->ic_channels[i].ic_freq = 367 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 368 ic->ic_channels[i].ic_flags = 369 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 370 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 371 } 372 373 ifp->if_softc = sc; 374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 375 ifp->if_init = urtwn_init; 376 ifp->if_ioctl = urtwn_ioctl; 377 ifp->if_start = urtwn_start; 378 ifp->if_watchdog = urtwn_watchdog; 379 IFQ_SET_READY(&ifp->if_snd); 380 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 381 382 if_attach(ifp); 383 ieee80211_ifattach(ic); 384 385 /* override default methods */ 386 ic->ic_reset = urtwn_reset; 387 ic->ic_wme.wme_update = urtwn_wme_update; 388 389 /* Override state transition machine. */ 390 sc->sc_newstate = ic->ic_newstate; 391 ic->ic_newstate = urtwn_newstate; 392 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 393 394 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 395 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 396 &sc->sc_drvbpf); 397 398 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 399 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 400 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 401 402 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 403 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 404 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 405 406 ieee80211_announce(ic); 407 408 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 409 410 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 411 return; 412 413 fail: 414 sc->sc_dying = 1; 415 aprint_error_dev(self, "attach failed\n"); 416 } 417 418 static int 419 urtwn_detach(device_t self, int flags) 420 { 421 struct urtwn_softc *sc = device_private(self); 422 struct ifnet *ifp = &sc->sc_if; 423 int s; 424 425 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 426 427 s = splusb(); 428 429 sc->sc_dying = 1; 430 431 callout_stop(&sc->sc_scan_to); 432 callout_stop(&sc->sc_calib_to); 433 434 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 435 usb_rem_task(sc->sc_udev, &sc->sc_task); 436 urtwn_stop(ifp, 0); 437 438 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 439 bpf_detach(ifp); 440 ieee80211_ifdetach(&sc->sc_ic); 441 if_detach(ifp); 442 443 /* Abort and close Tx/Rx pipes. */ 444 urtwn_close_pipes(sc); 445 } 446 447 splx(s); 448 449 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 450 451 callout_destroy(&sc->sc_scan_to); 452 callout_destroy(&sc->sc_calib_to); 453 454 mutex_destroy(&sc->sc_write_mtx); 455 mutex_destroy(&sc->sc_fwcmd_mtx); 456 mutex_destroy(&sc->sc_tx_mtx); 457 mutex_destroy(&sc->sc_task_mtx); 458 459 return (0); 460 } 461 462 static int 463 urtwn_activate(device_t self, enum devact act) 464 { 465 struct urtwn_softc *sc = device_private(self); 466 467 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 468 469 switch (act) { 470 case DVACT_DEACTIVATE: 471 if_deactivate(sc->sc_ic.ic_ifp); 472 return (0); 473 default: 474 return (EOPNOTSUPP); 475 } 476 } 477 478 static int 479 urtwn_open_pipes(struct urtwn_softc *sc) 480 { 481 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 482 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 483 usb_interface_descriptor_t *id; 484 usb_endpoint_descriptor_t *ed; 485 size_t i, ntx = 0; 486 int error; 487 488 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 489 490 /* Determine the number of bulk-out pipes. */ 491 id = usbd_get_interface_descriptor(sc->sc_iface); 492 for (i = 0; i < id->bNumEndpoints; i++) { 493 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 494 if (ed != NULL && 495 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 496 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 497 ntx++; 498 } 499 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 500 device_xname(sc->sc_dev), __func__, ntx)); 501 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 502 aprint_error_dev(sc->sc_dev, 503 "%zd: invalid number of Tx bulk pipes\n", ntx); 504 return (EIO); 505 } 506 sc->rx_npipe = 1; 507 sc->tx_npipe = ntx; 508 509 /* Open bulk-in pipe at address 0x81. */ 510 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 511 &sc->rx_pipe); 512 if (error != 0) { 513 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 514 ": %d\n", error); 515 goto fail; 516 } 517 518 /* Open bulk-out pipes (up to 3). */ 519 for (i = 0; i < ntx; i++) { 520 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 521 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 522 if (error != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "could not open Tx bulk pipe 0x%02x: %d\n", 525 epaddr[i], error); 526 goto fail; 527 } 528 } 529 530 /* Map 802.11 access categories to USB pipes. */ 531 sc->ac2idx[WME_AC_BK] = 532 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 533 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 534 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 535 536 fail: 537 if (error != 0) 538 urtwn_close_pipes(sc); 539 return (error); 540 } 541 542 static void 543 urtwn_close_pipes(struct urtwn_softc *sc) 544 { 545 usbd_pipe_handle pipe; 546 size_t i; 547 548 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 549 550 /* Close Rx pipe. */ 551 CTASSERT(sizeof(pipe) == sizeof(void *)); 552 pipe = atomic_swap_ptr(&sc->rx_pipe, NULL); 553 if (pipe != NULL) { 554 usbd_abort_pipe(pipe); 555 usbd_close_pipe(pipe); 556 } 557 /* Close Tx pipes. */ 558 for (i = 0; i < R92C_MAX_EPOUT; i++) { 559 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 560 if (pipe != NULL) { 561 usbd_abort_pipe(pipe); 562 usbd_close_pipe(pipe); 563 } 564 } 565 } 566 567 static int 568 urtwn_alloc_rx_list(struct urtwn_softc *sc) 569 { 570 struct urtwn_rx_data *data; 571 size_t i; 572 int error = 0; 573 574 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 575 576 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 577 data = &sc->rx_data[i]; 578 579 data->sc = sc; /* Backpointer for callbacks. */ 580 581 data->xfer = usbd_alloc_xfer(sc->sc_udev); 582 if (data->xfer == NULL) { 583 aprint_error_dev(sc->sc_dev, 584 "could not allocate xfer\n"); 585 error = ENOMEM; 586 break; 587 } 588 589 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 590 if (data->buf == NULL) { 591 aprint_error_dev(sc->sc_dev, 592 "could not allocate xfer buffer\n"); 593 error = ENOMEM; 594 break; 595 } 596 } 597 if (error != 0) 598 urtwn_free_rx_list(sc); 599 return (error); 600 } 601 602 static void 603 urtwn_free_rx_list(struct urtwn_softc *sc) 604 { 605 usbd_xfer_handle xfer; 606 size_t i; 607 608 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 609 610 /* NB: Caller must abort pipe first. */ 611 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 612 CTASSERT(sizeof(xfer) == sizeof(void *)); 613 xfer = atomic_swap_ptr(&sc->rx_data[i].xfer, NULL); 614 if (xfer != NULL) 615 usbd_free_xfer(xfer); 616 } 617 } 618 619 static int 620 urtwn_alloc_tx_list(struct urtwn_softc *sc) 621 { 622 struct urtwn_tx_data *data; 623 size_t i; 624 int error = 0; 625 626 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 627 628 mutex_enter(&sc->sc_tx_mtx); 629 TAILQ_INIT(&sc->tx_free_list); 630 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 631 data = &sc->tx_data[i]; 632 633 data->sc = sc; /* Backpointer for callbacks. */ 634 635 data->xfer = usbd_alloc_xfer(sc->sc_udev); 636 if (data->xfer == NULL) { 637 aprint_error_dev(sc->sc_dev, 638 "could not allocate xfer\n"); 639 error = ENOMEM; 640 goto fail; 641 } 642 643 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 644 if (data->buf == NULL) { 645 aprint_error_dev(sc->sc_dev, 646 "could not allocate xfer buffer\n"); 647 error = ENOMEM; 648 goto fail; 649 } 650 651 /* Append this Tx buffer to our free list. */ 652 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 653 } 654 mutex_exit(&sc->sc_tx_mtx); 655 return (0); 656 657 fail: 658 urtwn_free_tx_list(sc); 659 mutex_exit(&sc->sc_tx_mtx); 660 return (error); 661 } 662 663 static void 664 urtwn_free_tx_list(struct urtwn_softc *sc) 665 { 666 usbd_xfer_handle xfer; 667 size_t i; 668 669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 670 671 /* NB: Caller must abort pipe first. */ 672 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 673 CTASSERT(sizeof(xfer) == sizeof(void *)); 674 xfer = atomic_swap_ptr(&sc->tx_data[i].xfer, NULL); 675 if (xfer != NULL) 676 usbd_free_xfer(xfer); 677 } 678 } 679 680 static void 681 urtwn_task(void *arg) 682 { 683 struct urtwn_softc *sc = arg; 684 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 685 struct urtwn_host_cmd *cmd; 686 int s; 687 688 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 689 690 /* Process host commands. */ 691 s = splusb(); 692 mutex_spin_enter(&sc->sc_task_mtx); 693 while (ring->next != ring->cur) { 694 cmd = &ring->cmd[ring->next]; 695 mutex_spin_exit(&sc->sc_task_mtx); 696 splx(s); 697 /* Invoke callback with kernel lock held. */ 698 cmd->cb(sc, cmd->data); 699 s = splusb(); 700 mutex_spin_enter(&sc->sc_task_mtx); 701 ring->queued--; 702 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 703 } 704 mutex_spin_exit(&sc->sc_task_mtx); 705 wakeup(&sc->cmdq); 706 splx(s); 707 } 708 709 static void 710 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 711 void *arg, int len) 712 { 713 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 714 struct urtwn_host_cmd *cmd; 715 int s; 716 717 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 718 device_xname(sc->sc_dev), __func__, cb, arg, len)); 719 720 s = splusb(); 721 mutex_spin_enter(&sc->sc_task_mtx); 722 cmd = &ring->cmd[ring->cur]; 723 cmd->cb = cb; 724 KASSERT(len <= sizeof(cmd->data)); 725 memcpy(cmd->data, arg, len); 726 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 727 728 /* If there is no pending command already, schedule a task. */ 729 if (!sc->sc_dying && ++ring->queued == 1) { 730 mutex_spin_exit(&sc->sc_task_mtx); 731 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 732 } else 733 mutex_spin_exit(&sc->sc_task_mtx); 734 splx(s); 735 } 736 737 static void 738 urtwn_wait_async(struct urtwn_softc *sc) 739 { 740 741 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 742 743 /* Wait for all queued asynchronous commands to complete. */ 744 while (sc->cmdq.queued > 0) 745 tsleep(&sc->cmdq, 0, "endtask", 0); 746 } 747 748 static int 749 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 750 int len) 751 { 752 usb_device_request_t req; 753 usbd_status error; 754 755 KASSERT(mutex_owned(&sc->sc_write_mtx)); 756 757 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 758 req.bRequest = R92C_REQ_REGS; 759 USETW(req.wValue, addr); 760 USETW(req.wIndex, 0); 761 USETW(req.wLength, len); 762 error = usbd_do_request(sc->sc_udev, &req, buf); 763 if (error != USBD_NORMAL_COMPLETION) { 764 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 765 device_xname(sc->sc_dev), __func__, error, addr, len)); 766 } 767 return (error); 768 } 769 770 static void 771 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 772 { 773 774 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 775 device_xname(sc->sc_dev), __func__, addr, val)); 776 777 urtwn_write_region_1(sc, addr, &val, 1); 778 } 779 780 static void 781 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 782 { 783 uint8_t buf[2]; 784 785 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 786 device_xname(sc->sc_dev), __func__, addr, val)); 787 788 buf[0] = (uint8_t)val; 789 buf[1] = (uint8_t)(val >> 8); 790 urtwn_write_region_1(sc, addr, buf, 2); 791 } 792 793 static void 794 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 795 { 796 uint8_t buf[4]; 797 798 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 799 device_xname(sc->sc_dev), __func__, addr, val)); 800 801 buf[0] = (uint8_t)val; 802 buf[1] = (uint8_t)(val >> 8); 803 buf[2] = (uint8_t)(val >> 16); 804 buf[3] = (uint8_t)(val >> 24); 805 urtwn_write_region_1(sc, addr, buf, 4); 806 } 807 808 static int 809 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 810 { 811 812 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 813 device_xname(sc->sc_dev), __func__, addr, len)); 814 815 return urtwn_write_region_1(sc, addr, buf, len); 816 } 817 818 static int 819 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 820 int len) 821 { 822 usb_device_request_t req; 823 usbd_status error; 824 825 req.bmRequestType = UT_READ_VENDOR_DEVICE; 826 req.bRequest = R92C_REQ_REGS; 827 USETW(req.wValue, addr); 828 USETW(req.wIndex, 0); 829 USETW(req.wLength, len); 830 error = usbd_do_request(sc->sc_udev, &req, buf); 831 if (error != USBD_NORMAL_COMPLETION) { 832 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 833 device_xname(sc->sc_dev), __func__, error, addr, len)); 834 } 835 return (error); 836 } 837 838 static uint8_t 839 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 840 { 841 uint8_t val; 842 843 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 844 return (0xff); 845 846 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 847 device_xname(sc->sc_dev), __func__, addr, val)); 848 return (val); 849 } 850 851 static uint16_t 852 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 853 { 854 uint8_t buf[2]; 855 uint16_t val; 856 857 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 858 return (0xffff); 859 860 val = LE_READ_2(&buf[0]); 861 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 862 device_xname(sc->sc_dev), __func__, addr, val)); 863 return (val); 864 } 865 866 static uint32_t 867 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 868 { 869 uint8_t buf[4]; 870 uint32_t val; 871 872 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 873 return (0xffffffff); 874 875 val = LE_READ_4(&buf[0]); 876 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 877 device_xname(sc->sc_dev), __func__, addr, val)); 878 return (val); 879 } 880 881 static int 882 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 883 { 884 struct r92c_fw_cmd cmd; 885 uint8_t *cp; 886 int fwcur; 887 int ntries; 888 889 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 890 device_xname(sc->sc_dev), __func__, id, buf, len)); 891 892 KASSERT(mutex_owned(&sc->sc_write_mtx)); 893 894 mutex_enter(&sc->sc_fwcmd_mtx); 895 fwcur = sc->fwcur; 896 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 897 mutex_exit(&sc->sc_fwcmd_mtx); 898 899 /* Wait for current FW box to be empty. */ 900 for (ntries = 0; ntries < 100; ntries++) { 901 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 902 break; 903 DELAY(1); 904 } 905 if (ntries == 100) { 906 aprint_error_dev(sc->sc_dev, 907 "could not send firmware command %d\n", id); 908 return (ETIMEDOUT); 909 } 910 911 memset(&cmd, 0, sizeof(cmd)); 912 KASSERT(len <= sizeof(cmd.msg)); 913 memcpy(cmd.msg, buf, len); 914 915 /* Write the first word last since that will trigger the FW. */ 916 cp = (uint8_t *)&cmd; 917 if (len >= 4) { 918 cmd.id = id | R92C_CMD_FLAG_EXT; 919 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 920 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 921 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 922 } else { 923 cmd.id = id; 924 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 925 } 926 927 return (0); 928 } 929 930 static void 931 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 932 { 933 934 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 935 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 936 } 937 938 static uint32_t 939 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 940 { 941 uint32_t reg[R92C_MAX_CHAINS], val; 942 943 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 944 if (chain != 0) { 945 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 946 } 947 948 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 949 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 950 DELAY(1000); 951 952 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 953 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 954 R92C_HSSI_PARAM2_READ_EDGE); 955 DELAY(1000); 956 957 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 958 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 959 DELAY(1000); 960 961 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 962 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 963 } else { 964 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 965 } 966 return (MS(val, R92C_LSSI_READBACK_DATA)); 967 } 968 969 static int 970 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 971 { 972 int ntries; 973 974 KASSERT(mutex_owned(&sc->sc_write_mtx)); 975 976 urtwn_write_4(sc, R92C_LLT_INIT, 977 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 978 SM(R92C_LLT_INIT_ADDR, addr) | 979 SM(R92C_LLT_INIT_DATA, data)); 980 /* Wait for write operation to complete. */ 981 for (ntries = 0; ntries < 20; ntries++) { 982 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 983 R92C_LLT_INIT_OP_NO_ACTIVE) { 984 /* Done */ 985 return (0); 986 } 987 DELAY(5); 988 } 989 return (ETIMEDOUT); 990 } 991 992 static uint8_t 993 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 994 { 995 uint32_t reg; 996 int ntries; 997 998 KASSERT(mutex_owned(&sc->sc_write_mtx)); 999 1000 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1001 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1002 reg &= ~R92C_EFUSE_CTRL_VALID; 1003 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1004 1005 /* Wait for read operation to complete. */ 1006 for (ntries = 0; ntries < 100; ntries++) { 1007 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1008 if (reg & R92C_EFUSE_CTRL_VALID) { 1009 /* Done */ 1010 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1011 } 1012 DELAY(5); 1013 } 1014 aprint_error_dev(sc->sc_dev, 1015 "could not read efuse byte at address 0x%04x\n", addr); 1016 return (0xff); 1017 } 1018 1019 static void 1020 urtwn_efuse_read(struct urtwn_softc *sc) 1021 { 1022 uint8_t *rom = (uint8_t *)&sc->rom; 1023 uint32_t reg; 1024 uint16_t addr = 0; 1025 uint8_t off, msk; 1026 size_t i; 1027 1028 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1029 1030 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1031 1032 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1033 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1034 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1035 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1036 } 1037 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1038 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1039 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1040 reg | R92C_SYS_FUNC_EN_ELDR); 1041 } 1042 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1043 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1044 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1045 urtwn_write_2(sc, R92C_SYS_CLKR, 1046 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1047 } 1048 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1049 while (addr < 512) { 1050 reg = urtwn_efuse_read_1(sc, addr); 1051 if (reg == 0xff) 1052 break; 1053 addr++; 1054 off = reg >> 4; 1055 msk = reg & 0xf; 1056 for (i = 0; i < 4; i++) { 1057 if (msk & (1U << i)) 1058 continue; 1059 1060 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1061 addr++; 1062 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1063 addr++; 1064 } 1065 } 1066 #ifdef URTWN_DEBUG 1067 if (urtwn_debug & DBG_INIT) { 1068 /* Dump ROM content. */ 1069 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1070 for (i = 0; i < (int)sizeof(sc->rom); i++) 1071 printf(":%02x", rom[i]); 1072 printf("\n"); 1073 } 1074 #endif 1075 } 1076 1077 static int 1078 urtwn_read_chipid(struct urtwn_softc *sc) 1079 { 1080 uint32_t reg; 1081 1082 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1083 1084 sc->chip = 0; 1085 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1086 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1087 /* test chip, not supported */ 1088 return (EIO); 1089 } 1090 if (reg & R92C_SYS_CFG_TYPE_92C) { 1091 sc->chip |= URTWN_CHIP_92C; 1092 /* Check if it is a castrated 8192C. */ 1093 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1094 R92C_HPON_FSM_CHIP_BONDING_ID) == 1095 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1096 sc->chip |= URTWN_CHIP_92C_1T2R; 1097 } 1098 } 1099 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1100 sc->chip |= URTWN_CHIP_UMC; 1101 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1102 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1103 } 1104 } 1105 return (0); 1106 } 1107 1108 #ifdef URTWN_DEBUG 1109 static void 1110 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1111 { 1112 1113 aprint_normal_dev(sc->sc_dev, 1114 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1115 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1116 1117 aprint_normal_dev(sc->sc_dev, 1118 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1119 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1120 1121 aprint_normal_dev(sc->sc_dev, 1122 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1123 rp->macaddr[0], rp->macaddr[1], 1124 rp->macaddr[2], rp->macaddr[3], 1125 rp->macaddr[4], rp->macaddr[5]); 1126 1127 aprint_normal_dev(sc->sc_dev, 1128 "string %s, subcustomer_id 0x%x\n", 1129 rp->string, rp->subcustomer_id); 1130 1131 aprint_normal_dev(sc->sc_dev, 1132 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1133 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1134 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1135 1136 aprint_normal_dev(sc->sc_dev, 1137 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1138 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1139 rp->ht40_1s_tx_pwr[0][2], 1140 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1141 rp->ht40_1s_tx_pwr[1][2]); 1142 1143 aprint_normal_dev(sc->sc_dev, 1144 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1145 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1146 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1147 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1148 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1149 1150 aprint_normal_dev(sc->sc_dev, 1151 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1152 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1153 rp->ht20_tx_pwr_diff[2] & 0xf, 1154 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1155 rp->ht20_tx_pwr_diff[2] >> 4); 1156 1157 aprint_normal_dev(sc->sc_dev, 1158 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1159 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1160 rp->ofdm_tx_pwr_diff[2] & 0xf, 1161 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1162 rp->ofdm_tx_pwr_diff[2] >> 4); 1163 1164 aprint_normal_dev(sc->sc_dev, 1165 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1166 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1167 rp->ht40_max_pwr[2] & 0xf, 1168 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1169 rp->ht40_max_pwr[2] >> 4); 1170 1171 aprint_normal_dev(sc->sc_dev, 1172 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1173 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1174 rp->ht20_max_pwr[2] & 0xf, 1175 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1176 rp->ht20_max_pwr[2] >> 4); 1177 1178 aprint_normal_dev(sc->sc_dev, 1179 "xtal_calib %d, tssi %d %d, thermal %d\n", 1180 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1181 1182 aprint_normal_dev(sc->sc_dev, 1183 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1184 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1185 1186 aprint_normal_dev(sc->sc_dev, 1187 "channnel_plan %d, version %d customer_id 0x%x\n", 1188 rp->channel_plan, rp->version, rp->curstomer_id); 1189 } 1190 #endif 1191 1192 static void 1193 urtwn_read_rom(struct urtwn_softc *sc) 1194 { 1195 struct ieee80211com *ic = &sc->sc_ic; 1196 struct r92c_rom *rom = &sc->rom; 1197 1198 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1199 1200 mutex_enter(&sc->sc_write_mtx); 1201 1202 /* Read full ROM image. */ 1203 urtwn_efuse_read(sc); 1204 #ifdef URTWN_DEBUG 1205 if (urtwn_debug & DBG_REG) 1206 urtwn_dump_rom(sc, rom); 1207 #endif 1208 1209 /* XXX Weird but this is what the vendor driver does. */ 1210 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1211 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1212 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1213 1214 DPRINTFN(DBG_INIT, 1215 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1216 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1217 sc->board_type, sc->regulatory)); 1218 1219 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1220 1221 mutex_exit(&sc->sc_write_mtx); 1222 } 1223 1224 static int 1225 urtwn_media_change(struct ifnet *ifp) 1226 { 1227 #ifdef URTWN_DEBUG 1228 struct urtwn_softc *sc = ifp->if_softc; 1229 #endif 1230 int error; 1231 1232 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1233 1234 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1235 return (error); 1236 1237 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1238 (IFF_UP | IFF_RUNNING)) { 1239 urtwn_init(ifp); 1240 } 1241 return (0); 1242 } 1243 1244 /* 1245 * Initialize rate adaptation in firmware. 1246 */ 1247 static int 1248 urtwn_ra_init(struct urtwn_softc *sc) 1249 { 1250 static const uint8_t map[] = { 1251 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1252 }; 1253 struct ieee80211com *ic = &sc->sc_ic; 1254 struct ieee80211_node *ni = ic->ic_bss; 1255 struct ieee80211_rateset *rs = &ni->ni_rates; 1256 struct r92c_fw_cmd_macid_cfg cmd; 1257 uint32_t rates, basicrates; 1258 uint32_t mask; 1259 uint8_t mode; 1260 size_t maxrate, maxbasicrate, i, j; 1261 int error; 1262 1263 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1264 1265 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1266 1267 /* Get normal and basic rates mask. */ 1268 rates = basicrates = 0; 1269 maxrate = maxbasicrate = 0; 1270 for (i = 0; i < rs->rs_nrates; i++) { 1271 /* Convert 802.11 rate to HW rate index. */ 1272 for (j = 0; j < __arraycount(map); j++) { 1273 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1274 break; 1275 } 1276 } 1277 if (j == __arraycount(map)) { 1278 /* Unknown rate, skip. */ 1279 continue; 1280 } 1281 1282 rates |= 1U << j; 1283 if (j > maxrate) { 1284 maxrate = j; 1285 } 1286 1287 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1288 basicrates |= 1U << j; 1289 if (j > maxbasicrate) { 1290 maxbasicrate = j; 1291 } 1292 } 1293 } 1294 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1295 mode = R92C_RAID_11B; 1296 } else { 1297 mode = R92C_RAID_11BG; 1298 } 1299 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1300 "maxrate=%zx, maxbasicrate=%zx\n", 1301 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1302 maxrate, maxbasicrate)); 1303 if (basicrates == 0) { 1304 basicrates |= 1; /* add 1Mbps */ 1305 } 1306 1307 /* Set rates mask for group addressed frames. */ 1308 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1309 mask = (mode << 28) | basicrates; 1310 cmd.mask[0] = (uint8_t)mask; 1311 cmd.mask[1] = (uint8_t)(mask >> 8); 1312 cmd.mask[2] = (uint8_t)(mask >> 16); 1313 cmd.mask[3] = (uint8_t)(mask >> 24); 1314 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1315 if (error != 0) { 1316 aprint_error_dev(sc->sc_dev, 1317 "could not add broadcast station\n"); 1318 return (error); 1319 } 1320 /* Set initial MRR rate. */ 1321 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1322 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1323 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1324 1325 /* Set rates mask for unicast frames. */ 1326 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1327 mask = (mode << 28) | rates; 1328 cmd.mask[0] = (uint8_t)mask; 1329 cmd.mask[1] = (uint8_t)(mask >> 8); 1330 cmd.mask[2] = (uint8_t)(mask >> 16); 1331 cmd.mask[3] = (uint8_t)(mask >> 24); 1332 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1333 if (error != 0) { 1334 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1335 return (error); 1336 } 1337 /* Set initial MRR rate. */ 1338 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1339 __func__, maxrate)); 1340 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1341 1342 /* Indicate highest supported rate. */ 1343 ni->ni_txrate = rs->rs_nrates - 1; 1344 1345 return (0); 1346 } 1347 1348 static int 1349 urtwn_get_nettype(struct urtwn_softc *sc) 1350 { 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 int type; 1353 1354 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1355 1356 switch (ic->ic_opmode) { 1357 case IEEE80211_M_STA: 1358 type = R92C_CR_NETTYPE_INFRA; 1359 break; 1360 1361 case IEEE80211_M_IBSS: 1362 type = R92C_CR_NETTYPE_ADHOC; 1363 break; 1364 1365 default: 1366 type = R92C_CR_NETTYPE_NOLINK; 1367 break; 1368 } 1369 1370 return (type); 1371 } 1372 1373 static void 1374 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1375 { 1376 uint8_t reg; 1377 1378 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1379 __func__, type)); 1380 1381 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1382 1383 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1384 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1385 } 1386 1387 static void 1388 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1389 { 1390 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1391 uint64_t tsf; 1392 1393 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1394 1395 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1396 1397 /* Enable TSF synchronization. */ 1398 urtwn_write_1(sc, R92C_BCN_CTRL, 1399 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1400 1401 /* Correct TSF */ 1402 urtwn_write_1(sc, R92C_BCN_CTRL, 1403 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1404 1405 /* Set initial TSF. */ 1406 tsf = ni->ni_tstamp.tsf; 1407 tsf = le64toh(tsf); 1408 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1409 tsf -= IEEE80211_DUR_TU; 1410 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1411 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1412 1413 urtwn_write_1(sc, R92C_BCN_CTRL, 1414 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1415 } 1416 1417 static void 1418 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1419 { 1420 uint8_t reg; 1421 1422 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1423 __func__, led, on)); 1424 1425 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1426 1427 if (led == URTWN_LED_LINK) { 1428 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1429 if (!on) { 1430 reg |= R92C_LEDCFG0_DIS; 1431 } 1432 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1433 sc->ledlink = on; /* Save LED state. */ 1434 } 1435 } 1436 1437 static void 1438 urtwn_calib_to(void *arg) 1439 { 1440 struct urtwn_softc *sc = arg; 1441 1442 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1443 1444 if (sc->sc_dying) 1445 return; 1446 1447 /* Do it in a process context. */ 1448 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1449 } 1450 1451 /* ARGSUSED */ 1452 static void 1453 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1454 { 1455 struct r92c_fw_cmd_rssi cmd; 1456 1457 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1458 1459 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1460 goto restart_timer; 1461 1462 mutex_enter(&sc->sc_write_mtx); 1463 if (sc->avg_pwdb != -1) { 1464 /* Indicate Rx signal strength to FW for rate adaptation. */ 1465 memset(&cmd, 0, sizeof(cmd)); 1466 cmd.macid = 0; /* BSS. */ 1467 cmd.pwdb = sc->avg_pwdb; 1468 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1469 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1470 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1471 } 1472 1473 /* Do temperature compensation. */ 1474 urtwn_temp_calib(sc); 1475 mutex_exit(&sc->sc_write_mtx); 1476 1477 restart_timer: 1478 if (!sc->sc_dying) { 1479 /* Restart calibration timer. */ 1480 callout_schedule(&sc->sc_calib_to, hz); 1481 } 1482 } 1483 1484 static void 1485 urtwn_next_scan(void *arg) 1486 { 1487 struct urtwn_softc *sc = arg; 1488 int s; 1489 1490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1491 1492 if (sc->sc_dying) 1493 return; 1494 1495 s = splnet(); 1496 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1497 ieee80211_next_scan(&sc->sc_ic); 1498 splx(s); 1499 } 1500 1501 static int 1502 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1503 { 1504 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1505 struct urtwn_cmd_newstate cmd; 1506 1507 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1508 device_xname(sc->sc_dev), __func__, 1509 ieee80211_state_name[nstate], nstate, arg)); 1510 1511 callout_stop(&sc->sc_scan_to); 1512 callout_stop(&sc->sc_calib_to); 1513 1514 /* Do it in a process context. */ 1515 cmd.state = nstate; 1516 cmd.arg = arg; 1517 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1518 return (0); 1519 } 1520 1521 static void 1522 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1523 { 1524 struct urtwn_cmd_newstate *cmd = arg; 1525 struct ieee80211com *ic = &sc->sc_ic; 1526 struct ieee80211_node *ni; 1527 enum ieee80211_state ostate = ic->ic_state; 1528 enum ieee80211_state nstate = cmd->state; 1529 uint32_t reg; 1530 uint8_t sifs_time; 1531 int s; 1532 1533 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1534 device_xname(sc->sc_dev), __func__, 1535 ieee80211_state_name[ostate], ostate, 1536 ieee80211_state_name[nstate], nstate)); 1537 1538 s = splnet(); 1539 mutex_enter(&sc->sc_write_mtx); 1540 1541 callout_stop(&sc->sc_scan_to); 1542 callout_stop(&sc->sc_calib_to); 1543 1544 switch (ostate) { 1545 case IEEE80211_S_INIT: 1546 break; 1547 1548 case IEEE80211_S_SCAN: 1549 if (nstate != IEEE80211_S_SCAN) { 1550 /* 1551 * End of scanning 1552 */ 1553 /* flush 4-AC Queue after site_survey */ 1554 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1555 1556 /* Allow Rx from our BSSID only. */ 1557 urtwn_write_4(sc, R92C_RCR, 1558 urtwn_read_4(sc, R92C_RCR) | 1559 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1560 } 1561 break; 1562 1563 case IEEE80211_S_AUTH: 1564 case IEEE80211_S_ASSOC: 1565 break; 1566 1567 case IEEE80211_S_RUN: 1568 /* Turn link LED off. */ 1569 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1570 1571 /* Set media status to 'No Link'. */ 1572 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1573 1574 /* Stop Rx of data frames. */ 1575 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1576 1577 /* Reset TSF. */ 1578 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1579 1580 /* Disable TSF synchronization. */ 1581 urtwn_write_1(sc, R92C_BCN_CTRL, 1582 urtwn_read_1(sc, R92C_BCN_CTRL) | 1583 R92C_BCN_CTRL_DIS_TSF_UDT0); 1584 1585 /* Back to 20MHz mode */ 1586 urtwn_set_chan(sc, ic->ic_curchan, 1587 IEEE80211_HTINFO_2NDCHAN_NONE); 1588 1589 if (ic->ic_opmode == IEEE80211_M_IBSS || 1590 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1591 /* Stop BCN */ 1592 urtwn_write_1(sc, R92C_BCN_CTRL, 1593 urtwn_read_1(sc, R92C_BCN_CTRL) & 1594 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1595 } 1596 1597 /* Reset EDCA parameters. */ 1598 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1599 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1600 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1601 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1602 1603 /* flush all cam entries */ 1604 urtwn_cam_init(sc); 1605 break; 1606 } 1607 1608 switch (nstate) { 1609 case IEEE80211_S_INIT: 1610 /* Turn link LED off. */ 1611 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1612 break; 1613 1614 case IEEE80211_S_SCAN: 1615 if (ostate != IEEE80211_S_SCAN) { 1616 /* 1617 * Begin of scanning 1618 */ 1619 1620 /* Set gain for scanning. */ 1621 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1622 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1623 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1624 1625 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1626 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1627 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1628 1629 /* Set media status to 'No Link'. */ 1630 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1631 1632 /* Allow Rx from any BSSID. */ 1633 urtwn_write_4(sc, R92C_RCR, 1634 urtwn_read_4(sc, R92C_RCR) & 1635 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1636 1637 /* Stop Rx of data frames. */ 1638 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1639 1640 /* Disable update TSF */ 1641 urtwn_write_1(sc, R92C_BCN_CTRL, 1642 urtwn_read_1(sc, R92C_BCN_CTRL) | 1643 R92C_BCN_CTRL_DIS_TSF_UDT0); 1644 } 1645 1646 /* Make link LED blink during scan. */ 1647 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1648 1649 /* Pause AC Tx queues. */ 1650 urtwn_write_1(sc, R92C_TXPAUSE, 1651 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1652 1653 urtwn_set_chan(sc, ic->ic_curchan, 1654 IEEE80211_HTINFO_2NDCHAN_NONE); 1655 1656 /* Start periodic scan. */ 1657 if (!sc->sc_dying) 1658 callout_schedule(&sc->sc_scan_to, hz / 5); 1659 break; 1660 1661 case IEEE80211_S_AUTH: 1662 /* Set initial gain under link. */ 1663 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1664 #ifdef doaslinux 1665 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1666 #else 1667 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1668 #endif 1669 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1670 1671 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1672 #ifdef doaslinux 1673 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1674 #else 1675 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1676 #endif 1677 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1678 1679 /* Set media status to 'No Link'. */ 1680 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1681 1682 /* Allow Rx from any BSSID. */ 1683 urtwn_write_4(sc, R92C_RCR, 1684 urtwn_read_4(sc, R92C_RCR) & 1685 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1686 1687 urtwn_set_chan(sc, ic->ic_curchan, 1688 IEEE80211_HTINFO_2NDCHAN_NONE); 1689 break; 1690 1691 case IEEE80211_S_ASSOC: 1692 break; 1693 1694 case IEEE80211_S_RUN: 1695 ni = ic->ic_bss; 1696 1697 /* XXX: Set 20MHz mode */ 1698 urtwn_set_chan(sc, ic->ic_curchan, 1699 IEEE80211_HTINFO_2NDCHAN_NONE); 1700 1701 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1702 /* Back to 20MHz mode */ 1703 urtwn_set_chan(sc, ic->ic_curchan, 1704 IEEE80211_HTINFO_2NDCHAN_NONE); 1705 1706 /* Set media status to 'No Link'. */ 1707 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1708 1709 /* Enable Rx of data frames. */ 1710 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1711 1712 /* Allow Rx from any BSSID. */ 1713 urtwn_write_4(sc, R92C_RCR, 1714 urtwn_read_4(sc, R92C_RCR) & 1715 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1716 1717 /* Accept Rx data/control/management frames */ 1718 urtwn_write_4(sc, R92C_RCR, 1719 urtwn_read_4(sc, R92C_RCR) | 1720 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1721 1722 /* Turn link LED on. */ 1723 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1724 break; 1725 } 1726 1727 /* Set media status to 'Associated'. */ 1728 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1729 1730 /* Set BSSID. */ 1731 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1732 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1733 1734 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1735 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1736 } else { 1737 /* 802.11b/g */ 1738 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1739 } 1740 1741 /* Enable Rx of data frames. */ 1742 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1743 1744 /* Set beacon interval. */ 1745 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1746 1747 if (ic->ic_opmode == IEEE80211_M_STA) { 1748 /* Allow Rx from our BSSID only. */ 1749 urtwn_write_4(sc, R92C_RCR, 1750 urtwn_read_4(sc, R92C_RCR) | 1751 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1752 1753 /* Enable TSF synchronization. */ 1754 urtwn_tsf_sync_enable(sc); 1755 } 1756 1757 sifs_time = 10; 1758 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1759 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1760 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1761 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1762 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1763 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1764 1765 /* Intialize rate adaptation. */ 1766 urtwn_ra_init(sc); 1767 1768 /* Turn link LED on. */ 1769 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1770 1771 /* Reset average RSSI. */ 1772 sc->avg_pwdb = -1; 1773 1774 /* Reset temperature calibration state machine. */ 1775 sc->thcal_state = 0; 1776 sc->thcal_lctemp = 0; 1777 1778 /* Start periodic calibration. */ 1779 if (!sc->sc_dying) 1780 callout_schedule(&sc->sc_calib_to, hz); 1781 break; 1782 } 1783 1784 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1785 1786 mutex_exit(&sc->sc_write_mtx); 1787 splx(s); 1788 } 1789 1790 static int 1791 urtwn_wme_update(struct ieee80211com *ic) 1792 { 1793 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1794 1795 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1796 1797 /* don't override default WME values if WME is not actually enabled */ 1798 if (!(ic->ic_flags & IEEE80211_F_WME)) 1799 return (0); 1800 1801 /* Do it in a process context. */ 1802 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1803 return (0); 1804 } 1805 1806 static void 1807 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1808 { 1809 static const uint16_t ac2reg[WME_NUM_AC] = { 1810 R92C_EDCA_BE_PARAM, 1811 R92C_EDCA_BK_PARAM, 1812 R92C_EDCA_VI_PARAM, 1813 R92C_EDCA_VO_PARAM 1814 }; 1815 struct ieee80211com *ic = &sc->sc_ic; 1816 const struct wmeParams *wmep; 1817 int ac, aifs, slottime; 1818 int s; 1819 1820 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1821 __func__)); 1822 1823 s = splnet(); 1824 mutex_enter(&sc->sc_write_mtx); 1825 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1826 for (ac = 0; ac < WME_NUM_AC; ac++) { 1827 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1828 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1829 aifs = wmep->wmep_aifsn * slottime + 10; 1830 urtwn_write_4(sc, ac2reg[ac], 1831 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1832 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1833 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1834 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1835 } 1836 mutex_exit(&sc->sc_write_mtx); 1837 splx(s); 1838 } 1839 1840 static void 1841 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1842 { 1843 int pwdb; 1844 1845 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1846 device_xname(sc->sc_dev), __func__, rate, rssi)); 1847 1848 /* Convert antenna signal to percentage. */ 1849 if (rssi <= -100 || rssi >= 20) 1850 pwdb = 0; 1851 else if (rssi >= 0) 1852 pwdb = 100; 1853 else 1854 pwdb = 100 + rssi; 1855 if (rate <= 3) { 1856 /* CCK gain is smaller than OFDM/MCS gain. */ 1857 pwdb += 6; 1858 if (pwdb > 100) 1859 pwdb = 100; 1860 if (pwdb <= 14) 1861 pwdb -= 4; 1862 else if (pwdb <= 26) 1863 pwdb -= 8; 1864 else if (pwdb <= 34) 1865 pwdb -= 6; 1866 else if (pwdb <= 42) 1867 pwdb -= 2; 1868 } 1869 if (sc->avg_pwdb == -1) /* Init. */ 1870 sc->avg_pwdb = pwdb; 1871 else if (sc->avg_pwdb < pwdb) 1872 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1873 else 1874 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1875 1876 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 1877 device_xname(sc->sc_dev), __func__, 1878 rate, rssi, pwdb, sc->avg_pwdb)); 1879 } 1880 1881 static int8_t 1882 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1883 { 1884 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1885 struct r92c_rx_phystat *phy; 1886 struct r92c_rx_cck *cck; 1887 uint8_t rpt; 1888 int8_t rssi; 1889 1890 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1891 __func__, rate)); 1892 1893 if (rate <= 3) { 1894 cck = (struct r92c_rx_cck *)physt; 1895 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1896 rpt = (cck->agc_rpt >> 5) & 0x3; 1897 rssi = (cck->agc_rpt & 0x1f) << 1; 1898 } else { 1899 rpt = (cck->agc_rpt >> 6) & 0x3; 1900 rssi = cck->agc_rpt & 0x3e; 1901 } 1902 rssi = cckoff[rpt] - rssi; 1903 } else { /* OFDM/HT. */ 1904 phy = (struct r92c_rx_phystat *)physt; 1905 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1906 } 1907 return (rssi); 1908 } 1909 1910 static void 1911 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1912 { 1913 struct ieee80211com *ic = &sc->sc_ic; 1914 struct ifnet *ifp = ic->ic_ifp; 1915 struct ieee80211_frame *wh; 1916 struct ieee80211_node *ni; 1917 struct r92c_rx_stat *stat; 1918 uint32_t rxdw0, rxdw3; 1919 struct mbuf *m; 1920 uint8_t rate; 1921 int8_t rssi = 0; 1922 int s, infosz; 1923 1924 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1925 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1926 1927 stat = (struct r92c_rx_stat *)buf; 1928 rxdw0 = le32toh(stat->rxdw0); 1929 rxdw3 = le32toh(stat->rxdw3); 1930 1931 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1932 /* 1933 * This should not happen since we setup our Rx filter 1934 * to not receive these frames. 1935 */ 1936 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1937 device_xname(sc->sc_dev), __func__)); 1938 ifp->if_ierrors++; 1939 return; 1940 } 1941 /* 1942 * XXX: This will drop most control packets. Do we really 1943 * want this in IEEE80211_M_MONITOR mode? 1944 */ 1945 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 1946 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1947 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1948 device_xname(sc->sc_dev), __func__, pktlen)); 1949 ic->ic_stats.is_rx_tooshort++; 1950 ifp->if_ierrors++; 1951 return; 1952 } 1953 if (__predict_false(pktlen > MCLBYTES)) { 1954 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1955 device_xname(sc->sc_dev), __func__, pktlen)); 1956 ifp->if_ierrors++; 1957 return; 1958 } 1959 1960 rate = MS(rxdw3, R92C_RXDW3_RATE); 1961 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1962 1963 /* Get RSSI from PHY status descriptor if present. */ 1964 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1965 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1966 /* Update our average RSSI. */ 1967 urtwn_update_avgrssi(sc, rate, rssi); 1968 } 1969 1970 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1971 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1972 1973 MGETHDR(m, M_DONTWAIT, MT_DATA); 1974 if (__predict_false(m == NULL)) { 1975 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1976 ic->ic_stats.is_rx_nobuf++; 1977 ifp->if_ierrors++; 1978 return; 1979 } 1980 if (pktlen > (int)MHLEN) { 1981 MCLGET(m, M_DONTWAIT); 1982 if (__predict_false(!(m->m_flags & M_EXT))) { 1983 aprint_error_dev(sc->sc_dev, 1984 "couldn't allocate rx mbuf cluster\n"); 1985 m_freem(m); 1986 ic->ic_stats.is_rx_nobuf++; 1987 ifp->if_ierrors++; 1988 return; 1989 } 1990 } 1991 1992 /* Finalize mbuf. */ 1993 m->m_pkthdr.rcvif = ifp; 1994 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1995 memcpy(mtod(m, uint8_t *), wh, pktlen); 1996 m->m_pkthdr.len = m->m_len = pktlen; 1997 1998 s = splnet(); 1999 if (__predict_false(sc->sc_drvbpf != NULL)) { 2000 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2001 2002 tap->wr_flags = 0; 2003 if (!(rxdw3 & R92C_RXDW3_HT)) { 2004 switch (rate) { 2005 /* CCK. */ 2006 case 0: tap->wr_rate = 2; break; 2007 case 1: tap->wr_rate = 4; break; 2008 case 2: tap->wr_rate = 11; break; 2009 case 3: tap->wr_rate = 22; break; 2010 /* OFDM. */ 2011 case 4: tap->wr_rate = 12; break; 2012 case 5: tap->wr_rate = 18; break; 2013 case 6: tap->wr_rate = 24; break; 2014 case 7: tap->wr_rate = 36; break; 2015 case 8: tap->wr_rate = 48; break; 2016 case 9: tap->wr_rate = 72; break; 2017 case 10: tap->wr_rate = 96; break; 2018 case 11: tap->wr_rate = 108; break; 2019 } 2020 } else if (rate >= 12) { /* MCS0~15. */ 2021 /* Bit 7 set means HT MCS instead of rate. */ 2022 tap->wr_rate = 0x80 | (rate - 12); 2023 } 2024 tap->wr_dbm_antsignal = rssi; 2025 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2026 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2027 2028 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2029 } 2030 2031 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2032 2033 /* push the frame up to the 802.11 stack */ 2034 ieee80211_input(ic, m, ni, rssi, 0); 2035 2036 /* Node is no longer needed. */ 2037 ieee80211_free_node(ni); 2038 2039 splx(s); 2040 } 2041 2042 static void 2043 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2044 { 2045 struct urtwn_rx_data *data = priv; 2046 struct urtwn_softc *sc = data->sc; 2047 struct r92c_rx_stat *stat; 2048 uint32_t rxdw0; 2049 uint8_t *buf; 2050 int len, totlen, pktlen, infosz, npkts; 2051 2052 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2053 device_xname(sc->sc_dev), __func__, status)); 2054 2055 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2056 if (status == USBD_STALLED) 2057 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2058 else if (status != USBD_CANCELLED) 2059 goto resubmit; 2060 return; 2061 } 2062 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2063 2064 if (__predict_false(len < (int)sizeof(*stat))) { 2065 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2066 device_xname(sc->sc_dev), __func__, len)); 2067 goto resubmit; 2068 } 2069 buf = data->buf; 2070 2071 /* Get the number of encapsulated frames. */ 2072 stat = (struct r92c_rx_stat *)buf; 2073 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2074 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2075 device_xname(sc->sc_dev), __func__, npkts)); 2076 2077 /* Process all of them. */ 2078 while (npkts-- > 0) { 2079 if (__predict_false(len < (int)sizeof(*stat))) { 2080 DPRINTFN(DBG_RX, 2081 ("%s: %s: len(%d) is short than header\n", 2082 device_xname(sc->sc_dev), __func__, len)); 2083 break; 2084 } 2085 stat = (struct r92c_rx_stat *)buf; 2086 rxdw0 = le32toh(stat->rxdw0); 2087 2088 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2089 if (__predict_false(pktlen == 0)) { 2090 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2091 device_xname(sc->sc_dev), __func__)); 2092 break; 2093 } 2094 2095 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2096 2097 /* Make sure everything fits in xfer. */ 2098 totlen = sizeof(*stat) + infosz + pktlen; 2099 if (__predict_false(totlen > len)) { 2100 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2101 device_xname(sc->sc_dev), __func__, totlen, 2102 (int)sizeof(*stat), infosz, pktlen, len)); 2103 break; 2104 } 2105 2106 /* Process 802.11 frame. */ 2107 urtwn_rx_frame(sc, buf, pktlen); 2108 2109 /* Next chunk is 128-byte aligned. */ 2110 totlen = roundup2(totlen, 128); 2111 buf += totlen; 2112 len -= totlen; 2113 } 2114 2115 resubmit: 2116 /* Setup a new transfer. */ 2117 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 2118 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 2119 (void)usbd_transfer(xfer); 2120 } 2121 2122 static void 2123 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2124 { 2125 struct urtwn_tx_data *data = priv; 2126 struct urtwn_softc *sc = data->sc; 2127 struct ifnet *ifp = &sc->sc_if; 2128 usbd_pipe_handle pipe = data->pipe; 2129 int s; 2130 2131 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2132 device_xname(sc->sc_dev), __func__, status)); 2133 2134 mutex_enter(&sc->sc_tx_mtx); 2135 /* Put this Tx buffer back to our free list. */ 2136 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2137 mutex_exit(&sc->sc_tx_mtx); 2138 2139 s = splnet(); 2140 sc->tx_timer = 0; 2141 ifp->if_flags &= ~IFF_OACTIVE; 2142 2143 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2144 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2145 if (status == USBD_STALLED) 2146 usbd_clear_endpoint_stall_async(pipe); 2147 ifp->if_oerrors++; 2148 } 2149 splx(s); 2150 return; 2151 } 2152 2153 ifp->if_opackets++; 2154 urtwn_start(ifp); 2155 2156 splx(s); 2157 } 2158 2159 static int 2160 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2161 struct urtwn_tx_data *data) 2162 { 2163 struct ieee80211com *ic = &sc->sc_ic; 2164 struct ieee80211_frame *wh; 2165 struct ieee80211_key *k = NULL; 2166 struct r92c_tx_desc *txd; 2167 usbd_pipe_handle pipe; 2168 size_t i, padsize, xferlen; 2169 uint16_t seq, sum; 2170 uint8_t raid, type, tid, qid; 2171 int s, hasqos, error; 2172 2173 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2174 2175 wh = mtod(m, struct ieee80211_frame *); 2176 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2177 2178 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2179 k = ieee80211_crypto_encap(ic, ni, m); 2180 if (k == NULL) 2181 return ENOBUFS; 2182 2183 /* packet header may have moved, reset our local pointer */ 2184 wh = mtod(m, struct ieee80211_frame *); 2185 } 2186 2187 if (__predict_false(sc->sc_drvbpf != NULL)) { 2188 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2189 2190 tap->wt_flags = 0; 2191 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2192 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2193 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2194 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2195 2196 /* XXX: set tap->wt_rate? */ 2197 2198 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2199 } 2200 2201 if ((hasqos = ieee80211_has_qos(wh))) { 2202 /* data frames in 11n mode */ 2203 struct ieee80211_qosframe *qwh = (void *)wh; 2204 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2205 qid = TID_TO_WME_AC(tid); 2206 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2207 /* Use AC_VO for management frames. */ 2208 qid = WME_AC_VO; 2209 tid = 0; /* compiler happy */ 2210 } else { 2211 /* non-qos data frames */ 2212 tid = R92C_TXDW1_QSEL_BE; 2213 qid = WME_AC_BE; 2214 } 2215 2216 /* Get the USB pipe to use for this AC. */ 2217 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2218 2219 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2220 padsize = 8; 2221 else 2222 padsize = 0; 2223 2224 /* Fill Tx descriptor. */ 2225 txd = (struct r92c_tx_desc *)data->buf; 2226 memset(txd, 0, sizeof(*txd) + padsize); 2227 2228 txd->txdw0 |= htole32( 2229 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2230 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2231 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2232 2233 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2234 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2235 2236 /* fix pad field */ 2237 if (padsize > 0) { 2238 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2239 device_xname(sc->sc_dev), __func__, padsize)); 2240 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2241 } 2242 2243 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2244 type == IEEE80211_FC0_TYPE_DATA) { 2245 if (ic->ic_curmode == IEEE80211_MODE_11B) 2246 raid = R92C_RAID_11B; 2247 else 2248 raid = R92C_RAID_11BG; 2249 DPRINTFN(DBG_TX, 2250 ("%s: %s: data packet: tid=%d, raid=%d\n", 2251 device_xname(sc->sc_dev), __func__, tid, raid)); 2252 2253 txd->txdw1 |= htole32( 2254 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2255 SM(R92C_TXDW1_QSEL, tid) | 2256 SM(R92C_TXDW1_RAID, raid) | 2257 R92C_TXDW1_AGGBK); 2258 2259 if (hasqos) { 2260 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2261 } 2262 2263 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2264 /* for 11g */ 2265 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2266 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2267 R92C_TXDW4_HWRTSEN); 2268 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2269 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2270 R92C_TXDW4_HWRTSEN); 2271 } 2272 } 2273 /* Send RTS at OFDM24. */ 2274 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2275 txd->txdw5 |= htole32(0x0001ff00); 2276 /* Send data at OFDM54. */ 2277 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2278 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2279 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2280 device_xname(sc->sc_dev), __func__)); 2281 txd->txdw1 |= htole32( 2282 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2283 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2284 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2285 2286 /* Force CCK1. */ 2287 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2288 /* Use 1Mbps */ 2289 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2290 } else { 2291 /* broadcast or multicast packets */ 2292 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2293 device_xname(sc->sc_dev), __func__)); 2294 txd->txdw1 |= htole32( 2295 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2296 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2297 2298 /* Force CCK1. */ 2299 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2300 /* Use 1Mbps */ 2301 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2302 } 2303 2304 /* Set sequence number */ 2305 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2306 txd->txdseq |= htole16(seq); 2307 2308 if (!hasqos) { 2309 /* Use HW sequence numbering for non-QoS frames. */ 2310 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2311 txd->txdseq |= htole16(0x8000); /* WTF? */ 2312 } 2313 2314 /* Compute Tx descriptor checksum. */ 2315 sum = 0; 2316 for (i = 0; i < sizeof(*txd) / 2; i++) 2317 sum ^= ((uint16_t *)txd)[i]; 2318 txd->txdsum = sum; /* NB: already little endian. */ 2319 2320 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2321 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2322 2323 s = splnet(); 2324 data->pipe = pipe; 2325 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2326 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2327 urtwn_txeof); 2328 error = usbd_transfer(data->xfer); 2329 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2330 error != USBD_IN_PROGRESS)) { 2331 splx(s); 2332 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2333 device_xname(sc->sc_dev), __func__, error)); 2334 return error; 2335 } 2336 splx(s); 2337 return 0; 2338 } 2339 2340 static void 2341 urtwn_start(struct ifnet *ifp) 2342 { 2343 struct urtwn_softc *sc = ifp->if_softc; 2344 struct ieee80211com *ic = &sc->sc_ic; 2345 struct urtwn_tx_data *data; 2346 struct ether_header *eh; 2347 struct ieee80211_node *ni; 2348 struct mbuf *m; 2349 2350 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2351 2352 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2353 return; 2354 2355 data = NULL; 2356 for (;;) { 2357 mutex_enter(&sc->sc_tx_mtx); 2358 if (data == NULL && !TAILQ_EMPTY(&sc->tx_free_list)) { 2359 data = TAILQ_FIRST(&sc->tx_free_list); 2360 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2361 } 2362 mutex_exit(&sc->sc_tx_mtx); 2363 2364 if (data == NULL) { 2365 ifp->if_flags |= IFF_OACTIVE; 2366 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2367 device_xname(sc->sc_dev))); 2368 return; 2369 } 2370 2371 /* Send pending management frames first. */ 2372 IF_DEQUEUE(&ic->ic_mgtq, m); 2373 if (m != NULL) { 2374 ni = (void *)m->m_pkthdr.rcvif; 2375 m->m_pkthdr.rcvif = NULL; 2376 goto sendit; 2377 } 2378 if (ic->ic_state != IEEE80211_S_RUN) 2379 break; 2380 2381 /* Encapsulate and send data frames. */ 2382 IFQ_DEQUEUE(&ifp->if_snd, m); 2383 if (m == NULL) 2384 break; 2385 2386 if (m->m_len < (int)sizeof(*eh) && 2387 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2388 ifp->if_oerrors++; 2389 continue; 2390 } 2391 eh = mtod(m, struct ether_header *); 2392 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2393 if (ni == NULL) { 2394 m_freem(m); 2395 ifp->if_oerrors++; 2396 continue; 2397 } 2398 2399 bpf_mtap(ifp, m); 2400 2401 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2402 ieee80211_free_node(ni); 2403 ifp->if_oerrors++; 2404 continue; 2405 } 2406 sendit: 2407 bpf_mtap3(ic->ic_rawbpf, m); 2408 2409 if (urtwn_tx(sc, m, ni, data) != 0) { 2410 m_freem(m); 2411 ieee80211_free_node(ni); 2412 ifp->if_oerrors++; 2413 continue; 2414 } 2415 data = NULL; 2416 m_freem(m); 2417 ieee80211_free_node(ni); 2418 sc->tx_timer = 5; 2419 ifp->if_timer = 1; 2420 } 2421 2422 /* Return the Tx buffer to the free list */ 2423 mutex_enter(&sc->sc_tx_mtx); 2424 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2425 mutex_exit(&sc->sc_tx_mtx); 2426 } 2427 2428 static void 2429 urtwn_watchdog(struct ifnet *ifp) 2430 { 2431 struct urtwn_softc *sc = ifp->if_softc; 2432 2433 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2434 2435 ifp->if_timer = 0; 2436 2437 if (sc->tx_timer > 0) { 2438 if (--sc->tx_timer == 0) { 2439 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2440 /* urtwn_init(ifp); XXX needs a process context! */ 2441 ifp->if_oerrors++; 2442 return; 2443 } 2444 ifp->if_timer = 1; 2445 } 2446 ieee80211_watchdog(&sc->sc_ic); 2447 } 2448 2449 static int 2450 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2451 { 2452 struct urtwn_softc *sc = ifp->if_softc; 2453 struct ieee80211com *ic = &sc->sc_ic; 2454 int s, error = 0; 2455 2456 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2457 device_xname(sc->sc_dev), __func__, cmd, data)); 2458 2459 s = splnet(); 2460 2461 switch (cmd) { 2462 case SIOCSIFFLAGS: 2463 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2464 break; 2465 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2466 case IFF_UP | IFF_RUNNING: 2467 break; 2468 case IFF_UP: 2469 urtwn_init(ifp); 2470 break; 2471 case IFF_RUNNING: 2472 urtwn_stop(ifp, 1); 2473 break; 2474 case 0: 2475 break; 2476 } 2477 break; 2478 2479 case SIOCADDMULTI: 2480 case SIOCDELMULTI: 2481 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2482 /* setup multicast filter, etc */ 2483 error = 0; 2484 } 2485 break; 2486 2487 default: 2488 error = ieee80211_ioctl(ic, cmd, data); 2489 break; 2490 } 2491 if (error == ENETRESET) { 2492 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2493 (IFF_UP | IFF_RUNNING) && 2494 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2495 urtwn_init(ifp); 2496 } 2497 error = 0; 2498 } 2499 2500 splx(s); 2501 2502 return (error); 2503 } 2504 2505 static int 2506 urtwn_power_on(struct urtwn_softc *sc) 2507 { 2508 uint32_t reg; 2509 int ntries; 2510 2511 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2512 2513 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2514 2515 /* Wait for autoload done bit. */ 2516 for (ntries = 0; ntries < 1000; ntries++) { 2517 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2518 break; 2519 DELAY(5); 2520 } 2521 if (ntries == 1000) { 2522 aprint_error_dev(sc->sc_dev, 2523 "timeout waiting for chip autoload\n"); 2524 return (ETIMEDOUT); 2525 } 2526 2527 /* Unlock ISO/CLK/Power control register. */ 2528 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2529 /* Move SPS into PWM mode. */ 2530 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2531 DELAY(100); 2532 2533 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2534 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2535 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2536 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2537 DELAY(100); 2538 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2539 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2540 ~R92C_SYS_ISO_CTRL_MD2PP); 2541 } 2542 2543 /* Auto enable WLAN. */ 2544 urtwn_write_2(sc, R92C_APS_FSMCO, 2545 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2546 for (ntries = 0; ntries < 1000; ntries++) { 2547 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2548 R92C_APS_FSMCO_APFM_ONMAC)) 2549 break; 2550 DELAY(5); 2551 } 2552 if (ntries == 1000) { 2553 aprint_error_dev(sc->sc_dev, 2554 "timeout waiting for MAC auto ON\n"); 2555 return (ETIMEDOUT); 2556 } 2557 2558 /* Enable radio, GPIO and LED functions. */ 2559 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2560 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2561 urtwn_write_2(sc, R92C_APS_FSMCO, 2562 R92C_APS_FSMCO_AFSM_HSUS | 2563 R92C_APS_FSMCO_PDN_EN | 2564 R92C_APS_FSMCO_PFM_ALDN); 2565 2566 /* Release RF digital isolation. */ 2567 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2568 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2569 2570 /* Initialize MAC. */ 2571 urtwn_write_1(sc, R92C_APSD_CTRL, 2572 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2573 for (ntries = 0; ntries < 200; ntries++) { 2574 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2575 R92C_APSD_CTRL_OFF_STATUS)) 2576 break; 2577 DELAY(5); 2578 } 2579 if (ntries == 200) { 2580 aprint_error_dev(sc->sc_dev, 2581 "timeout waiting for MAC initialization\n"); 2582 return (ETIMEDOUT); 2583 } 2584 2585 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2586 reg = urtwn_read_2(sc, R92C_CR); 2587 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2588 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2589 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2590 R92C_CR_ENSEC; 2591 urtwn_write_2(sc, R92C_CR, reg); 2592 2593 urtwn_write_1(sc, 0xfe10, 0x19); 2594 return (0); 2595 } 2596 2597 static int 2598 urtwn_llt_init(struct urtwn_softc *sc) 2599 { 2600 size_t i; 2601 int error; 2602 2603 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2604 2605 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2606 2607 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2608 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2609 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2610 return (error); 2611 } 2612 /* NB: 0xff indicates end-of-list. */ 2613 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2614 return (error); 2615 /* 2616 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2617 * as ring buffer. 2618 */ 2619 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2620 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2621 return (error); 2622 } 2623 /* Make the last page point to the beginning of the ring buffer. */ 2624 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2625 return (error); 2626 } 2627 2628 static void 2629 urtwn_fw_reset(struct urtwn_softc *sc) 2630 { 2631 uint16_t reg; 2632 int ntries; 2633 2634 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2635 2636 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2637 2638 /* Tell 8051 to reset itself. */ 2639 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2640 2641 /* Wait until 8051 resets by itself. */ 2642 for (ntries = 0; ntries < 100; ntries++) { 2643 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2644 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2645 return; 2646 DELAY(50); 2647 } 2648 /* Force 8051 reset. */ 2649 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2650 } 2651 2652 static int 2653 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2654 { 2655 uint32_t reg; 2656 int off, mlen, error = 0; 2657 2658 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2659 device_xname(sc->sc_dev), __func__, page, buf, len)); 2660 2661 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2662 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2663 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2664 2665 off = R92C_FW_START_ADDR; 2666 while (len > 0) { 2667 if (len > 196) 2668 mlen = 196; 2669 else if (len > 4) 2670 mlen = 4; 2671 else 2672 mlen = 1; 2673 error = urtwn_write_region(sc, off, buf, mlen); 2674 if (error != 0) 2675 break; 2676 off += mlen; 2677 buf += mlen; 2678 len -= mlen; 2679 } 2680 return (error); 2681 } 2682 2683 static int 2684 urtwn_load_firmware(struct urtwn_softc *sc) 2685 { 2686 firmware_handle_t fwh; 2687 const struct r92c_fw_hdr *hdr; 2688 const char *name; 2689 u_char *fw, *ptr; 2690 size_t len; 2691 uint32_t reg; 2692 int mlen, ntries, page, error; 2693 2694 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2695 2696 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2697 2698 /* Read firmware image from the filesystem. */ 2699 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2700 URTWN_CHIP_UMC_A_CUT) 2701 name = "rtl8192cfwU.bin"; 2702 else 2703 name = "rtl8192cfw.bin"; 2704 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 2705 aprint_error_dev(sc->sc_dev, 2706 "failed loadfirmware of file %s (error %d)\n", name, error); 2707 return (error); 2708 } 2709 len = firmware_get_size(fwh); 2710 fw = firmware_malloc(len); 2711 if (fw == NULL) { 2712 aprint_error_dev(sc->sc_dev, 2713 "failed to allocate firmware memory\n"); 2714 firmware_close(fwh); 2715 return (ENOMEM); 2716 } 2717 error = firmware_read(fwh, 0, fw, len); 2718 firmware_close(fwh); 2719 if (error != 0) { 2720 aprint_error_dev(sc->sc_dev, 2721 "failed to read firmware (error %d)\n", error); 2722 firmware_free(fw, 0); 2723 return (error); 2724 } 2725 2726 ptr = fw; 2727 hdr = (const struct r92c_fw_hdr *)ptr; 2728 /* Check if there is a valid FW header and skip it. */ 2729 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2730 (le16toh(hdr->signature) >> 4) == 0x92c) { 2731 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2732 device_xname(sc->sc_dev), __func__, 2733 le16toh(hdr->version), le16toh(hdr->subversion), 2734 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2735 ptr += sizeof(*hdr); 2736 len -= sizeof(*hdr); 2737 } 2738 2739 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2740 urtwn_fw_reset(sc); 2741 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2742 } 2743 2744 /* download enabled */ 2745 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2746 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2747 R92C_SYS_FUNC_EN_CPUEN); 2748 urtwn_write_1(sc, R92C_MCUFWDL, 2749 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2750 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2751 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2752 2753 /* download firmware */ 2754 for (page = 0; len > 0; page++) { 2755 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2756 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2757 if (error != 0) { 2758 aprint_error_dev(sc->sc_dev, 2759 "could not load firmware page %d\n", page); 2760 goto fail; 2761 } 2762 ptr += mlen; 2763 len -= mlen; 2764 } 2765 2766 /* download disable */ 2767 urtwn_write_1(sc, R92C_MCUFWDL, 2768 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2769 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2770 2771 /* Wait for checksum report. */ 2772 for (ntries = 0; ntries < 1000; ntries++) { 2773 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2774 break; 2775 DELAY(5); 2776 } 2777 if (ntries == 1000) { 2778 aprint_error_dev(sc->sc_dev, 2779 "timeout waiting for checksum report\n"); 2780 error = ETIMEDOUT; 2781 goto fail; 2782 } 2783 2784 /* Wait for firmware readiness. */ 2785 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2786 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2787 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2788 for (ntries = 0; ntries < 1000; ntries++) { 2789 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2790 break; 2791 DELAY(5); 2792 } 2793 if (ntries == 1000) { 2794 aprint_error_dev(sc->sc_dev, 2795 "timeout waiting for firmware readiness\n"); 2796 error = ETIMEDOUT; 2797 goto fail; 2798 } 2799 fail: 2800 firmware_free(fw, 0); 2801 return (error); 2802 } 2803 2804 static int 2805 urtwn_dma_init(struct urtwn_softc *sc) 2806 { 2807 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2808 uint32_t reg; 2809 int error; 2810 2811 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2812 2813 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2814 2815 /* Initialize LLT table. */ 2816 error = urtwn_llt_init(sc); 2817 if (error != 0) 2818 return (error); 2819 2820 /* Get Tx queues to USB endpoints mapping. */ 2821 hashq = hasnq = haslq = 0; 2822 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2823 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2824 device_xname(sc->sc_dev), __func__, reg)); 2825 if (MS(reg, R92C_USB_EP_HQ) != 0) 2826 hashq = 1; 2827 if (MS(reg, R92C_USB_EP_NQ) != 0) 2828 hasnq = 1; 2829 if (MS(reg, R92C_USB_EP_LQ) != 0) 2830 haslq = 1; 2831 nqueues = hashq + hasnq + haslq; 2832 if (nqueues == 0) 2833 return (EIO); 2834 /* Get the number of pages for each queue. */ 2835 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2836 /* The remaining pages are assigned to the high priority queue. */ 2837 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2838 2839 /* Set number of pages for normal priority queue. */ 2840 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2841 urtwn_write_4(sc, R92C_RQPN, 2842 /* Set number of pages for public queue. */ 2843 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2844 /* Set number of pages for high priority queue. */ 2845 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2846 /* Set number of pages for low priority queue. */ 2847 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2848 /* Load values. */ 2849 R92C_RQPN_LD); 2850 2851 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2852 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2853 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2854 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2855 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2856 2857 /* Set queue to USB pipe mapping. */ 2858 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2859 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2860 if (nqueues == 1) { 2861 if (hashq) { 2862 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2863 } else if (hasnq) { 2864 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2865 } else { 2866 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2867 } 2868 } else if (nqueues == 2) { 2869 /* All 2-endpoints configs have a high priority queue. */ 2870 if (!hashq) { 2871 return (EIO); 2872 } 2873 if (hasnq) { 2874 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2875 } else { 2876 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2877 } 2878 } else { 2879 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2880 } 2881 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2882 2883 /* Set Tx/Rx transfer page boundary. */ 2884 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2885 2886 /* Set Tx/Rx transfer page size. */ 2887 urtwn_write_1(sc, R92C_PBP, 2888 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2889 return (0); 2890 } 2891 2892 static void 2893 urtwn_mac_init(struct urtwn_softc *sc) 2894 { 2895 size_t i; 2896 2897 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2898 2899 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2900 2901 /* Write MAC initialization values. */ 2902 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 2903 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2904 } 2905 2906 static void 2907 urtwn_bb_init(struct urtwn_softc *sc) 2908 { 2909 const struct urtwn_bb_prog *prog; 2910 uint32_t reg; 2911 size_t i; 2912 2913 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2914 2915 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2916 2917 /* Enable BB and RF. */ 2918 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2919 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2920 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2921 R92C_SYS_FUNC_EN_DIO_RF); 2922 2923 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2924 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2925 2926 urtwn_write_1(sc, R92C_RF_CTRL, 2927 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2928 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2929 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2930 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2931 2932 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2933 urtwn_write_1(sc, 0x15, 0xe9); 2934 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2935 2936 /* Select BB programming based on board type. */ 2937 if (!(sc->chip & URTWN_CHIP_92C)) { 2938 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2939 prog = &rtl8188ce_bb_prog; 2940 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2941 prog = &rtl8188ru_bb_prog; 2942 } else { 2943 prog = &rtl8188cu_bb_prog; 2944 } 2945 } else { 2946 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2947 prog = &rtl8192ce_bb_prog; 2948 } else { 2949 prog = &rtl8192cu_bb_prog; 2950 } 2951 } 2952 /* Write BB initialization values. */ 2953 for (i = 0; i < prog->count; i++) { 2954 /* additional delay depend on registers */ 2955 switch (prog->regs[i]) { 2956 case 0xfe: 2957 usbd_delay_ms(sc->sc_udev, 50); 2958 break; 2959 case 0xfd: 2960 usbd_delay_ms(sc->sc_udev, 5); 2961 break; 2962 case 0xfc: 2963 usbd_delay_ms(sc->sc_udev, 1); 2964 break; 2965 case 0xfb: 2966 DELAY(50); 2967 break; 2968 case 0xfa: 2969 DELAY(5); 2970 break; 2971 case 0xf9: 2972 DELAY(1); 2973 break; 2974 } 2975 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2976 DELAY(1); 2977 } 2978 2979 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2980 /* 8192C 1T only configuration. */ 2981 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2982 reg = (reg & ~0x00000003) | 0x2; 2983 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2984 2985 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2986 reg = (reg & ~0x00300033) | 0x00200022; 2987 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2988 2989 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2990 reg = (reg & ~0xff000000) | (0x45 << 24); 2991 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2992 2993 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2994 reg = (reg & ~0x000000ff) | 0x23; 2995 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2996 2997 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2998 reg = (reg & ~0x00000030) | (1 << 4); 2999 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3000 3001 reg = urtwn_bb_read(sc, 0xe74); 3002 reg = (reg & ~0x0c000000) | (2 << 26); 3003 urtwn_bb_write(sc, 0xe74, reg); 3004 reg = urtwn_bb_read(sc, 0xe78); 3005 reg = (reg & ~0x0c000000) | (2 << 26); 3006 urtwn_bb_write(sc, 0xe78, reg); 3007 reg = urtwn_bb_read(sc, 0xe7c); 3008 reg = (reg & ~0x0c000000) | (2 << 26); 3009 urtwn_bb_write(sc, 0xe7c, reg); 3010 reg = urtwn_bb_read(sc, 0xe80); 3011 reg = (reg & ~0x0c000000) | (2 << 26); 3012 urtwn_bb_write(sc, 0xe80, reg); 3013 reg = urtwn_bb_read(sc, 0xe88); 3014 reg = (reg & ~0x0c000000) | (2 << 26); 3015 urtwn_bb_write(sc, 0xe88, reg); 3016 } 3017 3018 /* Write AGC values. */ 3019 for (i = 0; i < prog->agccount; i++) { 3020 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3021 DELAY(1); 3022 } 3023 3024 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3025 R92C_HSSI_PARAM2_CCK_HIPWR) { 3026 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3027 } 3028 } 3029 3030 static void 3031 urtwn_rf_init(struct urtwn_softc *sc) 3032 { 3033 const struct urtwn_rf_prog *prog; 3034 uint32_t reg, mask, saved; 3035 size_t i, j, idx; 3036 3037 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3038 3039 /* Select RF programming based on board type. */ 3040 if (!(sc->chip & URTWN_CHIP_92C)) { 3041 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3042 prog = rtl8188ce_rf_prog; 3043 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3044 prog = rtl8188ru_rf_prog; 3045 } else { 3046 prog = rtl8188cu_rf_prog; 3047 } 3048 } else { 3049 prog = rtl8192ce_rf_prog; 3050 } 3051 3052 for (i = 0; i < sc->nrxchains; i++) { 3053 /* Save RF_ENV control type. */ 3054 idx = i / 2; 3055 mask = 0xffffU << ((i % 2) * 16); 3056 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3057 3058 /* Set RF_ENV enable. */ 3059 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3060 reg |= 0x100000; 3061 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3062 DELAY(1); 3063 3064 /* Set RF_ENV output high. */ 3065 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3066 reg |= 0x10; 3067 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3068 DELAY(1); 3069 3070 /* Set address and data lengths of RF registers. */ 3071 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3072 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3073 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3074 DELAY(1); 3075 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3076 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3077 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3078 DELAY(1); 3079 3080 /* Write RF initialization values for this chain. */ 3081 for (j = 0; j < prog[i].count; j++) { 3082 if (prog[i].regs[j] >= 0xf9 && 3083 prog[i].regs[j] <= 0xfe) { 3084 /* 3085 * These are fake RF registers offsets that 3086 * indicate a delay is required. 3087 */ 3088 usbd_delay_ms(sc->sc_udev, 50); 3089 continue; 3090 } 3091 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3092 DELAY(1); 3093 } 3094 3095 /* Restore RF_ENV control type. */ 3096 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3097 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3098 } 3099 3100 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3101 URTWN_CHIP_UMC_A_CUT) { 3102 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3103 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3104 } 3105 3106 /* Cache RF register CHNLBW. */ 3107 for (i = 0; i < 2; i++) { 3108 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3109 } 3110 } 3111 3112 static void 3113 urtwn_cam_init(struct urtwn_softc *sc) 3114 { 3115 uint32_t content, command; 3116 uint8_t idx; 3117 size_t i; 3118 3119 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3120 3121 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3122 3123 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3124 content = (idx & 3) 3125 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3126 | R92C_CAM_VALID; 3127 3128 command = R92C_CAMCMD_POLLING 3129 | R92C_CAMCMD_WRITE 3130 | R92C_CAM_CTL0(idx); 3131 3132 urtwn_write_4(sc, R92C_CAMWRITE, content); 3133 urtwn_write_4(sc, R92C_CAMCMD, command); 3134 } 3135 3136 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3137 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3138 if (i == 0) { 3139 content = (idx & 3) 3140 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3141 | R92C_CAM_VALID; 3142 } else { 3143 content = 0; 3144 } 3145 3146 command = R92C_CAMCMD_POLLING 3147 | R92C_CAMCMD_WRITE 3148 | R92C_CAM_CTL0(idx) 3149 | i; 3150 3151 urtwn_write_4(sc, R92C_CAMWRITE, content); 3152 urtwn_write_4(sc, R92C_CAMCMD, command); 3153 } 3154 } 3155 3156 /* Invalidate all CAM entries. */ 3157 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3158 } 3159 3160 static void 3161 urtwn_pa_bias_init(struct urtwn_softc *sc) 3162 { 3163 uint8_t reg; 3164 size_t i; 3165 3166 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3167 3168 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3169 3170 for (i = 0; i < sc->nrxchains; i++) { 3171 if (sc->pa_setting & (1U << i)) 3172 continue; 3173 3174 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3175 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3176 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3177 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3178 } 3179 if (!(sc->pa_setting & 0x10)) { 3180 reg = urtwn_read_1(sc, 0x16); 3181 reg = (reg & ~0xf0) | 0x90; 3182 urtwn_write_1(sc, 0x16, reg); 3183 } 3184 } 3185 3186 static void 3187 urtwn_rxfilter_init(struct urtwn_softc *sc) 3188 { 3189 3190 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3191 3192 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3193 3194 /* Initialize Rx filter. */ 3195 /* TODO: use better filter for monitor mode. */ 3196 urtwn_write_4(sc, R92C_RCR, 3197 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3198 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3199 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3200 /* Accept all multicast frames. */ 3201 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3202 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3203 /* Accept all management frames. */ 3204 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3205 /* Reject all control frames. */ 3206 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3207 /* Accept all data frames. */ 3208 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3209 } 3210 3211 static void 3212 urtwn_edca_init(struct urtwn_softc *sc) 3213 { 3214 3215 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3216 3217 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3218 3219 /* set spec SIFS (used in NAV) */ 3220 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3221 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3222 3223 /* set SIFS CCK/OFDM */ 3224 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3225 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3226 3227 /* TXOP */ 3228 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3229 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3230 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3231 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3232 } 3233 3234 static void 3235 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3236 uint16_t power[URTWN_RIDX_COUNT]) 3237 { 3238 uint32_t reg; 3239 3240 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3241 __func__, chain)); 3242 3243 /* Write per-CCK rate Tx power. */ 3244 if (chain == 0) { 3245 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3246 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3247 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3248 3249 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3250 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3251 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3252 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3253 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3254 } else { 3255 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3256 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3257 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3258 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3259 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3260 3261 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3262 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3263 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3264 } 3265 /* Write per-OFDM rate Tx power. */ 3266 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3267 SM(R92C_TXAGC_RATE06, power[ 4]) | 3268 SM(R92C_TXAGC_RATE09, power[ 5]) | 3269 SM(R92C_TXAGC_RATE12, power[ 6]) | 3270 SM(R92C_TXAGC_RATE18, power[ 7])); 3271 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3272 SM(R92C_TXAGC_RATE24, power[ 8]) | 3273 SM(R92C_TXAGC_RATE36, power[ 9]) | 3274 SM(R92C_TXAGC_RATE48, power[10]) | 3275 SM(R92C_TXAGC_RATE54, power[11])); 3276 /* Write per-MCS Tx power. */ 3277 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3278 SM(R92C_TXAGC_MCS00, power[12]) | 3279 SM(R92C_TXAGC_MCS01, power[13]) | 3280 SM(R92C_TXAGC_MCS02, power[14]) | 3281 SM(R92C_TXAGC_MCS03, power[15])); 3282 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3283 SM(R92C_TXAGC_MCS04, power[16]) | 3284 SM(R92C_TXAGC_MCS05, power[17]) | 3285 SM(R92C_TXAGC_MCS06, power[18]) | 3286 SM(R92C_TXAGC_MCS07, power[19])); 3287 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3288 SM(R92C_TXAGC_MCS08, power[20]) | 3289 SM(R92C_TXAGC_MCS09, power[21]) | 3290 SM(R92C_TXAGC_MCS10, power[22]) | 3291 SM(R92C_TXAGC_MCS11, power[23])); 3292 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3293 SM(R92C_TXAGC_MCS12, power[24]) | 3294 SM(R92C_TXAGC_MCS13, power[25]) | 3295 SM(R92C_TXAGC_MCS14, power[26]) | 3296 SM(R92C_TXAGC_MCS15, power[27])); 3297 } 3298 3299 static void 3300 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 3301 uint16_t power[URTWN_RIDX_COUNT]) 3302 { 3303 struct r92c_rom *rom = &sc->rom; 3304 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3305 const struct urtwn_txpwr *base; 3306 int ridx, group; 3307 3308 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3309 device_xname(sc->sc_dev), __func__, chain, chan)); 3310 3311 /* Determine channel group. */ 3312 if (chan <= 3) { 3313 group = 0; 3314 } else if (chan <= 9) { 3315 group = 1; 3316 } else { 3317 group = 2; 3318 } 3319 3320 /* Get original Tx power based on board type and RF chain. */ 3321 if (!(sc->chip & URTWN_CHIP_92C)) { 3322 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3323 base = &rtl8188ru_txagc[chain]; 3324 } else { 3325 base = &rtl8192cu_txagc[chain]; 3326 } 3327 } else { 3328 base = &rtl8192cu_txagc[chain]; 3329 } 3330 3331 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3332 if (sc->regulatory == 0) { 3333 for (ridx = 0; ridx <= 3; ridx++) { 3334 power[ridx] = base->pwr[0][ridx]; 3335 } 3336 } 3337 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3338 if (sc->regulatory == 3) { 3339 power[ridx] = base->pwr[0][ridx]; 3340 /* Apply vendor limits. */ 3341 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3342 maxpow = rom->ht40_max_pwr[group]; 3343 } else { 3344 maxpow = rom->ht20_max_pwr[group]; 3345 } 3346 maxpow = (maxpow >> (chain * 4)) & 0xf; 3347 if (power[ridx] > maxpow) { 3348 power[ridx] = maxpow; 3349 } 3350 } else if (sc->regulatory == 1) { 3351 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3352 power[ridx] = base->pwr[group][ridx]; 3353 } 3354 } else if (sc->regulatory != 2) { 3355 power[ridx] = base->pwr[0][ridx]; 3356 } 3357 } 3358 3359 /* Compute per-CCK rate Tx power. */ 3360 cckpow = rom->cck_tx_pwr[chain][group]; 3361 for (ridx = 0; ridx <= 3; ridx++) { 3362 power[ridx] += cckpow; 3363 if (power[ridx] > R92C_MAX_TX_PWR) { 3364 power[ridx] = R92C_MAX_TX_PWR; 3365 } 3366 } 3367 3368 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3369 if (sc->ntxchains > 1) { 3370 /* Apply reduction for 2 spatial streams. */ 3371 diff = rom->ht40_2s_tx_pwr_diff[group]; 3372 diff = (diff >> (chain * 4)) & 0xf; 3373 htpow = (htpow > diff) ? htpow - diff : 0; 3374 } 3375 3376 /* Compute per-OFDM rate Tx power. */ 3377 diff = rom->ofdm_tx_pwr_diff[group]; 3378 diff = (diff >> (chain * 4)) & 0xf; 3379 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3380 for (ridx = 4; ridx <= 11; ridx++) { 3381 power[ridx] += ofdmpow; 3382 if (power[ridx] > R92C_MAX_TX_PWR) { 3383 power[ridx] = R92C_MAX_TX_PWR; 3384 } 3385 } 3386 3387 /* Compute per-MCS Tx power. */ 3388 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3389 diff = rom->ht20_tx_pwr_diff[group]; 3390 diff = (diff >> (chain * 4)) & 0xf; 3391 htpow += diff; /* HT40->HT20 correction. */ 3392 } 3393 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3394 power[ridx] += htpow; 3395 if (power[ridx] > R92C_MAX_TX_PWR) { 3396 power[ridx] = R92C_MAX_TX_PWR; 3397 } 3398 } 3399 #ifdef URTWN_DEBUG 3400 if (urtwn_debug & DBG_RF) { 3401 /* Dump per-rate Tx power values. */ 3402 printf("%s: %s: Tx power for chain %zd:\n", 3403 device_xname(sc->sc_dev), __func__, chain); 3404 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3405 printf("%s: %s: Rate %d = %u\n", 3406 device_xname(sc->sc_dev), __func__, ridx, 3407 power[ridx]); 3408 } 3409 } 3410 #endif 3411 } 3412 3413 static void 3414 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3415 { 3416 uint16_t power[URTWN_RIDX_COUNT]; 3417 size_t i; 3418 3419 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3420 3421 for (i = 0; i < sc->ntxchains; i++) { 3422 /* Compute per-rate Tx power values. */ 3423 urtwn_get_txpower(sc, i, chan, ht40m, power); 3424 /* Write per-rate Tx power values to hardware. */ 3425 urtwn_write_txpower(sc, i, power); 3426 } 3427 } 3428 3429 static void 3430 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3431 { 3432 struct ieee80211com *ic = &sc->sc_ic; 3433 u_int chan; 3434 size_t i; 3435 3436 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3437 3438 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3439 __func__, chan)); 3440 3441 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3442 3443 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3444 chan += 2; 3445 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3446 chan -= 2; 3447 } 3448 3449 /* Set Tx power for this new channel. */ 3450 urtwn_set_txpower(sc, chan, ht40m); 3451 3452 for (i = 0; i < sc->nrxchains; i++) { 3453 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3454 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3455 } 3456 3457 if (ht40m) { 3458 /* Is secondary channel below or above primary? */ 3459 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3460 uint32_t reg; 3461 3462 urtwn_write_1(sc, R92C_BWOPMODE, 3463 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3464 3465 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3466 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3467 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3468 3469 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3470 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3471 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3472 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3473 3474 /* Set CCK side band. */ 3475 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3476 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3477 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3478 3479 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3480 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3481 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3482 3483 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3484 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3485 ~R92C_FPGA0_ANAPARAM2_CBW20); 3486 3487 reg = urtwn_bb_read(sc, 0x818); 3488 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3489 urtwn_bb_write(sc, 0x818, reg); 3490 3491 /* Select 40MHz bandwidth. */ 3492 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3493 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3494 } else { 3495 urtwn_write_1(sc, R92C_BWOPMODE, 3496 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3497 3498 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3499 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3500 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3501 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3502 3503 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3504 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3505 R92C_FPGA0_ANAPARAM2_CBW20); 3506 3507 /* Select 20MHz bandwidth. */ 3508 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3509 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3510 } 3511 } 3512 3513 static void 3514 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3515 { 3516 3517 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3518 __func__, inited)); 3519 3520 /* TODO */ 3521 } 3522 3523 static void 3524 urtwn_lc_calib(struct urtwn_softc *sc) 3525 { 3526 uint32_t rf_ac[2]; 3527 uint8_t txmode; 3528 size_t i; 3529 3530 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3531 3532 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3533 3534 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3535 if ((txmode & 0x70) != 0) { 3536 /* Disable all continuous Tx. */ 3537 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3538 3539 /* Set RF mode to standby mode. */ 3540 for (i = 0; i < sc->nrxchains; i++) { 3541 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3542 urtwn_rf_write(sc, i, R92C_RF_AC, 3543 RW(rf_ac[i], R92C_RF_AC_MODE, 3544 R92C_RF_AC_MODE_STANDBY)); 3545 } 3546 } else { 3547 /* Block all Tx queues. */ 3548 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3549 } 3550 /* Start calibration. */ 3551 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3552 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3553 3554 /* Give calibration the time to complete. */ 3555 usbd_delay_ms(sc->sc_udev, 100); 3556 3557 /* Restore configuration. */ 3558 if ((txmode & 0x70) != 0) { 3559 /* Restore Tx mode. */ 3560 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3561 /* Restore RF mode. */ 3562 for (i = 0; i < sc->nrxchains; i++) { 3563 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3564 } 3565 } else { 3566 /* Unblock all Tx queues. */ 3567 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3568 } 3569 } 3570 3571 static void 3572 urtwn_temp_calib(struct urtwn_softc *sc) 3573 { 3574 int temp; 3575 3576 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3577 3578 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3579 3580 if (sc->thcal_state == 0) { 3581 /* Start measuring temperature. */ 3582 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3583 device_xname(sc->sc_dev), __func__)); 3584 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3585 sc->thcal_state = 1; 3586 return; 3587 } 3588 sc->thcal_state = 0; 3589 3590 /* Read measured temperature. */ 3591 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3592 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3593 __func__, temp)); 3594 if (temp == 0) /* Read failed, skip. */ 3595 return; 3596 3597 /* 3598 * Redo LC calibration if temperature changed significantly since 3599 * last calibration. 3600 */ 3601 if (sc->thcal_lctemp == 0) { 3602 /* First LC calibration is performed in urtwn_init(). */ 3603 sc->thcal_lctemp = temp; 3604 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3605 DPRINTFN(DBG_RF, 3606 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3607 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3608 temp)); 3609 urtwn_lc_calib(sc); 3610 /* Record temperature of last LC calibration. */ 3611 sc->thcal_lctemp = temp; 3612 } 3613 } 3614 3615 static int 3616 urtwn_init(struct ifnet *ifp) 3617 { 3618 struct urtwn_softc *sc = ifp->if_softc; 3619 struct ieee80211com *ic = &sc->sc_ic; 3620 struct urtwn_rx_data *data; 3621 uint32_t reg; 3622 size_t i; 3623 int error; 3624 3625 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3626 3627 urtwn_stop(ifp, 0); 3628 3629 mutex_enter(&sc->sc_write_mtx); 3630 3631 mutex_enter(&sc->sc_task_mtx); 3632 /* Init host async commands ring. */ 3633 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3634 mutex_exit(&sc->sc_task_mtx); 3635 3636 mutex_enter(&sc->sc_fwcmd_mtx); 3637 /* Init firmware commands ring. */ 3638 sc->fwcur = 0; 3639 mutex_exit(&sc->sc_fwcmd_mtx); 3640 3641 /* Allocate Tx/Rx buffers. */ 3642 error = urtwn_alloc_rx_list(sc); 3643 if (error != 0) { 3644 aprint_error_dev(sc->sc_dev, 3645 "could not allocate Rx buffers\n"); 3646 goto fail; 3647 } 3648 error = urtwn_alloc_tx_list(sc); 3649 if (error != 0) { 3650 aprint_error_dev(sc->sc_dev, 3651 "could not allocate Tx buffers\n"); 3652 goto fail; 3653 } 3654 3655 /* Power on adapter. */ 3656 error = urtwn_power_on(sc); 3657 if (error != 0) 3658 goto fail; 3659 3660 /* Initialize DMA. */ 3661 error = urtwn_dma_init(sc); 3662 if (error != 0) 3663 goto fail; 3664 3665 /* Set info size in Rx descriptors (in 64-bit words). */ 3666 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3667 3668 /* Init interrupts. */ 3669 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3670 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3671 3672 /* Set MAC address. */ 3673 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3674 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3675 3676 /* Set initial network type. */ 3677 reg = urtwn_read_4(sc, R92C_CR); 3678 switch (ic->ic_opmode) { 3679 case IEEE80211_M_STA: 3680 default: 3681 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3682 break; 3683 3684 case IEEE80211_M_IBSS: 3685 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3686 break; 3687 } 3688 urtwn_write_4(sc, R92C_CR, reg); 3689 3690 /* Set response rate */ 3691 reg = urtwn_read_4(sc, R92C_RRSR); 3692 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3693 urtwn_write_4(sc, R92C_RRSR, reg); 3694 3695 /* SIFS (used in NAV) */ 3696 urtwn_write_2(sc, R92C_SPEC_SIFS, 3697 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3698 3699 /* Set short/long retry limits. */ 3700 urtwn_write_2(sc, R92C_RL, 3701 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3702 3703 /* Initialize EDCA parameters. */ 3704 urtwn_edca_init(sc); 3705 3706 /* Setup rate fallback. */ 3707 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3708 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3709 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3710 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3711 3712 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3713 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3714 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3715 /* Set ACK timeout. */ 3716 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3717 3718 /* Setup USB aggregation. */ 3719 /* Tx */ 3720 reg = urtwn_read_4(sc, R92C_TDECTRL); 3721 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3722 urtwn_write_4(sc, R92C_TDECTRL, reg); 3723 /* Rx */ 3724 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3725 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3726 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3727 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3728 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3729 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3730 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3731 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3732 3733 /* Initialize beacon parameters. */ 3734 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3735 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3736 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3737 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3738 3739 /* Setup AMPDU aggregation. */ 3740 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3741 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3742 urtwn_write_2(sc, 0x4ca, 0x0708); 3743 3744 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3745 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3746 3747 /* Load 8051 microcode. */ 3748 error = urtwn_load_firmware(sc); 3749 if (error != 0) 3750 goto fail; 3751 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3752 3753 /* Initialize MAC/BB/RF blocks. */ 3754 /* 3755 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 3756 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 3757 * XXX: This setting should be removed from rtl8192cu_mac[]. 3758 */ 3759 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 3760 urtwn_rxfilter_init(sc); // reset R92C_RCR 3761 urtwn_bb_init(sc); 3762 urtwn_rf_init(sc); 3763 3764 /* Turn CCK and OFDM blocks on. */ 3765 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3766 reg |= R92C_RFMOD_CCK_EN; 3767 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3768 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3769 reg |= R92C_RFMOD_OFDM_EN; 3770 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3771 3772 /* Clear per-station keys table. */ 3773 urtwn_cam_init(sc); 3774 3775 /* Enable hardware sequence numbering. */ 3776 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3777 3778 /* Perform LO and IQ calibrations. */ 3779 urtwn_iq_calib(sc, sc->iqk_inited); 3780 sc->iqk_inited = true; 3781 3782 /* Perform LC calibration. */ 3783 urtwn_lc_calib(sc); 3784 3785 /* Fix USB interference issue. */ 3786 urtwn_write_1(sc, 0xfe40, 0xe0); 3787 urtwn_write_1(sc, 0xfe41, 0x8d); 3788 urtwn_write_1(sc, 0xfe42, 0x80); 3789 urtwn_write_4(sc, 0x20c, 0xfd0320); 3790 3791 urtwn_pa_bias_init(sc); 3792 3793 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3794 /* 1T1R */ 3795 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3796 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3797 } 3798 3799 /* Initialize GPIO setting. */ 3800 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3801 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3802 3803 /* Fix for lower temperature. */ 3804 urtwn_write_1(sc, 0x15, 0xe9); 3805 3806 /* Set default channel. */ 3807 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3808 3809 /* Queue Rx xfers. */ 3810 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3811 data = &sc->rx_data[i]; 3812 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3813 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3814 USBD_NO_TIMEOUT, urtwn_rxeof); 3815 error = usbd_transfer(data->xfer); 3816 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3817 error != USBD_IN_PROGRESS)) 3818 goto fail; 3819 } 3820 3821 /* We're ready to go. */ 3822 ifp->if_flags &= ~IFF_OACTIVE; 3823 ifp->if_flags |= IFF_RUNNING; 3824 3825 mutex_exit(&sc->sc_write_mtx); 3826 3827 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3828 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3829 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 3830 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3831 urtwn_wait_async(sc); 3832 3833 return (0); 3834 3835 fail: 3836 mutex_exit(&sc->sc_write_mtx); 3837 3838 urtwn_stop(ifp, 1); 3839 return (error); 3840 } 3841 3842 static void 3843 urtwn_stop(struct ifnet *ifp, int disable) 3844 { 3845 struct urtwn_softc *sc = ifp->if_softc; 3846 struct ieee80211com *ic = &sc->sc_ic; 3847 size_t i; 3848 int s; 3849 3850 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3851 3852 s = splusb(); 3853 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3854 urtwn_wait_async(sc); 3855 splx(s); 3856 3857 sc->tx_timer = 0; 3858 ifp->if_timer = 0; 3859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3860 3861 callout_stop(&sc->sc_scan_to); 3862 callout_stop(&sc->sc_calib_to); 3863 3864 /* Abort Tx. */ 3865 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3866 if (sc->tx_pipe[i] != NULL) 3867 usbd_abort_pipe(sc->tx_pipe[i]); 3868 } 3869 3870 /* Stop Rx pipe. */ 3871 usbd_abort_pipe(sc->rx_pipe); 3872 3873 /* Free Tx/Rx buffers. */ 3874 urtwn_free_tx_list(sc); 3875 urtwn_free_rx_list(sc); 3876 3877 if (disable) 3878 urtwn_chip_stop(sc); 3879 } 3880 3881 static int 3882 urtwn_reset(struct ifnet *ifp) 3883 { 3884 struct urtwn_softc *sc = ifp->if_softc; 3885 struct ieee80211com *ic = &sc->sc_ic; 3886 3887 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3888 return ENETRESET; 3889 3890 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3891 3892 return 0; 3893 } 3894 3895 static void 3896 urtwn_chip_stop(struct urtwn_softc *sc) 3897 { 3898 uint32_t reg; 3899 bool disabled = true; 3900 3901 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3902 3903 mutex_enter(&sc->sc_write_mtx); 3904 3905 /* 3906 * RF Off Sequence 3907 */ 3908 /* Pause MAC TX queue */ 3909 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3910 3911 /* Disable RF */ 3912 urtwn_rf_write(sc, 0, 0, 0); 3913 3914 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3915 3916 /* Reset BB state machine */ 3917 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3918 R92C_SYS_FUNC_EN_USBD | 3919 R92C_SYS_FUNC_EN_USBA | 3920 R92C_SYS_FUNC_EN_BB_GLB_RST); 3921 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3922 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3923 3924 /* 3925 * Reset digital sequence 3926 */ 3927 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3928 /* Reset MCU ready status */ 3929 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3930 /* If firmware in ram code, do reset */ 3931 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3932 urtwn_fw_reset(sc); 3933 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3934 } 3935 } 3936 3937 /* Reset MAC and Enable 8051 */ 3938 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3939 3940 /* Reset MCU ready status */ 3941 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3942 3943 if (disabled) { 3944 /* Disable MAC clock */ 3945 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3946 /* Disable AFE PLL */ 3947 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3948 /* Gated AFE DIG_CLOCK */ 3949 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3950 /* Isolated digital to PON */ 3951 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3952 } 3953 3954 /* 3955 * Pull GPIO PIN to balance level and LED control 3956 */ 3957 /* 1. Disable GPIO[7:0] */ 3958 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3959 3960 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3961 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3962 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3963 3964 /* Disable GPIO[10:8] */ 3965 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3966 3967 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3968 reg |= (((reg & 0x000f) << 4) | 0x0780); 3969 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3970 3971 /* Disable LED0 & 1 */ 3972 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3973 3974 /* 3975 * Reset digital sequence 3976 */ 3977 if (disabled) { 3978 /* Disable ELDR clock */ 3979 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3980 /* Isolated ELDR to PON */ 3981 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3982 } 3983 3984 /* 3985 * Disable analog sequence 3986 */ 3987 if (disabled) { 3988 /* Disable A15 power */ 3989 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3990 /* Disable digital core power */ 3991 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3992 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3993 ~R92C_LDOV12D_CTRL_LDV12_EN); 3994 } 3995 3996 /* Enter PFM mode */ 3997 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3998 3999 /* Set USB suspend */ 4000 urtwn_write_2(sc, R92C_APS_FSMCO, 4001 R92C_APS_FSMCO_APDM_HOST | 4002 R92C_APS_FSMCO_AFSM_HSUS | 4003 R92C_APS_FSMCO_PFM_ALDN); 4004 4005 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 4006 4007 mutex_exit(&sc->sc_write_mtx); 4008 } 4009 4010 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 4011 4012 #ifdef _MODULE 4013 #include "ioconf.c" 4014 #endif 4015 4016 static int 4017 if_urtwn_modcmd(modcmd_t cmd, void *aux) 4018 { 4019 int error = 0; 4020 4021 switch (cmd) { 4022 case MODULE_CMD_INIT: 4023 #ifdef _MODULE 4024 error = config_init_component(cfdriver_ioconf_urtwn, 4025 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4026 #endif 4027 return (error); 4028 case MODULE_CMD_FINI: 4029 #ifdef _MODULE 4030 error = config_fini_component(cfdriver_ioconf_urtwn, 4031 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4032 #endif 4033 return (error); 4034 default: 4035 return (ENOTTY); 4036 } 4037 } 4038
Indexes created Thu Oct 02 14:10:14 GMT 2025