if_urtwn.c revision 1.33
1 /* $NetBSD: if_urtwn.c,v 1.33 2014/07/20 14:02:53 nonaka Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /*- 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.33 2014/07/20 14:02:53 nonaka Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_inet.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/conf.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <machine/endian.h> 46 #include <sys/intr.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_ether.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 62 #include <net80211/ieee80211_netbsd.h> 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/firmload.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 #include <dev/usb/usbdivar.h> 71 #include <dev/usb/usbdi_util.h> 72 #include <dev/usb/usbdevs.h> 73 74 #include <dev/usb/if_urtwnreg.h> 75 #include <dev/usb/if_urtwnvar.h> 76 #include <dev/usb/if_urtwn_data.h> 77 78 /* 79 * The sc_write_mtx locking is to prevent sequences of writes from 80 * being intermingled with each other. I don't know if this is really 81 * needed. I have added it just to be on the safe side. 82 */ 83 84 #ifdef URTWN_DEBUG 85 #define DBG_INIT __BIT(0) 86 #define DBG_FN __BIT(1) 87 #define DBG_TX __BIT(2) 88 #define DBG_RX __BIT(3) 89 #define DBG_STM __BIT(4) 90 #define DBG_RF __BIT(5) 91 #define DBG_REG __BIT(6) 92 #define DBG_ALL 0xffffffffU 93 u_int urtwn_debug = 0; 94 #define DPRINTFN(n, s) \ 95 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 96 #else 97 #define DPRINTFN(n, s) 98 #endif 99 100 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 101 #define URTWN_RTL8188E_DEV(v,p) \ 102 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 103 static const struct urtwn_dev { 104 struct usb_devno dev; 105 uint32_t flags; 106 #define FLAG_RTL8188E __BIT(0) 107 } urtwn_devs[] = { 108 URTWN_DEV(ABOCOM, RTL8188CU_1), 109 URTWN_DEV(ABOCOM, RTL8188CU_2), 110 URTWN_DEV(ABOCOM, RTL8192CU), 111 URTWN_DEV(ASUSTEK, RTL8192CU), 112 URTWN_DEV(ASUSTEK, USBN10NANO), 113 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 114 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 115 URTWN_DEV(AZUREWAVE, RTL8188CU), 116 URTWN_DEV(BELKIN, RTL8188CU), 117 URTWN_DEV(BELKIN, RTL8192CU), 118 URTWN_DEV(CHICONY, RTL8188CUS_1), 119 URTWN_DEV(CHICONY, RTL8188CUS_2), 120 URTWN_DEV(CHICONY, RTL8188CUS_3), 121 URTWN_DEV(CHICONY, RTL8188CUS_4), 122 URTWN_DEV(CHICONY, RTL8188CUS_5), 123 URTWN_DEV(COREGA, RTL8192CU), 124 URTWN_DEV(DLINK, RTL8188CU), 125 URTWN_DEV(DLINK, RTL8192CU_1), 126 URTWN_DEV(DLINK, RTL8192CU_2), 127 URTWN_DEV(DLINK, RTL8192CU_3), 128 URTWN_DEV(EDIMAX, RTL8188CU), 129 URTWN_DEV(EDIMAX, RTL8192CU), 130 URTWN_DEV(FEIXUN, RTL8188CU), 131 URTWN_DEV(FEIXUN, RTL8192CU), 132 URTWN_DEV(GUILLEMOT, HWNUP150), 133 URTWN_DEV(HAWKING, RTL8192CU), 134 URTWN_DEV(HP3, RTL8188CU), 135 URTWN_DEV(NETGEAR, WNA1000M), 136 URTWN_DEV(NETGEAR, RTL8192CU), 137 URTWN_DEV(NETGEAR4, RTL8188CU), 138 URTWN_DEV(NOVATECH, RTL8188CU), 139 URTWN_DEV(PLANEX2, RTL8188CU_1), 140 URTWN_DEV(PLANEX2, RTL8188CU_2), 141 URTWN_DEV(PLANEX2, RTL8192CU), 142 URTWN_DEV(PLANEX2, RTL8188CU_3), 143 URTWN_DEV(PLANEX2, RTL8188CU_4), 144 URTWN_DEV(PLANEX2, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188CE_0), 146 URTWN_DEV(REALTEK, RTL8188CE_1), 147 URTWN_DEV(REALTEK, RTL8188CTV), 148 URTWN_DEV(REALTEK, RTL8188CU_0), 149 URTWN_DEV(REALTEK, RTL8188CU_1), 150 URTWN_DEV(REALTEK, RTL8188CU_2), 151 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 152 URTWN_DEV(REALTEK, RTL8188CUS), 153 URTWN_DEV(REALTEK, RTL8188RU), 154 URTWN_DEV(REALTEK, RTL8188RU_2), 155 URTWN_DEV(REALTEK, RTL8191CU), 156 URTWN_DEV(REALTEK, RTL8192CE), 157 URTWN_DEV(REALTEK, RTL8192CU), 158 URTWN_DEV(SITECOMEU, RTL8188CU), 159 URTWN_DEV(SITECOMEU, RTL8188CU_2), 160 URTWN_DEV(SITECOMEU, RTL8192CU), 161 URTWN_DEV(SITECOMEU, RTL8192CUR2), 162 URTWN_DEV(TRENDNET, RTL8188CU), 163 URTWN_DEV(TRENDNET, RTL8192CU), 164 URTWN_DEV(ZYXEL, RTL8192CU), 165 166 /* URTWN_RTL8188E */ 167 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 168 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 169 }; 170 #undef URTWN_DEV 171 #undef URTWN_RTL8188E_DEV 172 173 static int urtwn_match(device_t, cfdata_t, void *); 174 static void urtwn_attach(device_t, device_t, void *); 175 static int urtwn_detach(device_t, int); 176 static int urtwn_activate(device_t, enum devact); 177 178 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 179 urtwn_attach, urtwn_detach, urtwn_activate); 180 181 static int urtwn_open_pipes(struct urtwn_softc *); 182 static void urtwn_close_pipes(struct urtwn_softc *); 183 static int urtwn_alloc_rx_list(struct urtwn_softc *); 184 static void urtwn_free_rx_list(struct urtwn_softc *); 185 static int urtwn_alloc_tx_list(struct urtwn_softc *); 186 static void urtwn_free_tx_list(struct urtwn_softc *); 187 static void urtwn_task(void *); 188 static void urtwn_do_async(struct urtwn_softc *, 189 void (*)(struct urtwn_softc *, void *), void *, int); 190 static void urtwn_wait_async(struct urtwn_softc *); 191 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 192 int); 193 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 194 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 195 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 196 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 197 int); 198 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 199 int); 200 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 201 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 202 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 203 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 204 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 205 uint32_t); 206 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 207 uint32_t); 208 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 209 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 210 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 211 static void urtwn_efuse_read(struct urtwn_softc *); 212 static void urtwn_efuse_switch_power(struct urtwn_softc *); 213 static int urtwn_read_chipid(struct urtwn_softc *); 214 #ifdef URTWN_DEBUG 215 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 216 #endif 217 static void urtwn_read_rom(struct urtwn_softc *); 218 static void urtwn_r88e_read_rom(struct urtwn_softc *); 219 static int urtwn_media_change(struct ifnet *); 220 static int urtwn_ra_init(struct urtwn_softc *); 221 static int urtwn_get_nettype(struct urtwn_softc *); 222 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 223 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 224 static void urtwn_set_led(struct urtwn_softc *, int, int); 225 static void urtwn_calib_to(void *); 226 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 227 static void urtwn_next_scan(void *); 228 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 229 int); 230 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 231 static int urtwn_wme_update(struct ieee80211com *); 232 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 233 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 234 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 235 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 236 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 237 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 238 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 239 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 240 struct ieee80211_node *, struct urtwn_tx_data *); 241 static void urtwn_start(struct ifnet *); 242 static void urtwn_watchdog(struct ifnet *); 243 static int urtwn_ioctl(struct ifnet *, u_long, void *); 244 static int urtwn_r92c_power_on(struct urtwn_softc *); 245 static int urtwn_r88e_power_on(struct urtwn_softc *); 246 static int urtwn_llt_init(struct urtwn_softc *); 247 static void urtwn_fw_reset(struct urtwn_softc *); 248 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 249 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 250 static int urtwn_load_firmware(struct urtwn_softc *); 251 static int urtwn_r92c_dma_init(struct urtwn_softc *); 252 static int urtwn_r88e_dma_init(struct urtwn_softc *); 253 static void urtwn_mac_init(struct urtwn_softc *); 254 static void urtwn_bb_init(struct urtwn_softc *); 255 static void urtwn_rf_init(struct urtwn_softc *); 256 static void urtwn_cam_init(struct urtwn_softc *); 257 static void urtwn_pa_bias_init(struct urtwn_softc *); 258 static void urtwn_rxfilter_init(struct urtwn_softc *); 259 static void urtwn_edca_init(struct urtwn_softc *); 260 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 261 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 262 uint16_t[]); 263 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 264 u_int, uint16_t[]); 265 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 266 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 267 u_int); 268 static void urtwn_iq_calib(struct urtwn_softc *, bool); 269 static void urtwn_lc_calib(struct urtwn_softc *); 270 static void urtwn_temp_calib(struct urtwn_softc *); 271 static int urtwn_init(struct ifnet *); 272 static void urtwn_stop(struct ifnet *, int); 273 static int urtwn_reset(struct ifnet *); 274 static void urtwn_chip_stop(struct urtwn_softc *); 275 static void urtwn_newassoc(struct ieee80211_node *, int); 276 277 /* Aliases. */ 278 #define urtwn_bb_write urtwn_write_4 279 #define urtwn_bb_read urtwn_read_4 280 281 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 282 283 static int 284 urtwn_match(device_t parent, cfdata_t match, void *aux) 285 { 286 struct usb_attach_arg *uaa = aux; 287 288 return ((urtwn_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 289 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 290 } 291 292 static void 293 urtwn_attach(device_t parent, device_t self, void *aux) 294 { 295 struct urtwn_softc *sc = device_private(self); 296 struct ieee80211com *ic = &sc->sc_ic; 297 struct ifnet *ifp = &sc->sc_if; 298 struct usb_attach_arg *uaa = aux; 299 char *devinfop; 300 const struct urtwn_dev *dev; 301 size_t i; 302 int error; 303 304 sc->sc_dev = self; 305 sc->sc_udev = uaa->device; 306 307 sc->chip = 0; 308 dev = urtwn_lookup(urtwn_devs, uaa->vendor, uaa->product); 309 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 310 SET(sc->chip, URTWN_CHIP_88E); 311 312 aprint_naive("\n"); 313 aprint_normal("\n"); 314 315 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 316 317 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 318 aprint_normal_dev(self, "%s\n", devinfop); 319 usbd_devinfo_free(devinfop); 320 321 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 322 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 323 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 324 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 325 326 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 327 328 callout_init(&sc->sc_scan_to, 0); 329 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 330 callout_init(&sc->sc_calib_to, 0); 331 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 332 333 error = usbd_set_config_no(sc->sc_udev, 1, 0); 334 if (error != 0) { 335 aprint_error_dev(self, "failed to set configuration" 336 ", err=%s\n", usbd_errstr(error)); 337 goto fail; 338 } 339 340 /* Get the first interface handle. */ 341 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 342 if (error != 0) { 343 aprint_error_dev(self, "could not get interface handle\n"); 344 goto fail; 345 } 346 347 error = urtwn_read_chipid(sc); 348 if (error != 0) { 349 aprint_error_dev(self, "unsupported test chip\n"); 350 goto fail; 351 } 352 353 /* Determine number of Tx/Rx chains. */ 354 if (sc->chip & URTWN_CHIP_92C) { 355 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 356 sc->nrxchains = 2; 357 } else { 358 sc->ntxchains = 1; 359 sc->nrxchains = 1; 360 } 361 362 if (ISSET(sc->chip, URTWN_CHIP_88E)) 363 urtwn_r88e_read_rom(sc); 364 else 365 urtwn_read_rom(sc); 366 367 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 368 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 369 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 370 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 371 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 372 "8188CUS", sc->ntxchains, sc->nrxchains, 373 ether_sprintf(ic->ic_myaddr)); 374 375 error = urtwn_open_pipes(sc); 376 if (error != 0) { 377 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 378 goto fail; 379 } 380 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 381 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 382 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 383 384 /* 385 * Setup the 802.11 device. 386 */ 387 ic->ic_ifp = ifp; 388 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 389 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 390 ic->ic_state = IEEE80211_S_INIT; 391 392 /* Set device capabilities. */ 393 ic->ic_caps = 394 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 395 IEEE80211_C_IBSS | /* IBSS mode supported */ 396 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 397 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 398 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 399 IEEE80211_C_WME | /* 802.11e */ 400 IEEE80211_C_WPA; /* 802.11i */ 401 402 /* Set supported .11b and .11g rates. */ 403 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 404 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 405 406 /* Set supported .11b and .11g channels (1 through 14). */ 407 for (i = 1; i <= 14; i++) { 408 ic->ic_channels[i].ic_freq = 409 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 410 ic->ic_channels[i].ic_flags = 411 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 412 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 413 } 414 415 ifp->if_softc = sc; 416 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 417 ifp->if_init = urtwn_init; 418 ifp->if_ioctl = urtwn_ioctl; 419 ifp->if_start = urtwn_start; 420 ifp->if_watchdog = urtwn_watchdog; 421 IFQ_SET_READY(&ifp->if_snd); 422 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 423 424 if_attach(ifp); 425 ieee80211_ifattach(ic); 426 427 /* override default methods */ 428 ic->ic_newassoc = urtwn_newassoc; 429 ic->ic_reset = urtwn_reset; 430 ic->ic_wme.wme_update = urtwn_wme_update; 431 432 /* Override state transition machine. */ 433 sc->sc_newstate = ic->ic_newstate; 434 ic->ic_newstate = urtwn_newstate; 435 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 436 437 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 438 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 439 &sc->sc_drvbpf); 440 441 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 442 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 443 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 444 445 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 446 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 447 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 448 449 ieee80211_announce(ic); 450 451 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 452 453 if (!pmf_device_register(self, NULL, NULL)) 454 aprint_error_dev(self, "couldn't establish power handler\n"); 455 456 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 457 return; 458 459 fail: 460 sc->sc_dying = 1; 461 aprint_error_dev(self, "attach failed\n"); 462 } 463 464 static int 465 urtwn_detach(device_t self, int flags) 466 { 467 struct urtwn_softc *sc = device_private(self); 468 struct ifnet *ifp = &sc->sc_if; 469 int s; 470 471 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 472 473 pmf_device_deregister(self); 474 475 s = splusb(); 476 477 sc->sc_dying = 1; 478 479 callout_stop(&sc->sc_scan_to); 480 callout_stop(&sc->sc_calib_to); 481 482 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 483 usb_rem_task(sc->sc_udev, &sc->sc_task); 484 urtwn_stop(ifp, 0); 485 486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 487 bpf_detach(ifp); 488 ieee80211_ifdetach(&sc->sc_ic); 489 if_detach(ifp); 490 491 /* Abort and close Tx/Rx pipes. */ 492 urtwn_close_pipes(sc); 493 } 494 495 splx(s); 496 497 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 498 499 callout_destroy(&sc->sc_scan_to); 500 callout_destroy(&sc->sc_calib_to); 501 502 mutex_destroy(&sc->sc_write_mtx); 503 mutex_destroy(&sc->sc_fwcmd_mtx); 504 mutex_destroy(&sc->sc_tx_mtx); 505 mutex_destroy(&sc->sc_task_mtx); 506 507 return (0); 508 } 509 510 static int 511 urtwn_activate(device_t self, enum devact act) 512 { 513 struct urtwn_softc *sc = device_private(self); 514 515 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 516 517 switch (act) { 518 case DVACT_DEACTIVATE: 519 if_deactivate(sc->sc_ic.ic_ifp); 520 return (0); 521 default: 522 return (EOPNOTSUPP); 523 } 524 } 525 526 static int 527 urtwn_open_pipes(struct urtwn_softc *sc) 528 { 529 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 530 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 531 usb_interface_descriptor_t *id; 532 usb_endpoint_descriptor_t *ed; 533 size_t i, ntx = 0; 534 int error; 535 536 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 537 538 /* Determine the number of bulk-out pipes. */ 539 id = usbd_get_interface_descriptor(sc->sc_iface); 540 for (i = 0; i < id->bNumEndpoints; i++) { 541 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 542 if (ed != NULL && 543 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 544 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 545 ntx++; 546 } 547 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 548 device_xname(sc->sc_dev), __func__, ntx)); 549 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 550 aprint_error_dev(sc->sc_dev, 551 "%zd: invalid number of Tx bulk pipes\n", ntx); 552 return (EIO); 553 } 554 sc->rx_npipe = 1; 555 sc->tx_npipe = ntx; 556 557 /* Open bulk-in pipe at address 0x81. */ 558 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 559 &sc->rx_pipe); 560 if (error != 0) { 561 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 562 ": %d\n", error); 563 goto fail; 564 } 565 566 /* Open bulk-out pipes (up to 3). */ 567 for (i = 0; i < ntx; i++) { 568 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 569 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 570 if (error != 0) { 571 aprint_error_dev(sc->sc_dev, 572 "could not open Tx bulk pipe 0x%02x: %d\n", 573 epaddr[i], error); 574 goto fail; 575 } 576 } 577 578 /* Map 802.11 access categories to USB pipes. */ 579 sc->ac2idx[WME_AC_BK] = 580 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 581 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 582 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 583 584 fail: 585 if (error != 0) 586 urtwn_close_pipes(sc); 587 return (error); 588 } 589 590 static void 591 urtwn_close_pipes(struct urtwn_softc *sc) 592 { 593 usbd_pipe_handle pipe; 594 size_t i; 595 596 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 597 598 /* Close Rx pipe. */ 599 CTASSERT(sizeof(pipe) == sizeof(void *)); 600 pipe = atomic_swap_ptr(&sc->rx_pipe, NULL); 601 if (pipe != NULL) { 602 usbd_abort_pipe(pipe); 603 usbd_close_pipe(pipe); 604 } 605 /* Close Tx pipes. */ 606 for (i = 0; i < R92C_MAX_EPOUT; i++) { 607 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 608 if (pipe != NULL) { 609 usbd_abort_pipe(pipe); 610 usbd_close_pipe(pipe); 611 } 612 } 613 } 614 615 static int 616 urtwn_alloc_rx_list(struct urtwn_softc *sc) 617 { 618 struct urtwn_rx_data *data; 619 size_t i; 620 int error = 0; 621 622 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 623 624 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 625 data = &sc->rx_data[i]; 626 627 data->sc = sc; /* Backpointer for callbacks. */ 628 629 data->xfer = usbd_alloc_xfer(sc->sc_udev); 630 if (data->xfer == NULL) { 631 aprint_error_dev(sc->sc_dev, 632 "could not allocate xfer\n"); 633 error = ENOMEM; 634 break; 635 } 636 637 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 638 if (data->buf == NULL) { 639 aprint_error_dev(sc->sc_dev, 640 "could not allocate xfer buffer\n"); 641 error = ENOMEM; 642 break; 643 } 644 } 645 if (error != 0) 646 urtwn_free_rx_list(sc); 647 return (error); 648 } 649 650 static void 651 urtwn_free_rx_list(struct urtwn_softc *sc) 652 { 653 usbd_xfer_handle xfer; 654 size_t i; 655 656 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 657 658 /* NB: Caller must abort pipe first. */ 659 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 660 CTASSERT(sizeof(xfer) == sizeof(void *)); 661 xfer = atomic_swap_ptr(&sc->rx_data[i].xfer, NULL); 662 if (xfer != NULL) 663 usbd_free_xfer(xfer); 664 } 665 } 666 667 static int 668 urtwn_alloc_tx_list(struct urtwn_softc *sc) 669 { 670 struct urtwn_tx_data *data; 671 size_t i; 672 int error = 0; 673 674 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 675 676 mutex_enter(&sc->sc_tx_mtx); 677 TAILQ_INIT(&sc->tx_free_list); 678 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 679 data = &sc->tx_data[i]; 680 681 data->sc = sc; /* Backpointer for callbacks. */ 682 683 data->xfer = usbd_alloc_xfer(sc->sc_udev); 684 if (data->xfer == NULL) { 685 aprint_error_dev(sc->sc_dev, 686 "could not allocate xfer\n"); 687 error = ENOMEM; 688 goto fail; 689 } 690 691 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 692 if (data->buf == NULL) { 693 aprint_error_dev(sc->sc_dev, 694 "could not allocate xfer buffer\n"); 695 error = ENOMEM; 696 goto fail; 697 } 698 699 /* Append this Tx buffer to our free list. */ 700 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 701 } 702 mutex_exit(&sc->sc_tx_mtx); 703 return (0); 704 705 fail: 706 urtwn_free_tx_list(sc); 707 mutex_exit(&sc->sc_tx_mtx); 708 return (error); 709 } 710 711 static void 712 urtwn_free_tx_list(struct urtwn_softc *sc) 713 { 714 usbd_xfer_handle xfer; 715 size_t i; 716 717 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 718 719 /* NB: Caller must abort pipe first. */ 720 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 721 CTASSERT(sizeof(xfer) == sizeof(void *)); 722 xfer = atomic_swap_ptr(&sc->tx_data[i].xfer, NULL); 723 if (xfer != NULL) 724 usbd_free_xfer(xfer); 725 } 726 } 727 728 static void 729 urtwn_task(void *arg) 730 { 731 struct urtwn_softc *sc = arg; 732 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 733 struct urtwn_host_cmd *cmd; 734 int s; 735 736 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 737 738 /* Process host commands. */ 739 s = splusb(); 740 mutex_spin_enter(&sc->sc_task_mtx); 741 while (ring->next != ring->cur) { 742 cmd = &ring->cmd[ring->next]; 743 mutex_spin_exit(&sc->sc_task_mtx); 744 splx(s); 745 /* Invoke callback with kernel lock held. */ 746 cmd->cb(sc, cmd->data); 747 s = splusb(); 748 mutex_spin_enter(&sc->sc_task_mtx); 749 ring->queued--; 750 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 751 } 752 mutex_spin_exit(&sc->sc_task_mtx); 753 wakeup(&sc->cmdq); 754 splx(s); 755 } 756 757 static void 758 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 759 void *arg, int len) 760 { 761 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 762 struct urtwn_host_cmd *cmd; 763 int s; 764 765 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 766 device_xname(sc->sc_dev), __func__, cb, arg, len)); 767 768 s = splusb(); 769 mutex_spin_enter(&sc->sc_task_mtx); 770 cmd = &ring->cmd[ring->cur]; 771 cmd->cb = cb; 772 KASSERT(len <= sizeof(cmd->data)); 773 memcpy(cmd->data, arg, len); 774 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 775 776 /* If there is no pending command already, schedule a task. */ 777 if (!sc->sc_dying && ++ring->queued == 1) { 778 mutex_spin_exit(&sc->sc_task_mtx); 779 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 780 } else 781 mutex_spin_exit(&sc->sc_task_mtx); 782 splx(s); 783 } 784 785 static void 786 urtwn_wait_async(struct urtwn_softc *sc) 787 { 788 789 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 790 791 /* Wait for all queued asynchronous commands to complete. */ 792 while (sc->cmdq.queued > 0) 793 tsleep(&sc->cmdq, 0, "endtask", 0); 794 } 795 796 static int 797 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 798 int len) 799 { 800 usb_device_request_t req; 801 usbd_status error; 802 803 KASSERT(mutex_owned(&sc->sc_write_mtx)); 804 805 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 806 req.bRequest = R92C_REQ_REGS; 807 USETW(req.wValue, addr); 808 USETW(req.wIndex, 0); 809 USETW(req.wLength, len); 810 error = usbd_do_request(sc->sc_udev, &req, buf); 811 if (error != USBD_NORMAL_COMPLETION) { 812 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 813 device_xname(sc->sc_dev), __func__, error, addr, len)); 814 } 815 return (error); 816 } 817 818 static void 819 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 820 { 821 822 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 823 device_xname(sc->sc_dev), __func__, addr, val)); 824 825 urtwn_write_region_1(sc, addr, &val, 1); 826 } 827 828 static void 829 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 830 { 831 uint8_t buf[2]; 832 833 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 834 device_xname(sc->sc_dev), __func__, addr, val)); 835 836 buf[0] = (uint8_t)val; 837 buf[1] = (uint8_t)(val >> 8); 838 urtwn_write_region_1(sc, addr, buf, 2); 839 } 840 841 static void 842 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 843 { 844 uint8_t buf[4]; 845 846 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 847 device_xname(sc->sc_dev), __func__, addr, val)); 848 849 buf[0] = (uint8_t)val; 850 buf[1] = (uint8_t)(val >> 8); 851 buf[2] = (uint8_t)(val >> 16); 852 buf[3] = (uint8_t)(val >> 24); 853 urtwn_write_region_1(sc, addr, buf, 4); 854 } 855 856 static int 857 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 858 { 859 860 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 861 device_xname(sc->sc_dev), __func__, addr, len)); 862 863 return urtwn_write_region_1(sc, addr, buf, len); 864 } 865 866 static int 867 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 868 int len) 869 { 870 usb_device_request_t req; 871 usbd_status error; 872 873 req.bmRequestType = UT_READ_VENDOR_DEVICE; 874 req.bRequest = R92C_REQ_REGS; 875 USETW(req.wValue, addr); 876 USETW(req.wIndex, 0); 877 USETW(req.wLength, len); 878 error = usbd_do_request(sc->sc_udev, &req, buf); 879 if (error != USBD_NORMAL_COMPLETION) { 880 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 881 device_xname(sc->sc_dev), __func__, error, addr, len)); 882 } 883 return (error); 884 } 885 886 static uint8_t 887 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 888 { 889 uint8_t val; 890 891 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 892 return (0xff); 893 894 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 895 device_xname(sc->sc_dev), __func__, addr, val)); 896 return (val); 897 } 898 899 static uint16_t 900 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 901 { 902 uint8_t buf[2]; 903 uint16_t val; 904 905 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 906 return (0xffff); 907 908 val = LE_READ_2(&buf[0]); 909 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 910 device_xname(sc->sc_dev), __func__, addr, val)); 911 return (val); 912 } 913 914 static uint32_t 915 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 916 { 917 uint8_t buf[4]; 918 uint32_t val; 919 920 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 921 return (0xffffffff); 922 923 val = LE_READ_4(&buf[0]); 924 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 925 device_xname(sc->sc_dev), __func__, addr, val)); 926 return (val); 927 } 928 929 static int 930 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 931 { 932 struct r92c_fw_cmd cmd; 933 uint8_t *cp; 934 int fwcur; 935 int ntries; 936 937 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 938 device_xname(sc->sc_dev), __func__, id, buf, len)); 939 940 KASSERT(mutex_owned(&sc->sc_write_mtx)); 941 942 mutex_enter(&sc->sc_fwcmd_mtx); 943 fwcur = sc->fwcur; 944 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 945 mutex_exit(&sc->sc_fwcmd_mtx); 946 947 /* Wait for current FW box to be empty. */ 948 for (ntries = 0; ntries < 100; ntries++) { 949 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 950 break; 951 DELAY(1); 952 } 953 if (ntries == 100) { 954 aprint_error_dev(sc->sc_dev, 955 "could not send firmware command %d\n", id); 956 return (ETIMEDOUT); 957 } 958 959 memset(&cmd, 0, sizeof(cmd)); 960 KASSERT(len <= sizeof(cmd.msg)); 961 memcpy(cmd.msg, buf, len); 962 963 /* Write the first word last since that will trigger the FW. */ 964 cp = (uint8_t *)&cmd; 965 if (len >= 4) { 966 cmd.id = id | R92C_CMD_FLAG_EXT; 967 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 968 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 969 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 970 } else { 971 cmd.id = id; 972 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 973 } 974 975 return (0); 976 } 977 978 static __inline void 979 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 980 { 981 982 sc->sc_rf_write(sc, chain, addr, val); 983 } 984 985 static void 986 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 987 uint32_t val) 988 { 989 990 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 991 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 992 } 993 994 static void 995 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 996 uint32_t val) 997 { 998 999 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1000 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1001 } 1002 1003 static uint32_t 1004 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1005 { 1006 uint32_t reg[R92C_MAX_CHAINS], val; 1007 1008 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1009 if (chain != 0) { 1010 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1011 } 1012 1013 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1014 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1015 DELAY(1000); 1016 1017 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1018 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1019 R92C_HSSI_PARAM2_READ_EDGE); 1020 DELAY(1000); 1021 1022 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1023 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1024 DELAY(1000); 1025 1026 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1027 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1028 } else { 1029 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1030 } 1031 return (MS(val, R92C_LSSI_READBACK_DATA)); 1032 } 1033 1034 static int 1035 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1036 { 1037 int ntries; 1038 1039 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1040 1041 urtwn_write_4(sc, R92C_LLT_INIT, 1042 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1043 SM(R92C_LLT_INIT_ADDR, addr) | 1044 SM(R92C_LLT_INIT_DATA, data)); 1045 /* Wait for write operation to complete. */ 1046 for (ntries = 0; ntries < 20; ntries++) { 1047 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1048 R92C_LLT_INIT_OP_NO_ACTIVE) { 1049 /* Done */ 1050 return (0); 1051 } 1052 DELAY(5); 1053 } 1054 return (ETIMEDOUT); 1055 } 1056 1057 static uint8_t 1058 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1059 { 1060 uint32_t reg; 1061 int ntries; 1062 1063 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1064 1065 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1066 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1067 reg &= ~R92C_EFUSE_CTRL_VALID; 1068 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1069 1070 /* Wait for read operation to complete. */ 1071 for (ntries = 0; ntries < 100; ntries++) { 1072 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1073 if (reg & R92C_EFUSE_CTRL_VALID) { 1074 /* Done */ 1075 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1076 } 1077 DELAY(5); 1078 } 1079 aprint_error_dev(sc->sc_dev, 1080 "could not read efuse byte at address 0x%04x\n", addr); 1081 return (0xff); 1082 } 1083 1084 static void 1085 urtwn_efuse_read(struct urtwn_softc *sc) 1086 { 1087 uint8_t *rom = (uint8_t *)&sc->rom; 1088 uint32_t reg; 1089 uint16_t addr = 0; 1090 uint8_t off, msk; 1091 size_t i; 1092 1093 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1094 1095 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1096 1097 urtwn_efuse_switch_power(sc); 1098 1099 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1100 while (addr < 512) { 1101 reg = urtwn_efuse_read_1(sc, addr); 1102 if (reg == 0xff) 1103 break; 1104 addr++; 1105 off = reg >> 4; 1106 msk = reg & 0xf; 1107 for (i = 0; i < 4; i++) { 1108 if (msk & (1U << i)) 1109 continue; 1110 1111 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1112 addr++; 1113 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1114 addr++; 1115 } 1116 } 1117 #ifdef URTWN_DEBUG 1118 if (urtwn_debug & DBG_INIT) { 1119 /* Dump ROM content. */ 1120 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1121 for (i = 0; i < (int)sizeof(sc->rom); i++) 1122 printf(":%02x", rom[i]); 1123 printf("\n"); 1124 } 1125 #endif 1126 } 1127 1128 static void 1129 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1130 { 1131 uint32_t reg; 1132 1133 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1134 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1135 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1136 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1137 } 1138 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1139 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1140 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1141 reg | R92C_SYS_FUNC_EN_ELDR); 1142 } 1143 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1144 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1145 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1146 urtwn_write_2(sc, R92C_SYS_CLKR, 1147 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1148 } 1149 } 1150 1151 static int 1152 urtwn_read_chipid(struct urtwn_softc *sc) 1153 { 1154 uint32_t reg; 1155 1156 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1157 1158 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1159 return (0); 1160 1161 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1162 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1163 /* test chip, not supported */ 1164 return (EIO); 1165 } 1166 if (reg & R92C_SYS_CFG_TYPE_92C) { 1167 sc->chip |= URTWN_CHIP_92C; 1168 /* Check if it is a castrated 8192C. */ 1169 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1170 R92C_HPON_FSM_CHIP_BONDING_ID) == 1171 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1172 sc->chip |= URTWN_CHIP_92C_1T2R; 1173 } 1174 } 1175 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1176 sc->chip |= URTWN_CHIP_UMC; 1177 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1178 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1179 } 1180 } 1181 return (0); 1182 } 1183 1184 #ifdef URTWN_DEBUG 1185 static void 1186 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1187 { 1188 1189 aprint_normal_dev(sc->sc_dev, 1190 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1191 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1192 1193 aprint_normal_dev(sc->sc_dev, 1194 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1195 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1196 1197 aprint_normal_dev(sc->sc_dev, 1198 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1199 rp->macaddr[0], rp->macaddr[1], 1200 rp->macaddr[2], rp->macaddr[3], 1201 rp->macaddr[4], rp->macaddr[5]); 1202 1203 aprint_normal_dev(sc->sc_dev, 1204 "string %s, subcustomer_id 0x%x\n", 1205 rp->string, rp->subcustomer_id); 1206 1207 aprint_normal_dev(sc->sc_dev, 1208 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1209 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1210 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1211 1212 aprint_normal_dev(sc->sc_dev, 1213 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1214 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1215 rp->ht40_1s_tx_pwr[0][2], 1216 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1217 rp->ht40_1s_tx_pwr[1][2]); 1218 1219 aprint_normal_dev(sc->sc_dev, 1220 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1221 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1222 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1223 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1224 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1225 1226 aprint_normal_dev(sc->sc_dev, 1227 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1228 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1229 rp->ht20_tx_pwr_diff[2] & 0xf, 1230 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1231 rp->ht20_tx_pwr_diff[2] >> 4); 1232 1233 aprint_normal_dev(sc->sc_dev, 1234 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1235 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1236 rp->ofdm_tx_pwr_diff[2] & 0xf, 1237 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1238 rp->ofdm_tx_pwr_diff[2] >> 4); 1239 1240 aprint_normal_dev(sc->sc_dev, 1241 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1242 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1243 rp->ht40_max_pwr[2] & 0xf, 1244 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1245 rp->ht40_max_pwr[2] >> 4); 1246 1247 aprint_normal_dev(sc->sc_dev, 1248 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1249 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1250 rp->ht20_max_pwr[2] & 0xf, 1251 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1252 rp->ht20_max_pwr[2] >> 4); 1253 1254 aprint_normal_dev(sc->sc_dev, 1255 "xtal_calib %d, tssi %d %d, thermal %d\n", 1256 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1257 1258 aprint_normal_dev(sc->sc_dev, 1259 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1260 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1261 1262 aprint_normal_dev(sc->sc_dev, 1263 "channnel_plan %d, version %d customer_id 0x%x\n", 1264 rp->channel_plan, rp->version, rp->curstomer_id); 1265 } 1266 #endif 1267 1268 static void 1269 urtwn_read_rom(struct urtwn_softc *sc) 1270 { 1271 struct ieee80211com *ic = &sc->sc_ic; 1272 struct r92c_rom *rom = &sc->rom; 1273 1274 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1275 1276 mutex_enter(&sc->sc_write_mtx); 1277 1278 /* Read full ROM image. */ 1279 urtwn_efuse_read(sc); 1280 #ifdef URTWN_DEBUG 1281 if (urtwn_debug & DBG_REG) 1282 urtwn_dump_rom(sc, rom); 1283 #endif 1284 1285 /* XXX Weird but this is what the vendor driver does. */ 1286 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1287 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1288 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1289 1290 DPRINTFN(DBG_INIT, 1291 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1292 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1293 sc->board_type, sc->regulatory)); 1294 1295 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1296 1297 sc->sc_rf_write = urtwn_r92c_rf_write; 1298 sc->sc_power_on = urtwn_r92c_power_on; 1299 sc->sc_dma_init = urtwn_r92c_dma_init; 1300 1301 mutex_exit(&sc->sc_write_mtx); 1302 } 1303 1304 static void 1305 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1306 { 1307 struct ieee80211com *ic = &sc->sc_ic; 1308 uint8_t *rom = sc->r88e_rom; 1309 uint32_t reg; 1310 uint16_t addr = 0; 1311 uint8_t off, msk, tmp; 1312 int i; 1313 1314 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1315 1316 mutex_enter(&sc->sc_write_mtx); 1317 1318 off = 0; 1319 urtwn_efuse_switch_power(sc); 1320 1321 /* Read full ROM image. */ 1322 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1323 while (addr < 1024) { 1324 reg = urtwn_efuse_read_1(sc, addr); 1325 if (reg == 0xff) 1326 break; 1327 addr++; 1328 if ((reg & 0x1f) == 0x0f) { 1329 tmp = (reg & 0xe0) >> 5; 1330 reg = urtwn_efuse_read_1(sc, addr); 1331 if ((reg & 0x0f) != 0x0f) 1332 off = ((reg & 0xf0) >> 1) | tmp; 1333 addr++; 1334 } else 1335 off = reg >> 4; 1336 msk = reg & 0xf; 1337 for (i = 0; i < 4; i++) { 1338 if (msk & (1 << i)) 1339 continue; 1340 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1341 addr++; 1342 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1343 addr++; 1344 } 1345 } 1346 #ifdef URTWN_DEBUG 1347 if (urtwn_debug & DBG_REG) { 1348 } 1349 #endif 1350 1351 addr = 0x10; 1352 for (i = 0; i < 6; i++) 1353 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1354 for (i = 0; i < 5; i++) 1355 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1356 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1357 if (sc->bw20_tx_pwr_diff & 0x08) 1358 sc->bw20_tx_pwr_diff |= 0xf0; 1359 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1360 if (sc->ofdm_tx_pwr_diff & 0x08) 1361 sc->ofdm_tx_pwr_diff |= 0xf0; 1362 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1363 1364 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1365 1366 sc->sc_rf_write = urtwn_r88e_rf_write; 1367 sc->sc_power_on = urtwn_r88e_power_on; 1368 sc->sc_dma_init = urtwn_r88e_dma_init; 1369 1370 mutex_exit(&sc->sc_write_mtx); 1371 } 1372 1373 static int 1374 urtwn_media_change(struct ifnet *ifp) 1375 { 1376 #ifdef URTWN_DEBUG 1377 struct urtwn_softc *sc = ifp->if_softc; 1378 #endif 1379 int error; 1380 1381 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1382 1383 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1384 return (error); 1385 1386 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1387 (IFF_UP | IFF_RUNNING)) { 1388 urtwn_init(ifp); 1389 } 1390 return (0); 1391 } 1392 1393 /* 1394 * Initialize rate adaptation in firmware. 1395 */ 1396 static int 1397 urtwn_ra_init(struct urtwn_softc *sc) 1398 { 1399 static const uint8_t map[] = { 1400 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1401 }; 1402 struct ieee80211com *ic = &sc->sc_ic; 1403 struct ieee80211_node *ni = ic->ic_bss; 1404 struct ieee80211_rateset *rs = &ni->ni_rates; 1405 struct r92c_fw_cmd_macid_cfg cmd; 1406 uint32_t rates, basicrates; 1407 uint32_t mask; 1408 uint8_t mode; 1409 size_t maxrate, maxbasicrate, i, j; 1410 int error; 1411 1412 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1413 1414 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1415 1416 /* Get normal and basic rates mask. */ 1417 rates = basicrates = 0; 1418 maxrate = maxbasicrate = 0; 1419 for (i = 0; i < rs->rs_nrates; i++) { 1420 /* Convert 802.11 rate to HW rate index. */ 1421 for (j = 0; j < __arraycount(map); j++) { 1422 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1423 break; 1424 } 1425 } 1426 if (j == __arraycount(map)) { 1427 /* Unknown rate, skip. */ 1428 continue; 1429 } 1430 1431 rates |= 1U << j; 1432 if (j > maxrate) { 1433 maxrate = j; 1434 } 1435 1436 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1437 basicrates |= 1U << j; 1438 if (j > maxbasicrate) { 1439 maxbasicrate = j; 1440 } 1441 } 1442 } 1443 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1444 mode = R92C_RAID_11B; 1445 } else { 1446 mode = R92C_RAID_11BG; 1447 } 1448 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1449 "maxrate=%zx, maxbasicrate=%zx\n", 1450 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1451 maxrate, maxbasicrate)); 1452 if (basicrates == 0) { 1453 basicrates |= 1; /* add 1Mbps */ 1454 } 1455 1456 /* Set rates mask for group addressed frames. */ 1457 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1458 mask = (mode << 28) | basicrates; 1459 cmd.mask[0] = (uint8_t)mask; 1460 cmd.mask[1] = (uint8_t)(mask >> 8); 1461 cmd.mask[2] = (uint8_t)(mask >> 16); 1462 cmd.mask[3] = (uint8_t)(mask >> 24); 1463 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1464 if (error != 0) { 1465 aprint_error_dev(sc->sc_dev, 1466 "could not add broadcast station\n"); 1467 return (error); 1468 } 1469 /* Set initial MRR rate. */ 1470 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1471 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1472 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1473 1474 /* Set rates mask for unicast frames. */ 1475 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1476 mask = (mode << 28) | rates; 1477 cmd.mask[0] = (uint8_t)mask; 1478 cmd.mask[1] = (uint8_t)(mask >> 8); 1479 cmd.mask[2] = (uint8_t)(mask >> 16); 1480 cmd.mask[3] = (uint8_t)(mask >> 24); 1481 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1482 if (error != 0) { 1483 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1484 return (error); 1485 } 1486 /* Set initial MRR rate. */ 1487 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1488 __func__, maxrate)); 1489 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1490 1491 /* Indicate highest supported rate. */ 1492 ni->ni_txrate = rs->rs_nrates - 1; 1493 1494 return (0); 1495 } 1496 1497 static int 1498 urtwn_get_nettype(struct urtwn_softc *sc) 1499 { 1500 struct ieee80211com *ic = &sc->sc_ic; 1501 int type; 1502 1503 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1504 1505 switch (ic->ic_opmode) { 1506 case IEEE80211_M_STA: 1507 type = R92C_CR_NETTYPE_INFRA; 1508 break; 1509 1510 case IEEE80211_M_IBSS: 1511 type = R92C_CR_NETTYPE_ADHOC; 1512 break; 1513 1514 default: 1515 type = R92C_CR_NETTYPE_NOLINK; 1516 break; 1517 } 1518 1519 return (type); 1520 } 1521 1522 static void 1523 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1524 { 1525 uint8_t reg; 1526 1527 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1528 __func__, type)); 1529 1530 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1531 1532 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1533 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1534 } 1535 1536 static void 1537 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1538 { 1539 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1540 uint64_t tsf; 1541 1542 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1543 1544 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1545 1546 /* Enable TSF synchronization. */ 1547 urtwn_write_1(sc, R92C_BCN_CTRL, 1548 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1549 1550 /* Correct TSF */ 1551 urtwn_write_1(sc, R92C_BCN_CTRL, 1552 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1553 1554 /* Set initial TSF. */ 1555 tsf = ni->ni_tstamp.tsf; 1556 tsf = le64toh(tsf); 1557 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1558 tsf -= IEEE80211_DUR_TU; 1559 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1560 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1561 1562 urtwn_write_1(sc, R92C_BCN_CTRL, 1563 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1564 } 1565 1566 static void 1567 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1568 { 1569 uint8_t reg; 1570 1571 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1572 __func__, led, on)); 1573 1574 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1575 1576 if (led == URTWN_LED_LINK) { 1577 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1578 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1579 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1580 if (!on) { 1581 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1582 urtwn_write_1(sc, R92C_LEDCFG2, 1583 reg | R92C_LEDCFG0_DIS); 1584 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1585 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1586 reg & 0xfe); 1587 } 1588 } else { 1589 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1590 if (!on) { 1591 reg |= R92C_LEDCFG0_DIS; 1592 } 1593 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1594 } 1595 sc->ledlink = on; /* Save LED state. */ 1596 } 1597 } 1598 1599 static void 1600 urtwn_calib_to(void *arg) 1601 { 1602 struct urtwn_softc *sc = arg; 1603 1604 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1605 1606 if (sc->sc_dying) 1607 return; 1608 1609 /* Do it in a process context. */ 1610 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1611 } 1612 1613 /* ARGSUSED */ 1614 static void 1615 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1616 { 1617 struct r92c_fw_cmd_rssi cmd; 1618 1619 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1620 1621 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1622 goto restart_timer; 1623 1624 mutex_enter(&sc->sc_write_mtx); 1625 if (sc->avg_pwdb != -1) { 1626 /* Indicate Rx signal strength to FW for rate adaptation. */ 1627 memset(&cmd, 0, sizeof(cmd)); 1628 cmd.macid = 0; /* BSS. */ 1629 cmd.pwdb = sc->avg_pwdb; 1630 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1631 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1632 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1633 } 1634 1635 /* Do temperature compensation. */ 1636 urtwn_temp_calib(sc); 1637 mutex_exit(&sc->sc_write_mtx); 1638 1639 restart_timer: 1640 if (!sc->sc_dying) { 1641 /* Restart calibration timer. */ 1642 callout_schedule(&sc->sc_calib_to, hz); 1643 } 1644 } 1645 1646 static void 1647 urtwn_next_scan(void *arg) 1648 { 1649 struct urtwn_softc *sc = arg; 1650 int s; 1651 1652 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1653 1654 if (sc->sc_dying) 1655 return; 1656 1657 s = splnet(); 1658 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1659 ieee80211_next_scan(&sc->sc_ic); 1660 splx(s); 1661 } 1662 1663 static void 1664 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1665 { 1666 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1667 ether_sprintf(ni->ni_macaddr))); 1668 /* start with lowest Tx rate */ 1669 ni->ni_txrate = 0; 1670 } 1671 1672 static int 1673 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1674 { 1675 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1676 struct urtwn_cmd_newstate cmd; 1677 1678 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1679 device_xname(sc->sc_dev), __func__, 1680 ieee80211_state_name[nstate], nstate, arg)); 1681 1682 callout_stop(&sc->sc_scan_to); 1683 callout_stop(&sc->sc_calib_to); 1684 1685 /* Do it in a process context. */ 1686 cmd.state = nstate; 1687 cmd.arg = arg; 1688 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1689 return (0); 1690 } 1691 1692 static void 1693 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1694 { 1695 struct urtwn_cmd_newstate *cmd = arg; 1696 struct ieee80211com *ic = &sc->sc_ic; 1697 struct ieee80211_node *ni; 1698 enum ieee80211_state ostate = ic->ic_state; 1699 enum ieee80211_state nstate = cmd->state; 1700 uint32_t reg; 1701 uint8_t sifs_time, msr; 1702 int s; 1703 1704 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1705 device_xname(sc->sc_dev), __func__, 1706 ieee80211_state_name[ostate], ostate, 1707 ieee80211_state_name[nstate], nstate)); 1708 1709 s = splnet(); 1710 mutex_enter(&sc->sc_write_mtx); 1711 1712 callout_stop(&sc->sc_scan_to); 1713 callout_stop(&sc->sc_calib_to); 1714 1715 switch (ostate) { 1716 case IEEE80211_S_INIT: 1717 break; 1718 1719 case IEEE80211_S_SCAN: 1720 if (nstate != IEEE80211_S_SCAN) { 1721 /* 1722 * End of scanning 1723 */ 1724 /* flush 4-AC Queue after site_survey */ 1725 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1726 1727 /* Allow Rx from our BSSID only. */ 1728 urtwn_write_4(sc, R92C_RCR, 1729 urtwn_read_4(sc, R92C_RCR) | 1730 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1731 } 1732 break; 1733 1734 case IEEE80211_S_AUTH: 1735 case IEEE80211_S_ASSOC: 1736 break; 1737 1738 case IEEE80211_S_RUN: 1739 /* Turn link LED off. */ 1740 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1741 1742 /* Set media status to 'No Link'. */ 1743 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1744 1745 /* Stop Rx of data frames. */ 1746 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1747 1748 /* Reset TSF. */ 1749 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1750 1751 /* Disable TSF synchronization. */ 1752 urtwn_write_1(sc, R92C_BCN_CTRL, 1753 urtwn_read_1(sc, R92C_BCN_CTRL) | 1754 R92C_BCN_CTRL_DIS_TSF_UDT0); 1755 1756 /* Back to 20MHz mode */ 1757 urtwn_set_chan(sc, ic->ic_curchan, 1758 IEEE80211_HTINFO_2NDCHAN_NONE); 1759 1760 if (ic->ic_opmode == IEEE80211_M_IBSS || 1761 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1762 /* Stop BCN */ 1763 urtwn_write_1(sc, R92C_BCN_CTRL, 1764 urtwn_read_1(sc, R92C_BCN_CTRL) & 1765 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1766 } 1767 1768 /* Reset EDCA parameters. */ 1769 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1770 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1771 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1772 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1773 1774 /* flush all cam entries */ 1775 urtwn_cam_init(sc); 1776 break; 1777 } 1778 1779 switch (nstate) { 1780 case IEEE80211_S_INIT: 1781 /* Turn link LED off. */ 1782 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1783 break; 1784 1785 case IEEE80211_S_SCAN: 1786 if (ostate != IEEE80211_S_SCAN) { 1787 /* 1788 * Begin of scanning 1789 */ 1790 1791 /* Set gain for scanning. */ 1792 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1793 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1794 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1795 1796 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1797 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1798 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1799 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1800 } 1801 1802 /* Set media status to 'No Link'. */ 1803 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1804 1805 /* Allow Rx from any BSSID. */ 1806 urtwn_write_4(sc, R92C_RCR, 1807 urtwn_read_4(sc, R92C_RCR) & 1808 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1809 1810 /* Stop Rx of data frames. */ 1811 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1812 1813 /* Disable update TSF */ 1814 urtwn_write_1(sc, R92C_BCN_CTRL, 1815 urtwn_read_1(sc, R92C_BCN_CTRL) | 1816 R92C_BCN_CTRL_DIS_TSF_UDT0); 1817 } 1818 1819 /* Make link LED blink during scan. */ 1820 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1821 1822 /* Pause AC Tx queues. */ 1823 urtwn_write_1(sc, R92C_TXPAUSE, 1824 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1825 1826 urtwn_set_chan(sc, ic->ic_curchan, 1827 IEEE80211_HTINFO_2NDCHAN_NONE); 1828 1829 /* Start periodic scan. */ 1830 if (!sc->sc_dying) 1831 callout_schedule(&sc->sc_scan_to, hz / 5); 1832 break; 1833 1834 case IEEE80211_S_AUTH: 1835 /* Set initial gain under link. */ 1836 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1837 #ifdef doaslinux 1838 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1839 #else 1840 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1841 #endif 1842 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1843 1844 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1845 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1846 #ifdef doaslinux 1847 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1848 #else 1849 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1850 #endif 1851 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1852 } 1853 1854 /* Set media status to 'No Link'. */ 1855 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1856 1857 /* Allow Rx from any BSSID. */ 1858 urtwn_write_4(sc, R92C_RCR, 1859 urtwn_read_4(sc, R92C_RCR) & 1860 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1861 1862 urtwn_set_chan(sc, ic->ic_curchan, 1863 IEEE80211_HTINFO_2NDCHAN_NONE); 1864 break; 1865 1866 case IEEE80211_S_ASSOC: 1867 break; 1868 1869 case IEEE80211_S_RUN: 1870 ni = ic->ic_bss; 1871 1872 /* XXX: Set 20MHz mode */ 1873 urtwn_set_chan(sc, ic->ic_curchan, 1874 IEEE80211_HTINFO_2NDCHAN_NONE); 1875 1876 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1877 /* Back to 20MHz mode */ 1878 urtwn_set_chan(sc, ic->ic_curchan, 1879 IEEE80211_HTINFO_2NDCHAN_NONE); 1880 1881 /* Set media status to 'No Link'. */ 1882 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1883 1884 /* Enable Rx of data frames. */ 1885 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1886 1887 /* Allow Rx from any BSSID. */ 1888 urtwn_write_4(sc, R92C_RCR, 1889 urtwn_read_4(sc, R92C_RCR) & 1890 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1891 1892 /* Accept Rx data/control/management frames */ 1893 urtwn_write_4(sc, R92C_RCR, 1894 urtwn_read_4(sc, R92C_RCR) | 1895 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1896 1897 /* Turn link LED on. */ 1898 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1899 break; 1900 } 1901 1902 /* Set media status to 'Associated'. */ 1903 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1904 1905 /* Set BSSID. */ 1906 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1907 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1908 1909 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1910 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1911 } else { 1912 /* 802.11b/g */ 1913 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1914 } 1915 1916 /* Enable Rx of data frames. */ 1917 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1918 1919 /* Set beacon interval. */ 1920 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1921 1922 msr = urtwn_read_1(sc, R92C_MSR); 1923 msr &= R92C_MSR_MASK; 1924 switch (ic->ic_opmode) { 1925 case IEEE80211_M_STA: 1926 /* Allow Rx from our BSSID only. */ 1927 urtwn_write_4(sc, R92C_RCR, 1928 urtwn_read_4(sc, R92C_RCR) | 1929 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1930 1931 /* Enable TSF synchronization. */ 1932 urtwn_tsf_sync_enable(sc); 1933 1934 msr |= R92C_MSR_INFRA; 1935 break; 1936 case IEEE80211_M_HOSTAP: 1937 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1938 1939 /* Allow Rx from any BSSID. */ 1940 urtwn_write_4(sc, R92C_RCR, 1941 urtwn_read_4(sc, R92C_RCR) & 1942 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1943 1944 /* Reset TSF timer to zero. */ 1945 reg = urtwn_read_4(sc, R92C_TCR); 1946 reg &= ~0x01; 1947 urtwn_write_4(sc, R92C_TCR, reg); 1948 reg |= 0x01; 1949 urtwn_write_4(sc, R92C_TCR, reg); 1950 1951 msr |= R92C_MSR_AP; 1952 break; 1953 default: 1954 msr |= R92C_MSR_ADHOC; 1955 break; 1956 } 1957 urtwn_write_1(sc, R92C_MSR, msr); 1958 1959 sifs_time = 10; 1960 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1961 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1962 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1963 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1964 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1965 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1966 1967 /* Intialize rate adaptation. */ 1968 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1969 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 1970 else 1971 urtwn_ra_init(sc); 1972 1973 /* Turn link LED on. */ 1974 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1975 1976 /* Reset average RSSI. */ 1977 sc->avg_pwdb = -1; 1978 1979 /* Reset temperature calibration state machine. */ 1980 sc->thcal_state = 0; 1981 sc->thcal_lctemp = 0; 1982 1983 /* Start periodic calibration. */ 1984 if (!sc->sc_dying) 1985 callout_schedule(&sc->sc_calib_to, hz); 1986 break; 1987 } 1988 1989 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1990 1991 mutex_exit(&sc->sc_write_mtx); 1992 splx(s); 1993 } 1994 1995 static int 1996 urtwn_wme_update(struct ieee80211com *ic) 1997 { 1998 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1999 2000 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2001 2002 /* don't override default WME values if WME is not actually enabled */ 2003 if (!(ic->ic_flags & IEEE80211_F_WME)) 2004 return (0); 2005 2006 /* Do it in a process context. */ 2007 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2008 return (0); 2009 } 2010 2011 static void 2012 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2013 { 2014 static const uint16_t ac2reg[WME_NUM_AC] = { 2015 R92C_EDCA_BE_PARAM, 2016 R92C_EDCA_BK_PARAM, 2017 R92C_EDCA_VI_PARAM, 2018 R92C_EDCA_VO_PARAM 2019 }; 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 const struct wmeParams *wmep; 2022 int ac, aifs, slottime; 2023 int s; 2024 2025 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2026 __func__)); 2027 2028 s = splnet(); 2029 mutex_enter(&sc->sc_write_mtx); 2030 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2031 for (ac = 0; ac < WME_NUM_AC; ac++) { 2032 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2033 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2034 aifs = wmep->wmep_aifsn * slottime + 10; 2035 urtwn_write_4(sc, ac2reg[ac], 2036 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2037 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2038 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2039 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2040 } 2041 mutex_exit(&sc->sc_write_mtx); 2042 splx(s); 2043 } 2044 2045 static void 2046 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2047 { 2048 int pwdb; 2049 2050 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2051 device_xname(sc->sc_dev), __func__, rate, rssi)); 2052 2053 /* Convert antenna signal to percentage. */ 2054 if (rssi <= -100 || rssi >= 20) 2055 pwdb = 0; 2056 else if (rssi >= 0) 2057 pwdb = 100; 2058 else 2059 pwdb = 100 + rssi; 2060 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2061 if (rate <= 3) { 2062 /* CCK gain is smaller than OFDM/MCS gain. */ 2063 pwdb += 6; 2064 if (pwdb > 100) 2065 pwdb = 100; 2066 if (pwdb <= 14) 2067 pwdb -= 4; 2068 else if (pwdb <= 26) 2069 pwdb -= 8; 2070 else if (pwdb <= 34) 2071 pwdb -= 6; 2072 else if (pwdb <= 42) 2073 pwdb -= 2; 2074 } 2075 } 2076 if (sc->avg_pwdb == -1) /* Init. */ 2077 sc->avg_pwdb = pwdb; 2078 else if (sc->avg_pwdb < pwdb) 2079 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2080 else 2081 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2082 2083 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2084 device_xname(sc->sc_dev), __func__, 2085 rate, rssi, pwdb, sc->avg_pwdb)); 2086 } 2087 2088 static int8_t 2089 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2090 { 2091 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2092 struct r92c_rx_phystat *phy; 2093 struct r92c_rx_cck *cck; 2094 uint8_t rpt; 2095 int8_t rssi; 2096 2097 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2098 __func__, rate)); 2099 2100 if (rate <= 3) { 2101 cck = (struct r92c_rx_cck *)physt; 2102 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2103 rpt = (cck->agc_rpt >> 5) & 0x3; 2104 rssi = (cck->agc_rpt & 0x1f) << 1; 2105 } else { 2106 rpt = (cck->agc_rpt >> 6) & 0x3; 2107 rssi = cck->agc_rpt & 0x3e; 2108 } 2109 rssi = cckoff[rpt] - rssi; 2110 } else { /* OFDM/HT. */ 2111 phy = (struct r92c_rx_phystat *)physt; 2112 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2113 } 2114 return (rssi); 2115 } 2116 2117 static int8_t 2118 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2119 { 2120 struct r92c_rx_phystat *phy; 2121 struct r88e_rx_cck *cck; 2122 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2123 int8_t rssi; 2124 2125 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2126 __func__, rate)); 2127 2128 rssi = 0; 2129 if (rate <= 3) { 2130 cck = (struct r88e_rx_cck *)physt; 2131 cck_agc_rpt = cck->agc_rpt; 2132 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2133 vga_idx = cck_agc_rpt & 0x1f; 2134 switch (lna_idx) { 2135 case 7: 2136 if (vga_idx <= 27) 2137 rssi = -100 + 2* (27 - vga_idx); 2138 else 2139 rssi = -100; 2140 break; 2141 case 6: 2142 rssi = -48 + 2 * (2 - vga_idx); 2143 break; 2144 case 5: 2145 rssi = -42 + 2 * (7 - vga_idx); 2146 break; 2147 case 4: 2148 rssi = -36 + 2 * (7 - vga_idx); 2149 break; 2150 case 3: 2151 rssi = -24 + 2 * (7 - vga_idx); 2152 break; 2153 case 2: 2154 rssi = -12 + 2 * (5 - vga_idx); 2155 break; 2156 case 1: 2157 rssi = 8 - (2 * vga_idx); 2158 break; 2159 case 0: 2160 rssi = 14 - (2 * vga_idx); 2161 break; 2162 } 2163 rssi += 6; 2164 } else { /* OFDM/HT. */ 2165 phy = (struct r92c_rx_phystat *)physt; 2166 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2167 } 2168 return (rssi); 2169 } 2170 2171 static void 2172 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2173 { 2174 struct ieee80211com *ic = &sc->sc_ic; 2175 struct ifnet *ifp = ic->ic_ifp; 2176 struct ieee80211_frame *wh; 2177 struct ieee80211_node *ni; 2178 struct r92c_rx_stat *stat; 2179 uint32_t rxdw0, rxdw3; 2180 struct mbuf *m; 2181 uint8_t rate; 2182 int8_t rssi = 0; 2183 int s, infosz; 2184 2185 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2186 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2187 2188 stat = (struct r92c_rx_stat *)buf; 2189 rxdw0 = le32toh(stat->rxdw0); 2190 rxdw3 = le32toh(stat->rxdw3); 2191 2192 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2193 /* 2194 * This should not happen since we setup our Rx filter 2195 * to not receive these frames. 2196 */ 2197 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2198 device_xname(sc->sc_dev), __func__)); 2199 ifp->if_ierrors++; 2200 return; 2201 } 2202 /* 2203 * XXX: This will drop most control packets. Do we really 2204 * want this in IEEE80211_M_MONITOR mode? 2205 */ 2206 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2207 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2208 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2209 device_xname(sc->sc_dev), __func__, pktlen)); 2210 ic->ic_stats.is_rx_tooshort++; 2211 ifp->if_ierrors++; 2212 return; 2213 } 2214 if (__predict_false(pktlen > MCLBYTES)) { 2215 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2216 device_xname(sc->sc_dev), __func__, pktlen)); 2217 ifp->if_ierrors++; 2218 return; 2219 } 2220 2221 rate = MS(rxdw3, R92C_RXDW3_RATE); 2222 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2223 2224 /* Get RSSI from PHY status descriptor if present. */ 2225 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2226 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2227 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2228 else 2229 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2230 /* Update our average RSSI. */ 2231 urtwn_update_avgrssi(sc, rate, rssi); 2232 } 2233 2234 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2235 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2236 2237 MGETHDR(m, M_DONTWAIT, MT_DATA); 2238 if (__predict_false(m == NULL)) { 2239 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2240 ic->ic_stats.is_rx_nobuf++; 2241 ifp->if_ierrors++; 2242 return; 2243 } 2244 if (pktlen > (int)MHLEN) { 2245 MCLGET(m, M_DONTWAIT); 2246 if (__predict_false(!(m->m_flags & M_EXT))) { 2247 aprint_error_dev(sc->sc_dev, 2248 "couldn't allocate rx mbuf cluster\n"); 2249 m_freem(m); 2250 ic->ic_stats.is_rx_nobuf++; 2251 ifp->if_ierrors++; 2252 return; 2253 } 2254 } 2255 2256 /* Finalize mbuf. */ 2257 m->m_pkthdr.rcvif = ifp; 2258 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2259 memcpy(mtod(m, uint8_t *), wh, pktlen); 2260 m->m_pkthdr.len = m->m_len = pktlen; 2261 2262 s = splnet(); 2263 if (__predict_false(sc->sc_drvbpf != NULL)) { 2264 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2265 2266 tap->wr_flags = 0; 2267 if (!(rxdw3 & R92C_RXDW3_HT)) { 2268 switch (rate) { 2269 /* CCK. */ 2270 case 0: tap->wr_rate = 2; break; 2271 case 1: tap->wr_rate = 4; break; 2272 case 2: tap->wr_rate = 11; break; 2273 case 3: tap->wr_rate = 22; break; 2274 /* OFDM. */ 2275 case 4: tap->wr_rate = 12; break; 2276 case 5: tap->wr_rate = 18; break; 2277 case 6: tap->wr_rate = 24; break; 2278 case 7: tap->wr_rate = 36; break; 2279 case 8: tap->wr_rate = 48; break; 2280 case 9: tap->wr_rate = 72; break; 2281 case 10: tap->wr_rate = 96; break; 2282 case 11: tap->wr_rate = 108; break; 2283 } 2284 } else if (rate >= 12) { /* MCS0~15. */ 2285 /* Bit 7 set means HT MCS instead of rate. */ 2286 tap->wr_rate = 0x80 | (rate - 12); 2287 } 2288 tap->wr_dbm_antsignal = rssi; 2289 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2290 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2291 2292 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2293 } 2294 2295 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2296 2297 /* push the frame up to the 802.11 stack */ 2298 ieee80211_input(ic, m, ni, rssi, 0); 2299 2300 /* Node is no longer needed. */ 2301 ieee80211_free_node(ni); 2302 2303 splx(s); 2304 } 2305 2306 static void 2307 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2308 { 2309 struct urtwn_rx_data *data = priv; 2310 struct urtwn_softc *sc = data->sc; 2311 struct r92c_rx_stat *stat; 2312 uint32_t rxdw0; 2313 uint8_t *buf; 2314 int len, totlen, pktlen, infosz, npkts; 2315 2316 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2317 device_xname(sc->sc_dev), __func__, status)); 2318 2319 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2320 if (status == USBD_STALLED) 2321 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2322 else if (status != USBD_CANCELLED) 2323 goto resubmit; 2324 return; 2325 } 2326 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2327 2328 if (__predict_false(len < (int)sizeof(*stat))) { 2329 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2330 device_xname(sc->sc_dev), __func__, len)); 2331 goto resubmit; 2332 } 2333 buf = data->buf; 2334 2335 /* Get the number of encapsulated frames. */ 2336 stat = (struct r92c_rx_stat *)buf; 2337 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2338 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2339 device_xname(sc->sc_dev), __func__, npkts)); 2340 2341 /* Process all of them. */ 2342 while (npkts-- > 0) { 2343 if (__predict_false(len < (int)sizeof(*stat))) { 2344 DPRINTFN(DBG_RX, 2345 ("%s: %s: len(%d) is short than header\n", 2346 device_xname(sc->sc_dev), __func__, len)); 2347 break; 2348 } 2349 stat = (struct r92c_rx_stat *)buf; 2350 rxdw0 = le32toh(stat->rxdw0); 2351 2352 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2353 if (__predict_false(pktlen == 0)) { 2354 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2355 device_xname(sc->sc_dev), __func__)); 2356 break; 2357 } 2358 2359 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2360 2361 /* Make sure everything fits in xfer. */ 2362 totlen = sizeof(*stat) + infosz + pktlen; 2363 if (__predict_false(totlen > len)) { 2364 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2365 device_xname(sc->sc_dev), __func__, totlen, 2366 (int)sizeof(*stat), infosz, pktlen, len)); 2367 break; 2368 } 2369 2370 /* Process 802.11 frame. */ 2371 urtwn_rx_frame(sc, buf, pktlen); 2372 2373 /* Next chunk is 128-byte aligned. */ 2374 totlen = roundup2(totlen, 128); 2375 buf += totlen; 2376 len -= totlen; 2377 } 2378 2379 resubmit: 2380 /* Setup a new transfer. */ 2381 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 2382 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 2383 (void)usbd_transfer(xfer); 2384 } 2385 2386 static void 2387 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2388 { 2389 struct urtwn_tx_data *data = priv; 2390 struct urtwn_softc *sc = data->sc; 2391 struct ifnet *ifp = &sc->sc_if; 2392 usbd_pipe_handle pipe = data->pipe; 2393 int s; 2394 2395 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2396 device_xname(sc->sc_dev), __func__, status)); 2397 2398 mutex_enter(&sc->sc_tx_mtx); 2399 /* Put this Tx buffer back to our free list. */ 2400 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2401 mutex_exit(&sc->sc_tx_mtx); 2402 2403 s = splnet(); 2404 sc->tx_timer = 0; 2405 ifp->if_flags &= ~IFF_OACTIVE; 2406 2407 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2408 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2409 if (status == USBD_STALLED) 2410 usbd_clear_endpoint_stall_async(pipe); 2411 ifp->if_oerrors++; 2412 } 2413 splx(s); 2414 return; 2415 } 2416 2417 ifp->if_opackets++; 2418 urtwn_start(ifp); 2419 2420 splx(s); 2421 } 2422 2423 static int 2424 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2425 struct urtwn_tx_data *data) 2426 { 2427 struct ieee80211com *ic = &sc->sc_ic; 2428 struct ieee80211_frame *wh; 2429 struct ieee80211_key *k = NULL; 2430 struct r92c_tx_desc *txd; 2431 usbd_pipe_handle pipe; 2432 size_t i, padsize, xferlen; 2433 uint16_t seq, sum; 2434 uint8_t raid, type, tid, qid; 2435 int s, hasqos, error; 2436 2437 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2438 2439 wh = mtod(m, struct ieee80211_frame *); 2440 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2441 2442 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2443 k = ieee80211_crypto_encap(ic, ni, m); 2444 if (k == NULL) 2445 return ENOBUFS; 2446 2447 /* packet header may have moved, reset our local pointer */ 2448 wh = mtod(m, struct ieee80211_frame *); 2449 } 2450 2451 if (__predict_false(sc->sc_drvbpf != NULL)) { 2452 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2453 2454 tap->wt_flags = 0; 2455 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2456 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2457 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2458 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2459 2460 /* XXX: set tap->wt_rate? */ 2461 2462 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2463 } 2464 2465 if ((hasqos = ieee80211_has_qos(wh))) { 2466 /* data frames in 11n mode */ 2467 struct ieee80211_qosframe *qwh = (void *)wh; 2468 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2469 qid = TID_TO_WME_AC(tid); 2470 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2471 /* Use AC_VO for management frames. */ 2472 qid = WME_AC_VO; 2473 tid = 0; /* compiler happy */ 2474 } else { 2475 /* non-qos data frames */ 2476 tid = R92C_TXDW1_QSEL_BE; 2477 qid = WME_AC_BE; 2478 } 2479 2480 /* Get the USB pipe to use for this AC. */ 2481 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2482 2483 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2484 padsize = 8; 2485 else 2486 padsize = 0; 2487 2488 /* Fill Tx descriptor. */ 2489 txd = (struct r92c_tx_desc *)data->buf; 2490 memset(txd, 0, sizeof(*txd) + padsize); 2491 2492 txd->txdw0 |= htole32( 2493 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2494 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2495 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2496 2497 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2498 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2499 2500 /* fix pad field */ 2501 if (padsize > 0) { 2502 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2503 device_xname(sc->sc_dev), __func__, padsize)); 2504 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2505 } 2506 2507 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2508 type == IEEE80211_FC0_TYPE_DATA) { 2509 if (ic->ic_curmode == IEEE80211_MODE_11B) 2510 raid = R92C_RAID_11B; 2511 else 2512 raid = R92C_RAID_11BG; 2513 DPRINTFN(DBG_TX, 2514 ("%s: %s: data packet: tid=%d, raid=%d\n", 2515 device_xname(sc->sc_dev), __func__, tid, raid)); 2516 2517 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 2518 txd->txdw1 |= htole32( 2519 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2520 SM(R92C_TXDW1_QSEL, tid) | 2521 SM(R92C_TXDW1_RAID, raid) | 2522 R92C_TXDW1_AGGBK); 2523 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2524 } else 2525 txd->txdw1 |= htole32( 2526 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2527 SM(R92C_TXDW1_QSEL, tid) | 2528 SM(R92C_TXDW1_RAID, raid) | 2529 R92C_TXDW1_AGGBK); 2530 2531 if (hasqos) { 2532 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2533 } 2534 2535 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2536 /* for 11g */ 2537 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2538 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2539 R92C_TXDW4_HWRTSEN); 2540 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2541 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2542 R92C_TXDW4_HWRTSEN); 2543 } 2544 } 2545 /* Send RTS at OFDM24. */ 2546 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2547 txd->txdw5 |= htole32(0x0001ff00); 2548 /* Send data at OFDM54. */ 2549 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2550 txd->txdw5 |= htole32(0x13 & 0x3f); 2551 else 2552 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2553 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2554 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2555 device_xname(sc->sc_dev), __func__)); 2556 txd->txdw1 |= htole32( 2557 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2558 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2559 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2560 2561 /* Force CCK1. */ 2562 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2563 /* Use 1Mbps */ 2564 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2565 } else { 2566 /* broadcast or multicast packets */ 2567 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2568 device_xname(sc->sc_dev), __func__)); 2569 txd->txdw1 |= htole32( 2570 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2571 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2572 2573 /* Force CCK1. */ 2574 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2575 /* Use 1Mbps */ 2576 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2577 } 2578 2579 /* Set sequence number */ 2580 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2581 txd->txdseq |= htole16(seq); 2582 2583 if (!hasqos) { 2584 /* Use HW sequence numbering for non-QoS frames. */ 2585 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2586 txd->txdseq |= htole16(0x8000); /* WTF? */ 2587 } 2588 2589 /* Compute Tx descriptor checksum. */ 2590 sum = 0; 2591 for (i = 0; i < sizeof(*txd) / 2; i++) 2592 sum ^= ((uint16_t *)txd)[i]; 2593 txd->txdsum = sum; /* NB: already little endian. */ 2594 2595 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2596 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2597 2598 s = splnet(); 2599 data->pipe = pipe; 2600 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2601 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2602 urtwn_txeof); 2603 error = usbd_transfer(data->xfer); 2604 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2605 error != USBD_IN_PROGRESS)) { 2606 splx(s); 2607 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2608 device_xname(sc->sc_dev), __func__, error)); 2609 return error; 2610 } 2611 splx(s); 2612 return 0; 2613 } 2614 2615 static void 2616 urtwn_start(struct ifnet *ifp) 2617 { 2618 struct urtwn_softc *sc = ifp->if_softc; 2619 struct ieee80211com *ic = &sc->sc_ic; 2620 struct urtwn_tx_data *data; 2621 struct ether_header *eh; 2622 struct ieee80211_node *ni; 2623 struct mbuf *m; 2624 2625 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2626 2627 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2628 return; 2629 2630 data = NULL; 2631 for (;;) { 2632 mutex_enter(&sc->sc_tx_mtx); 2633 if (data == NULL && !TAILQ_EMPTY(&sc->tx_free_list)) { 2634 data = TAILQ_FIRST(&sc->tx_free_list); 2635 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2636 } 2637 mutex_exit(&sc->sc_tx_mtx); 2638 2639 if (data == NULL) { 2640 ifp->if_flags |= IFF_OACTIVE; 2641 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2642 device_xname(sc->sc_dev))); 2643 return; 2644 } 2645 2646 /* Send pending management frames first. */ 2647 IF_DEQUEUE(&ic->ic_mgtq, m); 2648 if (m != NULL) { 2649 ni = (void *)m->m_pkthdr.rcvif; 2650 m->m_pkthdr.rcvif = NULL; 2651 goto sendit; 2652 } 2653 if (ic->ic_state != IEEE80211_S_RUN) 2654 break; 2655 2656 /* Encapsulate and send data frames. */ 2657 IFQ_DEQUEUE(&ifp->if_snd, m); 2658 if (m == NULL) 2659 break; 2660 2661 if (m->m_len < (int)sizeof(*eh) && 2662 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2663 ifp->if_oerrors++; 2664 continue; 2665 } 2666 eh = mtod(m, struct ether_header *); 2667 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2668 if (ni == NULL) { 2669 m_freem(m); 2670 ifp->if_oerrors++; 2671 continue; 2672 } 2673 2674 bpf_mtap(ifp, m); 2675 2676 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2677 ieee80211_free_node(ni); 2678 ifp->if_oerrors++; 2679 continue; 2680 } 2681 sendit: 2682 bpf_mtap3(ic->ic_rawbpf, m); 2683 2684 if (urtwn_tx(sc, m, ni, data) != 0) { 2685 m_freem(m); 2686 ieee80211_free_node(ni); 2687 ifp->if_oerrors++; 2688 continue; 2689 } 2690 data = NULL; 2691 m_freem(m); 2692 ieee80211_free_node(ni); 2693 sc->tx_timer = 5; 2694 ifp->if_timer = 1; 2695 } 2696 2697 /* Return the Tx buffer to the free list */ 2698 mutex_enter(&sc->sc_tx_mtx); 2699 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2700 mutex_exit(&sc->sc_tx_mtx); 2701 } 2702 2703 static void 2704 urtwn_watchdog(struct ifnet *ifp) 2705 { 2706 struct urtwn_softc *sc = ifp->if_softc; 2707 2708 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2709 2710 ifp->if_timer = 0; 2711 2712 if (sc->tx_timer > 0) { 2713 if (--sc->tx_timer == 0) { 2714 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2715 /* urtwn_init(ifp); XXX needs a process context! */ 2716 ifp->if_oerrors++; 2717 return; 2718 } 2719 ifp->if_timer = 1; 2720 } 2721 ieee80211_watchdog(&sc->sc_ic); 2722 } 2723 2724 static int 2725 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2726 { 2727 struct urtwn_softc *sc = ifp->if_softc; 2728 struct ieee80211com *ic = &sc->sc_ic; 2729 int s, error = 0; 2730 2731 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2732 device_xname(sc->sc_dev), __func__, cmd, data)); 2733 2734 s = splnet(); 2735 2736 switch (cmd) { 2737 case SIOCSIFFLAGS: 2738 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2739 break; 2740 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2741 case IFF_UP | IFF_RUNNING: 2742 break; 2743 case IFF_UP: 2744 urtwn_init(ifp); 2745 break; 2746 case IFF_RUNNING: 2747 urtwn_stop(ifp, 1); 2748 break; 2749 case 0: 2750 break; 2751 } 2752 break; 2753 2754 case SIOCADDMULTI: 2755 case SIOCDELMULTI: 2756 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2757 /* setup multicast filter, etc */ 2758 error = 0; 2759 } 2760 break; 2761 2762 default: 2763 error = ieee80211_ioctl(ic, cmd, data); 2764 break; 2765 } 2766 if (error == ENETRESET) { 2767 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2768 (IFF_UP | IFF_RUNNING) && 2769 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2770 urtwn_init(ifp); 2771 } 2772 error = 0; 2773 } 2774 2775 splx(s); 2776 2777 return (error); 2778 } 2779 2780 static __inline int 2781 urtwn_power_on(struct urtwn_softc *sc) 2782 { 2783 2784 return sc->sc_power_on(sc); 2785 } 2786 2787 static int 2788 urtwn_r92c_power_on(struct urtwn_softc *sc) 2789 { 2790 uint32_t reg; 2791 int ntries; 2792 2793 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2794 2795 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2796 2797 /* Wait for autoload done bit. */ 2798 for (ntries = 0; ntries < 1000; ntries++) { 2799 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2800 break; 2801 DELAY(5); 2802 } 2803 if (ntries == 1000) { 2804 aprint_error_dev(sc->sc_dev, 2805 "timeout waiting for chip autoload\n"); 2806 return (ETIMEDOUT); 2807 } 2808 2809 /* Unlock ISO/CLK/Power control register. */ 2810 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2811 /* Move SPS into PWM mode. */ 2812 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2813 DELAY(100); 2814 2815 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2816 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2817 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2818 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2819 DELAY(100); 2820 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2821 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2822 ~R92C_SYS_ISO_CTRL_MD2PP); 2823 } 2824 2825 /* Auto enable WLAN. */ 2826 urtwn_write_2(sc, R92C_APS_FSMCO, 2827 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2828 for (ntries = 0; ntries < 1000; ntries++) { 2829 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2830 R92C_APS_FSMCO_APFM_ONMAC)) 2831 break; 2832 DELAY(5); 2833 } 2834 if (ntries == 1000) { 2835 aprint_error_dev(sc->sc_dev, 2836 "timeout waiting for MAC auto ON\n"); 2837 return (ETIMEDOUT); 2838 } 2839 2840 /* Enable radio, GPIO and LED functions. */ 2841 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2842 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2843 urtwn_write_2(sc, R92C_APS_FSMCO, 2844 R92C_APS_FSMCO_AFSM_HSUS | 2845 R92C_APS_FSMCO_PDN_EN | 2846 R92C_APS_FSMCO_PFM_ALDN); 2847 2848 /* Release RF digital isolation. */ 2849 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2850 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2851 2852 /* Initialize MAC. */ 2853 urtwn_write_1(sc, R92C_APSD_CTRL, 2854 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2855 for (ntries = 0; ntries < 200; ntries++) { 2856 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2857 R92C_APSD_CTRL_OFF_STATUS)) 2858 break; 2859 DELAY(5); 2860 } 2861 if (ntries == 200) { 2862 aprint_error_dev(sc->sc_dev, 2863 "timeout waiting for MAC initialization\n"); 2864 return (ETIMEDOUT); 2865 } 2866 2867 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2868 reg = urtwn_read_2(sc, R92C_CR); 2869 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2870 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2871 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2872 R92C_CR_ENSEC; 2873 urtwn_write_2(sc, R92C_CR, reg); 2874 2875 urtwn_write_1(sc, 0xfe10, 0x19); 2876 return (0); 2877 } 2878 2879 static int 2880 urtwn_r88e_power_on(struct urtwn_softc *sc) 2881 { 2882 uint32_t reg; 2883 uint8_t val; 2884 int ntries; 2885 2886 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2887 2888 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2889 2890 /* Wait for power ready bit. */ 2891 for (ntries = 0; ntries < 5000; ntries++) { 2892 val = urtwn_read_1(sc, 0x6) & 0x2; 2893 if (val == 0x2) 2894 break; 2895 DELAY(10); 2896 } 2897 if (ntries == 5000) { 2898 aprint_error_dev(sc->sc_dev, 2899 "timeout waiting for chip power up\n"); 2900 return (ETIMEDOUT); 2901 } 2902 2903 /* Reset BB. */ 2904 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2905 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2906 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2907 2908 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2909 2910 /* Disable HWPDN. */ 2911 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2912 2913 /* Disable WL suspend. */ 2914 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2915 2916 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2917 for (ntries = 0; ntries < 5000; ntries++) { 2918 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2919 break; 2920 DELAY(10); 2921 } 2922 if (ntries == 5000) 2923 return (ETIMEDOUT); 2924 2925 /* Enable LDO normal mode. */ 2926 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2927 2928 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2929 urtwn_write_2(sc, R92C_CR, 0); 2930 reg = urtwn_read_2(sc, R92C_CR); 2931 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2932 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2933 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2934 urtwn_write_2(sc, R92C_CR, reg); 2935 2936 return (0); 2937 } 2938 2939 static int 2940 urtwn_llt_init(struct urtwn_softc *sc) 2941 { 2942 size_t i, page_count, pktbuf_count; 2943 int error; 2944 2945 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2946 2947 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2948 2949 page_count = (sc->chip & URTWN_CHIP_88E) ? 2950 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2951 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2952 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2953 2954 /* Reserve pages [0; page_count]. */ 2955 for (i = 0; i < page_count; i++) { 2956 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2957 return (error); 2958 } 2959 /* NB: 0xff indicates end-of-list. */ 2960 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2961 return (error); 2962 /* 2963 * Use pages [page_count + 1; pktbuf_count - 1] 2964 * as ring buffer. 2965 */ 2966 for (++i; i < pktbuf_count - 1; i++) { 2967 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2968 return (error); 2969 } 2970 /* Make the last page point to the beginning of the ring buffer. */ 2971 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 2972 return (error); 2973 } 2974 2975 static void 2976 urtwn_fw_reset(struct urtwn_softc *sc) 2977 { 2978 uint16_t reg; 2979 int ntries; 2980 2981 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2982 2983 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2984 2985 /* Tell 8051 to reset itself. */ 2986 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2987 2988 /* Wait until 8051 resets by itself. */ 2989 for (ntries = 0; ntries < 100; ntries++) { 2990 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2991 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2992 return; 2993 DELAY(50); 2994 } 2995 /* Force 8051 reset. */ 2996 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2997 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 2998 } 2999 3000 static void 3001 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3002 { 3003 uint16_t reg; 3004 3005 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3006 3007 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3008 3009 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3010 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3011 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3012 } 3013 3014 static int 3015 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3016 { 3017 uint32_t reg; 3018 int off, mlen, error = 0; 3019 3020 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3021 device_xname(sc->sc_dev), __func__, page, buf, len)); 3022 3023 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3024 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3025 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3026 3027 off = R92C_FW_START_ADDR; 3028 while (len > 0) { 3029 if (len > 196) 3030 mlen = 196; 3031 else if (len > 4) 3032 mlen = 4; 3033 else 3034 mlen = 1; 3035 error = urtwn_write_region(sc, off, buf, mlen); 3036 if (error != 0) 3037 break; 3038 off += mlen; 3039 buf += mlen; 3040 len -= mlen; 3041 } 3042 return (error); 3043 } 3044 3045 static int 3046 urtwn_load_firmware(struct urtwn_softc *sc) 3047 { 3048 firmware_handle_t fwh; 3049 const struct r92c_fw_hdr *hdr; 3050 const char *name; 3051 u_char *fw, *ptr; 3052 size_t len; 3053 uint32_t reg; 3054 int mlen, ntries, page, error; 3055 3056 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3057 3058 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3059 3060 /* Read firmware image from the filesystem. */ 3061 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3062 name = "rtl8188eufw.bin"; 3063 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3064 URTWN_CHIP_UMC_A_CUT) 3065 name = "rtl8192cfwU.bin"; 3066 else 3067 name = "rtl8192cfw.bin"; 3068 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3069 aprint_error_dev(sc->sc_dev, 3070 "failed load firmware of file %s (error %d)\n", name, 3071 error); 3072 return (error); 3073 } 3074 len = firmware_get_size(fwh); 3075 fw = firmware_malloc(len); 3076 if (fw == NULL) { 3077 aprint_error_dev(sc->sc_dev, 3078 "failed to allocate firmware memory\n"); 3079 firmware_close(fwh); 3080 return (ENOMEM); 3081 } 3082 error = firmware_read(fwh, 0, fw, len); 3083 firmware_close(fwh); 3084 if (error != 0) { 3085 aprint_error_dev(sc->sc_dev, 3086 "failed to read firmware (error %d)\n", error); 3087 firmware_free(fw, 0); 3088 return (error); 3089 } 3090 3091 ptr = fw; 3092 hdr = (const struct r92c_fw_hdr *)ptr; 3093 /* Check if there is a valid FW header and skip it. */ 3094 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3095 (le16toh(hdr->signature) >> 4) == 0x88e || 3096 (le16toh(hdr->signature) >> 4) == 0x92c) { 3097 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3098 device_xname(sc->sc_dev), __func__, 3099 le16toh(hdr->version), le16toh(hdr->subversion), 3100 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3101 ptr += sizeof(*hdr); 3102 len -= sizeof(*hdr); 3103 } 3104 3105 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3106 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3107 urtwn_r88e_fw_reset(sc); 3108 else 3109 urtwn_fw_reset(sc); 3110 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3111 } 3112 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3113 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3114 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3115 R92C_SYS_FUNC_EN_CPUEN); 3116 } 3117 3118 /* download enabled */ 3119 urtwn_write_1(sc, R92C_MCUFWDL, 3120 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3121 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3122 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3123 3124 /* Reset the FWDL checksum. */ 3125 urtwn_write_1(sc, R92C_MCUFWDL, 3126 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3127 3128 /* download firmware */ 3129 for (page = 0; len > 0; page++) { 3130 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3131 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3132 if (error != 0) { 3133 aprint_error_dev(sc->sc_dev, 3134 "could not load firmware page %d\n", page); 3135 goto fail; 3136 } 3137 ptr += mlen; 3138 len -= mlen; 3139 } 3140 3141 /* download disable */ 3142 urtwn_write_1(sc, R92C_MCUFWDL, 3143 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3144 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3145 3146 /* Wait for checksum report. */ 3147 for (ntries = 0; ntries < 1000; ntries++) { 3148 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3149 break; 3150 DELAY(5); 3151 } 3152 if (ntries == 1000) { 3153 aprint_error_dev(sc->sc_dev, 3154 "timeout waiting for checksum report\n"); 3155 error = ETIMEDOUT; 3156 goto fail; 3157 } 3158 3159 /* Wait for firmware readiness. */ 3160 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3161 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3162 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3163 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3164 urtwn_r88e_fw_reset(sc); 3165 for (ntries = 0; ntries < 1000; ntries++) { 3166 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3167 break; 3168 DELAY(5); 3169 } 3170 if (ntries == 1000) { 3171 aprint_error_dev(sc->sc_dev, 3172 "timeout waiting for firmware readiness\n"); 3173 error = ETIMEDOUT; 3174 goto fail; 3175 } 3176 fail: 3177 firmware_free(fw, 0); 3178 return (error); 3179 } 3180 3181 static __inline int 3182 urtwn_dma_init(struct urtwn_softc *sc) 3183 { 3184 3185 return sc->sc_dma_init(sc); 3186 } 3187 3188 static int 3189 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3190 { 3191 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3192 uint32_t reg; 3193 int error; 3194 3195 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3196 3197 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3198 3199 /* Initialize LLT table. */ 3200 error = urtwn_llt_init(sc); 3201 if (error != 0) 3202 return (error); 3203 3204 /* Get Tx queues to USB endpoints mapping. */ 3205 hashq = hasnq = haslq = 0; 3206 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3207 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3208 device_xname(sc->sc_dev), __func__, reg)); 3209 if (MS(reg, R92C_USB_EP_HQ) != 0) 3210 hashq = 1; 3211 if (MS(reg, R92C_USB_EP_NQ) != 0) 3212 hasnq = 1; 3213 if (MS(reg, R92C_USB_EP_LQ) != 0) 3214 haslq = 1; 3215 nqueues = hashq + hasnq + haslq; 3216 if (nqueues == 0) 3217 return (EIO); 3218 /* Get the number of pages for each queue. */ 3219 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3220 /* The remaining pages are assigned to the high priority queue. */ 3221 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3222 3223 /* Set number of pages for normal priority queue. */ 3224 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3225 urtwn_write_4(sc, R92C_RQPN, 3226 /* Set number of pages for public queue. */ 3227 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3228 /* Set number of pages for high priority queue. */ 3229 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3230 /* Set number of pages for low priority queue. */ 3231 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3232 /* Load values. */ 3233 R92C_RQPN_LD); 3234 3235 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3236 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3237 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3238 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3239 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3240 3241 /* Set queue to USB pipe mapping. */ 3242 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3243 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3244 if (nqueues == 1) { 3245 if (hashq) { 3246 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3247 } else if (hasnq) { 3248 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3249 } else { 3250 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3251 } 3252 } else if (nqueues == 2) { 3253 /* All 2-endpoints configs have a high priority queue. */ 3254 if (!hashq) { 3255 return (EIO); 3256 } 3257 if (hasnq) { 3258 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3259 } else { 3260 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3261 } 3262 } else { 3263 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3264 } 3265 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3266 3267 /* Set Tx/Rx transfer page boundary. */ 3268 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3269 3270 /* Set Tx/Rx transfer page size. */ 3271 urtwn_write_1(sc, R92C_PBP, 3272 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3273 return (0); 3274 } 3275 3276 static int 3277 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3278 { 3279 usb_interface_descriptor_t *id; 3280 uint32_t reg; 3281 int nqueues; 3282 int error; 3283 3284 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3285 3286 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3287 3288 /* Initialize LLT table. */ 3289 error = urtwn_llt_init(sc); 3290 if (error != 0) 3291 return (error); 3292 3293 /* Get Tx queues to USB endpoints mapping. */ 3294 id = usbd_get_interface_descriptor(sc->sc_iface); 3295 nqueues = id->bNumEndpoints - 1; 3296 if (nqueues == 0) 3297 return (EIO); 3298 3299 /* Set number of pages for normal priority queue. */ 3300 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3301 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3302 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3303 3304 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3305 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3306 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3307 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3308 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3309 3310 /* Set queue to USB pipe mapping. */ 3311 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3312 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3313 if (nqueues == 1) 3314 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3315 else if (nqueues == 2) 3316 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3317 else 3318 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3319 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3320 3321 /* Set Tx/Rx transfer page boundary. */ 3322 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3323 3324 /* Set Tx/Rx transfer page size. */ 3325 urtwn_write_1(sc, R92C_PBP, 3326 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3327 3328 return (0); 3329 } 3330 3331 static void 3332 urtwn_mac_init(struct urtwn_softc *sc) 3333 { 3334 size_t i; 3335 3336 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3337 3338 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3339 3340 /* Write MAC initialization values. */ 3341 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3342 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3343 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3344 rtl8188eu_mac[i].val); 3345 } else { 3346 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3347 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3348 rtl8192cu_mac[i].val); 3349 } 3350 } 3351 3352 static void 3353 urtwn_bb_init(struct urtwn_softc *sc) 3354 { 3355 const struct urtwn_bb_prog *prog; 3356 uint32_t reg; 3357 uint8_t crystalcap; 3358 size_t i; 3359 3360 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3361 3362 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3363 3364 /* Enable BB and RF. */ 3365 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3366 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3367 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3368 R92C_SYS_FUNC_EN_DIO_RF); 3369 3370 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3371 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3372 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3373 } 3374 3375 urtwn_write_1(sc, R92C_RF_CTRL, 3376 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3377 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3378 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3379 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3380 3381 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3382 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3383 urtwn_write_1(sc, 0x15, 0xe9); 3384 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3385 } 3386 3387 /* Select BB programming based on board type. */ 3388 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3389 prog = &rtl8188eu_bb_prog; 3390 else if (!(sc->chip & URTWN_CHIP_92C)) { 3391 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3392 prog = &rtl8188ce_bb_prog; 3393 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3394 prog = &rtl8188ru_bb_prog; 3395 } else { 3396 prog = &rtl8188cu_bb_prog; 3397 } 3398 } else { 3399 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3400 prog = &rtl8192ce_bb_prog; 3401 } else { 3402 prog = &rtl8192cu_bb_prog; 3403 } 3404 } 3405 /* Write BB initialization values. */ 3406 for (i = 0; i < prog->count; i++) { 3407 /* additional delay depend on registers */ 3408 switch (prog->regs[i]) { 3409 case 0xfe: 3410 usbd_delay_ms(sc->sc_udev, 50); 3411 break; 3412 case 0xfd: 3413 usbd_delay_ms(sc->sc_udev, 5); 3414 break; 3415 case 0xfc: 3416 usbd_delay_ms(sc->sc_udev, 1); 3417 break; 3418 case 0xfb: 3419 DELAY(50); 3420 break; 3421 case 0xfa: 3422 DELAY(5); 3423 break; 3424 case 0xf9: 3425 DELAY(1); 3426 break; 3427 } 3428 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3429 DELAY(1); 3430 } 3431 3432 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3433 /* 8192C 1T only configuration. */ 3434 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3435 reg = (reg & ~0x00000003) | 0x2; 3436 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3437 3438 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3439 reg = (reg & ~0x00300033) | 0x00200022; 3440 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3441 3442 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3443 reg = (reg & ~0xff000000) | (0x45 << 24); 3444 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3445 3446 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3447 reg = (reg & ~0x000000ff) | 0x23; 3448 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3449 3450 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3451 reg = (reg & ~0x00000030) | (1 << 4); 3452 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3453 3454 reg = urtwn_bb_read(sc, 0xe74); 3455 reg = (reg & ~0x0c000000) | (2 << 26); 3456 urtwn_bb_write(sc, 0xe74, reg); 3457 reg = urtwn_bb_read(sc, 0xe78); 3458 reg = (reg & ~0x0c000000) | (2 << 26); 3459 urtwn_bb_write(sc, 0xe78, reg); 3460 reg = urtwn_bb_read(sc, 0xe7c); 3461 reg = (reg & ~0x0c000000) | (2 << 26); 3462 urtwn_bb_write(sc, 0xe7c, reg); 3463 reg = urtwn_bb_read(sc, 0xe80); 3464 reg = (reg & ~0x0c000000) | (2 << 26); 3465 urtwn_bb_write(sc, 0xe80, reg); 3466 reg = urtwn_bb_read(sc, 0xe88); 3467 reg = (reg & ~0x0c000000) | (2 << 26); 3468 urtwn_bb_write(sc, 0xe88, reg); 3469 } 3470 3471 /* Write AGC values. */ 3472 for (i = 0; i < prog->agccount; i++) { 3473 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3474 DELAY(1); 3475 } 3476 3477 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3478 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3479 DELAY(1); 3480 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3481 DELAY(1); 3482 3483 crystalcap = sc->r88e_rom[0xb9]; 3484 if (crystalcap == 0xff) 3485 crystalcap = 0x20; 3486 crystalcap &= 0x3f; 3487 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3488 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3489 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3490 crystalcap | crystalcap << 6)); 3491 } else { 3492 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3493 R92C_HSSI_PARAM2_CCK_HIPWR) { 3494 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3495 } 3496 } 3497 } 3498 3499 static void 3500 urtwn_rf_init(struct urtwn_softc *sc) 3501 { 3502 const struct urtwn_rf_prog *prog; 3503 uint32_t reg, mask, saved; 3504 size_t i, j, idx; 3505 3506 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3507 3508 /* Select RF programming based on board type. */ 3509 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3510 prog = rtl8188eu_rf_prog; 3511 else if (!(sc->chip & URTWN_CHIP_92C)) { 3512 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3513 prog = rtl8188ce_rf_prog; 3514 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3515 prog = rtl8188ru_rf_prog; 3516 } else { 3517 prog = rtl8188cu_rf_prog; 3518 } 3519 } else { 3520 prog = rtl8192ce_rf_prog; 3521 } 3522 3523 for (i = 0; i < sc->nrxchains; i++) { 3524 /* Save RF_ENV control type. */ 3525 idx = i / 2; 3526 mask = 0xffffU << ((i % 2) * 16); 3527 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3528 3529 /* Set RF_ENV enable. */ 3530 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3531 reg |= 0x100000; 3532 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3533 DELAY(1); 3534 3535 /* Set RF_ENV output high. */ 3536 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3537 reg |= 0x10; 3538 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3539 DELAY(1); 3540 3541 /* Set address and data lengths of RF registers. */ 3542 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3543 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3544 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3545 DELAY(1); 3546 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3547 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3548 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3549 DELAY(1); 3550 3551 /* Write RF initialization values for this chain. */ 3552 for (j = 0; j < prog[i].count; j++) { 3553 if (prog[i].regs[j] >= 0xf9 && 3554 prog[i].regs[j] <= 0xfe) { 3555 /* 3556 * These are fake RF registers offsets that 3557 * indicate a delay is required. 3558 */ 3559 usbd_delay_ms(sc->sc_udev, 50); 3560 continue; 3561 } 3562 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3563 DELAY(1); 3564 } 3565 3566 /* Restore RF_ENV control type. */ 3567 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3568 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3569 } 3570 3571 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3572 URTWN_CHIP_UMC_A_CUT) { 3573 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3574 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3575 } 3576 3577 /* Cache RF register CHNLBW. */ 3578 for (i = 0; i < 2; i++) { 3579 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3580 } 3581 } 3582 3583 static void 3584 urtwn_cam_init(struct urtwn_softc *sc) 3585 { 3586 uint32_t content, command; 3587 uint8_t idx; 3588 size_t i; 3589 3590 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3591 3592 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3593 3594 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3595 content = (idx & 3) 3596 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3597 | R92C_CAM_VALID; 3598 3599 command = R92C_CAMCMD_POLLING 3600 | R92C_CAMCMD_WRITE 3601 | R92C_CAM_CTL0(idx); 3602 3603 urtwn_write_4(sc, R92C_CAMWRITE, content); 3604 urtwn_write_4(sc, R92C_CAMCMD, command); 3605 } 3606 3607 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3608 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3609 if (i == 0) { 3610 content = (idx & 3) 3611 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3612 | R92C_CAM_VALID; 3613 } else { 3614 content = 0; 3615 } 3616 3617 command = R92C_CAMCMD_POLLING 3618 | R92C_CAMCMD_WRITE 3619 | R92C_CAM_CTL0(idx) 3620 | i; 3621 3622 urtwn_write_4(sc, R92C_CAMWRITE, content); 3623 urtwn_write_4(sc, R92C_CAMCMD, command); 3624 } 3625 } 3626 3627 /* Invalidate all CAM entries. */ 3628 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3629 } 3630 3631 static void 3632 urtwn_pa_bias_init(struct urtwn_softc *sc) 3633 { 3634 uint8_t reg; 3635 size_t i; 3636 3637 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3638 3639 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3640 3641 for (i = 0; i < sc->nrxchains; i++) { 3642 if (sc->pa_setting & (1U << i)) 3643 continue; 3644 3645 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3646 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3647 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3648 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3649 } 3650 if (!(sc->pa_setting & 0x10)) { 3651 reg = urtwn_read_1(sc, 0x16); 3652 reg = (reg & ~0xf0) | 0x90; 3653 urtwn_write_1(sc, 0x16, reg); 3654 } 3655 } 3656 3657 static void 3658 urtwn_rxfilter_init(struct urtwn_softc *sc) 3659 { 3660 3661 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3662 3663 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3664 3665 /* Initialize Rx filter. */ 3666 /* TODO: use better filter for monitor mode. */ 3667 urtwn_write_4(sc, R92C_RCR, 3668 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3669 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3670 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3671 /* Accept all multicast frames. */ 3672 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3673 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3674 /* Accept all management frames. */ 3675 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3676 /* Reject all control frames. */ 3677 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3678 /* Accept all data frames. */ 3679 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3680 } 3681 3682 static void 3683 urtwn_edca_init(struct urtwn_softc *sc) 3684 { 3685 3686 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3687 3688 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3689 3690 /* set spec SIFS (used in NAV) */ 3691 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3692 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3693 3694 /* set SIFS CCK/OFDM */ 3695 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3696 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3697 3698 /* TXOP */ 3699 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3700 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3701 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3702 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3703 } 3704 3705 static void 3706 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3707 uint16_t power[URTWN_RIDX_COUNT]) 3708 { 3709 uint32_t reg; 3710 3711 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3712 __func__, chain)); 3713 3714 /* Write per-CCK rate Tx power. */ 3715 if (chain == 0) { 3716 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3717 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3718 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3719 3720 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3721 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3722 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3723 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3724 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3725 } else { 3726 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3727 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3728 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3729 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3730 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3731 3732 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3733 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3734 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3735 } 3736 /* Write per-OFDM rate Tx power. */ 3737 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3738 SM(R92C_TXAGC_RATE06, power[ 4]) | 3739 SM(R92C_TXAGC_RATE09, power[ 5]) | 3740 SM(R92C_TXAGC_RATE12, power[ 6]) | 3741 SM(R92C_TXAGC_RATE18, power[ 7])); 3742 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3743 SM(R92C_TXAGC_RATE24, power[ 8]) | 3744 SM(R92C_TXAGC_RATE36, power[ 9]) | 3745 SM(R92C_TXAGC_RATE48, power[10]) | 3746 SM(R92C_TXAGC_RATE54, power[11])); 3747 /* Write per-MCS Tx power. */ 3748 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3749 SM(R92C_TXAGC_MCS00, power[12]) | 3750 SM(R92C_TXAGC_MCS01, power[13]) | 3751 SM(R92C_TXAGC_MCS02, power[14]) | 3752 SM(R92C_TXAGC_MCS03, power[15])); 3753 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3754 SM(R92C_TXAGC_MCS04, power[16]) | 3755 SM(R92C_TXAGC_MCS05, power[17]) | 3756 SM(R92C_TXAGC_MCS06, power[18]) | 3757 SM(R92C_TXAGC_MCS07, power[19])); 3758 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3759 SM(R92C_TXAGC_MCS08, power[20]) | 3760 SM(R92C_TXAGC_MCS09, power[21]) | 3761 SM(R92C_TXAGC_MCS10, power[22]) | 3762 SM(R92C_TXAGC_MCS11, power[23])); 3763 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3764 SM(R92C_TXAGC_MCS12, power[24]) | 3765 SM(R92C_TXAGC_MCS13, power[25]) | 3766 SM(R92C_TXAGC_MCS14, power[26]) | 3767 SM(R92C_TXAGC_MCS15, power[27])); 3768 } 3769 3770 static void 3771 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 3772 uint16_t power[URTWN_RIDX_COUNT]) 3773 { 3774 struct r92c_rom *rom = &sc->rom; 3775 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3776 const struct urtwn_txpwr *base; 3777 int ridx, group; 3778 3779 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3780 device_xname(sc->sc_dev), __func__, chain, chan)); 3781 3782 /* Determine channel group. */ 3783 if (chan <= 3) { 3784 group = 0; 3785 } else if (chan <= 9) { 3786 group = 1; 3787 } else { 3788 group = 2; 3789 } 3790 3791 /* Get original Tx power based on board type and RF chain. */ 3792 if (!(sc->chip & URTWN_CHIP_92C)) { 3793 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3794 base = &rtl8188ru_txagc[chain]; 3795 } else { 3796 base = &rtl8192cu_txagc[chain]; 3797 } 3798 } else { 3799 base = &rtl8192cu_txagc[chain]; 3800 } 3801 3802 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3803 if (sc->regulatory == 0) { 3804 for (ridx = 0; ridx <= 3; ridx++) { 3805 power[ridx] = base->pwr[0][ridx]; 3806 } 3807 } 3808 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3809 if (sc->regulatory == 3) { 3810 power[ridx] = base->pwr[0][ridx]; 3811 /* Apply vendor limits. */ 3812 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3813 maxpow = rom->ht40_max_pwr[group]; 3814 } else { 3815 maxpow = rom->ht20_max_pwr[group]; 3816 } 3817 maxpow = (maxpow >> (chain * 4)) & 0xf; 3818 if (power[ridx] > maxpow) { 3819 power[ridx] = maxpow; 3820 } 3821 } else if (sc->regulatory == 1) { 3822 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3823 power[ridx] = base->pwr[group][ridx]; 3824 } 3825 } else if (sc->regulatory != 2) { 3826 power[ridx] = base->pwr[0][ridx]; 3827 } 3828 } 3829 3830 /* Compute per-CCK rate Tx power. */ 3831 cckpow = rom->cck_tx_pwr[chain][group]; 3832 for (ridx = 0; ridx <= 3; ridx++) { 3833 power[ridx] += cckpow; 3834 if (power[ridx] > R92C_MAX_TX_PWR) { 3835 power[ridx] = R92C_MAX_TX_PWR; 3836 } 3837 } 3838 3839 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3840 if (sc->ntxchains > 1) { 3841 /* Apply reduction for 2 spatial streams. */ 3842 diff = rom->ht40_2s_tx_pwr_diff[group]; 3843 diff = (diff >> (chain * 4)) & 0xf; 3844 htpow = (htpow > diff) ? htpow - diff : 0; 3845 } 3846 3847 /* Compute per-OFDM rate Tx power. */ 3848 diff = rom->ofdm_tx_pwr_diff[group]; 3849 diff = (diff >> (chain * 4)) & 0xf; 3850 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3851 for (ridx = 4; ridx <= 11; ridx++) { 3852 power[ridx] += ofdmpow; 3853 if (power[ridx] > R92C_MAX_TX_PWR) { 3854 power[ridx] = R92C_MAX_TX_PWR; 3855 } 3856 } 3857 3858 /* Compute per-MCS Tx power. */ 3859 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3860 diff = rom->ht20_tx_pwr_diff[group]; 3861 diff = (diff >> (chain * 4)) & 0xf; 3862 htpow += diff; /* HT40->HT20 correction. */ 3863 } 3864 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3865 power[ridx] += htpow; 3866 if (power[ridx] > R92C_MAX_TX_PWR) { 3867 power[ridx] = R92C_MAX_TX_PWR; 3868 } 3869 } 3870 #ifdef URTWN_DEBUG 3871 if (urtwn_debug & DBG_RF) { 3872 /* Dump per-rate Tx power values. */ 3873 printf("%s: %s: Tx power for chain %zd:\n", 3874 device_xname(sc->sc_dev), __func__, chain); 3875 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3876 printf("%s: %s: Rate %d = %u\n", 3877 device_xname(sc->sc_dev), __func__, ridx, 3878 power[ridx]); 3879 } 3880 } 3881 #endif 3882 } 3883 3884 void 3885 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 3886 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 3887 { 3888 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3889 const struct urtwn_r88e_txpwr *base; 3890 int ridx, group; 3891 3892 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3893 device_xname(sc->sc_dev), __func__, chain, chan)); 3894 3895 /* Determine channel group. */ 3896 if (chan <= 2) 3897 group = 0; 3898 else if (chan <= 5) 3899 group = 1; 3900 else if (chan <= 8) 3901 group = 2; 3902 else if (chan <= 11) 3903 group = 3; 3904 else if (chan <= 13) 3905 group = 4; 3906 else 3907 group = 5; 3908 3909 /* Get original Tx power based on board type and RF chain. */ 3910 base = &rtl8188eu_txagc[chain]; 3911 3912 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3913 if (sc->regulatory == 0) { 3914 for (ridx = 0; ridx <= 3; ridx++) 3915 power[ridx] = base->pwr[0][ridx]; 3916 } 3917 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3918 if (sc->regulatory == 3) 3919 power[ridx] = base->pwr[0][ridx]; 3920 else if (sc->regulatory == 1) { 3921 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 3922 power[ridx] = base->pwr[group][ridx]; 3923 } else if (sc->regulatory != 2) 3924 power[ridx] = base->pwr[0][ridx]; 3925 } 3926 3927 /* Compute per-CCK rate Tx power. */ 3928 cckpow = sc->cck_tx_pwr[group]; 3929 for (ridx = 0; ridx <= 3; ridx++) { 3930 power[ridx] += cckpow; 3931 if (power[ridx] > R92C_MAX_TX_PWR) 3932 power[ridx] = R92C_MAX_TX_PWR; 3933 } 3934 3935 htpow = sc->ht40_tx_pwr[group]; 3936 3937 /* Compute per-OFDM rate Tx power. */ 3938 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3939 for (ridx = 4; ridx <= 11; ridx++) { 3940 power[ridx] += ofdmpow; 3941 if (power[ridx] > R92C_MAX_TX_PWR) 3942 power[ridx] = R92C_MAX_TX_PWR; 3943 } 3944 3945 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3946 for (ridx = 12; ridx <= 27; ridx++) { 3947 power[ridx] += bw20pow; 3948 if (power[ridx] > R92C_MAX_TX_PWR) 3949 power[ridx] = R92C_MAX_TX_PWR; 3950 } 3951 } 3952 3953 static void 3954 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3955 { 3956 uint16_t power[URTWN_RIDX_COUNT]; 3957 size_t i; 3958 3959 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3960 3961 for (i = 0; i < sc->ntxchains; i++) { 3962 /* Compute per-rate Tx power values. */ 3963 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3964 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 3965 else 3966 urtwn_get_txpower(sc, i, chan, ht40m, power); 3967 /* Write per-rate Tx power values to hardware. */ 3968 urtwn_write_txpower(sc, i, power); 3969 } 3970 } 3971 3972 static void 3973 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3974 { 3975 struct ieee80211com *ic = &sc->sc_ic; 3976 u_int chan; 3977 size_t i; 3978 3979 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3980 3981 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3982 __func__, chan)); 3983 3984 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3985 3986 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3987 chan += 2; 3988 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3989 chan -= 2; 3990 } 3991 3992 /* Set Tx power for this new channel. */ 3993 urtwn_set_txpower(sc, chan, ht40m); 3994 3995 for (i = 0; i < sc->nrxchains; i++) { 3996 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3997 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3998 } 3999 4000 if (ht40m) { 4001 /* Is secondary channel below or above primary? */ 4002 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4003 uint32_t reg; 4004 4005 urtwn_write_1(sc, R92C_BWOPMODE, 4006 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4007 4008 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4009 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4010 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4011 4012 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4013 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4014 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4015 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4016 4017 /* Set CCK side band. */ 4018 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4019 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4020 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4021 4022 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4023 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4024 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4025 4026 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4027 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4028 ~R92C_FPGA0_ANAPARAM2_CBW20); 4029 4030 reg = urtwn_bb_read(sc, 0x818); 4031 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4032 urtwn_bb_write(sc, 0x818, reg); 4033 4034 /* Select 40MHz bandwidth. */ 4035 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4036 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4037 } else { 4038 urtwn_write_1(sc, R92C_BWOPMODE, 4039 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4040 4041 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4042 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4043 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4044 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4045 4046 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4047 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4048 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4049 R92C_FPGA0_ANAPARAM2_CBW20); 4050 } 4051 4052 /* Select 20MHz bandwidth. */ 4053 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4054 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4055 (ISSET(sc->chip, URTWN_CHIP_88E) ? 4056 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4057 } 4058 } 4059 4060 static void 4061 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4062 { 4063 4064 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4065 __func__, inited)); 4066 4067 /* TODO */ 4068 } 4069 4070 static void 4071 urtwn_lc_calib(struct urtwn_softc *sc) 4072 { 4073 uint32_t rf_ac[2]; 4074 uint8_t txmode; 4075 size_t i; 4076 4077 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4078 4079 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4080 4081 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4082 if ((txmode & 0x70) != 0) { 4083 /* Disable all continuous Tx. */ 4084 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4085 4086 /* Set RF mode to standby mode. */ 4087 for (i = 0; i < sc->nrxchains; i++) { 4088 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4089 urtwn_rf_write(sc, i, R92C_RF_AC, 4090 RW(rf_ac[i], R92C_RF_AC_MODE, 4091 R92C_RF_AC_MODE_STANDBY)); 4092 } 4093 } else { 4094 /* Block all Tx queues. */ 4095 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4096 } 4097 /* Start calibration. */ 4098 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4099 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4100 4101 /* Give calibration the time to complete. */ 4102 usbd_delay_ms(sc->sc_udev, 100); 4103 4104 /* Restore configuration. */ 4105 if ((txmode & 0x70) != 0) { 4106 /* Restore Tx mode. */ 4107 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4108 /* Restore RF mode. */ 4109 for (i = 0; i < sc->nrxchains; i++) { 4110 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4111 } 4112 } else { 4113 /* Unblock all Tx queues. */ 4114 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4115 } 4116 } 4117 4118 static void 4119 urtwn_temp_calib(struct urtwn_softc *sc) 4120 { 4121 int temp; 4122 4123 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4124 4125 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4126 4127 if (sc->thcal_state == 0) { 4128 /* Start measuring temperature. */ 4129 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4130 device_xname(sc->sc_dev), __func__)); 4131 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 4132 sc->thcal_state = 1; 4133 return; 4134 } 4135 sc->thcal_state = 0; 4136 4137 /* Read measured temperature. */ 4138 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4139 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4140 __func__, temp)); 4141 if (temp == 0) /* Read failed, skip. */ 4142 return; 4143 4144 /* 4145 * Redo LC calibration if temperature changed significantly since 4146 * last calibration. 4147 */ 4148 if (sc->thcal_lctemp == 0) { 4149 /* First LC calibration is performed in urtwn_init(). */ 4150 sc->thcal_lctemp = temp; 4151 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4152 DPRINTFN(DBG_RF, 4153 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4154 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4155 temp)); 4156 urtwn_lc_calib(sc); 4157 /* Record temperature of last LC calibration. */ 4158 sc->thcal_lctemp = temp; 4159 } 4160 } 4161 4162 static int 4163 urtwn_init(struct ifnet *ifp) 4164 { 4165 struct urtwn_softc *sc = ifp->if_softc; 4166 struct ieee80211com *ic = &sc->sc_ic; 4167 struct urtwn_rx_data *data; 4168 uint32_t reg; 4169 size_t i; 4170 int error; 4171 4172 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4173 4174 urtwn_stop(ifp, 0); 4175 4176 mutex_enter(&sc->sc_write_mtx); 4177 4178 mutex_enter(&sc->sc_task_mtx); 4179 /* Init host async commands ring. */ 4180 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4181 mutex_exit(&sc->sc_task_mtx); 4182 4183 mutex_enter(&sc->sc_fwcmd_mtx); 4184 /* Init firmware commands ring. */ 4185 sc->fwcur = 0; 4186 mutex_exit(&sc->sc_fwcmd_mtx); 4187 4188 /* Allocate Tx/Rx buffers. */ 4189 error = urtwn_alloc_rx_list(sc); 4190 if (error != 0) { 4191 aprint_error_dev(sc->sc_dev, 4192 "could not allocate Rx buffers\n"); 4193 goto fail; 4194 } 4195 error = urtwn_alloc_tx_list(sc); 4196 if (error != 0) { 4197 aprint_error_dev(sc->sc_dev, 4198 "could not allocate Tx buffers\n"); 4199 goto fail; 4200 } 4201 4202 /* Power on adapter. */ 4203 error = urtwn_power_on(sc); 4204 if (error != 0) 4205 goto fail; 4206 4207 /* Initialize DMA. */ 4208 error = urtwn_dma_init(sc); 4209 if (error != 0) 4210 goto fail; 4211 4212 /* Set info size in Rx descriptors (in 64-bit words). */ 4213 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4214 4215 /* Init interrupts. */ 4216 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4217 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4218 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4219 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4220 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4221 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4222 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4223 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4224 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4225 } else { 4226 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4227 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4228 } 4229 4230 /* Set MAC address. */ 4231 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4232 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4233 4234 /* Set initial network type. */ 4235 reg = urtwn_read_4(sc, R92C_CR); 4236 switch (ic->ic_opmode) { 4237 case IEEE80211_M_STA: 4238 default: 4239 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4240 break; 4241 4242 case IEEE80211_M_IBSS: 4243 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4244 break; 4245 } 4246 urtwn_write_4(sc, R92C_CR, reg); 4247 4248 /* Set response rate */ 4249 reg = urtwn_read_4(sc, R92C_RRSR); 4250 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4251 urtwn_write_4(sc, R92C_RRSR, reg); 4252 4253 /* SIFS (used in NAV) */ 4254 urtwn_write_2(sc, R92C_SPEC_SIFS, 4255 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4256 4257 /* Set short/long retry limits. */ 4258 urtwn_write_2(sc, R92C_RL, 4259 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4260 4261 /* Initialize EDCA parameters. */ 4262 urtwn_edca_init(sc); 4263 4264 /* Setup rate fallback. */ 4265 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4266 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4267 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4268 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4269 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4270 } 4271 4272 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4273 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4274 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4275 /* Set ACK timeout. */ 4276 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4277 4278 /* Setup USB aggregation. */ 4279 /* Tx */ 4280 reg = urtwn_read_4(sc, R92C_TDECTRL); 4281 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4282 urtwn_write_4(sc, R92C_TDECTRL, reg); 4283 /* Rx */ 4284 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4285 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4286 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4287 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4288 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4289 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4290 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4291 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4292 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4293 else 4294 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4295 4296 /* Initialize beacon parameters. */ 4297 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4298 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4299 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4300 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4301 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4302 4303 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4304 /* Setup AMPDU aggregation. */ 4305 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4306 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4307 urtwn_write_2(sc, 0x4ca, 0x0708); 4308 4309 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4310 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4311 } 4312 4313 /* Load 8051 microcode. */ 4314 error = urtwn_load_firmware(sc); 4315 if (error != 0) 4316 goto fail; 4317 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4318 4319 /* Initialize MAC/BB/RF blocks. */ 4320 /* 4321 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4322 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4323 * XXX: This setting should be removed from rtl8192cu_mac[]. 4324 */ 4325 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4326 urtwn_rxfilter_init(sc); // reset R92C_RCR 4327 urtwn_bb_init(sc); 4328 urtwn_rf_init(sc); 4329 4330 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4331 urtwn_write_2(sc, R92C_CR, 4332 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4333 R92C_CR_MACRXEN); 4334 } 4335 4336 /* Turn CCK and OFDM blocks on. */ 4337 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4338 reg |= R92C_RFMOD_CCK_EN; 4339 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4340 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4341 reg |= R92C_RFMOD_OFDM_EN; 4342 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4343 4344 /* Clear per-station keys table. */ 4345 urtwn_cam_init(sc); 4346 4347 /* Enable hardware sequence numbering. */ 4348 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4349 4350 /* Perform LO and IQ calibrations. */ 4351 urtwn_iq_calib(sc, sc->iqk_inited); 4352 sc->iqk_inited = true; 4353 4354 /* Perform LC calibration. */ 4355 urtwn_lc_calib(sc); 4356 4357 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4358 /* Fix USB interference issue. */ 4359 urtwn_write_1(sc, 0xfe40, 0xe0); 4360 urtwn_write_1(sc, 0xfe41, 0x8d); 4361 urtwn_write_1(sc, 0xfe42, 0x80); 4362 urtwn_write_4(sc, 0x20c, 0xfd0320); 4363 4364 urtwn_pa_bias_init(sc); 4365 } 4366 4367 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 4368 /* 1T1R */ 4369 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4370 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4371 } 4372 4373 /* Initialize GPIO setting. */ 4374 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4375 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4376 4377 /* Fix for lower temperature. */ 4378 if (!ISSET(sc->chip, URTWN_CHIP_88E)) 4379 urtwn_write_1(sc, 0x15, 0xe9); 4380 4381 /* Set default channel. */ 4382 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4383 4384 /* Queue Rx xfers. */ 4385 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4386 data = &sc->rx_data[i]; 4387 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 4388 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4389 USBD_NO_TIMEOUT, urtwn_rxeof); 4390 error = usbd_transfer(data->xfer); 4391 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4392 error != USBD_IN_PROGRESS)) 4393 goto fail; 4394 } 4395 4396 /* We're ready to go. */ 4397 ifp->if_flags &= ~IFF_OACTIVE; 4398 ifp->if_flags |= IFF_RUNNING; 4399 4400 mutex_exit(&sc->sc_write_mtx); 4401 4402 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4403 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4404 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4405 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4406 urtwn_wait_async(sc); 4407 4408 return (0); 4409 4410 fail: 4411 mutex_exit(&sc->sc_write_mtx); 4412 4413 urtwn_stop(ifp, 1); 4414 return (error); 4415 } 4416 4417 static void 4418 urtwn_stop(struct ifnet *ifp, int disable) 4419 { 4420 struct urtwn_softc *sc = ifp->if_softc; 4421 struct ieee80211com *ic = &sc->sc_ic; 4422 size_t i; 4423 int s; 4424 4425 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4426 4427 s = splusb(); 4428 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4429 urtwn_wait_async(sc); 4430 splx(s); 4431 4432 sc->tx_timer = 0; 4433 ifp->if_timer = 0; 4434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4435 4436 callout_stop(&sc->sc_scan_to); 4437 callout_stop(&sc->sc_calib_to); 4438 4439 /* Abort Tx. */ 4440 for (i = 0; i < R92C_MAX_EPOUT; i++) { 4441 if (sc->tx_pipe[i] != NULL) 4442 usbd_abort_pipe(sc->tx_pipe[i]); 4443 } 4444 4445 /* Stop Rx pipe. */ 4446 usbd_abort_pipe(sc->rx_pipe); 4447 4448 /* Free Tx/Rx buffers. */ 4449 urtwn_free_tx_list(sc); 4450 urtwn_free_rx_list(sc); 4451 4452 if (disable) 4453 urtwn_chip_stop(sc); 4454 } 4455 4456 static int 4457 urtwn_reset(struct ifnet *ifp) 4458 { 4459 struct urtwn_softc *sc = ifp->if_softc; 4460 struct ieee80211com *ic = &sc->sc_ic; 4461 4462 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4463 return ENETRESET; 4464 4465 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4466 4467 return 0; 4468 } 4469 4470 static void 4471 urtwn_chip_stop(struct urtwn_softc *sc) 4472 { 4473 uint32_t reg; 4474 bool disabled = true; 4475 4476 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4477 4478 mutex_enter(&sc->sc_write_mtx); 4479 4480 /* 4481 * RF Off Sequence 4482 */ 4483 /* Pause MAC TX queue */ 4484 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4485 4486 /* Disable RF */ 4487 urtwn_rf_write(sc, 0, 0, 0); 4488 4489 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4490 4491 /* Reset BB state machine */ 4492 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4493 R92C_SYS_FUNC_EN_USBD | 4494 R92C_SYS_FUNC_EN_USBA | 4495 R92C_SYS_FUNC_EN_BB_GLB_RST); 4496 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4497 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4498 4499 /* 4500 * Reset digital sequence 4501 */ 4502 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4503 /* Reset MCU ready status */ 4504 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4505 /* If firmware in ram code, do reset */ 4506 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4507 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4508 urtwn_r88e_fw_reset(sc); 4509 else 4510 urtwn_fw_reset(sc); 4511 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 4512 } 4513 } 4514 4515 /* Reset MAC and Enable 8051 */ 4516 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 4517 4518 /* Reset MCU ready status */ 4519 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4520 4521 if (disabled) { 4522 /* Disable MAC clock */ 4523 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4524 /* Disable AFE PLL */ 4525 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 4526 /* Gated AFE DIG_CLOCK */ 4527 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 4528 /* Isolated digital to PON */ 4529 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 4530 } 4531 4532 /* 4533 * Pull GPIO PIN to balance level and LED control 4534 */ 4535 /* 1. Disable GPIO[7:0] */ 4536 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 4537 4538 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 4539 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 4540 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 4541 4542 /* Disable GPIO[10:8] */ 4543 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 4544 4545 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 4546 reg |= (((reg & 0x000f) << 4) | 0x0780); 4547 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 4548 4549 /* Disable LED0 & 1 */ 4550 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 4551 4552 /* 4553 * Reset digital sequence 4554 */ 4555 if (disabled) { 4556 /* Disable ELDR clock */ 4557 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4558 /* Isolated ELDR to PON */ 4559 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 4560 } 4561 4562 /* 4563 * Disable analog sequence 4564 */ 4565 if (disabled) { 4566 /* Disable A15 power */ 4567 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 4568 /* Disable digital core power */ 4569 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 4570 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 4571 ~R92C_LDOV12D_CTRL_LDV12_EN); 4572 } 4573 4574 /* Enter PFM mode */ 4575 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 4576 4577 /* Set USB suspend */ 4578 urtwn_write_2(sc, R92C_APS_FSMCO, 4579 R92C_APS_FSMCO_APDM_HOST | 4580 R92C_APS_FSMCO_AFSM_HSUS | 4581 R92C_APS_FSMCO_PFM_ALDN); 4582 4583 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 4584 4585 mutex_exit(&sc->sc_write_mtx); 4586 } 4587 4588 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 4589 4590 #ifdef _MODULE 4591 #include "ioconf.c" 4592 #endif 4593 4594 static int 4595 if_urtwn_modcmd(modcmd_t cmd, void *aux) 4596 { 4597 int error = 0; 4598 4599 switch (cmd) { 4600 case MODULE_CMD_INIT: 4601 #ifdef _MODULE 4602 error = config_init_component(cfdriver_ioconf_urtwn, 4603 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4604 #endif 4605 return (error); 4606 case MODULE_CMD_FINI: 4607 #ifdef _MODULE 4608 error = config_fini_component(cfdriver_ioconf_urtwn, 4609 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4610 #endif 4611 return (error); 4612 default: 4613 return (ENOTTY); 4614 } 4615 } 4616
Indexes created Tue Sep 30 06:09:59 GMT 2025