if_urtwn.c revision 1.34.4.10
1 /* $NetBSD: if_urtwn.c,v 1.34.4.10 2015/12/27 12:09:59 skrll Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /*- 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.34.4.10 2015/12/27 12:09:59 skrll Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_inet.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 /* 78 * The sc_write_mtx locking is to prevent sequences of writes from 79 * being intermingled with each other. I don't know if this is really 80 * needed. I have added it just to be on the safe side. 81 */ 82 83 #ifdef URTWN_DEBUG 84 #define DBG_INIT __BIT(0) 85 #define DBG_FN __BIT(1) 86 #define DBG_TX __BIT(2) 87 #define DBG_RX __BIT(3) 88 #define DBG_STM __BIT(4) 89 #define DBG_RF __BIT(5) 90 #define DBG_REG __BIT(6) 91 #define DBG_ALL 0xffffffffU 92 u_int urtwn_debug = 0; 93 #define DPRINTFN(n, s) \ 94 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 95 #else 96 #define DPRINTFN(n, s) 97 #endif 98 99 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 100 #define URTWN_RTL8188E_DEV(v,p) \ 101 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 102 static const struct urtwn_dev { 103 struct usb_devno dev; 104 uint32_t flags; 105 #define FLAG_RTL8188E __BIT(0) 106 } urtwn_devs[] = { 107 URTWN_DEV(ABOCOM, RTL8188CU_1), 108 URTWN_DEV(ABOCOM, RTL8188CU_2), 109 URTWN_DEV(ABOCOM, RTL8192CU), 110 URTWN_DEV(ASUSTEK, RTL8192CU), 111 URTWN_DEV(ASUSTEK, RTL8192CU_3), 112 URTWN_DEV(ASUSTEK, USBN10NANO), 113 URTWN_DEV(ASUSTEK, RTL8192CU_3), 114 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 115 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 116 URTWN_DEV(AZUREWAVE, RTL8188CU), 117 URTWN_DEV(BELKIN, F7D2102), 118 URTWN_DEV(BELKIN, RTL8188CU), 119 URTWN_DEV(BELKIN, RTL8188CUS), 120 URTWN_DEV(BELKIN, RTL8192CU), 121 URTWN_DEV(BELKIN, RTL8192CU_1), 122 URTWN_DEV(BELKIN, RTL8192CU_2), 123 URTWN_DEV(CHICONY, RTL8188CUS_1), 124 URTWN_DEV(CHICONY, RTL8188CUS_2), 125 URTWN_DEV(CHICONY, RTL8188CUS_3), 126 URTWN_DEV(CHICONY, RTL8188CUS_4), 127 URTWN_DEV(CHICONY, RTL8188CUS_5), 128 URTWN_DEV(CHICONY, RTL8188CUS_6), 129 URTWN_DEV(COMPARE, RTL8192CU), 130 URTWN_DEV(COREGA, RTL8192CU), 131 URTWN_DEV(DLINK, DWA131B), 132 URTWN_DEV(DLINK, RTL8188CU), 133 URTWN_DEV(DLINK, RTL8192CU_1), 134 URTWN_DEV(DLINK, RTL8192CU_2), 135 URTWN_DEV(DLINK, RTL8192CU_3), 136 URTWN_DEV(DLINK, RTL8192CU_4), 137 URTWN_DEV(EDIMAX, RTL8188CU), 138 URTWN_DEV(EDIMAX, RTL8192CU), 139 URTWN_DEV(FEIXUN, RTL8188CU), 140 URTWN_DEV(FEIXUN, RTL8192CU), 141 URTWN_DEV(GUILLEMOT, HWNUP150), 142 URTWN_DEV(GUILLEMOT, RTL8192CU), 143 URTWN_DEV(HAWKING, RTL8192CU), 144 URTWN_DEV(HAWKING, RTL8192CU_2), 145 URTWN_DEV(HP3, RTL8188CU), 146 URTWN_DEV(IODATA, WNG150UM), 147 URTWN_DEV(IODATA, RTL8192CU), 148 URTWN_DEV(NETGEAR, WNA1000M), 149 URTWN_DEV(NETGEAR, RTL8192CU), 150 URTWN_DEV(NETGEAR4, RTL8188CU), 151 URTWN_DEV(NOVATECH, RTL8188CU), 152 URTWN_DEV(PLANEX2, RTL8188CU_1), 153 URTWN_DEV(PLANEX2, RTL8188CU_2), 154 URTWN_DEV(PLANEX2, RTL8192CU), 155 URTWN_DEV(PLANEX2, RTL8188CU_3), 156 URTWN_DEV(PLANEX2, RTL8188CU_4), 157 URTWN_DEV(PLANEX2, RTL8188CUS), 158 URTWN_DEV(REALTEK, RTL8188CE_0), 159 URTWN_DEV(REALTEK, RTL8188CE_1), 160 URTWN_DEV(REALTEK, RTL8188CTV), 161 URTWN_DEV(REALTEK, RTL8188CU_0), 162 URTWN_DEV(REALTEK, RTL8188CU_1), 163 URTWN_DEV(REALTEK, RTL8188CU_2), 164 URTWN_DEV(REALTEK, RTL8188CU_3), 165 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 166 URTWN_DEV(REALTEK, RTL8188CUS), 167 URTWN_DEV(REALTEK, RTL8188RU), 168 URTWN_DEV(REALTEK, RTL8188RU_2), 169 URTWN_DEV(REALTEK, RTL8188RU_3), 170 URTWN_DEV(REALTEK, RTL8191CU), 171 URTWN_DEV(REALTEK, RTL8192CE), 172 URTWN_DEV(REALTEK, RTL8192CU), 173 URTWN_DEV(SITECOMEU, RTL8188CU), 174 URTWN_DEV(SITECOMEU, RTL8188CU_2), 175 URTWN_DEV(SITECOMEU, RTL8192CU), 176 URTWN_DEV(SITECOMEU, RTL8192CUR2), 177 URTWN_DEV(TPLINK, RTL8192CU), 178 URTWN_DEV(TRENDNET, RTL8188CU), 179 URTWN_DEV(TRENDNET, RTL8192CU), 180 URTWN_DEV(ZYXEL, RTL8192CU), 181 182 /* URTWN_RTL8188E */ 183 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 184 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 185 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 186 }; 187 #undef URTWN_DEV 188 #undef URTWN_RTL8188E_DEV 189 190 static int urtwn_match(device_t, cfdata_t, void *); 191 static void urtwn_attach(device_t, device_t, void *); 192 static int urtwn_detach(device_t, int); 193 static int urtwn_activate(device_t, enum devact); 194 195 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 196 urtwn_attach, urtwn_detach, urtwn_activate); 197 198 static int urtwn_open_pipes(struct urtwn_softc *); 199 static void urtwn_close_pipes(struct urtwn_softc *); 200 static int urtwn_alloc_rx_list(struct urtwn_softc *); 201 static void urtwn_free_rx_list(struct urtwn_softc *); 202 static int urtwn_alloc_tx_list(struct urtwn_softc *); 203 static void urtwn_free_tx_list(struct urtwn_softc *); 204 static void urtwn_task(void *); 205 static void urtwn_do_async(struct urtwn_softc *, 206 void (*)(struct urtwn_softc *, void *), void *, int); 207 static void urtwn_wait_async(struct urtwn_softc *); 208 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 209 int); 210 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 211 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 212 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 213 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 214 int); 215 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 216 int); 217 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 218 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 219 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 220 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 221 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 222 uint32_t); 223 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 224 uint32_t); 225 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 226 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 227 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 228 static void urtwn_efuse_read(struct urtwn_softc *); 229 static void urtwn_efuse_switch_power(struct urtwn_softc *); 230 static int urtwn_read_chipid(struct urtwn_softc *); 231 #ifdef URTWN_DEBUG 232 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 233 #endif 234 static void urtwn_read_rom(struct urtwn_softc *); 235 static void urtwn_r88e_read_rom(struct urtwn_softc *); 236 static int urtwn_media_change(struct ifnet *); 237 static int urtwn_ra_init(struct urtwn_softc *); 238 static int urtwn_get_nettype(struct urtwn_softc *); 239 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 240 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 241 static void urtwn_set_led(struct urtwn_softc *, int, int); 242 static void urtwn_calib_to(void *); 243 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 244 static void urtwn_next_scan(void *); 245 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 246 int); 247 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 248 static int urtwn_wme_update(struct ieee80211com *); 249 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 250 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 251 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 252 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 253 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 254 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 255 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 256 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 257 struct ieee80211_node *, struct urtwn_tx_data *); 258 static struct urtwn_tx_data * 259 urtwn_get_tx_data(struct urtwn_softc *, size_t); 260 static void urtwn_start(struct ifnet *); 261 static void urtwn_watchdog(struct ifnet *); 262 static int urtwn_ioctl(struct ifnet *, u_long, void *); 263 static int urtwn_r92c_power_on(struct urtwn_softc *); 264 static int urtwn_r88e_power_on(struct urtwn_softc *); 265 static int urtwn_llt_init(struct urtwn_softc *); 266 static void urtwn_fw_reset(struct urtwn_softc *); 267 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 268 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 269 static int urtwn_load_firmware(struct urtwn_softc *); 270 static int urtwn_r92c_dma_init(struct urtwn_softc *); 271 static int urtwn_r88e_dma_init(struct urtwn_softc *); 272 static void urtwn_mac_init(struct urtwn_softc *); 273 static void urtwn_bb_init(struct urtwn_softc *); 274 static void urtwn_rf_init(struct urtwn_softc *); 275 static void urtwn_cam_init(struct urtwn_softc *); 276 static void urtwn_pa_bias_init(struct urtwn_softc *); 277 static void urtwn_rxfilter_init(struct urtwn_softc *); 278 static void urtwn_edca_init(struct urtwn_softc *); 279 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 280 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 281 uint16_t[]); 282 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 283 u_int, uint16_t[]); 284 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 285 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 286 u_int); 287 static void urtwn_iq_calib(struct urtwn_softc *, bool); 288 static void urtwn_lc_calib(struct urtwn_softc *); 289 static void urtwn_temp_calib(struct urtwn_softc *); 290 static int urtwn_init(struct ifnet *); 291 static void urtwn_stop(struct ifnet *, int); 292 static int urtwn_reset(struct ifnet *); 293 static void urtwn_chip_stop(struct urtwn_softc *); 294 static void urtwn_newassoc(struct ieee80211_node *, int); 295 296 /* Aliases. */ 297 #define urtwn_bb_write urtwn_write_4 298 #define urtwn_bb_read urtwn_read_4 299 300 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 301 302 static int 303 urtwn_match(device_t parent, cfdata_t match, void *aux) 304 { 305 struct usb_attach_arg *uaa = aux; 306 307 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 308 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 309 } 310 311 static void 312 urtwn_attach(device_t parent, device_t self, void *aux) 313 { 314 struct urtwn_softc *sc = device_private(self); 315 struct ieee80211com *ic = &sc->sc_ic; 316 struct ifnet *ifp = &sc->sc_if; 317 struct usb_attach_arg *uaa = aux; 318 char *devinfop; 319 const struct urtwn_dev *dev; 320 size_t i; 321 int error; 322 323 sc->sc_dev = self; 324 sc->sc_udev = uaa->uaa_device; 325 326 sc->chip = 0; 327 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 328 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 329 SET(sc->chip, URTWN_CHIP_88E); 330 331 aprint_naive("\n"); 332 aprint_normal("\n"); 333 334 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 335 336 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 337 aprint_normal_dev(self, "%s\n", devinfop); 338 usbd_devinfo_free(devinfop); 339 340 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 341 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 342 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 343 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 344 345 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 346 347 callout_init(&sc->sc_scan_to, 0); 348 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 349 callout_init(&sc->sc_calib_to, 0); 350 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 351 352 error = usbd_set_config_no(sc->sc_udev, 1, 0); 353 if (error != 0) { 354 aprint_error_dev(self, "failed to set configuration" 355 ", err=%s\n", usbd_errstr(error)); 356 goto fail; 357 } 358 359 /* Get the first interface handle. */ 360 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 361 if (error != 0) { 362 aprint_error_dev(self, "could not get interface handle\n"); 363 goto fail; 364 } 365 366 error = urtwn_read_chipid(sc); 367 if (error != 0) { 368 aprint_error_dev(self, "unsupported test chip\n"); 369 goto fail; 370 } 371 372 /* Determine number of Tx/Rx chains. */ 373 if (sc->chip & URTWN_CHIP_92C) { 374 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 375 sc->nrxchains = 2; 376 } else { 377 sc->ntxchains = 1; 378 sc->nrxchains = 1; 379 } 380 381 if (ISSET(sc->chip, URTWN_CHIP_88E)) 382 urtwn_r88e_read_rom(sc); 383 else 384 urtwn_read_rom(sc); 385 386 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 387 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 388 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 389 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 390 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 391 "8188CUS", sc->ntxchains, sc->nrxchains, 392 ether_sprintf(ic->ic_myaddr)); 393 394 error = urtwn_open_pipes(sc); 395 if (error != 0) { 396 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 397 goto fail; 398 } 399 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 400 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 401 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 402 403 /* 404 * Setup the 802.11 device. 405 */ 406 ic->ic_ifp = ifp; 407 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 408 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 409 ic->ic_state = IEEE80211_S_INIT; 410 411 /* Set device capabilities. */ 412 ic->ic_caps = 413 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 414 IEEE80211_C_IBSS | /* IBSS mode supported */ 415 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 416 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 417 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 418 IEEE80211_C_WME | /* 802.11e */ 419 IEEE80211_C_WPA; /* 802.11i */ 420 421 /* Set supported .11b and .11g rates. */ 422 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 423 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 424 425 /* Set supported .11b and .11g channels (1 through 14). */ 426 for (i = 1; i <= 14; i++) { 427 ic->ic_channels[i].ic_freq = 428 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 429 ic->ic_channels[i].ic_flags = 430 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 431 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 432 } 433 434 ifp->if_softc = sc; 435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 436 ifp->if_init = urtwn_init; 437 ifp->if_ioctl = urtwn_ioctl; 438 ifp->if_start = urtwn_start; 439 ifp->if_watchdog = urtwn_watchdog; 440 IFQ_SET_READY(&ifp->if_snd); 441 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 442 443 if_attach(ifp); 444 ieee80211_ifattach(ic); 445 446 /* override default methods */ 447 ic->ic_newassoc = urtwn_newassoc; 448 ic->ic_reset = urtwn_reset; 449 ic->ic_wme.wme_update = urtwn_wme_update; 450 451 /* Override state transition machine. */ 452 sc->sc_newstate = ic->ic_newstate; 453 ic->ic_newstate = urtwn_newstate; 454 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 455 456 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 457 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 458 &sc->sc_drvbpf); 459 460 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 461 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 462 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 463 464 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 465 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 466 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 467 468 ieee80211_announce(ic); 469 470 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 471 472 if (!pmf_device_register(self, NULL, NULL)) 473 aprint_error_dev(self, "couldn't establish power handler\n"); 474 475 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 476 return; 477 478 fail: 479 sc->sc_dying = 1; 480 aprint_error_dev(self, "attach failed\n"); 481 } 482 483 static int 484 urtwn_detach(device_t self, int flags) 485 { 486 struct urtwn_softc *sc = device_private(self); 487 struct ifnet *ifp = &sc->sc_if; 488 int s; 489 490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 491 492 pmf_device_deregister(self); 493 494 s = splusb(); 495 496 sc->sc_dying = 1; 497 498 callout_stop(&sc->sc_scan_to); 499 callout_stop(&sc->sc_calib_to); 500 501 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 502 usb_rem_task(sc->sc_udev, &sc->sc_task); 503 urtwn_stop(ifp, 0); 504 505 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 506 bpf_detach(ifp); 507 ieee80211_ifdetach(&sc->sc_ic); 508 if_detach(ifp); 509 510 /* Abort and close Tx/Rx pipes. */ 511 urtwn_close_pipes(sc); 512 } 513 514 splx(s); 515 516 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 517 518 callout_destroy(&sc->sc_scan_to); 519 callout_destroy(&sc->sc_calib_to); 520 521 mutex_destroy(&sc->sc_write_mtx); 522 mutex_destroy(&sc->sc_fwcmd_mtx); 523 mutex_destroy(&sc->sc_tx_mtx); 524 mutex_destroy(&sc->sc_task_mtx); 525 526 return 0; 527 } 528 529 static int 530 urtwn_activate(device_t self, enum devact act) 531 { 532 struct urtwn_softc *sc = device_private(self); 533 534 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 535 536 switch (act) { 537 case DVACT_DEACTIVATE: 538 if_deactivate(sc->sc_ic.ic_ifp); 539 return 0; 540 default: 541 return EOPNOTSUPP; 542 } 543 } 544 545 static int 546 urtwn_open_pipes(struct urtwn_softc *sc) 547 { 548 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 549 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 size_t i, ntx = 0; 553 int error; 554 555 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 556 557 /* Determine the number of bulk-out pipes. */ 558 id = usbd_get_interface_descriptor(sc->sc_iface); 559 for (i = 0; i < id->bNumEndpoints; i++) { 560 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 561 if (ed != NULL && 562 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 563 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 564 ntx++; 565 } 566 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 567 device_xname(sc->sc_dev), __func__, ntx)); 568 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 569 aprint_error_dev(sc->sc_dev, 570 "%zd: invalid number of Tx bulk pipes\n", ntx); 571 return EIO; 572 } 573 sc->rx_npipe = 1; 574 sc->tx_npipe = ntx; 575 576 /* Open bulk-in pipe at address 0x81. */ 577 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 578 &sc->rx_pipe); 579 if (error != 0) { 580 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 581 ": %d\n", error); 582 goto fail; 583 } 584 585 /* Open bulk-out pipes (up to 3). */ 586 for (i = 0; i < ntx; i++) { 587 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 588 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 589 if (error != 0) { 590 aprint_error_dev(sc->sc_dev, 591 "could not open Tx bulk pipe 0x%02x: %d\n", 592 epaddr[i], error); 593 goto fail; 594 } 595 } 596 597 /* Map 802.11 access categories to USB pipes. */ 598 sc->ac2idx[WME_AC_BK] = 599 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 600 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 601 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 602 603 fail: 604 if (error != 0) 605 urtwn_close_pipes(sc); 606 return error; 607 } 608 609 static void 610 urtwn_close_pipes(struct urtwn_softc *sc) 611 { 612 struct usbd_pipe *pipe; 613 size_t i; 614 615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 616 617 /* Close Rx pipe. */ 618 CTASSERT(sizeof(pipe) == sizeof(void *)); 619 pipe = atomic_swap_ptr(&sc->rx_pipe, NULL); 620 if (pipe != NULL) { 621 usbd_abort_pipe(pipe); 622 usbd_close_pipe(pipe); 623 } 624 /* Close Tx pipes. */ 625 for (i = 0; i < R92C_MAX_EPOUT; i++) { 626 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 627 if (pipe != NULL) { 628 usbd_abort_pipe(pipe); 629 usbd_close_pipe(pipe); 630 } 631 } 632 } 633 634 static int 635 urtwn_alloc_rx_list(struct urtwn_softc *sc) 636 { 637 struct urtwn_rx_data *data; 638 size_t i; 639 int error = 0; 640 641 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 642 643 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 644 data = &sc->rx_data[i]; 645 646 data->sc = sc; /* Backpointer for callbacks. */ 647 648 error = usbd_create_xfer(sc->rx_pipe, URTWN_RXBUFSZ, 649 USBD_SHORT_XFER_OK, 0, &data->xfer); 650 if (error) { 651 aprint_error_dev(sc->sc_dev, 652 "could not allocate xfer\n"); 653 break; 654 } 655 656 data->buf = usbd_get_buffer(data->xfer); 657 } 658 if (error != 0) 659 urtwn_free_rx_list(sc); 660 return error; 661 } 662 663 static void 664 urtwn_free_rx_list(struct urtwn_softc *sc) 665 { 666 struct usbd_xfer *xfer; 667 size_t i; 668 669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 670 671 /* NB: Caller must abort pipe first. */ 672 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 673 CTASSERT(sizeof(xfer) == sizeof(void *)); 674 xfer = atomic_swap_ptr(&sc->rx_data[i].xfer, NULL); 675 if (xfer != NULL) 676 usbd_destroy_xfer(xfer); 677 } 678 } 679 680 static int 681 urtwn_alloc_tx_list(struct urtwn_softc *sc) 682 { 683 struct urtwn_tx_data *data; 684 size_t i; 685 int error = 0; 686 687 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 688 689 mutex_enter(&sc->sc_tx_mtx); 690 for (size_t j = 0; j < sc->tx_npipe; j++) { 691 TAILQ_INIT(&sc->tx_free_list[j]); 692 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 693 data = &sc->tx_data[j][i]; 694 695 data->sc = sc; /* Backpointer for callbacks. */ 696 data->pidx = j; 697 698 error = usbd_create_xfer(sc->tx_pipe[j], 699 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 700 &data->xfer); 701 if (error) { 702 aprint_error_dev(sc->sc_dev, 703 "could not allocate xfer\n"); 704 goto fail; 705 } 706 707 data->buf = usbd_get_buffer(data->xfer); 708 709 /* Append this Tx buffer to our free list. */ 710 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 711 } 712 } 713 mutex_exit(&sc->sc_tx_mtx); 714 return 0; 715 716 fail: 717 urtwn_free_tx_list(sc); 718 mutex_exit(&sc->sc_tx_mtx); 719 return error; 720 } 721 722 static void 723 urtwn_free_tx_list(struct urtwn_softc *sc) 724 { 725 struct usbd_xfer *xfer; 726 size_t i; 727 728 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 729 730 /* NB: Caller must abort pipe first. */ 731 for (size_t j = 0; j < sc->tx_npipe; j++) { 732 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 733 CTASSERT(sizeof(xfer) == sizeof(void *)); 734 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 735 if (xfer != NULL) 736 usbd_destroy_xfer(xfer); 737 } 738 } 739 } 740 741 static void 742 urtwn_task(void *arg) 743 { 744 struct urtwn_softc *sc = arg; 745 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 746 struct urtwn_host_cmd *cmd; 747 int s; 748 749 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 750 751 /* Process host commands. */ 752 s = splusb(); 753 mutex_spin_enter(&sc->sc_task_mtx); 754 while (ring->next != ring->cur) { 755 cmd = &ring->cmd[ring->next]; 756 mutex_spin_exit(&sc->sc_task_mtx); 757 splx(s); 758 /* Invoke callback with kernel lock held. */ 759 cmd->cb(sc, cmd->data); 760 s = splusb(); 761 mutex_spin_enter(&sc->sc_task_mtx); 762 ring->queued--; 763 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 764 } 765 mutex_spin_exit(&sc->sc_task_mtx); 766 wakeup(&sc->cmdq); 767 splx(s); 768 } 769 770 static void 771 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 772 void *arg, int len) 773 { 774 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 775 struct urtwn_host_cmd *cmd; 776 int s; 777 778 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 779 device_xname(sc->sc_dev), __func__, cb, arg, len)); 780 781 s = splusb(); 782 mutex_spin_enter(&sc->sc_task_mtx); 783 cmd = &ring->cmd[ring->cur]; 784 cmd->cb = cb; 785 KASSERT(len <= sizeof(cmd->data)); 786 memcpy(cmd->data, arg, len); 787 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 788 789 /* If there is no pending command already, schedule a task. */ 790 if (!sc->sc_dying && ++ring->queued == 1) { 791 mutex_spin_exit(&sc->sc_task_mtx); 792 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 793 } else 794 mutex_spin_exit(&sc->sc_task_mtx); 795 splx(s); 796 } 797 798 static void 799 urtwn_wait_async(struct urtwn_softc *sc) 800 { 801 802 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 803 804 /* Wait for all queued asynchronous commands to complete. */ 805 while (sc->cmdq.queued > 0) 806 tsleep(&sc->cmdq, 0, "endtask", 0); 807 } 808 809 static int 810 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 811 int len) 812 { 813 usb_device_request_t req; 814 usbd_status error; 815 816 KASSERT(mutex_owned(&sc->sc_write_mtx)); 817 818 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 819 req.bRequest = R92C_REQ_REGS; 820 USETW(req.wValue, addr); 821 USETW(req.wIndex, 0); 822 USETW(req.wLength, len); 823 error = usbd_do_request(sc->sc_udev, &req, buf); 824 if (error != USBD_NORMAL_COMPLETION) { 825 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 826 device_xname(sc->sc_dev), __func__, error, addr, len)); 827 } 828 return error; 829 } 830 831 static void 832 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 833 { 834 835 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 836 device_xname(sc->sc_dev), __func__, addr, val)); 837 838 urtwn_write_region_1(sc, addr, &val, 1); 839 } 840 841 static void 842 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 843 { 844 uint8_t buf[2]; 845 846 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 847 device_xname(sc->sc_dev), __func__, addr, val)); 848 849 buf[0] = (uint8_t)val; 850 buf[1] = (uint8_t)(val >> 8); 851 urtwn_write_region_1(sc, addr, buf, 2); 852 } 853 854 static void 855 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 856 { 857 uint8_t buf[4]; 858 859 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 860 device_xname(sc->sc_dev), __func__, addr, val)); 861 862 buf[0] = (uint8_t)val; 863 buf[1] = (uint8_t)(val >> 8); 864 buf[2] = (uint8_t)(val >> 16); 865 buf[3] = (uint8_t)(val >> 24); 866 urtwn_write_region_1(sc, addr, buf, 4); 867 } 868 869 static int 870 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 871 { 872 873 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 874 device_xname(sc->sc_dev), __func__, addr, len)); 875 876 return urtwn_write_region_1(sc, addr, buf, len); 877 } 878 879 static int 880 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 881 int len) 882 { 883 usb_device_request_t req; 884 usbd_status error; 885 886 req.bmRequestType = UT_READ_VENDOR_DEVICE; 887 req.bRequest = R92C_REQ_REGS; 888 USETW(req.wValue, addr); 889 USETW(req.wIndex, 0); 890 USETW(req.wLength, len); 891 error = usbd_do_request(sc->sc_udev, &req, buf); 892 if (error != USBD_NORMAL_COMPLETION) { 893 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 894 device_xname(sc->sc_dev), __func__, error, addr, len)); 895 } 896 return error; 897 } 898 899 static uint8_t 900 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 901 { 902 uint8_t val; 903 904 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 905 return 0xff; 906 907 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 908 device_xname(sc->sc_dev), __func__, addr, val)); 909 return val; 910 } 911 912 static uint16_t 913 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 914 { 915 uint8_t buf[2]; 916 uint16_t val; 917 918 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 919 return 0xffff; 920 921 val = LE_READ_2(&buf[0]); 922 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 923 device_xname(sc->sc_dev), __func__, addr, val)); 924 return val; 925 } 926 927 static uint32_t 928 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 929 { 930 uint8_t buf[4]; 931 uint32_t val; 932 933 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 934 return 0xffffffff; 935 936 val = LE_READ_4(&buf[0]); 937 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 938 device_xname(sc->sc_dev), __func__, addr, val)); 939 return val; 940 } 941 942 static int 943 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 944 { 945 struct r92c_fw_cmd cmd; 946 uint8_t *cp; 947 int fwcur; 948 int ntries; 949 950 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 951 device_xname(sc->sc_dev), __func__, id, buf, len)); 952 953 KASSERT(mutex_owned(&sc->sc_write_mtx)); 954 955 mutex_enter(&sc->sc_fwcmd_mtx); 956 fwcur = sc->fwcur; 957 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 958 mutex_exit(&sc->sc_fwcmd_mtx); 959 960 /* Wait for current FW box to be empty. */ 961 for (ntries = 0; ntries < 100; ntries++) { 962 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 963 break; 964 DELAY(1); 965 } 966 if (ntries == 100) { 967 aprint_error_dev(sc->sc_dev, 968 "could not send firmware command %d\n", id); 969 return ETIMEDOUT; 970 } 971 972 memset(&cmd, 0, sizeof(cmd)); 973 KASSERT(len <= sizeof(cmd.msg)); 974 memcpy(cmd.msg, buf, len); 975 976 /* Write the first word last since that will trigger the FW. */ 977 cp = (uint8_t *)&cmd; 978 if (len >= 4) { 979 cmd.id = id | R92C_CMD_FLAG_EXT; 980 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 981 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 982 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 983 } else { 984 cmd.id = id; 985 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 986 } 987 988 return 0; 989 } 990 991 static __inline void 992 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 993 { 994 995 sc->sc_rf_write(sc, chain, addr, val); 996 } 997 998 static void 999 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1000 uint32_t val) 1001 { 1002 1003 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1004 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1005 } 1006 1007 static void 1008 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1009 uint32_t val) 1010 { 1011 1012 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1013 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1014 } 1015 1016 static uint32_t 1017 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1018 { 1019 uint32_t reg[R92C_MAX_CHAINS], val; 1020 1021 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1022 if (chain != 0) { 1023 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1024 } 1025 1026 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1027 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1028 DELAY(1000); 1029 1030 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1031 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1032 R92C_HSSI_PARAM2_READ_EDGE); 1033 DELAY(1000); 1034 1035 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1036 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1037 DELAY(1000); 1038 1039 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1040 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1041 } else { 1042 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1043 } 1044 return MS(val, R92C_LSSI_READBACK_DATA); 1045 } 1046 1047 static int 1048 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1049 { 1050 int ntries; 1051 1052 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1053 1054 urtwn_write_4(sc, R92C_LLT_INIT, 1055 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1056 SM(R92C_LLT_INIT_ADDR, addr) | 1057 SM(R92C_LLT_INIT_DATA, data)); 1058 /* Wait for write operation to complete. */ 1059 for (ntries = 0; ntries < 20; ntries++) { 1060 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1061 R92C_LLT_INIT_OP_NO_ACTIVE) { 1062 /* Done */ 1063 return 0; 1064 } 1065 DELAY(5); 1066 } 1067 return ETIMEDOUT; 1068 } 1069 1070 static uint8_t 1071 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1072 { 1073 uint32_t reg; 1074 int ntries; 1075 1076 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1077 1078 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1079 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1080 reg &= ~R92C_EFUSE_CTRL_VALID; 1081 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1082 1083 /* Wait for read operation to complete. */ 1084 for (ntries = 0; ntries < 100; ntries++) { 1085 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1086 if (reg & R92C_EFUSE_CTRL_VALID) { 1087 /* Done */ 1088 return MS(reg, R92C_EFUSE_CTRL_DATA); 1089 } 1090 DELAY(5); 1091 } 1092 aprint_error_dev(sc->sc_dev, 1093 "could not read efuse byte at address 0x%04x\n", addr); 1094 return 0xff; 1095 } 1096 1097 static void 1098 urtwn_efuse_read(struct urtwn_softc *sc) 1099 { 1100 uint8_t *rom = (uint8_t *)&sc->rom; 1101 uint32_t reg; 1102 uint16_t addr = 0; 1103 uint8_t off, msk; 1104 size_t i; 1105 1106 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1107 1108 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1109 1110 urtwn_efuse_switch_power(sc); 1111 1112 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1113 while (addr < 512) { 1114 reg = urtwn_efuse_read_1(sc, addr); 1115 if (reg == 0xff) 1116 break; 1117 addr++; 1118 off = reg >> 4; 1119 msk = reg & 0xf; 1120 for (i = 0; i < 4; i++) { 1121 if (msk & (1U << i)) 1122 continue; 1123 1124 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1125 addr++; 1126 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1127 addr++; 1128 } 1129 } 1130 #ifdef URTWN_DEBUG 1131 if (urtwn_debug & DBG_INIT) { 1132 /* Dump ROM content. */ 1133 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1134 for (i = 0; i < (int)sizeof(sc->rom); i++) 1135 printf(":%02x", rom[i]); 1136 printf("\n"); 1137 } 1138 #endif 1139 } 1140 1141 static void 1142 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1143 { 1144 uint32_t reg; 1145 1146 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1147 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1148 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1149 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1150 } 1151 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1152 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1153 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1154 reg | R92C_SYS_FUNC_EN_ELDR); 1155 } 1156 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1157 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1158 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1159 urtwn_write_2(sc, R92C_SYS_CLKR, 1160 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1161 } 1162 } 1163 1164 static int 1165 urtwn_read_chipid(struct urtwn_softc *sc) 1166 { 1167 uint32_t reg; 1168 1169 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1170 1171 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1172 return 0; 1173 1174 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1175 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1176 /* test chip, not supported */ 1177 return EIO; 1178 } 1179 if (reg & R92C_SYS_CFG_TYPE_92C) { 1180 sc->chip |= URTWN_CHIP_92C; 1181 /* Check if it is a castrated 8192C. */ 1182 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1183 R92C_HPON_FSM_CHIP_BONDING_ID) == 1184 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1185 sc->chip |= URTWN_CHIP_92C_1T2R; 1186 } 1187 } 1188 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1189 sc->chip |= URTWN_CHIP_UMC; 1190 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1191 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1192 } 1193 } 1194 return 0; 1195 } 1196 1197 #ifdef URTWN_DEBUG 1198 static void 1199 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1200 { 1201 1202 aprint_normal_dev(sc->sc_dev, 1203 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1204 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1205 1206 aprint_normal_dev(sc->sc_dev, 1207 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1208 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1209 1210 aprint_normal_dev(sc->sc_dev, 1211 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1212 rp->macaddr[0], rp->macaddr[1], 1213 rp->macaddr[2], rp->macaddr[3], 1214 rp->macaddr[4], rp->macaddr[5]); 1215 1216 aprint_normal_dev(sc->sc_dev, 1217 "string %s, subcustomer_id 0x%x\n", 1218 rp->string, rp->subcustomer_id); 1219 1220 aprint_normal_dev(sc->sc_dev, 1221 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1222 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1223 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1224 1225 aprint_normal_dev(sc->sc_dev, 1226 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1227 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1228 rp->ht40_1s_tx_pwr[0][2], 1229 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1230 rp->ht40_1s_tx_pwr[1][2]); 1231 1232 aprint_normal_dev(sc->sc_dev, 1233 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1234 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1235 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1236 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1237 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1238 1239 aprint_normal_dev(sc->sc_dev, 1240 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1241 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1242 rp->ht20_tx_pwr_diff[2] & 0xf, 1243 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1244 rp->ht20_tx_pwr_diff[2] >> 4); 1245 1246 aprint_normal_dev(sc->sc_dev, 1247 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1248 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1249 rp->ofdm_tx_pwr_diff[2] & 0xf, 1250 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1251 rp->ofdm_tx_pwr_diff[2] >> 4); 1252 1253 aprint_normal_dev(sc->sc_dev, 1254 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1255 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1256 rp->ht40_max_pwr[2] & 0xf, 1257 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1258 rp->ht40_max_pwr[2] >> 4); 1259 1260 aprint_normal_dev(sc->sc_dev, 1261 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1262 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1263 rp->ht20_max_pwr[2] & 0xf, 1264 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1265 rp->ht20_max_pwr[2] >> 4); 1266 1267 aprint_normal_dev(sc->sc_dev, 1268 "xtal_calib %d, tssi %d %d, thermal %d\n", 1269 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1270 1271 aprint_normal_dev(sc->sc_dev, 1272 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1273 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1274 1275 aprint_normal_dev(sc->sc_dev, 1276 "channnel_plan %d, version %d customer_id 0x%x\n", 1277 rp->channel_plan, rp->version, rp->curstomer_id); 1278 } 1279 #endif 1280 1281 static void 1282 urtwn_read_rom(struct urtwn_softc *sc) 1283 { 1284 struct ieee80211com *ic = &sc->sc_ic; 1285 struct r92c_rom *rom = &sc->rom; 1286 1287 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1288 1289 mutex_enter(&sc->sc_write_mtx); 1290 1291 /* Read full ROM image. */ 1292 urtwn_efuse_read(sc); 1293 #ifdef URTWN_DEBUG 1294 if (urtwn_debug & DBG_REG) 1295 urtwn_dump_rom(sc, rom); 1296 #endif 1297 1298 /* XXX Weird but this is what the vendor driver does. */ 1299 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1300 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1301 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1302 1303 DPRINTFN(DBG_INIT, 1304 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1305 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1306 sc->board_type, sc->regulatory)); 1307 1308 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1309 1310 sc->sc_rf_write = urtwn_r92c_rf_write; 1311 sc->sc_power_on = urtwn_r92c_power_on; 1312 sc->sc_dma_init = urtwn_r92c_dma_init; 1313 1314 mutex_exit(&sc->sc_write_mtx); 1315 } 1316 1317 static void 1318 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1319 { 1320 struct ieee80211com *ic = &sc->sc_ic; 1321 uint8_t *rom = sc->r88e_rom; 1322 uint32_t reg; 1323 uint16_t addr = 0; 1324 uint8_t off, msk, tmp; 1325 int i; 1326 1327 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1328 1329 mutex_enter(&sc->sc_write_mtx); 1330 1331 off = 0; 1332 urtwn_efuse_switch_power(sc); 1333 1334 /* Read full ROM image. */ 1335 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1336 while (addr < 1024) { 1337 reg = urtwn_efuse_read_1(sc, addr); 1338 if (reg == 0xff) 1339 break; 1340 addr++; 1341 if ((reg & 0x1f) == 0x0f) { 1342 tmp = (reg & 0xe0) >> 5; 1343 reg = urtwn_efuse_read_1(sc, addr); 1344 if ((reg & 0x0f) != 0x0f) 1345 off = ((reg & 0xf0) >> 1) | tmp; 1346 addr++; 1347 } else 1348 off = reg >> 4; 1349 msk = reg & 0xf; 1350 for (i = 0; i < 4; i++) { 1351 if (msk & (1 << i)) 1352 continue; 1353 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1354 addr++; 1355 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1356 addr++; 1357 } 1358 } 1359 #ifdef URTWN_DEBUG 1360 if (urtwn_debug & DBG_REG) { 1361 } 1362 #endif 1363 1364 addr = 0x10; 1365 for (i = 0; i < 6; i++) 1366 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1367 for (i = 0; i < 5; i++) 1368 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1369 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1370 if (sc->bw20_tx_pwr_diff & 0x08) 1371 sc->bw20_tx_pwr_diff |= 0xf0; 1372 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1373 if (sc->ofdm_tx_pwr_diff & 0x08) 1374 sc->ofdm_tx_pwr_diff |= 0xf0; 1375 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1376 1377 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1378 1379 sc->sc_rf_write = urtwn_r88e_rf_write; 1380 sc->sc_power_on = urtwn_r88e_power_on; 1381 sc->sc_dma_init = urtwn_r88e_dma_init; 1382 1383 mutex_exit(&sc->sc_write_mtx); 1384 } 1385 1386 static int 1387 urtwn_media_change(struct ifnet *ifp) 1388 { 1389 #ifdef URTWN_DEBUG 1390 struct urtwn_softc *sc = ifp->if_softc; 1391 #endif 1392 int error; 1393 1394 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1395 1396 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1397 return error; 1398 1399 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1400 (IFF_UP | IFF_RUNNING)) { 1401 urtwn_init(ifp); 1402 } 1403 return 0; 1404 } 1405 1406 /* 1407 * Initialize rate adaptation in firmware. 1408 */ 1409 static int 1410 urtwn_ra_init(struct urtwn_softc *sc) 1411 { 1412 static const uint8_t map[] = { 1413 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1414 }; 1415 struct ieee80211com *ic = &sc->sc_ic; 1416 struct ieee80211_node *ni = ic->ic_bss; 1417 struct ieee80211_rateset *rs = &ni->ni_rates; 1418 struct r92c_fw_cmd_macid_cfg cmd; 1419 uint32_t rates, basicrates; 1420 uint32_t mask; 1421 uint8_t mode; 1422 size_t maxrate, maxbasicrate, i, j; 1423 int error; 1424 1425 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1426 1427 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1428 1429 /* Get normal and basic rates mask. */ 1430 rates = basicrates = 0; 1431 maxrate = maxbasicrate = 0; 1432 for (i = 0; i < rs->rs_nrates; i++) { 1433 /* Convert 802.11 rate to HW rate index. */ 1434 for (j = 0; j < __arraycount(map); j++) { 1435 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1436 break; 1437 } 1438 } 1439 if (j == __arraycount(map)) { 1440 /* Unknown rate, skip. */ 1441 continue; 1442 } 1443 1444 rates |= 1U << j; 1445 if (j > maxrate) { 1446 maxrate = j; 1447 } 1448 1449 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1450 basicrates |= 1U << j; 1451 if (j > maxbasicrate) { 1452 maxbasicrate = j; 1453 } 1454 } 1455 } 1456 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1457 mode = R92C_RAID_11B; 1458 } else { 1459 mode = R92C_RAID_11BG; 1460 } 1461 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1462 "maxrate=%zx, maxbasicrate=%zx\n", 1463 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1464 maxrate, maxbasicrate)); 1465 if (basicrates == 0) { 1466 basicrates |= 1; /* add 1Mbps */ 1467 } 1468 1469 /* Set rates mask for group addressed frames. */ 1470 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1471 mask = (mode << 28) | basicrates; 1472 cmd.mask[0] = (uint8_t)mask; 1473 cmd.mask[1] = (uint8_t)(mask >> 8); 1474 cmd.mask[2] = (uint8_t)(mask >> 16); 1475 cmd.mask[3] = (uint8_t)(mask >> 24); 1476 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1477 if (error != 0) { 1478 aprint_error_dev(sc->sc_dev, 1479 "could not add broadcast station\n"); 1480 return error; 1481 } 1482 /* Set initial MRR rate. */ 1483 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1484 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1485 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1486 1487 /* Set rates mask for unicast frames. */ 1488 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1489 mask = (mode << 28) | rates; 1490 cmd.mask[0] = (uint8_t)mask; 1491 cmd.mask[1] = (uint8_t)(mask >> 8); 1492 cmd.mask[2] = (uint8_t)(mask >> 16); 1493 cmd.mask[3] = (uint8_t)(mask >> 24); 1494 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1495 if (error != 0) { 1496 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1497 return error; 1498 } 1499 /* Set initial MRR rate. */ 1500 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1501 __func__, maxrate)); 1502 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1503 1504 /* Indicate highest supported rate. */ 1505 ni->ni_txrate = rs->rs_nrates - 1; 1506 1507 return 0; 1508 } 1509 1510 static int 1511 urtwn_get_nettype(struct urtwn_softc *sc) 1512 { 1513 struct ieee80211com *ic = &sc->sc_ic; 1514 int type; 1515 1516 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1517 1518 switch (ic->ic_opmode) { 1519 case IEEE80211_M_STA: 1520 type = R92C_CR_NETTYPE_INFRA; 1521 break; 1522 1523 case IEEE80211_M_IBSS: 1524 type = R92C_CR_NETTYPE_ADHOC; 1525 break; 1526 1527 default: 1528 type = R92C_CR_NETTYPE_NOLINK; 1529 break; 1530 } 1531 1532 return type; 1533 } 1534 1535 static void 1536 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1537 { 1538 uint8_t reg; 1539 1540 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1541 __func__, type)); 1542 1543 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1544 1545 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1546 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1547 } 1548 1549 static void 1550 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1551 { 1552 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1553 uint64_t tsf; 1554 1555 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1556 1557 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1558 1559 /* Enable TSF synchronization. */ 1560 urtwn_write_1(sc, R92C_BCN_CTRL, 1561 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1562 1563 /* Correct TSF */ 1564 urtwn_write_1(sc, R92C_BCN_CTRL, 1565 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1566 1567 /* Set initial TSF. */ 1568 tsf = ni->ni_tstamp.tsf; 1569 tsf = le64toh(tsf); 1570 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1571 tsf -= IEEE80211_DUR_TU; 1572 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1573 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1574 1575 urtwn_write_1(sc, R92C_BCN_CTRL, 1576 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1577 } 1578 1579 static void 1580 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1581 { 1582 uint8_t reg; 1583 1584 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1585 __func__, led, on)); 1586 1587 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1588 1589 if (led == URTWN_LED_LINK) { 1590 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1591 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1592 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1593 if (!on) { 1594 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1595 urtwn_write_1(sc, R92C_LEDCFG2, 1596 reg | R92C_LEDCFG0_DIS); 1597 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1598 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1599 reg & 0xfe); 1600 } 1601 } else { 1602 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1603 if (!on) { 1604 reg |= R92C_LEDCFG0_DIS; 1605 } 1606 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1607 } 1608 sc->ledlink = on; /* Save LED state. */ 1609 } 1610 } 1611 1612 static void 1613 urtwn_calib_to(void *arg) 1614 { 1615 struct urtwn_softc *sc = arg; 1616 1617 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1618 1619 if (sc->sc_dying) 1620 return; 1621 1622 /* Do it in a process context. */ 1623 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1624 } 1625 1626 /* ARGSUSED */ 1627 static void 1628 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1629 { 1630 struct r92c_fw_cmd_rssi cmd; 1631 1632 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1633 1634 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1635 goto restart_timer; 1636 1637 mutex_enter(&sc->sc_write_mtx); 1638 if (sc->avg_pwdb != -1) { 1639 /* Indicate Rx signal strength to FW for rate adaptation. */ 1640 memset(&cmd, 0, sizeof(cmd)); 1641 cmd.macid = 0; /* BSS. */ 1642 cmd.pwdb = sc->avg_pwdb; 1643 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1644 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1645 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1646 } 1647 1648 /* Do temperature compensation. */ 1649 urtwn_temp_calib(sc); 1650 mutex_exit(&sc->sc_write_mtx); 1651 1652 restart_timer: 1653 if (!sc->sc_dying) { 1654 /* Restart calibration timer. */ 1655 callout_schedule(&sc->sc_calib_to, hz); 1656 } 1657 } 1658 1659 static void 1660 urtwn_next_scan(void *arg) 1661 { 1662 struct urtwn_softc *sc = arg; 1663 int s; 1664 1665 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1666 1667 if (sc->sc_dying) 1668 return; 1669 1670 s = splnet(); 1671 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1672 ieee80211_next_scan(&sc->sc_ic); 1673 splx(s); 1674 } 1675 1676 static void 1677 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1678 { 1679 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1680 ether_sprintf(ni->ni_macaddr))); 1681 /* start with lowest Tx rate */ 1682 ni->ni_txrate = 0; 1683 } 1684 1685 static int 1686 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1687 { 1688 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1689 struct urtwn_cmd_newstate cmd; 1690 1691 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1692 device_xname(sc->sc_dev), __func__, 1693 ieee80211_state_name[nstate], nstate, arg)); 1694 1695 callout_stop(&sc->sc_scan_to); 1696 callout_stop(&sc->sc_calib_to); 1697 1698 /* Do it in a process context. */ 1699 cmd.state = nstate; 1700 cmd.arg = arg; 1701 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1702 return 0; 1703 } 1704 1705 static void 1706 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1707 { 1708 struct urtwn_cmd_newstate *cmd = arg; 1709 struct ieee80211com *ic = &sc->sc_ic; 1710 struct ieee80211_node *ni; 1711 enum ieee80211_state ostate = ic->ic_state; 1712 enum ieee80211_state nstate = cmd->state; 1713 uint32_t reg; 1714 uint8_t sifs_time, msr; 1715 int s; 1716 1717 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1718 device_xname(sc->sc_dev), __func__, 1719 ieee80211_state_name[ostate], ostate, 1720 ieee80211_state_name[nstate], nstate)); 1721 1722 s = splnet(); 1723 mutex_enter(&sc->sc_write_mtx); 1724 1725 callout_stop(&sc->sc_scan_to); 1726 callout_stop(&sc->sc_calib_to); 1727 1728 switch (ostate) { 1729 case IEEE80211_S_INIT: 1730 break; 1731 1732 case IEEE80211_S_SCAN: 1733 if (nstate != IEEE80211_S_SCAN) { 1734 /* 1735 * End of scanning 1736 */ 1737 /* flush 4-AC Queue after site_survey */ 1738 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1739 1740 /* Allow Rx from our BSSID only. */ 1741 urtwn_write_4(sc, R92C_RCR, 1742 urtwn_read_4(sc, R92C_RCR) | 1743 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1744 } 1745 break; 1746 1747 case IEEE80211_S_AUTH: 1748 case IEEE80211_S_ASSOC: 1749 break; 1750 1751 case IEEE80211_S_RUN: 1752 /* Turn link LED off. */ 1753 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1754 1755 /* Set media status to 'No Link'. */ 1756 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1757 1758 /* Stop Rx of data frames. */ 1759 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1760 1761 /* Reset TSF. */ 1762 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1763 1764 /* Disable TSF synchronization. */ 1765 urtwn_write_1(sc, R92C_BCN_CTRL, 1766 urtwn_read_1(sc, R92C_BCN_CTRL) | 1767 R92C_BCN_CTRL_DIS_TSF_UDT0); 1768 1769 /* Back to 20MHz mode */ 1770 urtwn_set_chan(sc, ic->ic_curchan, 1771 IEEE80211_HTINFO_2NDCHAN_NONE); 1772 1773 if (ic->ic_opmode == IEEE80211_M_IBSS || 1774 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1775 /* Stop BCN */ 1776 urtwn_write_1(sc, R92C_BCN_CTRL, 1777 urtwn_read_1(sc, R92C_BCN_CTRL) & 1778 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1779 } 1780 1781 /* Reset EDCA parameters. */ 1782 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1783 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1784 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1785 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1786 1787 /* flush all cam entries */ 1788 urtwn_cam_init(sc); 1789 break; 1790 } 1791 1792 switch (nstate) { 1793 case IEEE80211_S_INIT: 1794 /* Turn link LED off. */ 1795 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1796 break; 1797 1798 case IEEE80211_S_SCAN: 1799 if (ostate != IEEE80211_S_SCAN) { 1800 /* 1801 * Begin of scanning 1802 */ 1803 1804 /* Set gain for scanning. */ 1805 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1806 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1807 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1808 1809 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1810 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1811 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1812 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1813 } 1814 1815 /* Set media status to 'No Link'. */ 1816 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1817 1818 /* Allow Rx from any BSSID. */ 1819 urtwn_write_4(sc, R92C_RCR, 1820 urtwn_read_4(sc, R92C_RCR) & 1821 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1822 1823 /* Stop Rx of data frames. */ 1824 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1825 1826 /* Disable update TSF */ 1827 urtwn_write_1(sc, R92C_BCN_CTRL, 1828 urtwn_read_1(sc, R92C_BCN_CTRL) | 1829 R92C_BCN_CTRL_DIS_TSF_UDT0); 1830 } 1831 1832 /* Make link LED blink during scan. */ 1833 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1834 1835 /* Pause AC Tx queues. */ 1836 urtwn_write_1(sc, R92C_TXPAUSE, 1837 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1838 1839 urtwn_set_chan(sc, ic->ic_curchan, 1840 IEEE80211_HTINFO_2NDCHAN_NONE); 1841 1842 /* Start periodic scan. */ 1843 if (!sc->sc_dying) 1844 callout_schedule(&sc->sc_scan_to, hz / 5); 1845 break; 1846 1847 case IEEE80211_S_AUTH: 1848 /* Set initial gain under link. */ 1849 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1850 #ifdef doaslinux 1851 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1852 #else 1853 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1854 #endif 1855 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1856 1857 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1858 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1859 #ifdef doaslinux 1860 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1861 #else 1862 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1863 #endif 1864 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1865 } 1866 1867 /* Set media status to 'No Link'. */ 1868 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1869 1870 /* Allow Rx from any BSSID. */ 1871 urtwn_write_4(sc, R92C_RCR, 1872 urtwn_read_4(sc, R92C_RCR) & 1873 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1874 1875 urtwn_set_chan(sc, ic->ic_curchan, 1876 IEEE80211_HTINFO_2NDCHAN_NONE); 1877 break; 1878 1879 case IEEE80211_S_ASSOC: 1880 break; 1881 1882 case IEEE80211_S_RUN: 1883 ni = ic->ic_bss; 1884 1885 /* XXX: Set 20MHz mode */ 1886 urtwn_set_chan(sc, ic->ic_curchan, 1887 IEEE80211_HTINFO_2NDCHAN_NONE); 1888 1889 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1890 /* Back to 20MHz mode */ 1891 urtwn_set_chan(sc, ic->ic_curchan, 1892 IEEE80211_HTINFO_2NDCHAN_NONE); 1893 1894 /* Set media status to 'No Link'. */ 1895 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1896 1897 /* Enable Rx of data frames. */ 1898 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1899 1900 /* Allow Rx from any BSSID. */ 1901 urtwn_write_4(sc, R92C_RCR, 1902 urtwn_read_4(sc, R92C_RCR) & 1903 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1904 1905 /* Accept Rx data/control/management frames */ 1906 urtwn_write_4(sc, R92C_RCR, 1907 urtwn_read_4(sc, R92C_RCR) | 1908 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1909 1910 /* Turn link LED on. */ 1911 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1912 break; 1913 } 1914 1915 /* Set media status to 'Associated'. */ 1916 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1917 1918 /* Set BSSID. */ 1919 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1920 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1921 1922 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1923 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1924 } else { 1925 /* 802.11b/g */ 1926 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1927 } 1928 1929 /* Enable Rx of data frames. */ 1930 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1931 1932 /* Set beacon interval. */ 1933 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1934 1935 msr = urtwn_read_1(sc, R92C_MSR); 1936 msr &= R92C_MSR_MASK; 1937 switch (ic->ic_opmode) { 1938 case IEEE80211_M_STA: 1939 /* Allow Rx from our BSSID only. */ 1940 urtwn_write_4(sc, R92C_RCR, 1941 urtwn_read_4(sc, R92C_RCR) | 1942 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1943 1944 /* Enable TSF synchronization. */ 1945 urtwn_tsf_sync_enable(sc); 1946 1947 msr |= R92C_MSR_INFRA; 1948 break; 1949 case IEEE80211_M_HOSTAP: 1950 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1951 1952 /* Allow Rx from any BSSID. */ 1953 urtwn_write_4(sc, R92C_RCR, 1954 urtwn_read_4(sc, R92C_RCR) & 1955 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1956 1957 /* Reset TSF timer to zero. */ 1958 reg = urtwn_read_4(sc, R92C_TCR); 1959 reg &= ~0x01; 1960 urtwn_write_4(sc, R92C_TCR, reg); 1961 reg |= 0x01; 1962 urtwn_write_4(sc, R92C_TCR, reg); 1963 1964 msr |= R92C_MSR_AP; 1965 break; 1966 default: 1967 msr |= R92C_MSR_ADHOC; 1968 break; 1969 } 1970 urtwn_write_1(sc, R92C_MSR, msr); 1971 1972 sifs_time = 10; 1973 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1974 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1975 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1976 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1977 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1978 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1979 1980 /* Intialize rate adaptation. */ 1981 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1982 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 1983 else 1984 urtwn_ra_init(sc); 1985 1986 /* Turn link LED on. */ 1987 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1988 1989 /* Reset average RSSI. */ 1990 sc->avg_pwdb = -1; 1991 1992 /* Reset temperature calibration state machine. */ 1993 sc->thcal_state = 0; 1994 sc->thcal_lctemp = 0; 1995 1996 /* Start periodic calibration. */ 1997 if (!sc->sc_dying) 1998 callout_schedule(&sc->sc_calib_to, hz); 1999 break; 2000 } 2001 2002 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2003 2004 mutex_exit(&sc->sc_write_mtx); 2005 splx(s); 2006 } 2007 2008 static int 2009 urtwn_wme_update(struct ieee80211com *ic) 2010 { 2011 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2012 2013 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2014 2015 /* don't override default WME values if WME is not actually enabled */ 2016 if (!(ic->ic_flags & IEEE80211_F_WME)) 2017 return 0; 2018 2019 /* Do it in a process context. */ 2020 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2021 return 0; 2022 } 2023 2024 static void 2025 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2026 { 2027 static const uint16_t ac2reg[WME_NUM_AC] = { 2028 R92C_EDCA_BE_PARAM, 2029 R92C_EDCA_BK_PARAM, 2030 R92C_EDCA_VI_PARAM, 2031 R92C_EDCA_VO_PARAM 2032 }; 2033 struct ieee80211com *ic = &sc->sc_ic; 2034 const struct wmeParams *wmep; 2035 int ac, aifs, slottime; 2036 int s; 2037 2038 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2039 __func__)); 2040 2041 s = splnet(); 2042 mutex_enter(&sc->sc_write_mtx); 2043 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2044 for (ac = 0; ac < WME_NUM_AC; ac++) { 2045 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2046 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2047 aifs = wmep->wmep_aifsn * slottime + 10; 2048 urtwn_write_4(sc, ac2reg[ac], 2049 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2050 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2051 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2052 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2053 } 2054 mutex_exit(&sc->sc_write_mtx); 2055 splx(s); 2056 } 2057 2058 static void 2059 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2060 { 2061 int pwdb; 2062 2063 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2064 device_xname(sc->sc_dev), __func__, rate, rssi)); 2065 2066 /* Convert antenna signal to percentage. */ 2067 if (rssi <= -100 || rssi >= 20) 2068 pwdb = 0; 2069 else if (rssi >= 0) 2070 pwdb = 100; 2071 else 2072 pwdb = 100 + rssi; 2073 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2074 if (rate <= 3) { 2075 /* CCK gain is smaller than OFDM/MCS gain. */ 2076 pwdb += 6; 2077 if (pwdb > 100) 2078 pwdb = 100; 2079 if (pwdb <= 14) 2080 pwdb -= 4; 2081 else if (pwdb <= 26) 2082 pwdb -= 8; 2083 else if (pwdb <= 34) 2084 pwdb -= 6; 2085 else if (pwdb <= 42) 2086 pwdb -= 2; 2087 } 2088 } 2089 if (sc->avg_pwdb == -1) /* Init. */ 2090 sc->avg_pwdb = pwdb; 2091 else if (sc->avg_pwdb < pwdb) 2092 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2093 else 2094 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2095 2096 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2097 device_xname(sc->sc_dev), __func__, 2098 rate, rssi, pwdb, sc->avg_pwdb)); 2099 } 2100 2101 static int8_t 2102 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2103 { 2104 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2105 struct r92c_rx_phystat *phy; 2106 struct r92c_rx_cck *cck; 2107 uint8_t rpt; 2108 int8_t rssi; 2109 2110 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2111 __func__, rate)); 2112 2113 if (rate <= 3) { 2114 cck = (struct r92c_rx_cck *)physt; 2115 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2116 rpt = (cck->agc_rpt >> 5) & 0x3; 2117 rssi = (cck->agc_rpt & 0x1f) << 1; 2118 } else { 2119 rpt = (cck->agc_rpt >> 6) & 0x3; 2120 rssi = cck->agc_rpt & 0x3e; 2121 } 2122 rssi = cckoff[rpt] - rssi; 2123 } else { /* OFDM/HT. */ 2124 phy = (struct r92c_rx_phystat *)physt; 2125 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2126 } 2127 return rssi; 2128 } 2129 2130 static int8_t 2131 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2132 { 2133 struct r92c_rx_phystat *phy; 2134 struct r88e_rx_cck *cck; 2135 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2136 int8_t rssi; 2137 2138 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2139 __func__, rate)); 2140 2141 rssi = 0; 2142 if (rate <= 3) { 2143 cck = (struct r88e_rx_cck *)physt; 2144 cck_agc_rpt = cck->agc_rpt; 2145 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2146 vga_idx = cck_agc_rpt & 0x1f; 2147 switch (lna_idx) { 2148 case 7: 2149 if (vga_idx <= 27) 2150 rssi = -100 + 2* (27 - vga_idx); 2151 else 2152 rssi = -100; 2153 break; 2154 case 6: 2155 rssi = -48 + 2 * (2 - vga_idx); 2156 break; 2157 case 5: 2158 rssi = -42 + 2 * (7 - vga_idx); 2159 break; 2160 case 4: 2161 rssi = -36 + 2 * (7 - vga_idx); 2162 break; 2163 case 3: 2164 rssi = -24 + 2 * (7 - vga_idx); 2165 break; 2166 case 2: 2167 rssi = -12 + 2 * (5 - vga_idx); 2168 break; 2169 case 1: 2170 rssi = 8 - (2 * vga_idx); 2171 break; 2172 case 0: 2173 rssi = 14 - (2 * vga_idx); 2174 break; 2175 } 2176 rssi += 6; 2177 } else { /* OFDM/HT. */ 2178 phy = (struct r92c_rx_phystat *)physt; 2179 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2180 } 2181 return rssi; 2182 } 2183 2184 static void 2185 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2186 { 2187 struct ieee80211com *ic = &sc->sc_ic; 2188 struct ifnet *ifp = ic->ic_ifp; 2189 struct ieee80211_frame *wh; 2190 struct ieee80211_node *ni; 2191 struct r92c_rx_stat *stat; 2192 uint32_t rxdw0, rxdw3; 2193 struct mbuf *m; 2194 uint8_t rate; 2195 int8_t rssi = 0; 2196 int s, infosz; 2197 2198 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2199 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2200 2201 stat = (struct r92c_rx_stat *)buf; 2202 rxdw0 = le32toh(stat->rxdw0); 2203 rxdw3 = le32toh(stat->rxdw3); 2204 2205 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2206 /* 2207 * This should not happen since we setup our Rx filter 2208 * to not receive these frames. 2209 */ 2210 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2211 device_xname(sc->sc_dev), __func__)); 2212 ifp->if_ierrors++; 2213 return; 2214 } 2215 /* 2216 * XXX: This will drop most control packets. Do we really 2217 * want this in IEEE80211_M_MONITOR mode? 2218 */ 2219 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2220 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2221 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2222 device_xname(sc->sc_dev), __func__, pktlen)); 2223 ic->ic_stats.is_rx_tooshort++; 2224 ifp->if_ierrors++; 2225 return; 2226 } 2227 if (__predict_false(pktlen > MCLBYTES)) { 2228 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2229 device_xname(sc->sc_dev), __func__, pktlen)); 2230 ifp->if_ierrors++; 2231 return; 2232 } 2233 2234 rate = MS(rxdw3, R92C_RXDW3_RATE); 2235 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2236 2237 /* Get RSSI from PHY status descriptor if present. */ 2238 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2239 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2240 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2241 else 2242 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2243 /* Update our average RSSI. */ 2244 urtwn_update_avgrssi(sc, rate, rssi); 2245 } 2246 2247 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2248 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2249 2250 MGETHDR(m, M_DONTWAIT, MT_DATA); 2251 if (__predict_false(m == NULL)) { 2252 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2253 ic->ic_stats.is_rx_nobuf++; 2254 ifp->if_ierrors++; 2255 return; 2256 } 2257 if (pktlen > (int)MHLEN) { 2258 MCLGET(m, M_DONTWAIT); 2259 if (__predict_false(!(m->m_flags & M_EXT))) { 2260 aprint_error_dev(sc->sc_dev, 2261 "couldn't allocate rx mbuf cluster\n"); 2262 m_freem(m); 2263 ic->ic_stats.is_rx_nobuf++; 2264 ifp->if_ierrors++; 2265 return; 2266 } 2267 } 2268 2269 /* Finalize mbuf. */ 2270 m->m_pkthdr.rcvif = ifp; 2271 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2272 memcpy(mtod(m, uint8_t *), wh, pktlen); 2273 m->m_pkthdr.len = m->m_len = pktlen; 2274 2275 s = splnet(); 2276 if (__predict_false(sc->sc_drvbpf != NULL)) { 2277 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2278 2279 tap->wr_flags = 0; 2280 if (!(rxdw3 & R92C_RXDW3_HT)) { 2281 switch (rate) { 2282 /* CCK. */ 2283 case 0: tap->wr_rate = 2; break; 2284 case 1: tap->wr_rate = 4; break; 2285 case 2: tap->wr_rate = 11; break; 2286 case 3: tap->wr_rate = 22; break; 2287 /* OFDM. */ 2288 case 4: tap->wr_rate = 12; break; 2289 case 5: tap->wr_rate = 18; break; 2290 case 6: tap->wr_rate = 24; break; 2291 case 7: tap->wr_rate = 36; break; 2292 case 8: tap->wr_rate = 48; break; 2293 case 9: tap->wr_rate = 72; break; 2294 case 10: tap->wr_rate = 96; break; 2295 case 11: tap->wr_rate = 108; break; 2296 } 2297 } else if (rate >= 12) { /* MCS0~15. */ 2298 /* Bit 7 set means HT MCS instead of rate. */ 2299 tap->wr_rate = 0x80 | (rate - 12); 2300 } 2301 tap->wr_dbm_antsignal = rssi; 2302 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2303 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2304 2305 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2306 } 2307 2308 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2309 2310 /* push the frame up to the 802.11 stack */ 2311 ieee80211_input(ic, m, ni, rssi, 0); 2312 2313 /* Node is no longer needed. */ 2314 ieee80211_free_node(ni); 2315 2316 splx(s); 2317 } 2318 2319 static void 2320 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2321 { 2322 struct urtwn_rx_data *data = priv; 2323 struct urtwn_softc *sc = data->sc; 2324 struct r92c_rx_stat *stat; 2325 uint32_t rxdw0; 2326 uint8_t *buf; 2327 int len, totlen, pktlen, infosz, npkts; 2328 2329 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2330 device_xname(sc->sc_dev), __func__, status)); 2331 2332 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2333 if (status == USBD_STALLED) 2334 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2335 else if (status != USBD_CANCELLED) 2336 goto resubmit; 2337 return; 2338 } 2339 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2340 2341 if (__predict_false(len < (int)sizeof(*stat))) { 2342 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2343 device_xname(sc->sc_dev), __func__, len)); 2344 goto resubmit; 2345 } 2346 buf = data->buf; 2347 2348 /* Get the number of encapsulated frames. */ 2349 stat = (struct r92c_rx_stat *)buf; 2350 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2351 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2352 device_xname(sc->sc_dev), __func__, npkts)); 2353 2354 /* Process all of them. */ 2355 while (npkts-- > 0) { 2356 if (__predict_false(len < (int)sizeof(*stat))) { 2357 DPRINTFN(DBG_RX, 2358 ("%s: %s: len(%d) is short than header\n", 2359 device_xname(sc->sc_dev), __func__, len)); 2360 break; 2361 } 2362 stat = (struct r92c_rx_stat *)buf; 2363 rxdw0 = le32toh(stat->rxdw0); 2364 2365 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2366 if (__predict_false(pktlen == 0)) { 2367 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2368 device_xname(sc->sc_dev), __func__)); 2369 break; 2370 } 2371 2372 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2373 2374 /* Make sure everything fits in xfer. */ 2375 totlen = sizeof(*stat) + infosz + pktlen; 2376 if (__predict_false(totlen > len)) { 2377 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2378 device_xname(sc->sc_dev), __func__, totlen, 2379 (int)sizeof(*stat), infosz, pktlen, len)); 2380 break; 2381 } 2382 2383 /* Process 802.11 frame. */ 2384 urtwn_rx_frame(sc, buf, pktlen); 2385 2386 /* Next chunk is 128-byte aligned. */ 2387 totlen = roundup2(totlen, 128); 2388 buf += totlen; 2389 len -= totlen; 2390 } 2391 2392 resubmit: 2393 /* Setup a new transfer. */ 2394 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2395 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2396 (void)usbd_transfer(xfer); 2397 } 2398 2399 static void 2400 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2401 { 2402 struct urtwn_tx_data *data = priv; 2403 struct urtwn_softc *sc = data->sc; 2404 struct ifnet *ifp = &sc->sc_if; 2405 size_t pidx = data->pidx; 2406 int s; 2407 2408 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2409 device_xname(sc->sc_dev), __func__, status)); 2410 2411 mutex_enter(&sc->sc_tx_mtx); 2412 /* Put this Tx buffer back to our free list. */ 2413 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2414 mutex_exit(&sc->sc_tx_mtx); 2415 2416 s = splnet(); 2417 sc->tx_timer = 0; 2418 ifp->if_flags &= ~IFF_OACTIVE; 2419 2420 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2421 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2422 if (status == USBD_STALLED) { 2423 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2424 usbd_clear_endpoint_stall_async(pipe); 2425 } 2426 ifp->if_oerrors++; 2427 } 2428 splx(s); 2429 return; 2430 } 2431 2432 ifp->if_opackets++; 2433 urtwn_start(ifp); 2434 2435 splx(s); 2436 } 2437 2438 static int 2439 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2440 struct urtwn_tx_data *data) 2441 { 2442 struct ieee80211com *ic = &sc->sc_ic; 2443 struct ieee80211_frame *wh; 2444 struct ieee80211_key *k = NULL; 2445 struct r92c_tx_desc *txd; 2446 size_t i, padsize, xferlen; 2447 uint16_t seq, sum; 2448 uint8_t raid, type, tid; 2449 int s, hasqos, error; 2450 2451 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2452 2453 wh = mtod(m, struct ieee80211_frame *); 2454 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2455 2456 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2457 k = ieee80211_crypto_encap(ic, ni, m); 2458 if (k == NULL) 2459 return ENOBUFS; 2460 2461 /* packet header may have moved, reset our local pointer */ 2462 wh = mtod(m, struct ieee80211_frame *); 2463 } 2464 2465 if (__predict_false(sc->sc_drvbpf != NULL)) { 2466 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2467 2468 tap->wt_flags = 0; 2469 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2470 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2471 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2472 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2473 2474 /* XXX: set tap->wt_rate? */ 2475 2476 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2477 } 2478 2479 /* non-qos data frames */ 2480 tid = R92C_TXDW1_QSEL_BE; 2481 if ((hasqos = ieee80211_has_qos(wh))) { 2482 /* data frames in 11n mode */ 2483 struct ieee80211_qosframe *qwh = (void *)wh; 2484 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2485 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2486 tid = R92C_TXDW1_QSEL_MGNT; 2487 } 2488 2489 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2490 padsize = 8; 2491 else 2492 padsize = 0; 2493 2494 /* Fill Tx descriptor. */ 2495 txd = (struct r92c_tx_desc *)data->buf; 2496 memset(txd, 0, sizeof(*txd) + padsize); 2497 2498 txd->txdw0 |= htole32( 2499 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2500 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2501 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2502 2503 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2504 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2505 2506 /* fix pad field */ 2507 if (padsize > 0) { 2508 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2509 device_xname(sc->sc_dev), __func__, padsize)); 2510 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2511 } 2512 2513 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2514 type == IEEE80211_FC0_TYPE_DATA) { 2515 if (ic->ic_curmode == IEEE80211_MODE_11B) 2516 raid = R92C_RAID_11B; 2517 else 2518 raid = R92C_RAID_11BG; 2519 DPRINTFN(DBG_TX, 2520 ("%s: %s: data packet: tid=%d, raid=%d\n", 2521 device_xname(sc->sc_dev), __func__, tid, raid)); 2522 2523 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 2524 txd->txdw1 |= htole32( 2525 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2526 SM(R92C_TXDW1_QSEL, tid) | 2527 SM(R92C_TXDW1_RAID, raid) | 2528 R92C_TXDW1_AGGBK); 2529 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2530 } else 2531 txd->txdw1 |= htole32( 2532 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2533 SM(R92C_TXDW1_QSEL, tid) | 2534 SM(R92C_TXDW1_RAID, raid) | 2535 R92C_TXDW1_AGGBK); 2536 2537 if (hasqos) { 2538 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2539 } 2540 2541 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2542 /* for 11g */ 2543 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2544 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2545 R92C_TXDW4_HWRTSEN); 2546 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2547 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2548 R92C_TXDW4_HWRTSEN); 2549 } 2550 } 2551 /* Send RTS at OFDM24. */ 2552 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2553 txd->txdw5 |= htole32(0x0001ff00); 2554 /* Send data at OFDM54. */ 2555 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2556 txd->txdw5 |= htole32(0x13 & 0x3f); 2557 else 2558 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2559 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2560 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2561 device_xname(sc->sc_dev), __func__)); 2562 txd->txdw1 |= htole32( 2563 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2564 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2565 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2566 2567 /* Force CCK1. */ 2568 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2569 /* Use 1Mbps */ 2570 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2571 } else { 2572 /* broadcast or multicast packets */ 2573 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2574 device_xname(sc->sc_dev), __func__)); 2575 txd->txdw1 |= htole32( 2576 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2577 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2578 2579 /* Force CCK1. */ 2580 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2581 /* Use 1Mbps */ 2582 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2583 } 2584 2585 /* Set sequence number */ 2586 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2587 txd->txdseq |= htole16(seq); 2588 2589 if (!hasqos) { 2590 /* Use HW sequence numbering for non-QoS frames. */ 2591 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2592 txd->txdseq |= htole16(0x8000); /* WTF? */ 2593 } 2594 2595 /* Compute Tx descriptor checksum. */ 2596 sum = 0; 2597 for (i = 0; i < sizeof(*txd) / 2; i++) 2598 sum ^= ((uint16_t *)txd)[i]; 2599 txd->txdsum = sum; /* NB: already little endian. */ 2600 2601 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2602 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2603 2604 s = splnet(); 2605 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2606 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2607 urtwn_txeof); 2608 error = usbd_transfer(data->xfer); 2609 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2610 error != USBD_IN_PROGRESS)) { 2611 splx(s); 2612 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2613 device_xname(sc->sc_dev), __func__, error)); 2614 return error; 2615 } 2616 splx(s); 2617 return 0; 2618 } 2619 2620 struct urtwn_tx_data * 2621 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2622 { 2623 struct urtwn_tx_data *data = NULL; 2624 2625 mutex_enter(&sc->sc_tx_mtx); 2626 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2627 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2628 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2629 } 2630 mutex_exit(&sc->sc_tx_mtx); 2631 2632 return data; 2633 } 2634 2635 static void 2636 urtwn_start(struct ifnet *ifp) 2637 { 2638 struct urtwn_softc *sc = ifp->if_softc; 2639 struct ieee80211com *ic = &sc->sc_ic; 2640 struct urtwn_tx_data *data; 2641 struct ether_header *eh; 2642 struct ieee80211_node *ni; 2643 struct mbuf *m; 2644 2645 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2646 2647 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2648 return; 2649 2650 data = NULL; 2651 for (;;) { 2652 /* Send pending management frames first. */ 2653 IF_POLL(&ic->ic_mgtq, m); 2654 if (m != NULL) { 2655 /* Use AC_VO for management frames. */ 2656 2657 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2658 2659 if (data == NULL) { 2660 ifp->if_flags |= IFF_OACTIVE; 2661 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2662 device_xname(sc->sc_dev))); 2663 return; 2664 } 2665 IF_DEQUEUE(&ic->ic_mgtq, m); 2666 ni = (void *)m->m_pkthdr.rcvif; 2667 m->m_pkthdr.rcvif = NULL; 2668 goto sendit; 2669 } 2670 if (ic->ic_state != IEEE80211_S_RUN) 2671 break; 2672 2673 /* Encapsulate and send data frames. */ 2674 IFQ_POLL(&ifp->if_snd, m); 2675 if (m == NULL) 2676 break; 2677 2678 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2679 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2680 uint8_t qid = WME_AC_BE; 2681 if (ieee80211_has_qos(wh)) { 2682 /* data frames in 11n mode */ 2683 struct ieee80211_qosframe *qwh = (void *)wh; 2684 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2685 qid = TID_TO_WME_AC(tid); 2686 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2687 qid = WME_AC_VO; 2688 } 2689 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2690 2691 if (data == NULL) { 2692 ifp->if_flags |= IFF_OACTIVE; 2693 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2694 device_xname(sc->sc_dev))); 2695 return; 2696 } 2697 IFQ_DEQUEUE(&ifp->if_snd, m); 2698 2699 if (m->m_len < (int)sizeof(*eh) && 2700 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2701 ifp->if_oerrors++; 2702 continue; 2703 } 2704 eh = mtod(m, struct ether_header *); 2705 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2706 if (ni == NULL) { 2707 m_freem(m); 2708 ifp->if_oerrors++; 2709 continue; 2710 } 2711 2712 bpf_mtap(ifp, m); 2713 2714 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2715 ieee80211_free_node(ni); 2716 ifp->if_oerrors++; 2717 continue; 2718 } 2719 sendit: 2720 bpf_mtap3(ic->ic_rawbpf, m); 2721 2722 if (urtwn_tx(sc, m, ni, data) != 0) { 2723 m_freem(m); 2724 ieee80211_free_node(ni); 2725 ifp->if_oerrors++; 2726 continue; 2727 } 2728 m_freem(m); 2729 ieee80211_free_node(ni); 2730 sc->tx_timer = 5; 2731 ifp->if_timer = 1; 2732 } 2733 } 2734 2735 static void 2736 urtwn_watchdog(struct ifnet *ifp) 2737 { 2738 struct urtwn_softc *sc = ifp->if_softc; 2739 2740 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2741 2742 ifp->if_timer = 0; 2743 2744 if (sc->tx_timer > 0) { 2745 if (--sc->tx_timer == 0) { 2746 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2747 /* urtwn_init(ifp); XXX needs a process context! */ 2748 ifp->if_oerrors++; 2749 return; 2750 } 2751 ifp->if_timer = 1; 2752 } 2753 ieee80211_watchdog(&sc->sc_ic); 2754 } 2755 2756 static int 2757 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2758 { 2759 struct urtwn_softc *sc = ifp->if_softc; 2760 struct ieee80211com *ic = &sc->sc_ic; 2761 int s, error = 0; 2762 2763 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2764 device_xname(sc->sc_dev), __func__, cmd, data)); 2765 2766 s = splnet(); 2767 2768 switch (cmd) { 2769 case SIOCSIFFLAGS: 2770 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2771 break; 2772 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2773 case IFF_UP | IFF_RUNNING: 2774 break; 2775 case IFF_UP: 2776 urtwn_init(ifp); 2777 break; 2778 case IFF_RUNNING: 2779 urtwn_stop(ifp, 1); 2780 break; 2781 case 0: 2782 break; 2783 } 2784 break; 2785 2786 case SIOCADDMULTI: 2787 case SIOCDELMULTI: 2788 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2789 /* setup multicast filter, etc */ 2790 error = 0; 2791 } 2792 break; 2793 2794 default: 2795 error = ieee80211_ioctl(ic, cmd, data); 2796 break; 2797 } 2798 if (error == ENETRESET) { 2799 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2800 (IFF_UP | IFF_RUNNING) && 2801 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2802 urtwn_init(ifp); 2803 } 2804 error = 0; 2805 } 2806 2807 splx(s); 2808 2809 return error; 2810 } 2811 2812 static __inline int 2813 urtwn_power_on(struct urtwn_softc *sc) 2814 { 2815 2816 return sc->sc_power_on(sc); 2817 } 2818 2819 static int 2820 urtwn_r92c_power_on(struct urtwn_softc *sc) 2821 { 2822 uint32_t reg; 2823 int ntries; 2824 2825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2826 2827 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2828 2829 /* Wait for autoload done bit. */ 2830 for (ntries = 0; ntries < 1000; ntries++) { 2831 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2832 break; 2833 DELAY(5); 2834 } 2835 if (ntries == 1000) { 2836 aprint_error_dev(sc->sc_dev, 2837 "timeout waiting for chip autoload\n"); 2838 return ETIMEDOUT; 2839 } 2840 2841 /* Unlock ISO/CLK/Power control register. */ 2842 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2843 /* Move SPS into PWM mode. */ 2844 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2845 DELAY(100); 2846 2847 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2848 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2849 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2850 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2851 DELAY(100); 2852 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2853 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2854 ~R92C_SYS_ISO_CTRL_MD2PP); 2855 } 2856 2857 /* Auto enable WLAN. */ 2858 urtwn_write_2(sc, R92C_APS_FSMCO, 2859 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2860 for (ntries = 0; ntries < 1000; ntries++) { 2861 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2862 R92C_APS_FSMCO_APFM_ONMAC)) 2863 break; 2864 DELAY(5); 2865 } 2866 if (ntries == 1000) { 2867 aprint_error_dev(sc->sc_dev, 2868 "timeout waiting for MAC auto ON\n"); 2869 return ETIMEDOUT; 2870 } 2871 2872 /* Enable radio, GPIO and LED functions. */ 2873 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2874 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2875 urtwn_write_2(sc, R92C_APS_FSMCO, 2876 R92C_APS_FSMCO_AFSM_HSUS | 2877 R92C_APS_FSMCO_PDN_EN | 2878 R92C_APS_FSMCO_PFM_ALDN); 2879 2880 /* Release RF digital isolation. */ 2881 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2882 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2883 2884 /* Initialize MAC. */ 2885 urtwn_write_1(sc, R92C_APSD_CTRL, 2886 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2887 for (ntries = 0; ntries < 200; ntries++) { 2888 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2889 R92C_APSD_CTRL_OFF_STATUS)) 2890 break; 2891 DELAY(5); 2892 } 2893 if (ntries == 200) { 2894 aprint_error_dev(sc->sc_dev, 2895 "timeout waiting for MAC initialization\n"); 2896 return ETIMEDOUT; 2897 } 2898 2899 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2900 reg = urtwn_read_2(sc, R92C_CR); 2901 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2902 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2903 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2904 R92C_CR_ENSEC; 2905 urtwn_write_2(sc, R92C_CR, reg); 2906 2907 urtwn_write_1(sc, 0xfe10, 0x19); 2908 return 0; 2909 } 2910 2911 static int 2912 urtwn_r88e_power_on(struct urtwn_softc *sc) 2913 { 2914 uint32_t reg; 2915 uint8_t val; 2916 int ntries; 2917 2918 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2919 2920 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2921 2922 /* Wait for power ready bit. */ 2923 for (ntries = 0; ntries < 5000; ntries++) { 2924 val = urtwn_read_1(sc, 0x6) & 0x2; 2925 if (val == 0x2) 2926 break; 2927 DELAY(10); 2928 } 2929 if (ntries == 5000) { 2930 aprint_error_dev(sc->sc_dev, 2931 "timeout waiting for chip power up\n"); 2932 return ETIMEDOUT; 2933 } 2934 2935 /* Reset BB. */ 2936 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2937 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2938 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2939 2940 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2941 2942 /* Disable HWPDN. */ 2943 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2944 2945 /* Disable WL suspend. */ 2946 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2947 2948 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2949 for (ntries = 0; ntries < 5000; ntries++) { 2950 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2951 break; 2952 DELAY(10); 2953 } 2954 if (ntries == 5000) 2955 return ETIMEDOUT; 2956 2957 /* Enable LDO normal mode. */ 2958 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2959 2960 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2961 urtwn_write_2(sc, R92C_CR, 0); 2962 reg = urtwn_read_2(sc, R92C_CR); 2963 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2964 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2965 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2966 urtwn_write_2(sc, R92C_CR, reg); 2967 2968 return 0; 2969 } 2970 2971 static int 2972 urtwn_llt_init(struct urtwn_softc *sc) 2973 { 2974 size_t i, page_count, pktbuf_count; 2975 int error; 2976 2977 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2978 2979 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2980 2981 page_count = (sc->chip & URTWN_CHIP_88E) ? 2982 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2983 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2984 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2985 2986 /* Reserve pages [0; page_count]. */ 2987 for (i = 0; i < page_count; i++) { 2988 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2989 return error; 2990 } 2991 /* NB: 0xff indicates end-of-list. */ 2992 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2993 return error; 2994 /* 2995 * Use pages [page_count + 1; pktbuf_count - 1] 2996 * as ring buffer. 2997 */ 2998 for (++i; i < pktbuf_count - 1; i++) { 2999 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3000 return error; 3001 } 3002 /* Make the last page point to the beginning of the ring buffer. */ 3003 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3004 return error; 3005 } 3006 3007 static void 3008 urtwn_fw_reset(struct urtwn_softc *sc) 3009 { 3010 uint16_t reg; 3011 int ntries; 3012 3013 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3014 3015 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3016 3017 /* Tell 8051 to reset itself. */ 3018 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3019 3020 /* Wait until 8051 resets by itself. */ 3021 for (ntries = 0; ntries < 100; ntries++) { 3022 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3023 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3024 return; 3025 DELAY(50); 3026 } 3027 /* Force 8051 reset. */ 3028 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3029 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3030 } 3031 3032 static void 3033 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3034 { 3035 uint16_t reg; 3036 3037 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3038 3039 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3040 3041 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3042 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3043 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3044 } 3045 3046 static int 3047 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3048 { 3049 uint32_t reg; 3050 int off, mlen, error = 0; 3051 3052 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3053 device_xname(sc->sc_dev), __func__, page, buf, len)); 3054 3055 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3056 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3057 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3058 3059 off = R92C_FW_START_ADDR; 3060 while (len > 0) { 3061 if (len > 196) 3062 mlen = 196; 3063 else if (len > 4) 3064 mlen = 4; 3065 else 3066 mlen = 1; 3067 error = urtwn_write_region(sc, off, buf, mlen); 3068 if (error != 0) 3069 break; 3070 off += mlen; 3071 buf += mlen; 3072 len -= mlen; 3073 } 3074 return error; 3075 } 3076 3077 static int 3078 urtwn_load_firmware(struct urtwn_softc *sc) 3079 { 3080 firmware_handle_t fwh; 3081 const struct r92c_fw_hdr *hdr; 3082 const char *name; 3083 u_char *fw, *ptr; 3084 size_t len; 3085 uint32_t reg; 3086 int mlen, ntries, page, error; 3087 3088 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3089 3090 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3091 3092 /* Read firmware image from the filesystem. */ 3093 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3094 name = "rtl8188eufw.bin"; 3095 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3096 URTWN_CHIP_UMC_A_CUT) 3097 name = "rtl8192cfwU.bin"; 3098 else 3099 name = "rtl8192cfw.bin"; 3100 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3101 aprint_error_dev(sc->sc_dev, 3102 "failed load firmware of file %s (error %d)\n", name, 3103 error); 3104 return error; 3105 } 3106 const size_t fwlen = len = firmware_get_size(fwh); 3107 fw = firmware_malloc(len); 3108 if (fw == NULL) { 3109 aprint_error_dev(sc->sc_dev, 3110 "failed to allocate firmware memory\n"); 3111 firmware_close(fwh); 3112 return ENOMEM; 3113 } 3114 error = firmware_read(fwh, 0, fw, len); 3115 firmware_close(fwh); 3116 if (error != 0) { 3117 aprint_error_dev(sc->sc_dev, 3118 "failed to read firmware (error %d)\n", error); 3119 firmware_free(fw, fwlen); 3120 return error; 3121 } 3122 3123 ptr = fw; 3124 hdr = (const struct r92c_fw_hdr *)ptr; 3125 /* Check if there is a valid FW header and skip it. */ 3126 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3127 (le16toh(hdr->signature) >> 4) == 0x88e || 3128 (le16toh(hdr->signature) >> 4) == 0x92c) { 3129 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3130 device_xname(sc->sc_dev), __func__, 3131 le16toh(hdr->version), le16toh(hdr->subversion), 3132 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3133 ptr += sizeof(*hdr); 3134 len -= sizeof(*hdr); 3135 } 3136 3137 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3138 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3139 urtwn_r88e_fw_reset(sc); 3140 else 3141 urtwn_fw_reset(sc); 3142 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3143 } 3144 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3145 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3146 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3147 R92C_SYS_FUNC_EN_CPUEN); 3148 } 3149 3150 /* download enabled */ 3151 urtwn_write_1(sc, R92C_MCUFWDL, 3152 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3153 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3154 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3155 3156 /* Reset the FWDL checksum. */ 3157 urtwn_write_1(sc, R92C_MCUFWDL, 3158 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3159 3160 /* download firmware */ 3161 for (page = 0; len > 0; page++) { 3162 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3163 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3164 if (error != 0) { 3165 aprint_error_dev(sc->sc_dev, 3166 "could not load firmware page %d\n", page); 3167 goto fail; 3168 } 3169 ptr += mlen; 3170 len -= mlen; 3171 } 3172 3173 /* download disable */ 3174 urtwn_write_1(sc, R92C_MCUFWDL, 3175 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3176 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3177 3178 /* Wait for checksum report. */ 3179 for (ntries = 0; ntries < 1000; ntries++) { 3180 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3181 break; 3182 DELAY(5); 3183 } 3184 if (ntries == 1000) { 3185 aprint_error_dev(sc->sc_dev, 3186 "timeout waiting for checksum report\n"); 3187 error = ETIMEDOUT; 3188 goto fail; 3189 } 3190 3191 /* Wait for firmware readiness. */ 3192 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3193 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3194 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3195 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3196 urtwn_r88e_fw_reset(sc); 3197 for (ntries = 0; ntries < 1000; ntries++) { 3198 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3199 break; 3200 DELAY(5); 3201 } 3202 if (ntries == 1000) { 3203 aprint_error_dev(sc->sc_dev, 3204 "timeout waiting for firmware readiness\n"); 3205 error = ETIMEDOUT; 3206 goto fail; 3207 } 3208 fail: 3209 firmware_free(fw, fwlen); 3210 return error; 3211 } 3212 3213 static __inline int 3214 urtwn_dma_init(struct urtwn_softc *sc) 3215 { 3216 3217 return sc->sc_dma_init(sc); 3218 } 3219 3220 static int 3221 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3222 { 3223 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3224 uint32_t reg; 3225 int error; 3226 3227 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3228 3229 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3230 3231 /* Initialize LLT table. */ 3232 error = urtwn_llt_init(sc); 3233 if (error != 0) 3234 return error; 3235 3236 /* Get Tx queues to USB endpoints mapping. */ 3237 hashq = hasnq = haslq = 0; 3238 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3239 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3240 device_xname(sc->sc_dev), __func__, reg)); 3241 if (MS(reg, R92C_USB_EP_HQ) != 0) 3242 hashq = 1; 3243 if (MS(reg, R92C_USB_EP_NQ) != 0) 3244 hasnq = 1; 3245 if (MS(reg, R92C_USB_EP_LQ) != 0) 3246 haslq = 1; 3247 nqueues = hashq + hasnq + haslq; 3248 if (nqueues == 0) 3249 return EIO; 3250 /* Get the number of pages for each queue. */ 3251 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3252 /* The remaining pages are assigned to the high priority queue. */ 3253 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3254 3255 /* Set number of pages for normal priority queue. */ 3256 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3257 urtwn_write_4(sc, R92C_RQPN, 3258 /* Set number of pages for public queue. */ 3259 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3260 /* Set number of pages for high priority queue. */ 3261 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3262 /* Set number of pages for low priority queue. */ 3263 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3264 /* Load values. */ 3265 R92C_RQPN_LD); 3266 3267 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3268 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3269 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3270 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3271 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3272 3273 /* Set queue to USB pipe mapping. */ 3274 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3275 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3276 if (nqueues == 1) { 3277 if (hashq) { 3278 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3279 } else if (hasnq) { 3280 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3281 } else { 3282 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3283 } 3284 } else if (nqueues == 2) { 3285 /* All 2-endpoints configs have a high priority queue. */ 3286 if (!hashq) { 3287 return EIO; 3288 } 3289 if (hasnq) { 3290 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3291 } else { 3292 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3293 } 3294 } else { 3295 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3296 } 3297 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3298 3299 /* Set Tx/Rx transfer page boundary. */ 3300 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3301 3302 /* Set Tx/Rx transfer page size. */ 3303 urtwn_write_1(sc, R92C_PBP, 3304 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3305 return 0; 3306 } 3307 3308 static int 3309 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3310 { 3311 usb_interface_descriptor_t *id; 3312 uint32_t reg; 3313 int nqueues; 3314 int error; 3315 3316 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3317 3318 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3319 3320 /* Initialize LLT table. */ 3321 error = urtwn_llt_init(sc); 3322 if (error != 0) 3323 return error; 3324 3325 /* Get Tx queues to USB endpoints mapping. */ 3326 id = usbd_get_interface_descriptor(sc->sc_iface); 3327 nqueues = id->bNumEndpoints - 1; 3328 if (nqueues == 0) 3329 return EIO; 3330 3331 /* Set number of pages for normal priority queue. */ 3332 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3333 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3334 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3335 3336 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3337 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3338 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3339 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3340 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3341 3342 /* Set queue to USB pipe mapping. */ 3343 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3344 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3345 if (nqueues == 1) 3346 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3347 else if (nqueues == 2) 3348 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3349 else 3350 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3351 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3352 3353 /* Set Tx/Rx transfer page boundary. */ 3354 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3355 3356 /* Set Tx/Rx transfer page size. */ 3357 urtwn_write_1(sc, R92C_PBP, 3358 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3359 3360 return 0; 3361 } 3362 3363 static void 3364 urtwn_mac_init(struct urtwn_softc *sc) 3365 { 3366 size_t i; 3367 3368 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3369 3370 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3371 3372 /* Write MAC initialization values. */ 3373 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3374 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3375 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3376 rtl8188eu_mac[i].val); 3377 } else { 3378 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3379 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3380 rtl8192cu_mac[i].val); 3381 } 3382 } 3383 3384 static void 3385 urtwn_bb_init(struct urtwn_softc *sc) 3386 { 3387 const struct urtwn_bb_prog *prog; 3388 uint32_t reg; 3389 uint8_t crystalcap; 3390 size_t i; 3391 3392 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3393 3394 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3395 3396 /* Enable BB and RF. */ 3397 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3398 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3399 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3400 R92C_SYS_FUNC_EN_DIO_RF); 3401 3402 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3403 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3404 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3405 } 3406 3407 urtwn_write_1(sc, R92C_RF_CTRL, 3408 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3409 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3410 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3411 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3412 3413 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3414 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3415 urtwn_write_1(sc, 0x15, 0xe9); 3416 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3417 } 3418 3419 /* Select BB programming based on board type. */ 3420 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3421 prog = &rtl8188eu_bb_prog; 3422 else if (!(sc->chip & URTWN_CHIP_92C)) { 3423 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3424 prog = &rtl8188ce_bb_prog; 3425 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3426 prog = &rtl8188ru_bb_prog; 3427 } else { 3428 prog = &rtl8188cu_bb_prog; 3429 } 3430 } else { 3431 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3432 prog = &rtl8192ce_bb_prog; 3433 } else { 3434 prog = &rtl8192cu_bb_prog; 3435 } 3436 } 3437 /* Write BB initialization values. */ 3438 for (i = 0; i < prog->count; i++) { 3439 /* additional delay depend on registers */ 3440 switch (prog->regs[i]) { 3441 case 0xfe: 3442 usbd_delay_ms(sc->sc_udev, 50); 3443 break; 3444 case 0xfd: 3445 usbd_delay_ms(sc->sc_udev, 5); 3446 break; 3447 case 0xfc: 3448 usbd_delay_ms(sc->sc_udev, 1); 3449 break; 3450 case 0xfb: 3451 DELAY(50); 3452 break; 3453 case 0xfa: 3454 DELAY(5); 3455 break; 3456 case 0xf9: 3457 DELAY(1); 3458 break; 3459 } 3460 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3461 DELAY(1); 3462 } 3463 3464 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3465 /* 8192C 1T only configuration. */ 3466 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3467 reg = (reg & ~0x00000003) | 0x2; 3468 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3469 3470 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3471 reg = (reg & ~0x00300033) | 0x00200022; 3472 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3473 3474 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3475 reg = (reg & ~0xff000000) | (0x45 << 24); 3476 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3477 3478 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3479 reg = (reg & ~0x000000ff) | 0x23; 3480 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3481 3482 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3483 reg = (reg & ~0x00000030) | (1 << 4); 3484 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3485 3486 reg = urtwn_bb_read(sc, 0xe74); 3487 reg = (reg & ~0x0c000000) | (2 << 26); 3488 urtwn_bb_write(sc, 0xe74, reg); 3489 reg = urtwn_bb_read(sc, 0xe78); 3490 reg = (reg & ~0x0c000000) | (2 << 26); 3491 urtwn_bb_write(sc, 0xe78, reg); 3492 reg = urtwn_bb_read(sc, 0xe7c); 3493 reg = (reg & ~0x0c000000) | (2 << 26); 3494 urtwn_bb_write(sc, 0xe7c, reg); 3495 reg = urtwn_bb_read(sc, 0xe80); 3496 reg = (reg & ~0x0c000000) | (2 << 26); 3497 urtwn_bb_write(sc, 0xe80, reg); 3498 reg = urtwn_bb_read(sc, 0xe88); 3499 reg = (reg & ~0x0c000000) | (2 << 26); 3500 urtwn_bb_write(sc, 0xe88, reg); 3501 } 3502 3503 /* Write AGC values. */ 3504 for (i = 0; i < prog->agccount; i++) { 3505 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3506 DELAY(1); 3507 } 3508 3509 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3510 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3511 DELAY(1); 3512 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3513 DELAY(1); 3514 3515 crystalcap = sc->r88e_rom[0xb9]; 3516 if (crystalcap == 0xff) 3517 crystalcap = 0x20; 3518 crystalcap &= 0x3f; 3519 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3520 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3521 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3522 crystalcap | crystalcap << 6)); 3523 } else { 3524 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3525 R92C_HSSI_PARAM2_CCK_HIPWR) { 3526 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3527 } 3528 } 3529 } 3530 3531 static void 3532 urtwn_rf_init(struct urtwn_softc *sc) 3533 { 3534 const struct urtwn_rf_prog *prog; 3535 uint32_t reg, mask, saved; 3536 size_t i, j, idx; 3537 3538 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3539 3540 /* Select RF programming based on board type. */ 3541 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3542 prog = rtl8188eu_rf_prog; 3543 else if (!(sc->chip & URTWN_CHIP_92C)) { 3544 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3545 prog = rtl8188ce_rf_prog; 3546 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3547 prog = rtl8188ru_rf_prog; 3548 } else { 3549 prog = rtl8188cu_rf_prog; 3550 } 3551 } else { 3552 prog = rtl8192ce_rf_prog; 3553 } 3554 3555 for (i = 0; i < sc->nrxchains; i++) { 3556 /* Save RF_ENV control type. */ 3557 idx = i / 2; 3558 mask = 0xffffU << ((i % 2) * 16); 3559 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3560 3561 /* Set RF_ENV enable. */ 3562 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3563 reg |= 0x100000; 3564 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3565 DELAY(1); 3566 3567 /* Set RF_ENV output high. */ 3568 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3569 reg |= 0x10; 3570 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3571 DELAY(1); 3572 3573 /* Set address and data lengths of RF registers. */ 3574 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3575 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3576 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3577 DELAY(1); 3578 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3579 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3580 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3581 DELAY(1); 3582 3583 /* Write RF initialization values for this chain. */ 3584 for (j = 0; j < prog[i].count; j++) { 3585 if (prog[i].regs[j] >= 0xf9 && 3586 prog[i].regs[j] <= 0xfe) { 3587 /* 3588 * These are fake RF registers offsets that 3589 * indicate a delay is required. 3590 */ 3591 usbd_delay_ms(sc->sc_udev, 50); 3592 continue; 3593 } 3594 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3595 DELAY(1); 3596 } 3597 3598 /* Restore RF_ENV control type. */ 3599 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3600 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3601 } 3602 3603 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3604 URTWN_CHIP_UMC_A_CUT) { 3605 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3606 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3607 } 3608 3609 /* Cache RF register CHNLBW. */ 3610 for (i = 0; i < 2; i++) { 3611 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3612 } 3613 } 3614 3615 static void 3616 urtwn_cam_init(struct urtwn_softc *sc) 3617 { 3618 uint32_t content, command; 3619 uint8_t idx; 3620 size_t i; 3621 3622 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3623 3624 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3625 3626 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3627 content = (idx & 3) 3628 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3629 | R92C_CAM_VALID; 3630 3631 command = R92C_CAMCMD_POLLING 3632 | R92C_CAMCMD_WRITE 3633 | R92C_CAM_CTL0(idx); 3634 3635 urtwn_write_4(sc, R92C_CAMWRITE, content); 3636 urtwn_write_4(sc, R92C_CAMCMD, command); 3637 } 3638 3639 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3640 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3641 if (i == 0) { 3642 content = (idx & 3) 3643 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3644 | R92C_CAM_VALID; 3645 } else { 3646 content = 0; 3647 } 3648 3649 command = R92C_CAMCMD_POLLING 3650 | R92C_CAMCMD_WRITE 3651 | R92C_CAM_CTL0(idx) 3652 | i; 3653 3654 urtwn_write_4(sc, R92C_CAMWRITE, content); 3655 urtwn_write_4(sc, R92C_CAMCMD, command); 3656 } 3657 } 3658 3659 /* Invalidate all CAM entries. */ 3660 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3661 } 3662 3663 static void 3664 urtwn_pa_bias_init(struct urtwn_softc *sc) 3665 { 3666 uint8_t reg; 3667 size_t i; 3668 3669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3670 3671 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3672 3673 for (i = 0; i < sc->nrxchains; i++) { 3674 if (sc->pa_setting & (1U << i)) 3675 continue; 3676 3677 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3678 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3679 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3680 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3681 } 3682 if (!(sc->pa_setting & 0x10)) { 3683 reg = urtwn_read_1(sc, 0x16); 3684 reg = (reg & ~0xf0) | 0x90; 3685 urtwn_write_1(sc, 0x16, reg); 3686 } 3687 } 3688 3689 static void 3690 urtwn_rxfilter_init(struct urtwn_softc *sc) 3691 { 3692 3693 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3694 3695 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3696 3697 /* Initialize Rx filter. */ 3698 /* TODO: use better filter for monitor mode. */ 3699 urtwn_write_4(sc, R92C_RCR, 3700 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3701 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3702 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3703 /* Accept all multicast frames. */ 3704 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3705 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3706 /* Accept all management frames. */ 3707 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3708 /* Reject all control frames. */ 3709 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3710 /* Accept all data frames. */ 3711 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3712 } 3713 3714 static void 3715 urtwn_edca_init(struct urtwn_softc *sc) 3716 { 3717 3718 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3719 3720 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3721 3722 /* set spec SIFS (used in NAV) */ 3723 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3724 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3725 3726 /* set SIFS CCK/OFDM */ 3727 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3728 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3729 3730 /* TXOP */ 3731 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3732 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3733 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3734 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3735 } 3736 3737 static void 3738 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3739 uint16_t power[URTWN_RIDX_COUNT]) 3740 { 3741 uint32_t reg; 3742 3743 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3744 __func__, chain)); 3745 3746 /* Write per-CCK rate Tx power. */ 3747 if (chain == 0) { 3748 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3749 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3750 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3751 3752 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3753 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3754 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3755 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3756 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3757 } else { 3758 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3759 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3760 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3761 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3762 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3763 3764 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3765 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3766 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3767 } 3768 /* Write per-OFDM rate Tx power. */ 3769 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3770 SM(R92C_TXAGC_RATE06, power[ 4]) | 3771 SM(R92C_TXAGC_RATE09, power[ 5]) | 3772 SM(R92C_TXAGC_RATE12, power[ 6]) | 3773 SM(R92C_TXAGC_RATE18, power[ 7])); 3774 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3775 SM(R92C_TXAGC_RATE24, power[ 8]) | 3776 SM(R92C_TXAGC_RATE36, power[ 9]) | 3777 SM(R92C_TXAGC_RATE48, power[10]) | 3778 SM(R92C_TXAGC_RATE54, power[11])); 3779 /* Write per-MCS Tx power. */ 3780 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3781 SM(R92C_TXAGC_MCS00, power[12]) | 3782 SM(R92C_TXAGC_MCS01, power[13]) | 3783 SM(R92C_TXAGC_MCS02, power[14]) | 3784 SM(R92C_TXAGC_MCS03, power[15])); 3785 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3786 SM(R92C_TXAGC_MCS04, power[16]) | 3787 SM(R92C_TXAGC_MCS05, power[17]) | 3788 SM(R92C_TXAGC_MCS06, power[18]) | 3789 SM(R92C_TXAGC_MCS07, power[19])); 3790 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3791 SM(R92C_TXAGC_MCS08, power[20]) | 3792 SM(R92C_TXAGC_MCS09, power[21]) | 3793 SM(R92C_TXAGC_MCS10, power[22]) | 3794 SM(R92C_TXAGC_MCS11, power[23])); 3795 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3796 SM(R92C_TXAGC_MCS12, power[24]) | 3797 SM(R92C_TXAGC_MCS13, power[25]) | 3798 SM(R92C_TXAGC_MCS14, power[26]) | 3799 SM(R92C_TXAGC_MCS15, power[27])); 3800 } 3801 3802 static void 3803 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 3804 uint16_t power[URTWN_RIDX_COUNT]) 3805 { 3806 struct r92c_rom *rom = &sc->rom; 3807 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3808 const struct urtwn_txpwr *base; 3809 int ridx, group; 3810 3811 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3812 device_xname(sc->sc_dev), __func__, chain, chan)); 3813 3814 /* Determine channel group. */ 3815 if (chan <= 3) { 3816 group = 0; 3817 } else if (chan <= 9) { 3818 group = 1; 3819 } else { 3820 group = 2; 3821 } 3822 3823 /* Get original Tx power based on board type and RF chain. */ 3824 if (!(sc->chip & URTWN_CHIP_92C)) { 3825 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3826 base = &rtl8188ru_txagc[chain]; 3827 } else { 3828 base = &rtl8192cu_txagc[chain]; 3829 } 3830 } else { 3831 base = &rtl8192cu_txagc[chain]; 3832 } 3833 3834 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3835 if (sc->regulatory == 0) { 3836 for (ridx = 0; ridx <= 3; ridx++) { 3837 power[ridx] = base->pwr[0][ridx]; 3838 } 3839 } 3840 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3841 if (sc->regulatory == 3) { 3842 power[ridx] = base->pwr[0][ridx]; 3843 /* Apply vendor limits. */ 3844 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3845 maxpow = rom->ht40_max_pwr[group]; 3846 } else { 3847 maxpow = rom->ht20_max_pwr[group]; 3848 } 3849 maxpow = (maxpow >> (chain * 4)) & 0xf; 3850 if (power[ridx] > maxpow) { 3851 power[ridx] = maxpow; 3852 } 3853 } else if (sc->regulatory == 1) { 3854 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3855 power[ridx] = base->pwr[group][ridx]; 3856 } 3857 } else if (sc->regulatory != 2) { 3858 power[ridx] = base->pwr[0][ridx]; 3859 } 3860 } 3861 3862 /* Compute per-CCK rate Tx power. */ 3863 cckpow = rom->cck_tx_pwr[chain][group]; 3864 for (ridx = 0; ridx <= 3; ridx++) { 3865 power[ridx] += cckpow; 3866 if (power[ridx] > R92C_MAX_TX_PWR) { 3867 power[ridx] = R92C_MAX_TX_PWR; 3868 } 3869 } 3870 3871 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3872 if (sc->ntxchains > 1) { 3873 /* Apply reduction for 2 spatial streams. */ 3874 diff = rom->ht40_2s_tx_pwr_diff[group]; 3875 diff = (diff >> (chain * 4)) & 0xf; 3876 htpow = (htpow > diff) ? htpow - diff : 0; 3877 } 3878 3879 /* Compute per-OFDM rate Tx power. */ 3880 diff = rom->ofdm_tx_pwr_diff[group]; 3881 diff = (diff >> (chain * 4)) & 0xf; 3882 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3883 for (ridx = 4; ridx <= 11; ridx++) { 3884 power[ridx] += ofdmpow; 3885 if (power[ridx] > R92C_MAX_TX_PWR) { 3886 power[ridx] = R92C_MAX_TX_PWR; 3887 } 3888 } 3889 3890 /* Compute per-MCS Tx power. */ 3891 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3892 diff = rom->ht20_tx_pwr_diff[group]; 3893 diff = (diff >> (chain * 4)) & 0xf; 3894 htpow += diff; /* HT40->HT20 correction. */ 3895 } 3896 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3897 power[ridx] += htpow; 3898 if (power[ridx] > R92C_MAX_TX_PWR) { 3899 power[ridx] = R92C_MAX_TX_PWR; 3900 } 3901 } 3902 #ifdef URTWN_DEBUG 3903 if (urtwn_debug & DBG_RF) { 3904 /* Dump per-rate Tx power values. */ 3905 printf("%s: %s: Tx power for chain %zd:\n", 3906 device_xname(sc->sc_dev), __func__, chain); 3907 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3908 printf("%s: %s: Rate %d = %u\n", 3909 device_xname(sc->sc_dev), __func__, ridx, 3910 power[ridx]); 3911 } 3912 } 3913 #endif 3914 } 3915 3916 void 3917 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 3918 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 3919 { 3920 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3921 const struct urtwn_r88e_txpwr *base; 3922 int ridx, group; 3923 3924 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3925 device_xname(sc->sc_dev), __func__, chain, chan)); 3926 3927 /* Determine channel group. */ 3928 if (chan <= 2) 3929 group = 0; 3930 else if (chan <= 5) 3931 group = 1; 3932 else if (chan <= 8) 3933 group = 2; 3934 else if (chan <= 11) 3935 group = 3; 3936 else if (chan <= 13) 3937 group = 4; 3938 else 3939 group = 5; 3940 3941 /* Get original Tx power based on board type and RF chain. */ 3942 base = &rtl8188eu_txagc[chain]; 3943 3944 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3945 if (sc->regulatory == 0) { 3946 for (ridx = 0; ridx <= 3; ridx++) 3947 power[ridx] = base->pwr[0][ridx]; 3948 } 3949 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3950 if (sc->regulatory == 3) 3951 power[ridx] = base->pwr[0][ridx]; 3952 else if (sc->regulatory == 1) { 3953 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 3954 power[ridx] = base->pwr[group][ridx]; 3955 } else if (sc->regulatory != 2) 3956 power[ridx] = base->pwr[0][ridx]; 3957 } 3958 3959 /* Compute per-CCK rate Tx power. */ 3960 cckpow = sc->cck_tx_pwr[group]; 3961 for (ridx = 0; ridx <= 3; ridx++) { 3962 power[ridx] += cckpow; 3963 if (power[ridx] > R92C_MAX_TX_PWR) 3964 power[ridx] = R92C_MAX_TX_PWR; 3965 } 3966 3967 htpow = sc->ht40_tx_pwr[group]; 3968 3969 /* Compute per-OFDM rate Tx power. */ 3970 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3971 for (ridx = 4; ridx <= 11; ridx++) { 3972 power[ridx] += ofdmpow; 3973 if (power[ridx] > R92C_MAX_TX_PWR) 3974 power[ridx] = R92C_MAX_TX_PWR; 3975 } 3976 3977 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3978 for (ridx = 12; ridx <= 27; ridx++) { 3979 power[ridx] += bw20pow; 3980 if (power[ridx] > R92C_MAX_TX_PWR) 3981 power[ridx] = R92C_MAX_TX_PWR; 3982 } 3983 } 3984 3985 static void 3986 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3987 { 3988 uint16_t power[URTWN_RIDX_COUNT]; 3989 size_t i; 3990 3991 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3992 3993 for (i = 0; i < sc->ntxchains; i++) { 3994 /* Compute per-rate Tx power values. */ 3995 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3996 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 3997 else 3998 urtwn_get_txpower(sc, i, chan, ht40m, power); 3999 /* Write per-rate Tx power values to hardware. */ 4000 urtwn_write_txpower(sc, i, power); 4001 } 4002 } 4003 4004 static void 4005 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4006 { 4007 struct ieee80211com *ic = &sc->sc_ic; 4008 u_int chan; 4009 size_t i; 4010 4011 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4012 4013 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4014 __func__, chan)); 4015 4016 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4017 4018 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4019 chan += 2; 4020 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4021 chan -= 2; 4022 } 4023 4024 /* Set Tx power for this new channel. */ 4025 urtwn_set_txpower(sc, chan, ht40m); 4026 4027 for (i = 0; i < sc->nrxchains; i++) { 4028 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4029 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4030 } 4031 4032 if (ht40m) { 4033 /* Is secondary channel below or above primary? */ 4034 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4035 uint32_t reg; 4036 4037 urtwn_write_1(sc, R92C_BWOPMODE, 4038 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4039 4040 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4041 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4042 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4043 4044 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4045 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4046 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4047 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4048 4049 /* Set CCK side band. */ 4050 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4051 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4052 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4053 4054 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4055 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4056 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4057 4058 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4059 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4060 ~R92C_FPGA0_ANAPARAM2_CBW20); 4061 4062 reg = urtwn_bb_read(sc, 0x818); 4063 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4064 urtwn_bb_write(sc, 0x818, reg); 4065 4066 /* Select 40MHz bandwidth. */ 4067 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4068 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4069 } else { 4070 urtwn_write_1(sc, R92C_BWOPMODE, 4071 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4072 4073 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4074 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4075 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4076 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4077 4078 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4079 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4080 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4081 R92C_FPGA0_ANAPARAM2_CBW20); 4082 } 4083 4084 /* Select 20MHz bandwidth. */ 4085 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4086 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4087 (ISSET(sc->chip, URTWN_CHIP_88E) ? 4088 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4089 } 4090 } 4091 4092 static void 4093 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4094 { 4095 4096 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4097 __func__, inited)); 4098 4099 /* TODO */ 4100 } 4101 4102 static void 4103 urtwn_lc_calib(struct urtwn_softc *sc) 4104 { 4105 uint32_t rf_ac[2]; 4106 uint8_t txmode; 4107 size_t i; 4108 4109 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4110 4111 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4112 4113 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4114 if ((txmode & 0x70) != 0) { 4115 /* Disable all continuous Tx. */ 4116 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4117 4118 /* Set RF mode to standby mode. */ 4119 for (i = 0; i < sc->nrxchains; i++) { 4120 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4121 urtwn_rf_write(sc, i, R92C_RF_AC, 4122 RW(rf_ac[i], R92C_RF_AC_MODE, 4123 R92C_RF_AC_MODE_STANDBY)); 4124 } 4125 } else { 4126 /* Block all Tx queues. */ 4127 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4128 } 4129 /* Start calibration. */ 4130 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4131 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4132 4133 /* Give calibration the time to complete. */ 4134 usbd_delay_ms(sc->sc_udev, 100); 4135 4136 /* Restore configuration. */ 4137 if ((txmode & 0x70) != 0) { 4138 /* Restore Tx mode. */ 4139 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4140 /* Restore RF mode. */ 4141 for (i = 0; i < sc->nrxchains; i++) { 4142 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4143 } 4144 } else { 4145 /* Unblock all Tx queues. */ 4146 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4147 } 4148 } 4149 4150 static void 4151 urtwn_temp_calib(struct urtwn_softc *sc) 4152 { 4153 int temp; 4154 4155 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4156 4157 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4158 4159 if (sc->thcal_state == 0) { 4160 /* Start measuring temperature. */ 4161 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4162 device_xname(sc->sc_dev), __func__)); 4163 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 4164 sc->thcal_state = 1; 4165 return; 4166 } 4167 sc->thcal_state = 0; 4168 4169 /* Read measured temperature. */ 4170 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4171 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4172 __func__, temp)); 4173 if (temp == 0) /* Read failed, skip. */ 4174 return; 4175 4176 /* 4177 * Redo LC calibration if temperature changed significantly since 4178 * last calibration. 4179 */ 4180 if (sc->thcal_lctemp == 0) { 4181 /* First LC calibration is performed in urtwn_init(). */ 4182 sc->thcal_lctemp = temp; 4183 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4184 DPRINTFN(DBG_RF, 4185 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4186 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4187 temp)); 4188 urtwn_lc_calib(sc); 4189 /* Record temperature of last LC calibration. */ 4190 sc->thcal_lctemp = temp; 4191 } 4192 } 4193 4194 static int 4195 urtwn_init(struct ifnet *ifp) 4196 { 4197 struct urtwn_softc *sc = ifp->if_softc; 4198 struct ieee80211com *ic = &sc->sc_ic; 4199 struct urtwn_rx_data *data; 4200 uint32_t reg; 4201 size_t i; 4202 int error; 4203 4204 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4205 4206 urtwn_stop(ifp, 0); 4207 4208 mutex_enter(&sc->sc_write_mtx); 4209 4210 mutex_enter(&sc->sc_task_mtx); 4211 /* Init host async commands ring. */ 4212 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4213 mutex_exit(&sc->sc_task_mtx); 4214 4215 mutex_enter(&sc->sc_fwcmd_mtx); 4216 /* Init firmware commands ring. */ 4217 sc->fwcur = 0; 4218 mutex_exit(&sc->sc_fwcmd_mtx); 4219 4220 /* Allocate Tx/Rx buffers. */ 4221 error = urtwn_alloc_rx_list(sc); 4222 if (error != 0) { 4223 aprint_error_dev(sc->sc_dev, 4224 "could not allocate Rx buffers\n"); 4225 goto fail; 4226 } 4227 error = urtwn_alloc_tx_list(sc); 4228 if (error != 0) { 4229 aprint_error_dev(sc->sc_dev, 4230 "could not allocate Tx buffers\n"); 4231 goto fail; 4232 } 4233 4234 /* Power on adapter. */ 4235 error = urtwn_power_on(sc); 4236 if (error != 0) 4237 goto fail; 4238 4239 /* Initialize DMA. */ 4240 error = urtwn_dma_init(sc); 4241 if (error != 0) 4242 goto fail; 4243 4244 /* Set info size in Rx descriptors (in 64-bit words). */ 4245 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4246 4247 /* Init interrupts. */ 4248 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4249 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4250 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4251 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4252 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4253 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4254 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4255 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4256 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4257 } else { 4258 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4259 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4260 } 4261 4262 /* Set MAC address. */ 4263 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4264 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4265 4266 /* Set initial network type. */ 4267 reg = urtwn_read_4(sc, R92C_CR); 4268 switch (ic->ic_opmode) { 4269 case IEEE80211_M_STA: 4270 default: 4271 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4272 break; 4273 4274 case IEEE80211_M_IBSS: 4275 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4276 break; 4277 } 4278 urtwn_write_4(sc, R92C_CR, reg); 4279 4280 /* Set response rate */ 4281 reg = urtwn_read_4(sc, R92C_RRSR); 4282 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4283 urtwn_write_4(sc, R92C_RRSR, reg); 4284 4285 /* SIFS (used in NAV) */ 4286 urtwn_write_2(sc, R92C_SPEC_SIFS, 4287 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4288 4289 /* Set short/long retry limits. */ 4290 urtwn_write_2(sc, R92C_RL, 4291 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4292 4293 /* Initialize EDCA parameters. */ 4294 urtwn_edca_init(sc); 4295 4296 /* Setup rate fallback. */ 4297 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4298 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4299 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4300 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4301 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4302 } 4303 4304 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4305 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4306 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4307 /* Set ACK timeout. */ 4308 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4309 4310 /* Setup USB aggregation. */ 4311 /* Tx */ 4312 reg = urtwn_read_4(sc, R92C_TDECTRL); 4313 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4314 urtwn_write_4(sc, R92C_TDECTRL, reg); 4315 /* Rx */ 4316 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4317 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4318 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4319 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4320 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4321 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4322 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4323 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4324 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4325 else 4326 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4327 4328 /* Initialize beacon parameters. */ 4329 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4330 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4331 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4332 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4333 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4334 4335 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4336 /* Setup AMPDU aggregation. */ 4337 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4338 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4339 urtwn_write_2(sc, 0x4ca, 0x0708); 4340 4341 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4342 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4343 } 4344 4345 /* Load 8051 microcode. */ 4346 error = urtwn_load_firmware(sc); 4347 if (error != 0) 4348 goto fail; 4349 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4350 4351 /* Initialize MAC/BB/RF blocks. */ 4352 /* 4353 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4354 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4355 * XXX: This setting should be removed from rtl8192cu_mac[]. 4356 */ 4357 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4358 urtwn_rxfilter_init(sc); // reset R92C_RCR 4359 urtwn_bb_init(sc); 4360 urtwn_rf_init(sc); 4361 4362 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4363 urtwn_write_2(sc, R92C_CR, 4364 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4365 R92C_CR_MACRXEN); 4366 } 4367 4368 /* Turn CCK and OFDM blocks on. */ 4369 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4370 reg |= R92C_RFMOD_CCK_EN; 4371 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4372 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4373 reg |= R92C_RFMOD_OFDM_EN; 4374 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4375 4376 /* Clear per-station keys table. */ 4377 urtwn_cam_init(sc); 4378 4379 /* Enable hardware sequence numbering. */ 4380 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4381 4382 /* Perform LO and IQ calibrations. */ 4383 urtwn_iq_calib(sc, sc->iqk_inited); 4384 sc->iqk_inited = true; 4385 4386 /* Perform LC calibration. */ 4387 urtwn_lc_calib(sc); 4388 4389 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4390 /* Fix USB interference issue. */ 4391 urtwn_write_1(sc, 0xfe40, 0xe0); 4392 urtwn_write_1(sc, 0xfe41, 0x8d); 4393 urtwn_write_1(sc, 0xfe42, 0x80); 4394 urtwn_write_4(sc, 0x20c, 0xfd0320); 4395 4396 urtwn_pa_bias_init(sc); 4397 } 4398 4399 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 4400 /* 1T1R */ 4401 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4402 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4403 } 4404 4405 /* Initialize GPIO setting. */ 4406 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4407 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4408 4409 /* Fix for lower temperature. */ 4410 if (!ISSET(sc->chip, URTWN_CHIP_88E)) 4411 urtwn_write_1(sc, 0x15, 0xe9); 4412 4413 /* Set default channel. */ 4414 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4415 4416 /* Queue Rx xfers. */ 4417 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4418 data = &sc->rx_data[i]; 4419 usbd_setup_xfer(data->xfer, data, data->buf, URTWN_RXBUFSZ, 4420 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 4421 error = usbd_transfer(data->xfer); 4422 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4423 error != USBD_IN_PROGRESS)) 4424 goto fail; 4425 } 4426 4427 /* We're ready to go. */ 4428 ifp->if_flags &= ~IFF_OACTIVE; 4429 ifp->if_flags |= IFF_RUNNING; 4430 4431 mutex_exit(&sc->sc_write_mtx); 4432 4433 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4434 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4435 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4436 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4437 urtwn_wait_async(sc); 4438 4439 return 0; 4440 4441 fail: 4442 mutex_exit(&sc->sc_write_mtx); 4443 4444 urtwn_stop(ifp, 1); 4445 return error; 4446 } 4447 4448 static void 4449 urtwn_stop(struct ifnet *ifp, int disable) 4450 { 4451 struct urtwn_softc *sc = ifp->if_softc; 4452 struct ieee80211com *ic = &sc->sc_ic; 4453 size_t i; 4454 int s; 4455 4456 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4457 4458 s = splusb(); 4459 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4460 urtwn_wait_async(sc); 4461 splx(s); 4462 4463 sc->tx_timer = 0; 4464 ifp->if_timer = 0; 4465 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4466 4467 callout_stop(&sc->sc_scan_to); 4468 callout_stop(&sc->sc_calib_to); 4469 4470 /* Abort Tx. */ 4471 for (i = 0; i < R92C_MAX_EPOUT; i++) { 4472 if (sc->tx_pipe[i] != NULL) 4473 usbd_abort_pipe(sc->tx_pipe[i]); 4474 } 4475 4476 /* Stop Rx pipe. */ 4477 usbd_abort_pipe(sc->rx_pipe); 4478 4479 /* Free Tx/Rx buffers. */ 4480 urtwn_free_tx_list(sc); 4481 urtwn_free_rx_list(sc); 4482 4483 if (disable) 4484 urtwn_chip_stop(sc); 4485 } 4486 4487 static int 4488 urtwn_reset(struct ifnet *ifp) 4489 { 4490 struct urtwn_softc *sc = ifp->if_softc; 4491 struct ieee80211com *ic = &sc->sc_ic; 4492 4493 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4494 return ENETRESET; 4495 4496 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4497 4498 return 0; 4499 } 4500 4501 static void 4502 urtwn_chip_stop(struct urtwn_softc *sc) 4503 { 4504 uint32_t reg; 4505 bool disabled = true; 4506 4507 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4508 4509 mutex_enter(&sc->sc_write_mtx); 4510 4511 /* 4512 * RF Off Sequence 4513 */ 4514 /* Pause MAC TX queue */ 4515 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4516 4517 /* Disable RF */ 4518 urtwn_rf_write(sc, 0, 0, 0); 4519 4520 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4521 4522 /* Reset BB state machine */ 4523 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4524 R92C_SYS_FUNC_EN_USBD | 4525 R92C_SYS_FUNC_EN_USBA | 4526 R92C_SYS_FUNC_EN_BB_GLB_RST); 4527 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4528 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4529 4530 /* 4531 * Reset digital sequence 4532 */ 4533 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4534 /* Reset MCU ready status */ 4535 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4536 /* If firmware in ram code, do reset */ 4537 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4538 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4539 urtwn_r88e_fw_reset(sc); 4540 else 4541 urtwn_fw_reset(sc); 4542 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 4543 } 4544 } 4545 4546 /* Reset MAC and Enable 8051 */ 4547 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 4548 4549 /* Reset MCU ready status */ 4550 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4551 4552 if (disabled) { 4553 /* Disable MAC clock */ 4554 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4555 /* Disable AFE PLL */ 4556 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 4557 /* Gated AFE DIG_CLOCK */ 4558 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 4559 /* Isolated digital to PON */ 4560 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 4561 } 4562 4563 /* 4564 * Pull GPIO PIN to balance level and LED control 4565 */ 4566 /* 1. Disable GPIO[7:0] */ 4567 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 4568 4569 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 4570 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 4571 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 4572 4573 /* Disable GPIO[10:8] */ 4574 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 4575 4576 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 4577 reg |= (((reg & 0x000f) << 4) | 0x0780); 4578 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 4579 4580 /* Disable LED0 & 1 */ 4581 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 4582 4583 /* 4584 * Reset digital sequence 4585 */ 4586 if (disabled) { 4587 /* Disable ELDR clock */ 4588 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4589 /* Isolated ELDR to PON */ 4590 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 4591 } 4592 4593 /* 4594 * Disable analog sequence 4595 */ 4596 if (disabled) { 4597 /* Disable A15 power */ 4598 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 4599 /* Disable digital core power */ 4600 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 4601 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 4602 ~R92C_LDOV12D_CTRL_LDV12_EN); 4603 } 4604 4605 /* Enter PFM mode */ 4606 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 4607 4608 /* Set USB suspend */ 4609 urtwn_write_2(sc, R92C_APS_FSMCO, 4610 R92C_APS_FSMCO_APDM_HOST | 4611 R92C_APS_FSMCO_AFSM_HSUS | 4612 R92C_APS_FSMCO_PFM_ALDN); 4613 4614 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 4615 4616 mutex_exit(&sc->sc_write_mtx); 4617 } 4618 4619 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 4620 4621 #ifdef _MODULE 4622 #include "ioconf.c" 4623 #endif 4624 4625 static int 4626 if_urtwn_modcmd(modcmd_t cmd, void *aux) 4627 { 4628 int error = 0; 4629 4630 switch (cmd) { 4631 case MODULE_CMD_INIT: 4632 #ifdef _MODULE 4633 error = config_init_component(cfdriver_ioconf_urtwn, 4634 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4635 #endif 4636 return error; 4637 case MODULE_CMD_FINI: 4638 #ifdef _MODULE 4639 error = config_fini_component(cfdriver_ioconf_urtwn, 4640 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4641 #endif 4642 return error; 4643 default: 4644 return ENOTTY; 4645 } 4646 } 4647
Indexes created Fri Oct 03 02:09:57 GMT 2025