if_urtwn.c revision 1.45
1 /* $NetBSD: if_urtwn.c,v 1.45 2016/06/10 13:27:15 ozaki-r Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /*- 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.45 2016/06/10 13:27:15 ozaki-r Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_inet.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 /* 78 * The sc_write_mtx locking is to prevent sequences of writes from 79 * being intermingled with each other. I don't know if this is really 80 * needed. I have added it just to be on the safe side. 81 */ 82 83 #ifdef URTWN_DEBUG 84 #define DBG_INIT __BIT(0) 85 #define DBG_FN __BIT(1) 86 #define DBG_TX __BIT(2) 87 #define DBG_RX __BIT(3) 88 #define DBG_STM __BIT(4) 89 #define DBG_RF __BIT(5) 90 #define DBG_REG __BIT(6) 91 #define DBG_ALL 0xffffffffU 92 u_int urtwn_debug = 0; 93 #define DPRINTFN(n, s) \ 94 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 95 #else 96 #define DPRINTFN(n, s) 97 #endif 98 99 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 100 #define URTWN_RTL8188E_DEV(v,p) \ 101 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 102 static const struct urtwn_dev { 103 struct usb_devno dev; 104 uint32_t flags; 105 #define FLAG_RTL8188E __BIT(0) 106 } urtwn_devs[] = { 107 URTWN_DEV(ABOCOM, RTL8188CU_1), 108 URTWN_DEV(ABOCOM, RTL8188CU_2), 109 URTWN_DEV(ABOCOM, RTL8192CU), 110 URTWN_DEV(ASUSTEK, RTL8192CU), 111 URTWN_DEV(ASUSTEK, RTL8192CU_3), 112 URTWN_DEV(ASUSTEK, USBN10NANO), 113 URTWN_DEV(ASUSTEK, RTL8192CU_3), 114 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 115 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 116 URTWN_DEV(AZUREWAVE, RTL8188CU), 117 URTWN_DEV(BELKIN, F7D2102), 118 URTWN_DEV(BELKIN, RTL8188CU), 119 URTWN_DEV(BELKIN, RTL8188CUS), 120 URTWN_DEV(BELKIN, RTL8192CU), 121 URTWN_DEV(BELKIN, RTL8192CU_1), 122 URTWN_DEV(BELKIN, RTL8192CU_2), 123 URTWN_DEV(CHICONY, RTL8188CUS_1), 124 URTWN_DEV(CHICONY, RTL8188CUS_2), 125 URTWN_DEV(CHICONY, RTL8188CUS_3), 126 URTWN_DEV(CHICONY, RTL8188CUS_4), 127 URTWN_DEV(CHICONY, RTL8188CUS_5), 128 URTWN_DEV(CHICONY, RTL8188CUS_6), 129 URTWN_DEV(COMPARE, RTL8192CU), 130 URTWN_DEV(COREGA, RTL8192CU), 131 URTWN_DEV(DLINK, DWA131B), 132 URTWN_DEV(DLINK, RTL8188CU), 133 URTWN_DEV(DLINK, RTL8192CU_1), 134 URTWN_DEV(DLINK, RTL8192CU_2), 135 URTWN_DEV(DLINK, RTL8192CU_3), 136 URTWN_DEV(DLINK, RTL8192CU_4), 137 URTWN_DEV(EDIMAX, RTL8188CU), 138 URTWN_DEV(EDIMAX, RTL8192CU), 139 URTWN_DEV(FEIXUN, RTL8188CU), 140 URTWN_DEV(FEIXUN, RTL8192CU), 141 URTWN_DEV(GUILLEMOT, HWNUP150), 142 URTWN_DEV(GUILLEMOT, RTL8192CU), 143 URTWN_DEV(HAWKING, RTL8192CU), 144 URTWN_DEV(HAWKING, RTL8192CU_2), 145 URTWN_DEV(HP3, RTL8188CU), 146 URTWN_DEV(IODATA, WNG150UM), 147 URTWN_DEV(IODATA, RTL8192CU), 148 URTWN_DEV(NETGEAR, WNA1000M), 149 URTWN_DEV(NETGEAR, RTL8192CU), 150 URTWN_DEV(NETGEAR4, RTL8188CU), 151 URTWN_DEV(NOVATECH, RTL8188CU), 152 URTWN_DEV(PLANEX2, RTL8188CU_1), 153 URTWN_DEV(PLANEX2, RTL8188CU_2), 154 URTWN_DEV(PLANEX2, RTL8192CU), 155 URTWN_DEV(PLANEX2, RTL8188CU_3), 156 URTWN_DEV(PLANEX2, RTL8188CU_4), 157 URTWN_DEV(PLANEX2, RTL8188CUS), 158 URTWN_DEV(REALTEK, RTL8188CE_0), 159 URTWN_DEV(REALTEK, RTL8188CE_1), 160 URTWN_DEV(REALTEK, RTL8188CTV), 161 URTWN_DEV(REALTEK, RTL8188CU_0), 162 URTWN_DEV(REALTEK, RTL8188CU_1), 163 URTWN_DEV(REALTEK, RTL8188CU_2), 164 URTWN_DEV(REALTEK, RTL8188CU_3), 165 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 166 URTWN_DEV(REALTEK, RTL8188CUS), 167 URTWN_DEV(REALTEK, RTL8188RU), 168 URTWN_DEV(REALTEK, RTL8188RU_2), 169 URTWN_DEV(REALTEK, RTL8188RU_3), 170 URTWN_DEV(REALTEK, RTL8191CU), 171 URTWN_DEV(REALTEK, RTL8192CE), 172 URTWN_DEV(REALTEK, RTL8192CU), 173 URTWN_DEV(SITECOMEU, RTL8188CU), 174 URTWN_DEV(SITECOMEU, RTL8188CU_2), 175 URTWN_DEV(SITECOMEU, RTL8192CU), 176 URTWN_DEV(SITECOMEU, RTL8192CUR2), 177 URTWN_DEV(TPLINK, RTL8192CU), 178 URTWN_DEV(TRENDNET, RTL8188CU), 179 URTWN_DEV(TRENDNET, RTL8192CU), 180 URTWN_DEV(ZYXEL, RTL8192CU), 181 182 /* URTWN_RTL8188E */ 183 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 184 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 185 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 186 }; 187 #undef URTWN_DEV 188 #undef URTWN_RTL8188E_DEV 189 190 static int urtwn_match(device_t, cfdata_t, void *); 191 static void urtwn_attach(device_t, device_t, void *); 192 static int urtwn_detach(device_t, int); 193 static int urtwn_activate(device_t, enum devact); 194 195 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 196 urtwn_attach, urtwn_detach, urtwn_activate); 197 198 static int urtwn_open_pipes(struct urtwn_softc *); 199 static void urtwn_close_pipes(struct urtwn_softc *); 200 static int urtwn_alloc_rx_list(struct urtwn_softc *); 201 static void urtwn_free_rx_list(struct urtwn_softc *); 202 static int urtwn_alloc_tx_list(struct urtwn_softc *); 203 static void urtwn_free_tx_list(struct urtwn_softc *); 204 static void urtwn_task(void *); 205 static void urtwn_do_async(struct urtwn_softc *, 206 void (*)(struct urtwn_softc *, void *), void *, int); 207 static void urtwn_wait_async(struct urtwn_softc *); 208 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 209 int); 210 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 211 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 212 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 213 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 214 int); 215 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 216 int); 217 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 218 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 219 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 220 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 221 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 222 uint32_t); 223 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 224 uint32_t); 225 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 226 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 227 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 228 static void urtwn_efuse_read(struct urtwn_softc *); 229 static void urtwn_efuse_switch_power(struct urtwn_softc *); 230 static int urtwn_read_chipid(struct urtwn_softc *); 231 #ifdef URTWN_DEBUG 232 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 233 #endif 234 static void urtwn_read_rom(struct urtwn_softc *); 235 static void urtwn_r88e_read_rom(struct urtwn_softc *); 236 static int urtwn_media_change(struct ifnet *); 237 static int urtwn_ra_init(struct urtwn_softc *); 238 static int urtwn_get_nettype(struct urtwn_softc *); 239 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 240 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 241 static void urtwn_set_led(struct urtwn_softc *, int, int); 242 static void urtwn_calib_to(void *); 243 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 244 static void urtwn_next_scan(void *); 245 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 246 int); 247 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 248 static int urtwn_wme_update(struct ieee80211com *); 249 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 250 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 251 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 252 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 253 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 254 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 255 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 256 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 257 struct ieee80211_node *, struct urtwn_tx_data *); 258 static struct urtwn_tx_data * 259 urtwn_get_tx_data(struct urtwn_softc *, size_t); 260 static void urtwn_start(struct ifnet *); 261 static void urtwn_watchdog(struct ifnet *); 262 static int urtwn_ioctl(struct ifnet *, u_long, void *); 263 static int urtwn_r92c_power_on(struct urtwn_softc *); 264 static int urtwn_r88e_power_on(struct urtwn_softc *); 265 static int urtwn_llt_init(struct urtwn_softc *); 266 static void urtwn_fw_reset(struct urtwn_softc *); 267 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 268 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 269 static int urtwn_load_firmware(struct urtwn_softc *); 270 static int urtwn_r92c_dma_init(struct urtwn_softc *); 271 static int urtwn_r88e_dma_init(struct urtwn_softc *); 272 static void urtwn_mac_init(struct urtwn_softc *); 273 static void urtwn_bb_init(struct urtwn_softc *); 274 static void urtwn_rf_init(struct urtwn_softc *); 275 static void urtwn_cam_init(struct urtwn_softc *); 276 static void urtwn_pa_bias_init(struct urtwn_softc *); 277 static void urtwn_rxfilter_init(struct urtwn_softc *); 278 static void urtwn_edca_init(struct urtwn_softc *); 279 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 280 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 281 uint16_t[]); 282 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 283 u_int, uint16_t[]); 284 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 285 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 286 u_int); 287 static void urtwn_iq_calib(struct urtwn_softc *, bool); 288 static void urtwn_lc_calib(struct urtwn_softc *); 289 static void urtwn_temp_calib(struct urtwn_softc *); 290 static int urtwn_init(struct ifnet *); 291 static void urtwn_stop(struct ifnet *, int); 292 static int urtwn_reset(struct ifnet *); 293 static void urtwn_chip_stop(struct urtwn_softc *); 294 static void urtwn_newassoc(struct ieee80211_node *, int); 295 296 /* Aliases. */ 297 #define urtwn_bb_write urtwn_write_4 298 #define urtwn_bb_read urtwn_read_4 299 300 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 301 302 static int 303 urtwn_match(device_t parent, cfdata_t match, void *aux) 304 { 305 struct usb_attach_arg *uaa = aux; 306 307 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 308 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 309 } 310 311 static void 312 urtwn_attach(device_t parent, device_t self, void *aux) 313 { 314 struct urtwn_softc *sc = device_private(self); 315 struct ieee80211com *ic = &sc->sc_ic; 316 struct ifnet *ifp = &sc->sc_if; 317 struct usb_attach_arg *uaa = aux; 318 char *devinfop; 319 const struct urtwn_dev *dev; 320 size_t i; 321 int error; 322 323 sc->sc_dev = self; 324 sc->sc_udev = uaa->uaa_device; 325 326 sc->chip = 0; 327 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 328 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 329 SET(sc->chip, URTWN_CHIP_88E); 330 331 aprint_naive("\n"); 332 aprint_normal("\n"); 333 334 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 335 336 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 337 aprint_normal_dev(self, "%s\n", devinfop); 338 usbd_devinfo_free(devinfop); 339 340 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 341 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 342 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 343 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 344 345 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 346 347 callout_init(&sc->sc_scan_to, 0); 348 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 349 callout_init(&sc->sc_calib_to, 0); 350 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 351 352 error = usbd_set_config_no(sc->sc_udev, 1, 0); 353 if (error != 0) { 354 aprint_error_dev(self, "failed to set configuration" 355 ", err=%s\n", usbd_errstr(error)); 356 goto fail; 357 } 358 359 /* Get the first interface handle. */ 360 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 361 if (error != 0) { 362 aprint_error_dev(self, "could not get interface handle\n"); 363 goto fail; 364 } 365 366 error = urtwn_read_chipid(sc); 367 if (error != 0) { 368 aprint_error_dev(self, "unsupported test chip\n"); 369 goto fail; 370 } 371 372 /* Determine number of Tx/Rx chains. */ 373 if (sc->chip & URTWN_CHIP_92C) { 374 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 375 sc->nrxchains = 2; 376 } else { 377 sc->ntxchains = 1; 378 sc->nrxchains = 1; 379 } 380 381 if (ISSET(sc->chip, URTWN_CHIP_88E)) 382 urtwn_r88e_read_rom(sc); 383 else 384 urtwn_read_rom(sc); 385 386 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 387 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 388 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 389 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 390 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 391 "8188CUS", sc->ntxchains, sc->nrxchains, 392 ether_sprintf(ic->ic_myaddr)); 393 394 error = urtwn_open_pipes(sc); 395 if (error != 0) { 396 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 397 goto fail; 398 } 399 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 400 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 401 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 402 403 /* 404 * Setup the 802.11 device. 405 */ 406 ic->ic_ifp = ifp; 407 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 408 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 409 ic->ic_state = IEEE80211_S_INIT; 410 411 /* Set device capabilities. */ 412 ic->ic_caps = 413 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 414 IEEE80211_C_IBSS | /* IBSS mode supported */ 415 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 416 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 417 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 418 IEEE80211_C_WME | /* 802.11e */ 419 IEEE80211_C_WPA; /* 802.11i */ 420 421 /* Set supported .11b and .11g rates. */ 422 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 423 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 424 425 /* Set supported .11b and .11g channels (1 through 14). */ 426 for (i = 1; i <= 14; i++) { 427 ic->ic_channels[i].ic_freq = 428 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 429 ic->ic_channels[i].ic_flags = 430 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 431 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 432 } 433 434 ifp->if_softc = sc; 435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 436 ifp->if_init = urtwn_init; 437 ifp->if_ioctl = urtwn_ioctl; 438 ifp->if_start = urtwn_start; 439 ifp->if_watchdog = urtwn_watchdog; 440 IFQ_SET_READY(&ifp->if_snd); 441 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 442 443 if_attach(ifp); 444 ieee80211_ifattach(ic); 445 446 /* override default methods */ 447 ic->ic_newassoc = urtwn_newassoc; 448 ic->ic_reset = urtwn_reset; 449 ic->ic_wme.wme_update = urtwn_wme_update; 450 451 /* Override state transition machine. */ 452 sc->sc_newstate = ic->ic_newstate; 453 ic->ic_newstate = urtwn_newstate; 454 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 455 456 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 457 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 458 &sc->sc_drvbpf); 459 460 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 461 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 462 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 463 464 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 465 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 466 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 467 468 ieee80211_announce(ic); 469 470 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 471 472 if (!pmf_device_register(self, NULL, NULL)) 473 aprint_error_dev(self, "couldn't establish power handler\n"); 474 475 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 476 return; 477 478 fail: 479 sc->sc_dying = 1; 480 aprint_error_dev(self, "attach failed\n"); 481 } 482 483 static int 484 urtwn_detach(device_t self, int flags) 485 { 486 struct urtwn_softc *sc = device_private(self); 487 struct ifnet *ifp = &sc->sc_if; 488 int s; 489 490 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 491 492 pmf_device_deregister(self); 493 494 s = splusb(); 495 496 sc->sc_dying = 1; 497 498 callout_stop(&sc->sc_scan_to); 499 callout_stop(&sc->sc_calib_to); 500 501 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 502 usb_rem_task(sc->sc_udev, &sc->sc_task); 503 urtwn_stop(ifp, 0); 504 505 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 506 bpf_detach(ifp); 507 ieee80211_ifdetach(&sc->sc_ic); 508 if_detach(ifp); 509 510 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 511 urtwn_close_pipes(sc); 512 } 513 514 splx(s); 515 516 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 517 518 callout_destroy(&sc->sc_scan_to); 519 callout_destroy(&sc->sc_calib_to); 520 521 mutex_destroy(&sc->sc_write_mtx); 522 mutex_destroy(&sc->sc_fwcmd_mtx); 523 mutex_destroy(&sc->sc_tx_mtx); 524 mutex_destroy(&sc->sc_task_mtx); 525 526 return 0; 527 } 528 529 static int 530 urtwn_activate(device_t self, enum devact act) 531 { 532 struct urtwn_softc *sc = device_private(self); 533 534 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 535 536 switch (act) { 537 case DVACT_DEACTIVATE: 538 if_deactivate(sc->sc_ic.ic_ifp); 539 return 0; 540 default: 541 return EOPNOTSUPP; 542 } 543 } 544 545 static int 546 urtwn_open_pipes(struct urtwn_softc *sc) 547 { 548 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 549 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 size_t i, ntx = 0; 553 int error; 554 555 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 556 557 /* Determine the number of bulk-out pipes. */ 558 id = usbd_get_interface_descriptor(sc->sc_iface); 559 for (i = 0; i < id->bNumEndpoints; i++) { 560 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 561 if (ed != NULL && 562 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 563 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 564 ntx++; 565 } 566 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 567 device_xname(sc->sc_dev), __func__, ntx)); 568 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 569 aprint_error_dev(sc->sc_dev, 570 "%zd: invalid number of Tx bulk pipes\n", ntx); 571 return EIO; 572 } 573 sc->rx_npipe = 1; 574 sc->tx_npipe = ntx; 575 576 /* Open bulk-in pipe at address 0x81. */ 577 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 578 &sc->rx_pipe); 579 if (error != 0) { 580 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 581 ": %d\n", error); 582 goto fail; 583 } 584 585 /* Open bulk-out pipes (up to 3). */ 586 for (i = 0; i < ntx; i++) { 587 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 588 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 589 if (error != 0) { 590 aprint_error_dev(sc->sc_dev, 591 "could not open Tx bulk pipe 0x%02x: %d\n", 592 epaddr[i], error); 593 goto fail; 594 } 595 } 596 597 /* Map 802.11 access categories to USB pipes. */ 598 sc->ac2idx[WME_AC_BK] = 599 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 600 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 601 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 602 603 fail: 604 if (error != 0) 605 urtwn_close_pipes(sc); 606 return error; 607 } 608 609 static void 610 urtwn_close_pipes(struct urtwn_softc *sc) 611 { 612 struct usbd_pipe *pipe; 613 size_t i; 614 615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 616 617 /* Close Rx pipe. */ 618 CTASSERT(sizeof(pipe) == sizeof(void *)); 619 pipe = atomic_swap_ptr(&sc->rx_pipe, NULL); 620 if (pipe != NULL) { 621 usbd_close_pipe(pipe); 622 } 623 /* Close Tx pipes. */ 624 for (i = 0; i < R92C_MAX_EPOUT; i++) { 625 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 626 if (pipe != NULL) { 627 usbd_close_pipe(pipe); 628 } 629 } 630 } 631 632 static int 633 urtwn_alloc_rx_list(struct urtwn_softc *sc) 634 { 635 struct urtwn_rx_data *data; 636 size_t i; 637 int error = 0; 638 639 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 640 641 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 642 data = &sc->rx_data[i]; 643 644 data->sc = sc; /* Backpointer for callbacks. */ 645 646 error = usbd_create_xfer(sc->rx_pipe, URTWN_RXBUFSZ, 647 USBD_SHORT_XFER_OK, 0, &data->xfer); 648 if (error) { 649 aprint_error_dev(sc->sc_dev, 650 "could not allocate xfer\n"); 651 break; 652 } 653 654 data->buf = usbd_get_buffer(data->xfer); 655 } 656 if (error != 0) 657 urtwn_free_rx_list(sc); 658 return error; 659 } 660 661 static void 662 urtwn_free_rx_list(struct urtwn_softc *sc) 663 { 664 struct usbd_xfer *xfer; 665 size_t i; 666 667 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 668 669 /* NB: Caller must abort pipe first. */ 670 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 671 CTASSERT(sizeof(xfer) == sizeof(void *)); 672 xfer = atomic_swap_ptr(&sc->rx_data[i].xfer, NULL); 673 if (xfer != NULL) 674 usbd_destroy_xfer(xfer); 675 } 676 } 677 678 static int 679 urtwn_alloc_tx_list(struct urtwn_softc *sc) 680 { 681 struct urtwn_tx_data *data; 682 size_t i; 683 int error = 0; 684 685 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 686 687 mutex_enter(&sc->sc_tx_mtx); 688 for (size_t j = 0; j < sc->tx_npipe; j++) { 689 TAILQ_INIT(&sc->tx_free_list[j]); 690 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 691 data = &sc->tx_data[j][i]; 692 693 data->sc = sc; /* Backpointer for callbacks. */ 694 data->pidx = j; 695 696 error = usbd_create_xfer(sc->tx_pipe[j], 697 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 698 &data->xfer); 699 if (error) { 700 aprint_error_dev(sc->sc_dev, 701 "could not allocate xfer\n"); 702 goto fail; 703 } 704 705 data->buf = usbd_get_buffer(data->xfer); 706 707 /* Append this Tx buffer to our free list. */ 708 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 709 } 710 } 711 mutex_exit(&sc->sc_tx_mtx); 712 return 0; 713 714 fail: 715 urtwn_free_tx_list(sc); 716 mutex_exit(&sc->sc_tx_mtx); 717 return error; 718 } 719 720 static void 721 urtwn_free_tx_list(struct urtwn_softc *sc) 722 { 723 struct usbd_xfer *xfer; 724 size_t i; 725 726 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 727 728 /* NB: Caller must abort pipe first. */ 729 for (size_t j = 0; j < sc->tx_npipe; j++) { 730 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 731 CTASSERT(sizeof(xfer) == sizeof(void *)); 732 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 733 if (xfer != NULL) 734 usbd_destroy_xfer(xfer); 735 } 736 } 737 } 738 739 static void 740 urtwn_task(void *arg) 741 { 742 struct urtwn_softc *sc = arg; 743 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 744 struct urtwn_host_cmd *cmd; 745 int s; 746 747 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 748 749 /* Process host commands. */ 750 s = splusb(); 751 mutex_spin_enter(&sc->sc_task_mtx); 752 while (ring->next != ring->cur) { 753 cmd = &ring->cmd[ring->next]; 754 mutex_spin_exit(&sc->sc_task_mtx); 755 splx(s); 756 /* Invoke callback with kernel lock held. */ 757 cmd->cb(sc, cmd->data); 758 s = splusb(); 759 mutex_spin_enter(&sc->sc_task_mtx); 760 ring->queued--; 761 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 762 } 763 mutex_spin_exit(&sc->sc_task_mtx); 764 wakeup(&sc->cmdq); 765 splx(s); 766 } 767 768 static void 769 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 770 void *arg, int len) 771 { 772 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 773 struct urtwn_host_cmd *cmd; 774 int s; 775 776 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 777 device_xname(sc->sc_dev), __func__, cb, arg, len)); 778 779 s = splusb(); 780 mutex_spin_enter(&sc->sc_task_mtx); 781 cmd = &ring->cmd[ring->cur]; 782 cmd->cb = cb; 783 KASSERT(len <= sizeof(cmd->data)); 784 memcpy(cmd->data, arg, len); 785 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 786 787 /* If there is no pending command already, schedule a task. */ 788 if (!sc->sc_dying && ++ring->queued == 1) { 789 mutex_spin_exit(&sc->sc_task_mtx); 790 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 791 } else 792 mutex_spin_exit(&sc->sc_task_mtx); 793 splx(s); 794 } 795 796 static void 797 urtwn_wait_async(struct urtwn_softc *sc) 798 { 799 800 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 801 802 /* Wait for all queued asynchronous commands to complete. */ 803 while (sc->cmdq.queued > 0) 804 tsleep(&sc->cmdq, 0, "endtask", 0); 805 } 806 807 static int 808 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 809 int len) 810 { 811 usb_device_request_t req; 812 usbd_status error; 813 814 KASSERT(mutex_owned(&sc->sc_write_mtx)); 815 816 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 817 req.bRequest = R92C_REQ_REGS; 818 USETW(req.wValue, addr); 819 USETW(req.wIndex, 0); 820 USETW(req.wLength, len); 821 error = usbd_do_request(sc->sc_udev, &req, buf); 822 if (error != USBD_NORMAL_COMPLETION) { 823 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 824 device_xname(sc->sc_dev), __func__, error, addr, len)); 825 } 826 return error; 827 } 828 829 static void 830 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 831 { 832 833 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 834 device_xname(sc->sc_dev), __func__, addr, val)); 835 836 urtwn_write_region_1(sc, addr, &val, 1); 837 } 838 839 static void 840 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 841 { 842 uint8_t buf[2]; 843 844 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 845 device_xname(sc->sc_dev), __func__, addr, val)); 846 847 buf[0] = (uint8_t)val; 848 buf[1] = (uint8_t)(val >> 8); 849 urtwn_write_region_1(sc, addr, buf, 2); 850 } 851 852 static void 853 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 854 { 855 uint8_t buf[4]; 856 857 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 858 device_xname(sc->sc_dev), __func__, addr, val)); 859 860 buf[0] = (uint8_t)val; 861 buf[1] = (uint8_t)(val >> 8); 862 buf[2] = (uint8_t)(val >> 16); 863 buf[3] = (uint8_t)(val >> 24); 864 urtwn_write_region_1(sc, addr, buf, 4); 865 } 866 867 static int 868 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 869 { 870 871 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 872 device_xname(sc->sc_dev), __func__, addr, len)); 873 874 return urtwn_write_region_1(sc, addr, buf, len); 875 } 876 877 static int 878 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 879 int len) 880 { 881 usb_device_request_t req; 882 usbd_status error; 883 884 req.bmRequestType = UT_READ_VENDOR_DEVICE; 885 req.bRequest = R92C_REQ_REGS; 886 USETW(req.wValue, addr); 887 USETW(req.wIndex, 0); 888 USETW(req.wLength, len); 889 error = usbd_do_request(sc->sc_udev, &req, buf); 890 if (error != USBD_NORMAL_COMPLETION) { 891 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 892 device_xname(sc->sc_dev), __func__, error, addr, len)); 893 } 894 return error; 895 } 896 897 static uint8_t 898 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 899 { 900 uint8_t val; 901 902 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 903 return 0xff; 904 905 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 906 device_xname(sc->sc_dev), __func__, addr, val)); 907 return val; 908 } 909 910 static uint16_t 911 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 912 { 913 uint8_t buf[2]; 914 uint16_t val; 915 916 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 917 return 0xffff; 918 919 val = LE_READ_2(&buf[0]); 920 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 921 device_xname(sc->sc_dev), __func__, addr, val)); 922 return val; 923 } 924 925 static uint32_t 926 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 927 { 928 uint8_t buf[4]; 929 uint32_t val; 930 931 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 932 return 0xffffffff; 933 934 val = LE_READ_4(&buf[0]); 935 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 936 device_xname(sc->sc_dev), __func__, addr, val)); 937 return val; 938 } 939 940 static int 941 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 942 { 943 struct r92c_fw_cmd cmd; 944 uint8_t *cp; 945 int fwcur; 946 int ntries; 947 948 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 949 device_xname(sc->sc_dev), __func__, id, buf, len)); 950 951 KASSERT(mutex_owned(&sc->sc_write_mtx)); 952 953 mutex_enter(&sc->sc_fwcmd_mtx); 954 fwcur = sc->fwcur; 955 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 956 mutex_exit(&sc->sc_fwcmd_mtx); 957 958 /* Wait for current FW box to be empty. */ 959 for (ntries = 0; ntries < 100; ntries++) { 960 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 961 break; 962 DELAY(1); 963 } 964 if (ntries == 100) { 965 aprint_error_dev(sc->sc_dev, 966 "could not send firmware command %d\n", id); 967 return ETIMEDOUT; 968 } 969 970 memset(&cmd, 0, sizeof(cmd)); 971 KASSERT(len <= sizeof(cmd.msg)); 972 memcpy(cmd.msg, buf, len); 973 974 /* Write the first word last since that will trigger the FW. */ 975 cp = (uint8_t *)&cmd; 976 if (len >= 4) { 977 cmd.id = id | R92C_CMD_FLAG_EXT; 978 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 979 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 980 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 981 } else { 982 cmd.id = id; 983 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 984 } 985 986 return 0; 987 } 988 989 static __inline void 990 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 991 { 992 993 sc->sc_rf_write(sc, chain, addr, val); 994 } 995 996 static void 997 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 998 uint32_t val) 999 { 1000 1001 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1002 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1003 } 1004 1005 static void 1006 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1007 uint32_t val) 1008 { 1009 1010 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1011 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1012 } 1013 1014 static uint32_t 1015 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1016 { 1017 uint32_t reg[R92C_MAX_CHAINS], val; 1018 1019 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1020 if (chain != 0) { 1021 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1022 } 1023 1024 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1025 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1026 DELAY(1000); 1027 1028 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1029 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1030 R92C_HSSI_PARAM2_READ_EDGE); 1031 DELAY(1000); 1032 1033 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1034 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1035 DELAY(1000); 1036 1037 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1038 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1039 } else { 1040 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1041 } 1042 return MS(val, R92C_LSSI_READBACK_DATA); 1043 } 1044 1045 static int 1046 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1047 { 1048 int ntries; 1049 1050 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1051 1052 urtwn_write_4(sc, R92C_LLT_INIT, 1053 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1054 SM(R92C_LLT_INIT_ADDR, addr) | 1055 SM(R92C_LLT_INIT_DATA, data)); 1056 /* Wait for write operation to complete. */ 1057 for (ntries = 0; ntries < 20; ntries++) { 1058 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1059 R92C_LLT_INIT_OP_NO_ACTIVE) { 1060 /* Done */ 1061 return 0; 1062 } 1063 DELAY(5); 1064 } 1065 return ETIMEDOUT; 1066 } 1067 1068 static uint8_t 1069 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1070 { 1071 uint32_t reg; 1072 int ntries; 1073 1074 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1075 1076 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1077 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1078 reg &= ~R92C_EFUSE_CTRL_VALID; 1079 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1080 1081 /* Wait for read operation to complete. */ 1082 for (ntries = 0; ntries < 100; ntries++) { 1083 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1084 if (reg & R92C_EFUSE_CTRL_VALID) { 1085 /* Done */ 1086 return MS(reg, R92C_EFUSE_CTRL_DATA); 1087 } 1088 DELAY(5); 1089 } 1090 aprint_error_dev(sc->sc_dev, 1091 "could not read efuse byte at address 0x%04x\n", addr); 1092 return 0xff; 1093 } 1094 1095 static void 1096 urtwn_efuse_read(struct urtwn_softc *sc) 1097 { 1098 uint8_t *rom = (uint8_t *)&sc->rom; 1099 uint32_t reg; 1100 uint16_t addr = 0; 1101 uint8_t off, msk; 1102 size_t i; 1103 1104 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1105 1106 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1107 1108 urtwn_efuse_switch_power(sc); 1109 1110 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1111 while (addr < 512) { 1112 reg = urtwn_efuse_read_1(sc, addr); 1113 if (reg == 0xff) 1114 break; 1115 addr++; 1116 off = reg >> 4; 1117 msk = reg & 0xf; 1118 for (i = 0; i < 4; i++) { 1119 if (msk & (1U << i)) 1120 continue; 1121 1122 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1123 addr++; 1124 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1125 addr++; 1126 } 1127 } 1128 #ifdef URTWN_DEBUG 1129 if (urtwn_debug & DBG_INIT) { 1130 /* Dump ROM content. */ 1131 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1132 for (i = 0; i < (int)sizeof(sc->rom); i++) 1133 printf(":%02x", rom[i]); 1134 printf("\n"); 1135 } 1136 #endif 1137 } 1138 1139 static void 1140 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1141 { 1142 uint32_t reg; 1143 1144 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1145 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1146 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1147 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1148 } 1149 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1150 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1151 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1152 reg | R92C_SYS_FUNC_EN_ELDR); 1153 } 1154 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1155 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1156 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1157 urtwn_write_2(sc, R92C_SYS_CLKR, 1158 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1159 } 1160 } 1161 1162 static int 1163 urtwn_read_chipid(struct urtwn_softc *sc) 1164 { 1165 uint32_t reg; 1166 1167 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1168 1169 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1170 return 0; 1171 1172 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1173 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1174 /* test chip, not supported */ 1175 return EIO; 1176 } 1177 if (reg & R92C_SYS_CFG_TYPE_92C) { 1178 sc->chip |= URTWN_CHIP_92C; 1179 /* Check if it is a castrated 8192C. */ 1180 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1181 R92C_HPON_FSM_CHIP_BONDING_ID) == 1182 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1183 sc->chip |= URTWN_CHIP_92C_1T2R; 1184 } 1185 } 1186 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1187 sc->chip |= URTWN_CHIP_UMC; 1188 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1189 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1190 } 1191 } 1192 return 0; 1193 } 1194 1195 #ifdef URTWN_DEBUG 1196 static void 1197 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1198 { 1199 1200 aprint_normal_dev(sc->sc_dev, 1201 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1202 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1203 1204 aprint_normal_dev(sc->sc_dev, 1205 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1206 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1207 1208 aprint_normal_dev(sc->sc_dev, 1209 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1210 rp->macaddr[0], rp->macaddr[1], 1211 rp->macaddr[2], rp->macaddr[3], 1212 rp->macaddr[4], rp->macaddr[5]); 1213 1214 aprint_normal_dev(sc->sc_dev, 1215 "string %s, subcustomer_id 0x%x\n", 1216 rp->string, rp->subcustomer_id); 1217 1218 aprint_normal_dev(sc->sc_dev, 1219 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1220 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1221 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1222 1223 aprint_normal_dev(sc->sc_dev, 1224 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1225 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1226 rp->ht40_1s_tx_pwr[0][2], 1227 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1228 rp->ht40_1s_tx_pwr[1][2]); 1229 1230 aprint_normal_dev(sc->sc_dev, 1231 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1232 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1233 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1234 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1235 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1236 1237 aprint_normal_dev(sc->sc_dev, 1238 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1239 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1240 rp->ht20_tx_pwr_diff[2] & 0xf, 1241 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1242 rp->ht20_tx_pwr_diff[2] >> 4); 1243 1244 aprint_normal_dev(sc->sc_dev, 1245 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1246 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1247 rp->ofdm_tx_pwr_diff[2] & 0xf, 1248 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1249 rp->ofdm_tx_pwr_diff[2] >> 4); 1250 1251 aprint_normal_dev(sc->sc_dev, 1252 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1253 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1254 rp->ht40_max_pwr[2] & 0xf, 1255 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1256 rp->ht40_max_pwr[2] >> 4); 1257 1258 aprint_normal_dev(sc->sc_dev, 1259 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1260 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1261 rp->ht20_max_pwr[2] & 0xf, 1262 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1263 rp->ht20_max_pwr[2] >> 4); 1264 1265 aprint_normal_dev(sc->sc_dev, 1266 "xtal_calib %d, tssi %d %d, thermal %d\n", 1267 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1268 1269 aprint_normal_dev(sc->sc_dev, 1270 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1271 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1272 1273 aprint_normal_dev(sc->sc_dev, 1274 "channnel_plan %d, version %d customer_id 0x%x\n", 1275 rp->channel_plan, rp->version, rp->curstomer_id); 1276 } 1277 #endif 1278 1279 static void 1280 urtwn_read_rom(struct urtwn_softc *sc) 1281 { 1282 struct ieee80211com *ic = &sc->sc_ic; 1283 struct r92c_rom *rom = &sc->rom; 1284 1285 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1286 1287 mutex_enter(&sc->sc_write_mtx); 1288 1289 /* Read full ROM image. */ 1290 urtwn_efuse_read(sc); 1291 #ifdef URTWN_DEBUG 1292 if (urtwn_debug & DBG_REG) 1293 urtwn_dump_rom(sc, rom); 1294 #endif 1295 1296 /* XXX Weird but this is what the vendor driver does. */ 1297 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1298 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1299 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1300 1301 DPRINTFN(DBG_INIT, 1302 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1303 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1304 sc->board_type, sc->regulatory)); 1305 1306 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1307 1308 sc->sc_rf_write = urtwn_r92c_rf_write; 1309 sc->sc_power_on = urtwn_r92c_power_on; 1310 sc->sc_dma_init = urtwn_r92c_dma_init; 1311 1312 mutex_exit(&sc->sc_write_mtx); 1313 } 1314 1315 static void 1316 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1317 { 1318 struct ieee80211com *ic = &sc->sc_ic; 1319 uint8_t *rom = sc->r88e_rom; 1320 uint32_t reg; 1321 uint16_t addr = 0; 1322 uint8_t off, msk, tmp; 1323 int i; 1324 1325 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1326 1327 mutex_enter(&sc->sc_write_mtx); 1328 1329 off = 0; 1330 urtwn_efuse_switch_power(sc); 1331 1332 /* Read full ROM image. */ 1333 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1334 while (addr < 1024) { 1335 reg = urtwn_efuse_read_1(sc, addr); 1336 if (reg == 0xff) 1337 break; 1338 addr++; 1339 if ((reg & 0x1f) == 0x0f) { 1340 tmp = (reg & 0xe0) >> 5; 1341 reg = urtwn_efuse_read_1(sc, addr); 1342 if ((reg & 0x0f) != 0x0f) 1343 off = ((reg & 0xf0) >> 1) | tmp; 1344 addr++; 1345 } else 1346 off = reg >> 4; 1347 msk = reg & 0xf; 1348 for (i = 0; i < 4; i++) { 1349 if (msk & (1 << i)) 1350 continue; 1351 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1352 addr++; 1353 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1354 addr++; 1355 } 1356 } 1357 #ifdef URTWN_DEBUG 1358 if (urtwn_debug & DBG_REG) { 1359 } 1360 #endif 1361 1362 addr = 0x10; 1363 for (i = 0; i < 6; i++) 1364 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1365 for (i = 0; i < 5; i++) 1366 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1367 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1368 if (sc->bw20_tx_pwr_diff & 0x08) 1369 sc->bw20_tx_pwr_diff |= 0xf0; 1370 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1371 if (sc->ofdm_tx_pwr_diff & 0x08) 1372 sc->ofdm_tx_pwr_diff |= 0xf0; 1373 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1374 1375 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1376 1377 sc->sc_rf_write = urtwn_r88e_rf_write; 1378 sc->sc_power_on = urtwn_r88e_power_on; 1379 sc->sc_dma_init = urtwn_r88e_dma_init; 1380 1381 mutex_exit(&sc->sc_write_mtx); 1382 } 1383 1384 static int 1385 urtwn_media_change(struct ifnet *ifp) 1386 { 1387 #ifdef URTWN_DEBUG 1388 struct urtwn_softc *sc = ifp->if_softc; 1389 #endif 1390 int error; 1391 1392 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1393 1394 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1395 return error; 1396 1397 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1398 (IFF_UP | IFF_RUNNING)) { 1399 urtwn_init(ifp); 1400 } 1401 return 0; 1402 } 1403 1404 /* 1405 * Initialize rate adaptation in firmware. 1406 */ 1407 static int 1408 urtwn_ra_init(struct urtwn_softc *sc) 1409 { 1410 static const uint8_t map[] = { 1411 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1412 }; 1413 struct ieee80211com *ic = &sc->sc_ic; 1414 struct ieee80211_node *ni = ic->ic_bss; 1415 struct ieee80211_rateset *rs = &ni->ni_rates; 1416 struct r92c_fw_cmd_macid_cfg cmd; 1417 uint32_t rates, basicrates; 1418 uint32_t mask; 1419 uint8_t mode; 1420 size_t maxrate, maxbasicrate, i, j; 1421 int error; 1422 1423 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1424 1425 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1426 1427 /* Get normal and basic rates mask. */ 1428 rates = basicrates = 0; 1429 maxrate = maxbasicrate = 0; 1430 for (i = 0; i < rs->rs_nrates; i++) { 1431 /* Convert 802.11 rate to HW rate index. */ 1432 for (j = 0; j < __arraycount(map); j++) { 1433 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1434 break; 1435 } 1436 } 1437 if (j == __arraycount(map)) { 1438 /* Unknown rate, skip. */ 1439 continue; 1440 } 1441 1442 rates |= 1U << j; 1443 if (j > maxrate) { 1444 maxrate = j; 1445 } 1446 1447 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1448 basicrates |= 1U << j; 1449 if (j > maxbasicrate) { 1450 maxbasicrate = j; 1451 } 1452 } 1453 } 1454 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1455 mode = R92C_RAID_11B; 1456 } else { 1457 mode = R92C_RAID_11BG; 1458 } 1459 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1460 "maxrate=%zx, maxbasicrate=%zx\n", 1461 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1462 maxrate, maxbasicrate)); 1463 if (basicrates == 0) { 1464 basicrates |= 1; /* add 1Mbps */ 1465 } 1466 1467 /* Set rates mask for group addressed frames. */ 1468 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1469 mask = (mode << 28) | basicrates; 1470 cmd.mask[0] = (uint8_t)mask; 1471 cmd.mask[1] = (uint8_t)(mask >> 8); 1472 cmd.mask[2] = (uint8_t)(mask >> 16); 1473 cmd.mask[3] = (uint8_t)(mask >> 24); 1474 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1475 if (error != 0) { 1476 aprint_error_dev(sc->sc_dev, 1477 "could not add broadcast station\n"); 1478 return error; 1479 } 1480 /* Set initial MRR rate. */ 1481 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1482 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1483 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1484 1485 /* Set rates mask for unicast frames. */ 1486 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1487 mask = (mode << 28) | rates; 1488 cmd.mask[0] = (uint8_t)mask; 1489 cmd.mask[1] = (uint8_t)(mask >> 8); 1490 cmd.mask[2] = (uint8_t)(mask >> 16); 1491 cmd.mask[3] = (uint8_t)(mask >> 24); 1492 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1493 if (error != 0) { 1494 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1495 return error; 1496 } 1497 /* Set initial MRR rate. */ 1498 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1499 __func__, maxrate)); 1500 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1501 1502 /* Indicate highest supported rate. */ 1503 ni->ni_txrate = rs->rs_nrates - 1; 1504 1505 return 0; 1506 } 1507 1508 static int 1509 urtwn_get_nettype(struct urtwn_softc *sc) 1510 { 1511 struct ieee80211com *ic = &sc->sc_ic; 1512 int type; 1513 1514 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1515 1516 switch (ic->ic_opmode) { 1517 case IEEE80211_M_STA: 1518 type = R92C_CR_NETTYPE_INFRA; 1519 break; 1520 1521 case IEEE80211_M_IBSS: 1522 type = R92C_CR_NETTYPE_ADHOC; 1523 break; 1524 1525 default: 1526 type = R92C_CR_NETTYPE_NOLINK; 1527 break; 1528 } 1529 1530 return type; 1531 } 1532 1533 static void 1534 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1535 { 1536 uint8_t reg; 1537 1538 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1539 __func__, type)); 1540 1541 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1542 1543 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1544 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1545 } 1546 1547 static void 1548 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1549 { 1550 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1551 uint64_t tsf; 1552 1553 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1554 1555 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1556 1557 /* Enable TSF synchronization. */ 1558 urtwn_write_1(sc, R92C_BCN_CTRL, 1559 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1560 1561 /* Correct TSF */ 1562 urtwn_write_1(sc, R92C_BCN_CTRL, 1563 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1564 1565 /* Set initial TSF. */ 1566 tsf = ni->ni_tstamp.tsf; 1567 tsf = le64toh(tsf); 1568 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1569 tsf -= IEEE80211_DUR_TU; 1570 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1571 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1572 1573 urtwn_write_1(sc, R92C_BCN_CTRL, 1574 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1575 } 1576 1577 static void 1578 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1579 { 1580 uint8_t reg; 1581 1582 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1583 __func__, led, on)); 1584 1585 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1586 1587 if (led == URTWN_LED_LINK) { 1588 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1589 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1590 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1591 if (!on) { 1592 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1593 urtwn_write_1(sc, R92C_LEDCFG2, 1594 reg | R92C_LEDCFG0_DIS); 1595 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1596 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1597 reg & 0xfe); 1598 } 1599 } else { 1600 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1601 if (!on) { 1602 reg |= R92C_LEDCFG0_DIS; 1603 } 1604 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1605 } 1606 sc->ledlink = on; /* Save LED state. */ 1607 } 1608 } 1609 1610 static void 1611 urtwn_calib_to(void *arg) 1612 { 1613 struct urtwn_softc *sc = arg; 1614 1615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1616 1617 if (sc->sc_dying) 1618 return; 1619 1620 /* Do it in a process context. */ 1621 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1622 } 1623 1624 /* ARGSUSED */ 1625 static void 1626 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1627 { 1628 struct r92c_fw_cmd_rssi cmd; 1629 1630 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1631 1632 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1633 goto restart_timer; 1634 1635 mutex_enter(&sc->sc_write_mtx); 1636 if (sc->avg_pwdb != -1) { 1637 /* Indicate Rx signal strength to FW for rate adaptation. */ 1638 memset(&cmd, 0, sizeof(cmd)); 1639 cmd.macid = 0; /* BSS. */ 1640 cmd.pwdb = sc->avg_pwdb; 1641 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1642 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1643 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1644 } 1645 1646 /* Do temperature compensation. */ 1647 urtwn_temp_calib(sc); 1648 mutex_exit(&sc->sc_write_mtx); 1649 1650 restart_timer: 1651 if (!sc->sc_dying) { 1652 /* Restart calibration timer. */ 1653 callout_schedule(&sc->sc_calib_to, hz); 1654 } 1655 } 1656 1657 static void 1658 urtwn_next_scan(void *arg) 1659 { 1660 struct urtwn_softc *sc = arg; 1661 int s; 1662 1663 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1664 1665 if (sc->sc_dying) 1666 return; 1667 1668 s = splnet(); 1669 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1670 ieee80211_next_scan(&sc->sc_ic); 1671 splx(s); 1672 } 1673 1674 static void 1675 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1676 { 1677 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1678 ether_sprintf(ni->ni_macaddr))); 1679 /* start with lowest Tx rate */ 1680 ni->ni_txrate = 0; 1681 } 1682 1683 static int 1684 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1685 { 1686 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1687 struct urtwn_cmd_newstate cmd; 1688 1689 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1690 device_xname(sc->sc_dev), __func__, 1691 ieee80211_state_name[nstate], nstate, arg)); 1692 1693 callout_stop(&sc->sc_scan_to); 1694 callout_stop(&sc->sc_calib_to); 1695 1696 /* Do it in a process context. */ 1697 cmd.state = nstate; 1698 cmd.arg = arg; 1699 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1700 return 0; 1701 } 1702 1703 static void 1704 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1705 { 1706 struct urtwn_cmd_newstate *cmd = arg; 1707 struct ieee80211com *ic = &sc->sc_ic; 1708 struct ieee80211_node *ni; 1709 enum ieee80211_state ostate = ic->ic_state; 1710 enum ieee80211_state nstate = cmd->state; 1711 uint32_t reg; 1712 uint8_t sifs_time, msr; 1713 int s; 1714 1715 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1716 device_xname(sc->sc_dev), __func__, 1717 ieee80211_state_name[ostate], ostate, 1718 ieee80211_state_name[nstate], nstate)); 1719 1720 s = splnet(); 1721 mutex_enter(&sc->sc_write_mtx); 1722 1723 callout_stop(&sc->sc_scan_to); 1724 callout_stop(&sc->sc_calib_to); 1725 1726 switch (ostate) { 1727 case IEEE80211_S_INIT: 1728 break; 1729 1730 case IEEE80211_S_SCAN: 1731 if (nstate != IEEE80211_S_SCAN) { 1732 /* 1733 * End of scanning 1734 */ 1735 /* flush 4-AC Queue after site_survey */ 1736 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1737 1738 /* Allow Rx from our BSSID only. */ 1739 urtwn_write_4(sc, R92C_RCR, 1740 urtwn_read_4(sc, R92C_RCR) | 1741 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1742 } 1743 break; 1744 1745 case IEEE80211_S_AUTH: 1746 case IEEE80211_S_ASSOC: 1747 break; 1748 1749 case IEEE80211_S_RUN: 1750 /* Turn link LED off. */ 1751 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1752 1753 /* Set media status to 'No Link'. */ 1754 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1755 1756 /* Stop Rx of data frames. */ 1757 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1758 1759 /* Reset TSF. */ 1760 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1761 1762 /* Disable TSF synchronization. */ 1763 urtwn_write_1(sc, R92C_BCN_CTRL, 1764 urtwn_read_1(sc, R92C_BCN_CTRL) | 1765 R92C_BCN_CTRL_DIS_TSF_UDT0); 1766 1767 /* Back to 20MHz mode */ 1768 urtwn_set_chan(sc, ic->ic_curchan, 1769 IEEE80211_HTINFO_2NDCHAN_NONE); 1770 1771 if (ic->ic_opmode == IEEE80211_M_IBSS || 1772 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1773 /* Stop BCN */ 1774 urtwn_write_1(sc, R92C_BCN_CTRL, 1775 urtwn_read_1(sc, R92C_BCN_CTRL) & 1776 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1777 } 1778 1779 /* Reset EDCA parameters. */ 1780 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1781 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1782 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1783 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1784 1785 /* flush all cam entries */ 1786 urtwn_cam_init(sc); 1787 break; 1788 } 1789 1790 switch (nstate) { 1791 case IEEE80211_S_INIT: 1792 /* Turn link LED off. */ 1793 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1794 break; 1795 1796 case IEEE80211_S_SCAN: 1797 if (ostate != IEEE80211_S_SCAN) { 1798 /* 1799 * Begin of scanning 1800 */ 1801 1802 /* Set gain for scanning. */ 1803 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1804 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1805 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1806 1807 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1808 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1809 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1810 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1811 } 1812 1813 /* Set media status to 'No Link'. */ 1814 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1815 1816 /* Allow Rx from any BSSID. */ 1817 urtwn_write_4(sc, R92C_RCR, 1818 urtwn_read_4(sc, R92C_RCR) & 1819 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1820 1821 /* Stop Rx of data frames. */ 1822 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1823 1824 /* Disable update TSF */ 1825 urtwn_write_1(sc, R92C_BCN_CTRL, 1826 urtwn_read_1(sc, R92C_BCN_CTRL) | 1827 R92C_BCN_CTRL_DIS_TSF_UDT0); 1828 } 1829 1830 /* Make link LED blink during scan. */ 1831 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1832 1833 /* Pause AC Tx queues. */ 1834 urtwn_write_1(sc, R92C_TXPAUSE, 1835 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1836 1837 urtwn_set_chan(sc, ic->ic_curchan, 1838 IEEE80211_HTINFO_2NDCHAN_NONE); 1839 1840 /* Start periodic scan. */ 1841 if (!sc->sc_dying) 1842 callout_schedule(&sc->sc_scan_to, hz / 5); 1843 break; 1844 1845 case IEEE80211_S_AUTH: 1846 /* Set initial gain under link. */ 1847 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1848 #ifdef doaslinux 1849 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1850 #else 1851 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1852 #endif 1853 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1854 1855 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1856 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1857 #ifdef doaslinux 1858 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1859 #else 1860 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1861 #endif 1862 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1863 } 1864 1865 /* Set media status to 'No Link'. */ 1866 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1867 1868 /* Allow Rx from any BSSID. */ 1869 urtwn_write_4(sc, R92C_RCR, 1870 urtwn_read_4(sc, R92C_RCR) & 1871 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1872 1873 urtwn_set_chan(sc, ic->ic_curchan, 1874 IEEE80211_HTINFO_2NDCHAN_NONE); 1875 break; 1876 1877 case IEEE80211_S_ASSOC: 1878 break; 1879 1880 case IEEE80211_S_RUN: 1881 ni = ic->ic_bss; 1882 1883 /* XXX: Set 20MHz mode */ 1884 urtwn_set_chan(sc, ic->ic_curchan, 1885 IEEE80211_HTINFO_2NDCHAN_NONE); 1886 1887 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1888 /* Back to 20MHz mode */ 1889 urtwn_set_chan(sc, ic->ic_curchan, 1890 IEEE80211_HTINFO_2NDCHAN_NONE); 1891 1892 /* Set media status to 'No Link'. */ 1893 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1894 1895 /* Enable Rx of data frames. */ 1896 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1897 1898 /* Allow Rx from any BSSID. */ 1899 urtwn_write_4(sc, R92C_RCR, 1900 urtwn_read_4(sc, R92C_RCR) & 1901 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1902 1903 /* Accept Rx data/control/management frames */ 1904 urtwn_write_4(sc, R92C_RCR, 1905 urtwn_read_4(sc, R92C_RCR) | 1906 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1907 1908 /* Turn link LED on. */ 1909 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1910 break; 1911 } 1912 1913 /* Set media status to 'Associated'. */ 1914 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1915 1916 /* Set BSSID. */ 1917 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1918 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1919 1920 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1921 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1922 } else { 1923 /* 802.11b/g */ 1924 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1925 } 1926 1927 /* Enable Rx of data frames. */ 1928 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1929 1930 /* Set beacon interval. */ 1931 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1932 1933 msr = urtwn_read_1(sc, R92C_MSR); 1934 msr &= R92C_MSR_MASK; 1935 switch (ic->ic_opmode) { 1936 case IEEE80211_M_STA: 1937 /* Allow Rx from our BSSID only. */ 1938 urtwn_write_4(sc, R92C_RCR, 1939 urtwn_read_4(sc, R92C_RCR) | 1940 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1941 1942 /* Enable TSF synchronization. */ 1943 urtwn_tsf_sync_enable(sc); 1944 1945 msr |= R92C_MSR_INFRA; 1946 break; 1947 case IEEE80211_M_HOSTAP: 1948 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1949 1950 /* Allow Rx from any BSSID. */ 1951 urtwn_write_4(sc, R92C_RCR, 1952 urtwn_read_4(sc, R92C_RCR) & 1953 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1954 1955 /* Reset TSF timer to zero. */ 1956 reg = urtwn_read_4(sc, R92C_TCR); 1957 reg &= ~0x01; 1958 urtwn_write_4(sc, R92C_TCR, reg); 1959 reg |= 0x01; 1960 urtwn_write_4(sc, R92C_TCR, reg); 1961 1962 msr |= R92C_MSR_AP; 1963 break; 1964 default: 1965 msr |= R92C_MSR_ADHOC; 1966 break; 1967 } 1968 urtwn_write_1(sc, R92C_MSR, msr); 1969 1970 sifs_time = 10; 1971 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1972 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1973 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1974 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1975 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1976 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1977 1978 /* Intialize rate adaptation. */ 1979 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1980 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 1981 else 1982 urtwn_ra_init(sc); 1983 1984 /* Turn link LED on. */ 1985 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1986 1987 /* Reset average RSSI. */ 1988 sc->avg_pwdb = -1; 1989 1990 /* Reset temperature calibration state machine. */ 1991 sc->thcal_state = 0; 1992 sc->thcal_lctemp = 0; 1993 1994 /* Start periodic calibration. */ 1995 if (!sc->sc_dying) 1996 callout_schedule(&sc->sc_calib_to, hz); 1997 break; 1998 } 1999 2000 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2001 2002 mutex_exit(&sc->sc_write_mtx); 2003 splx(s); 2004 } 2005 2006 static int 2007 urtwn_wme_update(struct ieee80211com *ic) 2008 { 2009 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2010 2011 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2012 2013 /* don't override default WME values if WME is not actually enabled */ 2014 if (!(ic->ic_flags & IEEE80211_F_WME)) 2015 return 0; 2016 2017 /* Do it in a process context. */ 2018 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2019 return 0; 2020 } 2021 2022 static void 2023 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2024 { 2025 static const uint16_t ac2reg[WME_NUM_AC] = { 2026 R92C_EDCA_BE_PARAM, 2027 R92C_EDCA_BK_PARAM, 2028 R92C_EDCA_VI_PARAM, 2029 R92C_EDCA_VO_PARAM 2030 }; 2031 struct ieee80211com *ic = &sc->sc_ic; 2032 const struct wmeParams *wmep; 2033 int ac, aifs, slottime; 2034 int s; 2035 2036 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2037 __func__)); 2038 2039 s = splnet(); 2040 mutex_enter(&sc->sc_write_mtx); 2041 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2042 for (ac = 0; ac < WME_NUM_AC; ac++) { 2043 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2044 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2045 aifs = wmep->wmep_aifsn * slottime + 10; 2046 urtwn_write_4(sc, ac2reg[ac], 2047 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2048 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2049 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2050 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2051 } 2052 mutex_exit(&sc->sc_write_mtx); 2053 splx(s); 2054 } 2055 2056 static void 2057 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2058 { 2059 int pwdb; 2060 2061 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2062 device_xname(sc->sc_dev), __func__, rate, rssi)); 2063 2064 /* Convert antenna signal to percentage. */ 2065 if (rssi <= -100 || rssi >= 20) 2066 pwdb = 0; 2067 else if (rssi >= 0) 2068 pwdb = 100; 2069 else 2070 pwdb = 100 + rssi; 2071 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2072 if (rate <= 3) { 2073 /* CCK gain is smaller than OFDM/MCS gain. */ 2074 pwdb += 6; 2075 if (pwdb > 100) 2076 pwdb = 100; 2077 if (pwdb <= 14) 2078 pwdb -= 4; 2079 else if (pwdb <= 26) 2080 pwdb -= 8; 2081 else if (pwdb <= 34) 2082 pwdb -= 6; 2083 else if (pwdb <= 42) 2084 pwdb -= 2; 2085 } 2086 } 2087 if (sc->avg_pwdb == -1) /* Init. */ 2088 sc->avg_pwdb = pwdb; 2089 else if (sc->avg_pwdb < pwdb) 2090 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2091 else 2092 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2093 2094 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2095 device_xname(sc->sc_dev), __func__, 2096 rate, rssi, pwdb, sc->avg_pwdb)); 2097 } 2098 2099 static int8_t 2100 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2101 { 2102 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2103 struct r92c_rx_phystat *phy; 2104 struct r92c_rx_cck *cck; 2105 uint8_t rpt; 2106 int8_t rssi; 2107 2108 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2109 __func__, rate)); 2110 2111 if (rate <= 3) { 2112 cck = (struct r92c_rx_cck *)physt; 2113 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2114 rpt = (cck->agc_rpt >> 5) & 0x3; 2115 rssi = (cck->agc_rpt & 0x1f) << 1; 2116 } else { 2117 rpt = (cck->agc_rpt >> 6) & 0x3; 2118 rssi = cck->agc_rpt & 0x3e; 2119 } 2120 rssi = cckoff[rpt] - rssi; 2121 } else { /* OFDM/HT. */ 2122 phy = (struct r92c_rx_phystat *)physt; 2123 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2124 } 2125 return rssi; 2126 } 2127 2128 static int8_t 2129 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2130 { 2131 struct r92c_rx_phystat *phy; 2132 struct r88e_rx_cck *cck; 2133 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2134 int8_t rssi; 2135 2136 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2137 __func__, rate)); 2138 2139 rssi = 0; 2140 if (rate <= 3) { 2141 cck = (struct r88e_rx_cck *)physt; 2142 cck_agc_rpt = cck->agc_rpt; 2143 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2144 vga_idx = cck_agc_rpt & 0x1f; 2145 switch (lna_idx) { 2146 case 7: 2147 if (vga_idx <= 27) 2148 rssi = -100 + 2* (27 - vga_idx); 2149 else 2150 rssi = -100; 2151 break; 2152 case 6: 2153 rssi = -48 + 2 * (2 - vga_idx); 2154 break; 2155 case 5: 2156 rssi = -42 + 2 * (7 - vga_idx); 2157 break; 2158 case 4: 2159 rssi = -36 + 2 * (7 - vga_idx); 2160 break; 2161 case 3: 2162 rssi = -24 + 2 * (7 - vga_idx); 2163 break; 2164 case 2: 2165 rssi = -12 + 2 * (5 - vga_idx); 2166 break; 2167 case 1: 2168 rssi = 8 - (2 * vga_idx); 2169 break; 2170 case 0: 2171 rssi = 14 - (2 * vga_idx); 2172 break; 2173 } 2174 rssi += 6; 2175 } else { /* OFDM/HT. */ 2176 phy = (struct r92c_rx_phystat *)physt; 2177 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2178 } 2179 return rssi; 2180 } 2181 2182 static void 2183 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2184 { 2185 struct ieee80211com *ic = &sc->sc_ic; 2186 struct ifnet *ifp = ic->ic_ifp; 2187 struct ieee80211_frame *wh; 2188 struct ieee80211_node *ni; 2189 struct r92c_rx_stat *stat; 2190 uint32_t rxdw0, rxdw3; 2191 struct mbuf *m; 2192 uint8_t rate; 2193 int8_t rssi = 0; 2194 int s, infosz; 2195 2196 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2197 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2198 2199 stat = (struct r92c_rx_stat *)buf; 2200 rxdw0 = le32toh(stat->rxdw0); 2201 rxdw3 = le32toh(stat->rxdw3); 2202 2203 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2204 /* 2205 * This should not happen since we setup our Rx filter 2206 * to not receive these frames. 2207 */ 2208 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2209 device_xname(sc->sc_dev), __func__)); 2210 ifp->if_ierrors++; 2211 return; 2212 } 2213 /* 2214 * XXX: This will drop most control packets. Do we really 2215 * want this in IEEE80211_M_MONITOR mode? 2216 */ 2217 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2218 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2219 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2220 device_xname(sc->sc_dev), __func__, pktlen)); 2221 ic->ic_stats.is_rx_tooshort++; 2222 ifp->if_ierrors++; 2223 return; 2224 } 2225 if (__predict_false(pktlen > MCLBYTES)) { 2226 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2227 device_xname(sc->sc_dev), __func__, pktlen)); 2228 ifp->if_ierrors++; 2229 return; 2230 } 2231 2232 rate = MS(rxdw3, R92C_RXDW3_RATE); 2233 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2234 2235 /* Get RSSI from PHY status descriptor if present. */ 2236 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2237 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2238 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2239 else 2240 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2241 /* Update our average RSSI. */ 2242 urtwn_update_avgrssi(sc, rate, rssi); 2243 } 2244 2245 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2246 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2247 2248 MGETHDR(m, M_DONTWAIT, MT_DATA); 2249 if (__predict_false(m == NULL)) { 2250 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2251 ic->ic_stats.is_rx_nobuf++; 2252 ifp->if_ierrors++; 2253 return; 2254 } 2255 if (pktlen > (int)MHLEN) { 2256 MCLGET(m, M_DONTWAIT); 2257 if (__predict_false(!(m->m_flags & M_EXT))) { 2258 aprint_error_dev(sc->sc_dev, 2259 "couldn't allocate rx mbuf cluster\n"); 2260 m_freem(m); 2261 ic->ic_stats.is_rx_nobuf++; 2262 ifp->if_ierrors++; 2263 return; 2264 } 2265 } 2266 2267 /* Finalize mbuf. */ 2268 m_set_rcvif(m, ifp); 2269 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2270 memcpy(mtod(m, uint8_t *), wh, pktlen); 2271 m->m_pkthdr.len = m->m_len = pktlen; 2272 2273 s = splnet(); 2274 if (__predict_false(sc->sc_drvbpf != NULL)) { 2275 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2276 2277 tap->wr_flags = 0; 2278 if (!(rxdw3 & R92C_RXDW3_HT)) { 2279 switch (rate) { 2280 /* CCK. */ 2281 case 0: tap->wr_rate = 2; break; 2282 case 1: tap->wr_rate = 4; break; 2283 case 2: tap->wr_rate = 11; break; 2284 case 3: tap->wr_rate = 22; break; 2285 /* OFDM. */ 2286 case 4: tap->wr_rate = 12; break; 2287 case 5: tap->wr_rate = 18; break; 2288 case 6: tap->wr_rate = 24; break; 2289 case 7: tap->wr_rate = 36; break; 2290 case 8: tap->wr_rate = 48; break; 2291 case 9: tap->wr_rate = 72; break; 2292 case 10: tap->wr_rate = 96; break; 2293 case 11: tap->wr_rate = 108; break; 2294 } 2295 } else if (rate >= 12) { /* MCS0~15. */ 2296 /* Bit 7 set means HT MCS instead of rate. */ 2297 tap->wr_rate = 0x80 | (rate - 12); 2298 } 2299 tap->wr_dbm_antsignal = rssi; 2300 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2301 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2302 2303 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2304 } 2305 2306 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2307 2308 /* push the frame up to the 802.11 stack */ 2309 ieee80211_input(ic, m, ni, rssi, 0); 2310 2311 /* Node is no longer needed. */ 2312 ieee80211_free_node(ni); 2313 2314 splx(s); 2315 } 2316 2317 static void 2318 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2319 { 2320 struct urtwn_rx_data *data = priv; 2321 struct urtwn_softc *sc = data->sc; 2322 struct r92c_rx_stat *stat; 2323 uint32_t rxdw0; 2324 uint8_t *buf; 2325 int len, totlen, pktlen, infosz, npkts; 2326 2327 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2328 device_xname(sc->sc_dev), __func__, status)); 2329 2330 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2331 if (status == USBD_STALLED) 2332 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2333 else if (status != USBD_CANCELLED) 2334 goto resubmit; 2335 return; 2336 } 2337 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2338 2339 if (__predict_false(len < (int)sizeof(*stat))) { 2340 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2341 device_xname(sc->sc_dev), __func__, len)); 2342 goto resubmit; 2343 } 2344 buf = data->buf; 2345 2346 /* Get the number of encapsulated frames. */ 2347 stat = (struct r92c_rx_stat *)buf; 2348 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2349 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2350 device_xname(sc->sc_dev), __func__, npkts)); 2351 2352 /* Process all of them. */ 2353 while (npkts-- > 0) { 2354 if (__predict_false(len < (int)sizeof(*stat))) { 2355 DPRINTFN(DBG_RX, 2356 ("%s: %s: len(%d) is short than header\n", 2357 device_xname(sc->sc_dev), __func__, len)); 2358 break; 2359 } 2360 stat = (struct r92c_rx_stat *)buf; 2361 rxdw0 = le32toh(stat->rxdw0); 2362 2363 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2364 if (__predict_false(pktlen == 0)) { 2365 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2366 device_xname(sc->sc_dev), __func__)); 2367 break; 2368 } 2369 2370 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2371 2372 /* Make sure everything fits in xfer. */ 2373 totlen = sizeof(*stat) + infosz + pktlen; 2374 if (__predict_false(totlen > len)) { 2375 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2376 device_xname(sc->sc_dev), __func__, totlen, 2377 (int)sizeof(*stat), infosz, pktlen, len)); 2378 break; 2379 } 2380 2381 /* Process 802.11 frame. */ 2382 urtwn_rx_frame(sc, buf, pktlen); 2383 2384 /* Next chunk is 128-byte aligned. */ 2385 totlen = roundup2(totlen, 128); 2386 buf += totlen; 2387 len -= totlen; 2388 } 2389 2390 resubmit: 2391 /* Setup a new transfer. */ 2392 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2393 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2394 (void)usbd_transfer(xfer); 2395 } 2396 2397 static void 2398 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2399 { 2400 struct urtwn_tx_data *data = priv; 2401 struct urtwn_softc *sc = data->sc; 2402 struct ifnet *ifp = &sc->sc_if; 2403 size_t pidx = data->pidx; 2404 int s; 2405 2406 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2407 device_xname(sc->sc_dev), __func__, status)); 2408 2409 mutex_enter(&sc->sc_tx_mtx); 2410 /* Put this Tx buffer back to our free list. */ 2411 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2412 mutex_exit(&sc->sc_tx_mtx); 2413 2414 s = splnet(); 2415 sc->tx_timer = 0; 2416 ifp->if_flags &= ~IFF_OACTIVE; 2417 2418 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2419 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2420 if (status == USBD_STALLED) { 2421 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2422 usbd_clear_endpoint_stall_async(pipe); 2423 } 2424 ifp->if_oerrors++; 2425 } 2426 splx(s); 2427 return; 2428 } 2429 2430 ifp->if_opackets++; 2431 urtwn_start(ifp); 2432 2433 splx(s); 2434 } 2435 2436 static int 2437 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2438 struct urtwn_tx_data *data) 2439 { 2440 struct ieee80211com *ic = &sc->sc_ic; 2441 struct ieee80211_frame *wh; 2442 struct ieee80211_key *k = NULL; 2443 struct r92c_tx_desc *txd; 2444 size_t i, padsize, xferlen; 2445 uint16_t seq, sum; 2446 uint8_t raid, type, tid; 2447 int s, hasqos, error; 2448 2449 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2450 2451 wh = mtod(m, struct ieee80211_frame *); 2452 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2453 2454 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2455 k = ieee80211_crypto_encap(ic, ni, m); 2456 if (k == NULL) 2457 return ENOBUFS; 2458 2459 /* packet header may have moved, reset our local pointer */ 2460 wh = mtod(m, struct ieee80211_frame *); 2461 } 2462 2463 if (__predict_false(sc->sc_drvbpf != NULL)) { 2464 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2465 2466 tap->wt_flags = 0; 2467 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2468 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2469 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2470 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2471 2472 /* XXX: set tap->wt_rate? */ 2473 2474 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2475 } 2476 2477 /* non-qos data frames */ 2478 tid = R92C_TXDW1_QSEL_BE; 2479 if ((hasqos = ieee80211_has_qos(wh))) { 2480 /* data frames in 11n mode */ 2481 struct ieee80211_qosframe *qwh = (void *)wh; 2482 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2483 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2484 tid = R92C_TXDW1_QSEL_MGNT; 2485 } 2486 2487 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2488 padsize = 8; 2489 else 2490 padsize = 0; 2491 2492 /* Fill Tx descriptor. */ 2493 txd = (struct r92c_tx_desc *)data->buf; 2494 memset(txd, 0, sizeof(*txd) + padsize); 2495 2496 txd->txdw0 |= htole32( 2497 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2498 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2499 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2500 2501 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2502 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2503 2504 /* fix pad field */ 2505 if (padsize > 0) { 2506 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2507 device_xname(sc->sc_dev), __func__, padsize)); 2508 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2509 } 2510 2511 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2512 type == IEEE80211_FC0_TYPE_DATA) { 2513 if (ic->ic_curmode == IEEE80211_MODE_11B) 2514 raid = R92C_RAID_11B; 2515 else 2516 raid = R92C_RAID_11BG; 2517 DPRINTFN(DBG_TX, 2518 ("%s: %s: data packet: tid=%d, raid=%d\n", 2519 device_xname(sc->sc_dev), __func__, tid, raid)); 2520 2521 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 2522 txd->txdw1 |= htole32( 2523 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2524 SM(R92C_TXDW1_QSEL, tid) | 2525 SM(R92C_TXDW1_RAID, raid) | 2526 R92C_TXDW1_AGGBK); 2527 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2528 } else 2529 txd->txdw1 |= htole32( 2530 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2531 SM(R92C_TXDW1_QSEL, tid) | 2532 SM(R92C_TXDW1_RAID, raid) | 2533 R92C_TXDW1_AGGBK); 2534 2535 if (hasqos) { 2536 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2537 } 2538 2539 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2540 /* for 11g */ 2541 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2542 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2543 R92C_TXDW4_HWRTSEN); 2544 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2545 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2546 R92C_TXDW4_HWRTSEN); 2547 } 2548 } 2549 /* Send RTS at OFDM24. */ 2550 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2551 txd->txdw5 |= htole32(0x0001ff00); 2552 /* Send data at OFDM54. */ 2553 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2554 txd->txdw5 |= htole32(0x13 & 0x3f); 2555 else 2556 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2557 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2558 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2559 device_xname(sc->sc_dev), __func__)); 2560 txd->txdw1 |= htole32( 2561 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2562 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2563 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2564 2565 /* Force CCK1. */ 2566 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2567 /* Use 1Mbps */ 2568 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2569 } else { 2570 /* broadcast or multicast packets */ 2571 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2572 device_xname(sc->sc_dev), __func__)); 2573 txd->txdw1 |= htole32( 2574 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2575 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2576 2577 /* Force CCK1. */ 2578 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2579 /* Use 1Mbps */ 2580 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2581 } 2582 2583 /* Set sequence number */ 2584 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2585 txd->txdseq |= htole16(seq); 2586 2587 if (!hasqos) { 2588 /* Use HW sequence numbering for non-QoS frames. */ 2589 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2590 txd->txdseq |= htole16(0x8000); /* WTF? */ 2591 } 2592 2593 /* Compute Tx descriptor checksum. */ 2594 sum = 0; 2595 for (i = 0; i < sizeof(*txd) / 2; i++) 2596 sum ^= ((uint16_t *)txd)[i]; 2597 txd->txdsum = sum; /* NB: already little endian. */ 2598 2599 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2600 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2601 2602 s = splnet(); 2603 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2604 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2605 urtwn_txeof); 2606 error = usbd_transfer(data->xfer); 2607 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2608 error != USBD_IN_PROGRESS)) { 2609 splx(s); 2610 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2611 device_xname(sc->sc_dev), __func__, error)); 2612 return error; 2613 } 2614 splx(s); 2615 return 0; 2616 } 2617 2618 struct urtwn_tx_data * 2619 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2620 { 2621 struct urtwn_tx_data *data = NULL; 2622 2623 mutex_enter(&sc->sc_tx_mtx); 2624 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2625 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2626 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2627 } 2628 mutex_exit(&sc->sc_tx_mtx); 2629 2630 return data; 2631 } 2632 2633 static void 2634 urtwn_start(struct ifnet *ifp) 2635 { 2636 struct urtwn_softc *sc = ifp->if_softc; 2637 struct ieee80211com *ic = &sc->sc_ic; 2638 struct urtwn_tx_data *data; 2639 struct ether_header *eh; 2640 struct ieee80211_node *ni; 2641 struct mbuf *m; 2642 2643 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2644 2645 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2646 return; 2647 2648 data = NULL; 2649 for (;;) { 2650 /* Send pending management frames first. */ 2651 IF_POLL(&ic->ic_mgtq, m); 2652 if (m != NULL) { 2653 /* Use AC_VO for management frames. */ 2654 2655 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2656 2657 if (data == NULL) { 2658 ifp->if_flags |= IFF_OACTIVE; 2659 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2660 device_xname(sc->sc_dev))); 2661 return; 2662 } 2663 IF_DEQUEUE(&ic->ic_mgtq, m); 2664 ni = M_GETCTX(m, struct ieee80211_node *); 2665 M_CLEARCTX(m); 2666 goto sendit; 2667 } 2668 if (ic->ic_state != IEEE80211_S_RUN) 2669 break; 2670 2671 /* Encapsulate and send data frames. */ 2672 IFQ_POLL(&ifp->if_snd, m); 2673 if (m == NULL) 2674 break; 2675 2676 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2677 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2678 uint8_t qid = WME_AC_BE; 2679 if (ieee80211_has_qos(wh)) { 2680 /* data frames in 11n mode */ 2681 struct ieee80211_qosframe *qwh = (void *)wh; 2682 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2683 qid = TID_TO_WME_AC(tid); 2684 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2685 qid = WME_AC_VO; 2686 } 2687 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2688 2689 if (data == NULL) { 2690 ifp->if_flags |= IFF_OACTIVE; 2691 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2692 device_xname(sc->sc_dev))); 2693 return; 2694 } 2695 IFQ_DEQUEUE(&ifp->if_snd, m); 2696 2697 if (m->m_len < (int)sizeof(*eh) && 2698 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2699 ifp->if_oerrors++; 2700 continue; 2701 } 2702 eh = mtod(m, struct ether_header *); 2703 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2704 if (ni == NULL) { 2705 m_freem(m); 2706 ifp->if_oerrors++; 2707 continue; 2708 } 2709 2710 bpf_mtap(ifp, m); 2711 2712 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2713 ieee80211_free_node(ni); 2714 ifp->if_oerrors++; 2715 continue; 2716 } 2717 sendit: 2718 bpf_mtap3(ic->ic_rawbpf, m); 2719 2720 if (urtwn_tx(sc, m, ni, data) != 0) { 2721 m_freem(m); 2722 ieee80211_free_node(ni); 2723 ifp->if_oerrors++; 2724 continue; 2725 } 2726 m_freem(m); 2727 ieee80211_free_node(ni); 2728 sc->tx_timer = 5; 2729 ifp->if_timer = 1; 2730 } 2731 } 2732 2733 static void 2734 urtwn_watchdog(struct ifnet *ifp) 2735 { 2736 struct urtwn_softc *sc = ifp->if_softc; 2737 2738 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2739 2740 ifp->if_timer = 0; 2741 2742 if (sc->tx_timer > 0) { 2743 if (--sc->tx_timer == 0) { 2744 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2745 /* urtwn_init(ifp); XXX needs a process context! */ 2746 ifp->if_oerrors++; 2747 return; 2748 } 2749 ifp->if_timer = 1; 2750 } 2751 ieee80211_watchdog(&sc->sc_ic); 2752 } 2753 2754 static int 2755 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2756 { 2757 struct urtwn_softc *sc = ifp->if_softc; 2758 struct ieee80211com *ic = &sc->sc_ic; 2759 int s, error = 0; 2760 2761 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2762 device_xname(sc->sc_dev), __func__, cmd, data)); 2763 2764 s = splnet(); 2765 2766 switch (cmd) { 2767 case SIOCSIFFLAGS: 2768 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2769 break; 2770 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2771 case IFF_UP | IFF_RUNNING: 2772 break; 2773 case IFF_UP: 2774 urtwn_init(ifp); 2775 break; 2776 case IFF_RUNNING: 2777 urtwn_stop(ifp, 1); 2778 break; 2779 case 0: 2780 break; 2781 } 2782 break; 2783 2784 case SIOCADDMULTI: 2785 case SIOCDELMULTI: 2786 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2787 /* setup multicast filter, etc */ 2788 error = 0; 2789 } 2790 break; 2791 2792 default: 2793 error = ieee80211_ioctl(ic, cmd, data); 2794 break; 2795 } 2796 if (error == ENETRESET) { 2797 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2798 (IFF_UP | IFF_RUNNING) && 2799 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2800 urtwn_init(ifp); 2801 } 2802 error = 0; 2803 } 2804 2805 splx(s); 2806 2807 return error; 2808 } 2809 2810 static __inline int 2811 urtwn_power_on(struct urtwn_softc *sc) 2812 { 2813 2814 return sc->sc_power_on(sc); 2815 } 2816 2817 static int 2818 urtwn_r92c_power_on(struct urtwn_softc *sc) 2819 { 2820 uint32_t reg; 2821 int ntries; 2822 2823 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2824 2825 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2826 2827 /* Wait for autoload done bit. */ 2828 for (ntries = 0; ntries < 1000; ntries++) { 2829 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2830 break; 2831 DELAY(5); 2832 } 2833 if (ntries == 1000) { 2834 aprint_error_dev(sc->sc_dev, 2835 "timeout waiting for chip autoload\n"); 2836 return ETIMEDOUT; 2837 } 2838 2839 /* Unlock ISO/CLK/Power control register. */ 2840 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2841 /* Move SPS into PWM mode. */ 2842 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2843 DELAY(100); 2844 2845 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2846 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2847 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2848 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2849 DELAY(100); 2850 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2851 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2852 ~R92C_SYS_ISO_CTRL_MD2PP); 2853 } 2854 2855 /* Auto enable WLAN. */ 2856 urtwn_write_2(sc, R92C_APS_FSMCO, 2857 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2858 for (ntries = 0; ntries < 1000; ntries++) { 2859 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2860 R92C_APS_FSMCO_APFM_ONMAC)) 2861 break; 2862 DELAY(5); 2863 } 2864 if (ntries == 1000) { 2865 aprint_error_dev(sc->sc_dev, 2866 "timeout waiting for MAC auto ON\n"); 2867 return ETIMEDOUT; 2868 } 2869 2870 /* Enable radio, GPIO and LED functions. */ 2871 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2872 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2873 urtwn_write_2(sc, R92C_APS_FSMCO, 2874 R92C_APS_FSMCO_AFSM_HSUS | 2875 R92C_APS_FSMCO_PDN_EN | 2876 R92C_APS_FSMCO_PFM_ALDN); 2877 2878 /* Release RF digital isolation. */ 2879 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2880 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2881 2882 /* Initialize MAC. */ 2883 urtwn_write_1(sc, R92C_APSD_CTRL, 2884 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2885 for (ntries = 0; ntries < 200; ntries++) { 2886 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2887 R92C_APSD_CTRL_OFF_STATUS)) 2888 break; 2889 DELAY(5); 2890 } 2891 if (ntries == 200) { 2892 aprint_error_dev(sc->sc_dev, 2893 "timeout waiting for MAC initialization\n"); 2894 return ETIMEDOUT; 2895 } 2896 2897 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2898 reg = urtwn_read_2(sc, R92C_CR); 2899 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2900 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2901 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2902 R92C_CR_ENSEC; 2903 urtwn_write_2(sc, R92C_CR, reg); 2904 2905 urtwn_write_1(sc, 0xfe10, 0x19); 2906 return 0; 2907 } 2908 2909 static int 2910 urtwn_r88e_power_on(struct urtwn_softc *sc) 2911 { 2912 uint32_t reg; 2913 uint8_t val; 2914 int ntries; 2915 2916 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2917 2918 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2919 2920 /* Wait for power ready bit. */ 2921 for (ntries = 0; ntries < 5000; ntries++) { 2922 val = urtwn_read_1(sc, 0x6) & 0x2; 2923 if (val == 0x2) 2924 break; 2925 DELAY(10); 2926 } 2927 if (ntries == 5000) { 2928 aprint_error_dev(sc->sc_dev, 2929 "timeout waiting for chip power up\n"); 2930 return ETIMEDOUT; 2931 } 2932 2933 /* Reset BB. */ 2934 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2935 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2936 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2937 2938 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2939 2940 /* Disable HWPDN. */ 2941 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2942 2943 /* Disable WL suspend. */ 2944 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2945 2946 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2947 for (ntries = 0; ntries < 5000; ntries++) { 2948 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2949 break; 2950 DELAY(10); 2951 } 2952 if (ntries == 5000) 2953 return ETIMEDOUT; 2954 2955 /* Enable LDO normal mode. */ 2956 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2957 2958 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2959 urtwn_write_2(sc, R92C_CR, 0); 2960 reg = urtwn_read_2(sc, R92C_CR); 2961 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2962 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2963 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2964 urtwn_write_2(sc, R92C_CR, reg); 2965 2966 return 0; 2967 } 2968 2969 static int 2970 urtwn_llt_init(struct urtwn_softc *sc) 2971 { 2972 size_t i, page_count, pktbuf_count; 2973 int error; 2974 2975 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2976 2977 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2978 2979 page_count = (sc->chip & URTWN_CHIP_88E) ? 2980 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2981 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2982 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2983 2984 /* Reserve pages [0; page_count]. */ 2985 for (i = 0; i < page_count; i++) { 2986 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2987 return error; 2988 } 2989 /* NB: 0xff indicates end-of-list. */ 2990 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2991 return error; 2992 /* 2993 * Use pages [page_count + 1; pktbuf_count - 1] 2994 * as ring buffer. 2995 */ 2996 for (++i; i < pktbuf_count - 1; i++) { 2997 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2998 return error; 2999 } 3000 /* Make the last page point to the beginning of the ring buffer. */ 3001 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3002 return error; 3003 } 3004 3005 static void 3006 urtwn_fw_reset(struct urtwn_softc *sc) 3007 { 3008 uint16_t reg; 3009 int ntries; 3010 3011 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3012 3013 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3014 3015 /* Tell 8051 to reset itself. */ 3016 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3017 3018 /* Wait until 8051 resets by itself. */ 3019 for (ntries = 0; ntries < 100; ntries++) { 3020 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3021 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3022 return; 3023 DELAY(50); 3024 } 3025 /* Force 8051 reset. */ 3026 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3027 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3028 } 3029 3030 static void 3031 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3032 { 3033 uint16_t reg; 3034 3035 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3036 3037 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3038 3039 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3040 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3041 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3042 } 3043 3044 static int 3045 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3046 { 3047 uint32_t reg; 3048 int off, mlen, error = 0; 3049 3050 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3051 device_xname(sc->sc_dev), __func__, page, buf, len)); 3052 3053 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3054 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3055 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3056 3057 off = R92C_FW_START_ADDR; 3058 while (len > 0) { 3059 if (len > 196) 3060 mlen = 196; 3061 else if (len > 4) 3062 mlen = 4; 3063 else 3064 mlen = 1; 3065 error = urtwn_write_region(sc, off, buf, mlen); 3066 if (error != 0) 3067 break; 3068 off += mlen; 3069 buf += mlen; 3070 len -= mlen; 3071 } 3072 return error; 3073 } 3074 3075 static int 3076 urtwn_load_firmware(struct urtwn_softc *sc) 3077 { 3078 firmware_handle_t fwh; 3079 const struct r92c_fw_hdr *hdr; 3080 const char *name; 3081 u_char *fw, *ptr; 3082 size_t len; 3083 uint32_t reg; 3084 int mlen, ntries, page, error; 3085 3086 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3087 3088 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3089 3090 /* Read firmware image from the filesystem. */ 3091 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3092 name = "rtl8188eufw.bin"; 3093 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3094 URTWN_CHIP_UMC_A_CUT) 3095 name = "rtl8192cfwU.bin"; 3096 else 3097 name = "rtl8192cfw.bin"; 3098 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3099 aprint_error_dev(sc->sc_dev, 3100 "failed load firmware of file %s (error %d)\n", name, 3101 error); 3102 return error; 3103 } 3104 const size_t fwlen = len = firmware_get_size(fwh); 3105 fw = firmware_malloc(len); 3106 if (fw == NULL) { 3107 aprint_error_dev(sc->sc_dev, 3108 "failed to allocate firmware memory\n"); 3109 firmware_close(fwh); 3110 return ENOMEM; 3111 } 3112 error = firmware_read(fwh, 0, fw, len); 3113 firmware_close(fwh); 3114 if (error != 0) { 3115 aprint_error_dev(sc->sc_dev, 3116 "failed to read firmware (error %d)\n", error); 3117 firmware_free(fw, fwlen); 3118 return error; 3119 } 3120 3121 ptr = fw; 3122 hdr = (const struct r92c_fw_hdr *)ptr; 3123 /* Check if there is a valid FW header and skip it. */ 3124 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3125 (le16toh(hdr->signature) >> 4) == 0x88e || 3126 (le16toh(hdr->signature) >> 4) == 0x92c) { 3127 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3128 device_xname(sc->sc_dev), __func__, 3129 le16toh(hdr->version), le16toh(hdr->subversion), 3130 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3131 ptr += sizeof(*hdr); 3132 len -= sizeof(*hdr); 3133 } 3134 3135 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3136 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3137 urtwn_r88e_fw_reset(sc); 3138 else 3139 urtwn_fw_reset(sc); 3140 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3141 } 3142 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3143 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3144 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3145 R92C_SYS_FUNC_EN_CPUEN); 3146 } 3147 3148 /* download enabled */ 3149 urtwn_write_1(sc, R92C_MCUFWDL, 3150 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3151 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3152 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3153 3154 /* Reset the FWDL checksum. */ 3155 urtwn_write_1(sc, R92C_MCUFWDL, 3156 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3157 3158 /* download firmware */ 3159 for (page = 0; len > 0; page++) { 3160 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3161 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3162 if (error != 0) { 3163 aprint_error_dev(sc->sc_dev, 3164 "could not load firmware page %d\n", page); 3165 goto fail; 3166 } 3167 ptr += mlen; 3168 len -= mlen; 3169 } 3170 3171 /* download disable */ 3172 urtwn_write_1(sc, R92C_MCUFWDL, 3173 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3174 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3175 3176 /* Wait for checksum report. */ 3177 for (ntries = 0; ntries < 1000; ntries++) { 3178 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3179 break; 3180 DELAY(5); 3181 } 3182 if (ntries == 1000) { 3183 aprint_error_dev(sc->sc_dev, 3184 "timeout waiting for checksum report\n"); 3185 error = ETIMEDOUT; 3186 goto fail; 3187 } 3188 3189 /* Wait for firmware readiness. */ 3190 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3191 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3192 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3193 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3194 urtwn_r88e_fw_reset(sc); 3195 for (ntries = 0; ntries < 1000; ntries++) { 3196 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3197 break; 3198 DELAY(5); 3199 } 3200 if (ntries == 1000) { 3201 aprint_error_dev(sc->sc_dev, 3202 "timeout waiting for firmware readiness\n"); 3203 error = ETIMEDOUT; 3204 goto fail; 3205 } 3206 fail: 3207 firmware_free(fw, fwlen); 3208 return error; 3209 } 3210 3211 static __inline int 3212 urtwn_dma_init(struct urtwn_softc *sc) 3213 { 3214 3215 return sc->sc_dma_init(sc); 3216 } 3217 3218 static int 3219 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3220 { 3221 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3222 uint32_t reg; 3223 int error; 3224 3225 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3226 3227 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3228 3229 /* Initialize LLT table. */ 3230 error = urtwn_llt_init(sc); 3231 if (error != 0) 3232 return error; 3233 3234 /* Get Tx queues to USB endpoints mapping. */ 3235 hashq = hasnq = haslq = 0; 3236 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3237 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3238 device_xname(sc->sc_dev), __func__, reg)); 3239 if (MS(reg, R92C_USB_EP_HQ) != 0) 3240 hashq = 1; 3241 if (MS(reg, R92C_USB_EP_NQ) != 0) 3242 hasnq = 1; 3243 if (MS(reg, R92C_USB_EP_LQ) != 0) 3244 haslq = 1; 3245 nqueues = hashq + hasnq + haslq; 3246 if (nqueues == 0) 3247 return EIO; 3248 /* Get the number of pages for each queue. */ 3249 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3250 /* The remaining pages are assigned to the high priority queue. */ 3251 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3252 3253 /* Set number of pages for normal priority queue. */ 3254 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3255 urtwn_write_4(sc, R92C_RQPN, 3256 /* Set number of pages for public queue. */ 3257 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3258 /* Set number of pages for high priority queue. */ 3259 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3260 /* Set number of pages for low priority queue. */ 3261 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3262 /* Load values. */ 3263 R92C_RQPN_LD); 3264 3265 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3266 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3267 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3268 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3269 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3270 3271 /* Set queue to USB pipe mapping. */ 3272 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3273 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3274 if (nqueues == 1) { 3275 if (hashq) { 3276 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3277 } else if (hasnq) { 3278 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3279 } else { 3280 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3281 } 3282 } else if (nqueues == 2) { 3283 /* All 2-endpoints configs have a high priority queue. */ 3284 if (!hashq) { 3285 return EIO; 3286 } 3287 if (hasnq) { 3288 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3289 } else { 3290 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3291 } 3292 } else { 3293 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3294 } 3295 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3296 3297 /* Set Tx/Rx transfer page boundary. */ 3298 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3299 3300 /* Set Tx/Rx transfer page size. */ 3301 urtwn_write_1(sc, R92C_PBP, 3302 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3303 return 0; 3304 } 3305 3306 static int 3307 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3308 { 3309 usb_interface_descriptor_t *id; 3310 uint32_t reg; 3311 int nqueues; 3312 int error; 3313 3314 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3315 3316 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3317 3318 /* Initialize LLT table. */ 3319 error = urtwn_llt_init(sc); 3320 if (error != 0) 3321 return error; 3322 3323 /* Get Tx queues to USB endpoints mapping. */ 3324 id = usbd_get_interface_descriptor(sc->sc_iface); 3325 nqueues = id->bNumEndpoints - 1; 3326 if (nqueues == 0) 3327 return EIO; 3328 3329 /* Set number of pages for normal priority queue. */ 3330 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3331 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3332 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3333 3334 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3335 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3336 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3337 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3338 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3339 3340 /* Set queue to USB pipe mapping. */ 3341 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3342 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3343 if (nqueues == 1) 3344 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3345 else if (nqueues == 2) 3346 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3347 else 3348 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3349 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3350 3351 /* Set Tx/Rx transfer page boundary. */ 3352 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3353 3354 /* Set Tx/Rx transfer page size. */ 3355 urtwn_write_1(sc, R92C_PBP, 3356 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3357 3358 return 0; 3359 } 3360 3361 static void 3362 urtwn_mac_init(struct urtwn_softc *sc) 3363 { 3364 size_t i; 3365 3366 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3367 3368 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3369 3370 /* Write MAC initialization values. */ 3371 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3372 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3373 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3374 rtl8188eu_mac[i].val); 3375 } else { 3376 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3377 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3378 rtl8192cu_mac[i].val); 3379 } 3380 } 3381 3382 static void 3383 urtwn_bb_init(struct urtwn_softc *sc) 3384 { 3385 const struct urtwn_bb_prog *prog; 3386 uint32_t reg; 3387 uint8_t crystalcap; 3388 size_t i; 3389 3390 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3391 3392 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3393 3394 /* Enable BB and RF. */ 3395 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3396 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3397 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3398 R92C_SYS_FUNC_EN_DIO_RF); 3399 3400 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3401 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3402 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3403 } 3404 3405 urtwn_write_1(sc, R92C_RF_CTRL, 3406 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3407 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3408 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3409 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3410 3411 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3412 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3413 urtwn_write_1(sc, 0x15, 0xe9); 3414 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3415 } 3416 3417 /* Select BB programming based on board type. */ 3418 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3419 prog = &rtl8188eu_bb_prog; 3420 else if (!(sc->chip & URTWN_CHIP_92C)) { 3421 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3422 prog = &rtl8188ce_bb_prog; 3423 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3424 prog = &rtl8188ru_bb_prog; 3425 } else { 3426 prog = &rtl8188cu_bb_prog; 3427 } 3428 } else { 3429 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3430 prog = &rtl8192ce_bb_prog; 3431 } else { 3432 prog = &rtl8192cu_bb_prog; 3433 } 3434 } 3435 /* Write BB initialization values. */ 3436 for (i = 0; i < prog->count; i++) { 3437 /* additional delay depend on registers */ 3438 switch (prog->regs[i]) { 3439 case 0xfe: 3440 usbd_delay_ms(sc->sc_udev, 50); 3441 break; 3442 case 0xfd: 3443 usbd_delay_ms(sc->sc_udev, 5); 3444 break; 3445 case 0xfc: 3446 usbd_delay_ms(sc->sc_udev, 1); 3447 break; 3448 case 0xfb: 3449 DELAY(50); 3450 break; 3451 case 0xfa: 3452 DELAY(5); 3453 break; 3454 case 0xf9: 3455 DELAY(1); 3456 break; 3457 } 3458 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3459 DELAY(1); 3460 } 3461 3462 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3463 /* 8192C 1T only configuration. */ 3464 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3465 reg = (reg & ~0x00000003) | 0x2; 3466 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3467 3468 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3469 reg = (reg & ~0x00300033) | 0x00200022; 3470 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3471 3472 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3473 reg = (reg & ~0xff000000) | (0x45 << 24); 3474 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3475 3476 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3477 reg = (reg & ~0x000000ff) | 0x23; 3478 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3479 3480 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3481 reg = (reg & ~0x00000030) | (1 << 4); 3482 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3483 3484 reg = urtwn_bb_read(sc, 0xe74); 3485 reg = (reg & ~0x0c000000) | (2 << 26); 3486 urtwn_bb_write(sc, 0xe74, reg); 3487 reg = urtwn_bb_read(sc, 0xe78); 3488 reg = (reg & ~0x0c000000) | (2 << 26); 3489 urtwn_bb_write(sc, 0xe78, reg); 3490 reg = urtwn_bb_read(sc, 0xe7c); 3491 reg = (reg & ~0x0c000000) | (2 << 26); 3492 urtwn_bb_write(sc, 0xe7c, reg); 3493 reg = urtwn_bb_read(sc, 0xe80); 3494 reg = (reg & ~0x0c000000) | (2 << 26); 3495 urtwn_bb_write(sc, 0xe80, reg); 3496 reg = urtwn_bb_read(sc, 0xe88); 3497 reg = (reg & ~0x0c000000) | (2 << 26); 3498 urtwn_bb_write(sc, 0xe88, reg); 3499 } 3500 3501 /* Write AGC values. */ 3502 for (i = 0; i < prog->agccount; i++) { 3503 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3504 DELAY(1); 3505 } 3506 3507 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3508 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3509 DELAY(1); 3510 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3511 DELAY(1); 3512 3513 crystalcap = sc->r88e_rom[0xb9]; 3514 if (crystalcap == 0xff) 3515 crystalcap = 0x20; 3516 crystalcap &= 0x3f; 3517 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3518 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3519 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3520 crystalcap | crystalcap << 6)); 3521 } else { 3522 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3523 R92C_HSSI_PARAM2_CCK_HIPWR) { 3524 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3525 } 3526 } 3527 } 3528 3529 static void 3530 urtwn_rf_init(struct urtwn_softc *sc) 3531 { 3532 const struct urtwn_rf_prog *prog; 3533 uint32_t reg, mask, saved; 3534 size_t i, j, idx; 3535 3536 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3537 3538 /* Select RF programming based on board type. */ 3539 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3540 prog = rtl8188eu_rf_prog; 3541 else if (!(sc->chip & URTWN_CHIP_92C)) { 3542 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3543 prog = rtl8188ce_rf_prog; 3544 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3545 prog = rtl8188ru_rf_prog; 3546 } else { 3547 prog = rtl8188cu_rf_prog; 3548 } 3549 } else { 3550 prog = rtl8192ce_rf_prog; 3551 } 3552 3553 for (i = 0; i < sc->nrxchains; i++) { 3554 /* Save RF_ENV control type. */ 3555 idx = i / 2; 3556 mask = 0xffffU << ((i % 2) * 16); 3557 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3558 3559 /* Set RF_ENV enable. */ 3560 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3561 reg |= 0x100000; 3562 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3563 DELAY(1); 3564 3565 /* Set RF_ENV output high. */ 3566 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3567 reg |= 0x10; 3568 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3569 DELAY(1); 3570 3571 /* Set address and data lengths of RF registers. */ 3572 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3573 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3574 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3575 DELAY(1); 3576 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3577 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3578 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3579 DELAY(1); 3580 3581 /* Write RF initialization values for this chain. */ 3582 for (j = 0; j < prog[i].count; j++) { 3583 if (prog[i].regs[j] >= 0xf9 && 3584 prog[i].regs[j] <= 0xfe) { 3585 /* 3586 * These are fake RF registers offsets that 3587 * indicate a delay is required. 3588 */ 3589 usbd_delay_ms(sc->sc_udev, 50); 3590 continue; 3591 } 3592 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3593 DELAY(1); 3594 } 3595 3596 /* Restore RF_ENV control type. */ 3597 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3598 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3599 } 3600 3601 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3602 URTWN_CHIP_UMC_A_CUT) { 3603 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3604 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3605 } 3606 3607 /* Cache RF register CHNLBW. */ 3608 for (i = 0; i < 2; i++) { 3609 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3610 } 3611 } 3612 3613 static void 3614 urtwn_cam_init(struct urtwn_softc *sc) 3615 { 3616 uint32_t content, command; 3617 uint8_t idx; 3618 size_t i; 3619 3620 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3621 3622 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3623 3624 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3625 content = (idx & 3) 3626 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3627 | R92C_CAM_VALID; 3628 3629 command = R92C_CAMCMD_POLLING 3630 | R92C_CAMCMD_WRITE 3631 | R92C_CAM_CTL0(idx); 3632 3633 urtwn_write_4(sc, R92C_CAMWRITE, content); 3634 urtwn_write_4(sc, R92C_CAMCMD, command); 3635 } 3636 3637 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3638 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3639 if (i == 0) { 3640 content = (idx & 3) 3641 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3642 | R92C_CAM_VALID; 3643 } else { 3644 content = 0; 3645 } 3646 3647 command = R92C_CAMCMD_POLLING 3648 | R92C_CAMCMD_WRITE 3649 | R92C_CAM_CTL0(idx) 3650 | i; 3651 3652 urtwn_write_4(sc, R92C_CAMWRITE, content); 3653 urtwn_write_4(sc, R92C_CAMCMD, command); 3654 } 3655 } 3656 3657 /* Invalidate all CAM entries. */ 3658 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3659 } 3660 3661 static void 3662 urtwn_pa_bias_init(struct urtwn_softc *sc) 3663 { 3664 uint8_t reg; 3665 size_t i; 3666 3667 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3668 3669 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3670 3671 for (i = 0; i < sc->nrxchains; i++) { 3672 if (sc->pa_setting & (1U << i)) 3673 continue; 3674 3675 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3676 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3677 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3678 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3679 } 3680 if (!(sc->pa_setting & 0x10)) { 3681 reg = urtwn_read_1(sc, 0x16); 3682 reg = (reg & ~0xf0) | 0x90; 3683 urtwn_write_1(sc, 0x16, reg); 3684 } 3685 } 3686 3687 static void 3688 urtwn_rxfilter_init(struct urtwn_softc *sc) 3689 { 3690 3691 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3692 3693 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3694 3695 /* Initialize Rx filter. */ 3696 /* TODO: use better filter for monitor mode. */ 3697 urtwn_write_4(sc, R92C_RCR, 3698 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3699 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3700 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3701 /* Accept all multicast frames. */ 3702 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3703 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3704 /* Accept all management frames. */ 3705 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3706 /* Reject all control frames. */ 3707 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3708 /* Accept all data frames. */ 3709 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3710 } 3711 3712 static void 3713 urtwn_edca_init(struct urtwn_softc *sc) 3714 { 3715 3716 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3717 3718 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3719 3720 /* set spec SIFS (used in NAV) */ 3721 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3722 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3723 3724 /* set SIFS CCK/OFDM */ 3725 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3726 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3727 3728 /* TXOP */ 3729 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3730 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3731 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3732 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3733 } 3734 3735 static void 3736 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3737 uint16_t power[URTWN_RIDX_COUNT]) 3738 { 3739 uint32_t reg; 3740 3741 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3742 __func__, chain)); 3743 3744 /* Write per-CCK rate Tx power. */ 3745 if (chain == 0) { 3746 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3747 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3748 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3749 3750 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3751 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3752 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3753 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3754 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3755 } else { 3756 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3757 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3758 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3759 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3760 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3761 3762 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3763 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3764 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3765 } 3766 /* Write per-OFDM rate Tx power. */ 3767 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3768 SM(R92C_TXAGC_RATE06, power[ 4]) | 3769 SM(R92C_TXAGC_RATE09, power[ 5]) | 3770 SM(R92C_TXAGC_RATE12, power[ 6]) | 3771 SM(R92C_TXAGC_RATE18, power[ 7])); 3772 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3773 SM(R92C_TXAGC_RATE24, power[ 8]) | 3774 SM(R92C_TXAGC_RATE36, power[ 9]) | 3775 SM(R92C_TXAGC_RATE48, power[10]) | 3776 SM(R92C_TXAGC_RATE54, power[11])); 3777 /* Write per-MCS Tx power. */ 3778 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3779 SM(R92C_TXAGC_MCS00, power[12]) | 3780 SM(R92C_TXAGC_MCS01, power[13]) | 3781 SM(R92C_TXAGC_MCS02, power[14]) | 3782 SM(R92C_TXAGC_MCS03, power[15])); 3783 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3784 SM(R92C_TXAGC_MCS04, power[16]) | 3785 SM(R92C_TXAGC_MCS05, power[17]) | 3786 SM(R92C_TXAGC_MCS06, power[18]) | 3787 SM(R92C_TXAGC_MCS07, power[19])); 3788 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3789 SM(R92C_TXAGC_MCS08, power[20]) | 3790 SM(R92C_TXAGC_MCS09, power[21]) | 3791 SM(R92C_TXAGC_MCS10, power[22]) | 3792 SM(R92C_TXAGC_MCS11, power[23])); 3793 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3794 SM(R92C_TXAGC_MCS12, power[24]) | 3795 SM(R92C_TXAGC_MCS13, power[25]) | 3796 SM(R92C_TXAGC_MCS14, power[26]) | 3797 SM(R92C_TXAGC_MCS15, power[27])); 3798 } 3799 3800 static void 3801 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 3802 uint16_t power[URTWN_RIDX_COUNT]) 3803 { 3804 struct r92c_rom *rom = &sc->rom; 3805 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3806 const struct urtwn_txpwr *base; 3807 int ridx, group; 3808 3809 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3810 device_xname(sc->sc_dev), __func__, chain, chan)); 3811 3812 /* Determine channel group. */ 3813 if (chan <= 3) { 3814 group = 0; 3815 } else if (chan <= 9) { 3816 group = 1; 3817 } else { 3818 group = 2; 3819 } 3820 3821 /* Get original Tx power based on board type and RF chain. */ 3822 if (!(sc->chip & URTWN_CHIP_92C)) { 3823 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3824 base = &rtl8188ru_txagc[chain]; 3825 } else { 3826 base = &rtl8192cu_txagc[chain]; 3827 } 3828 } else { 3829 base = &rtl8192cu_txagc[chain]; 3830 } 3831 3832 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3833 if (sc->regulatory == 0) { 3834 for (ridx = 0; ridx <= 3; ridx++) { 3835 power[ridx] = base->pwr[0][ridx]; 3836 } 3837 } 3838 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3839 if (sc->regulatory == 3) { 3840 power[ridx] = base->pwr[0][ridx]; 3841 /* Apply vendor limits. */ 3842 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3843 maxpow = rom->ht40_max_pwr[group]; 3844 } else { 3845 maxpow = rom->ht20_max_pwr[group]; 3846 } 3847 maxpow = (maxpow >> (chain * 4)) & 0xf; 3848 if (power[ridx] > maxpow) { 3849 power[ridx] = maxpow; 3850 } 3851 } else if (sc->regulatory == 1) { 3852 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3853 power[ridx] = base->pwr[group][ridx]; 3854 } 3855 } else if (sc->regulatory != 2) { 3856 power[ridx] = base->pwr[0][ridx]; 3857 } 3858 } 3859 3860 /* Compute per-CCK rate Tx power. */ 3861 cckpow = rom->cck_tx_pwr[chain][group]; 3862 for (ridx = 0; ridx <= 3; ridx++) { 3863 power[ridx] += cckpow; 3864 if (power[ridx] > R92C_MAX_TX_PWR) { 3865 power[ridx] = R92C_MAX_TX_PWR; 3866 } 3867 } 3868 3869 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3870 if (sc->ntxchains > 1) { 3871 /* Apply reduction for 2 spatial streams. */ 3872 diff = rom->ht40_2s_tx_pwr_diff[group]; 3873 diff = (diff >> (chain * 4)) & 0xf; 3874 htpow = (htpow > diff) ? htpow - diff : 0; 3875 } 3876 3877 /* Compute per-OFDM rate Tx power. */ 3878 diff = rom->ofdm_tx_pwr_diff[group]; 3879 diff = (diff >> (chain * 4)) & 0xf; 3880 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3881 for (ridx = 4; ridx <= 11; ridx++) { 3882 power[ridx] += ofdmpow; 3883 if (power[ridx] > R92C_MAX_TX_PWR) { 3884 power[ridx] = R92C_MAX_TX_PWR; 3885 } 3886 } 3887 3888 /* Compute per-MCS Tx power. */ 3889 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3890 diff = rom->ht20_tx_pwr_diff[group]; 3891 diff = (diff >> (chain * 4)) & 0xf; 3892 htpow += diff; /* HT40->HT20 correction. */ 3893 } 3894 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3895 power[ridx] += htpow; 3896 if (power[ridx] > R92C_MAX_TX_PWR) { 3897 power[ridx] = R92C_MAX_TX_PWR; 3898 } 3899 } 3900 #ifdef URTWN_DEBUG 3901 if (urtwn_debug & DBG_RF) { 3902 /* Dump per-rate Tx power values. */ 3903 printf("%s: %s: Tx power for chain %zd:\n", 3904 device_xname(sc->sc_dev), __func__, chain); 3905 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3906 printf("%s: %s: Rate %d = %u\n", 3907 device_xname(sc->sc_dev), __func__, ridx, 3908 power[ridx]); 3909 } 3910 } 3911 #endif 3912 } 3913 3914 void 3915 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 3916 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 3917 { 3918 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3919 const struct urtwn_r88e_txpwr *base; 3920 int ridx, group; 3921 3922 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3923 device_xname(sc->sc_dev), __func__, chain, chan)); 3924 3925 /* Determine channel group. */ 3926 if (chan <= 2) 3927 group = 0; 3928 else if (chan <= 5) 3929 group = 1; 3930 else if (chan <= 8) 3931 group = 2; 3932 else if (chan <= 11) 3933 group = 3; 3934 else if (chan <= 13) 3935 group = 4; 3936 else 3937 group = 5; 3938 3939 /* Get original Tx power based on board type and RF chain. */ 3940 base = &rtl8188eu_txagc[chain]; 3941 3942 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3943 if (sc->regulatory == 0) { 3944 for (ridx = 0; ridx <= 3; ridx++) 3945 power[ridx] = base->pwr[0][ridx]; 3946 } 3947 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3948 if (sc->regulatory == 3) 3949 power[ridx] = base->pwr[0][ridx]; 3950 else if (sc->regulatory == 1) { 3951 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 3952 power[ridx] = base->pwr[group][ridx]; 3953 } else if (sc->regulatory != 2) 3954 power[ridx] = base->pwr[0][ridx]; 3955 } 3956 3957 /* Compute per-CCK rate Tx power. */ 3958 cckpow = sc->cck_tx_pwr[group]; 3959 for (ridx = 0; ridx <= 3; ridx++) { 3960 power[ridx] += cckpow; 3961 if (power[ridx] > R92C_MAX_TX_PWR) 3962 power[ridx] = R92C_MAX_TX_PWR; 3963 } 3964 3965 htpow = sc->ht40_tx_pwr[group]; 3966 3967 /* Compute per-OFDM rate Tx power. */ 3968 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3969 for (ridx = 4; ridx <= 11; ridx++) { 3970 power[ridx] += ofdmpow; 3971 if (power[ridx] > R92C_MAX_TX_PWR) 3972 power[ridx] = R92C_MAX_TX_PWR; 3973 } 3974 3975 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3976 for (ridx = 12; ridx <= 27; ridx++) { 3977 power[ridx] += bw20pow; 3978 if (power[ridx] > R92C_MAX_TX_PWR) 3979 power[ridx] = R92C_MAX_TX_PWR; 3980 } 3981 } 3982 3983 static void 3984 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3985 { 3986 uint16_t power[URTWN_RIDX_COUNT]; 3987 size_t i; 3988 3989 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3990 3991 for (i = 0; i < sc->ntxchains; i++) { 3992 /* Compute per-rate Tx power values. */ 3993 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3994 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 3995 else 3996 urtwn_get_txpower(sc, i, chan, ht40m, power); 3997 /* Write per-rate Tx power values to hardware. */ 3998 urtwn_write_txpower(sc, i, power); 3999 } 4000 } 4001 4002 static void 4003 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4004 { 4005 struct ieee80211com *ic = &sc->sc_ic; 4006 u_int chan; 4007 size_t i; 4008 4009 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4010 4011 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4012 __func__, chan)); 4013 4014 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4015 4016 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4017 chan += 2; 4018 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4019 chan -= 2; 4020 } 4021 4022 /* Set Tx power for this new channel. */ 4023 urtwn_set_txpower(sc, chan, ht40m); 4024 4025 for (i = 0; i < sc->nrxchains; i++) { 4026 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4027 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4028 } 4029 4030 if (ht40m) { 4031 /* Is secondary channel below or above primary? */ 4032 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4033 uint32_t reg; 4034 4035 urtwn_write_1(sc, R92C_BWOPMODE, 4036 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4037 4038 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4039 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4040 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4041 4042 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4043 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4044 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4045 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4046 4047 /* Set CCK side band. */ 4048 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4049 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4050 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4051 4052 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4053 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4054 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4055 4056 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4057 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4058 ~R92C_FPGA0_ANAPARAM2_CBW20); 4059 4060 reg = urtwn_bb_read(sc, 0x818); 4061 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4062 urtwn_bb_write(sc, 0x818, reg); 4063 4064 /* Select 40MHz bandwidth. */ 4065 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4066 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4067 } else { 4068 urtwn_write_1(sc, R92C_BWOPMODE, 4069 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4070 4071 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4072 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4073 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4074 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4075 4076 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4077 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4078 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4079 R92C_FPGA0_ANAPARAM2_CBW20); 4080 } 4081 4082 /* Select 20MHz bandwidth. */ 4083 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4084 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4085 (ISSET(sc->chip, URTWN_CHIP_88E) ? 4086 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4087 } 4088 } 4089 4090 static void 4091 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4092 { 4093 4094 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4095 __func__, inited)); 4096 4097 /* TODO */ 4098 } 4099 4100 static void 4101 urtwn_lc_calib(struct urtwn_softc *sc) 4102 { 4103 uint32_t rf_ac[2]; 4104 uint8_t txmode; 4105 size_t i; 4106 4107 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4108 4109 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4110 4111 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4112 if ((txmode & 0x70) != 0) { 4113 /* Disable all continuous Tx. */ 4114 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4115 4116 /* Set RF mode to standby mode. */ 4117 for (i = 0; i < sc->nrxchains; i++) { 4118 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4119 urtwn_rf_write(sc, i, R92C_RF_AC, 4120 RW(rf_ac[i], R92C_RF_AC_MODE, 4121 R92C_RF_AC_MODE_STANDBY)); 4122 } 4123 } else { 4124 /* Block all Tx queues. */ 4125 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4126 } 4127 /* Start calibration. */ 4128 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4129 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4130 4131 /* Give calibration the time to complete. */ 4132 usbd_delay_ms(sc->sc_udev, 100); 4133 4134 /* Restore configuration. */ 4135 if ((txmode & 0x70) != 0) { 4136 /* Restore Tx mode. */ 4137 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4138 /* Restore RF mode. */ 4139 for (i = 0; i < sc->nrxchains; i++) { 4140 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4141 } 4142 } else { 4143 /* Unblock all Tx queues. */ 4144 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4145 } 4146 } 4147 4148 static void 4149 urtwn_temp_calib(struct urtwn_softc *sc) 4150 { 4151 int temp; 4152 4153 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4154 4155 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4156 4157 if (sc->thcal_state == 0) { 4158 /* Start measuring temperature. */ 4159 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4160 device_xname(sc->sc_dev), __func__)); 4161 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 4162 sc->thcal_state = 1; 4163 return; 4164 } 4165 sc->thcal_state = 0; 4166 4167 /* Read measured temperature. */ 4168 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4169 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4170 __func__, temp)); 4171 if (temp == 0) /* Read failed, skip. */ 4172 return; 4173 4174 /* 4175 * Redo LC calibration if temperature changed significantly since 4176 * last calibration. 4177 */ 4178 if (sc->thcal_lctemp == 0) { 4179 /* First LC calibration is performed in urtwn_init(). */ 4180 sc->thcal_lctemp = temp; 4181 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4182 DPRINTFN(DBG_RF, 4183 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4184 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4185 temp)); 4186 urtwn_lc_calib(sc); 4187 /* Record temperature of last LC calibration. */ 4188 sc->thcal_lctemp = temp; 4189 } 4190 } 4191 4192 static int 4193 urtwn_init(struct ifnet *ifp) 4194 { 4195 struct urtwn_softc *sc = ifp->if_softc; 4196 struct ieee80211com *ic = &sc->sc_ic; 4197 struct urtwn_rx_data *data; 4198 uint32_t reg; 4199 size_t i; 4200 int error; 4201 4202 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4203 4204 urtwn_stop(ifp, 0); 4205 4206 mutex_enter(&sc->sc_write_mtx); 4207 4208 mutex_enter(&sc->sc_task_mtx); 4209 /* Init host async commands ring. */ 4210 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4211 mutex_exit(&sc->sc_task_mtx); 4212 4213 mutex_enter(&sc->sc_fwcmd_mtx); 4214 /* Init firmware commands ring. */ 4215 sc->fwcur = 0; 4216 mutex_exit(&sc->sc_fwcmd_mtx); 4217 4218 /* Allocate Tx/Rx buffers. */ 4219 error = urtwn_alloc_rx_list(sc); 4220 if (error != 0) { 4221 aprint_error_dev(sc->sc_dev, 4222 "could not allocate Rx buffers\n"); 4223 goto fail; 4224 } 4225 error = urtwn_alloc_tx_list(sc); 4226 if (error != 0) { 4227 aprint_error_dev(sc->sc_dev, 4228 "could not allocate Tx buffers\n"); 4229 goto fail; 4230 } 4231 4232 /* Power on adapter. */ 4233 error = urtwn_power_on(sc); 4234 if (error != 0) 4235 goto fail; 4236 4237 /* Initialize DMA. */ 4238 error = urtwn_dma_init(sc); 4239 if (error != 0) 4240 goto fail; 4241 4242 /* Set info size in Rx descriptors (in 64-bit words). */ 4243 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4244 4245 /* Init interrupts. */ 4246 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4247 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4248 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4249 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4250 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4251 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4252 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4253 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4254 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4255 } else { 4256 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4257 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4258 } 4259 4260 /* Set MAC address. */ 4261 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4262 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4263 4264 /* Set initial network type. */ 4265 reg = urtwn_read_4(sc, R92C_CR); 4266 switch (ic->ic_opmode) { 4267 case IEEE80211_M_STA: 4268 default: 4269 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4270 break; 4271 4272 case IEEE80211_M_IBSS: 4273 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4274 break; 4275 } 4276 urtwn_write_4(sc, R92C_CR, reg); 4277 4278 /* Set response rate */ 4279 reg = urtwn_read_4(sc, R92C_RRSR); 4280 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4281 urtwn_write_4(sc, R92C_RRSR, reg); 4282 4283 /* SIFS (used in NAV) */ 4284 urtwn_write_2(sc, R92C_SPEC_SIFS, 4285 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4286 4287 /* Set short/long retry limits. */ 4288 urtwn_write_2(sc, R92C_RL, 4289 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4290 4291 /* Initialize EDCA parameters. */ 4292 urtwn_edca_init(sc); 4293 4294 /* Setup rate fallback. */ 4295 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4296 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4297 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4298 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4299 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4300 } 4301 4302 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4303 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4304 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4305 /* Set ACK timeout. */ 4306 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4307 4308 /* Setup USB aggregation. */ 4309 /* Tx */ 4310 reg = urtwn_read_4(sc, R92C_TDECTRL); 4311 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4312 urtwn_write_4(sc, R92C_TDECTRL, reg); 4313 /* Rx */ 4314 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4315 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4316 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4317 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4318 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4319 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4320 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4321 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4322 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4323 else 4324 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4325 4326 /* Initialize beacon parameters. */ 4327 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4328 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4329 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4330 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4331 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4332 4333 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4334 /* Setup AMPDU aggregation. */ 4335 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4336 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4337 urtwn_write_2(sc, 0x4ca, 0x0708); 4338 4339 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4340 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4341 } 4342 4343 /* Load 8051 microcode. */ 4344 error = urtwn_load_firmware(sc); 4345 if (error != 0) 4346 goto fail; 4347 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4348 4349 /* Initialize MAC/BB/RF blocks. */ 4350 /* 4351 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4352 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4353 * XXX: This setting should be removed from rtl8192cu_mac[]. 4354 */ 4355 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4356 urtwn_rxfilter_init(sc); // reset R92C_RCR 4357 urtwn_bb_init(sc); 4358 urtwn_rf_init(sc); 4359 4360 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4361 urtwn_write_2(sc, R92C_CR, 4362 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4363 R92C_CR_MACRXEN); 4364 } 4365 4366 /* Turn CCK and OFDM blocks on. */ 4367 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4368 reg |= R92C_RFMOD_CCK_EN; 4369 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4370 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4371 reg |= R92C_RFMOD_OFDM_EN; 4372 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4373 4374 /* Clear per-station keys table. */ 4375 urtwn_cam_init(sc); 4376 4377 /* Enable hardware sequence numbering. */ 4378 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4379 4380 /* Perform LO and IQ calibrations. */ 4381 urtwn_iq_calib(sc, sc->iqk_inited); 4382 sc->iqk_inited = true; 4383 4384 /* Perform LC calibration. */ 4385 urtwn_lc_calib(sc); 4386 4387 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4388 /* Fix USB interference issue. */ 4389 urtwn_write_1(sc, 0xfe40, 0xe0); 4390 urtwn_write_1(sc, 0xfe41, 0x8d); 4391 urtwn_write_1(sc, 0xfe42, 0x80); 4392 urtwn_write_4(sc, 0x20c, 0xfd0320); 4393 4394 urtwn_pa_bias_init(sc); 4395 } 4396 4397 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 4398 /* 1T1R */ 4399 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4400 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4401 } 4402 4403 /* Initialize GPIO setting. */ 4404 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4405 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4406 4407 /* Fix for lower temperature. */ 4408 if (!ISSET(sc->chip, URTWN_CHIP_88E)) 4409 urtwn_write_1(sc, 0x15, 0xe9); 4410 4411 /* Set default channel. */ 4412 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4413 4414 /* Queue Rx xfers. */ 4415 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4416 data = &sc->rx_data[i]; 4417 usbd_setup_xfer(data->xfer, data, data->buf, URTWN_RXBUFSZ, 4418 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 4419 error = usbd_transfer(data->xfer); 4420 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4421 error != USBD_IN_PROGRESS)) 4422 goto fail; 4423 } 4424 4425 /* We're ready to go. */ 4426 ifp->if_flags &= ~IFF_OACTIVE; 4427 ifp->if_flags |= IFF_RUNNING; 4428 4429 mutex_exit(&sc->sc_write_mtx); 4430 4431 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4432 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4433 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4434 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4435 urtwn_wait_async(sc); 4436 4437 return 0; 4438 4439 fail: 4440 mutex_exit(&sc->sc_write_mtx); 4441 4442 urtwn_stop(ifp, 1); 4443 return error; 4444 } 4445 4446 static void 4447 urtwn_stop(struct ifnet *ifp, int disable) 4448 { 4449 struct urtwn_softc *sc = ifp->if_softc; 4450 struct ieee80211com *ic = &sc->sc_ic; 4451 size_t i; 4452 int s; 4453 4454 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4455 4456 s = splusb(); 4457 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4458 urtwn_wait_async(sc); 4459 splx(s); 4460 4461 sc->tx_timer = 0; 4462 ifp->if_timer = 0; 4463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4464 4465 callout_stop(&sc->sc_scan_to); 4466 callout_stop(&sc->sc_calib_to); 4467 4468 /* Abort Tx. */ 4469 for (i = 0; i < R92C_MAX_EPOUT; i++) { 4470 if (sc->tx_pipe[i] != NULL) 4471 usbd_abort_pipe(sc->tx_pipe[i]); 4472 } 4473 4474 /* Stop Rx pipe. */ 4475 usbd_abort_pipe(sc->rx_pipe); 4476 4477 /* Free Tx/Rx buffers. */ 4478 urtwn_free_tx_list(sc); 4479 urtwn_free_rx_list(sc); 4480 4481 if (disable) 4482 urtwn_chip_stop(sc); 4483 } 4484 4485 static int 4486 urtwn_reset(struct ifnet *ifp) 4487 { 4488 struct urtwn_softc *sc = ifp->if_softc; 4489 struct ieee80211com *ic = &sc->sc_ic; 4490 4491 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4492 return ENETRESET; 4493 4494 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4495 4496 return 0; 4497 } 4498 4499 static void 4500 urtwn_chip_stop(struct urtwn_softc *sc) 4501 { 4502 uint32_t reg; 4503 bool disabled = true; 4504 4505 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4506 4507 mutex_enter(&sc->sc_write_mtx); 4508 4509 /* 4510 * RF Off Sequence 4511 */ 4512 /* Pause MAC TX queue */ 4513 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4514 4515 /* Disable RF */ 4516 urtwn_rf_write(sc, 0, 0, 0); 4517 4518 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4519 4520 /* Reset BB state machine */ 4521 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4522 R92C_SYS_FUNC_EN_USBD | 4523 R92C_SYS_FUNC_EN_USBA | 4524 R92C_SYS_FUNC_EN_BB_GLB_RST); 4525 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4526 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4527 4528 /* 4529 * Reset digital sequence 4530 */ 4531 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4532 /* Reset MCU ready status */ 4533 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4534 /* If firmware in ram code, do reset */ 4535 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4536 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4537 urtwn_r88e_fw_reset(sc); 4538 else 4539 urtwn_fw_reset(sc); 4540 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 4541 } 4542 } 4543 4544 /* Reset MAC and Enable 8051 */ 4545 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 4546 4547 /* Reset MCU ready status */ 4548 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4549 4550 if (disabled) { 4551 /* Disable MAC clock */ 4552 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4553 /* Disable AFE PLL */ 4554 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 4555 /* Gated AFE DIG_CLOCK */ 4556 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 4557 /* Isolated digital to PON */ 4558 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 4559 } 4560 4561 /* 4562 * Pull GPIO PIN to balance level and LED control 4563 */ 4564 /* 1. Disable GPIO[7:0] */ 4565 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 4566 4567 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 4568 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 4569 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 4570 4571 /* Disable GPIO[10:8] */ 4572 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 4573 4574 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 4575 reg |= (((reg & 0x000f) << 4) | 0x0780); 4576 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 4577 4578 /* Disable LED0 & 1 */ 4579 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 4580 4581 /* 4582 * Reset digital sequence 4583 */ 4584 if (disabled) { 4585 /* Disable ELDR clock */ 4586 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4587 /* Isolated ELDR to PON */ 4588 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 4589 } 4590 4591 /* 4592 * Disable analog sequence 4593 */ 4594 if (disabled) { 4595 /* Disable A15 power */ 4596 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 4597 /* Disable digital core power */ 4598 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 4599 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 4600 ~R92C_LDOV12D_CTRL_LDV12_EN); 4601 } 4602 4603 /* Enter PFM mode */ 4604 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 4605 4606 /* Set USB suspend */ 4607 urtwn_write_2(sc, R92C_APS_FSMCO, 4608 R92C_APS_FSMCO_APDM_HOST | 4609 R92C_APS_FSMCO_AFSM_HSUS | 4610 R92C_APS_FSMCO_PFM_ALDN); 4611 4612 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 4613 4614 mutex_exit(&sc->sc_write_mtx); 4615 } 4616 4617 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 4618 4619 #ifdef _MODULE 4620 #include "ioconf.c" 4621 #endif 4622 4623 static int 4624 if_urtwn_modcmd(modcmd_t cmd, void *aux) 4625 { 4626 int error = 0; 4627 4628 switch (cmd) { 4629 case MODULE_CMD_INIT: 4630 #ifdef _MODULE 4631 error = config_init_component(cfdriver_ioconf_urtwn, 4632 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4633 #endif 4634 return error; 4635 case MODULE_CMD_FINI: 4636 #ifdef _MODULE 4637 error = config_fini_component(cfdriver_ioconf_urtwn, 4638 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4639 #endif 4640 return error; 4641 default: 4642 return ENOTTY; 4643 } 4644 } 4645
Indexes created Tue Sep 30 11:09:46 GMT 2025