if_urtwn.c revision 1.45.2.1
1 /* $NetBSD: if_urtwn.c,v 1.45.2.1 2016/11/04 14:49:15 pgoyette Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.45.2.1 2016/11/04 14:49:15 pgoyette Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #endif 33 34 #include <sys/param.h> 35 #include <sys/sockio.h> 36 #include <sys/sysctl.h> 37 #include <sys/mbuf.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 63 #include <net80211/ieee80211_netbsd.h> 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/firmload.h> 68 69 #include <dev/usb/usb.h> 70 #include <dev/usb/usbdi.h> 71 #include <dev/usb/usbdivar.h> 72 #include <dev/usb/usbdi_util.h> 73 #include <dev/usb/usbdevs.h> 74 75 #include <dev/usb/if_urtwnreg.h> 76 #include <dev/usb/if_urtwnvar.h> 77 #include <dev/usb/if_urtwn_data.h> 78 79 /* 80 * The sc_write_mtx locking is to prevent sequences of writes from 81 * being intermingled with each other. I don't know if this is really 82 * needed. I have added it just to be on the safe side. 83 */ 84 85 #ifdef URTWN_DEBUG 86 #define DBG_INIT __BIT(0) 87 #define DBG_FN __BIT(1) 88 #define DBG_TX __BIT(2) 89 #define DBG_RX __BIT(3) 90 #define DBG_STM __BIT(4) 91 #define DBG_RF __BIT(5) 92 #define DBG_REG __BIT(6) 93 #define DBG_ALL 0xffffffffU 94 u_int urtwn_debug = 0; 95 #define DPRINTFN(n, s) \ 96 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 97 #else 98 #define DPRINTFN(n, s) 99 #endif 100 101 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 102 #define URTWN_RTL8188E_DEV(v,p) \ 103 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 104 #define URTWN_RTL8192EU_DEV(v,p) \ 105 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 106 static const struct urtwn_dev { 107 struct usb_devno dev; 108 uint32_t flags; 109 #define FLAG_RTL8188E __BIT(0) 110 #define FLAG_RTL8192E __BIT(1) 111 } urtwn_devs[] = { 112 URTWN_DEV(ABOCOM, RTL8188CU_1), 113 URTWN_DEV(ABOCOM, RTL8188CU_2), 114 URTWN_DEV(ABOCOM, RTL8192CU), 115 URTWN_DEV(ASUSTEK, RTL8192CU), 116 URTWN_DEV(ASUSTEK, RTL8192CU_3), 117 URTWN_DEV(ASUSTEK, USBN10NANO), 118 URTWN_DEV(ASUSTEK, RTL8192CU_3), 119 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 120 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 121 URTWN_DEV(AZUREWAVE, RTL8188CU), 122 URTWN_DEV(BELKIN, F7D2102), 123 URTWN_DEV(BELKIN, RTL8188CU), 124 URTWN_DEV(BELKIN, RTL8188CUS), 125 URTWN_DEV(BELKIN, RTL8192CU), 126 URTWN_DEV(BELKIN, RTL8192CU_1), 127 URTWN_DEV(BELKIN, RTL8192CU_2), 128 URTWN_DEV(CHICONY, RTL8188CUS_1), 129 URTWN_DEV(CHICONY, RTL8188CUS_2), 130 URTWN_DEV(CHICONY, RTL8188CUS_3), 131 URTWN_DEV(CHICONY, RTL8188CUS_4), 132 URTWN_DEV(CHICONY, RTL8188CUS_5), 133 URTWN_DEV(CHICONY, RTL8188CUS_6), 134 URTWN_DEV(COMPARE, RTL8192CU), 135 URTWN_DEV(COREGA, RTL8192CU), 136 URTWN_DEV(DLINK, DWA131B), 137 URTWN_DEV(DLINK, RTL8188CU), 138 URTWN_DEV(DLINK, RTL8192CU_1), 139 URTWN_DEV(DLINK, RTL8192CU_2), 140 URTWN_DEV(DLINK, RTL8192CU_3), 141 URTWN_DEV(DLINK, RTL8192CU_4), 142 URTWN_DEV(EDIMAX, RTL8188CU), 143 URTWN_DEV(EDIMAX, RTL8192CU), 144 URTWN_DEV(FEIXUN, RTL8188CU), 145 URTWN_DEV(FEIXUN, RTL8192CU), 146 URTWN_DEV(GUILLEMOT, HWNUP150), 147 URTWN_DEV(GUILLEMOT, RTL8192CU), 148 URTWN_DEV(HAWKING, RTL8192CU), 149 URTWN_DEV(HAWKING, RTL8192CU_2), 150 URTWN_DEV(HP3, RTL8188CU), 151 URTWN_DEV(IODATA, WNG150UM), 152 URTWN_DEV(IODATA, RTL8192CU), 153 URTWN_DEV(NETGEAR, WNA1000M), 154 URTWN_DEV(NETGEAR, RTL8192CU), 155 URTWN_DEV(NETGEAR4, RTL8188CU), 156 URTWN_DEV(NOVATECH, RTL8188CU), 157 URTWN_DEV(PLANEX2, RTL8188CU_1), 158 URTWN_DEV(PLANEX2, RTL8188CU_2), 159 URTWN_DEV(PLANEX2, RTL8192CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_3), 161 URTWN_DEV(PLANEX2, RTL8188CU_4), 162 URTWN_DEV(PLANEX2, RTL8188CUS), 163 URTWN_DEV(REALTEK, RTL8188CE_0), 164 URTWN_DEV(REALTEK, RTL8188CE_1), 165 URTWN_DEV(REALTEK, RTL8188CTV), 166 URTWN_DEV(REALTEK, RTL8188CU_0), 167 URTWN_DEV(REALTEK, RTL8188CU_1), 168 URTWN_DEV(REALTEK, RTL8188CU_2), 169 URTWN_DEV(REALTEK, RTL8188CU_3), 170 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 171 URTWN_DEV(REALTEK, RTL8188CUS), 172 URTWN_DEV(REALTEK, RTL8188RU), 173 URTWN_DEV(REALTEK, RTL8188RU_2), 174 URTWN_DEV(REALTEK, RTL8188RU_3), 175 URTWN_DEV(REALTEK, RTL8191CU), 176 URTWN_DEV(REALTEK, RTL8192CE), 177 URTWN_DEV(REALTEK, RTL8192CU), 178 URTWN_DEV(SITECOMEU, RTL8188CU), 179 URTWN_DEV(SITECOMEU, RTL8188CU_2), 180 URTWN_DEV(SITECOMEU, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8192CUR2), 182 URTWN_DEV(TPLINK, RTL8192CU), 183 URTWN_DEV(TRENDNET, RTL8188CU), 184 URTWN_DEV(TRENDNET, RTL8192CU), 185 URTWN_DEV(ZYXEL, RTL8192CU), 186 187 /* URTWN_RTL8188E */ 188 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 189 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 190 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 191 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 192 193 /* URTWN_RTL8192EU */ 194 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 195 }; 196 #undef URTWN_DEV 197 #undef URTWN_RTL8188E_DEV 198 #undef URTWN_RTL8192EU_DEV 199 200 static int urtwn_match(device_t, cfdata_t, void *); 201 static void urtwn_attach(device_t, device_t, void *); 202 static int urtwn_detach(device_t, int); 203 static int urtwn_activate(device_t, enum devact); 204 205 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 206 urtwn_attach, urtwn_detach, urtwn_activate); 207 208 static int urtwn_open_pipes(struct urtwn_softc *); 209 static void urtwn_close_pipes(struct urtwn_softc *); 210 static int urtwn_alloc_rx_list(struct urtwn_softc *); 211 static void urtwn_free_rx_list(struct urtwn_softc *); 212 static int urtwn_alloc_tx_list(struct urtwn_softc *); 213 static void urtwn_free_tx_list(struct urtwn_softc *); 214 static void urtwn_task(void *); 215 static void urtwn_do_async(struct urtwn_softc *, 216 void (*)(struct urtwn_softc *, void *), void *, int); 217 static void urtwn_wait_async(struct urtwn_softc *); 218 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 219 int); 220 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 221 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 222 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 223 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 224 int); 225 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 226 int); 227 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 228 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 229 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 230 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 231 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 232 uint32_t); 233 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 234 uint32_t); 235 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 236 uint32_t); 237 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 238 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 239 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 240 static void urtwn_efuse_read(struct urtwn_softc *); 241 static void urtwn_efuse_switch_power(struct urtwn_softc *); 242 static int urtwn_read_chipid(struct urtwn_softc *); 243 #ifdef URTWN_DEBUG 244 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 245 #endif 246 static void urtwn_read_rom(struct urtwn_softc *); 247 static void urtwn_r88e_read_rom(struct urtwn_softc *); 248 static int urtwn_media_change(struct ifnet *); 249 static int urtwn_ra_init(struct urtwn_softc *); 250 static int urtwn_get_nettype(struct urtwn_softc *); 251 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 252 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 253 static void urtwn_set_led(struct urtwn_softc *, int, int); 254 static void urtwn_calib_to(void *); 255 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 256 static void urtwn_next_scan(void *); 257 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 258 int); 259 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 260 static int urtwn_wme_update(struct ieee80211com *); 261 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 262 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 263 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 264 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 265 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 266 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 267 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 268 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 269 struct ieee80211_node *, struct urtwn_tx_data *); 270 static struct urtwn_tx_data * 271 urtwn_get_tx_data(struct urtwn_softc *, size_t); 272 static void urtwn_start(struct ifnet *); 273 static void urtwn_watchdog(struct ifnet *); 274 static int urtwn_ioctl(struct ifnet *, u_long, void *); 275 static int urtwn_r92c_power_on(struct urtwn_softc *); 276 static int urtwn_r92e_power_on(struct urtwn_softc *); 277 static int urtwn_r88e_power_on(struct urtwn_softc *); 278 static int urtwn_llt_init(struct urtwn_softc *); 279 static void urtwn_fw_reset(struct urtwn_softc *); 280 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 281 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 282 static int urtwn_load_firmware(struct urtwn_softc *); 283 static int urtwn_r92c_dma_init(struct urtwn_softc *); 284 static int urtwn_r88e_dma_init(struct urtwn_softc *); 285 static void urtwn_mac_init(struct urtwn_softc *); 286 static void urtwn_bb_init(struct urtwn_softc *); 287 static void urtwn_rf_init(struct urtwn_softc *); 288 static void urtwn_cam_init(struct urtwn_softc *); 289 static void urtwn_pa_bias_init(struct urtwn_softc *); 290 static void urtwn_rxfilter_init(struct urtwn_softc *); 291 static void urtwn_edca_init(struct urtwn_softc *); 292 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 293 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 294 uint16_t[]); 295 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 296 u_int, uint16_t[]); 297 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 298 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 299 u_int); 300 static void urtwn_iq_calib(struct urtwn_softc *, bool); 301 static void urtwn_lc_calib(struct urtwn_softc *); 302 static void urtwn_temp_calib(struct urtwn_softc *); 303 static int urtwn_init(struct ifnet *); 304 static void urtwn_stop(struct ifnet *, int); 305 static int urtwn_reset(struct ifnet *); 306 static void urtwn_chip_stop(struct urtwn_softc *); 307 static void urtwn_newassoc(struct ieee80211_node *, int); 308 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 309 310 /* Aliases. */ 311 #define urtwn_bb_write urtwn_write_4 312 #define urtwn_bb_read urtwn_read_4 313 314 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 315 316 static const uint16_t addaReg[] = { 317 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 318 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 319 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 320 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 321 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 322 }; 323 324 static int 325 urtwn_match(device_t parent, cfdata_t match, void *aux) 326 { 327 struct usb_attach_arg *uaa = aux; 328 329 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 330 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 331 } 332 333 static void 334 urtwn_attach(device_t parent, device_t self, void *aux) 335 { 336 struct urtwn_softc *sc = device_private(self); 337 struct ieee80211com *ic = &sc->sc_ic; 338 struct ifnet *ifp = &sc->sc_if; 339 struct usb_attach_arg *uaa = aux; 340 char *devinfop; 341 const struct urtwn_dev *dev; 342 usb_device_request_t req; 343 size_t i; 344 int error; 345 346 sc->sc_dev = self; 347 sc->sc_udev = uaa->uaa_device; 348 349 sc->chip = 0; 350 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 351 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 352 SET(sc->chip, URTWN_CHIP_88E); 353 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 354 SET(sc->chip, URTWN_CHIP_92EU); 355 356 aprint_naive("\n"); 357 aprint_normal("\n"); 358 359 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 360 361 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 362 aprint_normal_dev(self, "%s\n", devinfop); 363 usbd_devinfo_free(devinfop); 364 365 req.bmRequestType = UT_WRITE_DEVICE; 366 req.bRequest = UR_SET_FEATURE; 367 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 368 USETW(req.wIndex, UHF_PORT_SUSPEND); 369 USETW(req.wLength, 0); 370 371 (void) usbd_do_request(sc->sc_udev, &req, 0); 372 373 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 374 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 375 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 376 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 377 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 378 379 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 380 381 callout_init(&sc->sc_scan_to, 0); 382 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 383 callout_init(&sc->sc_calib_to, 0); 384 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 385 386 error = usbd_set_config_no(sc->sc_udev, 1, 0); 387 if (error != 0) { 388 aprint_error_dev(self, "failed to set configuration" 389 ", err=%s\n", usbd_errstr(error)); 390 goto fail; 391 } 392 393 /* Get the first interface handle. */ 394 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 395 if (error != 0) { 396 aprint_error_dev(self, "could not get interface handle\n"); 397 goto fail; 398 } 399 400 error = urtwn_read_chipid(sc); 401 if (error != 0) { 402 aprint_error_dev(self, "unsupported test chip\n"); 403 goto fail; 404 } 405 406 /* Determine number of Tx/Rx chains. */ 407 if (sc->chip & URTWN_CHIP_92C) { 408 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 409 sc->nrxchains = 2; 410 } else if (sc->chip & URTWN_CHIP_92EU) { 411 sc->ntxchains = 2; 412 sc->nrxchains = 2; 413 } else { 414 sc->ntxchains = 1; 415 sc->nrxchains = 1; 416 } 417 418 if (ISSET(sc->chip, URTWN_CHIP_88E) || 419 ISSET(sc->chip, URTWN_CHIP_92EU)) 420 urtwn_r88e_read_rom(sc); 421 else 422 urtwn_read_rom(sc); 423 424 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 425 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 426 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 427 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 428 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 429 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 430 "8188CUS", sc->ntxchains, sc->nrxchains, 431 ether_sprintf(ic->ic_myaddr)); 432 433 error = urtwn_open_pipes(sc); 434 if (error != 0) { 435 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 436 goto fail; 437 } 438 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 439 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 440 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 441 442 /* 443 * Setup the 802.11 device. 444 */ 445 ic->ic_ifp = ifp; 446 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 447 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 448 ic->ic_state = IEEE80211_S_INIT; 449 450 /* Set device capabilities. */ 451 ic->ic_caps = 452 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 453 IEEE80211_C_IBSS | /* IBSS mode supported */ 454 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 455 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 456 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 457 IEEE80211_C_WME | /* 802.11e */ 458 IEEE80211_C_WPA; /* 802.11i */ 459 460 /* Set supported .11b and .11g rates. */ 461 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 462 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 463 464 /* Set supported .11b and .11g channels (1 through 14). */ 465 for (i = 1; i <= 14; i++) { 466 ic->ic_channels[i].ic_freq = 467 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 468 ic->ic_channels[i].ic_flags = 469 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 470 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 471 } 472 473 ifp->if_softc = sc; 474 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 475 ifp->if_init = urtwn_init; 476 ifp->if_ioctl = urtwn_ioctl; 477 ifp->if_start = urtwn_start; 478 ifp->if_watchdog = urtwn_watchdog; 479 IFQ_SET_READY(&ifp->if_snd); 480 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 481 482 if_attach(ifp); 483 ieee80211_ifattach(ic); 484 485 /* override default methods */ 486 ic->ic_newassoc = urtwn_newassoc; 487 ic->ic_reset = urtwn_reset; 488 ic->ic_wme.wme_update = urtwn_wme_update; 489 490 /* Override state transition machine. */ 491 sc->sc_newstate = ic->ic_newstate; 492 ic->ic_newstate = urtwn_newstate; 493 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 494 495 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 496 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 497 &sc->sc_drvbpf); 498 499 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 500 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 501 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 502 503 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 504 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 505 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 506 507 ieee80211_announce(ic); 508 509 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 510 511 if (!pmf_device_register(self, NULL, NULL)) 512 aprint_error_dev(self, "couldn't establish power handler\n"); 513 514 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 515 return; 516 517 fail: 518 sc->sc_dying = 1; 519 aprint_error_dev(self, "attach failed\n"); 520 } 521 522 static int 523 urtwn_detach(device_t self, int flags) 524 { 525 struct urtwn_softc *sc = device_private(self); 526 struct ifnet *ifp = &sc->sc_if; 527 int s; 528 529 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 530 531 pmf_device_deregister(self); 532 533 s = splusb(); 534 535 sc->sc_dying = 1; 536 537 callout_stop(&sc->sc_scan_to); 538 callout_stop(&sc->sc_calib_to); 539 540 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 541 usb_rem_task(sc->sc_udev, &sc->sc_task); 542 urtwn_stop(ifp, 0); 543 544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 545 bpf_detach(ifp); 546 ieee80211_ifdetach(&sc->sc_ic); 547 if_detach(ifp); 548 549 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 550 urtwn_close_pipes(sc); 551 } 552 553 splx(s); 554 555 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 556 557 callout_destroy(&sc->sc_scan_to); 558 callout_destroy(&sc->sc_calib_to); 559 560 mutex_destroy(&sc->sc_write_mtx); 561 mutex_destroy(&sc->sc_fwcmd_mtx); 562 mutex_destroy(&sc->sc_tx_mtx); 563 mutex_destroy(&sc->sc_rx_mtx); 564 mutex_destroy(&sc->sc_task_mtx); 565 566 return 0; 567 } 568 569 static int 570 urtwn_activate(device_t self, enum devact act) 571 { 572 struct urtwn_softc *sc = device_private(self); 573 574 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 575 576 switch (act) { 577 case DVACT_DEACTIVATE: 578 if_deactivate(sc->sc_ic.ic_ifp); 579 return 0; 580 default: 581 return EOPNOTSUPP; 582 } 583 } 584 585 static int 586 urtwn_open_pipes(struct urtwn_softc *sc) 587 { 588 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 589 static uint8_t epaddr[3]; 590 static uint8_t rxepaddr[3]; 591 usb_interface_descriptor_t *id; 592 usb_endpoint_descriptor_t *ed; 593 size_t i, ntx = 0, nrx = 0; 594 int error; 595 596 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 597 598 /* Determine the number of bulk-out pipes. */ 599 id = usbd_get_interface_descriptor(sc->sc_iface); 600 for (i = 0; i < id->bNumEndpoints; i++) { 601 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 602 if (ed != NULL && 603 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 604 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 605 epaddr[ntx] = ed->bEndpointAddress; 606 ntx++; 607 } 608 if (ed != NULL && 609 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 610 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 611 rxepaddr[nrx] = ed->bEndpointAddress; 612 nrx++; 613 } 614 } 615 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 616 device_xname(sc->sc_dev), __func__, ntx)); 617 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 618 aprint_error_dev(sc->sc_dev, 619 "%zd: invalid number of Tx bulk pipes\n", ntx); 620 return EIO; 621 } 622 sc->rx_npipe = nrx; 623 sc->tx_npipe = ntx; 624 625 /* Open bulk-in pipe at address 0x81. */ 626 for (i = 0; i < nrx; i++) { 627 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 628 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 629 if (error != 0) { 630 aprint_error_dev(sc->sc_dev, 631 "could not open Rx bulk pipe 0x%02x: %d\n", 632 rxepaddr[i], error); 633 goto fail; 634 } 635 } 636 637 /* Open bulk-out pipes (up to 3). */ 638 for (i = 0; i < ntx; i++) { 639 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 640 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 641 if (error != 0) { 642 aprint_error_dev(sc->sc_dev, 643 "could not open Tx bulk pipe 0x%02x: %d\n", 644 epaddr[i], error); 645 goto fail; 646 } 647 } 648 649 /* Map 802.11 access categories to USB pipes. */ 650 sc->ac2idx[WME_AC_BK] = 651 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 652 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 653 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 654 655 fail: 656 if (error != 0) 657 urtwn_close_pipes(sc); 658 return error; 659 } 660 661 static void 662 urtwn_close_pipes(struct urtwn_softc *sc) 663 { 664 struct usbd_pipe *pipe; 665 size_t i; 666 667 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 668 669 /* Close Rx pipes. */ 670 CTASSERT(sizeof(pipe) == sizeof(void *)); 671 for (i = 0; i < sc->rx_npipe; i++) { 672 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 673 if (pipe != NULL) { 674 usbd_close_pipe(pipe); 675 } 676 } 677 678 /* Close Tx pipes. */ 679 for (i = 0; i < sc->tx_npipe; i++) { 680 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 681 if (pipe != NULL) { 682 usbd_close_pipe(pipe); 683 } 684 } 685 } 686 687 static int 688 urtwn_alloc_rx_list(struct urtwn_softc *sc) 689 { 690 struct urtwn_rx_data *data; 691 size_t i; 692 int error = 0; 693 694 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 695 696 for (size_t j = 0; j < sc->rx_npipe; j++) { 697 TAILQ_INIT(&sc->rx_free_list[j]); 698 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 699 data = &sc->rx_data[j][i]; 700 701 data->sc = sc; /* Backpointer for callbacks. */ 702 703 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 704 USBD_SHORT_XFER_OK, 0, &data->xfer); 705 if (error) { 706 aprint_error_dev(sc->sc_dev, 707 "could not allocate xfer\n"); 708 break; 709 } 710 711 data->buf = usbd_get_buffer(data->xfer); 712 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 713 } 714 } 715 if (error != 0) 716 urtwn_free_rx_list(sc); 717 return error; 718 } 719 720 static void 721 urtwn_free_rx_list(struct urtwn_softc *sc) 722 { 723 struct usbd_xfer *xfer; 724 size_t i; 725 726 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 727 728 /* NB: Caller must abort pipe first. */ 729 for (size_t j = 0; j < sc->rx_npipe; j++) { 730 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 731 CTASSERT(sizeof(xfer) == sizeof(void *)); 732 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 733 if (xfer != NULL) 734 usbd_destroy_xfer(xfer); 735 } 736 } 737 } 738 739 static int 740 urtwn_alloc_tx_list(struct urtwn_softc *sc) 741 { 742 struct urtwn_tx_data *data; 743 size_t i; 744 int error = 0; 745 746 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 747 748 mutex_enter(&sc->sc_tx_mtx); 749 for (size_t j = 0; j < sc->tx_npipe; j++) { 750 TAILQ_INIT(&sc->tx_free_list[j]); 751 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 752 data = &sc->tx_data[j][i]; 753 754 data->sc = sc; /* Backpointer for callbacks. */ 755 data->pidx = j; 756 757 error = usbd_create_xfer(sc->tx_pipe[j], 758 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 759 &data->xfer); 760 if (error) { 761 aprint_error_dev(sc->sc_dev, 762 "could not allocate xfer\n"); 763 goto fail; 764 } 765 766 data->buf = usbd_get_buffer(data->xfer); 767 768 /* Append this Tx buffer to our free list. */ 769 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 770 } 771 } 772 mutex_exit(&sc->sc_tx_mtx); 773 return 0; 774 775 fail: 776 urtwn_free_tx_list(sc); 777 mutex_exit(&sc->sc_tx_mtx); 778 return error; 779 } 780 781 static void 782 urtwn_free_tx_list(struct urtwn_softc *sc) 783 { 784 struct usbd_xfer *xfer; 785 size_t i; 786 787 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 788 789 /* NB: Caller must abort pipe first. */ 790 for (size_t j = 0; j < sc->tx_npipe; j++) { 791 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 792 CTASSERT(sizeof(xfer) == sizeof(void *)); 793 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 794 if (xfer != NULL) 795 usbd_destroy_xfer(xfer); 796 } 797 } 798 } 799 800 static void 801 urtwn_task(void *arg) 802 { 803 struct urtwn_softc *sc = arg; 804 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 805 struct urtwn_host_cmd *cmd; 806 int s; 807 808 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 809 810 /* Process host commands. */ 811 s = splusb(); 812 mutex_spin_enter(&sc->sc_task_mtx); 813 while (ring->next != ring->cur) { 814 cmd = &ring->cmd[ring->next]; 815 mutex_spin_exit(&sc->sc_task_mtx); 816 splx(s); 817 /* Invoke callback with kernel lock held. */ 818 cmd->cb(sc, cmd->data); 819 s = splusb(); 820 mutex_spin_enter(&sc->sc_task_mtx); 821 ring->queued--; 822 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 823 } 824 mutex_spin_exit(&sc->sc_task_mtx); 825 wakeup(&sc->cmdq); 826 splx(s); 827 } 828 829 static void 830 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 831 void *arg, int len) 832 { 833 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 834 struct urtwn_host_cmd *cmd; 835 int s; 836 837 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 838 device_xname(sc->sc_dev), __func__, cb, arg, len)); 839 840 s = splusb(); 841 mutex_spin_enter(&sc->sc_task_mtx); 842 cmd = &ring->cmd[ring->cur]; 843 cmd->cb = cb; 844 KASSERT(len <= sizeof(cmd->data)); 845 memcpy(cmd->data, arg, len); 846 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 847 848 /* If there is no pending command already, schedule a task. */ 849 if (!sc->sc_dying && ++ring->queued == 1) { 850 mutex_spin_exit(&sc->sc_task_mtx); 851 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 852 } else 853 mutex_spin_exit(&sc->sc_task_mtx); 854 splx(s); 855 } 856 857 static void 858 urtwn_wait_async(struct urtwn_softc *sc) 859 { 860 861 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 862 863 /* Wait for all queued asynchronous commands to complete. */ 864 while (sc->cmdq.queued > 0) 865 tsleep(&sc->cmdq, 0, "endtask", 0); 866 } 867 868 static int 869 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 870 int len) 871 { 872 usb_device_request_t req; 873 usbd_status error; 874 875 KASSERT(mutex_owned(&sc->sc_write_mtx)); 876 877 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 878 req.bRequest = R92C_REQ_REGS; 879 USETW(req.wValue, addr); 880 USETW(req.wIndex, 0); 881 USETW(req.wLength, len); 882 error = usbd_do_request(sc->sc_udev, &req, buf); 883 if (error != USBD_NORMAL_COMPLETION) { 884 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 885 device_xname(sc->sc_dev), __func__, error, addr, len)); 886 } 887 return error; 888 } 889 890 static void 891 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 892 { 893 894 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 895 device_xname(sc->sc_dev), __func__, addr, val)); 896 897 urtwn_write_region_1(sc, addr, &val, 1); 898 } 899 900 static void 901 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 902 { 903 uint8_t buf[2]; 904 905 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 906 device_xname(sc->sc_dev), __func__, addr, val)); 907 908 buf[0] = (uint8_t)val; 909 buf[1] = (uint8_t)(val >> 8); 910 urtwn_write_region_1(sc, addr, buf, 2); 911 } 912 913 static void 914 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 915 { 916 uint8_t buf[4]; 917 918 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 919 device_xname(sc->sc_dev), __func__, addr, val)); 920 921 buf[0] = (uint8_t)val; 922 buf[1] = (uint8_t)(val >> 8); 923 buf[2] = (uint8_t)(val >> 16); 924 buf[3] = (uint8_t)(val >> 24); 925 urtwn_write_region_1(sc, addr, buf, 4); 926 } 927 928 static int 929 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 930 { 931 932 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 933 device_xname(sc->sc_dev), __func__, addr, len)); 934 935 return urtwn_write_region_1(sc, addr, buf, len); 936 } 937 938 static int 939 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 940 int len) 941 { 942 usb_device_request_t req; 943 usbd_status error; 944 945 req.bmRequestType = UT_READ_VENDOR_DEVICE; 946 req.bRequest = R92C_REQ_REGS; 947 USETW(req.wValue, addr); 948 USETW(req.wIndex, 0); 949 USETW(req.wLength, len); 950 error = usbd_do_request(sc->sc_udev, &req, buf); 951 if (error != USBD_NORMAL_COMPLETION) { 952 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 953 device_xname(sc->sc_dev), __func__, error, addr, len)); 954 } 955 return error; 956 } 957 958 static uint8_t 959 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 960 { 961 uint8_t val; 962 963 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 964 return 0xff; 965 966 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 967 device_xname(sc->sc_dev), __func__, addr, val)); 968 return val; 969 } 970 971 static uint16_t 972 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 973 { 974 uint8_t buf[2]; 975 uint16_t val; 976 977 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 978 return 0xffff; 979 980 val = LE_READ_2(&buf[0]); 981 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 982 device_xname(sc->sc_dev), __func__, addr, val)); 983 return val; 984 } 985 986 static uint32_t 987 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 988 { 989 uint8_t buf[4]; 990 uint32_t val; 991 992 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 993 return 0xffffffff; 994 995 val = LE_READ_4(&buf[0]); 996 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 997 device_xname(sc->sc_dev), __func__, addr, val)); 998 return val; 999 } 1000 1001 static int 1002 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1003 { 1004 struct r92c_fw_cmd cmd; 1005 uint8_t *cp; 1006 int fwcur; 1007 int ntries; 1008 1009 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1010 device_xname(sc->sc_dev), __func__, id, buf, len)); 1011 1012 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1013 1014 mutex_enter(&sc->sc_fwcmd_mtx); 1015 fwcur = sc->fwcur; 1016 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1017 mutex_exit(&sc->sc_fwcmd_mtx); 1018 1019 /* Wait for current FW box to be empty. */ 1020 for (ntries = 0; ntries < 100; ntries++) { 1021 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1022 break; 1023 DELAY(10); 1024 } 1025 if (ntries == 100) { 1026 aprint_error_dev(sc->sc_dev, 1027 "could not send firmware command %d\n", id); 1028 return ETIMEDOUT; 1029 } 1030 1031 memset(&cmd, 0, sizeof(cmd)); 1032 KASSERT(len <= sizeof(cmd.msg)); 1033 memcpy(cmd.msg, buf, len); 1034 1035 /* Write the first word last since that will trigger the FW. */ 1036 cp = (uint8_t *)&cmd; 1037 cmd.id = id; 1038 if (len >= 4) { 1039 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1040 cmd.id |= R92C_CMD_FLAG_EXT; 1041 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1042 &cp[1], 2); 1043 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1044 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1045 (cp[5] << 24)); 1046 } else { 1047 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1048 &cp[4], 2); 1049 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1050 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1051 (cp[3] << 24)); 1052 } 1053 } else { 1054 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1055 } 1056 1057 return 0; 1058 } 1059 1060 static __inline void 1061 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1062 { 1063 1064 sc->sc_rf_write(sc, chain, addr, val); 1065 } 1066 1067 static void 1068 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1069 uint32_t val) 1070 { 1071 1072 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1073 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1074 } 1075 1076 static void 1077 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1078 uint32_t val) 1079 { 1080 1081 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1082 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1083 } 1084 1085 static void 1086 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1087 uint32_t val) 1088 { 1089 1090 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1091 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1092 } 1093 1094 static uint32_t 1095 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1096 { 1097 uint32_t reg[R92C_MAX_CHAINS], val; 1098 1099 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1100 if (chain != 0) { 1101 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1102 } 1103 1104 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1105 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1106 DELAY(1000); 1107 1108 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1109 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1110 R92C_HSSI_PARAM2_READ_EDGE); 1111 DELAY(1000); 1112 1113 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1114 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1115 DELAY(1000); 1116 1117 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1118 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1119 } else { 1120 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1121 } 1122 return MS(val, R92C_LSSI_READBACK_DATA); 1123 } 1124 1125 static int 1126 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1127 { 1128 int ntries; 1129 1130 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1131 1132 urtwn_write_4(sc, R92C_LLT_INIT, 1133 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1134 SM(R92C_LLT_INIT_ADDR, addr) | 1135 SM(R92C_LLT_INIT_DATA, data)); 1136 /* Wait for write operation to complete. */ 1137 for (ntries = 0; ntries < 20; ntries++) { 1138 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1139 R92C_LLT_INIT_OP_NO_ACTIVE) { 1140 /* Done */ 1141 return 0; 1142 } 1143 DELAY(5); 1144 } 1145 return ETIMEDOUT; 1146 } 1147 1148 static uint8_t 1149 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1150 { 1151 uint32_t reg; 1152 int ntries; 1153 1154 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1155 1156 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1157 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1158 reg &= ~R92C_EFUSE_CTRL_VALID; 1159 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1160 1161 /* Wait for read operation to complete. */ 1162 for (ntries = 0; ntries < 100; ntries++) { 1163 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1164 if (reg & R92C_EFUSE_CTRL_VALID) { 1165 /* Done */ 1166 return MS(reg, R92C_EFUSE_CTRL_DATA); 1167 } 1168 DELAY(5); 1169 } 1170 aprint_error_dev(sc->sc_dev, 1171 "could not read efuse byte at address 0x%04x\n", addr); 1172 return 0xff; 1173 } 1174 1175 static void 1176 urtwn_efuse_read(struct urtwn_softc *sc) 1177 { 1178 uint8_t *rom = (uint8_t *)&sc->rom; 1179 uint32_t reg; 1180 uint16_t addr = 0; 1181 uint8_t off, msk; 1182 size_t i; 1183 1184 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1185 1186 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1187 1188 urtwn_efuse_switch_power(sc); 1189 1190 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1191 while (addr < 512) { 1192 reg = urtwn_efuse_read_1(sc, addr); 1193 if (reg == 0xff) 1194 break; 1195 addr++; 1196 off = reg >> 4; 1197 msk = reg & 0xf; 1198 for (i = 0; i < 4; i++) { 1199 if (msk & (1U << i)) 1200 continue; 1201 1202 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1203 addr++; 1204 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1205 addr++; 1206 } 1207 } 1208 #ifdef URTWN_DEBUG 1209 if (urtwn_debug & DBG_INIT) { 1210 /* Dump ROM content. */ 1211 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1212 for (i = 0; i < (int)sizeof(sc->rom); i++) 1213 printf(":%02x", rom[i]); 1214 printf("\n"); 1215 } 1216 #endif 1217 } 1218 1219 static void 1220 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1221 { 1222 uint32_t reg; 1223 1224 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1225 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1226 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1227 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1228 } 1229 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1230 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1231 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1232 reg | R92C_SYS_FUNC_EN_ELDR); 1233 } 1234 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1235 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1236 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1237 urtwn_write_2(sc, R92C_SYS_CLKR, 1238 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1239 } 1240 } 1241 1242 static int 1243 urtwn_read_chipid(struct urtwn_softc *sc) 1244 { 1245 uint32_t reg; 1246 1247 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1248 1249 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1250 ISSET(sc->chip, URTWN_CHIP_92EU)) 1251 return 0; 1252 1253 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1254 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1255 /* test chip, not supported */ 1256 return EIO; 1257 } 1258 if (reg & R92C_SYS_CFG_TYPE_92C) { 1259 sc->chip |= URTWN_CHIP_92C; 1260 /* Check if it is a castrated 8192C. */ 1261 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1262 R92C_HPON_FSM_CHIP_BONDING_ID) == 1263 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1264 sc->chip |= URTWN_CHIP_92C_1T2R; 1265 } 1266 } 1267 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1268 sc->chip |= URTWN_CHIP_UMC; 1269 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1270 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1271 } 1272 } 1273 return 0; 1274 } 1275 1276 #ifdef URTWN_DEBUG 1277 static void 1278 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1279 { 1280 1281 aprint_normal_dev(sc->sc_dev, 1282 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1283 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1284 1285 aprint_normal_dev(sc->sc_dev, 1286 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1287 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1288 1289 aprint_normal_dev(sc->sc_dev, 1290 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1291 rp->macaddr[0], rp->macaddr[1], 1292 rp->macaddr[2], rp->macaddr[3], 1293 rp->macaddr[4], rp->macaddr[5]); 1294 1295 aprint_normal_dev(sc->sc_dev, 1296 "string %s, subcustomer_id 0x%x\n", 1297 rp->string, rp->subcustomer_id); 1298 1299 aprint_normal_dev(sc->sc_dev, 1300 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1301 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1302 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1303 1304 aprint_normal_dev(sc->sc_dev, 1305 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1306 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1307 rp->ht40_1s_tx_pwr[0][2], 1308 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1309 rp->ht40_1s_tx_pwr[1][2]); 1310 1311 aprint_normal_dev(sc->sc_dev, 1312 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1313 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1314 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1315 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1316 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1317 1318 aprint_normal_dev(sc->sc_dev, 1319 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1320 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1321 rp->ht20_tx_pwr_diff[2] & 0xf, 1322 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1323 rp->ht20_tx_pwr_diff[2] >> 4); 1324 1325 aprint_normal_dev(sc->sc_dev, 1326 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1327 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1328 rp->ofdm_tx_pwr_diff[2] & 0xf, 1329 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1330 rp->ofdm_tx_pwr_diff[2] >> 4); 1331 1332 aprint_normal_dev(sc->sc_dev, 1333 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1334 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1335 rp->ht40_max_pwr[2] & 0xf, 1336 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1337 rp->ht40_max_pwr[2] >> 4); 1338 1339 aprint_normal_dev(sc->sc_dev, 1340 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1341 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1342 rp->ht20_max_pwr[2] & 0xf, 1343 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1344 rp->ht20_max_pwr[2] >> 4); 1345 1346 aprint_normal_dev(sc->sc_dev, 1347 "xtal_calib %d, tssi %d %d, thermal %d\n", 1348 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1349 1350 aprint_normal_dev(sc->sc_dev, 1351 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1352 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1353 1354 aprint_normal_dev(sc->sc_dev, 1355 "channnel_plan %d, version %d customer_id 0x%x\n", 1356 rp->channel_plan, rp->version, rp->curstomer_id); 1357 } 1358 #endif 1359 1360 static void 1361 urtwn_read_rom(struct urtwn_softc *sc) 1362 { 1363 struct ieee80211com *ic = &sc->sc_ic; 1364 struct r92c_rom *rom = &sc->rom; 1365 1366 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1367 1368 mutex_enter(&sc->sc_write_mtx); 1369 1370 /* Read full ROM image. */ 1371 urtwn_efuse_read(sc); 1372 #ifdef URTWN_DEBUG 1373 if (urtwn_debug & DBG_REG) 1374 urtwn_dump_rom(sc, rom); 1375 #endif 1376 1377 /* XXX Weird but this is what the vendor driver does. */ 1378 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1379 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1380 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1381 1382 DPRINTFN(DBG_INIT, 1383 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1384 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1385 sc->board_type, sc->regulatory)); 1386 1387 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1388 1389 sc->sc_rf_write = urtwn_r92c_rf_write; 1390 sc->sc_power_on = urtwn_r92c_power_on; 1391 sc->sc_dma_init = urtwn_r92c_dma_init; 1392 1393 mutex_exit(&sc->sc_write_mtx); 1394 } 1395 1396 static void 1397 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1398 { 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 uint8_t *rom = sc->r88e_rom; 1401 uint32_t reg; 1402 uint16_t addr = 0; 1403 uint8_t off, msk, tmp; 1404 int i; 1405 1406 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1407 1408 mutex_enter(&sc->sc_write_mtx); 1409 1410 off = 0; 1411 urtwn_efuse_switch_power(sc); 1412 1413 /* Read full ROM image. */ 1414 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1415 while (addr < 4096) { 1416 reg = urtwn_efuse_read_1(sc, addr); 1417 if (reg == 0xff) 1418 break; 1419 addr++; 1420 if ((reg & 0x1f) == 0x0f) { 1421 tmp = (reg & 0xe0) >> 5; 1422 reg = urtwn_efuse_read_1(sc, addr); 1423 if ((reg & 0x0f) != 0x0f) 1424 off = ((reg & 0xf0) >> 1) | tmp; 1425 addr++; 1426 } else 1427 off = reg >> 4; 1428 msk = reg & 0xf; 1429 for (i = 0; i < 4; i++) { 1430 if (msk & (1 << i)) 1431 continue; 1432 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1433 addr++; 1434 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1435 addr++; 1436 } 1437 } 1438 #ifdef URTWN_DEBUG 1439 if (urtwn_debug & DBG_REG) { 1440 } 1441 #endif 1442 1443 addr = 0x10; 1444 for (i = 0; i < 6; i++) 1445 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1446 for (i = 0; i < 5; i++) 1447 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1448 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1449 if (sc->bw20_tx_pwr_diff & 0x08) 1450 sc->bw20_tx_pwr_diff |= 0xf0; 1451 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1452 if (sc->ofdm_tx_pwr_diff & 0x08) 1453 sc->ofdm_tx_pwr_diff |= 0xf0; 1454 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1455 1456 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1457 1458 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1459 sc->sc_power_on = urtwn_r92e_power_on; 1460 sc->sc_rf_write = urtwn_r92e_rf_write; 1461 } else { 1462 sc->sc_power_on = urtwn_r88e_power_on; 1463 sc->sc_rf_write = urtwn_r88e_rf_write; 1464 } 1465 sc->sc_dma_init = urtwn_r88e_dma_init; 1466 1467 mutex_exit(&sc->sc_write_mtx); 1468 } 1469 1470 static int 1471 urtwn_media_change(struct ifnet *ifp) 1472 { 1473 #ifdef URTWN_DEBUG 1474 struct urtwn_softc *sc = ifp->if_softc; 1475 #endif 1476 int error; 1477 1478 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1479 1480 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1481 return error; 1482 1483 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1484 (IFF_UP | IFF_RUNNING)) { 1485 urtwn_init(ifp); 1486 } 1487 return 0; 1488 } 1489 1490 /* 1491 * Initialize rate adaptation in firmware. 1492 */ 1493 static int 1494 urtwn_ra_init(struct urtwn_softc *sc) 1495 { 1496 static const uint8_t map[] = { 1497 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1498 }; 1499 struct ieee80211com *ic = &sc->sc_ic; 1500 struct ieee80211_node *ni = ic->ic_bss; 1501 struct ieee80211_rateset *rs = &ni->ni_rates; 1502 struct r92c_fw_cmd_macid_cfg cmd; 1503 uint32_t rates, basicrates; 1504 uint32_t mask, rrsr_mask, rrsr_rate; 1505 uint8_t mode; 1506 size_t maxrate, maxbasicrate, i, j; 1507 int error; 1508 1509 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1510 1511 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1512 1513 /* Get normal and basic rates mask. */ 1514 rates = basicrates = 1; 1515 maxrate = maxbasicrate = 0; 1516 for (i = 0; i < rs->rs_nrates; i++) { 1517 /* Convert 802.11 rate to HW rate index. */ 1518 for (j = 0; j < __arraycount(map); j++) { 1519 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1520 break; 1521 } 1522 } 1523 if (j == __arraycount(map)) { 1524 /* Unknown rate, skip. */ 1525 continue; 1526 } 1527 1528 rates |= 1U << j; 1529 if (j > maxrate) { 1530 maxrate = j; 1531 } 1532 1533 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1534 basicrates |= 1U << j; 1535 if (j > maxbasicrate) { 1536 maxbasicrate = j; 1537 } 1538 } 1539 } 1540 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1541 mode = R92C_RAID_11B; 1542 } else { 1543 mode = R92C_RAID_11BG; 1544 } 1545 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1546 "maxrate=%zx, maxbasicrate=%zx\n", 1547 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1548 maxrate, maxbasicrate)); 1549 1550 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1551 maxbasicrate |= R92C_RATE_SHORTGI; 1552 maxrate |= R92C_RATE_SHORTGI; 1553 } 1554 1555 /* Set rates mask for group addressed frames. */ 1556 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1557 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1558 cmd.macid |= URTWN_MACID_SHORTGI; 1559 1560 mask = (mode << 28) | basicrates; 1561 cmd.mask[0] = (uint8_t)mask; 1562 cmd.mask[1] = (uint8_t)(mask >> 8); 1563 cmd.mask[2] = (uint8_t)(mask >> 16); 1564 cmd.mask[3] = (uint8_t)(mask >> 24); 1565 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1566 if (error != 0) { 1567 aprint_error_dev(sc->sc_dev, 1568 "could not add broadcast station\n"); 1569 return error; 1570 } 1571 /* Set initial MRR rate. */ 1572 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1573 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1574 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1575 1576 /* Set rates mask for unicast frames. */ 1577 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1578 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1579 cmd.macid |= URTWN_MACID_SHORTGI; 1580 1581 mask = (mode << 28) | rates; 1582 cmd.mask[0] = (uint8_t)mask; 1583 cmd.mask[1] = (uint8_t)(mask >> 8); 1584 cmd.mask[2] = (uint8_t)(mask >> 16); 1585 cmd.mask[3] = (uint8_t)(mask >> 24); 1586 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1587 if (error != 0) { 1588 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1589 return error; 1590 } 1591 /* Set initial MRR rate. */ 1592 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1593 __func__, maxrate)); 1594 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1595 1596 rrsr_rate = ic->ic_fixed_rate; 1597 if (rrsr_rate == -1) 1598 rrsr_rate = 11; 1599 1600 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1601 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1602 1603 /* Indicate highest supported rate. */ 1604 ni->ni_txrate = rs->rs_nrates - 1; 1605 1606 return 0; 1607 } 1608 1609 static int 1610 urtwn_get_nettype(struct urtwn_softc *sc) 1611 { 1612 struct ieee80211com *ic = &sc->sc_ic; 1613 int type; 1614 1615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1616 1617 switch (ic->ic_opmode) { 1618 case IEEE80211_M_STA: 1619 type = R92C_CR_NETTYPE_INFRA; 1620 break; 1621 1622 case IEEE80211_M_IBSS: 1623 type = R92C_CR_NETTYPE_ADHOC; 1624 break; 1625 1626 default: 1627 type = R92C_CR_NETTYPE_NOLINK; 1628 break; 1629 } 1630 1631 return type; 1632 } 1633 1634 static void 1635 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1636 { 1637 uint8_t reg; 1638 1639 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1640 __func__, type)); 1641 1642 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1643 1644 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1645 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1646 } 1647 1648 static void 1649 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1650 { 1651 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1652 uint64_t tsf; 1653 1654 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1655 1656 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1657 1658 /* Enable TSF synchronization. */ 1659 urtwn_write_1(sc, R92C_BCN_CTRL, 1660 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1661 1662 /* Correct TSF */ 1663 urtwn_write_1(sc, R92C_BCN_CTRL, 1664 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1665 1666 /* Set initial TSF. */ 1667 tsf = ni->ni_tstamp.tsf; 1668 tsf = le64toh(tsf); 1669 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1670 tsf -= IEEE80211_DUR_TU; 1671 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1672 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1673 1674 urtwn_write_1(sc, R92C_BCN_CTRL, 1675 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1676 } 1677 1678 static void 1679 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1680 { 1681 uint8_t reg; 1682 1683 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1684 __func__, led, on)); 1685 1686 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1687 1688 if (led == URTWN_LED_LINK) { 1689 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1690 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1691 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1692 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1693 (R92C_LEDCFG0_DIS << 1)); 1694 if (on) { 1695 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1696 R92E_LEDSON; 1697 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1698 } 1699 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1700 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1701 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1702 if (!on) { 1703 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1704 urtwn_write_1(sc, R92C_LEDCFG2, 1705 reg | R92C_LEDCFG0_DIS); 1706 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1707 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1708 reg & 0xfe); 1709 } 1710 } else { 1711 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1712 if (!on) { 1713 reg |= R92C_LEDCFG0_DIS; 1714 } 1715 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1716 } 1717 sc->ledlink = on; /* Save LED state. */ 1718 } 1719 } 1720 1721 static void 1722 urtwn_calib_to(void *arg) 1723 { 1724 struct urtwn_softc *sc = arg; 1725 1726 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1727 1728 if (sc->sc_dying) 1729 return; 1730 1731 /* Do it in a process context. */ 1732 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1733 } 1734 1735 /* ARGSUSED */ 1736 static void 1737 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1738 { 1739 struct r92c_fw_cmd_rssi cmd; 1740 struct r92e_fw_cmd_rssi cmde; 1741 1742 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1743 1744 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1745 goto restart_timer; 1746 1747 mutex_enter(&sc->sc_write_mtx); 1748 if (sc->avg_pwdb != -1) { 1749 /* Indicate Rx signal strength to FW for rate adaptation. */ 1750 memset(&cmd, 0, sizeof(cmd)); 1751 memset(&cmde, 0, sizeof(cmde)); 1752 cmd.macid = 0; /* BSS. */ 1753 cmde.macid = 0; /* BSS. */ 1754 cmd.pwdb = sc->avg_pwdb; 1755 cmde.pwdb = sc->avg_pwdb; 1756 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1757 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1758 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1759 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1760 sizeof(cmd)); 1761 } else { 1762 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1763 sizeof(cmde)); 1764 } 1765 } 1766 1767 /* Do temperature compensation. */ 1768 urtwn_temp_calib(sc); 1769 mutex_exit(&sc->sc_write_mtx); 1770 1771 restart_timer: 1772 if (!sc->sc_dying) { 1773 /* Restart calibration timer. */ 1774 callout_schedule(&sc->sc_calib_to, hz); 1775 } 1776 } 1777 1778 static void 1779 urtwn_next_scan(void *arg) 1780 { 1781 struct urtwn_softc *sc = arg; 1782 int s; 1783 1784 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1785 1786 if (sc->sc_dying) 1787 return; 1788 1789 s = splnet(); 1790 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1791 ieee80211_next_scan(&sc->sc_ic); 1792 splx(s); 1793 } 1794 1795 static void 1796 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1797 { 1798 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1799 ether_sprintf(ni->ni_macaddr))); 1800 /* start with lowest Tx rate */ 1801 ni->ni_txrate = 0; 1802 } 1803 1804 static int 1805 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1806 { 1807 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1808 struct urtwn_cmd_newstate cmd; 1809 1810 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1811 device_xname(sc->sc_dev), __func__, 1812 ieee80211_state_name[nstate], nstate, arg)); 1813 1814 callout_stop(&sc->sc_scan_to); 1815 callout_stop(&sc->sc_calib_to); 1816 1817 /* Do it in a process context. */ 1818 cmd.state = nstate; 1819 cmd.arg = arg; 1820 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1821 return 0; 1822 } 1823 1824 static void 1825 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1826 { 1827 struct urtwn_cmd_newstate *cmd = arg; 1828 struct ieee80211com *ic = &sc->sc_ic; 1829 struct ieee80211_node *ni; 1830 enum ieee80211_state ostate = ic->ic_state; 1831 enum ieee80211_state nstate = cmd->state; 1832 uint32_t reg; 1833 uint8_t sifs_time, msr; 1834 int s; 1835 1836 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1837 device_xname(sc->sc_dev), __func__, 1838 ieee80211_state_name[ostate], ostate, 1839 ieee80211_state_name[nstate], nstate)); 1840 1841 s = splnet(); 1842 mutex_enter(&sc->sc_write_mtx); 1843 1844 callout_stop(&sc->sc_scan_to); 1845 callout_stop(&sc->sc_calib_to); 1846 1847 switch (ostate) { 1848 case IEEE80211_S_INIT: 1849 break; 1850 1851 case IEEE80211_S_SCAN: 1852 if (nstate != IEEE80211_S_SCAN) { 1853 /* 1854 * End of scanning 1855 */ 1856 /* flush 4-AC Queue after site_survey */ 1857 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1858 1859 /* Allow Rx from our BSSID only. */ 1860 urtwn_write_4(sc, R92C_RCR, 1861 urtwn_read_4(sc, R92C_RCR) | 1862 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1863 } 1864 break; 1865 1866 case IEEE80211_S_AUTH: 1867 case IEEE80211_S_ASSOC: 1868 break; 1869 1870 case IEEE80211_S_RUN: 1871 /* Turn link LED off. */ 1872 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1873 1874 /* Set media status to 'No Link'. */ 1875 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1876 1877 /* Stop Rx of data frames. */ 1878 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1879 1880 /* Reset TSF. */ 1881 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1882 1883 /* Disable TSF synchronization. */ 1884 urtwn_write_1(sc, R92C_BCN_CTRL, 1885 urtwn_read_1(sc, R92C_BCN_CTRL) | 1886 R92C_BCN_CTRL_DIS_TSF_UDT0); 1887 1888 /* Back to 20MHz mode */ 1889 urtwn_set_chan(sc, ic->ic_curchan, 1890 IEEE80211_HTINFO_2NDCHAN_NONE); 1891 1892 if (ic->ic_opmode == IEEE80211_M_IBSS || 1893 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1894 /* Stop BCN */ 1895 urtwn_write_1(sc, R92C_BCN_CTRL, 1896 urtwn_read_1(sc, R92C_BCN_CTRL) & 1897 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1898 } 1899 1900 /* Reset EDCA parameters. */ 1901 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1902 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1903 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1904 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1905 1906 /* flush all cam entries */ 1907 urtwn_cam_init(sc); 1908 break; 1909 } 1910 1911 switch (nstate) { 1912 case IEEE80211_S_INIT: 1913 /* Turn link LED off. */ 1914 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1915 break; 1916 1917 case IEEE80211_S_SCAN: 1918 if (ostate != IEEE80211_S_SCAN) { 1919 /* 1920 * Begin of scanning 1921 */ 1922 1923 /* Set gain for scanning. */ 1924 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1925 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1926 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1927 1928 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1929 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1930 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1931 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1932 } 1933 1934 /* Set media status to 'No Link'. */ 1935 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1936 1937 /* Allow Rx from any BSSID. */ 1938 urtwn_write_4(sc, R92C_RCR, 1939 urtwn_read_4(sc, R92C_RCR) & 1940 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1941 1942 /* Stop Rx of data frames. */ 1943 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1944 1945 /* Disable update TSF */ 1946 urtwn_write_1(sc, R92C_BCN_CTRL, 1947 urtwn_read_1(sc, R92C_BCN_CTRL) | 1948 R92C_BCN_CTRL_DIS_TSF_UDT0); 1949 } 1950 1951 /* Make link LED blink during scan. */ 1952 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1953 1954 /* Pause AC Tx queues. */ 1955 urtwn_write_1(sc, R92C_TXPAUSE, 1956 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1957 1958 urtwn_set_chan(sc, ic->ic_curchan, 1959 IEEE80211_HTINFO_2NDCHAN_NONE); 1960 1961 /* Start periodic scan. */ 1962 if (!sc->sc_dying) 1963 callout_schedule(&sc->sc_scan_to, hz / 5); 1964 break; 1965 1966 case IEEE80211_S_AUTH: 1967 /* Set initial gain under link. */ 1968 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1969 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1970 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1971 1972 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1973 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1974 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1975 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1976 } 1977 1978 /* Set media status to 'No Link'. */ 1979 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1980 1981 /* Allow Rx from any BSSID. */ 1982 urtwn_write_4(sc, R92C_RCR, 1983 urtwn_read_4(sc, R92C_RCR) & 1984 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1985 1986 urtwn_set_chan(sc, ic->ic_curchan, 1987 IEEE80211_HTINFO_2NDCHAN_NONE); 1988 break; 1989 1990 case IEEE80211_S_ASSOC: 1991 break; 1992 1993 case IEEE80211_S_RUN: 1994 ni = ic->ic_bss; 1995 1996 /* XXX: Set 20MHz mode */ 1997 urtwn_set_chan(sc, ic->ic_curchan, 1998 IEEE80211_HTINFO_2NDCHAN_NONE); 1999 2000 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2001 /* Back to 20MHz mode */ 2002 urtwn_set_chan(sc, ic->ic_curchan, 2003 IEEE80211_HTINFO_2NDCHAN_NONE); 2004 2005 /* Set media status to 'No Link'. */ 2006 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2007 2008 /* Enable Rx of data frames. */ 2009 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2010 2011 /* Allow Rx from any BSSID. */ 2012 urtwn_write_4(sc, R92C_RCR, 2013 urtwn_read_4(sc, R92C_RCR) & 2014 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2015 2016 /* Accept Rx data/control/management frames */ 2017 urtwn_write_4(sc, R92C_RCR, 2018 urtwn_read_4(sc, R92C_RCR) | 2019 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2020 2021 /* Turn link LED on. */ 2022 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2023 break; 2024 } 2025 2026 /* Set media status to 'Associated'. */ 2027 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2028 2029 /* Set BSSID. */ 2030 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2031 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2032 2033 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2034 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2035 } else { 2036 /* 802.11b/g */ 2037 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2038 } 2039 2040 /* Enable Rx of data frames. */ 2041 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2042 2043 /* Set beacon interval. */ 2044 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2045 2046 msr = urtwn_read_1(sc, R92C_MSR); 2047 msr &= R92C_MSR_MASK; 2048 switch (ic->ic_opmode) { 2049 case IEEE80211_M_STA: 2050 /* Allow Rx from our BSSID only. */ 2051 urtwn_write_4(sc, R92C_RCR, 2052 urtwn_read_4(sc, R92C_RCR) | 2053 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2054 2055 /* Enable TSF synchronization. */ 2056 urtwn_tsf_sync_enable(sc); 2057 2058 msr |= R92C_MSR_INFRA; 2059 break; 2060 case IEEE80211_M_HOSTAP: 2061 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2062 2063 /* Allow Rx from any BSSID. */ 2064 urtwn_write_4(sc, R92C_RCR, 2065 urtwn_read_4(sc, R92C_RCR) & 2066 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2067 2068 /* Reset TSF timer to zero. */ 2069 reg = urtwn_read_4(sc, R92C_TCR); 2070 reg &= ~0x01; 2071 urtwn_write_4(sc, R92C_TCR, reg); 2072 reg |= 0x01; 2073 urtwn_write_4(sc, R92C_TCR, reg); 2074 2075 msr |= R92C_MSR_AP; 2076 break; 2077 default: 2078 msr |= R92C_MSR_ADHOC; 2079 break; 2080 } 2081 urtwn_write_1(sc, R92C_MSR, msr); 2082 2083 sifs_time = 10; 2084 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2085 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2086 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2087 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2088 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2089 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2090 2091 /* Intialize rate adaptation. */ 2092 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2093 ISSET(sc->chip, URTWN_CHIP_92EU)) 2094 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2095 else 2096 urtwn_ra_init(sc); 2097 2098 /* Turn link LED on. */ 2099 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2100 2101 /* Reset average RSSI. */ 2102 sc->avg_pwdb = -1; 2103 2104 /* Reset temperature calibration state machine. */ 2105 sc->thcal_state = 0; 2106 sc->thcal_lctemp = 0; 2107 2108 /* Start periodic calibration. */ 2109 if (!sc->sc_dying) 2110 callout_schedule(&sc->sc_calib_to, hz); 2111 break; 2112 } 2113 2114 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2115 2116 mutex_exit(&sc->sc_write_mtx); 2117 splx(s); 2118 } 2119 2120 static int 2121 urtwn_wme_update(struct ieee80211com *ic) 2122 { 2123 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2124 2125 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2126 2127 /* don't override default WME values if WME is not actually enabled */ 2128 if (!(ic->ic_flags & IEEE80211_F_WME)) 2129 return 0; 2130 2131 /* Do it in a process context. */ 2132 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2133 return 0; 2134 } 2135 2136 static void 2137 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2138 { 2139 static const uint16_t ac2reg[WME_NUM_AC] = { 2140 R92C_EDCA_BE_PARAM, 2141 R92C_EDCA_BK_PARAM, 2142 R92C_EDCA_VI_PARAM, 2143 R92C_EDCA_VO_PARAM 2144 }; 2145 struct ieee80211com *ic = &sc->sc_ic; 2146 const struct wmeParams *wmep; 2147 int ac, aifs, slottime; 2148 int s; 2149 2150 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2151 __func__)); 2152 2153 s = splnet(); 2154 mutex_enter(&sc->sc_write_mtx); 2155 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2156 for (ac = 0; ac < WME_NUM_AC; ac++) { 2157 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2158 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2159 aifs = wmep->wmep_aifsn * slottime + 10; 2160 urtwn_write_4(sc, ac2reg[ac], 2161 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2162 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2163 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2164 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2165 } 2166 mutex_exit(&sc->sc_write_mtx); 2167 splx(s); 2168 } 2169 2170 static void 2171 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2172 { 2173 int pwdb; 2174 2175 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2176 device_xname(sc->sc_dev), __func__, rate, rssi)); 2177 2178 /* Convert antenna signal to percentage. */ 2179 if (rssi <= -100 || rssi >= 20) 2180 pwdb = 0; 2181 else if (rssi >= 0) 2182 pwdb = 100; 2183 else 2184 pwdb = 100 + rssi; 2185 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2186 if (rate <= 3) { 2187 /* CCK gain is smaller than OFDM/MCS gain. */ 2188 pwdb += 6; 2189 if (pwdb > 100) 2190 pwdb = 100; 2191 if (pwdb <= 14) 2192 pwdb -= 4; 2193 else if (pwdb <= 26) 2194 pwdb -= 8; 2195 else if (pwdb <= 34) 2196 pwdb -= 6; 2197 else if (pwdb <= 42) 2198 pwdb -= 2; 2199 } 2200 } 2201 if (sc->avg_pwdb == -1) /* Init. */ 2202 sc->avg_pwdb = pwdb; 2203 else if (sc->avg_pwdb < pwdb) 2204 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2205 else 2206 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2207 2208 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2209 device_xname(sc->sc_dev), __func__, 2210 rate, rssi, pwdb, sc->avg_pwdb)); 2211 } 2212 2213 static int8_t 2214 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2215 { 2216 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2217 struct r92c_rx_phystat *phy; 2218 struct r92c_rx_cck *cck; 2219 uint8_t rpt; 2220 int8_t rssi; 2221 2222 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2223 __func__, rate)); 2224 2225 if (rate <= 3) { 2226 cck = (struct r92c_rx_cck *)physt; 2227 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2228 rpt = (cck->agc_rpt >> 5) & 0x3; 2229 rssi = (cck->agc_rpt & 0x1f) << 1; 2230 } else { 2231 rpt = (cck->agc_rpt >> 6) & 0x3; 2232 rssi = cck->agc_rpt & 0x3e; 2233 } 2234 rssi = cckoff[rpt] - rssi; 2235 } else { /* OFDM/HT. */ 2236 phy = (struct r92c_rx_phystat *)physt; 2237 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2238 } 2239 return rssi; 2240 } 2241 2242 static int8_t 2243 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2244 { 2245 struct r92c_rx_phystat *phy; 2246 struct r88e_rx_cck *cck; 2247 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2248 int8_t rssi; 2249 2250 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2251 __func__, rate)); 2252 2253 rssi = 0; 2254 if (rate <= 3) { 2255 cck = (struct r88e_rx_cck *)physt; 2256 cck_agc_rpt = cck->agc_rpt; 2257 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2258 vga_idx = cck_agc_rpt & 0x1f; 2259 switch (lna_idx) { 2260 case 7: 2261 if (vga_idx <= 27) 2262 rssi = -100 + 2* (27 - vga_idx); 2263 else 2264 rssi = -100; 2265 break; 2266 case 6: 2267 rssi = -48 + 2 * (2 - vga_idx); 2268 break; 2269 case 5: 2270 rssi = -42 + 2 * (7 - vga_idx); 2271 break; 2272 case 4: 2273 rssi = -36 + 2 * (7 - vga_idx); 2274 break; 2275 case 3: 2276 rssi = -24 + 2 * (7 - vga_idx); 2277 break; 2278 case 2: 2279 rssi = -12 + 2 * (5 - vga_idx); 2280 break; 2281 case 1: 2282 rssi = 8 - (2 * vga_idx); 2283 break; 2284 case 0: 2285 rssi = 14 - (2 * vga_idx); 2286 break; 2287 } 2288 rssi += 6; 2289 } else { /* OFDM/HT. */ 2290 phy = (struct r92c_rx_phystat *)physt; 2291 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2292 } 2293 return rssi; 2294 } 2295 2296 static void 2297 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2298 { 2299 struct ieee80211com *ic = &sc->sc_ic; 2300 struct ifnet *ifp = ic->ic_ifp; 2301 struct ieee80211_frame *wh; 2302 struct ieee80211_node *ni; 2303 struct r92c_rx_stat *stat; 2304 uint32_t rxdw0, rxdw3; 2305 struct mbuf *m; 2306 uint8_t rate; 2307 int8_t rssi = 0; 2308 int s, infosz; 2309 2310 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2311 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2312 2313 stat = (struct r92c_rx_stat *)buf; 2314 rxdw0 = le32toh(stat->rxdw0); 2315 rxdw3 = le32toh(stat->rxdw3); 2316 2317 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2318 /* 2319 * This should not happen since we setup our Rx filter 2320 * to not receive these frames. 2321 */ 2322 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2323 device_xname(sc->sc_dev), __func__)); 2324 ifp->if_ierrors++; 2325 return; 2326 } 2327 /* 2328 * XXX: This will drop most control packets. Do we really 2329 * want this in IEEE80211_M_MONITOR mode? 2330 */ 2331 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2332 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2333 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2334 device_xname(sc->sc_dev), __func__, pktlen)); 2335 ic->ic_stats.is_rx_tooshort++; 2336 ifp->if_ierrors++; 2337 return; 2338 } 2339 if (__predict_false(pktlen > MCLBYTES)) { 2340 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2341 device_xname(sc->sc_dev), __func__, pktlen)); 2342 ifp->if_ierrors++; 2343 return; 2344 } 2345 2346 rate = MS(rxdw3, R92C_RXDW3_RATE); 2347 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2348 2349 /* Get RSSI from PHY status descriptor if present. */ 2350 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2351 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2352 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2353 else 2354 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2355 /* Update our average RSSI. */ 2356 urtwn_update_avgrssi(sc, rate, rssi); 2357 } 2358 2359 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2360 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2361 2362 MGETHDR(m, M_DONTWAIT, MT_DATA); 2363 if (__predict_false(m == NULL)) { 2364 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2365 ic->ic_stats.is_rx_nobuf++; 2366 ifp->if_ierrors++; 2367 return; 2368 } 2369 if (pktlen > (int)MHLEN) { 2370 MCLGET(m, M_DONTWAIT); 2371 if (__predict_false(!(m->m_flags & M_EXT))) { 2372 aprint_error_dev(sc->sc_dev, 2373 "couldn't allocate rx mbuf cluster\n"); 2374 m_freem(m); 2375 ic->ic_stats.is_rx_nobuf++; 2376 ifp->if_ierrors++; 2377 return; 2378 } 2379 } 2380 2381 /* Finalize mbuf. */ 2382 m_set_rcvif(m, ifp); 2383 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2384 memcpy(mtod(m, uint8_t *), wh, pktlen); 2385 m->m_pkthdr.len = m->m_len = pktlen; 2386 2387 s = splnet(); 2388 if (__predict_false(sc->sc_drvbpf != NULL)) { 2389 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2390 2391 tap->wr_flags = 0; 2392 if (!(rxdw3 & R92C_RXDW3_HT)) { 2393 switch (rate) { 2394 /* CCK. */ 2395 case 0: tap->wr_rate = 2; break; 2396 case 1: tap->wr_rate = 4; break; 2397 case 2: tap->wr_rate = 11; break; 2398 case 3: tap->wr_rate = 22; break; 2399 /* OFDM. */ 2400 case 4: tap->wr_rate = 12; break; 2401 case 5: tap->wr_rate = 18; break; 2402 case 6: tap->wr_rate = 24; break; 2403 case 7: tap->wr_rate = 36; break; 2404 case 8: tap->wr_rate = 48; break; 2405 case 9: tap->wr_rate = 72; break; 2406 case 10: tap->wr_rate = 96; break; 2407 case 11: tap->wr_rate = 108; break; 2408 } 2409 } else if (rate >= 12) { /* MCS0~15. */ 2410 /* Bit 7 set means HT MCS instead of rate. */ 2411 tap->wr_rate = 0x80 | (rate - 12); 2412 } 2413 tap->wr_dbm_antsignal = rssi; 2414 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2415 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2416 2417 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2418 } 2419 2420 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2421 2422 /* push the frame up to the 802.11 stack */ 2423 ieee80211_input(ic, m, ni, rssi, 0); 2424 2425 /* Node is no longer needed. */ 2426 ieee80211_free_node(ni); 2427 2428 splx(s); 2429 } 2430 2431 static void 2432 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2433 { 2434 struct urtwn_rx_data *data = priv; 2435 struct urtwn_softc *sc = data->sc; 2436 struct r92c_rx_stat *stat; 2437 size_t pidx = data->pidx; 2438 uint32_t rxdw0; 2439 uint8_t *buf; 2440 int len, totlen, pktlen, infosz, npkts; 2441 2442 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2443 device_xname(sc->sc_dev), __func__, status)); 2444 2445 mutex_enter(&sc->sc_rx_mtx); 2446 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2447 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2448 /* Put this Rx buffer back to our free list. */ 2449 mutex_exit(&sc->sc_rx_mtx); 2450 2451 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2452 if (status == USBD_STALLED) 2453 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2454 else if (status != USBD_CANCELLED) 2455 goto resubmit; 2456 return; 2457 } 2458 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2459 2460 if (__predict_false(len < (int)sizeof(*stat))) { 2461 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2462 device_xname(sc->sc_dev), __func__, len)); 2463 goto resubmit; 2464 } 2465 buf = data->buf; 2466 2467 /* Get the number of encapsulated frames. */ 2468 stat = (struct r92c_rx_stat *)buf; 2469 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2470 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2471 device_xname(sc->sc_dev), __func__, npkts)); 2472 2473 /* Process all of them. */ 2474 while (npkts-- > 0) { 2475 if (__predict_false(len < (int)sizeof(*stat))) { 2476 DPRINTFN(DBG_RX, 2477 ("%s: %s: len(%d) is short than header\n", 2478 device_xname(sc->sc_dev), __func__, len)); 2479 break; 2480 } 2481 stat = (struct r92c_rx_stat *)buf; 2482 rxdw0 = le32toh(stat->rxdw0); 2483 2484 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2485 if (__predict_false(pktlen == 0)) { 2486 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2487 device_xname(sc->sc_dev), __func__)); 2488 break; 2489 } 2490 2491 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2492 2493 /* Make sure everything fits in xfer. */ 2494 totlen = sizeof(*stat) + infosz + pktlen; 2495 if (__predict_false(totlen > len)) { 2496 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2497 device_xname(sc->sc_dev), __func__, totlen, 2498 (int)sizeof(*stat), infosz, pktlen, len)); 2499 break; 2500 } 2501 2502 /* Process 802.11 frame. */ 2503 urtwn_rx_frame(sc, buf, pktlen); 2504 2505 /* Next chunk is 128-byte aligned. */ 2506 totlen = roundup2(totlen, 128); 2507 buf += totlen; 2508 len -= totlen; 2509 } 2510 2511 resubmit: 2512 /* Setup a new transfer. */ 2513 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2514 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2515 (void)usbd_transfer(xfer); 2516 } 2517 2518 static void 2519 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2520 { 2521 struct urtwn_tx_data *data = priv; 2522 struct urtwn_softc *sc = data->sc; 2523 struct ifnet *ifp = &sc->sc_if; 2524 size_t pidx = data->pidx; 2525 int s; 2526 2527 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2528 device_xname(sc->sc_dev), __func__, status)); 2529 2530 mutex_enter(&sc->sc_tx_mtx); 2531 /* Put this Tx buffer back to our free list. */ 2532 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2533 mutex_exit(&sc->sc_tx_mtx); 2534 2535 s = splnet(); 2536 sc->tx_timer = 0; 2537 ifp->if_flags &= ~IFF_OACTIVE; 2538 2539 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2540 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2541 if (status == USBD_STALLED) { 2542 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2543 usbd_clear_endpoint_stall_async(pipe); 2544 } 2545 printf("ERROR1\n"); 2546 ifp->if_oerrors++; 2547 } 2548 splx(s); 2549 return; 2550 } 2551 2552 ifp->if_opackets++; 2553 urtwn_start(ifp); 2554 splx(s); 2555 2556 } 2557 2558 static int 2559 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2560 struct urtwn_tx_data *data) 2561 { 2562 struct ieee80211com *ic = &sc->sc_ic; 2563 struct ieee80211_frame *wh; 2564 struct ieee80211_key *k = NULL; 2565 struct r92c_tx_desc *txd; 2566 size_t i, padsize, xferlen, txd_len; 2567 uint16_t seq, sum; 2568 uint8_t raid, type, tid; 2569 int s, hasqos, error; 2570 2571 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2572 2573 wh = mtod(m, struct ieee80211_frame *); 2574 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2575 txd_len = sizeof(*txd); 2576 2577 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2578 txd_len = 32; 2579 2580 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2581 k = ieee80211_crypto_encap(ic, ni, m); 2582 if (k == NULL) 2583 return ENOBUFS; 2584 2585 /* packet header may have moved, reset our local pointer */ 2586 wh = mtod(m, struct ieee80211_frame *); 2587 } 2588 2589 if (__predict_false(sc->sc_drvbpf != NULL)) { 2590 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2591 2592 tap->wt_flags = 0; 2593 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2594 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2595 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2596 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2597 2598 /* XXX: set tap->wt_rate? */ 2599 2600 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2601 } 2602 2603 /* non-qos data frames */ 2604 tid = R92C_TXDW1_QSEL_BE; 2605 if ((hasqos = ieee80211_has_qos(wh))) { 2606 /* data frames in 11n mode */ 2607 struct ieee80211_qosframe *qwh = (void *)wh; 2608 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2609 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2610 tid = R92C_TXDW1_QSEL_MGNT; 2611 } 2612 2613 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2614 padsize = 8; 2615 else 2616 padsize = 0; 2617 2618 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2619 padsize = 0; 2620 2621 /* Fill Tx descriptor. */ 2622 txd = (struct r92c_tx_desc *)data->buf; 2623 memset(txd, 0, txd_len + padsize); 2624 2625 txd->txdw0 |= htole32( 2626 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2627 SM(R92C_TXDW0_OFFSET, txd_len)); 2628 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2629 txd->txdw0 |= htole32( 2630 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2631 } 2632 2633 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2634 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2635 2636 /* fix pad field */ 2637 if (padsize > 0) { 2638 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2639 device_xname(sc->sc_dev), __func__, padsize)); 2640 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2641 } 2642 2643 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2644 type == IEEE80211_FC0_TYPE_DATA) { 2645 if (ic->ic_curmode == IEEE80211_MODE_11B) 2646 raid = R92C_RAID_11B; 2647 else 2648 raid = R92C_RAID_11BG; 2649 DPRINTFN(DBG_TX, 2650 ("%s: %s: data packet: tid=%d, raid=%d\n", 2651 device_xname(sc->sc_dev), __func__, tid, raid)); 2652 2653 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2654 txd->txdw1 |= htole32( 2655 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2656 SM(R92C_TXDW1_QSEL, tid) | 2657 SM(R92C_TXDW1_RAID, raid) | 2658 R92C_TXDW1_AGGBK); 2659 } else 2660 txd->txdw1 |= htole32( 2661 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2662 SM(R92C_TXDW1_QSEL, tid) | 2663 SM(R92C_TXDW1_RAID, raid) | 2664 R92C_TXDW1_AGGBK); 2665 2666 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2667 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2668 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2669 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2670 2671 if (hasqos) { 2672 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2673 } 2674 2675 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2676 /* for 11g */ 2677 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2678 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2679 R92C_TXDW4_HWRTSEN); 2680 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2681 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2682 R92C_TXDW4_HWRTSEN); 2683 } 2684 } 2685 /* Send RTS at OFDM24. */ 2686 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2687 txd->txdw5 |= htole32(0x0001ff00); 2688 /* Send data at OFDM54. */ 2689 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2690 txd->txdw5 |= htole32(0x13 & 0x3f); 2691 else 2692 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2693 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2694 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2695 device_xname(sc->sc_dev), __func__)); 2696 txd->txdw1 |= htole32( 2697 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2698 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2699 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2700 2701 /* Force CCK1. */ 2702 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2703 /* Use 1Mbps */ 2704 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2705 } else { 2706 /* broadcast or multicast packets */ 2707 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2708 device_xname(sc->sc_dev), __func__)); 2709 txd->txdw1 |= htole32( 2710 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2711 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2712 2713 /* Force CCK1. */ 2714 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2715 /* Use 1Mbps */ 2716 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2717 } 2718 /* Set sequence number */ 2719 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2720 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2721 txd->txdseq |= htole16(seq); 2722 2723 if (!hasqos) { 2724 /* Use HW sequence numbering for non-QoS frames. */ 2725 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2726 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2727 } 2728 } else { 2729 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2730 R92E_HWSEQ_SHIFT); 2731 if (!hasqos) { 2732 /* Use HW sequence numbering for non-QoS frames. */ 2733 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2734 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2735 } 2736 } 2737 2738 /* Compute Tx descriptor checksum. */ 2739 sum = 0; 2740 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2741 sum ^= ((uint16_t *)txd)[i]; 2742 txd->txdsum = sum; /* NB: already little endian. */ 2743 2744 xferlen = txd_len + m->m_pkthdr.len + padsize; 2745 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2746 2747 s = splnet(); 2748 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2749 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2750 urtwn_txeof); 2751 error = usbd_transfer(data->xfer); 2752 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2753 error != USBD_IN_PROGRESS)) { 2754 splx(s); 2755 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2756 device_xname(sc->sc_dev), __func__, error)); 2757 return error; 2758 } 2759 splx(s); 2760 return 0; 2761 } 2762 2763 struct urtwn_tx_data * 2764 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2765 { 2766 struct urtwn_tx_data *data = NULL; 2767 2768 mutex_enter(&sc->sc_tx_mtx); 2769 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2770 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2771 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2772 } 2773 mutex_exit(&sc->sc_tx_mtx); 2774 2775 return data; 2776 } 2777 2778 static void 2779 urtwn_start(struct ifnet *ifp) 2780 { 2781 struct urtwn_softc *sc = ifp->if_softc; 2782 struct ieee80211com *ic = &sc->sc_ic; 2783 struct urtwn_tx_data *data; 2784 struct ether_header *eh; 2785 struct ieee80211_node *ni; 2786 struct mbuf *m; 2787 2788 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2789 2790 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2791 return; 2792 2793 data = NULL; 2794 for (;;) { 2795 /* Send pending management frames first. */ 2796 IF_POLL(&ic->ic_mgtq, m); 2797 if (m != NULL) { 2798 /* Use AC_VO for management frames. */ 2799 2800 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2801 2802 if (data == NULL) { 2803 ifp->if_flags |= IFF_OACTIVE; 2804 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2805 device_xname(sc->sc_dev))); 2806 return; 2807 } 2808 IF_DEQUEUE(&ic->ic_mgtq, m); 2809 ni = M_GETCTX(m, struct ieee80211_node *); 2810 M_CLEARCTX(m); 2811 goto sendit; 2812 } 2813 if (ic->ic_state != IEEE80211_S_RUN) 2814 break; 2815 2816 /* Encapsulate and send data frames. */ 2817 IFQ_POLL(&ifp->if_snd, m); 2818 if (m == NULL) 2819 break; 2820 2821 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2822 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2823 uint8_t qid = WME_AC_BE; 2824 if (ieee80211_has_qos(wh)) { 2825 /* data frames in 11n mode */ 2826 struct ieee80211_qosframe *qwh = (void *)wh; 2827 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2828 qid = TID_TO_WME_AC(tid); 2829 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2830 qid = WME_AC_VO; 2831 } 2832 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2833 2834 if (data == NULL) { 2835 ifp->if_flags |= IFF_OACTIVE; 2836 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2837 device_xname(sc->sc_dev))); 2838 return; 2839 } 2840 IFQ_DEQUEUE(&ifp->if_snd, m); 2841 2842 if (m->m_len < (int)sizeof(*eh) && 2843 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2844 printf("ERROR6\n"); 2845 ifp->if_oerrors++; 2846 continue; 2847 } 2848 eh = mtod(m, struct ether_header *); 2849 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2850 if (ni == NULL) { 2851 m_freem(m); 2852 printf("ERROR5\n"); 2853 ifp->if_oerrors++; 2854 continue; 2855 } 2856 2857 bpf_mtap(ifp, m); 2858 2859 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2860 ieee80211_free_node(ni); 2861 printf("ERROR4\n"); 2862 ifp->if_oerrors++; 2863 continue; 2864 } 2865 sendit: 2866 bpf_mtap3(ic->ic_rawbpf, m); 2867 2868 if (urtwn_tx(sc, m, ni, data) != 0) { 2869 m_freem(m); 2870 ieee80211_free_node(ni); 2871 printf("ERROR3\n"); 2872 ifp->if_oerrors++; 2873 continue; 2874 } 2875 m_freem(m); 2876 ieee80211_free_node(ni); 2877 sc->tx_timer = 5; 2878 ifp->if_timer = 1; 2879 } 2880 } 2881 2882 static void 2883 urtwn_watchdog(struct ifnet *ifp) 2884 { 2885 struct urtwn_softc *sc = ifp->if_softc; 2886 2887 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2888 2889 ifp->if_timer = 0; 2890 2891 if (sc->tx_timer > 0) { 2892 if (--sc->tx_timer == 0) { 2893 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2894 /* urtwn_init(ifp); XXX needs a process context! */ 2895 printf("ERROR2\n"); 2896 ifp->if_oerrors++; 2897 return; 2898 } 2899 ifp->if_timer = 1; 2900 } 2901 ieee80211_watchdog(&sc->sc_ic); 2902 } 2903 2904 static int 2905 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2906 { 2907 struct urtwn_softc *sc = ifp->if_softc; 2908 struct ieee80211com *ic = &sc->sc_ic; 2909 int s, error = 0; 2910 2911 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2912 device_xname(sc->sc_dev), __func__, cmd, data)); 2913 2914 s = splnet(); 2915 2916 switch (cmd) { 2917 case SIOCSIFFLAGS: 2918 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2919 break; 2920 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2921 case IFF_UP | IFF_RUNNING: 2922 break; 2923 case IFF_UP: 2924 urtwn_init(ifp); 2925 break; 2926 case IFF_RUNNING: 2927 urtwn_stop(ifp, 1); 2928 break; 2929 case 0: 2930 break; 2931 } 2932 break; 2933 2934 case SIOCADDMULTI: 2935 case SIOCDELMULTI: 2936 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2937 /* setup multicast filter, etc */ 2938 error = 0; 2939 } 2940 break; 2941 2942 default: 2943 error = ieee80211_ioctl(ic, cmd, data); 2944 break; 2945 } 2946 if (error == ENETRESET) { 2947 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2948 (IFF_UP | IFF_RUNNING) && 2949 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2950 urtwn_init(ifp); 2951 } 2952 error = 0; 2953 } 2954 2955 splx(s); 2956 2957 return error; 2958 } 2959 2960 static __inline int 2961 urtwn_power_on(struct urtwn_softc *sc) 2962 { 2963 2964 return sc->sc_power_on(sc); 2965 } 2966 2967 static int 2968 urtwn_r92c_power_on(struct urtwn_softc *sc) 2969 { 2970 uint32_t reg; 2971 int ntries; 2972 2973 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2974 2975 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2976 2977 /* Wait for autoload done bit. */ 2978 for (ntries = 0; ntries < 1000; ntries++) { 2979 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2980 break; 2981 DELAY(5); 2982 } 2983 if (ntries == 1000) { 2984 aprint_error_dev(sc->sc_dev, 2985 "timeout waiting for chip autoload\n"); 2986 return ETIMEDOUT; 2987 } 2988 2989 /* Unlock ISO/CLK/Power control register. */ 2990 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2991 /* Move SPS into PWM mode. */ 2992 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2993 DELAY(5); 2994 2995 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2996 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2997 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2998 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2999 DELAY(100); 3000 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3001 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3002 ~R92C_SYS_ISO_CTRL_MD2PP); 3003 } 3004 3005 /* Auto enable WLAN. */ 3006 urtwn_write_2(sc, R92C_APS_FSMCO, 3007 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3008 for (ntries = 0; ntries < 1000; ntries++) { 3009 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3010 R92C_APS_FSMCO_APFM_ONMAC)) 3011 break; 3012 DELAY(100); 3013 } 3014 if (ntries == 1000) { 3015 aprint_error_dev(sc->sc_dev, 3016 "timeout waiting for MAC auto ON\n"); 3017 return ETIMEDOUT; 3018 } 3019 3020 /* Enable radio, GPIO and LED functions. */ 3021 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3022 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3023 urtwn_write_2(sc, R92C_APS_FSMCO, 3024 R92C_APS_FSMCO_AFSM_HSUS | 3025 R92C_APS_FSMCO_PDN_EN | 3026 R92C_APS_FSMCO_PFM_ALDN); 3027 3028 /* Release RF digital isolation. */ 3029 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3030 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3031 3032 /* Initialize MAC. */ 3033 urtwn_write_1(sc, R92C_APSD_CTRL, 3034 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3035 for (ntries = 0; ntries < 200; ntries++) { 3036 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3037 R92C_APSD_CTRL_OFF_STATUS)) 3038 break; 3039 DELAY(5); 3040 } 3041 if (ntries == 200) { 3042 aprint_error_dev(sc->sc_dev, 3043 "timeout waiting for MAC initialization\n"); 3044 return ETIMEDOUT; 3045 } 3046 3047 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3048 reg = urtwn_read_2(sc, R92C_CR); 3049 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3050 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3051 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3052 R92C_CR_ENSEC; 3053 urtwn_write_2(sc, R92C_CR, reg); 3054 3055 urtwn_write_1(sc, 0xfe10, 0x19); 3056 return 0; 3057 } 3058 3059 static int 3060 urtwn_r92e_power_on(struct urtwn_softc *sc) 3061 { 3062 uint32_t reg; 3063 uint32_t val; 3064 int ntries; 3065 3066 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3067 3068 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3069 3070 /* Enable radio, GPIO and LED functions. */ 3071 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3072 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3073 urtwn_write_2(sc, R92C_APS_FSMCO, 3074 R92C_APS_FSMCO_AFSM_HSUS | 3075 R92C_APS_FSMCO_PDN_EN | 3076 R92C_APS_FSMCO_PFM_ALDN); 3077 3078 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3079 /* LDO. */ 3080 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3081 } 3082 else { 3083 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3084 R92C_SYS_SWR_CTRL2) & 0xffff); 3085 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3086 } 3087 3088 for (ntries = 0; ntries < 2; ntries++) { 3089 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3090 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3091 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3092 R92C_AFE_CTRL4)); 3093 } 3094 3095 /* Reset BB. */ 3096 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3097 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3098 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3099 3100 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3101 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3102 3103 /* Disable HWPDN. */ 3104 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3105 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3106 3107 /* Disable WL suspend. */ 3108 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3109 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3110 R92C_APS_FSMCO_AFSM_HSUS)); 3111 3112 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3113 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3114 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3115 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3116 for (ntries = 0; ntries < 10000; ntries++) { 3117 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3118 R92C_APS_FSMCO_APFM_ONMAC; 3119 if (val == 0x0) 3120 break; 3121 DELAY(10); 3122 } 3123 if (ntries == 10000) { 3124 aprint_error_dev(sc->sc_dev, 3125 "timeout waiting for chip power up\n"); 3126 return ETIMEDOUT; 3127 } 3128 3129 urtwn_write_2(sc, R92C_CR, 0x00); 3130 reg = urtwn_read_2(sc, R92C_CR); 3131 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3132 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3133 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3134 urtwn_write_2(sc, R92C_CR, reg); 3135 3136 return 0; 3137 } 3138 3139 static int 3140 urtwn_r88e_power_on(struct urtwn_softc *sc) 3141 { 3142 uint32_t reg; 3143 uint8_t val; 3144 int ntries; 3145 3146 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3147 3148 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3149 3150 /* Wait for power ready bit. */ 3151 for (ntries = 0; ntries < 5000; ntries++) { 3152 val = urtwn_read_1(sc, 0x6) & 0x2; 3153 if (val == 0x2) 3154 break; 3155 DELAY(10); 3156 } 3157 if (ntries == 5000) { 3158 aprint_error_dev(sc->sc_dev, 3159 "timeout waiting for chip power up\n"); 3160 return ETIMEDOUT; 3161 } 3162 3163 /* Reset BB. */ 3164 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3165 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3166 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3167 3168 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3169 3170 /* Disable HWPDN. */ 3171 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3172 3173 /* Disable WL suspend. */ 3174 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3175 3176 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3177 for (ntries = 0; ntries < 5000; ntries++) { 3178 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3179 break; 3180 DELAY(10); 3181 } 3182 if (ntries == 5000) 3183 return ETIMEDOUT; 3184 3185 /* Enable LDO normal mode. */ 3186 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3187 3188 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3189 urtwn_write_2(sc, R92C_CR, 0); 3190 reg = urtwn_read_2(sc, R92C_CR); 3191 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3192 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3193 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3194 urtwn_write_2(sc, R92C_CR, reg); 3195 3196 return 0; 3197 } 3198 3199 static int 3200 urtwn_llt_init(struct urtwn_softc *sc) 3201 { 3202 size_t i, page_count, pktbuf_count; 3203 uint32_t val; 3204 int error; 3205 3206 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3207 3208 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3209 3210 if (sc->chip & URTWN_CHIP_88E) 3211 page_count = R88E_TX_PAGE_COUNT; 3212 else if (sc->chip & URTWN_CHIP_92EU) 3213 page_count = R92E_TX_PAGE_COUNT; 3214 else 3215 page_count = R92C_TX_PAGE_COUNT; 3216 if (sc->chip & URTWN_CHIP_88E) 3217 pktbuf_count = R88E_TXPKTBUF_COUNT; 3218 else if (sc->chip & URTWN_CHIP_92EU) 3219 pktbuf_count = R88E_TXPKTBUF_COUNT; 3220 else 3221 pktbuf_count = R92C_TXPKTBUF_COUNT; 3222 3223 if (sc->chip & URTWN_CHIP_92EU) { 3224 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3225 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3226 DELAY(100); 3227 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3228 if (val & R92E_AUTO_LLT_EN) 3229 return EIO; 3230 return 0; 3231 } 3232 3233 /* Reserve pages [0; page_count]. */ 3234 for (i = 0; i < page_count; i++) { 3235 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3236 return error; 3237 } 3238 /* NB: 0xff indicates end-of-list. */ 3239 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3240 return error; 3241 /* 3242 * Use pages [page_count + 1; pktbuf_count - 1] 3243 * as ring buffer. 3244 */ 3245 for (++i; i < pktbuf_count - 1; i++) { 3246 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3247 return error; 3248 } 3249 /* Make the last page point to the beginning of the ring buffer. */ 3250 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3251 return error; 3252 } 3253 3254 static void 3255 urtwn_fw_reset(struct urtwn_softc *sc) 3256 { 3257 uint16_t reg; 3258 int ntries; 3259 3260 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3261 3262 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3263 3264 /* Tell 8051 to reset itself. */ 3265 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3266 3267 /* Wait until 8051 resets by itself. */ 3268 for (ntries = 0; ntries < 100; ntries++) { 3269 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3270 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3271 return; 3272 DELAY(50); 3273 } 3274 /* Force 8051 reset. */ 3275 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3276 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3277 } 3278 3279 static void 3280 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3281 { 3282 uint16_t reg; 3283 3284 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3285 3286 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3287 3288 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3289 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3290 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3291 } 3292 DELAY(50); 3293 3294 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3295 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3296 DELAY(50); 3297 3298 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3299 DELAY(50); 3300 3301 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3302 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3303 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3304 } 3305 DELAY(50); 3306 3307 } 3308 3309 static int 3310 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3311 { 3312 uint32_t reg; 3313 int off, mlen, error = 0; 3314 3315 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3316 device_xname(sc->sc_dev), __func__, page, buf, len)); 3317 3318 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3319 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3320 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3321 3322 off = R92C_FW_START_ADDR; 3323 while (len > 0) { 3324 if (len > 196) 3325 mlen = 196; 3326 else if (len > 4) 3327 mlen = 4; 3328 else 3329 mlen = 1; 3330 error = urtwn_write_region(sc, off, buf, mlen); 3331 if (error != 0) 3332 break; 3333 off += mlen; 3334 buf += mlen; 3335 len -= mlen; 3336 } 3337 return error; 3338 } 3339 3340 static int 3341 urtwn_load_firmware(struct urtwn_softc *sc) 3342 { 3343 firmware_handle_t fwh; 3344 const struct r92c_fw_hdr *hdr; 3345 const char *name; 3346 u_char *fw, *ptr; 3347 size_t len; 3348 uint32_t reg; 3349 int mlen, ntries, page, error; 3350 3351 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3352 3353 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3354 3355 /* Read firmware image from the filesystem. */ 3356 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3357 name = "rtl8188eufw.bin"; 3358 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3359 name = "rtl8192eefw.bin"; 3360 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3361 URTWN_CHIP_UMC_A_CUT) 3362 name = "rtl8192cfwU.bin"; 3363 else 3364 name = "rtl8192cfw.bin"; 3365 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3366 aprint_error_dev(sc->sc_dev, 3367 "failed load firmware of file %s (error %d)\n", name, 3368 error); 3369 return error; 3370 } 3371 const size_t fwlen = len = firmware_get_size(fwh); 3372 fw = firmware_malloc(len); 3373 if (fw == NULL) { 3374 aprint_error_dev(sc->sc_dev, 3375 "failed to allocate firmware memory\n"); 3376 firmware_close(fwh); 3377 return ENOMEM; 3378 } 3379 error = firmware_read(fwh, 0, fw, len); 3380 firmware_close(fwh); 3381 if (error != 0) { 3382 aprint_error_dev(sc->sc_dev, 3383 "failed to read firmware (error %d)\n", error); 3384 firmware_free(fw, fwlen); 3385 return error; 3386 } 3387 3388 len = fwlen; 3389 ptr = fw; 3390 hdr = (const struct r92c_fw_hdr *)ptr; 3391 /* Check if there is a valid FW header and skip it. */ 3392 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3393 (le16toh(hdr->signature) >> 4) == 0x88e || 3394 (le16toh(hdr->signature) >> 4) == 0x92e || 3395 (le16toh(hdr->signature) >> 4) == 0x92c) { 3396 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3397 device_xname(sc->sc_dev), __func__, 3398 le16toh(hdr->version), le16toh(hdr->subversion), 3399 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3400 ptr += sizeof(*hdr); 3401 len -= sizeof(*hdr); 3402 } 3403 3404 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3405 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3406 ISSET(sc->chip, URTWN_CHIP_92EU)) 3407 urtwn_r88e_fw_reset(sc); 3408 else 3409 urtwn_fw_reset(sc); 3410 } 3411 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3412 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3413 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3414 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3415 R92C_SYS_FUNC_EN_CPUEN); 3416 } 3417 3418 /* download enabled */ 3419 urtwn_write_1(sc, R92C_MCUFWDL, 3420 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3421 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3422 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3423 3424 /* Reset the FWDL checksum. */ 3425 urtwn_write_1(sc, R92C_MCUFWDL, 3426 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3427 3428 DELAY(50); 3429 /* download firmware */ 3430 for (page = 0; len > 0; page++) { 3431 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3432 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3433 if (error != 0) { 3434 aprint_error_dev(sc->sc_dev, 3435 "could not load firmware page %d\n", page); 3436 goto fail; 3437 } 3438 ptr += mlen; 3439 len -= mlen; 3440 } 3441 3442 /* download disable */ 3443 urtwn_write_1(sc, R92C_MCUFWDL, 3444 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3445 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3446 3447 /* Wait for checksum report. */ 3448 for (ntries = 0; ntries < 1000; ntries++) { 3449 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3450 break; 3451 DELAY(5); 3452 } 3453 if (ntries == 1000) { 3454 aprint_error_dev(sc->sc_dev, 3455 "timeout waiting for checksum report\n"); 3456 error = ETIMEDOUT; 3457 goto fail; 3458 } 3459 3460 /* Wait for firmware readiness. */ 3461 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3462 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3463 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3464 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3465 ISSET(sc->chip, URTWN_CHIP_92EU)) 3466 urtwn_r88e_fw_reset(sc); 3467 for (ntries = 0; ntries < 1000; ntries++) { 3468 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3469 break; 3470 DELAY(5); 3471 } 3472 if (ntries == 1000) { 3473 aprint_error_dev(sc->sc_dev, 3474 "timeout waiting for firmware readiness\n"); 3475 error = ETIMEDOUT; 3476 goto fail; 3477 } 3478 fail: 3479 firmware_free(fw, fwlen); 3480 return error; 3481 } 3482 3483 static __inline int 3484 urtwn_dma_init(struct urtwn_softc *sc) 3485 { 3486 3487 return sc->sc_dma_init(sc); 3488 } 3489 3490 static int 3491 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3492 { 3493 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3494 uint32_t reg; 3495 int error; 3496 3497 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3498 3499 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3500 3501 /* Initialize LLT table. */ 3502 error = urtwn_llt_init(sc); 3503 if (error != 0) 3504 return error; 3505 3506 /* Get Tx queues to USB endpoints mapping. */ 3507 hashq = hasnq = haslq = 0; 3508 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3509 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3510 device_xname(sc->sc_dev), __func__, reg)); 3511 if (MS(reg, R92C_USB_EP_HQ) != 0) 3512 hashq = 1; 3513 if (MS(reg, R92C_USB_EP_NQ) != 0) 3514 hasnq = 1; 3515 if (MS(reg, R92C_USB_EP_LQ) != 0) 3516 haslq = 1; 3517 nqueues = hashq + hasnq + haslq; 3518 if (nqueues == 0) 3519 return EIO; 3520 /* Get the number of pages for each queue. */ 3521 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3522 /* The remaining pages are assigned to the high priority queue. */ 3523 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3524 3525 /* Set number of pages for normal priority queue. */ 3526 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3527 urtwn_write_4(sc, R92C_RQPN, 3528 /* Set number of pages for public queue. */ 3529 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3530 /* Set number of pages for high priority queue. */ 3531 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3532 /* Set number of pages for low priority queue. */ 3533 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3534 /* Load values. */ 3535 R92C_RQPN_LD); 3536 3537 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3538 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3539 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3540 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3541 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3542 3543 /* Set queue to USB pipe mapping. */ 3544 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3545 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3546 if (nqueues == 1) { 3547 if (hashq) { 3548 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3549 } else if (hasnq) { 3550 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3551 } else { 3552 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3553 } 3554 } else if (nqueues == 2) { 3555 /* All 2-endpoints configs have a high priority queue. */ 3556 if (!hashq) { 3557 return EIO; 3558 } 3559 if (hasnq) { 3560 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3561 } else { 3562 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3563 } 3564 } else { 3565 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3566 } 3567 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3568 3569 /* Set Tx/Rx transfer page boundary. */ 3570 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3571 3572 /* Set Tx/Rx transfer page size. */ 3573 urtwn_write_1(sc, R92C_PBP, 3574 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3575 return 0; 3576 } 3577 3578 static int 3579 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3580 { 3581 usb_interface_descriptor_t *id; 3582 uint32_t reg; 3583 int nqueues; 3584 int error; 3585 3586 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3587 3588 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3589 3590 /* Initialize LLT table. */ 3591 error = urtwn_llt_init(sc); 3592 if (error != 0) 3593 return error; 3594 3595 /* Get Tx queues to USB endpoints mapping. */ 3596 id = usbd_get_interface_descriptor(sc->sc_iface); 3597 nqueues = id->bNumEndpoints - 1; 3598 if (nqueues == 0) 3599 return EIO; 3600 3601 /* Set number of pages for normal priority queue. */ 3602 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3603 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3604 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3605 3606 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3607 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3608 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3609 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3610 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3611 3612 /* Set queue to USB pipe mapping. */ 3613 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3614 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3615 if (nqueues == 1) 3616 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3617 else if (nqueues == 2) 3618 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3619 else 3620 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3621 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3622 3623 /* Set Tx/Rx transfer page boundary. */ 3624 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3625 3626 /* Set Tx/Rx transfer page size. */ 3627 urtwn_write_1(sc, R92C_PBP, 3628 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3629 3630 return 0; 3631 } 3632 3633 static void 3634 urtwn_mac_init(struct urtwn_softc *sc) 3635 { 3636 size_t i; 3637 3638 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3639 3640 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3641 3642 /* Write MAC initialization values. */ 3643 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3644 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3645 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3646 rtl8188eu_mac[i].val); 3647 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3648 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3649 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3650 rtl8192eu_mac[i].val); 3651 } else { 3652 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3653 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3654 rtl8192cu_mac[i].val); 3655 } 3656 } 3657 3658 static void 3659 urtwn_bb_init(struct urtwn_softc *sc) 3660 { 3661 const struct urtwn_bb_prog *prog; 3662 uint32_t reg; 3663 uint8_t crystalcap; 3664 size_t i; 3665 3666 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3667 3668 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3669 3670 /* Enable BB and RF. */ 3671 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3672 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3673 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3674 R92C_SYS_FUNC_EN_DIO_RF); 3675 3676 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3677 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3678 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3679 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3680 } 3681 3682 urtwn_write_1(sc, R92C_RF_CTRL, 3683 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3684 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3685 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3686 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3687 3688 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3689 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3690 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3691 urtwn_write_1(sc, 0x15, 0xe9); 3692 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3693 } 3694 3695 /* Select BB programming based on board type. */ 3696 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3697 prog = &rtl8188eu_bb_prog; 3698 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3699 prog = &rtl8192eu_bb_prog; 3700 else if (!(sc->chip & URTWN_CHIP_92C)) { 3701 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3702 prog = &rtl8188ce_bb_prog; 3703 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3704 prog = &rtl8188ru_bb_prog; 3705 } else { 3706 prog = &rtl8188cu_bb_prog; 3707 } 3708 } else { 3709 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3710 prog = &rtl8192ce_bb_prog; 3711 } else { 3712 prog = &rtl8192cu_bb_prog; 3713 } 3714 } 3715 /* Write BB initialization values. */ 3716 for (i = 0; i < prog->count; i++) { 3717 /* additional delay depend on registers */ 3718 switch (prog->regs[i]) { 3719 case 0xfe: 3720 urtwn_delay_ms(sc, 50); 3721 break; 3722 case 0xfd: 3723 urtwn_delay_ms(sc, 5); 3724 break; 3725 case 0xfc: 3726 urtwn_delay_ms(sc, 1); 3727 break; 3728 case 0xfb: 3729 DELAY(50); 3730 break; 3731 case 0xfa: 3732 DELAY(5); 3733 break; 3734 case 0xf9: 3735 DELAY(1); 3736 break; 3737 } 3738 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3739 DELAY(1); 3740 } 3741 3742 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3743 /* 8192C 1T only configuration. */ 3744 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3745 reg = (reg & ~0x00000003) | 0x2; 3746 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3747 3748 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3749 reg = (reg & ~0x00300033) | 0x00200022; 3750 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3751 3752 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3753 reg = (reg & ~0xff000000) | (0x45 << 24); 3754 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3755 3756 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3757 reg = (reg & ~0x000000ff) | 0x23; 3758 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3759 3760 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3761 reg = (reg & ~0x00000030) | (1 << 4); 3762 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3763 3764 reg = urtwn_bb_read(sc, 0xe74); 3765 reg = (reg & ~0x0c000000) | (2 << 26); 3766 urtwn_bb_write(sc, 0xe74, reg); 3767 reg = urtwn_bb_read(sc, 0xe78); 3768 reg = (reg & ~0x0c000000) | (2 << 26); 3769 urtwn_bb_write(sc, 0xe78, reg); 3770 reg = urtwn_bb_read(sc, 0xe7c); 3771 reg = (reg & ~0x0c000000) | (2 << 26); 3772 urtwn_bb_write(sc, 0xe7c, reg); 3773 reg = urtwn_bb_read(sc, 0xe80); 3774 reg = (reg & ~0x0c000000) | (2 << 26); 3775 urtwn_bb_write(sc, 0xe80, reg); 3776 reg = urtwn_bb_read(sc, 0xe88); 3777 reg = (reg & ~0x0c000000) | (2 << 26); 3778 urtwn_bb_write(sc, 0xe88, reg); 3779 } 3780 3781 /* Write AGC values. */ 3782 for (i = 0; i < prog->agccount; i++) { 3783 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3784 DELAY(1); 3785 } 3786 3787 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3788 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3789 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3790 DELAY(1); 3791 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3792 DELAY(1); 3793 3794 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3795 urtwn_write_2(sc, R92C_AFE_CTRL3, urtwn_read_2(sc, 3796 R92C_AFE_CTRL3)); 3797 } 3798 3799 crystalcap = sc->r88e_rom[0xb9]; 3800 if (crystalcap == 0xff) 3801 crystalcap = 0x20; 3802 crystalcap &= 0x3f; 3803 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3804 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3805 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3806 crystalcap | crystalcap << 6)); 3807 } else { 3808 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3809 R92C_HSSI_PARAM2_CCK_HIPWR) { 3810 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3811 } 3812 } 3813 } 3814 3815 static void 3816 urtwn_rf_init(struct urtwn_softc *sc) 3817 { 3818 const struct urtwn_rf_prog *prog; 3819 uint32_t reg, mask, saved; 3820 size_t i, j, idx; 3821 3822 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3823 3824 /* Select RF programming based on board type. */ 3825 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3826 prog = rtl8188eu_rf_prog; 3827 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3828 prog = rtl8192eu_rf_prog; 3829 else if (!(sc->chip & URTWN_CHIP_92C)) { 3830 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3831 prog = rtl8188ce_rf_prog; 3832 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3833 prog = rtl8188ru_rf_prog; 3834 } else { 3835 prog = rtl8188cu_rf_prog; 3836 } 3837 } else { 3838 prog = rtl8192ce_rf_prog; 3839 } 3840 3841 for (i = 0; i < sc->nrxchains; i++) { 3842 /* Save RF_ENV control type. */ 3843 idx = i / 2; 3844 mask = 0xffffU << ((i % 2) * 16); 3845 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3846 3847 /* Set RF_ENV enable. */ 3848 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3849 reg |= 0x100000; 3850 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3851 DELAY(50); 3852 3853 /* Set RF_ENV output high. */ 3854 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3855 reg |= 0x10; 3856 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3857 DELAY(50); 3858 3859 /* Set address and data lengths of RF registers. */ 3860 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3861 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3862 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3863 DELAY(50); 3864 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3865 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3866 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3867 DELAY(50); 3868 3869 /* Write RF initialization values for this chain. */ 3870 for (j = 0; j < prog[i].count; j++) { 3871 if (prog[i].regs[j] >= 0xf9 && 3872 prog[i].regs[j] <= 0xfe) { 3873 /* 3874 * These are fake RF registers offsets that 3875 * indicate a delay is required. 3876 */ 3877 urtwn_delay_ms(sc, 50); 3878 continue; 3879 } 3880 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3881 DELAY(5); 3882 } 3883 3884 /* Restore RF_ENV control type. */ 3885 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3886 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3887 } 3888 3889 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3890 URTWN_CHIP_UMC_A_CUT) { 3891 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3892 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3893 } 3894 3895 /* Cache RF register CHNLBW. */ 3896 for (i = 0; i < 2; i++) { 3897 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3898 } 3899 } 3900 3901 static void 3902 urtwn_cam_init(struct urtwn_softc *sc) 3903 { 3904 uint32_t content, command; 3905 uint8_t idx; 3906 size_t i; 3907 3908 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3909 3910 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3911 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3912 return; 3913 3914 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3915 content = (idx & 3) 3916 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3917 | R92C_CAM_VALID; 3918 3919 command = R92C_CAMCMD_POLLING 3920 | R92C_CAMCMD_WRITE 3921 | R92C_CAM_CTL0(idx); 3922 3923 urtwn_write_4(sc, R92C_CAMWRITE, content); 3924 urtwn_write_4(sc, R92C_CAMCMD, command); 3925 } 3926 3927 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3928 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3929 if (i == 0) { 3930 content = (idx & 3) 3931 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3932 | R92C_CAM_VALID; 3933 } else { 3934 content = 0; 3935 } 3936 3937 command = R92C_CAMCMD_POLLING 3938 | R92C_CAMCMD_WRITE 3939 | R92C_CAM_CTL0(idx) 3940 | i; 3941 3942 urtwn_write_4(sc, R92C_CAMWRITE, content); 3943 urtwn_write_4(sc, R92C_CAMCMD, command); 3944 } 3945 } 3946 3947 /* Invalidate all CAM entries. */ 3948 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3949 } 3950 3951 static void 3952 urtwn_pa_bias_init(struct urtwn_softc *sc) 3953 { 3954 uint8_t reg; 3955 size_t i; 3956 3957 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3958 3959 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3960 3961 for (i = 0; i < sc->nrxchains; i++) { 3962 if (sc->pa_setting & (1U << i)) 3963 continue; 3964 3965 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3966 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3967 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3968 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3969 } 3970 if (!(sc->pa_setting & 0x10)) { 3971 reg = urtwn_read_1(sc, 0x16); 3972 reg = (reg & ~0xf0) | 0x90; 3973 urtwn_write_1(sc, 0x16, reg); 3974 } 3975 } 3976 3977 static void 3978 urtwn_rxfilter_init(struct urtwn_softc *sc) 3979 { 3980 3981 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3982 3983 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3984 3985 /* Initialize Rx filter. */ 3986 /* TODO: use better filter for monitor mode. */ 3987 urtwn_write_4(sc, R92C_RCR, 3988 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3989 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3990 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3991 /* Accept all multicast frames. */ 3992 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3993 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3994 /* Accept all management frames. */ 3995 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3996 /* Reject all control frames. */ 3997 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3998 /* Accept all data frames. */ 3999 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4000 } 4001 4002 static void 4003 urtwn_edca_init(struct urtwn_softc *sc) 4004 { 4005 4006 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4007 4008 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4009 4010 /* set spec SIFS (used in NAV) */ 4011 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4012 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4013 4014 /* set SIFS CCK/OFDM */ 4015 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4016 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4017 4018 /* TXOP */ 4019 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4020 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4021 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4022 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4023 } 4024 4025 static void 4026 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4027 uint16_t power[URTWN_RIDX_COUNT]) 4028 { 4029 uint32_t reg; 4030 4031 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4032 __func__, chain)); 4033 4034 /* Write per-CCK rate Tx power. */ 4035 if (chain == 0) { 4036 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4037 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4038 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4039 4040 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4041 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4042 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4043 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4044 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4045 } else { 4046 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4047 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4048 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4049 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4050 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4051 4052 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4053 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4054 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4055 } 4056 /* Write per-OFDM rate Tx power. */ 4057 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4058 SM(R92C_TXAGC_RATE06, power[ 4]) | 4059 SM(R92C_TXAGC_RATE09, power[ 5]) | 4060 SM(R92C_TXAGC_RATE12, power[ 6]) | 4061 SM(R92C_TXAGC_RATE18, power[ 7])); 4062 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4063 SM(R92C_TXAGC_RATE24, power[ 8]) | 4064 SM(R92C_TXAGC_RATE36, power[ 9]) | 4065 SM(R92C_TXAGC_RATE48, power[10]) | 4066 SM(R92C_TXAGC_RATE54, power[11])); 4067 /* Write per-MCS Tx power. */ 4068 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4069 SM(R92C_TXAGC_MCS00, power[12]) | 4070 SM(R92C_TXAGC_MCS01, power[13]) | 4071 SM(R92C_TXAGC_MCS02, power[14]) | 4072 SM(R92C_TXAGC_MCS03, power[15])); 4073 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4074 SM(R92C_TXAGC_MCS04, power[16]) | 4075 SM(R92C_TXAGC_MCS05, power[17]) | 4076 SM(R92C_TXAGC_MCS06, power[18]) | 4077 SM(R92C_TXAGC_MCS07, power[19])); 4078 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4079 SM(R92C_TXAGC_MCS08, power[20]) | 4080 SM(R92C_TXAGC_MCS09, power[21]) | 4081 SM(R92C_TXAGC_MCS10, power[22]) | 4082 SM(R92C_TXAGC_MCS11, power[23])); 4083 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4084 SM(R92C_TXAGC_MCS12, power[24]) | 4085 SM(R92C_TXAGC_MCS13, power[25]) | 4086 SM(R92C_TXAGC_MCS14, power[26]) | 4087 SM(R92C_TXAGC_MCS15, power[27])); 4088 } 4089 4090 static void 4091 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4092 uint16_t power[URTWN_RIDX_COUNT]) 4093 { 4094 struct r92c_rom *rom = &sc->rom; 4095 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4096 const struct urtwn_txpwr *base; 4097 int ridx, group; 4098 4099 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4100 device_xname(sc->sc_dev), __func__, chain, chan)); 4101 4102 /* Determine channel group. */ 4103 if (chan <= 3) { 4104 group = 0; 4105 } else if (chan <= 9) { 4106 group = 1; 4107 } else { 4108 group = 2; 4109 } 4110 4111 /* Get original Tx power based on board type and RF chain. */ 4112 if (!(sc->chip & URTWN_CHIP_92C)) { 4113 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4114 base = &rtl8188ru_txagc[chain]; 4115 } else { 4116 base = &rtl8192cu_txagc[chain]; 4117 } 4118 } else { 4119 base = &rtl8192cu_txagc[chain]; 4120 } 4121 4122 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4123 if (sc->regulatory == 0) { 4124 for (ridx = 0; ridx <= 3; ridx++) { 4125 power[ridx] = base->pwr[0][ridx]; 4126 } 4127 } 4128 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4129 if (sc->regulatory == 3) { 4130 power[ridx] = base->pwr[0][ridx]; 4131 /* Apply vendor limits. */ 4132 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4133 maxpow = rom->ht40_max_pwr[group]; 4134 } else { 4135 maxpow = rom->ht20_max_pwr[group]; 4136 } 4137 maxpow = (maxpow >> (chain * 4)) & 0xf; 4138 if (power[ridx] > maxpow) { 4139 power[ridx] = maxpow; 4140 } 4141 } else if (sc->regulatory == 1) { 4142 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4143 power[ridx] = base->pwr[group][ridx]; 4144 } 4145 } else if (sc->regulatory != 2) { 4146 power[ridx] = base->pwr[0][ridx]; 4147 } 4148 } 4149 4150 /* Compute per-CCK rate Tx power. */ 4151 cckpow = rom->cck_tx_pwr[chain][group]; 4152 for (ridx = 0; ridx <= 3; ridx++) { 4153 power[ridx] += cckpow; 4154 if (power[ridx] > R92C_MAX_TX_PWR) { 4155 power[ridx] = R92C_MAX_TX_PWR; 4156 } 4157 } 4158 4159 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4160 if (sc->ntxchains > 1) { 4161 /* Apply reduction for 2 spatial streams. */ 4162 diff = rom->ht40_2s_tx_pwr_diff[group]; 4163 diff = (diff >> (chain * 4)) & 0xf; 4164 htpow = (htpow > diff) ? htpow - diff : 0; 4165 } 4166 4167 /* Compute per-OFDM rate Tx power. */ 4168 diff = rom->ofdm_tx_pwr_diff[group]; 4169 diff = (diff >> (chain * 4)) & 0xf; 4170 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4171 for (ridx = 4; ridx <= 11; ridx++) { 4172 power[ridx] += ofdmpow; 4173 if (power[ridx] > R92C_MAX_TX_PWR) { 4174 power[ridx] = R92C_MAX_TX_PWR; 4175 } 4176 } 4177 4178 /* Compute per-MCS Tx power. */ 4179 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4180 diff = rom->ht20_tx_pwr_diff[group]; 4181 diff = (diff >> (chain * 4)) & 0xf; 4182 htpow += diff; /* HT40->HT20 correction. */ 4183 } 4184 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4185 power[ridx] += htpow; 4186 if (power[ridx] > R92C_MAX_TX_PWR) { 4187 power[ridx] = R92C_MAX_TX_PWR; 4188 } 4189 } 4190 #ifdef URTWN_DEBUG 4191 if (urtwn_debug & DBG_RF) { 4192 /* Dump per-rate Tx power values. */ 4193 printf("%s: %s: Tx power for chain %zd:\n", 4194 device_xname(sc->sc_dev), __func__, chain); 4195 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4196 printf("%s: %s: Rate %d = %u\n", 4197 device_xname(sc->sc_dev), __func__, ridx, 4198 power[ridx]); 4199 } 4200 } 4201 #endif 4202 } 4203 4204 void 4205 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4206 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4207 { 4208 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4209 const struct urtwn_r88e_txpwr *base; 4210 int ridx, group; 4211 4212 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4213 device_xname(sc->sc_dev), __func__, chain, chan)); 4214 4215 /* Determine channel group. */ 4216 if (chan <= 2) 4217 group = 0; 4218 else if (chan <= 5) 4219 group = 1; 4220 else if (chan <= 8) 4221 group = 2; 4222 else if (chan <= 11) 4223 group = 3; 4224 else if (chan <= 13) 4225 group = 4; 4226 else 4227 group = 5; 4228 4229 /* Get original Tx power based on board type and RF chain. */ 4230 base = &rtl8188eu_txagc[chain]; 4231 4232 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4233 if (sc->regulatory == 0) { 4234 for (ridx = 0; ridx <= 3; ridx++) 4235 power[ridx] = base->pwr[0][ridx]; 4236 } 4237 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4238 if (sc->regulatory == 3) 4239 power[ridx] = base->pwr[0][ridx]; 4240 else if (sc->regulatory == 1) { 4241 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4242 power[ridx] = base->pwr[group][ridx]; 4243 } else if (sc->regulatory != 2) 4244 power[ridx] = base->pwr[0][ridx]; 4245 } 4246 4247 /* Compute per-CCK rate Tx power. */ 4248 cckpow = sc->cck_tx_pwr[group]; 4249 for (ridx = 0; ridx <= 3; ridx++) { 4250 power[ridx] += cckpow; 4251 if (power[ridx] > R92C_MAX_TX_PWR) 4252 power[ridx] = R92C_MAX_TX_PWR; 4253 } 4254 4255 htpow = sc->ht40_tx_pwr[group]; 4256 4257 /* Compute per-OFDM rate Tx power. */ 4258 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4259 for (ridx = 4; ridx <= 11; ridx++) { 4260 power[ridx] += ofdmpow; 4261 if (power[ridx] > R92C_MAX_TX_PWR) 4262 power[ridx] = R92C_MAX_TX_PWR; 4263 } 4264 4265 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4266 for (ridx = 12; ridx <= 27; ridx++) { 4267 power[ridx] += bw20pow; 4268 if (power[ridx] > R92C_MAX_TX_PWR) 4269 power[ridx] = R92C_MAX_TX_PWR; 4270 } 4271 } 4272 4273 static void 4274 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4275 { 4276 uint16_t power[URTWN_RIDX_COUNT]; 4277 size_t i; 4278 4279 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4280 4281 for (i = 0; i < sc->ntxchains; i++) { 4282 /* Compute per-rate Tx power values. */ 4283 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4284 ISSET(sc->chip, URTWN_CHIP_92EU)) 4285 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4286 else 4287 urtwn_get_txpower(sc, i, chan, ht40m, power); 4288 /* Write per-rate Tx power values to hardware. */ 4289 urtwn_write_txpower(sc, i, power); 4290 } 4291 } 4292 4293 static void 4294 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4295 { 4296 struct ieee80211com *ic = &sc->sc_ic; 4297 u_int chan; 4298 size_t i; 4299 4300 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4301 4302 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4303 __func__, chan)); 4304 4305 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4306 4307 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4308 chan += 2; 4309 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4310 chan -= 2; 4311 } 4312 4313 /* Set Tx power for this new channel. */ 4314 urtwn_set_txpower(sc, chan, ht40m); 4315 4316 for (i = 0; i < sc->nrxchains; i++) { 4317 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4318 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4319 } 4320 4321 if (ht40m) { 4322 /* Is secondary channel below or above primary? */ 4323 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4324 uint32_t reg; 4325 4326 urtwn_write_1(sc, R92C_BWOPMODE, 4327 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4328 4329 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4330 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4331 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4332 4333 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4334 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4335 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4336 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4337 4338 /* Set CCK side band. */ 4339 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4340 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4341 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4342 4343 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4344 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4345 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4346 4347 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4348 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4349 ~R92C_FPGA0_ANAPARAM2_CBW20); 4350 4351 reg = urtwn_bb_read(sc, 0x818); 4352 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4353 urtwn_bb_write(sc, 0x818, reg); 4354 4355 /* Select 40MHz bandwidth. */ 4356 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4357 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4358 } else { 4359 urtwn_write_1(sc, R92C_BWOPMODE, 4360 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4361 4362 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4363 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4364 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4365 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4366 4367 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4368 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4369 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4370 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4371 R92C_FPGA0_ANAPARAM2_CBW20); 4372 } 4373 4374 /* Select 20MHz bandwidth. */ 4375 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4376 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4377 (ISSET(sc->chip, URTWN_CHIP_88E) || 4378 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4379 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4380 } 4381 } 4382 4383 static void 4384 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4385 { 4386 4387 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4388 __func__, inited)); 4389 4390 uint32_t addaBackup[16], iqkBackup[4], piMode; 4391 4392 #ifdef notyet 4393 uint32_t odfm0_agccore_regs[3]; 4394 uint32_t ant_regs[3]; 4395 uint32_t rf_regs[8]; 4396 #endif 4397 uint32_t reg0, reg1, reg2; 4398 int i, attempt; 4399 4400 #ifdef notyet 4401 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4402 R92E_STBC_SETTING + 2)); 4403 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4404 /* Save AGCCORE regs. */ 4405 for (i = 0; i < sc->nrxchains; i++) { 4406 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4407 R92C_OFDM0_AGCCORE1(i)); 4408 } 4409 #endif 4410 /* Save BB regs. */ 4411 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4412 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4413 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4414 4415 /* Save adda regs to be restored when finished. */ 4416 for (i = 0; i < __arraycount(addaReg); i++) 4417 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4418 /* Save mac regs. */ 4419 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4420 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4421 iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF); 4422 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4423 4424 #ifdef notyet 4425 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4426 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4427 4428 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4429 for (i = 0; i < sc->nrxchains; i++) 4430 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4431 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4432 #endif 4433 4434 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4435 R92C_HSSI_PARAM1_PI); 4436 if (piMode == 0) { 4437 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4438 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4439 R92C_HSSI_PARAM1_PI); 4440 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4441 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4442 R92C_HSSI_PARAM1_PI); 4443 } 4444 4445 attempt = 1; 4446 4447 next_attempt: 4448 4449 /* Set mac regs for calibration. */ 4450 for (i = 0; i < __arraycount(addaReg); i++) { 4451 urtwn_bb_write(sc, addaReg[i], 4452 addaReg[__arraycount(addaReg) - 1]); 4453 } 4454 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4455 R92C_CCK0_AFESETTING)); 4456 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4457 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4458 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4459 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4460 4461 if (sc->ntxchains > 1) 4462 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4463 4464 urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL); 4465 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4466 ~R92C_BCN_CTRL_EN_BCN)); 4467 urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8)); 4468 4469 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4470 ~R92C_GPIO_MUXCFG_ENBT)); 4471 4472 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4473 4474 if (sc->ntxchains > 1) 4475 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4476 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4477 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4478 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4479 4480 /* Restore BB regs. */ 4481 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4482 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4483 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4484 4485 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4486 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4487 if (sc->nrxchains > 1) 4488 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4489 4490 if (attempt-- > 0) 4491 goto next_attempt; 4492 4493 /* Restore mode. */ 4494 if (piMode == 0) { 4495 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4496 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4497 ~R92C_HSSI_PARAM1_PI); 4498 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4499 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4500 ~R92C_HSSI_PARAM1_PI); 4501 } 4502 4503 #ifdef notyet 4504 for (i = 0; i < sc->nrxchains; i++) { 4505 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4506 odfm0_agccore_regs[i]); 4507 } 4508 #endif 4509 4510 /* Restore adda regs. */ 4511 for (i = 0; i < __arraycount(addaReg); i++) 4512 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4513 /* Restore mac regs. */ 4514 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4515 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4516 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4517 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4518 4519 #ifdef notyet 4520 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4521 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4522 4523 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4524 for (i = 0; i < sc->nrxchains; i++) 4525 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4526 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4527 #endif 4528 } 4529 4530 static void 4531 urtwn_lc_calib(struct urtwn_softc *sc) 4532 { 4533 uint32_t rf_ac[2]; 4534 uint8_t txmode; 4535 size_t i; 4536 4537 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4538 4539 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4540 4541 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4542 if ((txmode & 0x70) != 0) { 4543 /* Disable all continuous Tx. */ 4544 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4545 4546 /* Set RF mode to standby mode. */ 4547 for (i = 0; i < sc->nrxchains; i++) { 4548 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4549 urtwn_rf_write(sc, i, R92C_RF_AC, 4550 RW(rf_ac[i], R92C_RF_AC_MODE, 4551 R92C_RF_AC_MODE_STANDBY)); 4552 } 4553 } else { 4554 /* Block all Tx queues. */ 4555 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4556 } 4557 /* Start calibration. */ 4558 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4559 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4560 4561 /* Give calibration the time to complete. */ 4562 urtwn_delay_ms(sc, 100); 4563 4564 /* Restore configuration. */ 4565 if ((txmode & 0x70) != 0) { 4566 /* Restore Tx mode. */ 4567 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4568 /* Restore RF mode. */ 4569 for (i = 0; i < sc->nrxchains; i++) { 4570 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4571 } 4572 } else { 4573 /* Unblock all Tx queues. */ 4574 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4575 } 4576 } 4577 4578 static void 4579 urtwn_temp_calib(struct urtwn_softc *sc) 4580 { 4581 int temp, t_meter_reg; 4582 4583 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4584 4585 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4586 4587 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4588 t_meter_reg = R92C_RF_T_METER; 4589 else 4590 t_meter_reg = R92E_RF_T_METER; 4591 4592 if (sc->thcal_state == 0) { 4593 /* Start measuring temperature. */ 4594 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4595 device_xname(sc->sc_dev), __func__)); 4596 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4597 sc->thcal_state = 1; 4598 return; 4599 } 4600 sc->thcal_state = 0; 4601 4602 /* Read measured temperature. */ 4603 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4604 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4605 __func__, temp)); 4606 if (temp == 0) /* Read failed, skip. */ 4607 return; 4608 4609 /* 4610 * Redo LC calibration if temperature changed significantly since 4611 * last calibration. 4612 */ 4613 if (sc->thcal_lctemp == 0) { 4614 /* First LC calibration is performed in urtwn_init(). */ 4615 sc->thcal_lctemp = temp; 4616 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4617 DPRINTFN(DBG_RF, 4618 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4619 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4620 temp)); 4621 urtwn_lc_calib(sc); 4622 /* Record temperature of last LC calibration. */ 4623 sc->thcal_lctemp = temp; 4624 } 4625 } 4626 4627 static int 4628 urtwn_init(struct ifnet *ifp) 4629 { 4630 struct urtwn_softc *sc = ifp->if_softc; 4631 struct ieee80211com *ic = &sc->sc_ic; 4632 struct urtwn_rx_data *data; 4633 uint32_t reg; 4634 size_t i; 4635 int error; 4636 4637 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4638 4639 urtwn_stop(ifp, 0); 4640 4641 mutex_enter(&sc->sc_write_mtx); 4642 4643 mutex_enter(&sc->sc_task_mtx); 4644 /* Init host async commands ring. */ 4645 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4646 mutex_exit(&sc->sc_task_mtx); 4647 4648 mutex_enter(&sc->sc_fwcmd_mtx); 4649 /* Init firmware commands ring. */ 4650 sc->fwcur = 0; 4651 mutex_exit(&sc->sc_fwcmd_mtx); 4652 4653 /* Allocate Tx/Rx buffers. */ 4654 error = urtwn_alloc_rx_list(sc); 4655 if (error != 0) { 4656 aprint_error_dev(sc->sc_dev, 4657 "could not allocate Rx buffers\n"); 4658 goto fail; 4659 } 4660 error = urtwn_alloc_tx_list(sc); 4661 if (error != 0) { 4662 aprint_error_dev(sc->sc_dev, 4663 "could not allocate Tx buffers\n"); 4664 goto fail; 4665 } 4666 4667 /* Power on adapter. */ 4668 error = urtwn_power_on(sc); 4669 if (error != 0) 4670 goto fail; 4671 4672 /* Initialize DMA. */ 4673 error = urtwn_dma_init(sc); 4674 if (error != 0) 4675 goto fail; 4676 4677 /* Set info size in Rx descriptors (in 64-bit words). */ 4678 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4679 4680 /* Init interrupts. */ 4681 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4682 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4683 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4684 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4685 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4686 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4687 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4688 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4689 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4690 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4691 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4692 } 4693 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4694 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4695 } else { 4696 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4697 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4698 } 4699 4700 /* Set MAC address. */ 4701 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4702 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4703 4704 /* Set initial network type. */ 4705 reg = urtwn_read_4(sc, R92C_CR); 4706 switch (ic->ic_opmode) { 4707 case IEEE80211_M_STA: 4708 default: 4709 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4710 break; 4711 4712 case IEEE80211_M_IBSS: 4713 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4714 break; 4715 } 4716 urtwn_write_4(sc, R92C_CR, reg); 4717 4718 /* Set response rate */ 4719 reg = urtwn_read_4(sc, R92C_RRSR); 4720 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4721 urtwn_write_4(sc, R92C_RRSR, reg); 4722 4723 /* SIFS (used in NAV) */ 4724 urtwn_write_2(sc, R92C_SPEC_SIFS, 4725 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4726 4727 /* Set short/long retry limits. */ 4728 urtwn_write_2(sc, R92C_RL, 4729 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4730 4731 /* Initialize EDCA parameters. */ 4732 urtwn_edca_init(sc); 4733 4734 /* Setup rate fallback. */ 4735 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4736 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4737 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4738 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4739 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4740 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4741 } 4742 4743 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4744 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4745 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4746 /* Set ACK timeout. */ 4747 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4748 4749 /* Setup USB aggregation. */ 4750 /* Tx */ 4751 reg = urtwn_read_4(sc, R92C_TDECTRL); 4752 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4753 urtwn_write_4(sc, R92C_TDECTRL, reg); 4754 /* Rx */ 4755 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4756 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4757 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4758 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4759 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4760 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4761 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4762 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4763 ISSET(sc->chip, URTWN_CHIP_92EU)) 4764 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4765 else 4766 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4767 4768 /* Initialize beacon parameters. */ 4769 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4770 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4771 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4772 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4773 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4774 4775 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4776 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4777 /* Setup AMPDU aggregation. */ 4778 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4779 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4780 urtwn_write_2(sc, 0x4ca, 0x0708); 4781 4782 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4783 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4784 } 4785 4786 /* Load 8051 microcode. */ 4787 error = urtwn_load_firmware(sc); 4788 if (error != 0) 4789 goto fail; 4790 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4791 4792 /* Initialize MAC/BB/RF blocks. */ 4793 /* 4794 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4795 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4796 * XXX: This setting should be removed from rtl8192cu_mac[]. 4797 */ 4798 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4799 urtwn_rxfilter_init(sc); // reset R92C_RCR 4800 urtwn_bb_init(sc); 4801 urtwn_rf_init(sc); 4802 4803 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4804 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4805 urtwn_write_2(sc, R92C_CR, 4806 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4807 R92C_CR_MACRXEN); 4808 } 4809 4810 /* Turn CCK and OFDM blocks on. */ 4811 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4812 reg |= R92C_RFMOD_CCK_EN; 4813 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4814 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4815 reg |= R92C_RFMOD_OFDM_EN; 4816 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4817 4818 /* Clear per-station keys table. */ 4819 urtwn_cam_init(sc); 4820 4821 /* Enable hardware sequence numbering. */ 4822 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4823 4824 /* Perform LO and IQ calibrations. */ 4825 urtwn_iq_calib(sc, sc->iqk_inited); 4826 sc->iqk_inited = true; 4827 4828 /* Perform LC calibration. */ 4829 urtwn_lc_calib(sc); 4830 4831 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4832 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4833 /* Fix USB interference issue. */ 4834 urtwn_write_1(sc, 0xfe40, 0xe0); 4835 urtwn_write_1(sc, 0xfe41, 0x8d); 4836 urtwn_write_1(sc, 0xfe42, 0x80); 4837 urtwn_write_4(sc, 0x20c, 0xfd0320); 4838 4839 urtwn_pa_bias_init(sc); 4840 } 4841 4842 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4843 !(sc->chip & URTWN_CHIP_92EU)) { 4844 /* 1T1R */ 4845 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4846 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4847 } 4848 4849 /* Initialize GPIO setting. */ 4850 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4851 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4852 4853 /* Fix for lower temperature. */ 4854 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4855 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4856 urtwn_write_1(sc, 0x15, 0xe9); 4857 4858 /* Set default channel. */ 4859 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4860 4861 /* Queue Rx xfers. */ 4862 for (size_t j = 0; j < sc->rx_npipe; j++) { 4863 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4864 data = &sc->rx_data[j][i]; 4865 usbd_setup_xfer(data->xfer, data, data->buf, 4866 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4867 urtwn_rxeof); 4868 error = usbd_transfer(data->xfer); 4869 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4870 error != USBD_IN_PROGRESS)) 4871 goto fail; 4872 } 4873 } 4874 4875 /* We're ready to go. */ 4876 ifp->if_flags &= ~IFF_OACTIVE; 4877 ifp->if_flags |= IFF_RUNNING; 4878 sc->sc_running = true; 4879 4880 mutex_exit(&sc->sc_write_mtx); 4881 4882 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4883 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4884 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4885 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4886 urtwn_wait_async(sc); 4887 4888 return 0; 4889 4890 fail: 4891 mutex_exit(&sc->sc_write_mtx); 4892 4893 urtwn_stop(ifp, 1); 4894 return error; 4895 } 4896 4897 static void 4898 urtwn_stop(struct ifnet *ifp, int disable) 4899 { 4900 struct urtwn_softc *sc = ifp->if_softc; 4901 struct ieee80211com *ic = &sc->sc_ic; 4902 size_t i; 4903 int s; 4904 4905 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4906 4907 s = splusb(); 4908 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4909 urtwn_wait_async(sc); 4910 splx(s); 4911 4912 sc->tx_timer = 0; 4913 ifp->if_timer = 0; 4914 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4915 4916 callout_stop(&sc->sc_scan_to); 4917 callout_stop(&sc->sc_calib_to); 4918 4919 /* Abort Tx. */ 4920 for (i = 0; i < sc->tx_npipe; i++) { 4921 if (sc->tx_pipe[i] != NULL) 4922 usbd_abort_pipe(sc->tx_pipe[i]); 4923 } 4924 4925 /* Stop Rx pipe. */ 4926 for (i = 0; i < sc->rx_npipe; i++) { 4927 if (sc->rx_pipe[i] != NULL) 4928 usbd_abort_pipe(sc->rx_pipe[i]); 4929 } 4930 4931 /* Free Tx/Rx buffers. */ 4932 urtwn_free_tx_list(sc); 4933 urtwn_free_rx_list(sc); 4934 4935 sc->sc_running = false; 4936 if (disable) 4937 urtwn_chip_stop(sc); 4938 } 4939 4940 static int 4941 urtwn_reset(struct ifnet *ifp) 4942 { 4943 struct urtwn_softc *sc = ifp->if_softc; 4944 struct ieee80211com *ic = &sc->sc_ic; 4945 4946 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4947 return ENETRESET; 4948 4949 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4950 4951 return 0; 4952 } 4953 4954 static void 4955 urtwn_chip_stop(struct urtwn_softc *sc) 4956 { 4957 uint32_t reg; 4958 bool disabled = true; 4959 4960 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4961 4962 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4963 return; 4964 4965 mutex_enter(&sc->sc_write_mtx); 4966 4967 /* 4968 * RF Off Sequence 4969 */ 4970 /* Pause MAC TX queue */ 4971 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4972 4973 /* Disable RF */ 4974 urtwn_rf_write(sc, 0, 0, 0); 4975 4976 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4977 4978 /* Reset BB state machine */ 4979 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4980 R92C_SYS_FUNC_EN_USBD | 4981 R92C_SYS_FUNC_EN_USBA | 4982 R92C_SYS_FUNC_EN_BB_GLB_RST); 4983 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4984 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4985 4986 /* 4987 * Reset digital sequence 4988 */ 4989 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4990 /* Reset MCU ready status */ 4991 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4992 /* If firmware in ram code, do reset */ 4993 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4994 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4995 ISSET(sc->chip, URTWN_CHIP_92EU)) 4996 urtwn_r88e_fw_reset(sc); 4997 else 4998 urtwn_fw_reset(sc); 4999 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5000 } 5001 } 5002 5003 /* Reset MAC and Enable 8051 */ 5004 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5005 5006 /* Reset MCU ready status */ 5007 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5008 5009 if (disabled) { 5010 /* Disable MAC clock */ 5011 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5012 /* Disable AFE PLL */ 5013 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5014 /* Gated AFE DIG_CLOCK */ 5015 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5016 /* Isolated digital to PON */ 5017 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5018 } 5019 5020 /* 5021 * Pull GPIO PIN to balance level and LED control 5022 */ 5023 /* 1. Disable GPIO[7:0] */ 5024 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5025 5026 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5027 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5028 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5029 5030 /* Disable GPIO[10:8] */ 5031 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5032 5033 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5034 reg |= (((reg & 0x000f) << 4) | 0x0780); 5035 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5036 5037 /* Disable LED0 & 1 */ 5038 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5039 5040 /* 5041 * Reset digital sequence 5042 */ 5043 if (disabled) { 5044 /* Disable ELDR clock */ 5045 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5046 /* Isolated ELDR to PON */ 5047 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5048 } 5049 5050 /* 5051 * Disable analog sequence 5052 */ 5053 if (disabled) { 5054 /* Disable A15 power */ 5055 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5056 /* Disable digital core power */ 5057 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5058 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5059 ~R92C_LDOV12D_CTRL_LDV12_EN); 5060 } 5061 5062 /* Enter PFM mode */ 5063 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5064 5065 /* Set USB suspend */ 5066 urtwn_write_2(sc, R92C_APS_FSMCO, 5067 R92C_APS_FSMCO_APDM_HOST | 5068 R92C_APS_FSMCO_AFSM_HSUS | 5069 R92C_APS_FSMCO_PFM_ALDN); 5070 5071 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5072 5073 mutex_exit(&sc->sc_write_mtx); 5074 } 5075 5076 static void 5077 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5078 { 5079 if (sc->sc_running == false) 5080 DELAY(ms * 1000); 5081 else 5082 usbd_delay_ms(sc->sc_udev, ms); 5083 } 5084 5085 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 5086 5087 #ifdef _MODULE 5088 #include "ioconf.c" 5089 #endif 5090 5091 static int 5092 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5093 { 5094 int error = 0; 5095 5096 switch (cmd) { 5097 case MODULE_CMD_INIT: 5098 #ifdef _MODULE 5099 error = config_init_component(cfdriver_ioconf_urtwn, 5100 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5101 #endif 5102 return error; 5103 case MODULE_CMD_FINI: 5104 #ifdef _MODULE 5105 error = config_fini_component(cfdriver_ioconf_urtwn, 5106 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5107 #endif 5108 return error; 5109 default: 5110 return ENOTTY; 5111 } 5112 } 5113
Indexes created Thu Oct 02 14:10:14 GMT 2025