if_urtwn.c revision 1.47
1 /* $NetBSD: if_urtwn.c,v 1.47 2016/10/12 02:50:44 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /*- 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.47 2016/10/12 02:50:44 nat Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_inet.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/module.h> 40 #include <sys/conf.h> 41 #include <sys/device.h> 42 43 #include <sys/bus.h> 44 #include <machine/endian.h> 45 #include <sys/intr.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 61 #include <net80211/ieee80211_netbsd.h> 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_radiotap.h> 64 65 #include <dev/firmload.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdevs.h> 72 73 #include <dev/usb/if_urtwnreg.h> 74 #include <dev/usb/if_urtwnvar.h> 75 #include <dev/usb/if_urtwn_data.h> 76 77 /* 78 * The sc_write_mtx locking is to prevent sequences of writes from 79 * being intermingled with each other. I don't know if this is really 80 * needed. I have added it just to be on the safe side. 81 */ 82 83 #ifdef URTWN_DEBUG 84 #define DBG_INIT __BIT(0) 85 #define DBG_FN __BIT(1) 86 #define DBG_TX __BIT(2) 87 #define DBG_RX __BIT(3) 88 #define DBG_STM __BIT(4) 89 #define DBG_RF __BIT(5) 90 #define DBG_REG __BIT(6) 91 #define DBG_ALL 0xffffffffU 92 u_int urtwn_debug = 0; 93 #define DPRINTFN(n, s) \ 94 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 95 #else 96 #define DPRINTFN(n, s) 97 #endif 98 99 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 100 #define URTWN_RTL8188E_DEV(v,p) \ 101 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 102 static const struct urtwn_dev { 103 struct usb_devno dev; 104 uint32_t flags; 105 #define FLAG_RTL8188E __BIT(0) 106 } urtwn_devs[] = { 107 URTWN_DEV(ABOCOM, RTL8188CU_1), 108 URTWN_DEV(ABOCOM, RTL8188CU_2), 109 URTWN_DEV(ABOCOM, RTL8192CU), 110 URTWN_DEV(ASUSTEK, RTL8192CU), 111 URTWN_DEV(ASUSTEK, RTL8192CU_3), 112 URTWN_DEV(ASUSTEK, USBN10NANO), 113 URTWN_DEV(ASUSTEK, RTL8192CU_3), 114 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 115 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 116 URTWN_DEV(AZUREWAVE, RTL8188CU), 117 URTWN_DEV(BELKIN, F7D2102), 118 URTWN_DEV(BELKIN, RTL8188CU), 119 URTWN_DEV(BELKIN, RTL8188CUS), 120 URTWN_DEV(BELKIN, RTL8192CU), 121 URTWN_DEV(BELKIN, RTL8192CU_1), 122 URTWN_DEV(BELKIN, RTL8192CU_2), 123 URTWN_DEV(CHICONY, RTL8188CUS_1), 124 URTWN_DEV(CHICONY, RTL8188CUS_2), 125 URTWN_DEV(CHICONY, RTL8188CUS_3), 126 URTWN_DEV(CHICONY, RTL8188CUS_4), 127 URTWN_DEV(CHICONY, RTL8188CUS_5), 128 URTWN_DEV(CHICONY, RTL8188CUS_6), 129 URTWN_DEV(COMPARE, RTL8192CU), 130 URTWN_DEV(COREGA, RTL8192CU), 131 URTWN_DEV(DLINK, DWA131B), 132 URTWN_DEV(DLINK, RTL8188CU), 133 URTWN_DEV(DLINK, RTL8192CU_1), 134 URTWN_DEV(DLINK, RTL8192CU_2), 135 URTWN_DEV(DLINK, RTL8192CU_3), 136 URTWN_DEV(DLINK, RTL8192CU_4), 137 URTWN_DEV(EDIMAX, RTL8188CU), 138 URTWN_DEV(EDIMAX, RTL8192CU), 139 URTWN_DEV(FEIXUN, RTL8188CU), 140 URTWN_DEV(FEIXUN, RTL8192CU), 141 URTWN_DEV(GUILLEMOT, HWNUP150), 142 URTWN_DEV(GUILLEMOT, RTL8192CU), 143 URTWN_DEV(HAWKING, RTL8192CU), 144 URTWN_DEV(HAWKING, RTL8192CU_2), 145 URTWN_DEV(HP3, RTL8188CU), 146 URTWN_DEV(IODATA, WNG150UM), 147 URTWN_DEV(IODATA, RTL8192CU), 148 URTWN_DEV(NETGEAR, WNA1000M), 149 URTWN_DEV(NETGEAR, RTL8192CU), 150 URTWN_DEV(NETGEAR4, RTL8188CU), 151 URTWN_DEV(NOVATECH, RTL8188CU), 152 URTWN_DEV(PLANEX2, RTL8188CU_1), 153 URTWN_DEV(PLANEX2, RTL8188CU_2), 154 URTWN_DEV(PLANEX2, RTL8192CU), 155 URTWN_DEV(PLANEX2, RTL8188CU_3), 156 URTWN_DEV(PLANEX2, RTL8188CU_4), 157 URTWN_DEV(PLANEX2, RTL8188CUS), 158 URTWN_DEV(REALTEK, RTL8188CE_0), 159 URTWN_DEV(REALTEK, RTL8188CE_1), 160 URTWN_DEV(REALTEK, RTL8188CTV), 161 URTWN_DEV(REALTEK, RTL8188CU_0), 162 URTWN_DEV(REALTEK, RTL8188CU_1), 163 URTWN_DEV(REALTEK, RTL8188CU_2), 164 URTWN_DEV(REALTEK, RTL8188CU_3), 165 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 166 URTWN_DEV(REALTEK, RTL8188CUS), 167 URTWN_DEV(REALTEK, RTL8188RU), 168 URTWN_DEV(REALTEK, RTL8188RU_2), 169 URTWN_DEV(REALTEK, RTL8188RU_3), 170 URTWN_DEV(REALTEK, RTL8191CU), 171 URTWN_DEV(REALTEK, RTL8192CE), 172 URTWN_DEV(REALTEK, RTL8192CU), 173 URTWN_DEV(SITECOMEU, RTL8188CU), 174 URTWN_DEV(SITECOMEU, RTL8188CU_2), 175 URTWN_DEV(SITECOMEU, RTL8192CU), 176 URTWN_DEV(SITECOMEU, RTL8192CUR2), 177 URTWN_DEV(TPLINK, RTL8192CU), 178 URTWN_DEV(TRENDNET, RTL8188CU), 179 URTWN_DEV(TRENDNET, RTL8192CU), 180 URTWN_DEV(ZYXEL, RTL8192CU), 181 182 /* URTWN_RTL8188E */ 183 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 184 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 185 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 186 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 187 }; 188 #undef URTWN_DEV 189 #undef URTWN_RTL8188E_DEV 190 191 static int urtwn_match(device_t, cfdata_t, void *); 192 static void urtwn_attach(device_t, device_t, void *); 193 static int urtwn_detach(device_t, int); 194 static int urtwn_activate(device_t, enum devact); 195 196 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 197 urtwn_attach, urtwn_detach, urtwn_activate); 198 199 static int urtwn_open_pipes(struct urtwn_softc *); 200 static void urtwn_close_pipes(struct urtwn_softc *); 201 static int urtwn_alloc_rx_list(struct urtwn_softc *); 202 static void urtwn_free_rx_list(struct urtwn_softc *); 203 static int urtwn_alloc_tx_list(struct urtwn_softc *); 204 static void urtwn_free_tx_list(struct urtwn_softc *); 205 static void urtwn_task(void *); 206 static void urtwn_do_async(struct urtwn_softc *, 207 void (*)(struct urtwn_softc *, void *), void *, int); 208 static void urtwn_wait_async(struct urtwn_softc *); 209 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 210 int); 211 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 212 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 213 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 214 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 215 int); 216 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 217 int); 218 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 219 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 220 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 221 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 222 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 223 uint32_t); 224 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 225 uint32_t); 226 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 227 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 228 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 229 static void urtwn_efuse_read(struct urtwn_softc *); 230 static void urtwn_efuse_switch_power(struct urtwn_softc *); 231 static int urtwn_read_chipid(struct urtwn_softc *); 232 #ifdef URTWN_DEBUG 233 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 234 #endif 235 static void urtwn_read_rom(struct urtwn_softc *); 236 static void urtwn_r88e_read_rom(struct urtwn_softc *); 237 static int urtwn_media_change(struct ifnet *); 238 static int urtwn_ra_init(struct urtwn_softc *); 239 static int urtwn_get_nettype(struct urtwn_softc *); 240 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 241 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 242 static void urtwn_set_led(struct urtwn_softc *, int, int); 243 static void urtwn_calib_to(void *); 244 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 245 static void urtwn_next_scan(void *); 246 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 247 int); 248 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 249 static int urtwn_wme_update(struct ieee80211com *); 250 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 251 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 252 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 253 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 254 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 255 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 256 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 257 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 258 struct ieee80211_node *, struct urtwn_tx_data *); 259 static struct urtwn_tx_data * 260 urtwn_get_tx_data(struct urtwn_softc *, size_t); 261 static void urtwn_start(struct ifnet *); 262 static void urtwn_watchdog(struct ifnet *); 263 static int urtwn_ioctl(struct ifnet *, u_long, void *); 264 static int urtwn_r92c_power_on(struct urtwn_softc *); 265 static int urtwn_r88e_power_on(struct urtwn_softc *); 266 static int urtwn_llt_init(struct urtwn_softc *); 267 static void urtwn_fw_reset(struct urtwn_softc *); 268 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 269 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 270 static int urtwn_load_firmware(struct urtwn_softc *); 271 static int urtwn_r92c_dma_init(struct urtwn_softc *); 272 static int urtwn_r88e_dma_init(struct urtwn_softc *); 273 static void urtwn_mac_init(struct urtwn_softc *); 274 static void urtwn_bb_init(struct urtwn_softc *); 275 static void urtwn_rf_init(struct urtwn_softc *); 276 static void urtwn_cam_init(struct urtwn_softc *); 277 static void urtwn_pa_bias_init(struct urtwn_softc *); 278 static void urtwn_rxfilter_init(struct urtwn_softc *); 279 static void urtwn_edca_init(struct urtwn_softc *); 280 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 281 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 282 uint16_t[]); 283 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 284 u_int, uint16_t[]); 285 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 286 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 287 u_int); 288 static void urtwn_iq_calib(struct urtwn_softc *, bool); 289 static void urtwn_lc_calib(struct urtwn_softc *); 290 static void urtwn_temp_calib(struct urtwn_softc *); 291 static int urtwn_init(struct ifnet *); 292 static void urtwn_stop(struct ifnet *, int); 293 static int urtwn_reset(struct ifnet *); 294 static void urtwn_chip_stop(struct urtwn_softc *); 295 static void urtwn_newassoc(struct ieee80211_node *, int); 296 297 /* Aliases. */ 298 #define urtwn_bb_write urtwn_write_4 299 #define urtwn_bb_read urtwn_read_4 300 301 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 302 303 static int 304 urtwn_match(device_t parent, cfdata_t match, void *aux) 305 { 306 struct usb_attach_arg *uaa = aux; 307 308 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 309 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 310 } 311 312 static void 313 urtwn_attach(device_t parent, device_t self, void *aux) 314 { 315 struct urtwn_softc *sc = device_private(self); 316 struct ieee80211com *ic = &sc->sc_ic; 317 struct ifnet *ifp = &sc->sc_if; 318 struct usb_attach_arg *uaa = aux; 319 char *devinfop; 320 const struct urtwn_dev *dev; 321 usb_device_request_t req; 322 size_t i; 323 int error; 324 325 sc->sc_dev = self; 326 sc->sc_udev = uaa->uaa_device; 327 328 sc->chip = 0; 329 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 330 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 331 SET(sc->chip, URTWN_CHIP_88E); 332 333 aprint_naive("\n"); 334 aprint_normal("\n"); 335 336 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 337 338 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 339 aprint_normal_dev(self, "%s\n", devinfop); 340 usbd_devinfo_free(devinfop); 341 342 req.bmRequestType = UT_WRITE_DEVICE; 343 req.bRequest = UR_SET_FEATURE; 344 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 345 USETW(req.wIndex, UHF_PORT_SUSPEND); 346 USETW(req.wLength, 0); 347 348 (void) usbd_do_request(sc->sc_udev, &req, 0); 349 350 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 351 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 352 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 353 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 354 355 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 356 357 callout_init(&sc->sc_scan_to, 0); 358 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 359 callout_init(&sc->sc_calib_to, 0); 360 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 361 362 error = usbd_set_config_no(sc->sc_udev, 1, 0); 363 if (error != 0) { 364 aprint_error_dev(self, "failed to set configuration" 365 ", err=%s\n", usbd_errstr(error)); 366 goto fail; 367 } 368 369 /* Get the first interface handle. */ 370 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 371 if (error != 0) { 372 aprint_error_dev(self, "could not get interface handle\n"); 373 goto fail; 374 } 375 376 error = urtwn_read_chipid(sc); 377 if (error != 0) { 378 aprint_error_dev(self, "unsupported test chip\n"); 379 goto fail; 380 } 381 382 /* Determine number of Tx/Rx chains. */ 383 if (sc->chip & URTWN_CHIP_92C) { 384 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 385 sc->nrxchains = 2; 386 } else { 387 sc->ntxchains = 1; 388 sc->nrxchains = 1; 389 } 390 391 if (ISSET(sc->chip, URTWN_CHIP_88E)) 392 urtwn_r88e_read_rom(sc); 393 else 394 urtwn_read_rom(sc); 395 396 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 397 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 398 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 399 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 400 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 401 "8188CUS", sc->ntxchains, sc->nrxchains, 402 ether_sprintf(ic->ic_myaddr)); 403 404 error = urtwn_open_pipes(sc); 405 if (error != 0) { 406 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 407 goto fail; 408 } 409 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 410 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 411 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 412 413 /* 414 * Setup the 802.11 device. 415 */ 416 ic->ic_ifp = ifp; 417 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 418 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 419 ic->ic_state = IEEE80211_S_INIT; 420 421 /* Set device capabilities. */ 422 ic->ic_caps = 423 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 424 IEEE80211_C_IBSS | /* IBSS mode supported */ 425 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 426 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 427 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 428 IEEE80211_C_WME | /* 802.11e */ 429 IEEE80211_C_WPA; /* 802.11i */ 430 431 /* Set supported .11b and .11g rates. */ 432 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 433 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 434 435 /* Set supported .11b and .11g channels (1 through 14). */ 436 for (i = 1; i <= 14; i++) { 437 ic->ic_channels[i].ic_freq = 438 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 439 ic->ic_channels[i].ic_flags = 440 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 441 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 442 } 443 444 ifp->if_softc = sc; 445 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 446 ifp->if_init = urtwn_init; 447 ifp->if_ioctl = urtwn_ioctl; 448 ifp->if_start = urtwn_start; 449 ifp->if_watchdog = urtwn_watchdog; 450 IFQ_SET_READY(&ifp->if_snd); 451 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 452 453 if_attach(ifp); 454 ieee80211_ifattach(ic); 455 456 /* override default methods */ 457 ic->ic_newassoc = urtwn_newassoc; 458 ic->ic_reset = urtwn_reset; 459 ic->ic_wme.wme_update = urtwn_wme_update; 460 461 /* Override state transition machine. */ 462 sc->sc_newstate = ic->ic_newstate; 463 ic->ic_newstate = urtwn_newstate; 464 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 465 466 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 467 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 468 &sc->sc_drvbpf); 469 470 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 471 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 472 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 473 474 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 475 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 476 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 477 478 ieee80211_announce(ic); 479 480 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 481 482 if (!pmf_device_register(self, NULL, NULL)) 483 aprint_error_dev(self, "couldn't establish power handler\n"); 484 485 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 486 return; 487 488 fail: 489 sc->sc_dying = 1; 490 aprint_error_dev(self, "attach failed\n"); 491 } 492 493 static int 494 urtwn_detach(device_t self, int flags) 495 { 496 struct urtwn_softc *sc = device_private(self); 497 struct ifnet *ifp = &sc->sc_if; 498 int s; 499 500 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 501 502 pmf_device_deregister(self); 503 504 s = splusb(); 505 506 sc->sc_dying = 1; 507 508 callout_stop(&sc->sc_scan_to); 509 callout_stop(&sc->sc_calib_to); 510 511 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 512 usb_rem_task(sc->sc_udev, &sc->sc_task); 513 urtwn_stop(ifp, 0); 514 515 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 516 bpf_detach(ifp); 517 ieee80211_ifdetach(&sc->sc_ic); 518 if_detach(ifp); 519 520 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 521 urtwn_close_pipes(sc); 522 } 523 524 splx(s); 525 526 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 527 528 callout_destroy(&sc->sc_scan_to); 529 callout_destroy(&sc->sc_calib_to); 530 531 mutex_destroy(&sc->sc_write_mtx); 532 mutex_destroy(&sc->sc_fwcmd_mtx); 533 mutex_destroy(&sc->sc_tx_mtx); 534 mutex_destroy(&sc->sc_task_mtx); 535 536 return 0; 537 } 538 539 static int 540 urtwn_activate(device_t self, enum devact act) 541 { 542 struct urtwn_softc *sc = device_private(self); 543 544 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 545 546 switch (act) { 547 case DVACT_DEACTIVATE: 548 if_deactivate(sc->sc_ic.ic_ifp); 549 return 0; 550 default: 551 return EOPNOTSUPP; 552 } 553 } 554 555 static int 556 urtwn_open_pipes(struct urtwn_softc *sc) 557 { 558 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 559 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 560 usb_interface_descriptor_t *id; 561 usb_endpoint_descriptor_t *ed; 562 size_t i, ntx = 0; 563 int error; 564 565 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 566 567 /* Determine the number of bulk-out pipes. */ 568 id = usbd_get_interface_descriptor(sc->sc_iface); 569 for (i = 0; i < id->bNumEndpoints; i++) { 570 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 571 if (ed != NULL && 572 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 573 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 574 ntx++; 575 } 576 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 577 device_xname(sc->sc_dev), __func__, ntx)); 578 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 579 aprint_error_dev(sc->sc_dev, 580 "%zd: invalid number of Tx bulk pipes\n", ntx); 581 return EIO; 582 } 583 sc->rx_npipe = 1; 584 sc->tx_npipe = ntx; 585 586 /* Open bulk-in pipe at address 0x81. */ 587 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 588 &sc->rx_pipe); 589 if (error != 0) { 590 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe" 591 ": %d\n", error); 592 goto fail; 593 } 594 595 /* Open bulk-out pipes (up to 3). */ 596 for (i = 0; i < ntx; i++) { 597 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 598 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 599 if (error != 0) { 600 aprint_error_dev(sc->sc_dev, 601 "could not open Tx bulk pipe 0x%02x: %d\n", 602 epaddr[i], error); 603 goto fail; 604 } 605 } 606 607 /* Map 802.11 access categories to USB pipes. */ 608 sc->ac2idx[WME_AC_BK] = 609 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 610 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 611 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 612 613 fail: 614 if (error != 0) 615 urtwn_close_pipes(sc); 616 return error; 617 } 618 619 static void 620 urtwn_close_pipes(struct urtwn_softc *sc) 621 { 622 struct usbd_pipe *pipe; 623 size_t i; 624 625 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 626 627 /* Close Rx pipe. */ 628 CTASSERT(sizeof(pipe) == sizeof(void *)); 629 pipe = atomic_swap_ptr(&sc->rx_pipe, NULL); 630 if (pipe != NULL) { 631 usbd_close_pipe(pipe); 632 } 633 /* Close Tx pipes. */ 634 for (i = 0; i < R92C_MAX_EPOUT; i++) { 635 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 636 if (pipe != NULL) { 637 usbd_close_pipe(pipe); 638 } 639 } 640 } 641 642 static int 643 urtwn_alloc_rx_list(struct urtwn_softc *sc) 644 { 645 struct urtwn_rx_data *data; 646 size_t i; 647 int error = 0; 648 649 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 650 651 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 652 data = &sc->rx_data[i]; 653 654 data->sc = sc; /* Backpointer for callbacks. */ 655 656 error = usbd_create_xfer(sc->rx_pipe, URTWN_RXBUFSZ, 657 USBD_SHORT_XFER_OK, 0, &data->xfer); 658 if (error) { 659 aprint_error_dev(sc->sc_dev, 660 "could not allocate xfer\n"); 661 break; 662 } 663 664 data->buf = usbd_get_buffer(data->xfer); 665 } 666 if (error != 0) 667 urtwn_free_rx_list(sc); 668 return error; 669 } 670 671 static void 672 urtwn_free_rx_list(struct urtwn_softc *sc) 673 { 674 struct usbd_xfer *xfer; 675 size_t i; 676 677 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 678 679 /* NB: Caller must abort pipe first. */ 680 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 681 CTASSERT(sizeof(xfer) == sizeof(void *)); 682 xfer = atomic_swap_ptr(&sc->rx_data[i].xfer, NULL); 683 if (xfer != NULL) 684 usbd_destroy_xfer(xfer); 685 } 686 } 687 688 static int 689 urtwn_alloc_tx_list(struct urtwn_softc *sc) 690 { 691 struct urtwn_tx_data *data; 692 size_t i; 693 int error = 0; 694 695 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 696 697 mutex_enter(&sc->sc_tx_mtx); 698 for (size_t j = 0; j < sc->tx_npipe; j++) { 699 TAILQ_INIT(&sc->tx_free_list[j]); 700 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 701 data = &sc->tx_data[j][i]; 702 703 data->sc = sc; /* Backpointer for callbacks. */ 704 data->pidx = j; 705 706 error = usbd_create_xfer(sc->tx_pipe[j], 707 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 708 &data->xfer); 709 if (error) { 710 aprint_error_dev(sc->sc_dev, 711 "could not allocate xfer\n"); 712 goto fail; 713 } 714 715 data->buf = usbd_get_buffer(data->xfer); 716 717 /* Append this Tx buffer to our free list. */ 718 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 719 } 720 } 721 mutex_exit(&sc->sc_tx_mtx); 722 return 0; 723 724 fail: 725 urtwn_free_tx_list(sc); 726 mutex_exit(&sc->sc_tx_mtx); 727 return error; 728 } 729 730 static void 731 urtwn_free_tx_list(struct urtwn_softc *sc) 732 { 733 struct usbd_xfer *xfer; 734 size_t i; 735 736 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 737 738 /* NB: Caller must abort pipe first. */ 739 for (size_t j = 0; j < sc->tx_npipe; j++) { 740 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 741 CTASSERT(sizeof(xfer) == sizeof(void *)); 742 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 743 if (xfer != NULL) 744 usbd_destroy_xfer(xfer); 745 } 746 } 747 } 748 749 static void 750 urtwn_task(void *arg) 751 { 752 struct urtwn_softc *sc = arg; 753 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 754 struct urtwn_host_cmd *cmd; 755 int s; 756 757 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 758 759 /* Process host commands. */ 760 s = splusb(); 761 mutex_spin_enter(&sc->sc_task_mtx); 762 while (ring->next != ring->cur) { 763 cmd = &ring->cmd[ring->next]; 764 mutex_spin_exit(&sc->sc_task_mtx); 765 splx(s); 766 /* Invoke callback with kernel lock held. */ 767 cmd->cb(sc, cmd->data); 768 s = splusb(); 769 mutex_spin_enter(&sc->sc_task_mtx); 770 ring->queued--; 771 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 772 } 773 mutex_spin_exit(&sc->sc_task_mtx); 774 wakeup(&sc->cmdq); 775 splx(s); 776 } 777 778 static void 779 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 780 void *arg, int len) 781 { 782 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 783 struct urtwn_host_cmd *cmd; 784 int s; 785 786 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 787 device_xname(sc->sc_dev), __func__, cb, arg, len)); 788 789 s = splusb(); 790 mutex_spin_enter(&sc->sc_task_mtx); 791 cmd = &ring->cmd[ring->cur]; 792 cmd->cb = cb; 793 KASSERT(len <= sizeof(cmd->data)); 794 memcpy(cmd->data, arg, len); 795 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 796 797 /* If there is no pending command already, schedule a task. */ 798 if (!sc->sc_dying && ++ring->queued == 1) { 799 mutex_spin_exit(&sc->sc_task_mtx); 800 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 801 } else 802 mutex_spin_exit(&sc->sc_task_mtx); 803 splx(s); 804 } 805 806 static void 807 urtwn_wait_async(struct urtwn_softc *sc) 808 { 809 810 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 811 812 /* Wait for all queued asynchronous commands to complete. */ 813 while (sc->cmdq.queued > 0) 814 tsleep(&sc->cmdq, 0, "endtask", 0); 815 } 816 817 static int 818 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 819 int len) 820 { 821 usb_device_request_t req; 822 usbd_status error; 823 824 KASSERT(mutex_owned(&sc->sc_write_mtx)); 825 826 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 827 req.bRequest = R92C_REQ_REGS; 828 USETW(req.wValue, addr); 829 USETW(req.wIndex, 0); 830 USETW(req.wLength, len); 831 error = usbd_do_request(sc->sc_udev, &req, buf); 832 if (error != USBD_NORMAL_COMPLETION) { 833 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 834 device_xname(sc->sc_dev), __func__, error, addr, len)); 835 } 836 return error; 837 } 838 839 static void 840 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 841 { 842 843 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 844 device_xname(sc->sc_dev), __func__, addr, val)); 845 846 urtwn_write_region_1(sc, addr, &val, 1); 847 } 848 849 static void 850 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 851 { 852 uint8_t buf[2]; 853 854 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 855 device_xname(sc->sc_dev), __func__, addr, val)); 856 857 buf[0] = (uint8_t)val; 858 buf[1] = (uint8_t)(val >> 8); 859 urtwn_write_region_1(sc, addr, buf, 2); 860 } 861 862 static void 863 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 864 { 865 uint8_t buf[4]; 866 867 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 868 device_xname(sc->sc_dev), __func__, addr, val)); 869 870 buf[0] = (uint8_t)val; 871 buf[1] = (uint8_t)(val >> 8); 872 buf[2] = (uint8_t)(val >> 16); 873 buf[3] = (uint8_t)(val >> 24); 874 urtwn_write_region_1(sc, addr, buf, 4); 875 } 876 877 static int 878 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 879 { 880 881 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 882 device_xname(sc->sc_dev), __func__, addr, len)); 883 884 return urtwn_write_region_1(sc, addr, buf, len); 885 } 886 887 static int 888 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 889 int len) 890 { 891 usb_device_request_t req; 892 usbd_status error; 893 894 req.bmRequestType = UT_READ_VENDOR_DEVICE; 895 req.bRequest = R92C_REQ_REGS; 896 USETW(req.wValue, addr); 897 USETW(req.wIndex, 0); 898 USETW(req.wLength, len); 899 error = usbd_do_request(sc->sc_udev, &req, buf); 900 if (error != USBD_NORMAL_COMPLETION) { 901 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 902 device_xname(sc->sc_dev), __func__, error, addr, len)); 903 } 904 return error; 905 } 906 907 static uint8_t 908 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 909 { 910 uint8_t val; 911 912 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 913 return 0xff; 914 915 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 916 device_xname(sc->sc_dev), __func__, addr, val)); 917 return val; 918 } 919 920 static uint16_t 921 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 922 { 923 uint8_t buf[2]; 924 uint16_t val; 925 926 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 927 return 0xffff; 928 929 val = LE_READ_2(&buf[0]); 930 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 931 device_xname(sc->sc_dev), __func__, addr, val)); 932 return val; 933 } 934 935 static uint32_t 936 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 937 { 938 uint8_t buf[4]; 939 uint32_t val; 940 941 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 942 return 0xffffffff; 943 944 val = LE_READ_4(&buf[0]); 945 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 946 device_xname(sc->sc_dev), __func__, addr, val)); 947 return val; 948 } 949 950 static int 951 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 952 { 953 struct r92c_fw_cmd cmd; 954 uint8_t *cp; 955 int fwcur; 956 int ntries; 957 958 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 959 device_xname(sc->sc_dev), __func__, id, buf, len)); 960 961 KASSERT(mutex_owned(&sc->sc_write_mtx)); 962 963 mutex_enter(&sc->sc_fwcmd_mtx); 964 fwcur = sc->fwcur; 965 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 966 mutex_exit(&sc->sc_fwcmd_mtx); 967 968 /* Wait for current FW box to be empty. */ 969 for (ntries = 0; ntries < 100; ntries++) { 970 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 971 break; 972 DELAY(1); 973 } 974 if (ntries == 100) { 975 aprint_error_dev(sc->sc_dev, 976 "could not send firmware command %d\n", id); 977 return ETIMEDOUT; 978 } 979 980 memset(&cmd, 0, sizeof(cmd)); 981 KASSERT(len <= sizeof(cmd.msg)); 982 memcpy(cmd.msg, buf, len); 983 984 /* Write the first word last since that will trigger the FW. */ 985 cp = (uint8_t *)&cmd; 986 if (len >= 4) { 987 cmd.id = id | R92C_CMD_FLAG_EXT; 988 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 989 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 990 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 991 } else { 992 cmd.id = id; 993 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 994 } 995 996 return 0; 997 } 998 999 static __inline void 1000 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1001 { 1002 1003 sc->sc_rf_write(sc, chain, addr, val); 1004 } 1005 1006 static void 1007 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1008 uint32_t val) 1009 { 1010 1011 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1012 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1013 } 1014 1015 static void 1016 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1017 uint32_t val) 1018 { 1019 1020 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1021 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1022 } 1023 1024 static uint32_t 1025 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1026 { 1027 uint32_t reg[R92C_MAX_CHAINS], val; 1028 1029 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1030 if (chain != 0) { 1031 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1032 } 1033 1034 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1035 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1036 DELAY(1000); 1037 1038 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1039 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1040 R92C_HSSI_PARAM2_READ_EDGE); 1041 DELAY(1000); 1042 1043 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1044 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1045 DELAY(1000); 1046 1047 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1048 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1049 } else { 1050 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1051 } 1052 return MS(val, R92C_LSSI_READBACK_DATA); 1053 } 1054 1055 static int 1056 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1057 { 1058 int ntries; 1059 1060 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1061 1062 urtwn_write_4(sc, R92C_LLT_INIT, 1063 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1064 SM(R92C_LLT_INIT_ADDR, addr) | 1065 SM(R92C_LLT_INIT_DATA, data)); 1066 /* Wait for write operation to complete. */ 1067 for (ntries = 0; ntries < 20; ntries++) { 1068 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1069 R92C_LLT_INIT_OP_NO_ACTIVE) { 1070 /* Done */ 1071 return 0; 1072 } 1073 DELAY(5); 1074 } 1075 return ETIMEDOUT; 1076 } 1077 1078 static uint8_t 1079 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1080 { 1081 uint32_t reg; 1082 int ntries; 1083 1084 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1085 1086 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1087 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1088 reg &= ~R92C_EFUSE_CTRL_VALID; 1089 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1090 1091 /* Wait for read operation to complete. */ 1092 for (ntries = 0; ntries < 100; ntries++) { 1093 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1094 if (reg & R92C_EFUSE_CTRL_VALID) { 1095 /* Done */ 1096 return MS(reg, R92C_EFUSE_CTRL_DATA); 1097 } 1098 DELAY(5); 1099 } 1100 aprint_error_dev(sc->sc_dev, 1101 "could not read efuse byte at address 0x%04x\n", addr); 1102 return 0xff; 1103 } 1104 1105 static void 1106 urtwn_efuse_read(struct urtwn_softc *sc) 1107 { 1108 uint8_t *rom = (uint8_t *)&sc->rom; 1109 uint32_t reg; 1110 uint16_t addr = 0; 1111 uint8_t off, msk; 1112 size_t i; 1113 1114 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1115 1116 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1117 1118 urtwn_efuse_switch_power(sc); 1119 1120 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1121 while (addr < 512) { 1122 reg = urtwn_efuse_read_1(sc, addr); 1123 if (reg == 0xff) 1124 break; 1125 addr++; 1126 off = reg >> 4; 1127 msk = reg & 0xf; 1128 for (i = 0; i < 4; i++) { 1129 if (msk & (1U << i)) 1130 continue; 1131 1132 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1133 addr++; 1134 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1135 addr++; 1136 } 1137 } 1138 #ifdef URTWN_DEBUG 1139 if (urtwn_debug & DBG_INIT) { 1140 /* Dump ROM content. */ 1141 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1142 for (i = 0; i < (int)sizeof(sc->rom); i++) 1143 printf(":%02x", rom[i]); 1144 printf("\n"); 1145 } 1146 #endif 1147 } 1148 1149 static void 1150 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1151 { 1152 uint32_t reg; 1153 1154 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1155 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1156 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1157 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1158 } 1159 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1160 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1161 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1162 reg | R92C_SYS_FUNC_EN_ELDR); 1163 } 1164 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1165 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1166 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1167 urtwn_write_2(sc, R92C_SYS_CLKR, 1168 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1169 } 1170 } 1171 1172 static int 1173 urtwn_read_chipid(struct urtwn_softc *sc) 1174 { 1175 uint32_t reg; 1176 1177 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1178 1179 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1180 return 0; 1181 1182 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1183 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1184 /* test chip, not supported */ 1185 return EIO; 1186 } 1187 if (reg & R92C_SYS_CFG_TYPE_92C) { 1188 sc->chip |= URTWN_CHIP_92C; 1189 /* Check if it is a castrated 8192C. */ 1190 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1191 R92C_HPON_FSM_CHIP_BONDING_ID) == 1192 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1193 sc->chip |= URTWN_CHIP_92C_1T2R; 1194 } 1195 } 1196 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1197 sc->chip |= URTWN_CHIP_UMC; 1198 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1199 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1200 } 1201 } 1202 return 0; 1203 } 1204 1205 #ifdef URTWN_DEBUG 1206 static void 1207 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1208 { 1209 1210 aprint_normal_dev(sc->sc_dev, 1211 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1212 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1213 1214 aprint_normal_dev(sc->sc_dev, 1215 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1216 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1217 1218 aprint_normal_dev(sc->sc_dev, 1219 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1220 rp->macaddr[0], rp->macaddr[1], 1221 rp->macaddr[2], rp->macaddr[3], 1222 rp->macaddr[4], rp->macaddr[5]); 1223 1224 aprint_normal_dev(sc->sc_dev, 1225 "string %s, subcustomer_id 0x%x\n", 1226 rp->string, rp->subcustomer_id); 1227 1228 aprint_normal_dev(sc->sc_dev, 1229 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1230 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1231 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1232 1233 aprint_normal_dev(sc->sc_dev, 1234 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1235 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1236 rp->ht40_1s_tx_pwr[0][2], 1237 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1238 rp->ht40_1s_tx_pwr[1][2]); 1239 1240 aprint_normal_dev(sc->sc_dev, 1241 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1242 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1243 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1244 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1245 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1246 1247 aprint_normal_dev(sc->sc_dev, 1248 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1249 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1250 rp->ht20_tx_pwr_diff[2] & 0xf, 1251 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1252 rp->ht20_tx_pwr_diff[2] >> 4); 1253 1254 aprint_normal_dev(sc->sc_dev, 1255 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1256 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1257 rp->ofdm_tx_pwr_diff[2] & 0xf, 1258 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1259 rp->ofdm_tx_pwr_diff[2] >> 4); 1260 1261 aprint_normal_dev(sc->sc_dev, 1262 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1263 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1264 rp->ht40_max_pwr[2] & 0xf, 1265 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1266 rp->ht40_max_pwr[2] >> 4); 1267 1268 aprint_normal_dev(sc->sc_dev, 1269 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1270 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1271 rp->ht20_max_pwr[2] & 0xf, 1272 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1273 rp->ht20_max_pwr[2] >> 4); 1274 1275 aprint_normal_dev(sc->sc_dev, 1276 "xtal_calib %d, tssi %d %d, thermal %d\n", 1277 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1278 1279 aprint_normal_dev(sc->sc_dev, 1280 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1281 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1282 1283 aprint_normal_dev(sc->sc_dev, 1284 "channnel_plan %d, version %d customer_id 0x%x\n", 1285 rp->channel_plan, rp->version, rp->curstomer_id); 1286 } 1287 #endif 1288 1289 static void 1290 urtwn_read_rom(struct urtwn_softc *sc) 1291 { 1292 struct ieee80211com *ic = &sc->sc_ic; 1293 struct r92c_rom *rom = &sc->rom; 1294 1295 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1296 1297 mutex_enter(&sc->sc_write_mtx); 1298 1299 /* Read full ROM image. */ 1300 urtwn_efuse_read(sc); 1301 #ifdef URTWN_DEBUG 1302 if (urtwn_debug & DBG_REG) 1303 urtwn_dump_rom(sc, rom); 1304 #endif 1305 1306 /* XXX Weird but this is what the vendor driver does. */ 1307 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1308 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1309 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1310 1311 DPRINTFN(DBG_INIT, 1312 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1313 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1314 sc->board_type, sc->regulatory)); 1315 1316 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1317 1318 sc->sc_rf_write = urtwn_r92c_rf_write; 1319 sc->sc_power_on = urtwn_r92c_power_on; 1320 sc->sc_dma_init = urtwn_r92c_dma_init; 1321 1322 mutex_exit(&sc->sc_write_mtx); 1323 } 1324 1325 static void 1326 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1327 { 1328 struct ieee80211com *ic = &sc->sc_ic; 1329 uint8_t *rom = sc->r88e_rom; 1330 uint32_t reg; 1331 uint16_t addr = 0; 1332 uint8_t off, msk, tmp; 1333 int i; 1334 1335 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1336 1337 mutex_enter(&sc->sc_write_mtx); 1338 1339 off = 0; 1340 urtwn_efuse_switch_power(sc); 1341 1342 /* Read full ROM image. */ 1343 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1344 while (addr < 1024) { 1345 reg = urtwn_efuse_read_1(sc, addr); 1346 if (reg == 0xff) 1347 break; 1348 addr++; 1349 if ((reg & 0x1f) == 0x0f) { 1350 tmp = (reg & 0xe0) >> 5; 1351 reg = urtwn_efuse_read_1(sc, addr); 1352 if ((reg & 0x0f) != 0x0f) 1353 off = ((reg & 0xf0) >> 1) | tmp; 1354 addr++; 1355 } else 1356 off = reg >> 4; 1357 msk = reg & 0xf; 1358 for (i = 0; i < 4; i++) { 1359 if (msk & (1 << i)) 1360 continue; 1361 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1362 addr++; 1363 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1364 addr++; 1365 } 1366 } 1367 #ifdef URTWN_DEBUG 1368 if (urtwn_debug & DBG_REG) { 1369 } 1370 #endif 1371 1372 addr = 0x10; 1373 for (i = 0; i < 6; i++) 1374 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1375 for (i = 0; i < 5; i++) 1376 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1377 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1378 if (sc->bw20_tx_pwr_diff & 0x08) 1379 sc->bw20_tx_pwr_diff |= 0xf0; 1380 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1381 if (sc->ofdm_tx_pwr_diff & 0x08) 1382 sc->ofdm_tx_pwr_diff |= 0xf0; 1383 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1384 1385 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1386 1387 sc->sc_rf_write = urtwn_r88e_rf_write; 1388 sc->sc_power_on = urtwn_r88e_power_on; 1389 sc->sc_dma_init = urtwn_r88e_dma_init; 1390 1391 mutex_exit(&sc->sc_write_mtx); 1392 } 1393 1394 static int 1395 urtwn_media_change(struct ifnet *ifp) 1396 { 1397 #ifdef URTWN_DEBUG 1398 struct urtwn_softc *sc = ifp->if_softc; 1399 #endif 1400 int error; 1401 1402 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1403 1404 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1405 return error; 1406 1407 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1408 (IFF_UP | IFF_RUNNING)) { 1409 urtwn_init(ifp); 1410 } 1411 return 0; 1412 } 1413 1414 /* 1415 * Initialize rate adaptation in firmware. 1416 */ 1417 static int 1418 urtwn_ra_init(struct urtwn_softc *sc) 1419 { 1420 static const uint8_t map[] = { 1421 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1422 }; 1423 struct ieee80211com *ic = &sc->sc_ic; 1424 struct ieee80211_node *ni = ic->ic_bss; 1425 struct ieee80211_rateset *rs = &ni->ni_rates; 1426 struct r92c_fw_cmd_macid_cfg cmd; 1427 uint32_t rates, basicrates; 1428 uint32_t mask; 1429 uint8_t mode; 1430 size_t maxrate, maxbasicrate, i, j; 1431 int error; 1432 1433 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1434 1435 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1436 1437 /* Get normal and basic rates mask. */ 1438 rates = basicrates = 0; 1439 maxrate = maxbasicrate = 0; 1440 for (i = 0; i < rs->rs_nrates; i++) { 1441 /* Convert 802.11 rate to HW rate index. */ 1442 for (j = 0; j < __arraycount(map); j++) { 1443 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1444 break; 1445 } 1446 } 1447 if (j == __arraycount(map)) { 1448 /* Unknown rate, skip. */ 1449 continue; 1450 } 1451 1452 rates |= 1U << j; 1453 if (j > maxrate) { 1454 maxrate = j; 1455 } 1456 1457 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1458 basicrates |= 1U << j; 1459 if (j > maxbasicrate) { 1460 maxbasicrate = j; 1461 } 1462 } 1463 } 1464 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1465 mode = R92C_RAID_11B; 1466 } else { 1467 mode = R92C_RAID_11BG; 1468 } 1469 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1470 "maxrate=%zx, maxbasicrate=%zx\n", 1471 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1472 maxrate, maxbasicrate)); 1473 if (basicrates == 0) { 1474 basicrates |= 1; /* add 1Mbps */ 1475 } 1476 1477 /* Set rates mask for group addressed frames. */ 1478 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1479 mask = (mode << 28) | basicrates; 1480 cmd.mask[0] = (uint8_t)mask; 1481 cmd.mask[1] = (uint8_t)(mask >> 8); 1482 cmd.mask[2] = (uint8_t)(mask >> 16); 1483 cmd.mask[3] = (uint8_t)(mask >> 24); 1484 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1485 if (error != 0) { 1486 aprint_error_dev(sc->sc_dev, 1487 "could not add broadcast station\n"); 1488 return error; 1489 } 1490 /* Set initial MRR rate. */ 1491 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1492 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1493 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1494 1495 /* Set rates mask for unicast frames. */ 1496 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1497 mask = (mode << 28) | rates; 1498 cmd.mask[0] = (uint8_t)mask; 1499 cmd.mask[1] = (uint8_t)(mask >> 8); 1500 cmd.mask[2] = (uint8_t)(mask >> 16); 1501 cmd.mask[3] = (uint8_t)(mask >> 24); 1502 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1503 if (error != 0) { 1504 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1505 return error; 1506 } 1507 /* Set initial MRR rate. */ 1508 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1509 __func__, maxrate)); 1510 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1511 1512 /* Indicate highest supported rate. */ 1513 ni->ni_txrate = rs->rs_nrates - 1; 1514 1515 return 0; 1516 } 1517 1518 static int 1519 urtwn_get_nettype(struct urtwn_softc *sc) 1520 { 1521 struct ieee80211com *ic = &sc->sc_ic; 1522 int type; 1523 1524 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1525 1526 switch (ic->ic_opmode) { 1527 case IEEE80211_M_STA: 1528 type = R92C_CR_NETTYPE_INFRA; 1529 break; 1530 1531 case IEEE80211_M_IBSS: 1532 type = R92C_CR_NETTYPE_ADHOC; 1533 break; 1534 1535 default: 1536 type = R92C_CR_NETTYPE_NOLINK; 1537 break; 1538 } 1539 1540 return type; 1541 } 1542 1543 static void 1544 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1545 { 1546 uint8_t reg; 1547 1548 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1549 __func__, type)); 1550 1551 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1552 1553 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1554 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1555 } 1556 1557 static void 1558 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1559 { 1560 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1561 uint64_t tsf; 1562 1563 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1564 1565 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1566 1567 /* Enable TSF synchronization. */ 1568 urtwn_write_1(sc, R92C_BCN_CTRL, 1569 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1570 1571 /* Correct TSF */ 1572 urtwn_write_1(sc, R92C_BCN_CTRL, 1573 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1574 1575 /* Set initial TSF. */ 1576 tsf = ni->ni_tstamp.tsf; 1577 tsf = le64toh(tsf); 1578 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1579 tsf -= IEEE80211_DUR_TU; 1580 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1581 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1582 1583 urtwn_write_1(sc, R92C_BCN_CTRL, 1584 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1585 } 1586 1587 static void 1588 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1589 { 1590 uint8_t reg; 1591 1592 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1593 __func__, led, on)); 1594 1595 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1596 1597 if (led == URTWN_LED_LINK) { 1598 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1599 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1600 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1601 if (!on) { 1602 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1603 urtwn_write_1(sc, R92C_LEDCFG2, 1604 reg | R92C_LEDCFG0_DIS); 1605 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1606 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1607 reg & 0xfe); 1608 } 1609 } else { 1610 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1611 if (!on) { 1612 reg |= R92C_LEDCFG0_DIS; 1613 } 1614 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1615 } 1616 sc->ledlink = on; /* Save LED state. */ 1617 } 1618 } 1619 1620 static void 1621 urtwn_calib_to(void *arg) 1622 { 1623 struct urtwn_softc *sc = arg; 1624 1625 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1626 1627 if (sc->sc_dying) 1628 return; 1629 1630 /* Do it in a process context. */ 1631 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1632 } 1633 1634 /* ARGSUSED */ 1635 static void 1636 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1637 { 1638 struct r92c_fw_cmd_rssi cmd; 1639 1640 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1641 1642 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1643 goto restart_timer; 1644 1645 mutex_enter(&sc->sc_write_mtx); 1646 if (sc->avg_pwdb != -1) { 1647 /* Indicate Rx signal strength to FW for rate adaptation. */ 1648 memset(&cmd, 0, sizeof(cmd)); 1649 cmd.macid = 0; /* BSS. */ 1650 cmd.pwdb = sc->avg_pwdb; 1651 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1652 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1653 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1654 } 1655 1656 /* Do temperature compensation. */ 1657 urtwn_temp_calib(sc); 1658 mutex_exit(&sc->sc_write_mtx); 1659 1660 restart_timer: 1661 if (!sc->sc_dying) { 1662 /* Restart calibration timer. */ 1663 callout_schedule(&sc->sc_calib_to, hz); 1664 } 1665 } 1666 1667 static void 1668 urtwn_next_scan(void *arg) 1669 { 1670 struct urtwn_softc *sc = arg; 1671 int s; 1672 1673 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1674 1675 if (sc->sc_dying) 1676 return; 1677 1678 s = splnet(); 1679 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1680 ieee80211_next_scan(&sc->sc_ic); 1681 splx(s); 1682 } 1683 1684 static void 1685 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1686 { 1687 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1688 ether_sprintf(ni->ni_macaddr))); 1689 /* start with lowest Tx rate */ 1690 ni->ni_txrate = 0; 1691 } 1692 1693 static int 1694 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1695 { 1696 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1697 struct urtwn_cmd_newstate cmd; 1698 1699 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1700 device_xname(sc->sc_dev), __func__, 1701 ieee80211_state_name[nstate], nstate, arg)); 1702 1703 callout_stop(&sc->sc_scan_to); 1704 callout_stop(&sc->sc_calib_to); 1705 1706 /* Do it in a process context. */ 1707 cmd.state = nstate; 1708 cmd.arg = arg; 1709 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1710 return 0; 1711 } 1712 1713 static void 1714 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1715 { 1716 struct urtwn_cmd_newstate *cmd = arg; 1717 struct ieee80211com *ic = &sc->sc_ic; 1718 struct ieee80211_node *ni; 1719 enum ieee80211_state ostate = ic->ic_state; 1720 enum ieee80211_state nstate = cmd->state; 1721 uint32_t reg; 1722 uint8_t sifs_time, msr; 1723 int s; 1724 1725 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1726 device_xname(sc->sc_dev), __func__, 1727 ieee80211_state_name[ostate], ostate, 1728 ieee80211_state_name[nstate], nstate)); 1729 1730 s = splnet(); 1731 mutex_enter(&sc->sc_write_mtx); 1732 1733 callout_stop(&sc->sc_scan_to); 1734 callout_stop(&sc->sc_calib_to); 1735 1736 switch (ostate) { 1737 case IEEE80211_S_INIT: 1738 break; 1739 1740 case IEEE80211_S_SCAN: 1741 if (nstate != IEEE80211_S_SCAN) { 1742 /* 1743 * End of scanning 1744 */ 1745 /* flush 4-AC Queue after site_survey */ 1746 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1747 1748 /* Allow Rx from our BSSID only. */ 1749 urtwn_write_4(sc, R92C_RCR, 1750 urtwn_read_4(sc, R92C_RCR) | 1751 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1752 } 1753 break; 1754 1755 case IEEE80211_S_AUTH: 1756 case IEEE80211_S_ASSOC: 1757 break; 1758 1759 case IEEE80211_S_RUN: 1760 /* Turn link LED off. */ 1761 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1762 1763 /* Set media status to 'No Link'. */ 1764 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1765 1766 /* Stop Rx of data frames. */ 1767 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1768 1769 /* Reset TSF. */ 1770 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1771 1772 /* Disable TSF synchronization. */ 1773 urtwn_write_1(sc, R92C_BCN_CTRL, 1774 urtwn_read_1(sc, R92C_BCN_CTRL) | 1775 R92C_BCN_CTRL_DIS_TSF_UDT0); 1776 1777 /* Back to 20MHz mode */ 1778 urtwn_set_chan(sc, ic->ic_curchan, 1779 IEEE80211_HTINFO_2NDCHAN_NONE); 1780 1781 if (ic->ic_opmode == IEEE80211_M_IBSS || 1782 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1783 /* Stop BCN */ 1784 urtwn_write_1(sc, R92C_BCN_CTRL, 1785 urtwn_read_1(sc, R92C_BCN_CTRL) & 1786 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1787 } 1788 1789 /* Reset EDCA parameters. */ 1790 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1791 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1792 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1793 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1794 1795 /* flush all cam entries */ 1796 urtwn_cam_init(sc); 1797 break; 1798 } 1799 1800 switch (nstate) { 1801 case IEEE80211_S_INIT: 1802 /* Turn link LED off. */ 1803 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1804 break; 1805 1806 case IEEE80211_S_SCAN: 1807 if (ostate != IEEE80211_S_SCAN) { 1808 /* 1809 * Begin of scanning 1810 */ 1811 1812 /* Set gain for scanning. */ 1813 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1814 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1815 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1816 1817 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1818 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1819 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1820 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1821 } 1822 1823 /* Set media status to 'No Link'. */ 1824 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1825 1826 /* Allow Rx from any BSSID. */ 1827 urtwn_write_4(sc, R92C_RCR, 1828 urtwn_read_4(sc, R92C_RCR) & 1829 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1830 1831 /* Stop Rx of data frames. */ 1832 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1833 1834 /* Disable update TSF */ 1835 urtwn_write_1(sc, R92C_BCN_CTRL, 1836 urtwn_read_1(sc, R92C_BCN_CTRL) | 1837 R92C_BCN_CTRL_DIS_TSF_UDT0); 1838 } 1839 1840 /* Make link LED blink during scan. */ 1841 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1842 1843 /* Pause AC Tx queues. */ 1844 urtwn_write_1(sc, R92C_TXPAUSE, 1845 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1846 1847 urtwn_set_chan(sc, ic->ic_curchan, 1848 IEEE80211_HTINFO_2NDCHAN_NONE); 1849 1850 /* Start periodic scan. */ 1851 if (!sc->sc_dying) 1852 callout_schedule(&sc->sc_scan_to, hz / 5); 1853 break; 1854 1855 case IEEE80211_S_AUTH: 1856 /* Set initial gain under link. */ 1857 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1858 #ifdef doaslinux 1859 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1860 #else 1861 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1862 #endif 1863 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1864 1865 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1866 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1867 #ifdef doaslinux 1868 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1869 #else 1870 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1871 #endif 1872 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1873 } 1874 1875 /* Set media status to 'No Link'. */ 1876 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1877 1878 /* Allow Rx from any BSSID. */ 1879 urtwn_write_4(sc, R92C_RCR, 1880 urtwn_read_4(sc, R92C_RCR) & 1881 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1882 1883 urtwn_set_chan(sc, ic->ic_curchan, 1884 IEEE80211_HTINFO_2NDCHAN_NONE); 1885 break; 1886 1887 case IEEE80211_S_ASSOC: 1888 break; 1889 1890 case IEEE80211_S_RUN: 1891 ni = ic->ic_bss; 1892 1893 /* XXX: Set 20MHz mode */ 1894 urtwn_set_chan(sc, ic->ic_curchan, 1895 IEEE80211_HTINFO_2NDCHAN_NONE); 1896 1897 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1898 /* Back to 20MHz mode */ 1899 urtwn_set_chan(sc, ic->ic_curchan, 1900 IEEE80211_HTINFO_2NDCHAN_NONE); 1901 1902 /* Set media status to 'No Link'. */ 1903 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1904 1905 /* Enable Rx of data frames. */ 1906 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1907 1908 /* Allow Rx from any BSSID. */ 1909 urtwn_write_4(sc, R92C_RCR, 1910 urtwn_read_4(sc, R92C_RCR) & 1911 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1912 1913 /* Accept Rx data/control/management frames */ 1914 urtwn_write_4(sc, R92C_RCR, 1915 urtwn_read_4(sc, R92C_RCR) | 1916 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1917 1918 /* Turn link LED on. */ 1919 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1920 break; 1921 } 1922 1923 /* Set media status to 'Associated'. */ 1924 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1925 1926 /* Set BSSID. */ 1927 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1928 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1929 1930 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1931 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1932 } else { 1933 /* 802.11b/g */ 1934 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1935 } 1936 1937 /* Enable Rx of data frames. */ 1938 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1939 1940 /* Set beacon interval. */ 1941 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1942 1943 msr = urtwn_read_1(sc, R92C_MSR); 1944 msr &= R92C_MSR_MASK; 1945 switch (ic->ic_opmode) { 1946 case IEEE80211_M_STA: 1947 /* Allow Rx from our BSSID only. */ 1948 urtwn_write_4(sc, R92C_RCR, 1949 urtwn_read_4(sc, R92C_RCR) | 1950 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1951 1952 /* Enable TSF synchronization. */ 1953 urtwn_tsf_sync_enable(sc); 1954 1955 msr |= R92C_MSR_INFRA; 1956 break; 1957 case IEEE80211_M_HOSTAP: 1958 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1959 1960 /* Allow Rx from any BSSID. */ 1961 urtwn_write_4(sc, R92C_RCR, 1962 urtwn_read_4(sc, R92C_RCR) & 1963 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1964 1965 /* Reset TSF timer to zero. */ 1966 reg = urtwn_read_4(sc, R92C_TCR); 1967 reg &= ~0x01; 1968 urtwn_write_4(sc, R92C_TCR, reg); 1969 reg |= 0x01; 1970 urtwn_write_4(sc, R92C_TCR, reg); 1971 1972 msr |= R92C_MSR_AP; 1973 break; 1974 default: 1975 msr |= R92C_MSR_ADHOC; 1976 break; 1977 } 1978 urtwn_write_1(sc, R92C_MSR, msr); 1979 1980 sifs_time = 10; 1981 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1982 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1983 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1984 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1985 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1986 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1987 1988 /* Intialize rate adaptation. */ 1989 if (ISSET(sc->chip, URTWN_CHIP_88E)) 1990 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 1991 else 1992 urtwn_ra_init(sc); 1993 1994 /* Turn link LED on. */ 1995 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1996 1997 /* Reset average RSSI. */ 1998 sc->avg_pwdb = -1; 1999 2000 /* Reset temperature calibration state machine. */ 2001 sc->thcal_state = 0; 2002 sc->thcal_lctemp = 0; 2003 2004 /* Start periodic calibration. */ 2005 if (!sc->sc_dying) 2006 callout_schedule(&sc->sc_calib_to, hz); 2007 break; 2008 } 2009 2010 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2011 2012 mutex_exit(&sc->sc_write_mtx); 2013 splx(s); 2014 } 2015 2016 static int 2017 urtwn_wme_update(struct ieee80211com *ic) 2018 { 2019 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2020 2021 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2022 2023 /* don't override default WME values if WME is not actually enabled */ 2024 if (!(ic->ic_flags & IEEE80211_F_WME)) 2025 return 0; 2026 2027 /* Do it in a process context. */ 2028 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2029 return 0; 2030 } 2031 2032 static void 2033 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2034 { 2035 static const uint16_t ac2reg[WME_NUM_AC] = { 2036 R92C_EDCA_BE_PARAM, 2037 R92C_EDCA_BK_PARAM, 2038 R92C_EDCA_VI_PARAM, 2039 R92C_EDCA_VO_PARAM 2040 }; 2041 struct ieee80211com *ic = &sc->sc_ic; 2042 const struct wmeParams *wmep; 2043 int ac, aifs, slottime; 2044 int s; 2045 2046 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2047 __func__)); 2048 2049 s = splnet(); 2050 mutex_enter(&sc->sc_write_mtx); 2051 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2052 for (ac = 0; ac < WME_NUM_AC; ac++) { 2053 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2054 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2055 aifs = wmep->wmep_aifsn * slottime + 10; 2056 urtwn_write_4(sc, ac2reg[ac], 2057 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2058 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2059 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2060 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2061 } 2062 mutex_exit(&sc->sc_write_mtx); 2063 splx(s); 2064 } 2065 2066 static void 2067 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2068 { 2069 int pwdb; 2070 2071 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2072 device_xname(sc->sc_dev), __func__, rate, rssi)); 2073 2074 /* Convert antenna signal to percentage. */ 2075 if (rssi <= -100 || rssi >= 20) 2076 pwdb = 0; 2077 else if (rssi >= 0) 2078 pwdb = 100; 2079 else 2080 pwdb = 100 + rssi; 2081 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2082 if (rate <= 3) { 2083 /* CCK gain is smaller than OFDM/MCS gain. */ 2084 pwdb += 6; 2085 if (pwdb > 100) 2086 pwdb = 100; 2087 if (pwdb <= 14) 2088 pwdb -= 4; 2089 else if (pwdb <= 26) 2090 pwdb -= 8; 2091 else if (pwdb <= 34) 2092 pwdb -= 6; 2093 else if (pwdb <= 42) 2094 pwdb -= 2; 2095 } 2096 } 2097 if (sc->avg_pwdb == -1) /* Init. */ 2098 sc->avg_pwdb = pwdb; 2099 else if (sc->avg_pwdb < pwdb) 2100 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2101 else 2102 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2103 2104 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2105 device_xname(sc->sc_dev), __func__, 2106 rate, rssi, pwdb, sc->avg_pwdb)); 2107 } 2108 2109 static int8_t 2110 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2111 { 2112 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2113 struct r92c_rx_phystat *phy; 2114 struct r92c_rx_cck *cck; 2115 uint8_t rpt; 2116 int8_t rssi; 2117 2118 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2119 __func__, rate)); 2120 2121 if (rate <= 3) { 2122 cck = (struct r92c_rx_cck *)physt; 2123 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2124 rpt = (cck->agc_rpt >> 5) & 0x3; 2125 rssi = (cck->agc_rpt & 0x1f) << 1; 2126 } else { 2127 rpt = (cck->agc_rpt >> 6) & 0x3; 2128 rssi = cck->agc_rpt & 0x3e; 2129 } 2130 rssi = cckoff[rpt] - rssi; 2131 } else { /* OFDM/HT. */ 2132 phy = (struct r92c_rx_phystat *)physt; 2133 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2134 } 2135 return rssi; 2136 } 2137 2138 static int8_t 2139 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2140 { 2141 struct r92c_rx_phystat *phy; 2142 struct r88e_rx_cck *cck; 2143 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2144 int8_t rssi; 2145 2146 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2147 __func__, rate)); 2148 2149 rssi = 0; 2150 if (rate <= 3) { 2151 cck = (struct r88e_rx_cck *)physt; 2152 cck_agc_rpt = cck->agc_rpt; 2153 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2154 vga_idx = cck_agc_rpt & 0x1f; 2155 switch (lna_idx) { 2156 case 7: 2157 if (vga_idx <= 27) 2158 rssi = -100 + 2* (27 - vga_idx); 2159 else 2160 rssi = -100; 2161 break; 2162 case 6: 2163 rssi = -48 + 2 * (2 - vga_idx); 2164 break; 2165 case 5: 2166 rssi = -42 + 2 * (7 - vga_idx); 2167 break; 2168 case 4: 2169 rssi = -36 + 2 * (7 - vga_idx); 2170 break; 2171 case 3: 2172 rssi = -24 + 2 * (7 - vga_idx); 2173 break; 2174 case 2: 2175 rssi = -12 + 2 * (5 - vga_idx); 2176 break; 2177 case 1: 2178 rssi = 8 - (2 * vga_idx); 2179 break; 2180 case 0: 2181 rssi = 14 - (2 * vga_idx); 2182 break; 2183 } 2184 rssi += 6; 2185 } else { /* OFDM/HT. */ 2186 phy = (struct r92c_rx_phystat *)physt; 2187 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2188 } 2189 return rssi; 2190 } 2191 2192 static void 2193 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2194 { 2195 struct ieee80211com *ic = &sc->sc_ic; 2196 struct ifnet *ifp = ic->ic_ifp; 2197 struct ieee80211_frame *wh; 2198 struct ieee80211_node *ni; 2199 struct r92c_rx_stat *stat; 2200 uint32_t rxdw0, rxdw3; 2201 struct mbuf *m; 2202 uint8_t rate; 2203 int8_t rssi = 0; 2204 int s, infosz; 2205 2206 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2207 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2208 2209 stat = (struct r92c_rx_stat *)buf; 2210 rxdw0 = le32toh(stat->rxdw0); 2211 rxdw3 = le32toh(stat->rxdw3); 2212 2213 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2214 /* 2215 * This should not happen since we setup our Rx filter 2216 * to not receive these frames. 2217 */ 2218 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2219 device_xname(sc->sc_dev), __func__)); 2220 ifp->if_ierrors++; 2221 return; 2222 } 2223 /* 2224 * XXX: This will drop most control packets. Do we really 2225 * want this in IEEE80211_M_MONITOR mode? 2226 */ 2227 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2228 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2229 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2230 device_xname(sc->sc_dev), __func__, pktlen)); 2231 ic->ic_stats.is_rx_tooshort++; 2232 ifp->if_ierrors++; 2233 return; 2234 } 2235 if (__predict_false(pktlen > MCLBYTES)) { 2236 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2237 device_xname(sc->sc_dev), __func__, pktlen)); 2238 ifp->if_ierrors++; 2239 return; 2240 } 2241 2242 rate = MS(rxdw3, R92C_RXDW3_RATE); 2243 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2244 2245 /* Get RSSI from PHY status descriptor if present. */ 2246 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2247 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2248 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2249 else 2250 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2251 /* Update our average RSSI. */ 2252 urtwn_update_avgrssi(sc, rate, rssi); 2253 } 2254 2255 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2256 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2257 2258 MGETHDR(m, M_DONTWAIT, MT_DATA); 2259 if (__predict_false(m == NULL)) { 2260 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2261 ic->ic_stats.is_rx_nobuf++; 2262 ifp->if_ierrors++; 2263 return; 2264 } 2265 if (pktlen > (int)MHLEN) { 2266 MCLGET(m, M_DONTWAIT); 2267 if (__predict_false(!(m->m_flags & M_EXT))) { 2268 aprint_error_dev(sc->sc_dev, 2269 "couldn't allocate rx mbuf cluster\n"); 2270 m_freem(m); 2271 ic->ic_stats.is_rx_nobuf++; 2272 ifp->if_ierrors++; 2273 return; 2274 } 2275 } 2276 2277 /* Finalize mbuf. */ 2278 m_set_rcvif(m, ifp); 2279 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2280 memcpy(mtod(m, uint8_t *), wh, pktlen); 2281 m->m_pkthdr.len = m->m_len = pktlen; 2282 2283 s = splnet(); 2284 if (__predict_false(sc->sc_drvbpf != NULL)) { 2285 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2286 2287 tap->wr_flags = 0; 2288 if (!(rxdw3 & R92C_RXDW3_HT)) { 2289 switch (rate) { 2290 /* CCK. */ 2291 case 0: tap->wr_rate = 2; break; 2292 case 1: tap->wr_rate = 4; break; 2293 case 2: tap->wr_rate = 11; break; 2294 case 3: tap->wr_rate = 22; break; 2295 /* OFDM. */ 2296 case 4: tap->wr_rate = 12; break; 2297 case 5: tap->wr_rate = 18; break; 2298 case 6: tap->wr_rate = 24; break; 2299 case 7: tap->wr_rate = 36; break; 2300 case 8: tap->wr_rate = 48; break; 2301 case 9: tap->wr_rate = 72; break; 2302 case 10: tap->wr_rate = 96; break; 2303 case 11: tap->wr_rate = 108; break; 2304 } 2305 } else if (rate >= 12) { /* MCS0~15. */ 2306 /* Bit 7 set means HT MCS instead of rate. */ 2307 tap->wr_rate = 0x80 | (rate - 12); 2308 } 2309 tap->wr_dbm_antsignal = rssi; 2310 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2311 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2312 2313 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2314 } 2315 2316 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2317 2318 /* push the frame up to the 802.11 stack */ 2319 ieee80211_input(ic, m, ni, rssi, 0); 2320 2321 /* Node is no longer needed. */ 2322 ieee80211_free_node(ni); 2323 2324 splx(s); 2325 } 2326 2327 static void 2328 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2329 { 2330 struct urtwn_rx_data *data = priv; 2331 struct urtwn_softc *sc = data->sc; 2332 struct r92c_rx_stat *stat; 2333 uint32_t rxdw0; 2334 uint8_t *buf; 2335 int len, totlen, pktlen, infosz, npkts; 2336 2337 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2338 device_xname(sc->sc_dev), __func__, status)); 2339 2340 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2341 if (status == USBD_STALLED) 2342 usbd_clear_endpoint_stall_async(sc->rx_pipe); 2343 else if (status != USBD_CANCELLED) 2344 goto resubmit; 2345 return; 2346 } 2347 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2348 2349 if (__predict_false(len < (int)sizeof(*stat))) { 2350 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2351 device_xname(sc->sc_dev), __func__, len)); 2352 goto resubmit; 2353 } 2354 buf = data->buf; 2355 2356 /* Get the number of encapsulated frames. */ 2357 stat = (struct r92c_rx_stat *)buf; 2358 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2359 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2360 device_xname(sc->sc_dev), __func__, npkts)); 2361 2362 /* Process all of them. */ 2363 while (npkts-- > 0) { 2364 if (__predict_false(len < (int)sizeof(*stat))) { 2365 DPRINTFN(DBG_RX, 2366 ("%s: %s: len(%d) is short than header\n", 2367 device_xname(sc->sc_dev), __func__, len)); 2368 break; 2369 } 2370 stat = (struct r92c_rx_stat *)buf; 2371 rxdw0 = le32toh(stat->rxdw0); 2372 2373 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2374 if (__predict_false(pktlen == 0)) { 2375 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2376 device_xname(sc->sc_dev), __func__)); 2377 break; 2378 } 2379 2380 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2381 2382 /* Make sure everything fits in xfer. */ 2383 totlen = sizeof(*stat) + infosz + pktlen; 2384 if (__predict_false(totlen > len)) { 2385 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2386 device_xname(sc->sc_dev), __func__, totlen, 2387 (int)sizeof(*stat), infosz, pktlen, len)); 2388 break; 2389 } 2390 2391 /* Process 802.11 frame. */ 2392 urtwn_rx_frame(sc, buf, pktlen); 2393 2394 /* Next chunk is 128-byte aligned. */ 2395 totlen = roundup2(totlen, 128); 2396 buf += totlen; 2397 len -= totlen; 2398 } 2399 2400 resubmit: 2401 /* Setup a new transfer. */ 2402 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2403 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2404 (void)usbd_transfer(xfer); 2405 } 2406 2407 static void 2408 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2409 { 2410 struct urtwn_tx_data *data = priv; 2411 struct urtwn_softc *sc = data->sc; 2412 struct ifnet *ifp = &sc->sc_if; 2413 size_t pidx = data->pidx; 2414 int s; 2415 2416 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2417 device_xname(sc->sc_dev), __func__, status)); 2418 2419 mutex_enter(&sc->sc_tx_mtx); 2420 /* Put this Tx buffer back to our free list. */ 2421 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2422 mutex_exit(&sc->sc_tx_mtx); 2423 2424 s = splnet(); 2425 sc->tx_timer = 0; 2426 ifp->if_flags &= ~IFF_OACTIVE; 2427 2428 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2429 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2430 if (status == USBD_STALLED) { 2431 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2432 usbd_clear_endpoint_stall_async(pipe); 2433 } 2434 ifp->if_oerrors++; 2435 } 2436 splx(s); 2437 return; 2438 } 2439 2440 ifp->if_opackets++; 2441 urtwn_start(ifp); 2442 2443 splx(s); 2444 } 2445 2446 static int 2447 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2448 struct urtwn_tx_data *data) 2449 { 2450 struct ieee80211com *ic = &sc->sc_ic; 2451 struct ieee80211_frame *wh; 2452 struct ieee80211_key *k = NULL; 2453 struct r92c_tx_desc *txd; 2454 size_t i, padsize, xferlen; 2455 uint16_t seq, sum; 2456 uint8_t raid, type, tid; 2457 int s, hasqos, error; 2458 2459 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2460 2461 wh = mtod(m, struct ieee80211_frame *); 2462 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2463 2464 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2465 k = ieee80211_crypto_encap(ic, ni, m); 2466 if (k == NULL) 2467 return ENOBUFS; 2468 2469 /* packet header may have moved, reset our local pointer */ 2470 wh = mtod(m, struct ieee80211_frame *); 2471 } 2472 2473 if (__predict_false(sc->sc_drvbpf != NULL)) { 2474 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2475 2476 tap->wt_flags = 0; 2477 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2478 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2479 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2480 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2481 2482 /* XXX: set tap->wt_rate? */ 2483 2484 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2485 } 2486 2487 /* non-qos data frames */ 2488 tid = R92C_TXDW1_QSEL_BE; 2489 if ((hasqos = ieee80211_has_qos(wh))) { 2490 /* data frames in 11n mode */ 2491 struct ieee80211_qosframe *qwh = (void *)wh; 2492 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2493 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2494 tid = R92C_TXDW1_QSEL_MGNT; 2495 } 2496 2497 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2498 padsize = 8; 2499 else 2500 padsize = 0; 2501 2502 /* Fill Tx descriptor. */ 2503 txd = (struct r92c_tx_desc *)data->buf; 2504 memset(txd, 0, sizeof(*txd) + padsize); 2505 2506 txd->txdw0 |= htole32( 2507 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2508 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2509 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2510 2511 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2512 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2513 2514 /* fix pad field */ 2515 if (padsize > 0) { 2516 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2517 device_xname(sc->sc_dev), __func__, padsize)); 2518 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2519 } 2520 2521 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2522 type == IEEE80211_FC0_TYPE_DATA) { 2523 if (ic->ic_curmode == IEEE80211_MODE_11B) 2524 raid = R92C_RAID_11B; 2525 else 2526 raid = R92C_RAID_11BG; 2527 DPRINTFN(DBG_TX, 2528 ("%s: %s: data packet: tid=%d, raid=%d\n", 2529 device_xname(sc->sc_dev), __func__, tid, raid)); 2530 2531 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 2532 txd->txdw1 |= htole32( 2533 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2534 SM(R92C_TXDW1_QSEL, tid) | 2535 SM(R92C_TXDW1_RAID, raid) | 2536 R92C_TXDW1_AGGBK); 2537 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2538 } else 2539 txd->txdw1 |= htole32( 2540 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2541 SM(R92C_TXDW1_QSEL, tid) | 2542 SM(R92C_TXDW1_RAID, raid) | 2543 R92C_TXDW1_AGGBK); 2544 2545 if (hasqos) { 2546 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2547 } 2548 2549 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2550 /* for 11g */ 2551 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2552 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2553 R92C_TXDW4_HWRTSEN); 2554 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2555 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2556 R92C_TXDW4_HWRTSEN); 2557 } 2558 } 2559 /* Send RTS at OFDM24. */ 2560 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2561 txd->txdw5 |= htole32(0x0001ff00); 2562 /* Send data at OFDM54. */ 2563 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2564 txd->txdw5 |= htole32(0x13 & 0x3f); 2565 else 2566 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2567 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2568 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2569 device_xname(sc->sc_dev), __func__)); 2570 txd->txdw1 |= htole32( 2571 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2572 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2573 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2574 2575 /* Force CCK1. */ 2576 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2577 /* Use 1Mbps */ 2578 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2579 } else { 2580 /* broadcast or multicast packets */ 2581 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2582 device_xname(sc->sc_dev), __func__)); 2583 txd->txdw1 |= htole32( 2584 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2585 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2586 2587 /* Force CCK1. */ 2588 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2589 /* Use 1Mbps */ 2590 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2591 } 2592 2593 /* Set sequence number */ 2594 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2595 txd->txdseq |= htole16(seq); 2596 2597 if (!hasqos) { 2598 /* Use HW sequence numbering for non-QoS frames. */ 2599 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2600 txd->txdseq |= htole16(0x8000); /* WTF? */ 2601 } 2602 2603 /* Compute Tx descriptor checksum. */ 2604 sum = 0; 2605 for (i = 0; i < sizeof(*txd) / 2; i++) 2606 sum ^= ((uint16_t *)txd)[i]; 2607 txd->txdsum = sum; /* NB: already little endian. */ 2608 2609 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2610 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2611 2612 s = splnet(); 2613 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2614 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2615 urtwn_txeof); 2616 error = usbd_transfer(data->xfer); 2617 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2618 error != USBD_IN_PROGRESS)) { 2619 splx(s); 2620 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2621 device_xname(sc->sc_dev), __func__, error)); 2622 return error; 2623 } 2624 splx(s); 2625 return 0; 2626 } 2627 2628 struct urtwn_tx_data * 2629 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2630 { 2631 struct urtwn_tx_data *data = NULL; 2632 2633 mutex_enter(&sc->sc_tx_mtx); 2634 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2635 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2636 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2637 } 2638 mutex_exit(&sc->sc_tx_mtx); 2639 2640 return data; 2641 } 2642 2643 static void 2644 urtwn_start(struct ifnet *ifp) 2645 { 2646 struct urtwn_softc *sc = ifp->if_softc; 2647 struct ieee80211com *ic = &sc->sc_ic; 2648 struct urtwn_tx_data *data; 2649 struct ether_header *eh; 2650 struct ieee80211_node *ni; 2651 struct mbuf *m; 2652 2653 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2654 2655 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2656 return; 2657 2658 data = NULL; 2659 for (;;) { 2660 /* Send pending management frames first. */ 2661 IF_POLL(&ic->ic_mgtq, m); 2662 if (m != NULL) { 2663 /* Use AC_VO for management frames. */ 2664 2665 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2666 2667 if (data == NULL) { 2668 ifp->if_flags |= IFF_OACTIVE; 2669 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2670 device_xname(sc->sc_dev))); 2671 return; 2672 } 2673 IF_DEQUEUE(&ic->ic_mgtq, m); 2674 ni = M_GETCTX(m, struct ieee80211_node *); 2675 M_CLEARCTX(m); 2676 goto sendit; 2677 } 2678 if (ic->ic_state != IEEE80211_S_RUN) 2679 break; 2680 2681 /* Encapsulate and send data frames. */ 2682 IFQ_POLL(&ifp->if_snd, m); 2683 if (m == NULL) 2684 break; 2685 2686 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2687 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2688 uint8_t qid = WME_AC_BE; 2689 if (ieee80211_has_qos(wh)) { 2690 /* data frames in 11n mode */ 2691 struct ieee80211_qosframe *qwh = (void *)wh; 2692 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2693 qid = TID_TO_WME_AC(tid); 2694 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2695 qid = WME_AC_VO; 2696 } 2697 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2698 2699 if (data == NULL) { 2700 ifp->if_flags |= IFF_OACTIVE; 2701 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2702 device_xname(sc->sc_dev))); 2703 return; 2704 } 2705 IFQ_DEQUEUE(&ifp->if_snd, m); 2706 2707 if (m->m_len < (int)sizeof(*eh) && 2708 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2709 ifp->if_oerrors++; 2710 continue; 2711 } 2712 eh = mtod(m, struct ether_header *); 2713 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2714 if (ni == NULL) { 2715 m_freem(m); 2716 ifp->if_oerrors++; 2717 continue; 2718 } 2719 2720 bpf_mtap(ifp, m); 2721 2722 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2723 ieee80211_free_node(ni); 2724 ifp->if_oerrors++; 2725 continue; 2726 } 2727 sendit: 2728 bpf_mtap3(ic->ic_rawbpf, m); 2729 2730 if (urtwn_tx(sc, m, ni, data) != 0) { 2731 m_freem(m); 2732 ieee80211_free_node(ni); 2733 ifp->if_oerrors++; 2734 continue; 2735 } 2736 m_freem(m); 2737 ieee80211_free_node(ni); 2738 sc->tx_timer = 5; 2739 ifp->if_timer = 1; 2740 } 2741 } 2742 2743 static void 2744 urtwn_watchdog(struct ifnet *ifp) 2745 { 2746 struct urtwn_softc *sc = ifp->if_softc; 2747 2748 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2749 2750 ifp->if_timer = 0; 2751 2752 if (sc->tx_timer > 0) { 2753 if (--sc->tx_timer == 0) { 2754 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2755 /* urtwn_init(ifp); XXX needs a process context! */ 2756 ifp->if_oerrors++; 2757 return; 2758 } 2759 ifp->if_timer = 1; 2760 } 2761 ieee80211_watchdog(&sc->sc_ic); 2762 } 2763 2764 static int 2765 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2766 { 2767 struct urtwn_softc *sc = ifp->if_softc; 2768 struct ieee80211com *ic = &sc->sc_ic; 2769 int s, error = 0; 2770 2771 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2772 device_xname(sc->sc_dev), __func__, cmd, data)); 2773 2774 s = splnet(); 2775 2776 switch (cmd) { 2777 case SIOCSIFFLAGS: 2778 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2779 break; 2780 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2781 case IFF_UP | IFF_RUNNING: 2782 break; 2783 case IFF_UP: 2784 urtwn_init(ifp); 2785 break; 2786 case IFF_RUNNING: 2787 urtwn_stop(ifp, 1); 2788 break; 2789 case 0: 2790 break; 2791 } 2792 break; 2793 2794 case SIOCADDMULTI: 2795 case SIOCDELMULTI: 2796 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2797 /* setup multicast filter, etc */ 2798 error = 0; 2799 } 2800 break; 2801 2802 default: 2803 error = ieee80211_ioctl(ic, cmd, data); 2804 break; 2805 } 2806 if (error == ENETRESET) { 2807 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2808 (IFF_UP | IFF_RUNNING) && 2809 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2810 urtwn_init(ifp); 2811 } 2812 error = 0; 2813 } 2814 2815 splx(s); 2816 2817 return error; 2818 } 2819 2820 static __inline int 2821 urtwn_power_on(struct urtwn_softc *sc) 2822 { 2823 2824 return sc->sc_power_on(sc); 2825 } 2826 2827 static int 2828 urtwn_r92c_power_on(struct urtwn_softc *sc) 2829 { 2830 uint32_t reg; 2831 int ntries; 2832 2833 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2834 2835 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2836 2837 /* Wait for autoload done bit. */ 2838 for (ntries = 0; ntries < 1000; ntries++) { 2839 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2840 break; 2841 DELAY(5); 2842 } 2843 if (ntries == 1000) { 2844 aprint_error_dev(sc->sc_dev, 2845 "timeout waiting for chip autoload\n"); 2846 return ETIMEDOUT; 2847 } 2848 2849 /* Unlock ISO/CLK/Power control register. */ 2850 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2851 /* Move SPS into PWM mode. */ 2852 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2853 DELAY(100); 2854 2855 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2856 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2857 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2858 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2859 DELAY(100); 2860 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2861 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2862 ~R92C_SYS_ISO_CTRL_MD2PP); 2863 } 2864 2865 /* Auto enable WLAN. */ 2866 urtwn_write_2(sc, R92C_APS_FSMCO, 2867 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2868 for (ntries = 0; ntries < 1000; ntries++) { 2869 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2870 R92C_APS_FSMCO_APFM_ONMAC)) 2871 break; 2872 DELAY(5); 2873 } 2874 if (ntries == 1000) { 2875 aprint_error_dev(sc->sc_dev, 2876 "timeout waiting for MAC auto ON\n"); 2877 return ETIMEDOUT; 2878 } 2879 2880 /* Enable radio, GPIO and LED functions. */ 2881 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2882 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2883 urtwn_write_2(sc, R92C_APS_FSMCO, 2884 R92C_APS_FSMCO_AFSM_HSUS | 2885 R92C_APS_FSMCO_PDN_EN | 2886 R92C_APS_FSMCO_PFM_ALDN); 2887 2888 /* Release RF digital isolation. */ 2889 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2890 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2891 2892 /* Initialize MAC. */ 2893 urtwn_write_1(sc, R92C_APSD_CTRL, 2894 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2895 for (ntries = 0; ntries < 200; ntries++) { 2896 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2897 R92C_APSD_CTRL_OFF_STATUS)) 2898 break; 2899 DELAY(5); 2900 } 2901 if (ntries == 200) { 2902 aprint_error_dev(sc->sc_dev, 2903 "timeout waiting for MAC initialization\n"); 2904 return ETIMEDOUT; 2905 } 2906 2907 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2908 reg = urtwn_read_2(sc, R92C_CR); 2909 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2910 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2911 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2912 R92C_CR_ENSEC; 2913 urtwn_write_2(sc, R92C_CR, reg); 2914 2915 urtwn_write_1(sc, 0xfe10, 0x19); 2916 return 0; 2917 } 2918 2919 static int 2920 urtwn_r88e_power_on(struct urtwn_softc *sc) 2921 { 2922 uint32_t reg; 2923 uint8_t val; 2924 int ntries; 2925 2926 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2927 2928 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2929 2930 /* Wait for power ready bit. */ 2931 for (ntries = 0; ntries < 5000; ntries++) { 2932 val = urtwn_read_1(sc, 0x6) & 0x2; 2933 if (val == 0x2) 2934 break; 2935 DELAY(10); 2936 } 2937 if (ntries == 5000) { 2938 aprint_error_dev(sc->sc_dev, 2939 "timeout waiting for chip power up\n"); 2940 return ETIMEDOUT; 2941 } 2942 2943 /* Reset BB. */ 2944 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2945 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2946 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2947 2948 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2949 2950 /* Disable HWPDN. */ 2951 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2952 2953 /* Disable WL suspend. */ 2954 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2955 2956 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2957 for (ntries = 0; ntries < 5000; ntries++) { 2958 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2959 break; 2960 DELAY(10); 2961 } 2962 if (ntries == 5000) 2963 return ETIMEDOUT; 2964 2965 /* Enable LDO normal mode. */ 2966 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2967 2968 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2969 urtwn_write_2(sc, R92C_CR, 0); 2970 reg = urtwn_read_2(sc, R92C_CR); 2971 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2972 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2973 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2974 urtwn_write_2(sc, R92C_CR, reg); 2975 2976 return 0; 2977 } 2978 2979 static int 2980 urtwn_llt_init(struct urtwn_softc *sc) 2981 { 2982 size_t i, page_count, pktbuf_count; 2983 int error; 2984 2985 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2986 2987 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2988 2989 page_count = (sc->chip & URTWN_CHIP_88E) ? 2990 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2991 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2992 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2993 2994 /* Reserve pages [0; page_count]. */ 2995 for (i = 0; i < page_count; i++) { 2996 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2997 return error; 2998 } 2999 /* NB: 0xff indicates end-of-list. */ 3000 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3001 return error; 3002 /* 3003 * Use pages [page_count + 1; pktbuf_count - 1] 3004 * as ring buffer. 3005 */ 3006 for (++i; i < pktbuf_count - 1; i++) { 3007 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3008 return error; 3009 } 3010 /* Make the last page point to the beginning of the ring buffer. */ 3011 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3012 return error; 3013 } 3014 3015 static void 3016 urtwn_fw_reset(struct urtwn_softc *sc) 3017 { 3018 uint16_t reg; 3019 int ntries; 3020 3021 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3022 3023 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3024 3025 /* Tell 8051 to reset itself. */ 3026 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3027 3028 /* Wait until 8051 resets by itself. */ 3029 for (ntries = 0; ntries < 100; ntries++) { 3030 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3031 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3032 return; 3033 DELAY(50); 3034 } 3035 /* Force 8051 reset. */ 3036 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3037 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3038 } 3039 3040 static void 3041 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3042 { 3043 uint16_t reg; 3044 3045 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3046 3047 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3048 3049 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3050 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3051 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3052 } 3053 3054 static int 3055 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3056 { 3057 uint32_t reg; 3058 int off, mlen, error = 0; 3059 3060 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3061 device_xname(sc->sc_dev), __func__, page, buf, len)); 3062 3063 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3064 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3065 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3066 3067 off = R92C_FW_START_ADDR; 3068 while (len > 0) { 3069 if (len > 196) 3070 mlen = 196; 3071 else if (len > 4) 3072 mlen = 4; 3073 else 3074 mlen = 1; 3075 error = urtwn_write_region(sc, off, buf, mlen); 3076 if (error != 0) 3077 break; 3078 off += mlen; 3079 buf += mlen; 3080 len -= mlen; 3081 } 3082 return error; 3083 } 3084 3085 static int 3086 urtwn_load_firmware(struct urtwn_softc *sc) 3087 { 3088 firmware_handle_t fwh; 3089 const struct r92c_fw_hdr *hdr; 3090 const char *name; 3091 u_char *fw, *ptr; 3092 size_t len; 3093 uint32_t reg; 3094 int mlen, ntries, page, error; 3095 3096 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3097 3098 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3099 3100 /* Read firmware image from the filesystem. */ 3101 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3102 name = "rtl8188eufw.bin"; 3103 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3104 URTWN_CHIP_UMC_A_CUT) 3105 name = "rtl8192cfwU.bin"; 3106 else 3107 name = "rtl8192cfw.bin"; 3108 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3109 aprint_error_dev(sc->sc_dev, 3110 "failed load firmware of file %s (error %d)\n", name, 3111 error); 3112 return error; 3113 } 3114 const size_t fwlen = len = firmware_get_size(fwh); 3115 fw = firmware_malloc(len); 3116 if (fw == NULL) { 3117 aprint_error_dev(sc->sc_dev, 3118 "failed to allocate firmware memory\n"); 3119 firmware_close(fwh); 3120 return ENOMEM; 3121 } 3122 error = firmware_read(fwh, 0, fw, len); 3123 firmware_close(fwh); 3124 if (error != 0) { 3125 aprint_error_dev(sc->sc_dev, 3126 "failed to read firmware (error %d)\n", error); 3127 firmware_free(fw, fwlen); 3128 return error; 3129 } 3130 3131 ptr = fw; 3132 hdr = (const struct r92c_fw_hdr *)ptr; 3133 /* Check if there is a valid FW header and skip it. */ 3134 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3135 (le16toh(hdr->signature) >> 4) == 0x88e || 3136 (le16toh(hdr->signature) >> 4) == 0x92c) { 3137 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3138 device_xname(sc->sc_dev), __func__, 3139 le16toh(hdr->version), le16toh(hdr->subversion), 3140 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3141 ptr += sizeof(*hdr); 3142 len -= sizeof(*hdr); 3143 } 3144 3145 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3146 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3147 urtwn_r88e_fw_reset(sc); 3148 else 3149 urtwn_fw_reset(sc); 3150 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3151 } 3152 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3153 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3154 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3155 R92C_SYS_FUNC_EN_CPUEN); 3156 } 3157 3158 /* download enabled */ 3159 urtwn_write_1(sc, R92C_MCUFWDL, 3160 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3161 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3162 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3163 3164 /* Reset the FWDL checksum. */ 3165 urtwn_write_1(sc, R92C_MCUFWDL, 3166 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3167 3168 /* download firmware */ 3169 for (page = 0; len > 0; page++) { 3170 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3171 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3172 if (error != 0) { 3173 aprint_error_dev(sc->sc_dev, 3174 "could not load firmware page %d\n", page); 3175 goto fail; 3176 } 3177 ptr += mlen; 3178 len -= mlen; 3179 } 3180 3181 /* download disable */ 3182 urtwn_write_1(sc, R92C_MCUFWDL, 3183 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3184 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3185 3186 /* Wait for checksum report. */ 3187 for (ntries = 0; ntries < 1000; ntries++) { 3188 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3189 break; 3190 DELAY(5); 3191 } 3192 if (ntries == 1000) { 3193 aprint_error_dev(sc->sc_dev, 3194 "timeout waiting for checksum report\n"); 3195 error = ETIMEDOUT; 3196 goto fail; 3197 } 3198 3199 /* Wait for firmware readiness. */ 3200 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3201 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3202 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3203 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3204 urtwn_r88e_fw_reset(sc); 3205 for (ntries = 0; ntries < 1000; ntries++) { 3206 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3207 break; 3208 DELAY(5); 3209 } 3210 if (ntries == 1000) { 3211 aprint_error_dev(sc->sc_dev, 3212 "timeout waiting for firmware readiness\n"); 3213 error = ETIMEDOUT; 3214 goto fail; 3215 } 3216 fail: 3217 firmware_free(fw, fwlen); 3218 return error; 3219 } 3220 3221 static __inline int 3222 urtwn_dma_init(struct urtwn_softc *sc) 3223 { 3224 3225 return sc->sc_dma_init(sc); 3226 } 3227 3228 static int 3229 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3230 { 3231 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3232 uint32_t reg; 3233 int error; 3234 3235 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3236 3237 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3238 3239 /* Initialize LLT table. */ 3240 error = urtwn_llt_init(sc); 3241 if (error != 0) 3242 return error; 3243 3244 /* Get Tx queues to USB endpoints mapping. */ 3245 hashq = hasnq = haslq = 0; 3246 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3247 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3248 device_xname(sc->sc_dev), __func__, reg)); 3249 if (MS(reg, R92C_USB_EP_HQ) != 0) 3250 hashq = 1; 3251 if (MS(reg, R92C_USB_EP_NQ) != 0) 3252 hasnq = 1; 3253 if (MS(reg, R92C_USB_EP_LQ) != 0) 3254 haslq = 1; 3255 nqueues = hashq + hasnq + haslq; 3256 if (nqueues == 0) 3257 return EIO; 3258 /* Get the number of pages for each queue. */ 3259 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3260 /* The remaining pages are assigned to the high priority queue. */ 3261 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3262 3263 /* Set number of pages for normal priority queue. */ 3264 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3265 urtwn_write_4(sc, R92C_RQPN, 3266 /* Set number of pages for public queue. */ 3267 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3268 /* Set number of pages for high priority queue. */ 3269 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3270 /* Set number of pages for low priority queue. */ 3271 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3272 /* Load values. */ 3273 R92C_RQPN_LD); 3274 3275 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3276 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3277 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3278 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3279 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3280 3281 /* Set queue to USB pipe mapping. */ 3282 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3283 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3284 if (nqueues == 1) { 3285 if (hashq) { 3286 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3287 } else if (hasnq) { 3288 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3289 } else { 3290 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3291 } 3292 } else if (nqueues == 2) { 3293 /* All 2-endpoints configs have a high priority queue. */ 3294 if (!hashq) { 3295 return EIO; 3296 } 3297 if (hasnq) { 3298 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3299 } else { 3300 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3301 } 3302 } else { 3303 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3304 } 3305 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3306 3307 /* Set Tx/Rx transfer page boundary. */ 3308 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3309 3310 /* Set Tx/Rx transfer page size. */ 3311 urtwn_write_1(sc, R92C_PBP, 3312 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3313 return 0; 3314 } 3315 3316 static int 3317 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3318 { 3319 usb_interface_descriptor_t *id; 3320 uint32_t reg; 3321 int nqueues; 3322 int error; 3323 3324 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3325 3326 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3327 3328 /* Initialize LLT table. */ 3329 error = urtwn_llt_init(sc); 3330 if (error != 0) 3331 return error; 3332 3333 /* Get Tx queues to USB endpoints mapping. */ 3334 id = usbd_get_interface_descriptor(sc->sc_iface); 3335 nqueues = id->bNumEndpoints - 1; 3336 if (nqueues == 0) 3337 return EIO; 3338 3339 /* Set number of pages for normal priority queue. */ 3340 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3341 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3342 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3343 3344 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3345 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3346 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3347 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3348 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3349 3350 /* Set queue to USB pipe mapping. */ 3351 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3352 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3353 if (nqueues == 1) 3354 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3355 else if (nqueues == 2) 3356 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3357 else 3358 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3359 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3360 3361 /* Set Tx/Rx transfer page boundary. */ 3362 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3363 3364 /* Set Tx/Rx transfer page size. */ 3365 urtwn_write_1(sc, R92C_PBP, 3366 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3367 3368 return 0; 3369 } 3370 3371 static void 3372 urtwn_mac_init(struct urtwn_softc *sc) 3373 { 3374 size_t i; 3375 3376 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3377 3378 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3379 3380 /* Write MAC initialization values. */ 3381 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3382 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3383 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3384 rtl8188eu_mac[i].val); 3385 } else { 3386 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3387 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3388 rtl8192cu_mac[i].val); 3389 } 3390 } 3391 3392 static void 3393 urtwn_bb_init(struct urtwn_softc *sc) 3394 { 3395 const struct urtwn_bb_prog *prog; 3396 uint32_t reg; 3397 uint8_t crystalcap; 3398 size_t i; 3399 3400 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3401 3402 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3403 3404 /* Enable BB and RF. */ 3405 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3406 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3407 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3408 R92C_SYS_FUNC_EN_DIO_RF); 3409 3410 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3411 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3412 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3413 } 3414 3415 urtwn_write_1(sc, R92C_RF_CTRL, 3416 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3417 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3418 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3419 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3420 3421 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3422 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3423 urtwn_write_1(sc, 0x15, 0xe9); 3424 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3425 } 3426 3427 /* Select BB programming based on board type. */ 3428 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3429 prog = &rtl8188eu_bb_prog; 3430 else if (!(sc->chip & URTWN_CHIP_92C)) { 3431 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3432 prog = &rtl8188ce_bb_prog; 3433 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3434 prog = &rtl8188ru_bb_prog; 3435 } else { 3436 prog = &rtl8188cu_bb_prog; 3437 } 3438 } else { 3439 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3440 prog = &rtl8192ce_bb_prog; 3441 } else { 3442 prog = &rtl8192cu_bb_prog; 3443 } 3444 } 3445 /* Write BB initialization values. */ 3446 for (i = 0; i < prog->count; i++) { 3447 /* additional delay depend on registers */ 3448 switch (prog->regs[i]) { 3449 case 0xfe: 3450 usbd_delay_ms(sc->sc_udev, 50); 3451 break; 3452 case 0xfd: 3453 usbd_delay_ms(sc->sc_udev, 5); 3454 break; 3455 case 0xfc: 3456 usbd_delay_ms(sc->sc_udev, 1); 3457 break; 3458 case 0xfb: 3459 DELAY(50); 3460 break; 3461 case 0xfa: 3462 DELAY(5); 3463 break; 3464 case 0xf9: 3465 DELAY(1); 3466 break; 3467 } 3468 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3469 DELAY(1); 3470 } 3471 3472 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3473 /* 8192C 1T only configuration. */ 3474 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3475 reg = (reg & ~0x00000003) | 0x2; 3476 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3477 3478 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3479 reg = (reg & ~0x00300033) | 0x00200022; 3480 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3481 3482 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3483 reg = (reg & ~0xff000000) | (0x45 << 24); 3484 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3485 3486 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3487 reg = (reg & ~0x000000ff) | 0x23; 3488 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3489 3490 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3491 reg = (reg & ~0x00000030) | (1 << 4); 3492 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3493 3494 reg = urtwn_bb_read(sc, 0xe74); 3495 reg = (reg & ~0x0c000000) | (2 << 26); 3496 urtwn_bb_write(sc, 0xe74, reg); 3497 reg = urtwn_bb_read(sc, 0xe78); 3498 reg = (reg & ~0x0c000000) | (2 << 26); 3499 urtwn_bb_write(sc, 0xe78, reg); 3500 reg = urtwn_bb_read(sc, 0xe7c); 3501 reg = (reg & ~0x0c000000) | (2 << 26); 3502 urtwn_bb_write(sc, 0xe7c, reg); 3503 reg = urtwn_bb_read(sc, 0xe80); 3504 reg = (reg & ~0x0c000000) | (2 << 26); 3505 urtwn_bb_write(sc, 0xe80, reg); 3506 reg = urtwn_bb_read(sc, 0xe88); 3507 reg = (reg & ~0x0c000000) | (2 << 26); 3508 urtwn_bb_write(sc, 0xe88, reg); 3509 } 3510 3511 /* Write AGC values. */ 3512 for (i = 0; i < prog->agccount; i++) { 3513 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3514 DELAY(1); 3515 } 3516 3517 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3518 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3519 DELAY(1); 3520 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3521 DELAY(1); 3522 3523 crystalcap = sc->r88e_rom[0xb9]; 3524 if (crystalcap == 0xff) 3525 crystalcap = 0x20; 3526 crystalcap &= 0x3f; 3527 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3528 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3529 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3530 crystalcap | crystalcap << 6)); 3531 } else { 3532 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3533 R92C_HSSI_PARAM2_CCK_HIPWR) { 3534 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3535 } 3536 } 3537 } 3538 3539 static void 3540 urtwn_rf_init(struct urtwn_softc *sc) 3541 { 3542 const struct urtwn_rf_prog *prog; 3543 uint32_t reg, mask, saved; 3544 size_t i, j, idx; 3545 3546 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3547 3548 /* Select RF programming based on board type. */ 3549 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3550 prog = rtl8188eu_rf_prog; 3551 else if (!(sc->chip & URTWN_CHIP_92C)) { 3552 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3553 prog = rtl8188ce_rf_prog; 3554 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3555 prog = rtl8188ru_rf_prog; 3556 } else { 3557 prog = rtl8188cu_rf_prog; 3558 } 3559 } else { 3560 prog = rtl8192ce_rf_prog; 3561 } 3562 3563 for (i = 0; i < sc->nrxchains; i++) { 3564 /* Save RF_ENV control type. */ 3565 idx = i / 2; 3566 mask = 0xffffU << ((i % 2) * 16); 3567 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3568 3569 /* Set RF_ENV enable. */ 3570 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3571 reg |= 0x100000; 3572 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3573 DELAY(1); 3574 3575 /* Set RF_ENV output high. */ 3576 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3577 reg |= 0x10; 3578 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3579 DELAY(1); 3580 3581 /* Set address and data lengths of RF registers. */ 3582 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3583 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3584 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3585 DELAY(1); 3586 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3587 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3588 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3589 DELAY(1); 3590 3591 /* Write RF initialization values for this chain. */ 3592 for (j = 0; j < prog[i].count; j++) { 3593 if (prog[i].regs[j] >= 0xf9 && 3594 prog[i].regs[j] <= 0xfe) { 3595 /* 3596 * These are fake RF registers offsets that 3597 * indicate a delay is required. 3598 */ 3599 usbd_delay_ms(sc->sc_udev, 50); 3600 continue; 3601 } 3602 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3603 DELAY(1); 3604 } 3605 3606 /* Restore RF_ENV control type. */ 3607 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3608 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3609 } 3610 3611 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3612 URTWN_CHIP_UMC_A_CUT) { 3613 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3614 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3615 } 3616 3617 /* Cache RF register CHNLBW. */ 3618 for (i = 0; i < 2; i++) { 3619 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3620 } 3621 } 3622 3623 static void 3624 urtwn_cam_init(struct urtwn_softc *sc) 3625 { 3626 uint32_t content, command; 3627 uint8_t idx; 3628 size_t i; 3629 3630 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3631 3632 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3633 3634 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3635 content = (idx & 3) 3636 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3637 | R92C_CAM_VALID; 3638 3639 command = R92C_CAMCMD_POLLING 3640 | R92C_CAMCMD_WRITE 3641 | R92C_CAM_CTL0(idx); 3642 3643 urtwn_write_4(sc, R92C_CAMWRITE, content); 3644 urtwn_write_4(sc, R92C_CAMCMD, command); 3645 } 3646 3647 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3648 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3649 if (i == 0) { 3650 content = (idx & 3) 3651 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3652 | R92C_CAM_VALID; 3653 } else { 3654 content = 0; 3655 } 3656 3657 command = R92C_CAMCMD_POLLING 3658 | R92C_CAMCMD_WRITE 3659 | R92C_CAM_CTL0(idx) 3660 | i; 3661 3662 urtwn_write_4(sc, R92C_CAMWRITE, content); 3663 urtwn_write_4(sc, R92C_CAMCMD, command); 3664 } 3665 } 3666 3667 /* Invalidate all CAM entries. */ 3668 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3669 } 3670 3671 static void 3672 urtwn_pa_bias_init(struct urtwn_softc *sc) 3673 { 3674 uint8_t reg; 3675 size_t i; 3676 3677 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3678 3679 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3680 3681 for (i = 0; i < sc->nrxchains; i++) { 3682 if (sc->pa_setting & (1U << i)) 3683 continue; 3684 3685 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3686 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3687 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3688 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3689 } 3690 if (!(sc->pa_setting & 0x10)) { 3691 reg = urtwn_read_1(sc, 0x16); 3692 reg = (reg & ~0xf0) | 0x90; 3693 urtwn_write_1(sc, 0x16, reg); 3694 } 3695 } 3696 3697 static void 3698 urtwn_rxfilter_init(struct urtwn_softc *sc) 3699 { 3700 3701 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3702 3703 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3704 3705 /* Initialize Rx filter. */ 3706 /* TODO: use better filter for monitor mode. */ 3707 urtwn_write_4(sc, R92C_RCR, 3708 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3709 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3710 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3711 /* Accept all multicast frames. */ 3712 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3713 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3714 /* Accept all management frames. */ 3715 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3716 /* Reject all control frames. */ 3717 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3718 /* Accept all data frames. */ 3719 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3720 } 3721 3722 static void 3723 urtwn_edca_init(struct urtwn_softc *sc) 3724 { 3725 3726 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3727 3728 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3729 3730 /* set spec SIFS (used in NAV) */ 3731 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3732 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3733 3734 /* set SIFS CCK/OFDM */ 3735 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3736 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3737 3738 /* TXOP */ 3739 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3740 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3741 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3742 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3743 } 3744 3745 static void 3746 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3747 uint16_t power[URTWN_RIDX_COUNT]) 3748 { 3749 uint32_t reg; 3750 3751 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3752 __func__, chain)); 3753 3754 /* Write per-CCK rate Tx power. */ 3755 if (chain == 0) { 3756 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3757 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3758 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3759 3760 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3761 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3762 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3763 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3764 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3765 } else { 3766 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3767 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3768 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3769 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3770 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3771 3772 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3773 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3774 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3775 } 3776 /* Write per-OFDM rate Tx power. */ 3777 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3778 SM(R92C_TXAGC_RATE06, power[ 4]) | 3779 SM(R92C_TXAGC_RATE09, power[ 5]) | 3780 SM(R92C_TXAGC_RATE12, power[ 6]) | 3781 SM(R92C_TXAGC_RATE18, power[ 7])); 3782 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3783 SM(R92C_TXAGC_RATE24, power[ 8]) | 3784 SM(R92C_TXAGC_RATE36, power[ 9]) | 3785 SM(R92C_TXAGC_RATE48, power[10]) | 3786 SM(R92C_TXAGC_RATE54, power[11])); 3787 /* Write per-MCS Tx power. */ 3788 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3789 SM(R92C_TXAGC_MCS00, power[12]) | 3790 SM(R92C_TXAGC_MCS01, power[13]) | 3791 SM(R92C_TXAGC_MCS02, power[14]) | 3792 SM(R92C_TXAGC_MCS03, power[15])); 3793 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3794 SM(R92C_TXAGC_MCS04, power[16]) | 3795 SM(R92C_TXAGC_MCS05, power[17]) | 3796 SM(R92C_TXAGC_MCS06, power[18]) | 3797 SM(R92C_TXAGC_MCS07, power[19])); 3798 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3799 SM(R92C_TXAGC_MCS08, power[20]) | 3800 SM(R92C_TXAGC_MCS09, power[21]) | 3801 SM(R92C_TXAGC_MCS10, power[22]) | 3802 SM(R92C_TXAGC_MCS11, power[23])); 3803 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3804 SM(R92C_TXAGC_MCS12, power[24]) | 3805 SM(R92C_TXAGC_MCS13, power[25]) | 3806 SM(R92C_TXAGC_MCS14, power[26]) | 3807 SM(R92C_TXAGC_MCS15, power[27])); 3808 } 3809 3810 static void 3811 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 3812 uint16_t power[URTWN_RIDX_COUNT]) 3813 { 3814 struct r92c_rom *rom = &sc->rom; 3815 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3816 const struct urtwn_txpwr *base; 3817 int ridx, group; 3818 3819 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3820 device_xname(sc->sc_dev), __func__, chain, chan)); 3821 3822 /* Determine channel group. */ 3823 if (chan <= 3) { 3824 group = 0; 3825 } else if (chan <= 9) { 3826 group = 1; 3827 } else { 3828 group = 2; 3829 } 3830 3831 /* Get original Tx power based on board type and RF chain. */ 3832 if (!(sc->chip & URTWN_CHIP_92C)) { 3833 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3834 base = &rtl8188ru_txagc[chain]; 3835 } else { 3836 base = &rtl8192cu_txagc[chain]; 3837 } 3838 } else { 3839 base = &rtl8192cu_txagc[chain]; 3840 } 3841 3842 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3843 if (sc->regulatory == 0) { 3844 for (ridx = 0; ridx <= 3; ridx++) { 3845 power[ridx] = base->pwr[0][ridx]; 3846 } 3847 } 3848 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3849 if (sc->regulatory == 3) { 3850 power[ridx] = base->pwr[0][ridx]; 3851 /* Apply vendor limits. */ 3852 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3853 maxpow = rom->ht40_max_pwr[group]; 3854 } else { 3855 maxpow = rom->ht20_max_pwr[group]; 3856 } 3857 maxpow = (maxpow >> (chain * 4)) & 0xf; 3858 if (power[ridx] > maxpow) { 3859 power[ridx] = maxpow; 3860 } 3861 } else if (sc->regulatory == 1) { 3862 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3863 power[ridx] = base->pwr[group][ridx]; 3864 } 3865 } else if (sc->regulatory != 2) { 3866 power[ridx] = base->pwr[0][ridx]; 3867 } 3868 } 3869 3870 /* Compute per-CCK rate Tx power. */ 3871 cckpow = rom->cck_tx_pwr[chain][group]; 3872 for (ridx = 0; ridx <= 3; ridx++) { 3873 power[ridx] += cckpow; 3874 if (power[ridx] > R92C_MAX_TX_PWR) { 3875 power[ridx] = R92C_MAX_TX_PWR; 3876 } 3877 } 3878 3879 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3880 if (sc->ntxchains > 1) { 3881 /* Apply reduction for 2 spatial streams. */ 3882 diff = rom->ht40_2s_tx_pwr_diff[group]; 3883 diff = (diff >> (chain * 4)) & 0xf; 3884 htpow = (htpow > diff) ? htpow - diff : 0; 3885 } 3886 3887 /* Compute per-OFDM rate Tx power. */ 3888 diff = rom->ofdm_tx_pwr_diff[group]; 3889 diff = (diff >> (chain * 4)) & 0xf; 3890 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3891 for (ridx = 4; ridx <= 11; ridx++) { 3892 power[ridx] += ofdmpow; 3893 if (power[ridx] > R92C_MAX_TX_PWR) { 3894 power[ridx] = R92C_MAX_TX_PWR; 3895 } 3896 } 3897 3898 /* Compute per-MCS Tx power. */ 3899 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3900 diff = rom->ht20_tx_pwr_diff[group]; 3901 diff = (diff >> (chain * 4)) & 0xf; 3902 htpow += diff; /* HT40->HT20 correction. */ 3903 } 3904 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3905 power[ridx] += htpow; 3906 if (power[ridx] > R92C_MAX_TX_PWR) { 3907 power[ridx] = R92C_MAX_TX_PWR; 3908 } 3909 } 3910 #ifdef URTWN_DEBUG 3911 if (urtwn_debug & DBG_RF) { 3912 /* Dump per-rate Tx power values. */ 3913 printf("%s: %s: Tx power for chain %zd:\n", 3914 device_xname(sc->sc_dev), __func__, chain); 3915 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3916 printf("%s: %s: Rate %d = %u\n", 3917 device_xname(sc->sc_dev), __func__, ridx, 3918 power[ridx]); 3919 } 3920 } 3921 #endif 3922 } 3923 3924 void 3925 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 3926 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 3927 { 3928 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3929 const struct urtwn_r88e_txpwr *base; 3930 int ridx, group; 3931 3932 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 3933 device_xname(sc->sc_dev), __func__, chain, chan)); 3934 3935 /* Determine channel group. */ 3936 if (chan <= 2) 3937 group = 0; 3938 else if (chan <= 5) 3939 group = 1; 3940 else if (chan <= 8) 3941 group = 2; 3942 else if (chan <= 11) 3943 group = 3; 3944 else if (chan <= 13) 3945 group = 4; 3946 else 3947 group = 5; 3948 3949 /* Get original Tx power based on board type and RF chain. */ 3950 base = &rtl8188eu_txagc[chain]; 3951 3952 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3953 if (sc->regulatory == 0) { 3954 for (ridx = 0; ridx <= 3; ridx++) 3955 power[ridx] = base->pwr[0][ridx]; 3956 } 3957 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3958 if (sc->regulatory == 3) 3959 power[ridx] = base->pwr[0][ridx]; 3960 else if (sc->regulatory == 1) { 3961 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 3962 power[ridx] = base->pwr[group][ridx]; 3963 } else if (sc->regulatory != 2) 3964 power[ridx] = base->pwr[0][ridx]; 3965 } 3966 3967 /* Compute per-CCK rate Tx power. */ 3968 cckpow = sc->cck_tx_pwr[group]; 3969 for (ridx = 0; ridx <= 3; ridx++) { 3970 power[ridx] += cckpow; 3971 if (power[ridx] > R92C_MAX_TX_PWR) 3972 power[ridx] = R92C_MAX_TX_PWR; 3973 } 3974 3975 htpow = sc->ht40_tx_pwr[group]; 3976 3977 /* Compute per-OFDM rate Tx power. */ 3978 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3979 for (ridx = 4; ridx <= 11; ridx++) { 3980 power[ridx] += ofdmpow; 3981 if (power[ridx] > R92C_MAX_TX_PWR) 3982 power[ridx] = R92C_MAX_TX_PWR; 3983 } 3984 3985 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3986 for (ridx = 12; ridx <= 27; ridx++) { 3987 power[ridx] += bw20pow; 3988 if (power[ridx] > R92C_MAX_TX_PWR) 3989 power[ridx] = R92C_MAX_TX_PWR; 3990 } 3991 } 3992 3993 static void 3994 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3995 { 3996 uint16_t power[URTWN_RIDX_COUNT]; 3997 size_t i; 3998 3999 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4000 4001 for (i = 0; i < sc->ntxchains; i++) { 4002 /* Compute per-rate Tx power values. */ 4003 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4004 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4005 else 4006 urtwn_get_txpower(sc, i, chan, ht40m, power); 4007 /* Write per-rate Tx power values to hardware. */ 4008 urtwn_write_txpower(sc, i, power); 4009 } 4010 } 4011 4012 static void 4013 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4014 { 4015 struct ieee80211com *ic = &sc->sc_ic; 4016 u_int chan; 4017 size_t i; 4018 4019 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4020 4021 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4022 __func__, chan)); 4023 4024 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4025 4026 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4027 chan += 2; 4028 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4029 chan -= 2; 4030 } 4031 4032 /* Set Tx power for this new channel. */ 4033 urtwn_set_txpower(sc, chan, ht40m); 4034 4035 for (i = 0; i < sc->nrxchains; i++) { 4036 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4037 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4038 } 4039 4040 if (ht40m) { 4041 /* Is secondary channel below or above primary? */ 4042 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4043 uint32_t reg; 4044 4045 urtwn_write_1(sc, R92C_BWOPMODE, 4046 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4047 4048 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4049 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4050 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4051 4052 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4053 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4054 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4055 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4056 4057 /* Set CCK side band. */ 4058 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4059 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4060 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4061 4062 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4063 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4064 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4065 4066 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4067 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4068 ~R92C_FPGA0_ANAPARAM2_CBW20); 4069 4070 reg = urtwn_bb_read(sc, 0x818); 4071 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4072 urtwn_bb_write(sc, 0x818, reg); 4073 4074 /* Select 40MHz bandwidth. */ 4075 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4076 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4077 } else { 4078 urtwn_write_1(sc, R92C_BWOPMODE, 4079 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4080 4081 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4082 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4083 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4084 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4085 4086 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4087 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4088 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4089 R92C_FPGA0_ANAPARAM2_CBW20); 4090 } 4091 4092 /* Select 20MHz bandwidth. */ 4093 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4094 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4095 (ISSET(sc->chip, URTWN_CHIP_88E) ? 4096 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4097 } 4098 } 4099 4100 static void 4101 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4102 { 4103 4104 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4105 __func__, inited)); 4106 4107 /* TODO */ 4108 } 4109 4110 static void 4111 urtwn_lc_calib(struct urtwn_softc *sc) 4112 { 4113 uint32_t rf_ac[2]; 4114 uint8_t txmode; 4115 size_t i; 4116 4117 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4118 4119 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4120 4121 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4122 if ((txmode & 0x70) != 0) { 4123 /* Disable all continuous Tx. */ 4124 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4125 4126 /* Set RF mode to standby mode. */ 4127 for (i = 0; i < sc->nrxchains; i++) { 4128 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4129 urtwn_rf_write(sc, i, R92C_RF_AC, 4130 RW(rf_ac[i], R92C_RF_AC_MODE, 4131 R92C_RF_AC_MODE_STANDBY)); 4132 } 4133 } else { 4134 /* Block all Tx queues. */ 4135 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4136 } 4137 /* Start calibration. */ 4138 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4139 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4140 4141 /* Give calibration the time to complete. */ 4142 usbd_delay_ms(sc->sc_udev, 100); 4143 4144 /* Restore configuration. */ 4145 if ((txmode & 0x70) != 0) { 4146 /* Restore Tx mode. */ 4147 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4148 /* Restore RF mode. */ 4149 for (i = 0; i < sc->nrxchains; i++) { 4150 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4151 } 4152 } else { 4153 /* Unblock all Tx queues. */ 4154 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4155 } 4156 } 4157 4158 static void 4159 urtwn_temp_calib(struct urtwn_softc *sc) 4160 { 4161 int temp; 4162 4163 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4164 4165 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4166 4167 if (sc->thcal_state == 0) { 4168 /* Start measuring temperature. */ 4169 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4170 device_xname(sc->sc_dev), __func__)); 4171 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 4172 sc->thcal_state = 1; 4173 return; 4174 } 4175 sc->thcal_state = 0; 4176 4177 /* Read measured temperature. */ 4178 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4179 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4180 __func__, temp)); 4181 if (temp == 0) /* Read failed, skip. */ 4182 return; 4183 4184 /* 4185 * Redo LC calibration if temperature changed significantly since 4186 * last calibration. 4187 */ 4188 if (sc->thcal_lctemp == 0) { 4189 /* First LC calibration is performed in urtwn_init(). */ 4190 sc->thcal_lctemp = temp; 4191 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4192 DPRINTFN(DBG_RF, 4193 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4194 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4195 temp)); 4196 urtwn_lc_calib(sc); 4197 /* Record temperature of last LC calibration. */ 4198 sc->thcal_lctemp = temp; 4199 } 4200 } 4201 4202 static int 4203 urtwn_init(struct ifnet *ifp) 4204 { 4205 struct urtwn_softc *sc = ifp->if_softc; 4206 struct ieee80211com *ic = &sc->sc_ic; 4207 struct urtwn_rx_data *data; 4208 uint32_t reg; 4209 size_t i; 4210 int error; 4211 4212 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4213 4214 urtwn_stop(ifp, 0); 4215 4216 mutex_enter(&sc->sc_write_mtx); 4217 4218 mutex_enter(&sc->sc_task_mtx); 4219 /* Init host async commands ring. */ 4220 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4221 mutex_exit(&sc->sc_task_mtx); 4222 4223 mutex_enter(&sc->sc_fwcmd_mtx); 4224 /* Init firmware commands ring. */ 4225 sc->fwcur = 0; 4226 mutex_exit(&sc->sc_fwcmd_mtx); 4227 4228 /* Allocate Tx/Rx buffers. */ 4229 error = urtwn_alloc_rx_list(sc); 4230 if (error != 0) { 4231 aprint_error_dev(sc->sc_dev, 4232 "could not allocate Rx buffers\n"); 4233 goto fail; 4234 } 4235 error = urtwn_alloc_tx_list(sc); 4236 if (error != 0) { 4237 aprint_error_dev(sc->sc_dev, 4238 "could not allocate Tx buffers\n"); 4239 goto fail; 4240 } 4241 4242 /* Power on adapter. */ 4243 error = urtwn_power_on(sc); 4244 if (error != 0) 4245 goto fail; 4246 4247 /* Initialize DMA. */ 4248 error = urtwn_dma_init(sc); 4249 if (error != 0) 4250 goto fail; 4251 4252 /* Set info size in Rx descriptors (in 64-bit words). */ 4253 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4254 4255 /* Init interrupts. */ 4256 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4257 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4258 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4259 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4260 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4261 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4262 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4263 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4264 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4265 } else { 4266 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4267 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4268 } 4269 4270 /* Set MAC address. */ 4271 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4272 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4273 4274 /* Set initial network type. */ 4275 reg = urtwn_read_4(sc, R92C_CR); 4276 switch (ic->ic_opmode) { 4277 case IEEE80211_M_STA: 4278 default: 4279 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4280 break; 4281 4282 case IEEE80211_M_IBSS: 4283 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4284 break; 4285 } 4286 urtwn_write_4(sc, R92C_CR, reg); 4287 4288 /* Set response rate */ 4289 reg = urtwn_read_4(sc, R92C_RRSR); 4290 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4291 urtwn_write_4(sc, R92C_RRSR, reg); 4292 4293 /* SIFS (used in NAV) */ 4294 urtwn_write_2(sc, R92C_SPEC_SIFS, 4295 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4296 4297 /* Set short/long retry limits. */ 4298 urtwn_write_2(sc, R92C_RL, 4299 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4300 4301 /* Initialize EDCA parameters. */ 4302 urtwn_edca_init(sc); 4303 4304 /* Setup rate fallback. */ 4305 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4306 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4307 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4308 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4309 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4310 } 4311 4312 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4313 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4314 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4315 /* Set ACK timeout. */ 4316 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4317 4318 /* Setup USB aggregation. */ 4319 /* Tx */ 4320 reg = urtwn_read_4(sc, R92C_TDECTRL); 4321 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4322 urtwn_write_4(sc, R92C_TDECTRL, reg); 4323 /* Rx */ 4324 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4325 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4326 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4327 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4328 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4329 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4330 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4331 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4332 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4333 else 4334 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4335 4336 /* Initialize beacon parameters. */ 4337 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4338 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4339 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4340 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4341 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4342 4343 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4344 /* Setup AMPDU aggregation. */ 4345 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4346 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4347 urtwn_write_2(sc, 0x4ca, 0x0708); 4348 4349 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4350 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4351 } 4352 4353 /* Load 8051 microcode. */ 4354 error = urtwn_load_firmware(sc); 4355 if (error != 0) 4356 goto fail; 4357 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4358 4359 /* Initialize MAC/BB/RF blocks. */ 4360 /* 4361 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4362 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4363 * XXX: This setting should be removed from rtl8192cu_mac[]. 4364 */ 4365 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4366 urtwn_rxfilter_init(sc); // reset R92C_RCR 4367 urtwn_bb_init(sc); 4368 urtwn_rf_init(sc); 4369 4370 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4371 urtwn_write_2(sc, R92C_CR, 4372 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4373 R92C_CR_MACRXEN); 4374 } 4375 4376 /* Turn CCK and OFDM blocks on. */ 4377 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4378 reg |= R92C_RFMOD_CCK_EN; 4379 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4380 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4381 reg |= R92C_RFMOD_OFDM_EN; 4382 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4383 4384 /* Clear per-station keys table. */ 4385 urtwn_cam_init(sc); 4386 4387 /* Enable hardware sequence numbering. */ 4388 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4389 4390 /* Perform LO and IQ calibrations. */ 4391 urtwn_iq_calib(sc, sc->iqk_inited); 4392 sc->iqk_inited = true; 4393 4394 /* Perform LC calibration. */ 4395 urtwn_lc_calib(sc); 4396 4397 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 4398 /* Fix USB interference issue. */ 4399 urtwn_write_1(sc, 0xfe40, 0xe0); 4400 urtwn_write_1(sc, 0xfe41, 0x8d); 4401 urtwn_write_1(sc, 0xfe42, 0x80); 4402 urtwn_write_4(sc, 0x20c, 0xfd0320); 4403 4404 urtwn_pa_bias_init(sc); 4405 } 4406 4407 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 4408 /* 1T1R */ 4409 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4410 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4411 } 4412 4413 /* Initialize GPIO setting. */ 4414 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4415 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4416 4417 /* Fix for lower temperature. */ 4418 if (!ISSET(sc->chip, URTWN_CHIP_88E)) 4419 urtwn_write_1(sc, 0x15, 0xe9); 4420 4421 /* Set default channel. */ 4422 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4423 4424 /* Queue Rx xfers. */ 4425 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4426 data = &sc->rx_data[i]; 4427 usbd_setup_xfer(data->xfer, data, data->buf, URTWN_RXBUFSZ, 4428 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 4429 error = usbd_transfer(data->xfer); 4430 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4431 error != USBD_IN_PROGRESS)) 4432 goto fail; 4433 } 4434 4435 /* We're ready to go. */ 4436 ifp->if_flags &= ~IFF_OACTIVE; 4437 ifp->if_flags |= IFF_RUNNING; 4438 4439 mutex_exit(&sc->sc_write_mtx); 4440 4441 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4442 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4443 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4444 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4445 urtwn_wait_async(sc); 4446 4447 return 0; 4448 4449 fail: 4450 mutex_exit(&sc->sc_write_mtx); 4451 4452 urtwn_stop(ifp, 1); 4453 return error; 4454 } 4455 4456 static void 4457 urtwn_stop(struct ifnet *ifp, int disable) 4458 { 4459 struct urtwn_softc *sc = ifp->if_softc; 4460 struct ieee80211com *ic = &sc->sc_ic; 4461 size_t i; 4462 int s; 4463 4464 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4465 4466 s = splusb(); 4467 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4468 urtwn_wait_async(sc); 4469 splx(s); 4470 4471 sc->tx_timer = 0; 4472 ifp->if_timer = 0; 4473 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4474 4475 callout_stop(&sc->sc_scan_to); 4476 callout_stop(&sc->sc_calib_to); 4477 4478 /* Abort Tx. */ 4479 for (i = 0; i < R92C_MAX_EPOUT; i++) { 4480 if (sc->tx_pipe[i] != NULL) 4481 usbd_abort_pipe(sc->tx_pipe[i]); 4482 } 4483 4484 /* Stop Rx pipe. */ 4485 usbd_abort_pipe(sc->rx_pipe); 4486 4487 /* Free Tx/Rx buffers. */ 4488 urtwn_free_tx_list(sc); 4489 urtwn_free_rx_list(sc); 4490 4491 if (disable) 4492 urtwn_chip_stop(sc); 4493 } 4494 4495 static int 4496 urtwn_reset(struct ifnet *ifp) 4497 { 4498 struct urtwn_softc *sc = ifp->if_softc; 4499 struct ieee80211com *ic = &sc->sc_ic; 4500 4501 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4502 return ENETRESET; 4503 4504 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4505 4506 return 0; 4507 } 4508 4509 static void 4510 urtwn_chip_stop(struct urtwn_softc *sc) 4511 { 4512 uint32_t reg; 4513 bool disabled = true; 4514 4515 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4516 4517 mutex_enter(&sc->sc_write_mtx); 4518 4519 /* 4520 * RF Off Sequence 4521 */ 4522 /* Pause MAC TX queue */ 4523 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4524 4525 /* Disable RF */ 4526 urtwn_rf_write(sc, 0, 0, 0); 4527 4528 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4529 4530 /* Reset BB state machine */ 4531 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4532 R92C_SYS_FUNC_EN_USBD | 4533 R92C_SYS_FUNC_EN_USBA | 4534 R92C_SYS_FUNC_EN_BB_GLB_RST); 4535 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4536 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4537 4538 /* 4539 * Reset digital sequence 4540 */ 4541 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4542 /* Reset MCU ready status */ 4543 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4544 /* If firmware in ram code, do reset */ 4545 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4546 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4547 urtwn_r88e_fw_reset(sc); 4548 else 4549 urtwn_fw_reset(sc); 4550 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 4551 } 4552 } 4553 4554 /* Reset MAC and Enable 8051 */ 4555 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 4556 4557 /* Reset MCU ready status */ 4558 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4559 4560 if (disabled) { 4561 /* Disable MAC clock */ 4562 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4563 /* Disable AFE PLL */ 4564 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 4565 /* Gated AFE DIG_CLOCK */ 4566 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 4567 /* Isolated digital to PON */ 4568 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 4569 } 4570 4571 /* 4572 * Pull GPIO PIN to balance level and LED control 4573 */ 4574 /* 1. Disable GPIO[7:0] */ 4575 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 4576 4577 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 4578 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 4579 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 4580 4581 /* Disable GPIO[10:8] */ 4582 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 4583 4584 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 4585 reg |= (((reg & 0x000f) << 4) | 0x0780); 4586 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 4587 4588 /* Disable LED0 & 1 */ 4589 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 4590 4591 /* 4592 * Reset digital sequence 4593 */ 4594 if (disabled) { 4595 /* Disable ELDR clock */ 4596 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 4597 /* Isolated ELDR to PON */ 4598 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 4599 } 4600 4601 /* 4602 * Disable analog sequence 4603 */ 4604 if (disabled) { 4605 /* Disable A15 power */ 4606 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 4607 /* Disable digital core power */ 4608 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 4609 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 4610 ~R92C_LDOV12D_CTRL_LDV12_EN); 4611 } 4612 4613 /* Enter PFM mode */ 4614 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 4615 4616 /* Set USB suspend */ 4617 urtwn_write_2(sc, R92C_APS_FSMCO, 4618 R92C_APS_FSMCO_APDM_HOST | 4619 R92C_APS_FSMCO_AFSM_HSUS | 4620 R92C_APS_FSMCO_PFM_ALDN); 4621 4622 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 4623 4624 mutex_exit(&sc->sc_write_mtx); 4625 } 4626 4627 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 4628 4629 #ifdef _MODULE 4630 #include "ioconf.c" 4631 #endif 4632 4633 static int 4634 if_urtwn_modcmd(modcmd_t cmd, void *aux) 4635 { 4636 int error = 0; 4637 4638 switch (cmd) { 4639 case MODULE_CMD_INIT: 4640 #ifdef _MODULE 4641 error = config_init_component(cfdriver_ioconf_urtwn, 4642 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4643 #endif 4644 return error; 4645 case MODULE_CMD_FINI: 4646 #ifdef _MODULE 4647 error = config_fini_component(cfdriver_ioconf_urtwn, 4648 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 4649 #endif 4650 return error; 4651 default: 4652 return ENOTTY; 4653 } 4654 } 4655
Indexes created Tue Sep 30 20:09:53 GMT 2025