if_urtwn.c revision 1.52.6.1
1 /* $NetBSD: if_urtwn.c,v 1.52.6.1 2017/05/11 02:58:40 pgoyette Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.52.6.1 2017/05/11 02:58:40 pgoyette Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 46 #include <sys/bus.h> 47 #include <machine/endian.h> 48 #include <sys/intr.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_inarp.h> 63 64 #include <net80211/ieee80211_netbsd.h> 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 68 #include <dev/firmload.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 #include <dev/usb/usbdivar.h> 73 #include <dev/usb/usbdi_util.h> 74 #include <dev/usb/usbdevs.h> 75 76 #include <dev/usb/if_urtwnreg.h> 77 #include <dev/usb/if_urtwnvar.h> 78 #include <dev/usb/if_urtwn_data.h> 79 80 /* 81 * The sc_write_mtx locking is to prevent sequences of writes from 82 * being intermingled with each other. I don't know if this is really 83 * needed. I have added it just to be on the safe side. 84 */ 85 86 #ifdef URTWN_DEBUG 87 #define DBG_INIT __BIT(0) 88 #define DBG_FN __BIT(1) 89 #define DBG_TX __BIT(2) 90 #define DBG_RX __BIT(3) 91 #define DBG_STM __BIT(4) 92 #define DBG_RF __BIT(5) 93 #define DBG_REG __BIT(6) 94 #define DBG_ALL 0xffffffffU 95 u_int urtwn_debug = 0; 96 #define DPRINTFN(n, s) \ 97 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 98 #else 99 #define DPRINTFN(n, s) 100 #endif 101 102 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 103 #define URTWN_RTL8188E_DEV(v,p) \ 104 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 105 #define URTWN_RTL8192EU_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 107 static const struct urtwn_dev { 108 struct usb_devno dev; 109 uint32_t flags; 110 #define FLAG_RTL8188E __BIT(0) 111 #define FLAG_RTL8192E __BIT(1) 112 } urtwn_devs[] = { 113 URTWN_DEV(ABOCOM, RTL8188CU_1), 114 URTWN_DEV(ABOCOM, RTL8188CU_2), 115 URTWN_DEV(ABOCOM, RTL8192CU), 116 URTWN_DEV(ASUSTEK, RTL8192CU), 117 URTWN_DEV(ASUSTEK, RTL8192CU_3), 118 URTWN_DEV(ASUSTEK, USBN10NANO), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 121 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 122 URTWN_DEV(AZUREWAVE, RTL8188CU), 123 URTWN_DEV(BELKIN, F7D2102), 124 URTWN_DEV(BELKIN, RTL8188CU), 125 URTWN_DEV(BELKIN, RTL8188CUS), 126 URTWN_DEV(BELKIN, RTL8192CU), 127 URTWN_DEV(BELKIN, RTL8192CU_1), 128 URTWN_DEV(BELKIN, RTL8192CU_2), 129 URTWN_DEV(CHICONY, RTL8188CUS_1), 130 URTWN_DEV(CHICONY, RTL8188CUS_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_3), 132 URTWN_DEV(CHICONY, RTL8188CUS_4), 133 URTWN_DEV(CHICONY, RTL8188CUS_5), 134 URTWN_DEV(CHICONY, RTL8188CUS_6), 135 URTWN_DEV(COMPARE, RTL8192CU), 136 URTWN_DEV(COREGA, RTL8192CU), 137 URTWN_DEV(DLINK, DWA131B), 138 URTWN_DEV(DLINK, RTL8188CU), 139 URTWN_DEV(DLINK, RTL8192CU_1), 140 URTWN_DEV(DLINK, RTL8192CU_2), 141 URTWN_DEV(DLINK, RTL8192CU_3), 142 URTWN_DEV(DLINK, RTL8192CU_4), 143 URTWN_DEV(EDIMAX, RTL8188CU), 144 URTWN_DEV(EDIMAX, RTL8192CU), 145 URTWN_DEV(FEIXUN, RTL8188CU), 146 URTWN_DEV(FEIXUN, RTL8192CU), 147 URTWN_DEV(GUILLEMOT, HWNUP150), 148 URTWN_DEV(GUILLEMOT, RTL8192CU), 149 URTWN_DEV(HAWKING, RTL8192CU), 150 URTWN_DEV(HAWKING, RTL8192CU_2), 151 URTWN_DEV(HP3, RTL8188CU), 152 URTWN_DEV(IODATA, WNG150UM), 153 URTWN_DEV(IODATA, RTL8192CU), 154 URTWN_DEV(NETGEAR, WNA1000M), 155 URTWN_DEV(NETGEAR, RTL8192CU), 156 URTWN_DEV(NETGEAR4, RTL8188CU), 157 URTWN_DEV(NOVATECH, RTL8188CU), 158 URTWN_DEV(PLANEX2, RTL8188CU_1), 159 URTWN_DEV(PLANEX2, RTL8188CU_2), 160 URTWN_DEV(PLANEX2, RTL8192CU), 161 URTWN_DEV(PLANEX2, RTL8188CU_3), 162 URTWN_DEV(PLANEX2, RTL8188CU_4), 163 URTWN_DEV(PLANEX2, RTL8188CUS), 164 URTWN_DEV(REALTEK, RTL8188CE_0), 165 URTWN_DEV(REALTEK, RTL8188CE_1), 166 URTWN_DEV(REALTEK, RTL8188CTV), 167 URTWN_DEV(REALTEK, RTL8188CU_0), 168 URTWN_DEV(REALTEK, RTL8188CU_1), 169 URTWN_DEV(REALTEK, RTL8188CU_2), 170 URTWN_DEV(REALTEK, RTL8188CU_3), 171 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 172 URTWN_DEV(REALTEK, RTL8188CUS), 173 URTWN_DEV(REALTEK, RTL8188RU), 174 URTWN_DEV(REALTEK, RTL8188RU_2), 175 URTWN_DEV(REALTEK, RTL8188RU_3), 176 URTWN_DEV(REALTEK, RTL8191CU), 177 URTWN_DEV(REALTEK, RTL8192CE), 178 URTWN_DEV(REALTEK, RTL8192CU), 179 URTWN_DEV(SITECOMEU, RTL8188CU), 180 URTWN_DEV(SITECOMEU, RTL8188CU_2), 181 URTWN_DEV(SITECOMEU, RTL8192CU), 182 URTWN_DEV(SITECOMEU, RTL8192CUR2), 183 URTWN_DEV(TPLINK, RTL8192CU), 184 URTWN_DEV(TRENDNET, RTL8188CU), 185 URTWN_DEV(TRENDNET, RTL8192CU), 186 URTWN_DEV(ZYXEL, RTL8192CU), 187 188 /* URTWN_RTL8188E */ 189 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 190 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 191 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 192 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 193 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 194 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 195 196 /* URTWN_RTL8192EU */ 197 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 198 }; 199 #undef URTWN_DEV 200 #undef URTWN_RTL8188E_DEV 201 #undef URTWN_RTL8192EU_DEV 202 203 static int urtwn_match(device_t, cfdata_t, void *); 204 static void urtwn_attach(device_t, device_t, void *); 205 static int urtwn_detach(device_t, int); 206 static int urtwn_activate(device_t, enum devact); 207 208 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 209 urtwn_attach, urtwn_detach, urtwn_activate); 210 211 static int urtwn_open_pipes(struct urtwn_softc *); 212 static void urtwn_close_pipes(struct urtwn_softc *); 213 static int urtwn_alloc_rx_list(struct urtwn_softc *); 214 static void urtwn_free_rx_list(struct urtwn_softc *); 215 static int urtwn_alloc_tx_list(struct urtwn_softc *); 216 static void urtwn_free_tx_list(struct urtwn_softc *); 217 static void urtwn_task(void *); 218 static void urtwn_do_async(struct urtwn_softc *, 219 void (*)(struct urtwn_softc *, void *), void *, int); 220 static void urtwn_wait_async(struct urtwn_softc *); 221 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 222 int); 223 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 224 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 225 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 226 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 227 int); 228 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 229 int); 230 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 231 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 232 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 233 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 234 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 235 uint32_t); 236 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 237 uint32_t); 238 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 239 uint32_t); 240 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 241 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 242 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 243 static void urtwn_efuse_read(struct urtwn_softc *); 244 static void urtwn_efuse_switch_power(struct urtwn_softc *); 245 static int urtwn_read_chipid(struct urtwn_softc *); 246 #ifdef URTWN_DEBUG 247 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 248 #endif 249 static void urtwn_read_rom(struct urtwn_softc *); 250 static void urtwn_r88e_read_rom(struct urtwn_softc *); 251 static int urtwn_media_change(struct ifnet *); 252 static int urtwn_ra_init(struct urtwn_softc *); 253 static int urtwn_get_nettype(struct urtwn_softc *); 254 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 255 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 256 static void urtwn_set_led(struct urtwn_softc *, int, int); 257 static void urtwn_calib_to(void *); 258 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 259 static void urtwn_next_scan(void *); 260 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 261 int); 262 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 263 static int urtwn_wme_update(struct ieee80211com *); 264 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 265 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 266 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 267 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 268 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 269 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 270 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 271 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 272 struct ieee80211_node *, struct urtwn_tx_data *); 273 static struct urtwn_tx_data * 274 urtwn_get_tx_data(struct urtwn_softc *, size_t); 275 static void urtwn_start(struct ifnet *); 276 static void urtwn_watchdog(struct ifnet *); 277 static int urtwn_ioctl(struct ifnet *, u_long, void *); 278 static int urtwn_r92c_power_on(struct urtwn_softc *); 279 static int urtwn_r92e_power_on(struct urtwn_softc *); 280 static int urtwn_r88e_power_on(struct urtwn_softc *); 281 static int urtwn_llt_init(struct urtwn_softc *); 282 static void urtwn_fw_reset(struct urtwn_softc *); 283 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 284 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 285 static int urtwn_load_firmware(struct urtwn_softc *); 286 static int urtwn_r92c_dma_init(struct urtwn_softc *); 287 static int urtwn_r88e_dma_init(struct urtwn_softc *); 288 static void urtwn_mac_init(struct urtwn_softc *); 289 static void urtwn_bb_init(struct urtwn_softc *); 290 static void urtwn_rf_init(struct urtwn_softc *); 291 static void urtwn_cam_init(struct urtwn_softc *); 292 static void urtwn_pa_bias_init(struct urtwn_softc *); 293 static void urtwn_rxfilter_init(struct urtwn_softc *); 294 static void urtwn_edca_init(struct urtwn_softc *); 295 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 296 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 297 uint16_t[]); 298 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 299 u_int, uint16_t[]); 300 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 301 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 302 u_int); 303 static void urtwn_iq_calib(struct urtwn_softc *, bool); 304 static void urtwn_lc_calib(struct urtwn_softc *); 305 static void urtwn_temp_calib(struct urtwn_softc *); 306 static int urtwn_init(struct ifnet *); 307 static void urtwn_stop(struct ifnet *, int); 308 static int urtwn_reset(struct ifnet *); 309 static void urtwn_chip_stop(struct urtwn_softc *); 310 static void urtwn_newassoc(struct ieee80211_node *, int); 311 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 312 313 /* Aliases. */ 314 #define urtwn_bb_write urtwn_write_4 315 #define urtwn_bb_read urtwn_read_4 316 317 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 318 319 static const uint16_t addaReg[] = { 320 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 321 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 322 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 323 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 324 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 325 }; 326 327 static int 328 urtwn_match(device_t parent, cfdata_t match, void *aux) 329 { 330 struct usb_attach_arg *uaa = aux; 331 332 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 333 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 334 } 335 336 static void 337 urtwn_attach(device_t parent, device_t self, void *aux) 338 { 339 struct urtwn_softc *sc = device_private(self); 340 struct ieee80211com *ic = &sc->sc_ic; 341 struct ifnet *ifp = &sc->sc_if; 342 struct usb_attach_arg *uaa = aux; 343 char *devinfop; 344 const struct urtwn_dev *dev; 345 usb_device_request_t req; 346 size_t i; 347 int error; 348 349 sc->sc_dev = self; 350 sc->sc_udev = uaa->uaa_device; 351 352 sc->chip = 0; 353 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 354 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 355 SET(sc->chip, URTWN_CHIP_88E); 356 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 357 SET(sc->chip, URTWN_CHIP_92EU); 358 359 aprint_naive("\n"); 360 aprint_normal("\n"); 361 362 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 363 364 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 365 aprint_normal_dev(self, "%s\n", devinfop); 366 usbd_devinfo_free(devinfop); 367 368 req.bmRequestType = UT_WRITE_DEVICE; 369 req.bRequest = UR_SET_FEATURE; 370 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 371 USETW(req.wIndex, UHF_PORT_SUSPEND); 372 USETW(req.wLength, 0); 373 374 (void) usbd_do_request(sc->sc_udev, &req, 0); 375 376 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 377 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 378 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 379 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 380 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 381 382 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 383 384 callout_init(&sc->sc_scan_to, 0); 385 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 386 callout_init(&sc->sc_calib_to, 0); 387 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 388 389 error = usbd_set_config_no(sc->sc_udev, 1, 0); 390 if (error != 0) { 391 aprint_error_dev(self, "failed to set configuration" 392 ", err=%s\n", usbd_errstr(error)); 393 goto fail; 394 } 395 396 /* Get the first interface handle. */ 397 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 398 if (error != 0) { 399 aprint_error_dev(self, "could not get interface handle\n"); 400 goto fail; 401 } 402 403 error = urtwn_read_chipid(sc); 404 if (error != 0) { 405 aprint_error_dev(self, "unsupported test chip\n"); 406 goto fail; 407 } 408 409 /* Determine number of Tx/Rx chains. */ 410 if (sc->chip & URTWN_CHIP_92C) { 411 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 412 sc->nrxchains = 2; 413 } else if (sc->chip & URTWN_CHIP_92EU) { 414 sc->ntxchains = 2; 415 sc->nrxchains = 2; 416 } else { 417 sc->ntxchains = 1; 418 sc->nrxchains = 1; 419 } 420 421 if (ISSET(sc->chip, URTWN_CHIP_88E) || 422 ISSET(sc->chip, URTWN_CHIP_92EU)) 423 urtwn_r88e_read_rom(sc); 424 else 425 urtwn_read_rom(sc); 426 427 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 428 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 429 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 430 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 431 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 432 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 433 "8188CUS", sc->ntxchains, sc->nrxchains, 434 ether_sprintf(ic->ic_myaddr)); 435 436 error = urtwn_open_pipes(sc); 437 if (error != 0) { 438 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 439 goto fail; 440 } 441 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 442 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 443 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 444 445 /* 446 * Setup the 802.11 device. 447 */ 448 ic->ic_ifp = ifp; 449 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 450 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 451 ic->ic_state = IEEE80211_S_INIT; 452 453 /* Set device capabilities. */ 454 ic->ic_caps = 455 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 456 IEEE80211_C_IBSS | /* IBSS mode supported */ 457 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 458 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 459 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 460 IEEE80211_C_WME | /* 802.11e */ 461 IEEE80211_C_WPA; /* 802.11i */ 462 463 /* Set supported .11b and .11g rates. */ 464 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 465 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 466 467 /* Set supported .11b and .11g channels (1 through 14). */ 468 for (i = 1; i <= 14; i++) { 469 ic->ic_channels[i].ic_freq = 470 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 471 ic->ic_channels[i].ic_flags = 472 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 473 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 474 } 475 476 ifp->if_softc = sc; 477 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 478 ifp->if_init = urtwn_init; 479 ifp->if_ioctl = urtwn_ioctl; 480 ifp->if_start = urtwn_start; 481 ifp->if_watchdog = urtwn_watchdog; 482 IFQ_SET_READY(&ifp->if_snd); 483 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 484 485 if_attach(ifp); 486 ieee80211_ifattach(ic); 487 488 /* override default methods */ 489 ic->ic_newassoc = urtwn_newassoc; 490 ic->ic_reset = urtwn_reset; 491 ic->ic_wme.wme_update = urtwn_wme_update; 492 493 /* Override state transition machine. */ 494 sc->sc_newstate = ic->ic_newstate; 495 ic->ic_newstate = urtwn_newstate; 496 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 497 498 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 499 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 500 &sc->sc_drvbpf); 501 502 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 503 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 504 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 505 506 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 507 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 508 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 509 510 ieee80211_announce(ic); 511 512 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 513 514 if (!pmf_device_register(self, NULL, NULL)) 515 aprint_error_dev(self, "couldn't establish power handler\n"); 516 517 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 518 return; 519 520 fail: 521 sc->sc_dying = 1; 522 aprint_error_dev(self, "attach failed\n"); 523 } 524 525 static int 526 urtwn_detach(device_t self, int flags) 527 { 528 struct urtwn_softc *sc = device_private(self); 529 struct ifnet *ifp = &sc->sc_if; 530 int s; 531 532 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 533 534 pmf_device_deregister(self); 535 536 s = splusb(); 537 538 sc->sc_dying = 1; 539 540 callout_stop(&sc->sc_scan_to); 541 callout_stop(&sc->sc_calib_to); 542 543 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 544 usb_rem_task(sc->sc_udev, &sc->sc_task); 545 urtwn_stop(ifp, 0); 546 547 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 548 bpf_detach(ifp); 549 ieee80211_ifdetach(&sc->sc_ic); 550 if_detach(ifp); 551 552 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 553 urtwn_close_pipes(sc); 554 } 555 556 splx(s); 557 558 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 559 560 callout_destroy(&sc->sc_scan_to); 561 callout_destroy(&sc->sc_calib_to); 562 563 mutex_destroy(&sc->sc_write_mtx); 564 mutex_destroy(&sc->sc_fwcmd_mtx); 565 mutex_destroy(&sc->sc_tx_mtx); 566 mutex_destroy(&sc->sc_rx_mtx); 567 mutex_destroy(&sc->sc_task_mtx); 568 569 return 0; 570 } 571 572 static int 573 urtwn_activate(device_t self, enum devact act) 574 { 575 struct urtwn_softc *sc = device_private(self); 576 577 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 578 579 switch (act) { 580 case DVACT_DEACTIVATE: 581 if_deactivate(sc->sc_ic.ic_ifp); 582 return 0; 583 default: 584 return EOPNOTSUPP; 585 } 586 } 587 588 static int 589 urtwn_open_pipes(struct urtwn_softc *sc) 590 { 591 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 592 static uint8_t epaddr[3]; 593 static uint8_t rxepaddr[3]; 594 usb_interface_descriptor_t *id; 595 usb_endpoint_descriptor_t *ed; 596 size_t i, ntx = 0, nrx = 0; 597 int error; 598 599 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 600 601 /* Determine the number of bulk-out pipes. */ 602 id = usbd_get_interface_descriptor(sc->sc_iface); 603 for (i = 0; i < id->bNumEndpoints; i++) { 604 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 605 if (ed != NULL && 606 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 607 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 608 epaddr[ntx] = ed->bEndpointAddress; 609 ntx++; 610 } 611 if (ed != NULL && 612 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 613 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 614 rxepaddr[nrx] = ed->bEndpointAddress; 615 nrx++; 616 } 617 } 618 DPRINTFN(DBG_INIT, ("%s: %s: found %zd bulk-out pipes\n", 619 device_xname(sc->sc_dev), __func__, ntx)); 620 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 621 aprint_error_dev(sc->sc_dev, 622 "%zd: invalid number of Tx bulk pipes\n", ntx); 623 return EIO; 624 } 625 sc->rx_npipe = nrx; 626 sc->tx_npipe = ntx; 627 628 /* Open bulk-in pipe at address 0x81. */ 629 for (i = 0; i < nrx; i++) { 630 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 631 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 632 if (error != 0) { 633 aprint_error_dev(sc->sc_dev, 634 "could not open Rx bulk pipe 0x%02x: %d\n", 635 rxepaddr[i], error); 636 goto fail; 637 } 638 } 639 640 /* Open bulk-out pipes (up to 3). */ 641 for (i = 0; i < ntx; i++) { 642 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 643 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 644 if (error != 0) { 645 aprint_error_dev(sc->sc_dev, 646 "could not open Tx bulk pipe 0x%02x: %d\n", 647 epaddr[i], error); 648 goto fail; 649 } 650 } 651 652 /* Map 802.11 access categories to USB pipes. */ 653 sc->ac2idx[WME_AC_BK] = 654 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 655 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 656 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 657 658 fail: 659 if (error != 0) 660 urtwn_close_pipes(sc); 661 return error; 662 } 663 664 static void 665 urtwn_close_pipes(struct urtwn_softc *sc) 666 { 667 struct usbd_pipe *pipe; 668 size_t i; 669 670 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 671 672 /* Close Rx pipes. */ 673 CTASSERT(sizeof(pipe) == sizeof(void *)); 674 for (i = 0; i < sc->rx_npipe; i++) { 675 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 676 if (pipe != NULL) { 677 usbd_close_pipe(pipe); 678 } 679 } 680 681 /* Close Tx pipes. */ 682 for (i = 0; i < sc->tx_npipe; i++) { 683 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 684 if (pipe != NULL) { 685 usbd_close_pipe(pipe); 686 } 687 } 688 } 689 690 static int 691 urtwn_alloc_rx_list(struct urtwn_softc *sc) 692 { 693 struct urtwn_rx_data *data; 694 size_t i; 695 int error = 0; 696 697 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 698 699 for (size_t j = 0; j < sc->rx_npipe; j++) { 700 TAILQ_INIT(&sc->rx_free_list[j]); 701 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 702 data = &sc->rx_data[j][i]; 703 704 data->sc = sc; /* Backpointer for callbacks. */ 705 706 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 707 USBD_SHORT_XFER_OK, 0, &data->xfer); 708 if (error) { 709 aprint_error_dev(sc->sc_dev, 710 "could not allocate xfer\n"); 711 break; 712 } 713 714 data->buf = usbd_get_buffer(data->xfer); 715 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 716 } 717 } 718 if (error != 0) 719 urtwn_free_rx_list(sc); 720 return error; 721 } 722 723 static void 724 urtwn_free_rx_list(struct urtwn_softc *sc) 725 { 726 struct usbd_xfer *xfer; 727 size_t i; 728 729 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 730 731 /* NB: Caller must abort pipe first. */ 732 for (size_t j = 0; j < sc->rx_npipe; j++) { 733 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 734 CTASSERT(sizeof(xfer) == sizeof(void *)); 735 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 736 if (xfer != NULL) 737 usbd_destroy_xfer(xfer); 738 } 739 } 740 } 741 742 static int 743 urtwn_alloc_tx_list(struct urtwn_softc *sc) 744 { 745 struct urtwn_tx_data *data; 746 size_t i; 747 int error = 0; 748 749 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 750 751 mutex_enter(&sc->sc_tx_mtx); 752 for (size_t j = 0; j < sc->tx_npipe; j++) { 753 TAILQ_INIT(&sc->tx_free_list[j]); 754 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 755 data = &sc->tx_data[j][i]; 756 757 data->sc = sc; /* Backpointer for callbacks. */ 758 data->pidx = j; 759 760 error = usbd_create_xfer(sc->tx_pipe[j], 761 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 762 &data->xfer); 763 if (error) { 764 aprint_error_dev(sc->sc_dev, 765 "could not allocate xfer\n"); 766 goto fail; 767 } 768 769 data->buf = usbd_get_buffer(data->xfer); 770 771 /* Append this Tx buffer to our free list. */ 772 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 773 } 774 } 775 mutex_exit(&sc->sc_tx_mtx); 776 return 0; 777 778 fail: 779 urtwn_free_tx_list(sc); 780 mutex_exit(&sc->sc_tx_mtx); 781 return error; 782 } 783 784 static void 785 urtwn_free_tx_list(struct urtwn_softc *sc) 786 { 787 struct usbd_xfer *xfer; 788 size_t i; 789 790 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 791 792 /* NB: Caller must abort pipe first. */ 793 for (size_t j = 0; j < sc->tx_npipe; j++) { 794 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 795 CTASSERT(sizeof(xfer) == sizeof(void *)); 796 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 797 if (xfer != NULL) 798 usbd_destroy_xfer(xfer); 799 } 800 } 801 } 802 803 static void 804 urtwn_task(void *arg) 805 { 806 struct urtwn_softc *sc = arg; 807 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 808 struct urtwn_host_cmd *cmd; 809 int s; 810 811 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 812 813 /* Process host commands. */ 814 s = splusb(); 815 mutex_spin_enter(&sc->sc_task_mtx); 816 while (ring->next != ring->cur) { 817 cmd = &ring->cmd[ring->next]; 818 mutex_spin_exit(&sc->sc_task_mtx); 819 splx(s); 820 /* Invoke callback with kernel lock held. */ 821 cmd->cb(sc, cmd->data); 822 s = splusb(); 823 mutex_spin_enter(&sc->sc_task_mtx); 824 ring->queued--; 825 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 826 } 827 mutex_spin_exit(&sc->sc_task_mtx); 828 wakeup(&sc->cmdq); 829 splx(s); 830 } 831 832 static void 833 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 834 void *arg, int len) 835 { 836 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 837 struct urtwn_host_cmd *cmd; 838 int s; 839 840 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 841 device_xname(sc->sc_dev), __func__, cb, arg, len)); 842 843 s = splusb(); 844 mutex_spin_enter(&sc->sc_task_mtx); 845 cmd = &ring->cmd[ring->cur]; 846 cmd->cb = cb; 847 KASSERT(len <= sizeof(cmd->data)); 848 memcpy(cmd->data, arg, len); 849 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 850 851 /* If there is no pending command already, schedule a task. */ 852 if (!sc->sc_dying && ++ring->queued == 1) { 853 mutex_spin_exit(&sc->sc_task_mtx); 854 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 855 } else 856 mutex_spin_exit(&sc->sc_task_mtx); 857 splx(s); 858 } 859 860 static void 861 urtwn_wait_async(struct urtwn_softc *sc) 862 { 863 864 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 865 866 /* Wait for all queued asynchronous commands to complete. */ 867 while (sc->cmdq.queued > 0) 868 tsleep(&sc->cmdq, 0, "endtask", 0); 869 } 870 871 static int 872 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 873 int len) 874 { 875 usb_device_request_t req; 876 usbd_status error; 877 878 KASSERT(mutex_owned(&sc->sc_write_mtx)); 879 880 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 881 req.bRequest = R92C_REQ_REGS; 882 USETW(req.wValue, addr); 883 USETW(req.wIndex, 0); 884 USETW(req.wLength, len); 885 error = usbd_do_request(sc->sc_udev, &req, buf); 886 if (error != USBD_NORMAL_COMPLETION) { 887 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 888 device_xname(sc->sc_dev), __func__, error, addr, len)); 889 } 890 return error; 891 } 892 893 static void 894 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 895 { 896 897 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 898 device_xname(sc->sc_dev), __func__, addr, val)); 899 900 urtwn_write_region_1(sc, addr, &val, 1); 901 } 902 903 static void 904 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 905 { 906 uint8_t buf[2]; 907 908 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 909 device_xname(sc->sc_dev), __func__, addr, val)); 910 911 buf[0] = (uint8_t)val; 912 buf[1] = (uint8_t)(val >> 8); 913 urtwn_write_region_1(sc, addr, buf, 2); 914 } 915 916 static void 917 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 918 { 919 uint8_t buf[4]; 920 921 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 922 device_xname(sc->sc_dev), __func__, addr, val)); 923 924 buf[0] = (uint8_t)val; 925 buf[1] = (uint8_t)(val >> 8); 926 buf[2] = (uint8_t)(val >> 16); 927 buf[3] = (uint8_t)(val >> 24); 928 urtwn_write_region_1(sc, addr, buf, 4); 929 } 930 931 static int 932 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 933 { 934 935 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 936 device_xname(sc->sc_dev), __func__, addr, len)); 937 938 return urtwn_write_region_1(sc, addr, buf, len); 939 } 940 941 static int 942 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 943 int len) 944 { 945 usb_device_request_t req; 946 usbd_status error; 947 948 req.bmRequestType = UT_READ_VENDOR_DEVICE; 949 req.bRequest = R92C_REQ_REGS; 950 USETW(req.wValue, addr); 951 USETW(req.wIndex, 0); 952 USETW(req.wLength, len); 953 error = usbd_do_request(sc->sc_udev, &req, buf); 954 if (error != USBD_NORMAL_COMPLETION) { 955 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 956 device_xname(sc->sc_dev), __func__, error, addr, len)); 957 } 958 return error; 959 } 960 961 static uint8_t 962 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 963 { 964 uint8_t val; 965 966 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 967 return 0xff; 968 969 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 970 device_xname(sc->sc_dev), __func__, addr, val)); 971 return val; 972 } 973 974 static uint16_t 975 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 976 { 977 uint8_t buf[2]; 978 uint16_t val; 979 980 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 981 return 0xffff; 982 983 val = LE_READ_2(&buf[0]); 984 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 985 device_xname(sc->sc_dev), __func__, addr, val)); 986 return val; 987 } 988 989 static uint32_t 990 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 991 { 992 uint8_t buf[4]; 993 uint32_t val; 994 995 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 996 return 0xffffffff; 997 998 val = LE_READ_4(&buf[0]); 999 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1000 device_xname(sc->sc_dev), __func__, addr, val)); 1001 return val; 1002 } 1003 1004 static int 1005 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1006 { 1007 struct r92c_fw_cmd cmd; 1008 uint8_t *cp; 1009 int fwcur; 1010 int ntries; 1011 1012 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1013 device_xname(sc->sc_dev), __func__, id, buf, len)); 1014 1015 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1016 1017 mutex_enter(&sc->sc_fwcmd_mtx); 1018 fwcur = sc->fwcur; 1019 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1020 mutex_exit(&sc->sc_fwcmd_mtx); 1021 1022 /* Wait for current FW box to be empty. */ 1023 for (ntries = 0; ntries < 100; ntries++) { 1024 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1025 break; 1026 DELAY(10); 1027 } 1028 if (ntries == 100) { 1029 aprint_error_dev(sc->sc_dev, 1030 "could not send firmware command %d\n", id); 1031 return ETIMEDOUT; 1032 } 1033 1034 memset(&cmd, 0, sizeof(cmd)); 1035 KASSERT(len <= sizeof(cmd.msg)); 1036 memcpy(cmd.msg, buf, len); 1037 1038 /* Write the first word last since that will trigger the FW. */ 1039 cp = (uint8_t *)&cmd; 1040 cmd.id = id; 1041 if (len >= 4) { 1042 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1043 cmd.id |= R92C_CMD_FLAG_EXT; 1044 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1045 &cp[1], 2); 1046 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1047 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1048 (cp[5] << 24)); 1049 } else { 1050 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1051 &cp[4], 2); 1052 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1053 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1054 (cp[3] << 24)); 1055 } 1056 } else { 1057 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1058 } 1059 1060 return 0; 1061 } 1062 1063 static __inline void 1064 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1065 { 1066 1067 sc->sc_rf_write(sc, chain, addr, val); 1068 } 1069 1070 static void 1071 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1072 uint32_t val) 1073 { 1074 1075 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1076 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1077 } 1078 1079 static void 1080 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1081 uint32_t val) 1082 { 1083 1084 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1085 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1086 } 1087 1088 static void 1089 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1090 uint32_t val) 1091 { 1092 1093 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1094 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1095 } 1096 1097 static uint32_t 1098 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1099 { 1100 uint32_t reg[R92C_MAX_CHAINS], val; 1101 1102 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1103 if (chain != 0) { 1104 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1105 } 1106 1107 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1108 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1109 DELAY(1000); 1110 1111 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1112 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1113 R92C_HSSI_PARAM2_READ_EDGE); 1114 DELAY(1000); 1115 1116 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1117 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1118 DELAY(1000); 1119 1120 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1121 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1122 } else { 1123 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1124 } 1125 return MS(val, R92C_LSSI_READBACK_DATA); 1126 } 1127 1128 static int 1129 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1130 { 1131 int ntries; 1132 1133 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1134 1135 urtwn_write_4(sc, R92C_LLT_INIT, 1136 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1137 SM(R92C_LLT_INIT_ADDR, addr) | 1138 SM(R92C_LLT_INIT_DATA, data)); 1139 /* Wait for write operation to complete. */ 1140 for (ntries = 0; ntries < 20; ntries++) { 1141 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1142 R92C_LLT_INIT_OP_NO_ACTIVE) { 1143 /* Done */ 1144 return 0; 1145 } 1146 DELAY(5); 1147 } 1148 return ETIMEDOUT; 1149 } 1150 1151 static uint8_t 1152 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1153 { 1154 uint32_t reg; 1155 int ntries; 1156 1157 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1158 1159 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1160 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1161 reg &= ~R92C_EFUSE_CTRL_VALID; 1162 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1163 1164 /* Wait for read operation to complete. */ 1165 for (ntries = 0; ntries < 100; ntries++) { 1166 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1167 if (reg & R92C_EFUSE_CTRL_VALID) { 1168 /* Done */ 1169 return MS(reg, R92C_EFUSE_CTRL_DATA); 1170 } 1171 DELAY(5); 1172 } 1173 aprint_error_dev(sc->sc_dev, 1174 "could not read efuse byte at address 0x%04x\n", addr); 1175 return 0xff; 1176 } 1177 1178 static void 1179 urtwn_efuse_read(struct urtwn_softc *sc) 1180 { 1181 uint8_t *rom = (uint8_t *)&sc->rom; 1182 uint32_t reg; 1183 uint16_t addr = 0; 1184 uint8_t off, msk; 1185 size_t i; 1186 1187 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1188 1189 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1190 1191 urtwn_efuse_switch_power(sc); 1192 1193 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1194 while (addr < 512) { 1195 reg = urtwn_efuse_read_1(sc, addr); 1196 if (reg == 0xff) 1197 break; 1198 addr++; 1199 off = reg >> 4; 1200 msk = reg & 0xf; 1201 for (i = 0; i < 4; i++) { 1202 if (msk & (1U << i)) 1203 continue; 1204 1205 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1206 addr++; 1207 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1208 addr++; 1209 } 1210 } 1211 #ifdef URTWN_DEBUG 1212 if (urtwn_debug & DBG_INIT) { 1213 /* Dump ROM content. */ 1214 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1215 for (i = 0; i < (int)sizeof(sc->rom); i++) 1216 printf(":%02x", rom[i]); 1217 printf("\n"); 1218 } 1219 #endif 1220 } 1221 1222 static void 1223 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1224 { 1225 uint32_t reg; 1226 1227 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1228 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1229 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1230 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1231 } 1232 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1233 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1234 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1235 reg | R92C_SYS_FUNC_EN_ELDR); 1236 } 1237 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1238 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1239 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1240 urtwn_write_2(sc, R92C_SYS_CLKR, 1241 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1242 } 1243 } 1244 1245 static int 1246 urtwn_read_chipid(struct urtwn_softc *sc) 1247 { 1248 uint32_t reg; 1249 1250 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1251 1252 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1253 ISSET(sc->chip, URTWN_CHIP_92EU)) 1254 return 0; 1255 1256 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1257 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1258 /* test chip, not supported */ 1259 return EIO; 1260 } 1261 if (reg & R92C_SYS_CFG_TYPE_92C) { 1262 sc->chip |= URTWN_CHIP_92C; 1263 /* Check if it is a castrated 8192C. */ 1264 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1265 R92C_HPON_FSM_CHIP_BONDING_ID) == 1266 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1267 sc->chip |= URTWN_CHIP_92C_1T2R; 1268 } 1269 } 1270 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1271 sc->chip |= URTWN_CHIP_UMC; 1272 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1273 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1274 } 1275 } 1276 return 0; 1277 } 1278 1279 #ifdef URTWN_DEBUG 1280 static void 1281 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1282 { 1283 1284 aprint_normal_dev(sc->sc_dev, 1285 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1286 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1287 1288 aprint_normal_dev(sc->sc_dev, 1289 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1290 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1291 1292 aprint_normal_dev(sc->sc_dev, 1293 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1294 rp->macaddr[0], rp->macaddr[1], 1295 rp->macaddr[2], rp->macaddr[3], 1296 rp->macaddr[4], rp->macaddr[5]); 1297 1298 aprint_normal_dev(sc->sc_dev, 1299 "string %s, subcustomer_id 0x%x\n", 1300 rp->string, rp->subcustomer_id); 1301 1302 aprint_normal_dev(sc->sc_dev, 1303 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1304 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1305 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1306 1307 aprint_normal_dev(sc->sc_dev, 1308 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1309 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1310 rp->ht40_1s_tx_pwr[0][2], 1311 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1312 rp->ht40_1s_tx_pwr[1][2]); 1313 1314 aprint_normal_dev(sc->sc_dev, 1315 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1316 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1317 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1318 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1319 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1320 1321 aprint_normal_dev(sc->sc_dev, 1322 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1323 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1324 rp->ht20_tx_pwr_diff[2] & 0xf, 1325 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1326 rp->ht20_tx_pwr_diff[2] >> 4); 1327 1328 aprint_normal_dev(sc->sc_dev, 1329 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1330 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1331 rp->ofdm_tx_pwr_diff[2] & 0xf, 1332 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1333 rp->ofdm_tx_pwr_diff[2] >> 4); 1334 1335 aprint_normal_dev(sc->sc_dev, 1336 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1337 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1338 rp->ht40_max_pwr[2] & 0xf, 1339 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1340 rp->ht40_max_pwr[2] >> 4); 1341 1342 aprint_normal_dev(sc->sc_dev, 1343 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1344 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1345 rp->ht20_max_pwr[2] & 0xf, 1346 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1347 rp->ht20_max_pwr[2] >> 4); 1348 1349 aprint_normal_dev(sc->sc_dev, 1350 "xtal_calib %d, tssi %d %d, thermal %d\n", 1351 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1352 1353 aprint_normal_dev(sc->sc_dev, 1354 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1355 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1356 1357 aprint_normal_dev(sc->sc_dev, 1358 "channnel_plan %d, version %d customer_id 0x%x\n", 1359 rp->channel_plan, rp->version, rp->curstomer_id); 1360 } 1361 #endif 1362 1363 static void 1364 urtwn_read_rom(struct urtwn_softc *sc) 1365 { 1366 struct ieee80211com *ic = &sc->sc_ic; 1367 struct r92c_rom *rom = &sc->rom; 1368 1369 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1370 1371 mutex_enter(&sc->sc_write_mtx); 1372 1373 /* Read full ROM image. */ 1374 urtwn_efuse_read(sc); 1375 #ifdef URTWN_DEBUG 1376 if (urtwn_debug & DBG_REG) 1377 urtwn_dump_rom(sc, rom); 1378 #endif 1379 1380 /* XXX Weird but this is what the vendor driver does. */ 1381 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1382 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1383 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1384 1385 DPRINTFN(DBG_INIT, 1386 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1387 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1388 sc->board_type, sc->regulatory)); 1389 1390 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1391 1392 sc->sc_rf_write = urtwn_r92c_rf_write; 1393 sc->sc_power_on = urtwn_r92c_power_on; 1394 sc->sc_dma_init = urtwn_r92c_dma_init; 1395 1396 mutex_exit(&sc->sc_write_mtx); 1397 } 1398 1399 static void 1400 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1401 { 1402 struct ieee80211com *ic = &sc->sc_ic; 1403 uint8_t *rom = sc->r88e_rom; 1404 uint32_t reg; 1405 uint16_t addr = 0; 1406 uint8_t off, msk, tmp; 1407 int i; 1408 1409 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1410 1411 mutex_enter(&sc->sc_write_mtx); 1412 1413 off = 0; 1414 urtwn_efuse_switch_power(sc); 1415 1416 /* Read full ROM image. */ 1417 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1418 while (addr < 4096) { 1419 reg = urtwn_efuse_read_1(sc, addr); 1420 if (reg == 0xff) 1421 break; 1422 addr++; 1423 if ((reg & 0x1f) == 0x0f) { 1424 tmp = (reg & 0xe0) >> 5; 1425 reg = urtwn_efuse_read_1(sc, addr); 1426 if ((reg & 0x0f) != 0x0f) 1427 off = ((reg & 0xf0) >> 1) | tmp; 1428 addr++; 1429 } else 1430 off = reg >> 4; 1431 msk = reg & 0xf; 1432 for (i = 0; i < 4; i++) { 1433 if (msk & (1 << i)) 1434 continue; 1435 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1436 addr++; 1437 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1438 addr++; 1439 } 1440 } 1441 #ifdef URTWN_DEBUG 1442 if (urtwn_debug & DBG_REG) { 1443 } 1444 #endif 1445 1446 addr = 0x10; 1447 for (i = 0; i < 6; i++) 1448 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1449 for (i = 0; i < 5; i++) 1450 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1451 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1452 if (sc->bw20_tx_pwr_diff & 0x08) 1453 sc->bw20_tx_pwr_diff |= 0xf0; 1454 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1455 if (sc->ofdm_tx_pwr_diff & 0x08) 1456 sc->ofdm_tx_pwr_diff |= 0xf0; 1457 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1458 1459 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1460 1461 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1462 sc->sc_power_on = urtwn_r92e_power_on; 1463 sc->sc_rf_write = urtwn_r92e_rf_write; 1464 } else { 1465 sc->sc_power_on = urtwn_r88e_power_on; 1466 sc->sc_rf_write = urtwn_r88e_rf_write; 1467 } 1468 sc->sc_dma_init = urtwn_r88e_dma_init; 1469 1470 mutex_exit(&sc->sc_write_mtx); 1471 } 1472 1473 static int 1474 urtwn_media_change(struct ifnet *ifp) 1475 { 1476 #ifdef URTWN_DEBUG 1477 struct urtwn_softc *sc = ifp->if_softc; 1478 #endif 1479 int error; 1480 1481 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1482 1483 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1484 return error; 1485 1486 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1487 (IFF_UP | IFF_RUNNING)) { 1488 urtwn_init(ifp); 1489 } 1490 return 0; 1491 } 1492 1493 /* 1494 * Initialize rate adaptation in firmware. 1495 */ 1496 static int 1497 urtwn_ra_init(struct urtwn_softc *sc) 1498 { 1499 static const uint8_t map[] = { 1500 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1501 }; 1502 struct ieee80211com *ic = &sc->sc_ic; 1503 struct ieee80211_node *ni = ic->ic_bss; 1504 struct ieee80211_rateset *rs = &ni->ni_rates; 1505 struct r92c_fw_cmd_macid_cfg cmd; 1506 uint32_t rates, basicrates; 1507 uint32_t mask, rrsr_mask, rrsr_rate; 1508 uint8_t mode; 1509 size_t maxrate, maxbasicrate, i, j; 1510 int error; 1511 1512 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1513 1514 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1515 1516 /* Get normal and basic rates mask. */ 1517 rates = basicrates = 1; 1518 maxrate = maxbasicrate = 0; 1519 for (i = 0; i < rs->rs_nrates; i++) { 1520 /* Convert 802.11 rate to HW rate index. */ 1521 for (j = 0; j < __arraycount(map); j++) { 1522 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1523 break; 1524 } 1525 } 1526 if (j == __arraycount(map)) { 1527 /* Unknown rate, skip. */ 1528 continue; 1529 } 1530 1531 rates |= 1U << j; 1532 if (j > maxrate) { 1533 maxrate = j; 1534 } 1535 1536 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1537 basicrates |= 1U << j; 1538 if (j > maxbasicrate) { 1539 maxbasicrate = j; 1540 } 1541 } 1542 } 1543 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1544 mode = R92C_RAID_11B; 1545 } else { 1546 mode = R92C_RAID_11BG; 1547 } 1548 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1549 "maxrate=%zx, maxbasicrate=%zx\n", 1550 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1551 maxrate, maxbasicrate)); 1552 1553 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1554 maxbasicrate |= R92C_RATE_SHORTGI; 1555 maxrate |= R92C_RATE_SHORTGI; 1556 } 1557 1558 /* Set rates mask for group addressed frames. */ 1559 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1560 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1561 cmd.macid |= URTWN_MACID_SHORTGI; 1562 1563 mask = (mode << 28) | basicrates; 1564 cmd.mask[0] = (uint8_t)mask; 1565 cmd.mask[1] = (uint8_t)(mask >> 8); 1566 cmd.mask[2] = (uint8_t)(mask >> 16); 1567 cmd.mask[3] = (uint8_t)(mask >> 24); 1568 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1569 if (error != 0) { 1570 aprint_error_dev(sc->sc_dev, 1571 "could not add broadcast station\n"); 1572 return error; 1573 } 1574 /* Set initial MRR rate. */ 1575 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1576 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1577 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1578 1579 /* Set rates mask for unicast frames. */ 1580 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1581 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1582 cmd.macid |= URTWN_MACID_SHORTGI; 1583 1584 mask = (mode << 28) | rates; 1585 cmd.mask[0] = (uint8_t)mask; 1586 cmd.mask[1] = (uint8_t)(mask >> 8); 1587 cmd.mask[2] = (uint8_t)(mask >> 16); 1588 cmd.mask[3] = (uint8_t)(mask >> 24); 1589 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1590 if (error != 0) { 1591 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1592 return error; 1593 } 1594 /* Set initial MRR rate. */ 1595 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1596 __func__, maxrate)); 1597 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1598 1599 rrsr_rate = ic->ic_fixed_rate; 1600 if (rrsr_rate == -1) 1601 rrsr_rate = 11; 1602 1603 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1604 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1605 1606 /* Indicate highest supported rate. */ 1607 ni->ni_txrate = rs->rs_nrates - 1; 1608 1609 return 0; 1610 } 1611 1612 static int 1613 urtwn_get_nettype(struct urtwn_softc *sc) 1614 { 1615 struct ieee80211com *ic = &sc->sc_ic; 1616 int type; 1617 1618 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1619 1620 switch (ic->ic_opmode) { 1621 case IEEE80211_M_STA: 1622 type = R92C_CR_NETTYPE_INFRA; 1623 break; 1624 1625 case IEEE80211_M_IBSS: 1626 type = R92C_CR_NETTYPE_ADHOC; 1627 break; 1628 1629 default: 1630 type = R92C_CR_NETTYPE_NOLINK; 1631 break; 1632 } 1633 1634 return type; 1635 } 1636 1637 static void 1638 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1639 { 1640 uint8_t reg; 1641 1642 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1643 __func__, type)); 1644 1645 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1646 1647 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1648 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1649 } 1650 1651 static void 1652 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1653 { 1654 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1655 uint64_t tsf; 1656 1657 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1658 1659 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1660 1661 /* Enable TSF synchronization. */ 1662 urtwn_write_1(sc, R92C_BCN_CTRL, 1663 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1664 1665 /* Correct TSF */ 1666 urtwn_write_1(sc, R92C_BCN_CTRL, 1667 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1668 1669 /* Set initial TSF. */ 1670 tsf = ni->ni_tstamp.tsf; 1671 tsf = le64toh(tsf); 1672 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1673 tsf -= IEEE80211_DUR_TU; 1674 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1675 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1676 1677 urtwn_write_1(sc, R92C_BCN_CTRL, 1678 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1679 } 1680 1681 static void 1682 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1683 { 1684 uint8_t reg; 1685 1686 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1687 __func__, led, on)); 1688 1689 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1690 1691 if (led == URTWN_LED_LINK) { 1692 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1693 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1694 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1695 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1696 (R92C_LEDCFG0_DIS << 1)); 1697 if (on) { 1698 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1699 R92E_LEDSON; 1700 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1701 } 1702 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1703 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1704 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1705 if (!on) { 1706 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1707 urtwn_write_1(sc, R92C_LEDCFG2, 1708 reg | R92C_LEDCFG0_DIS); 1709 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1710 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1711 reg & 0xfe); 1712 } 1713 } else { 1714 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1715 if (!on) { 1716 reg |= R92C_LEDCFG0_DIS; 1717 } 1718 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1719 } 1720 sc->ledlink = on; /* Save LED state. */ 1721 } 1722 } 1723 1724 static void 1725 urtwn_calib_to(void *arg) 1726 { 1727 struct urtwn_softc *sc = arg; 1728 1729 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1730 1731 if (sc->sc_dying) 1732 return; 1733 1734 /* Do it in a process context. */ 1735 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1736 } 1737 1738 /* ARGSUSED */ 1739 static void 1740 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1741 { 1742 struct r92c_fw_cmd_rssi cmd; 1743 struct r92e_fw_cmd_rssi cmde; 1744 1745 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1746 1747 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1748 goto restart_timer; 1749 1750 mutex_enter(&sc->sc_write_mtx); 1751 if (sc->avg_pwdb != -1) { 1752 /* Indicate Rx signal strength to FW for rate adaptation. */ 1753 memset(&cmd, 0, sizeof(cmd)); 1754 memset(&cmde, 0, sizeof(cmde)); 1755 cmd.macid = 0; /* BSS. */ 1756 cmde.macid = 0; /* BSS. */ 1757 cmd.pwdb = sc->avg_pwdb; 1758 cmde.pwdb = sc->avg_pwdb; 1759 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1760 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1761 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1762 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1763 sizeof(cmd)); 1764 } else { 1765 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1766 sizeof(cmde)); 1767 } 1768 } 1769 1770 /* Do temperature compensation. */ 1771 urtwn_temp_calib(sc); 1772 mutex_exit(&sc->sc_write_mtx); 1773 1774 restart_timer: 1775 if (!sc->sc_dying) { 1776 /* Restart calibration timer. */ 1777 callout_schedule(&sc->sc_calib_to, hz); 1778 } 1779 } 1780 1781 static void 1782 urtwn_next_scan(void *arg) 1783 { 1784 struct urtwn_softc *sc = arg; 1785 int s; 1786 1787 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1788 1789 if (sc->sc_dying) 1790 return; 1791 1792 s = splnet(); 1793 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1794 ieee80211_next_scan(&sc->sc_ic); 1795 splx(s); 1796 } 1797 1798 static void 1799 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1800 { 1801 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1802 ether_sprintf(ni->ni_macaddr))); 1803 /* start with lowest Tx rate */ 1804 ni->ni_txrate = 0; 1805 } 1806 1807 static int 1808 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1809 { 1810 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1811 struct urtwn_cmd_newstate cmd; 1812 1813 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1814 device_xname(sc->sc_dev), __func__, 1815 ieee80211_state_name[nstate], nstate, arg)); 1816 1817 callout_stop(&sc->sc_scan_to); 1818 callout_stop(&sc->sc_calib_to); 1819 1820 /* Do it in a process context. */ 1821 cmd.state = nstate; 1822 cmd.arg = arg; 1823 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1824 return 0; 1825 } 1826 1827 static void 1828 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1829 { 1830 struct urtwn_cmd_newstate *cmd = arg; 1831 struct ieee80211com *ic = &sc->sc_ic; 1832 struct ieee80211_node *ni; 1833 enum ieee80211_state ostate = ic->ic_state; 1834 enum ieee80211_state nstate = cmd->state; 1835 uint32_t reg; 1836 uint8_t sifs_time, msr; 1837 int s; 1838 1839 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1840 device_xname(sc->sc_dev), __func__, 1841 ieee80211_state_name[ostate], ostate, 1842 ieee80211_state_name[nstate], nstate)); 1843 1844 s = splnet(); 1845 mutex_enter(&sc->sc_write_mtx); 1846 1847 callout_stop(&sc->sc_scan_to); 1848 callout_stop(&sc->sc_calib_to); 1849 1850 switch (ostate) { 1851 case IEEE80211_S_INIT: 1852 break; 1853 1854 case IEEE80211_S_SCAN: 1855 if (nstate != IEEE80211_S_SCAN) { 1856 /* 1857 * End of scanning 1858 */ 1859 /* flush 4-AC Queue after site_survey */ 1860 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1861 1862 /* Allow Rx from our BSSID only. */ 1863 urtwn_write_4(sc, R92C_RCR, 1864 urtwn_read_4(sc, R92C_RCR) | 1865 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1866 } 1867 break; 1868 1869 case IEEE80211_S_AUTH: 1870 case IEEE80211_S_ASSOC: 1871 break; 1872 1873 case IEEE80211_S_RUN: 1874 /* Turn link LED off. */ 1875 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1876 1877 /* Set media status to 'No Link'. */ 1878 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1879 1880 /* Stop Rx of data frames. */ 1881 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1882 1883 /* Reset TSF. */ 1884 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1885 1886 /* Disable TSF synchronization. */ 1887 urtwn_write_1(sc, R92C_BCN_CTRL, 1888 urtwn_read_1(sc, R92C_BCN_CTRL) | 1889 R92C_BCN_CTRL_DIS_TSF_UDT0); 1890 1891 /* Back to 20MHz mode */ 1892 urtwn_set_chan(sc, ic->ic_curchan, 1893 IEEE80211_HTINFO_2NDCHAN_NONE); 1894 1895 if (ic->ic_opmode == IEEE80211_M_IBSS || 1896 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1897 /* Stop BCN */ 1898 urtwn_write_1(sc, R92C_BCN_CTRL, 1899 urtwn_read_1(sc, R92C_BCN_CTRL) & 1900 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1901 } 1902 1903 /* Reset EDCA parameters. */ 1904 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1905 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1906 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1907 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1908 1909 /* flush all cam entries */ 1910 urtwn_cam_init(sc); 1911 break; 1912 } 1913 1914 switch (nstate) { 1915 case IEEE80211_S_INIT: 1916 /* Turn link LED off. */ 1917 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1918 break; 1919 1920 case IEEE80211_S_SCAN: 1921 if (ostate != IEEE80211_S_SCAN) { 1922 /* 1923 * Begin of scanning 1924 */ 1925 1926 /* Set gain for scanning. */ 1927 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1928 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1929 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1930 1931 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1932 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1933 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1934 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1935 } 1936 1937 /* Set media status to 'No Link'. */ 1938 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1939 1940 /* Allow Rx from any BSSID. */ 1941 urtwn_write_4(sc, R92C_RCR, 1942 urtwn_read_4(sc, R92C_RCR) & 1943 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1944 1945 /* Stop Rx of data frames. */ 1946 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1947 1948 /* Disable update TSF */ 1949 urtwn_write_1(sc, R92C_BCN_CTRL, 1950 urtwn_read_1(sc, R92C_BCN_CTRL) | 1951 R92C_BCN_CTRL_DIS_TSF_UDT0); 1952 } 1953 1954 /* Make link LED blink during scan. */ 1955 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1956 1957 /* Pause AC Tx queues. */ 1958 urtwn_write_1(sc, R92C_TXPAUSE, 1959 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1960 1961 urtwn_set_chan(sc, ic->ic_curchan, 1962 IEEE80211_HTINFO_2NDCHAN_NONE); 1963 1964 /* Start periodic scan. */ 1965 if (!sc->sc_dying) 1966 callout_schedule(&sc->sc_scan_to, hz / 5); 1967 break; 1968 1969 case IEEE80211_S_AUTH: 1970 /* Set initial gain under link. */ 1971 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1972 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1973 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1974 1975 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1976 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1977 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1978 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1979 } 1980 1981 /* Set media status to 'No Link'. */ 1982 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1983 1984 /* Allow Rx from any BSSID. */ 1985 urtwn_write_4(sc, R92C_RCR, 1986 urtwn_read_4(sc, R92C_RCR) & 1987 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1988 1989 urtwn_set_chan(sc, ic->ic_curchan, 1990 IEEE80211_HTINFO_2NDCHAN_NONE); 1991 break; 1992 1993 case IEEE80211_S_ASSOC: 1994 break; 1995 1996 case IEEE80211_S_RUN: 1997 ni = ic->ic_bss; 1998 1999 /* XXX: Set 20MHz mode */ 2000 urtwn_set_chan(sc, ic->ic_curchan, 2001 IEEE80211_HTINFO_2NDCHAN_NONE); 2002 2003 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2004 /* Back to 20MHz mode */ 2005 urtwn_set_chan(sc, ic->ic_curchan, 2006 IEEE80211_HTINFO_2NDCHAN_NONE); 2007 2008 /* Set media status to 'No Link'. */ 2009 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2010 2011 /* Enable Rx of data frames. */ 2012 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2013 2014 /* Allow Rx from any BSSID. */ 2015 urtwn_write_4(sc, R92C_RCR, 2016 urtwn_read_4(sc, R92C_RCR) & 2017 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2018 2019 /* Accept Rx data/control/management frames */ 2020 urtwn_write_4(sc, R92C_RCR, 2021 urtwn_read_4(sc, R92C_RCR) | 2022 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2023 2024 /* Turn link LED on. */ 2025 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2026 break; 2027 } 2028 2029 /* Set media status to 'Associated'. */ 2030 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2031 2032 /* Set BSSID. */ 2033 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2034 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2035 2036 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2037 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2038 } else { 2039 /* 802.11b/g */ 2040 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2041 } 2042 2043 /* Enable Rx of data frames. */ 2044 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2045 2046 /* Set beacon interval. */ 2047 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2048 2049 msr = urtwn_read_1(sc, R92C_MSR); 2050 msr &= R92C_MSR_MASK; 2051 switch (ic->ic_opmode) { 2052 case IEEE80211_M_STA: 2053 /* Allow Rx from our BSSID only. */ 2054 urtwn_write_4(sc, R92C_RCR, 2055 urtwn_read_4(sc, R92C_RCR) | 2056 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2057 2058 /* Enable TSF synchronization. */ 2059 urtwn_tsf_sync_enable(sc); 2060 2061 msr |= R92C_MSR_INFRA; 2062 break; 2063 case IEEE80211_M_HOSTAP: 2064 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2065 2066 /* Allow Rx from any BSSID. */ 2067 urtwn_write_4(sc, R92C_RCR, 2068 urtwn_read_4(sc, R92C_RCR) & 2069 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2070 2071 /* Reset TSF timer to zero. */ 2072 reg = urtwn_read_4(sc, R92C_TCR); 2073 reg &= ~0x01; 2074 urtwn_write_4(sc, R92C_TCR, reg); 2075 reg |= 0x01; 2076 urtwn_write_4(sc, R92C_TCR, reg); 2077 2078 msr |= R92C_MSR_AP; 2079 break; 2080 default: 2081 msr |= R92C_MSR_ADHOC; 2082 break; 2083 } 2084 urtwn_write_1(sc, R92C_MSR, msr); 2085 2086 sifs_time = 10; 2087 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2088 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2089 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2090 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2091 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2092 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2093 2094 /* Intialize rate adaptation. */ 2095 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2096 ISSET(sc->chip, URTWN_CHIP_92EU)) 2097 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2098 else 2099 urtwn_ra_init(sc); 2100 2101 /* Turn link LED on. */ 2102 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2103 2104 /* Reset average RSSI. */ 2105 sc->avg_pwdb = -1; 2106 2107 /* Reset temperature calibration state machine. */ 2108 sc->thcal_state = 0; 2109 sc->thcal_lctemp = 0; 2110 2111 /* Start periodic calibration. */ 2112 if (!sc->sc_dying) 2113 callout_schedule(&sc->sc_calib_to, hz); 2114 break; 2115 } 2116 2117 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2118 2119 mutex_exit(&sc->sc_write_mtx); 2120 splx(s); 2121 } 2122 2123 static int 2124 urtwn_wme_update(struct ieee80211com *ic) 2125 { 2126 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2127 2128 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2129 2130 /* don't override default WME values if WME is not actually enabled */ 2131 if (!(ic->ic_flags & IEEE80211_F_WME)) 2132 return 0; 2133 2134 /* Do it in a process context. */ 2135 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2136 return 0; 2137 } 2138 2139 static void 2140 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2141 { 2142 static const uint16_t ac2reg[WME_NUM_AC] = { 2143 R92C_EDCA_BE_PARAM, 2144 R92C_EDCA_BK_PARAM, 2145 R92C_EDCA_VI_PARAM, 2146 R92C_EDCA_VO_PARAM 2147 }; 2148 struct ieee80211com *ic = &sc->sc_ic; 2149 const struct wmeParams *wmep; 2150 int ac, aifs, slottime; 2151 int s; 2152 2153 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2154 __func__)); 2155 2156 s = splnet(); 2157 mutex_enter(&sc->sc_write_mtx); 2158 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2159 for (ac = 0; ac < WME_NUM_AC; ac++) { 2160 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2161 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2162 aifs = wmep->wmep_aifsn * slottime + 10; 2163 urtwn_write_4(sc, ac2reg[ac], 2164 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2165 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2166 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2167 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2168 } 2169 mutex_exit(&sc->sc_write_mtx); 2170 splx(s); 2171 } 2172 2173 static void 2174 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2175 { 2176 int pwdb; 2177 2178 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2179 device_xname(sc->sc_dev), __func__, rate, rssi)); 2180 2181 /* Convert antenna signal to percentage. */ 2182 if (rssi <= -100 || rssi >= 20) 2183 pwdb = 0; 2184 else if (rssi >= 0) 2185 pwdb = 100; 2186 else 2187 pwdb = 100 + rssi; 2188 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2189 if (rate <= 3) { 2190 /* CCK gain is smaller than OFDM/MCS gain. */ 2191 pwdb += 6; 2192 if (pwdb > 100) 2193 pwdb = 100; 2194 if (pwdb <= 14) 2195 pwdb -= 4; 2196 else if (pwdb <= 26) 2197 pwdb -= 8; 2198 else if (pwdb <= 34) 2199 pwdb -= 6; 2200 else if (pwdb <= 42) 2201 pwdb -= 2; 2202 } 2203 } 2204 if (sc->avg_pwdb == -1) /* Init. */ 2205 sc->avg_pwdb = pwdb; 2206 else if (sc->avg_pwdb < pwdb) 2207 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2208 else 2209 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2210 2211 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2212 device_xname(sc->sc_dev), __func__, 2213 rate, rssi, pwdb, sc->avg_pwdb)); 2214 } 2215 2216 static int8_t 2217 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2218 { 2219 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2220 struct r92c_rx_phystat *phy; 2221 struct r92c_rx_cck *cck; 2222 uint8_t rpt; 2223 int8_t rssi; 2224 2225 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2226 __func__, rate)); 2227 2228 if (rate <= 3) { 2229 cck = (struct r92c_rx_cck *)physt; 2230 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2231 rpt = (cck->agc_rpt >> 5) & 0x3; 2232 rssi = (cck->agc_rpt & 0x1f) << 1; 2233 } else { 2234 rpt = (cck->agc_rpt >> 6) & 0x3; 2235 rssi = cck->agc_rpt & 0x3e; 2236 } 2237 rssi = cckoff[rpt] - rssi; 2238 } else { /* OFDM/HT. */ 2239 phy = (struct r92c_rx_phystat *)physt; 2240 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2241 } 2242 return rssi; 2243 } 2244 2245 static int8_t 2246 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2247 { 2248 struct r92c_rx_phystat *phy; 2249 struct r88e_rx_cck *cck; 2250 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2251 int8_t rssi; 2252 2253 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2254 __func__, rate)); 2255 2256 rssi = 0; 2257 if (rate <= 3) { 2258 cck = (struct r88e_rx_cck *)physt; 2259 cck_agc_rpt = cck->agc_rpt; 2260 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2261 vga_idx = cck_agc_rpt & 0x1f; 2262 switch (lna_idx) { 2263 case 7: 2264 if (vga_idx <= 27) 2265 rssi = -100 + 2* (27 - vga_idx); 2266 else 2267 rssi = -100; 2268 break; 2269 case 6: 2270 rssi = -48 + 2 * (2 - vga_idx); 2271 break; 2272 case 5: 2273 rssi = -42 + 2 * (7 - vga_idx); 2274 break; 2275 case 4: 2276 rssi = -36 + 2 * (7 - vga_idx); 2277 break; 2278 case 3: 2279 rssi = -24 + 2 * (7 - vga_idx); 2280 break; 2281 case 2: 2282 rssi = -12 + 2 * (5 - vga_idx); 2283 break; 2284 case 1: 2285 rssi = 8 - (2 * vga_idx); 2286 break; 2287 case 0: 2288 rssi = 14 - (2 * vga_idx); 2289 break; 2290 } 2291 rssi += 6; 2292 } else { /* OFDM/HT. */ 2293 phy = (struct r92c_rx_phystat *)physt; 2294 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2295 } 2296 return rssi; 2297 } 2298 2299 static void 2300 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2301 { 2302 struct ieee80211com *ic = &sc->sc_ic; 2303 struct ifnet *ifp = ic->ic_ifp; 2304 struct ieee80211_frame *wh; 2305 struct ieee80211_node *ni; 2306 struct r92c_rx_stat *stat; 2307 uint32_t rxdw0, rxdw3; 2308 struct mbuf *m; 2309 uint8_t rate; 2310 int8_t rssi = 0; 2311 int s, infosz; 2312 2313 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2314 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2315 2316 stat = (struct r92c_rx_stat *)buf; 2317 rxdw0 = le32toh(stat->rxdw0); 2318 rxdw3 = le32toh(stat->rxdw3); 2319 2320 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2321 /* 2322 * This should not happen since we setup our Rx filter 2323 * to not receive these frames. 2324 */ 2325 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2326 device_xname(sc->sc_dev), __func__)); 2327 ifp->if_ierrors++; 2328 return; 2329 } 2330 /* 2331 * XXX: This will drop most control packets. Do we really 2332 * want this in IEEE80211_M_MONITOR mode? 2333 */ 2334 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2335 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2336 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2337 device_xname(sc->sc_dev), __func__, pktlen)); 2338 ic->ic_stats.is_rx_tooshort++; 2339 ifp->if_ierrors++; 2340 return; 2341 } 2342 if (__predict_false(pktlen > MCLBYTES)) { 2343 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2344 device_xname(sc->sc_dev), __func__, pktlen)); 2345 ifp->if_ierrors++; 2346 return; 2347 } 2348 2349 rate = MS(rxdw3, R92C_RXDW3_RATE); 2350 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2351 2352 /* Get RSSI from PHY status descriptor if present. */ 2353 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2354 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2355 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2356 else 2357 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2358 /* Update our average RSSI. */ 2359 urtwn_update_avgrssi(sc, rate, rssi); 2360 } 2361 2362 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2363 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2364 2365 MGETHDR(m, M_DONTWAIT, MT_DATA); 2366 if (__predict_false(m == NULL)) { 2367 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2368 ic->ic_stats.is_rx_nobuf++; 2369 ifp->if_ierrors++; 2370 return; 2371 } 2372 if (pktlen > (int)MHLEN) { 2373 MCLGET(m, M_DONTWAIT); 2374 if (__predict_false(!(m->m_flags & M_EXT))) { 2375 aprint_error_dev(sc->sc_dev, 2376 "couldn't allocate rx mbuf cluster\n"); 2377 m_freem(m); 2378 ic->ic_stats.is_rx_nobuf++; 2379 ifp->if_ierrors++; 2380 return; 2381 } 2382 } 2383 2384 /* Finalize mbuf. */ 2385 m_set_rcvif(m, ifp); 2386 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2387 memcpy(mtod(m, uint8_t *), wh, pktlen); 2388 m->m_pkthdr.len = m->m_len = pktlen; 2389 2390 s = splnet(); 2391 if (__predict_false(sc->sc_drvbpf != NULL)) { 2392 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2393 2394 tap->wr_flags = 0; 2395 if (!(rxdw3 & R92C_RXDW3_HT)) { 2396 switch (rate) { 2397 /* CCK. */ 2398 case 0: tap->wr_rate = 2; break; 2399 case 1: tap->wr_rate = 4; break; 2400 case 2: tap->wr_rate = 11; break; 2401 case 3: tap->wr_rate = 22; break; 2402 /* OFDM. */ 2403 case 4: tap->wr_rate = 12; break; 2404 case 5: tap->wr_rate = 18; break; 2405 case 6: tap->wr_rate = 24; break; 2406 case 7: tap->wr_rate = 36; break; 2407 case 8: tap->wr_rate = 48; break; 2408 case 9: tap->wr_rate = 72; break; 2409 case 10: tap->wr_rate = 96; break; 2410 case 11: tap->wr_rate = 108; break; 2411 } 2412 } else if (rate >= 12) { /* MCS0~15. */ 2413 /* Bit 7 set means HT MCS instead of rate. */ 2414 tap->wr_rate = 0x80 | (rate - 12); 2415 } 2416 tap->wr_dbm_antsignal = rssi; 2417 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2418 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2419 2420 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2421 } 2422 2423 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2424 2425 /* push the frame up to the 802.11 stack */ 2426 ieee80211_input(ic, m, ni, rssi, 0); 2427 2428 /* Node is no longer needed. */ 2429 ieee80211_free_node(ni); 2430 2431 splx(s); 2432 } 2433 2434 static void 2435 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2436 { 2437 struct urtwn_rx_data *data = priv; 2438 struct urtwn_softc *sc = data->sc; 2439 struct r92c_rx_stat *stat; 2440 size_t pidx = data->pidx; 2441 uint32_t rxdw0; 2442 uint8_t *buf; 2443 int len, totlen, pktlen, infosz, npkts; 2444 2445 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2446 device_xname(sc->sc_dev), __func__, status)); 2447 2448 mutex_enter(&sc->sc_rx_mtx); 2449 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2450 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2451 /* Put this Rx buffer back to our free list. */ 2452 mutex_exit(&sc->sc_rx_mtx); 2453 2454 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2455 if (status == USBD_STALLED) 2456 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2457 else if (status != USBD_CANCELLED) 2458 goto resubmit; 2459 return; 2460 } 2461 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2462 2463 if (__predict_false(len < (int)sizeof(*stat))) { 2464 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2465 device_xname(sc->sc_dev), __func__, len)); 2466 goto resubmit; 2467 } 2468 buf = data->buf; 2469 2470 /* Get the number of encapsulated frames. */ 2471 stat = (struct r92c_rx_stat *)buf; 2472 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2473 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2474 device_xname(sc->sc_dev), __func__, npkts)); 2475 2476 /* Process all of them. */ 2477 while (npkts-- > 0) { 2478 if (__predict_false(len < (int)sizeof(*stat))) { 2479 DPRINTFN(DBG_RX, 2480 ("%s: %s: len(%d) is short than header\n", 2481 device_xname(sc->sc_dev), __func__, len)); 2482 break; 2483 } 2484 stat = (struct r92c_rx_stat *)buf; 2485 rxdw0 = le32toh(stat->rxdw0); 2486 2487 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2488 if (__predict_false(pktlen == 0)) { 2489 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2490 device_xname(sc->sc_dev), __func__)); 2491 break; 2492 } 2493 2494 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2495 2496 /* Make sure everything fits in xfer. */ 2497 totlen = sizeof(*stat) + infosz + pktlen; 2498 if (__predict_false(totlen > len)) { 2499 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2500 device_xname(sc->sc_dev), __func__, totlen, 2501 (int)sizeof(*stat), infosz, pktlen, len)); 2502 break; 2503 } 2504 2505 /* Process 802.11 frame. */ 2506 urtwn_rx_frame(sc, buf, pktlen); 2507 2508 /* Next chunk is 128-byte aligned. */ 2509 totlen = roundup2(totlen, 128); 2510 buf += totlen; 2511 len -= totlen; 2512 } 2513 2514 resubmit: 2515 /* Setup a new transfer. */ 2516 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2517 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2518 (void)usbd_transfer(xfer); 2519 } 2520 2521 static void 2522 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2523 { 2524 struct urtwn_tx_data *data = priv; 2525 struct urtwn_softc *sc = data->sc; 2526 struct ifnet *ifp = &sc->sc_if; 2527 size_t pidx = data->pidx; 2528 int s; 2529 2530 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2531 device_xname(sc->sc_dev), __func__, status)); 2532 2533 mutex_enter(&sc->sc_tx_mtx); 2534 /* Put this Tx buffer back to our free list. */ 2535 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2536 mutex_exit(&sc->sc_tx_mtx); 2537 2538 s = splnet(); 2539 sc->tx_timer = 0; 2540 ifp->if_flags &= ~IFF_OACTIVE; 2541 2542 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2543 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2544 if (status == USBD_STALLED) { 2545 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2546 usbd_clear_endpoint_stall_async(pipe); 2547 } 2548 printf("ERROR1\n"); 2549 ifp->if_oerrors++; 2550 } 2551 splx(s); 2552 return; 2553 } 2554 2555 ifp->if_opackets++; 2556 urtwn_start(ifp); 2557 splx(s); 2558 2559 } 2560 2561 static int 2562 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2563 struct urtwn_tx_data *data) 2564 { 2565 struct ieee80211com *ic = &sc->sc_ic; 2566 struct ieee80211_frame *wh; 2567 struct ieee80211_key *k = NULL; 2568 struct r92c_tx_desc *txd; 2569 size_t i, padsize, xferlen, txd_len; 2570 uint16_t seq, sum; 2571 uint8_t raid, type, tid; 2572 int s, hasqos, error; 2573 2574 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2575 2576 wh = mtod(m, struct ieee80211_frame *); 2577 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2578 txd_len = sizeof(*txd); 2579 2580 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2581 txd_len = 32; 2582 2583 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2584 k = ieee80211_crypto_encap(ic, ni, m); 2585 if (k == NULL) 2586 return ENOBUFS; 2587 2588 /* packet header may have moved, reset our local pointer */ 2589 wh = mtod(m, struct ieee80211_frame *); 2590 } 2591 2592 if (__predict_false(sc->sc_drvbpf != NULL)) { 2593 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2594 2595 tap->wt_flags = 0; 2596 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2597 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2598 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2599 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2600 2601 /* XXX: set tap->wt_rate? */ 2602 2603 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2604 } 2605 2606 /* non-qos data frames */ 2607 tid = R92C_TXDW1_QSEL_BE; 2608 if ((hasqos = ieee80211_has_qos(wh))) { 2609 /* data frames in 11n mode */ 2610 struct ieee80211_qosframe *qwh = (void *)wh; 2611 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2612 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2613 tid = R92C_TXDW1_QSEL_MGNT; 2614 } 2615 2616 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2617 padsize = 8; 2618 else 2619 padsize = 0; 2620 2621 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2622 padsize = 0; 2623 2624 /* Fill Tx descriptor. */ 2625 txd = (struct r92c_tx_desc *)data->buf; 2626 memset(txd, 0, txd_len + padsize); 2627 2628 txd->txdw0 |= htole32( 2629 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2630 SM(R92C_TXDW0_OFFSET, txd_len)); 2631 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2632 txd->txdw0 |= htole32( 2633 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2634 } 2635 2636 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2637 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2638 2639 /* fix pad field */ 2640 if (padsize > 0) { 2641 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2642 device_xname(sc->sc_dev), __func__, padsize)); 2643 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2644 } 2645 2646 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2647 type == IEEE80211_FC0_TYPE_DATA) { 2648 if (ic->ic_curmode == IEEE80211_MODE_11B) 2649 raid = R92C_RAID_11B; 2650 else 2651 raid = R92C_RAID_11BG; 2652 DPRINTFN(DBG_TX, 2653 ("%s: %s: data packet: tid=%d, raid=%d\n", 2654 device_xname(sc->sc_dev), __func__, tid, raid)); 2655 2656 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2657 txd->txdw1 |= htole32( 2658 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2659 SM(R92C_TXDW1_QSEL, tid) | 2660 SM(R92C_TXDW1_RAID, raid) | 2661 R92C_TXDW1_AGGBK); 2662 } else 2663 txd->txdw1 |= htole32( 2664 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2665 SM(R92C_TXDW1_QSEL, tid) | 2666 SM(R92C_TXDW1_RAID, raid) | 2667 R92C_TXDW1_AGGBK); 2668 2669 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2670 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2671 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2672 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2673 2674 if (hasqos) { 2675 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2676 } 2677 2678 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2679 /* for 11g */ 2680 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2681 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2682 R92C_TXDW4_HWRTSEN); 2683 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2684 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2685 R92C_TXDW4_HWRTSEN); 2686 } 2687 } 2688 /* Send RTS at OFDM24. */ 2689 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2690 txd->txdw5 |= htole32(0x0001ff00); 2691 /* Send data at OFDM54. */ 2692 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2693 txd->txdw5 |= htole32(0x13 & 0x3f); 2694 else 2695 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2696 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2697 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2698 device_xname(sc->sc_dev), __func__)); 2699 txd->txdw1 |= htole32( 2700 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2701 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2702 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2703 2704 /* Force CCK1. */ 2705 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2706 /* Use 1Mbps */ 2707 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2708 } else { 2709 /* broadcast or multicast packets */ 2710 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2711 device_xname(sc->sc_dev), __func__)); 2712 txd->txdw1 |= htole32( 2713 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2714 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2715 2716 /* Force CCK1. */ 2717 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2718 /* Use 1Mbps */ 2719 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2720 } 2721 /* Set sequence number */ 2722 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2723 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2724 txd->txdseq |= htole16(seq); 2725 2726 if (!hasqos) { 2727 /* Use HW sequence numbering for non-QoS frames. */ 2728 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2729 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2730 } 2731 } else { 2732 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2733 R92E_HWSEQ_SHIFT); 2734 if (!hasqos) { 2735 /* Use HW sequence numbering for non-QoS frames. */ 2736 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2737 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2738 } 2739 } 2740 2741 /* Compute Tx descriptor checksum. */ 2742 sum = 0; 2743 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2744 sum ^= ((uint16_t *)txd)[i]; 2745 txd->txdsum = sum; /* NB: already little endian. */ 2746 2747 xferlen = txd_len + m->m_pkthdr.len + padsize; 2748 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2749 2750 s = splnet(); 2751 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2752 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2753 urtwn_txeof); 2754 error = usbd_transfer(data->xfer); 2755 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2756 error != USBD_IN_PROGRESS)) { 2757 splx(s); 2758 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2759 device_xname(sc->sc_dev), __func__, error)); 2760 return error; 2761 } 2762 splx(s); 2763 return 0; 2764 } 2765 2766 struct urtwn_tx_data * 2767 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2768 { 2769 struct urtwn_tx_data *data = NULL; 2770 2771 mutex_enter(&sc->sc_tx_mtx); 2772 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2773 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2774 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2775 } 2776 mutex_exit(&sc->sc_tx_mtx); 2777 2778 return data; 2779 } 2780 2781 static void 2782 urtwn_start(struct ifnet *ifp) 2783 { 2784 struct urtwn_softc *sc = ifp->if_softc; 2785 struct ieee80211com *ic = &sc->sc_ic; 2786 struct urtwn_tx_data *data; 2787 struct ether_header *eh; 2788 struct ieee80211_node *ni; 2789 struct mbuf *m; 2790 2791 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2792 2793 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2794 return; 2795 2796 data = NULL; 2797 for (;;) { 2798 /* Send pending management frames first. */ 2799 IF_POLL(&ic->ic_mgtq, m); 2800 if (m != NULL) { 2801 /* Use AC_VO for management frames. */ 2802 2803 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2804 2805 if (data == NULL) { 2806 ifp->if_flags |= IFF_OACTIVE; 2807 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2808 device_xname(sc->sc_dev))); 2809 return; 2810 } 2811 IF_DEQUEUE(&ic->ic_mgtq, m); 2812 ni = M_GETCTX(m, struct ieee80211_node *); 2813 M_CLEARCTX(m); 2814 goto sendit; 2815 } 2816 if (ic->ic_state != IEEE80211_S_RUN) 2817 break; 2818 2819 /* Encapsulate and send data frames. */ 2820 IFQ_POLL(&ifp->if_snd, m); 2821 if (m == NULL) 2822 break; 2823 2824 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2825 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2826 uint8_t qid = WME_AC_BE; 2827 if (ieee80211_has_qos(wh)) { 2828 /* data frames in 11n mode */ 2829 struct ieee80211_qosframe *qwh = (void *)wh; 2830 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2831 qid = TID_TO_WME_AC(tid); 2832 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2833 qid = WME_AC_VO; 2834 } 2835 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2836 2837 if (data == NULL) { 2838 ifp->if_flags |= IFF_OACTIVE; 2839 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2840 device_xname(sc->sc_dev))); 2841 return; 2842 } 2843 IFQ_DEQUEUE(&ifp->if_snd, m); 2844 2845 if (m->m_len < (int)sizeof(*eh) && 2846 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2847 printf("ERROR6\n"); 2848 ifp->if_oerrors++; 2849 continue; 2850 } 2851 eh = mtod(m, struct ether_header *); 2852 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2853 if (ni == NULL) { 2854 m_freem(m); 2855 printf("ERROR5\n"); 2856 ifp->if_oerrors++; 2857 continue; 2858 } 2859 2860 bpf_mtap(ifp, m); 2861 2862 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2863 ieee80211_free_node(ni); 2864 printf("ERROR4\n"); 2865 ifp->if_oerrors++; 2866 continue; 2867 } 2868 sendit: 2869 bpf_mtap3(ic->ic_rawbpf, m); 2870 2871 if (urtwn_tx(sc, m, ni, data) != 0) { 2872 m_freem(m); 2873 ieee80211_free_node(ni); 2874 printf("ERROR3\n"); 2875 ifp->if_oerrors++; 2876 continue; 2877 } 2878 m_freem(m); 2879 ieee80211_free_node(ni); 2880 sc->tx_timer = 5; 2881 ifp->if_timer = 1; 2882 } 2883 } 2884 2885 static void 2886 urtwn_watchdog(struct ifnet *ifp) 2887 { 2888 struct urtwn_softc *sc = ifp->if_softc; 2889 2890 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2891 2892 ifp->if_timer = 0; 2893 2894 if (sc->tx_timer > 0) { 2895 if (--sc->tx_timer == 0) { 2896 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2897 /* urtwn_init(ifp); XXX needs a process context! */ 2898 printf("ERROR2\n"); 2899 ifp->if_oerrors++; 2900 return; 2901 } 2902 ifp->if_timer = 1; 2903 } 2904 ieee80211_watchdog(&sc->sc_ic); 2905 } 2906 2907 static int 2908 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2909 { 2910 struct urtwn_softc *sc = ifp->if_softc; 2911 struct ieee80211com *ic = &sc->sc_ic; 2912 int s, error = 0; 2913 2914 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2915 device_xname(sc->sc_dev), __func__, cmd, data)); 2916 2917 s = splnet(); 2918 2919 switch (cmd) { 2920 case SIOCSIFFLAGS: 2921 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2922 break; 2923 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2924 case IFF_UP | IFF_RUNNING: 2925 break; 2926 case IFF_UP: 2927 urtwn_init(ifp); 2928 break; 2929 case IFF_RUNNING: 2930 urtwn_stop(ifp, 1); 2931 break; 2932 case 0: 2933 break; 2934 } 2935 break; 2936 2937 case SIOCADDMULTI: 2938 case SIOCDELMULTI: 2939 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2940 /* setup multicast filter, etc */ 2941 error = 0; 2942 } 2943 break; 2944 2945 default: 2946 error = ieee80211_ioctl(ic, cmd, data); 2947 break; 2948 } 2949 if (error == ENETRESET) { 2950 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2951 (IFF_UP | IFF_RUNNING) && 2952 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2953 urtwn_init(ifp); 2954 } 2955 error = 0; 2956 } 2957 2958 splx(s); 2959 2960 return error; 2961 } 2962 2963 static __inline int 2964 urtwn_power_on(struct urtwn_softc *sc) 2965 { 2966 2967 return sc->sc_power_on(sc); 2968 } 2969 2970 static int 2971 urtwn_r92c_power_on(struct urtwn_softc *sc) 2972 { 2973 uint32_t reg; 2974 int ntries; 2975 2976 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2977 2978 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2979 2980 /* Wait for autoload done bit. */ 2981 for (ntries = 0; ntries < 1000; ntries++) { 2982 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2983 break; 2984 DELAY(5); 2985 } 2986 if (ntries == 1000) { 2987 aprint_error_dev(sc->sc_dev, 2988 "timeout waiting for chip autoload\n"); 2989 return ETIMEDOUT; 2990 } 2991 2992 /* Unlock ISO/CLK/Power control register. */ 2993 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2994 /* Move SPS into PWM mode. */ 2995 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2996 DELAY(5); 2997 2998 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2999 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3000 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3001 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3002 DELAY(100); 3003 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3004 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3005 ~R92C_SYS_ISO_CTRL_MD2PP); 3006 } 3007 3008 /* Auto enable WLAN. */ 3009 urtwn_write_2(sc, R92C_APS_FSMCO, 3010 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3011 for (ntries = 0; ntries < 1000; ntries++) { 3012 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3013 R92C_APS_FSMCO_APFM_ONMAC)) 3014 break; 3015 DELAY(100); 3016 } 3017 if (ntries == 1000) { 3018 aprint_error_dev(sc->sc_dev, 3019 "timeout waiting for MAC auto ON\n"); 3020 return ETIMEDOUT; 3021 } 3022 3023 /* Enable radio, GPIO and LED functions. */ 3024 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3025 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3026 urtwn_write_2(sc, R92C_APS_FSMCO, 3027 R92C_APS_FSMCO_AFSM_HSUS | 3028 R92C_APS_FSMCO_PDN_EN | 3029 R92C_APS_FSMCO_PFM_ALDN); 3030 3031 /* Release RF digital isolation. */ 3032 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3033 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3034 3035 /* Initialize MAC. */ 3036 urtwn_write_1(sc, R92C_APSD_CTRL, 3037 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3038 for (ntries = 0; ntries < 200; ntries++) { 3039 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3040 R92C_APSD_CTRL_OFF_STATUS)) 3041 break; 3042 DELAY(5); 3043 } 3044 if (ntries == 200) { 3045 aprint_error_dev(sc->sc_dev, 3046 "timeout waiting for MAC initialization\n"); 3047 return ETIMEDOUT; 3048 } 3049 3050 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3051 reg = urtwn_read_2(sc, R92C_CR); 3052 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3053 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3054 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3055 R92C_CR_ENSEC; 3056 urtwn_write_2(sc, R92C_CR, reg); 3057 3058 urtwn_write_1(sc, 0xfe10, 0x19); 3059 return 0; 3060 } 3061 3062 static int 3063 urtwn_r92e_power_on(struct urtwn_softc *sc) 3064 { 3065 uint32_t reg; 3066 uint32_t val; 3067 int ntries; 3068 3069 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3070 3071 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3072 3073 /* Enable radio, GPIO and LED functions. */ 3074 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3075 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3076 urtwn_write_2(sc, R92C_APS_FSMCO, 3077 R92C_APS_FSMCO_AFSM_HSUS | 3078 R92C_APS_FSMCO_PDN_EN | 3079 R92C_APS_FSMCO_PFM_ALDN); 3080 3081 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3082 /* LDO. */ 3083 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3084 } 3085 else { 3086 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3087 R92C_SYS_SWR_CTRL2) & 0xffff); 3088 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3089 } 3090 3091 for (ntries = 0; ntries < 2; ntries++) { 3092 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3093 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3094 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3095 R92C_AFE_CTRL4)); 3096 } 3097 3098 /* Reset BB. */ 3099 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3100 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3101 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3102 3103 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3104 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3105 3106 /* Disable HWPDN. */ 3107 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3108 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3109 3110 /* Disable WL suspend. */ 3111 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3112 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3113 R92C_APS_FSMCO_AFSM_HSUS)); 3114 3115 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3116 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3117 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3118 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3119 for (ntries = 0; ntries < 10000; ntries++) { 3120 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3121 R92C_APS_FSMCO_APFM_ONMAC; 3122 if (val == 0x0) 3123 break; 3124 DELAY(10); 3125 } 3126 if (ntries == 10000) { 3127 aprint_error_dev(sc->sc_dev, 3128 "timeout waiting for chip power up\n"); 3129 return ETIMEDOUT; 3130 } 3131 3132 urtwn_write_2(sc, R92C_CR, 0x00); 3133 reg = urtwn_read_2(sc, R92C_CR); 3134 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3135 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3136 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3137 urtwn_write_2(sc, R92C_CR, reg); 3138 3139 return 0; 3140 } 3141 3142 static int 3143 urtwn_r88e_power_on(struct urtwn_softc *sc) 3144 { 3145 uint32_t reg; 3146 uint8_t val; 3147 int ntries; 3148 3149 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3150 3151 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3152 3153 /* Wait for power ready bit. */ 3154 for (ntries = 0; ntries < 5000; ntries++) { 3155 val = urtwn_read_1(sc, 0x6) & 0x2; 3156 if (val == 0x2) 3157 break; 3158 DELAY(10); 3159 } 3160 if (ntries == 5000) { 3161 aprint_error_dev(sc->sc_dev, 3162 "timeout waiting for chip power up\n"); 3163 return ETIMEDOUT; 3164 } 3165 3166 /* Reset BB. */ 3167 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3168 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3169 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3170 3171 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3172 3173 /* Disable HWPDN. */ 3174 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3175 3176 /* Disable WL suspend. */ 3177 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3178 3179 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3180 for (ntries = 0; ntries < 5000; ntries++) { 3181 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3182 break; 3183 DELAY(10); 3184 } 3185 if (ntries == 5000) 3186 return ETIMEDOUT; 3187 3188 /* Enable LDO normal mode. */ 3189 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3190 3191 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3192 urtwn_write_2(sc, R92C_CR, 0); 3193 reg = urtwn_read_2(sc, R92C_CR); 3194 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3195 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3196 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3197 urtwn_write_2(sc, R92C_CR, reg); 3198 3199 return 0; 3200 } 3201 3202 static int 3203 urtwn_llt_init(struct urtwn_softc *sc) 3204 { 3205 size_t i, page_count, pktbuf_count; 3206 uint32_t val; 3207 int error; 3208 3209 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3210 3211 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3212 3213 if (sc->chip & URTWN_CHIP_88E) 3214 page_count = R88E_TX_PAGE_COUNT; 3215 else if (sc->chip & URTWN_CHIP_92EU) 3216 page_count = R92E_TX_PAGE_COUNT; 3217 else 3218 page_count = R92C_TX_PAGE_COUNT; 3219 if (sc->chip & URTWN_CHIP_88E) 3220 pktbuf_count = R88E_TXPKTBUF_COUNT; 3221 else if (sc->chip & URTWN_CHIP_92EU) 3222 pktbuf_count = R88E_TXPKTBUF_COUNT; 3223 else 3224 pktbuf_count = R92C_TXPKTBUF_COUNT; 3225 3226 if (sc->chip & URTWN_CHIP_92EU) { 3227 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3228 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3229 DELAY(100); 3230 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3231 if (val & R92E_AUTO_LLT_EN) 3232 return EIO; 3233 return 0; 3234 } 3235 3236 /* Reserve pages [0; page_count]. */ 3237 for (i = 0; i < page_count; i++) { 3238 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3239 return error; 3240 } 3241 /* NB: 0xff indicates end-of-list. */ 3242 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3243 return error; 3244 /* 3245 * Use pages [page_count + 1; pktbuf_count - 1] 3246 * as ring buffer. 3247 */ 3248 for (++i; i < pktbuf_count - 1; i++) { 3249 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3250 return error; 3251 } 3252 /* Make the last page point to the beginning of the ring buffer. */ 3253 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3254 return error; 3255 } 3256 3257 static void 3258 urtwn_fw_reset(struct urtwn_softc *sc) 3259 { 3260 uint16_t reg; 3261 int ntries; 3262 3263 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3264 3265 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3266 3267 /* Tell 8051 to reset itself. */ 3268 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3269 3270 /* Wait until 8051 resets by itself. */ 3271 for (ntries = 0; ntries < 100; ntries++) { 3272 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3273 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3274 return; 3275 DELAY(50); 3276 } 3277 /* Force 8051 reset. */ 3278 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3279 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3280 } 3281 3282 static void 3283 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3284 { 3285 uint16_t reg; 3286 3287 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3288 3289 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3290 3291 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3292 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3293 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3294 } 3295 DELAY(50); 3296 3297 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3298 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3299 DELAY(50); 3300 3301 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3302 DELAY(50); 3303 3304 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3305 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3306 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3307 } 3308 DELAY(50); 3309 3310 } 3311 3312 static int 3313 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3314 { 3315 uint32_t reg; 3316 int off, mlen, error = 0; 3317 3318 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3319 device_xname(sc->sc_dev), __func__, page, buf, len)); 3320 3321 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3322 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3323 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3324 3325 off = R92C_FW_START_ADDR; 3326 while (len > 0) { 3327 if (len > 196) 3328 mlen = 196; 3329 else if (len > 4) 3330 mlen = 4; 3331 else 3332 mlen = 1; 3333 error = urtwn_write_region(sc, off, buf, mlen); 3334 if (error != 0) 3335 break; 3336 off += mlen; 3337 buf += mlen; 3338 len -= mlen; 3339 } 3340 return error; 3341 } 3342 3343 static int 3344 urtwn_load_firmware(struct urtwn_softc *sc) 3345 { 3346 firmware_handle_t fwh; 3347 const struct r92c_fw_hdr *hdr; 3348 const char *name; 3349 u_char *fw, *ptr; 3350 size_t len; 3351 uint32_t reg; 3352 int mlen, ntries, page, error; 3353 3354 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3355 3356 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3357 3358 /* Read firmware image from the filesystem. */ 3359 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3360 name = "rtl8188eufw.bin"; 3361 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3362 name = "rtl8192eefw.bin"; 3363 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3364 URTWN_CHIP_UMC_A_CUT) 3365 name = "rtl8192cfwU.bin"; 3366 else 3367 name = "rtl8192cfw.bin"; 3368 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3369 aprint_error_dev(sc->sc_dev, 3370 "failed load firmware of file %s (error %d)\n", name, 3371 error); 3372 return error; 3373 } 3374 const size_t fwlen = len = firmware_get_size(fwh); 3375 fw = firmware_malloc(len); 3376 if (fw == NULL) { 3377 aprint_error_dev(sc->sc_dev, 3378 "failed to allocate firmware memory\n"); 3379 firmware_close(fwh); 3380 return ENOMEM; 3381 } 3382 error = firmware_read(fwh, 0, fw, len); 3383 firmware_close(fwh); 3384 if (error != 0) { 3385 aprint_error_dev(sc->sc_dev, 3386 "failed to read firmware (error %d)\n", error); 3387 firmware_free(fw, fwlen); 3388 return error; 3389 } 3390 3391 len = fwlen; 3392 ptr = fw; 3393 hdr = (const struct r92c_fw_hdr *)ptr; 3394 /* Check if there is a valid FW header and skip it. */ 3395 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3396 (le16toh(hdr->signature) >> 4) == 0x88e || 3397 (le16toh(hdr->signature) >> 4) == 0x92e || 3398 (le16toh(hdr->signature) >> 4) == 0x92c) { 3399 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3400 device_xname(sc->sc_dev), __func__, 3401 le16toh(hdr->version), le16toh(hdr->subversion), 3402 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3403 ptr += sizeof(*hdr); 3404 len -= sizeof(*hdr); 3405 } 3406 3407 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3408 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3409 ISSET(sc->chip, URTWN_CHIP_92EU)) 3410 urtwn_r88e_fw_reset(sc); 3411 else 3412 urtwn_fw_reset(sc); 3413 } 3414 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3415 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3416 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3417 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3418 R92C_SYS_FUNC_EN_CPUEN); 3419 } 3420 3421 /* download enabled */ 3422 urtwn_write_1(sc, R92C_MCUFWDL, 3423 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3424 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3425 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3426 3427 /* Reset the FWDL checksum. */ 3428 urtwn_write_1(sc, R92C_MCUFWDL, 3429 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3430 3431 DELAY(50); 3432 /* download firmware */ 3433 for (page = 0; len > 0; page++) { 3434 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3435 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3436 if (error != 0) { 3437 aprint_error_dev(sc->sc_dev, 3438 "could not load firmware page %d\n", page); 3439 goto fail; 3440 } 3441 ptr += mlen; 3442 len -= mlen; 3443 } 3444 3445 /* download disable */ 3446 urtwn_write_1(sc, R92C_MCUFWDL, 3447 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3448 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3449 3450 /* Wait for checksum report. */ 3451 for (ntries = 0; ntries < 1000; ntries++) { 3452 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3453 break; 3454 DELAY(5); 3455 } 3456 if (ntries == 1000) { 3457 aprint_error_dev(sc->sc_dev, 3458 "timeout waiting for checksum report\n"); 3459 error = ETIMEDOUT; 3460 goto fail; 3461 } 3462 3463 /* Wait for firmware readiness. */ 3464 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3465 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3466 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3467 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3468 ISSET(sc->chip, URTWN_CHIP_92EU)) 3469 urtwn_r88e_fw_reset(sc); 3470 for (ntries = 0; ntries < 1000; ntries++) { 3471 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3472 break; 3473 DELAY(5); 3474 } 3475 if (ntries == 1000) { 3476 aprint_error_dev(sc->sc_dev, 3477 "timeout waiting for firmware readiness\n"); 3478 error = ETIMEDOUT; 3479 goto fail; 3480 } 3481 fail: 3482 firmware_free(fw, fwlen); 3483 return error; 3484 } 3485 3486 static __inline int 3487 urtwn_dma_init(struct urtwn_softc *sc) 3488 { 3489 3490 return sc->sc_dma_init(sc); 3491 } 3492 3493 static int 3494 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3495 { 3496 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3497 uint32_t reg; 3498 int error; 3499 3500 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3501 3502 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3503 3504 /* Initialize LLT table. */ 3505 error = urtwn_llt_init(sc); 3506 if (error != 0) 3507 return error; 3508 3509 /* Get Tx queues to USB endpoints mapping. */ 3510 hashq = hasnq = haslq = 0; 3511 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3512 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3513 device_xname(sc->sc_dev), __func__, reg)); 3514 if (MS(reg, R92C_USB_EP_HQ) != 0) 3515 hashq = 1; 3516 if (MS(reg, R92C_USB_EP_NQ) != 0) 3517 hasnq = 1; 3518 if (MS(reg, R92C_USB_EP_LQ) != 0) 3519 haslq = 1; 3520 nqueues = hashq + hasnq + haslq; 3521 if (nqueues == 0) 3522 return EIO; 3523 /* Get the number of pages for each queue. */ 3524 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3525 /* The remaining pages are assigned to the high priority queue. */ 3526 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3527 3528 /* Set number of pages for normal priority queue. */ 3529 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3530 urtwn_write_4(sc, R92C_RQPN, 3531 /* Set number of pages for public queue. */ 3532 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3533 /* Set number of pages for high priority queue. */ 3534 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3535 /* Set number of pages for low priority queue. */ 3536 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3537 /* Load values. */ 3538 R92C_RQPN_LD); 3539 3540 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3541 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3542 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3543 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3544 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3545 3546 /* Set queue to USB pipe mapping. */ 3547 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3548 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3549 if (nqueues == 1) { 3550 if (hashq) { 3551 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3552 } else if (hasnq) { 3553 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3554 } else { 3555 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3556 } 3557 } else if (nqueues == 2) { 3558 /* All 2-endpoints configs have a high priority queue. */ 3559 if (!hashq) { 3560 return EIO; 3561 } 3562 if (hasnq) { 3563 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3564 } else { 3565 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3566 } 3567 } else { 3568 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3569 } 3570 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3571 3572 /* Set Tx/Rx transfer page boundary. */ 3573 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3574 3575 /* Set Tx/Rx transfer page size. */ 3576 urtwn_write_1(sc, R92C_PBP, 3577 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3578 return 0; 3579 } 3580 3581 static int 3582 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3583 { 3584 usb_interface_descriptor_t *id; 3585 uint32_t reg; 3586 int nqueues; 3587 int error; 3588 3589 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3590 3591 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3592 3593 /* Initialize LLT table. */ 3594 error = urtwn_llt_init(sc); 3595 if (error != 0) 3596 return error; 3597 3598 /* Get Tx queues to USB endpoints mapping. */ 3599 id = usbd_get_interface_descriptor(sc->sc_iface); 3600 nqueues = id->bNumEndpoints - 1; 3601 if (nqueues == 0) 3602 return EIO; 3603 3604 /* Set number of pages for normal priority queue. */ 3605 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3606 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3607 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3608 3609 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3610 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3611 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3612 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3613 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3614 3615 /* Set queue to USB pipe mapping. */ 3616 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3617 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3618 if (nqueues == 1) 3619 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3620 else if (nqueues == 2) 3621 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3622 else 3623 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3624 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3625 3626 /* Set Tx/Rx transfer page boundary. */ 3627 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3628 3629 /* Set Tx/Rx transfer page size. */ 3630 urtwn_write_1(sc, R92C_PBP, 3631 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3632 3633 return 0; 3634 } 3635 3636 static void 3637 urtwn_mac_init(struct urtwn_softc *sc) 3638 { 3639 size_t i; 3640 3641 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3642 3643 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3644 3645 /* Write MAC initialization values. */ 3646 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3647 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3648 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3649 rtl8188eu_mac[i].val); 3650 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3651 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3652 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3653 rtl8192eu_mac[i].val); 3654 } else { 3655 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3656 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3657 rtl8192cu_mac[i].val); 3658 } 3659 } 3660 3661 static void 3662 urtwn_bb_init(struct urtwn_softc *sc) 3663 { 3664 const struct urtwn_bb_prog *prog; 3665 uint32_t reg; 3666 uint8_t crystalcap; 3667 size_t i; 3668 3669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3670 3671 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3672 3673 /* Enable BB and RF. */ 3674 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3675 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3676 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3677 R92C_SYS_FUNC_EN_DIO_RF); 3678 3679 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3680 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3681 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3682 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3683 } 3684 3685 urtwn_write_1(sc, R92C_RF_CTRL, 3686 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3687 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3688 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3689 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3690 3691 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3692 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3693 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3694 urtwn_write_1(sc, 0x15, 0xe9); 3695 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3696 } 3697 3698 /* Select BB programming based on board type. */ 3699 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3700 prog = &rtl8188eu_bb_prog; 3701 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3702 prog = &rtl8192eu_bb_prog; 3703 else if (!(sc->chip & URTWN_CHIP_92C)) { 3704 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3705 prog = &rtl8188ce_bb_prog; 3706 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3707 prog = &rtl8188ru_bb_prog; 3708 } else { 3709 prog = &rtl8188cu_bb_prog; 3710 } 3711 } else { 3712 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3713 prog = &rtl8192ce_bb_prog; 3714 } else { 3715 prog = &rtl8192cu_bb_prog; 3716 } 3717 } 3718 /* Write BB initialization values. */ 3719 for (i = 0; i < prog->count; i++) { 3720 /* additional delay depend on registers */ 3721 switch (prog->regs[i]) { 3722 case 0xfe: 3723 urtwn_delay_ms(sc, 50); 3724 break; 3725 case 0xfd: 3726 urtwn_delay_ms(sc, 5); 3727 break; 3728 case 0xfc: 3729 urtwn_delay_ms(sc, 1); 3730 break; 3731 case 0xfb: 3732 DELAY(50); 3733 break; 3734 case 0xfa: 3735 DELAY(5); 3736 break; 3737 case 0xf9: 3738 DELAY(1); 3739 break; 3740 } 3741 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3742 DELAY(1); 3743 } 3744 3745 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3746 /* 8192C 1T only configuration. */ 3747 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3748 reg = (reg & ~0x00000003) | 0x2; 3749 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3750 3751 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3752 reg = (reg & ~0x00300033) | 0x00200022; 3753 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3754 3755 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3756 reg = (reg & ~0xff000000) | (0x45 << 24); 3757 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3758 3759 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3760 reg = (reg & ~0x000000ff) | 0x23; 3761 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3762 3763 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3764 reg = (reg & ~0x00000030) | (1 << 4); 3765 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3766 3767 reg = urtwn_bb_read(sc, 0xe74); 3768 reg = (reg & ~0x0c000000) | (2 << 26); 3769 urtwn_bb_write(sc, 0xe74, reg); 3770 reg = urtwn_bb_read(sc, 0xe78); 3771 reg = (reg & ~0x0c000000) | (2 << 26); 3772 urtwn_bb_write(sc, 0xe78, reg); 3773 reg = urtwn_bb_read(sc, 0xe7c); 3774 reg = (reg & ~0x0c000000) | (2 << 26); 3775 urtwn_bb_write(sc, 0xe7c, reg); 3776 reg = urtwn_bb_read(sc, 0xe80); 3777 reg = (reg & ~0x0c000000) | (2 << 26); 3778 urtwn_bb_write(sc, 0xe80, reg); 3779 reg = urtwn_bb_read(sc, 0xe88); 3780 reg = (reg & ~0x0c000000) | (2 << 26); 3781 urtwn_bb_write(sc, 0xe88, reg); 3782 } 3783 3784 /* Write AGC values. */ 3785 for (i = 0; i < prog->agccount; i++) { 3786 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3787 DELAY(1); 3788 } 3789 3790 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3791 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3792 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3793 DELAY(1); 3794 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3795 DELAY(1); 3796 3797 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3798 urtwn_write_2(sc, R92C_AFE_CTRL3, urtwn_read_2(sc, 3799 R92C_AFE_CTRL3)); 3800 } 3801 3802 crystalcap = sc->r88e_rom[0xb9]; 3803 if (crystalcap == 0xff) 3804 crystalcap = 0x20; 3805 crystalcap &= 0x3f; 3806 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3807 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3808 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3809 crystalcap | crystalcap << 6)); 3810 } else { 3811 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3812 R92C_HSSI_PARAM2_CCK_HIPWR) { 3813 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3814 } 3815 } 3816 } 3817 3818 static void 3819 urtwn_rf_init(struct urtwn_softc *sc) 3820 { 3821 const struct urtwn_rf_prog *prog; 3822 uint32_t reg, mask, saved; 3823 size_t i, j, idx; 3824 3825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3826 3827 /* Select RF programming based on board type. */ 3828 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3829 prog = rtl8188eu_rf_prog; 3830 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3831 prog = rtl8192eu_rf_prog; 3832 else if (!(sc->chip & URTWN_CHIP_92C)) { 3833 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3834 prog = rtl8188ce_rf_prog; 3835 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3836 prog = rtl8188ru_rf_prog; 3837 } else { 3838 prog = rtl8188cu_rf_prog; 3839 } 3840 } else { 3841 prog = rtl8192ce_rf_prog; 3842 } 3843 3844 for (i = 0; i < sc->nrxchains; i++) { 3845 /* Save RF_ENV control type. */ 3846 idx = i / 2; 3847 mask = 0xffffU << ((i % 2) * 16); 3848 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3849 3850 /* Set RF_ENV enable. */ 3851 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3852 reg |= 0x100000; 3853 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3854 DELAY(50); 3855 3856 /* Set RF_ENV output high. */ 3857 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3858 reg |= 0x10; 3859 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3860 DELAY(50); 3861 3862 /* Set address and data lengths of RF registers. */ 3863 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3864 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3865 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3866 DELAY(50); 3867 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3868 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3869 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3870 DELAY(50); 3871 3872 /* Write RF initialization values for this chain. */ 3873 for (j = 0; j < prog[i].count; j++) { 3874 if (prog[i].regs[j] >= 0xf9 && 3875 prog[i].regs[j] <= 0xfe) { 3876 /* 3877 * These are fake RF registers offsets that 3878 * indicate a delay is required. 3879 */ 3880 urtwn_delay_ms(sc, 50); 3881 continue; 3882 } 3883 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3884 DELAY(5); 3885 } 3886 3887 /* Restore RF_ENV control type. */ 3888 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3889 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3890 } 3891 3892 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3893 URTWN_CHIP_UMC_A_CUT) { 3894 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3895 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3896 } 3897 3898 /* Cache RF register CHNLBW. */ 3899 for (i = 0; i < 2; i++) { 3900 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3901 } 3902 } 3903 3904 static void 3905 urtwn_cam_init(struct urtwn_softc *sc) 3906 { 3907 uint32_t content, command; 3908 uint8_t idx; 3909 size_t i; 3910 3911 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3912 3913 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3914 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3915 return; 3916 3917 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3918 content = (idx & 3) 3919 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3920 | R92C_CAM_VALID; 3921 3922 command = R92C_CAMCMD_POLLING 3923 | R92C_CAMCMD_WRITE 3924 | R92C_CAM_CTL0(idx); 3925 3926 urtwn_write_4(sc, R92C_CAMWRITE, content); 3927 urtwn_write_4(sc, R92C_CAMCMD, command); 3928 } 3929 3930 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3931 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3932 if (i == 0) { 3933 content = (idx & 3) 3934 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3935 | R92C_CAM_VALID; 3936 } else { 3937 content = 0; 3938 } 3939 3940 command = R92C_CAMCMD_POLLING 3941 | R92C_CAMCMD_WRITE 3942 | R92C_CAM_CTL0(idx) 3943 | i; 3944 3945 urtwn_write_4(sc, R92C_CAMWRITE, content); 3946 urtwn_write_4(sc, R92C_CAMCMD, command); 3947 } 3948 } 3949 3950 /* Invalidate all CAM entries. */ 3951 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3952 } 3953 3954 static void 3955 urtwn_pa_bias_init(struct urtwn_softc *sc) 3956 { 3957 uint8_t reg; 3958 size_t i; 3959 3960 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3961 3962 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3963 3964 for (i = 0; i < sc->nrxchains; i++) { 3965 if (sc->pa_setting & (1U << i)) 3966 continue; 3967 3968 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3969 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3970 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3971 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3972 } 3973 if (!(sc->pa_setting & 0x10)) { 3974 reg = urtwn_read_1(sc, 0x16); 3975 reg = (reg & ~0xf0) | 0x90; 3976 urtwn_write_1(sc, 0x16, reg); 3977 } 3978 } 3979 3980 static void 3981 urtwn_rxfilter_init(struct urtwn_softc *sc) 3982 { 3983 3984 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3985 3986 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3987 3988 /* Initialize Rx filter. */ 3989 /* TODO: use better filter for monitor mode. */ 3990 urtwn_write_4(sc, R92C_RCR, 3991 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3992 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3993 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3994 /* Accept all multicast frames. */ 3995 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3996 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3997 /* Accept all management frames. */ 3998 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3999 /* Reject all control frames. */ 4000 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4001 /* Accept all data frames. */ 4002 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4003 } 4004 4005 static void 4006 urtwn_edca_init(struct urtwn_softc *sc) 4007 { 4008 4009 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4010 4011 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4012 4013 /* set spec SIFS (used in NAV) */ 4014 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4015 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4016 4017 /* set SIFS CCK/OFDM */ 4018 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4019 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4020 4021 /* TXOP */ 4022 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4023 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4024 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4025 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4026 } 4027 4028 static void 4029 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4030 uint16_t power[URTWN_RIDX_COUNT]) 4031 { 4032 uint32_t reg; 4033 4034 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4035 __func__, chain)); 4036 4037 /* Write per-CCK rate Tx power. */ 4038 if (chain == 0) { 4039 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4040 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4041 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4042 4043 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4044 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4045 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4046 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4047 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4048 } else { 4049 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4050 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4051 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4052 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4053 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4054 4055 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4056 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4057 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4058 } 4059 /* Write per-OFDM rate Tx power. */ 4060 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4061 SM(R92C_TXAGC_RATE06, power[ 4]) | 4062 SM(R92C_TXAGC_RATE09, power[ 5]) | 4063 SM(R92C_TXAGC_RATE12, power[ 6]) | 4064 SM(R92C_TXAGC_RATE18, power[ 7])); 4065 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4066 SM(R92C_TXAGC_RATE24, power[ 8]) | 4067 SM(R92C_TXAGC_RATE36, power[ 9]) | 4068 SM(R92C_TXAGC_RATE48, power[10]) | 4069 SM(R92C_TXAGC_RATE54, power[11])); 4070 /* Write per-MCS Tx power. */ 4071 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4072 SM(R92C_TXAGC_MCS00, power[12]) | 4073 SM(R92C_TXAGC_MCS01, power[13]) | 4074 SM(R92C_TXAGC_MCS02, power[14]) | 4075 SM(R92C_TXAGC_MCS03, power[15])); 4076 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4077 SM(R92C_TXAGC_MCS04, power[16]) | 4078 SM(R92C_TXAGC_MCS05, power[17]) | 4079 SM(R92C_TXAGC_MCS06, power[18]) | 4080 SM(R92C_TXAGC_MCS07, power[19])); 4081 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4082 SM(R92C_TXAGC_MCS08, power[20]) | 4083 SM(R92C_TXAGC_MCS09, power[21]) | 4084 SM(R92C_TXAGC_MCS10, power[22]) | 4085 SM(R92C_TXAGC_MCS11, power[23])); 4086 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4087 SM(R92C_TXAGC_MCS12, power[24]) | 4088 SM(R92C_TXAGC_MCS13, power[25]) | 4089 SM(R92C_TXAGC_MCS14, power[26]) | 4090 SM(R92C_TXAGC_MCS15, power[27])); 4091 } 4092 4093 static void 4094 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4095 uint16_t power[URTWN_RIDX_COUNT]) 4096 { 4097 struct r92c_rom *rom = &sc->rom; 4098 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4099 const struct urtwn_txpwr *base; 4100 int ridx, group; 4101 4102 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4103 device_xname(sc->sc_dev), __func__, chain, chan)); 4104 4105 /* Determine channel group. */ 4106 if (chan <= 3) { 4107 group = 0; 4108 } else if (chan <= 9) { 4109 group = 1; 4110 } else { 4111 group = 2; 4112 } 4113 4114 /* Get original Tx power based on board type and RF chain. */ 4115 if (!(sc->chip & URTWN_CHIP_92C)) { 4116 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4117 base = &rtl8188ru_txagc[chain]; 4118 } else { 4119 base = &rtl8192cu_txagc[chain]; 4120 } 4121 } else { 4122 base = &rtl8192cu_txagc[chain]; 4123 } 4124 4125 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4126 if (sc->regulatory == 0) { 4127 for (ridx = 0; ridx <= 3; ridx++) { 4128 power[ridx] = base->pwr[0][ridx]; 4129 } 4130 } 4131 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4132 if (sc->regulatory == 3) { 4133 power[ridx] = base->pwr[0][ridx]; 4134 /* Apply vendor limits. */ 4135 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4136 maxpow = rom->ht40_max_pwr[group]; 4137 } else { 4138 maxpow = rom->ht20_max_pwr[group]; 4139 } 4140 maxpow = (maxpow >> (chain * 4)) & 0xf; 4141 if (power[ridx] > maxpow) { 4142 power[ridx] = maxpow; 4143 } 4144 } else if (sc->regulatory == 1) { 4145 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4146 power[ridx] = base->pwr[group][ridx]; 4147 } 4148 } else if (sc->regulatory != 2) { 4149 power[ridx] = base->pwr[0][ridx]; 4150 } 4151 } 4152 4153 /* Compute per-CCK rate Tx power. */ 4154 cckpow = rom->cck_tx_pwr[chain][group]; 4155 for (ridx = 0; ridx <= 3; ridx++) { 4156 power[ridx] += cckpow; 4157 if (power[ridx] > R92C_MAX_TX_PWR) { 4158 power[ridx] = R92C_MAX_TX_PWR; 4159 } 4160 } 4161 4162 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4163 if (sc->ntxchains > 1) { 4164 /* Apply reduction for 2 spatial streams. */ 4165 diff = rom->ht40_2s_tx_pwr_diff[group]; 4166 diff = (diff >> (chain * 4)) & 0xf; 4167 htpow = (htpow > diff) ? htpow - diff : 0; 4168 } 4169 4170 /* Compute per-OFDM rate Tx power. */ 4171 diff = rom->ofdm_tx_pwr_diff[group]; 4172 diff = (diff >> (chain * 4)) & 0xf; 4173 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4174 for (ridx = 4; ridx <= 11; ridx++) { 4175 power[ridx] += ofdmpow; 4176 if (power[ridx] > R92C_MAX_TX_PWR) { 4177 power[ridx] = R92C_MAX_TX_PWR; 4178 } 4179 } 4180 4181 /* Compute per-MCS Tx power. */ 4182 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4183 diff = rom->ht20_tx_pwr_diff[group]; 4184 diff = (diff >> (chain * 4)) & 0xf; 4185 htpow += diff; /* HT40->HT20 correction. */ 4186 } 4187 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4188 power[ridx] += htpow; 4189 if (power[ridx] > R92C_MAX_TX_PWR) { 4190 power[ridx] = R92C_MAX_TX_PWR; 4191 } 4192 } 4193 #ifdef URTWN_DEBUG 4194 if (urtwn_debug & DBG_RF) { 4195 /* Dump per-rate Tx power values. */ 4196 printf("%s: %s: Tx power for chain %zd:\n", 4197 device_xname(sc->sc_dev), __func__, chain); 4198 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4199 printf("%s: %s: Rate %d = %u\n", 4200 device_xname(sc->sc_dev), __func__, ridx, 4201 power[ridx]); 4202 } 4203 } 4204 #endif 4205 } 4206 4207 void 4208 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4209 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4210 { 4211 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4212 const struct urtwn_r88e_txpwr *base; 4213 int ridx, group; 4214 4215 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4216 device_xname(sc->sc_dev), __func__, chain, chan)); 4217 4218 /* Determine channel group. */ 4219 if (chan <= 2) 4220 group = 0; 4221 else if (chan <= 5) 4222 group = 1; 4223 else if (chan <= 8) 4224 group = 2; 4225 else if (chan <= 11) 4226 group = 3; 4227 else if (chan <= 13) 4228 group = 4; 4229 else 4230 group = 5; 4231 4232 /* Get original Tx power based on board type and RF chain. */ 4233 base = &rtl8188eu_txagc[chain]; 4234 4235 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4236 if (sc->regulatory == 0) { 4237 for (ridx = 0; ridx <= 3; ridx++) 4238 power[ridx] = base->pwr[0][ridx]; 4239 } 4240 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4241 if (sc->regulatory == 3) 4242 power[ridx] = base->pwr[0][ridx]; 4243 else if (sc->regulatory == 1) { 4244 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4245 power[ridx] = base->pwr[group][ridx]; 4246 } else if (sc->regulatory != 2) 4247 power[ridx] = base->pwr[0][ridx]; 4248 } 4249 4250 /* Compute per-CCK rate Tx power. */ 4251 cckpow = sc->cck_tx_pwr[group]; 4252 for (ridx = 0; ridx <= 3; ridx++) { 4253 power[ridx] += cckpow; 4254 if (power[ridx] > R92C_MAX_TX_PWR) 4255 power[ridx] = R92C_MAX_TX_PWR; 4256 } 4257 4258 htpow = sc->ht40_tx_pwr[group]; 4259 4260 /* Compute per-OFDM rate Tx power. */ 4261 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4262 for (ridx = 4; ridx <= 11; ridx++) { 4263 power[ridx] += ofdmpow; 4264 if (power[ridx] > R92C_MAX_TX_PWR) 4265 power[ridx] = R92C_MAX_TX_PWR; 4266 } 4267 4268 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4269 for (ridx = 12; ridx <= 27; ridx++) { 4270 power[ridx] += bw20pow; 4271 if (power[ridx] > R92C_MAX_TX_PWR) 4272 power[ridx] = R92C_MAX_TX_PWR; 4273 } 4274 } 4275 4276 static void 4277 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4278 { 4279 uint16_t power[URTWN_RIDX_COUNT]; 4280 size_t i; 4281 4282 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4283 4284 for (i = 0; i < sc->ntxchains; i++) { 4285 /* Compute per-rate Tx power values. */ 4286 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4287 ISSET(sc->chip, URTWN_CHIP_92EU)) 4288 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4289 else 4290 urtwn_get_txpower(sc, i, chan, ht40m, power); 4291 /* Write per-rate Tx power values to hardware. */ 4292 urtwn_write_txpower(sc, i, power); 4293 } 4294 } 4295 4296 static void 4297 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4298 { 4299 struct ieee80211com *ic = &sc->sc_ic; 4300 u_int chan; 4301 size_t i; 4302 4303 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4304 4305 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4306 __func__, chan)); 4307 4308 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4309 4310 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4311 chan += 2; 4312 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4313 chan -= 2; 4314 } 4315 4316 /* Set Tx power for this new channel. */ 4317 urtwn_set_txpower(sc, chan, ht40m); 4318 4319 for (i = 0; i < sc->nrxchains; i++) { 4320 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4321 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4322 } 4323 4324 if (ht40m) { 4325 /* Is secondary channel below or above primary? */ 4326 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4327 uint32_t reg; 4328 4329 urtwn_write_1(sc, R92C_BWOPMODE, 4330 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4331 4332 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4333 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4334 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4335 4336 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4337 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4338 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4339 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4340 4341 /* Set CCK side band. */ 4342 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4343 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4344 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4345 4346 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4347 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4348 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4349 4350 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4351 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4352 ~R92C_FPGA0_ANAPARAM2_CBW20); 4353 4354 reg = urtwn_bb_read(sc, 0x818); 4355 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4356 urtwn_bb_write(sc, 0x818, reg); 4357 4358 /* Select 40MHz bandwidth. */ 4359 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4360 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4361 } else { 4362 urtwn_write_1(sc, R92C_BWOPMODE, 4363 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4364 4365 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4366 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4367 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4368 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4369 4370 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4371 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4372 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4373 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4374 R92C_FPGA0_ANAPARAM2_CBW20); 4375 } 4376 4377 /* Select 20MHz bandwidth. */ 4378 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4379 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4380 (ISSET(sc->chip, URTWN_CHIP_88E) || 4381 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4382 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4383 } 4384 } 4385 4386 static void 4387 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4388 { 4389 4390 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4391 __func__, inited)); 4392 4393 uint32_t addaBackup[16], iqkBackup[4], piMode; 4394 4395 #ifdef notyet 4396 uint32_t odfm0_agccore_regs[3]; 4397 uint32_t ant_regs[3]; 4398 uint32_t rf_regs[8]; 4399 #endif 4400 uint32_t reg0, reg1, reg2; 4401 int i, attempt; 4402 4403 #ifdef notyet 4404 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4405 R92E_STBC_SETTING + 2)); 4406 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4407 /* Save AGCCORE regs. */ 4408 for (i = 0; i < sc->nrxchains; i++) { 4409 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4410 R92C_OFDM0_AGCCORE1(i)); 4411 } 4412 #endif 4413 /* Save BB regs. */ 4414 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4415 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4416 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4417 4418 /* Save adda regs to be restored when finished. */ 4419 for (i = 0; i < __arraycount(addaReg); i++) 4420 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4421 /* Save mac regs. */ 4422 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4423 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4424 iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF); 4425 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4426 4427 #ifdef notyet 4428 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4429 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4430 4431 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4432 for (i = 0; i < sc->nrxchains; i++) 4433 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4434 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4435 #endif 4436 4437 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4438 R92C_HSSI_PARAM1_PI); 4439 if (piMode == 0) { 4440 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4441 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4442 R92C_HSSI_PARAM1_PI); 4443 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4444 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4445 R92C_HSSI_PARAM1_PI); 4446 } 4447 4448 attempt = 1; 4449 4450 next_attempt: 4451 4452 /* Set mac regs for calibration. */ 4453 for (i = 0; i < __arraycount(addaReg); i++) { 4454 urtwn_bb_write(sc, addaReg[i], 4455 addaReg[__arraycount(addaReg) - 1]); 4456 } 4457 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4458 R92C_CCK0_AFESETTING)); 4459 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4460 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4461 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4462 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4463 4464 if (sc->ntxchains > 1) 4465 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4466 4467 urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL); 4468 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4469 ~R92C_BCN_CTRL_EN_BCN)); 4470 urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8)); 4471 4472 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4473 ~R92C_GPIO_MUXCFG_ENBT)); 4474 4475 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4476 4477 if (sc->ntxchains > 1) 4478 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4479 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4480 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4481 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4482 4483 /* Restore BB regs. */ 4484 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4485 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4486 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4487 4488 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4489 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4490 if (sc->nrxchains > 1) 4491 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4492 4493 if (attempt-- > 0) 4494 goto next_attempt; 4495 4496 /* Restore mode. */ 4497 if (piMode == 0) { 4498 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4499 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4500 ~R92C_HSSI_PARAM1_PI); 4501 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4502 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4503 ~R92C_HSSI_PARAM1_PI); 4504 } 4505 4506 #ifdef notyet 4507 for (i = 0; i < sc->nrxchains; i++) { 4508 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4509 odfm0_agccore_regs[i]); 4510 } 4511 #endif 4512 4513 /* Restore adda regs. */ 4514 for (i = 0; i < __arraycount(addaReg); i++) 4515 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4516 /* Restore mac regs. */ 4517 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4518 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4519 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4520 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4521 4522 #ifdef notyet 4523 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4524 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4525 4526 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4527 for (i = 0; i < sc->nrxchains; i++) 4528 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4529 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4530 #endif 4531 } 4532 4533 static void 4534 urtwn_lc_calib(struct urtwn_softc *sc) 4535 { 4536 uint32_t rf_ac[2]; 4537 uint8_t txmode; 4538 size_t i; 4539 4540 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4541 4542 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4543 4544 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4545 if ((txmode & 0x70) != 0) { 4546 /* Disable all continuous Tx. */ 4547 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4548 4549 /* Set RF mode to standby mode. */ 4550 for (i = 0; i < sc->nrxchains; i++) { 4551 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4552 urtwn_rf_write(sc, i, R92C_RF_AC, 4553 RW(rf_ac[i], R92C_RF_AC_MODE, 4554 R92C_RF_AC_MODE_STANDBY)); 4555 } 4556 } else { 4557 /* Block all Tx queues. */ 4558 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4559 } 4560 /* Start calibration. */ 4561 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4562 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4563 4564 /* Give calibration the time to complete. */ 4565 urtwn_delay_ms(sc, 100); 4566 4567 /* Restore configuration. */ 4568 if ((txmode & 0x70) != 0) { 4569 /* Restore Tx mode. */ 4570 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4571 /* Restore RF mode. */ 4572 for (i = 0; i < sc->nrxchains; i++) { 4573 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4574 } 4575 } else { 4576 /* Unblock all Tx queues. */ 4577 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4578 } 4579 } 4580 4581 static void 4582 urtwn_temp_calib(struct urtwn_softc *sc) 4583 { 4584 int temp, t_meter_reg; 4585 4586 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4587 4588 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4589 4590 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4591 t_meter_reg = R92C_RF_T_METER; 4592 else 4593 t_meter_reg = R92E_RF_T_METER; 4594 4595 if (sc->thcal_state == 0) { 4596 /* Start measuring temperature. */ 4597 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4598 device_xname(sc->sc_dev), __func__)); 4599 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4600 sc->thcal_state = 1; 4601 return; 4602 } 4603 sc->thcal_state = 0; 4604 4605 /* Read measured temperature. */ 4606 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4607 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4608 __func__, temp)); 4609 if (temp == 0) /* Read failed, skip. */ 4610 return; 4611 4612 /* 4613 * Redo LC calibration if temperature changed significantly since 4614 * last calibration. 4615 */ 4616 if (sc->thcal_lctemp == 0) { 4617 /* First LC calibration is performed in urtwn_init(). */ 4618 sc->thcal_lctemp = temp; 4619 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4620 DPRINTFN(DBG_RF, 4621 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4622 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4623 temp)); 4624 urtwn_lc_calib(sc); 4625 /* Record temperature of last LC calibration. */ 4626 sc->thcal_lctemp = temp; 4627 } 4628 } 4629 4630 static int 4631 urtwn_init(struct ifnet *ifp) 4632 { 4633 struct urtwn_softc *sc = ifp->if_softc; 4634 struct ieee80211com *ic = &sc->sc_ic; 4635 struct urtwn_rx_data *data; 4636 uint32_t reg; 4637 size_t i; 4638 int error; 4639 4640 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4641 4642 urtwn_stop(ifp, 0); 4643 4644 mutex_enter(&sc->sc_write_mtx); 4645 4646 mutex_enter(&sc->sc_task_mtx); 4647 /* Init host async commands ring. */ 4648 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4649 mutex_exit(&sc->sc_task_mtx); 4650 4651 mutex_enter(&sc->sc_fwcmd_mtx); 4652 /* Init firmware commands ring. */ 4653 sc->fwcur = 0; 4654 mutex_exit(&sc->sc_fwcmd_mtx); 4655 4656 /* Allocate Tx/Rx buffers. */ 4657 error = urtwn_alloc_rx_list(sc); 4658 if (error != 0) { 4659 aprint_error_dev(sc->sc_dev, 4660 "could not allocate Rx buffers\n"); 4661 goto fail; 4662 } 4663 error = urtwn_alloc_tx_list(sc); 4664 if (error != 0) { 4665 aprint_error_dev(sc->sc_dev, 4666 "could not allocate Tx buffers\n"); 4667 goto fail; 4668 } 4669 4670 /* Power on adapter. */ 4671 error = urtwn_power_on(sc); 4672 if (error != 0) 4673 goto fail; 4674 4675 /* Initialize DMA. */ 4676 error = urtwn_dma_init(sc); 4677 if (error != 0) 4678 goto fail; 4679 4680 /* Set info size in Rx descriptors (in 64-bit words). */ 4681 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4682 4683 /* Init interrupts. */ 4684 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4685 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4686 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4687 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4688 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4689 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4690 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4691 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4692 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4693 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4694 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4695 } 4696 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4697 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4698 } else { 4699 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4700 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4701 } 4702 4703 /* Set MAC address. */ 4704 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4705 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4706 4707 /* Set initial network type. */ 4708 reg = urtwn_read_4(sc, R92C_CR); 4709 switch (ic->ic_opmode) { 4710 case IEEE80211_M_STA: 4711 default: 4712 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4713 break; 4714 4715 case IEEE80211_M_IBSS: 4716 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4717 break; 4718 } 4719 urtwn_write_4(sc, R92C_CR, reg); 4720 4721 /* Set response rate */ 4722 reg = urtwn_read_4(sc, R92C_RRSR); 4723 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4724 urtwn_write_4(sc, R92C_RRSR, reg); 4725 4726 /* SIFS (used in NAV) */ 4727 urtwn_write_2(sc, R92C_SPEC_SIFS, 4728 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4729 4730 /* Set short/long retry limits. */ 4731 urtwn_write_2(sc, R92C_RL, 4732 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4733 4734 /* Initialize EDCA parameters. */ 4735 urtwn_edca_init(sc); 4736 4737 /* Setup rate fallback. */ 4738 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4739 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4740 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4741 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4742 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4743 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4744 } 4745 4746 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4747 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4748 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4749 /* Set ACK timeout. */ 4750 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4751 4752 /* Setup USB aggregation. */ 4753 /* Tx */ 4754 reg = urtwn_read_4(sc, R92C_TDECTRL); 4755 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4756 urtwn_write_4(sc, R92C_TDECTRL, reg); 4757 /* Rx */ 4758 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4759 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4760 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4761 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4762 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4763 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4764 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4765 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4766 ISSET(sc->chip, URTWN_CHIP_92EU)) 4767 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4768 else 4769 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4770 4771 /* Initialize beacon parameters. */ 4772 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4773 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4774 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4775 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4776 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4777 4778 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4779 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4780 /* Setup AMPDU aggregation. */ 4781 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4782 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4783 urtwn_write_2(sc, 0x4ca, 0x0708); 4784 4785 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4786 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4787 } 4788 4789 /* Load 8051 microcode. */ 4790 error = urtwn_load_firmware(sc); 4791 if (error != 0) 4792 goto fail; 4793 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4794 4795 /* Initialize MAC/BB/RF blocks. */ 4796 /* 4797 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4798 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4799 * XXX: This setting should be removed from rtl8192cu_mac[]. 4800 */ 4801 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4802 urtwn_rxfilter_init(sc); // reset R92C_RCR 4803 urtwn_bb_init(sc); 4804 urtwn_rf_init(sc); 4805 4806 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4807 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4808 urtwn_write_2(sc, R92C_CR, 4809 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4810 R92C_CR_MACRXEN); 4811 } 4812 4813 /* Turn CCK and OFDM blocks on. */ 4814 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4815 reg |= R92C_RFMOD_CCK_EN; 4816 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4817 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4818 reg |= R92C_RFMOD_OFDM_EN; 4819 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4820 4821 /* Clear per-station keys table. */ 4822 urtwn_cam_init(sc); 4823 4824 /* Enable hardware sequence numbering. */ 4825 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4826 4827 /* Perform LO and IQ calibrations. */ 4828 urtwn_iq_calib(sc, sc->iqk_inited); 4829 sc->iqk_inited = true; 4830 4831 /* Perform LC calibration. */ 4832 urtwn_lc_calib(sc); 4833 4834 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4835 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4836 /* Fix USB interference issue. */ 4837 urtwn_write_1(sc, 0xfe40, 0xe0); 4838 urtwn_write_1(sc, 0xfe41, 0x8d); 4839 urtwn_write_1(sc, 0xfe42, 0x80); 4840 urtwn_write_4(sc, 0x20c, 0xfd0320); 4841 4842 urtwn_pa_bias_init(sc); 4843 } 4844 4845 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4846 !(sc->chip & URTWN_CHIP_92EU)) { 4847 /* 1T1R */ 4848 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4849 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4850 } 4851 4852 /* Initialize GPIO setting. */ 4853 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4854 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4855 4856 /* Fix for lower temperature. */ 4857 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4858 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4859 urtwn_write_1(sc, 0x15, 0xe9); 4860 4861 /* Set default channel. */ 4862 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4863 4864 /* Queue Rx xfers. */ 4865 for (size_t j = 0; j < sc->rx_npipe; j++) { 4866 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4867 data = &sc->rx_data[j][i]; 4868 usbd_setup_xfer(data->xfer, data, data->buf, 4869 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4870 urtwn_rxeof); 4871 error = usbd_transfer(data->xfer); 4872 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4873 error != USBD_IN_PROGRESS)) 4874 goto fail; 4875 } 4876 } 4877 4878 /* We're ready to go. */ 4879 ifp->if_flags &= ~IFF_OACTIVE; 4880 ifp->if_flags |= IFF_RUNNING; 4881 sc->sc_running = true; 4882 4883 mutex_exit(&sc->sc_write_mtx); 4884 4885 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4886 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4887 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4888 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4889 urtwn_wait_async(sc); 4890 4891 return 0; 4892 4893 fail: 4894 mutex_exit(&sc->sc_write_mtx); 4895 4896 urtwn_stop(ifp, 1); 4897 return error; 4898 } 4899 4900 static void 4901 urtwn_stop(struct ifnet *ifp, int disable) 4902 { 4903 struct urtwn_softc *sc = ifp->if_softc; 4904 struct ieee80211com *ic = &sc->sc_ic; 4905 size_t i; 4906 int s; 4907 4908 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4909 4910 s = splusb(); 4911 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4912 urtwn_wait_async(sc); 4913 splx(s); 4914 4915 sc->tx_timer = 0; 4916 ifp->if_timer = 0; 4917 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4918 4919 callout_stop(&sc->sc_scan_to); 4920 callout_stop(&sc->sc_calib_to); 4921 4922 /* Abort Tx. */ 4923 for (i = 0; i < sc->tx_npipe; i++) { 4924 if (sc->tx_pipe[i] != NULL) 4925 usbd_abort_pipe(sc->tx_pipe[i]); 4926 } 4927 4928 /* Stop Rx pipe. */ 4929 for (i = 0; i < sc->rx_npipe; i++) { 4930 if (sc->rx_pipe[i] != NULL) 4931 usbd_abort_pipe(sc->rx_pipe[i]); 4932 } 4933 4934 /* Free Tx/Rx buffers. */ 4935 urtwn_free_tx_list(sc); 4936 urtwn_free_rx_list(sc); 4937 4938 sc->sc_running = false; 4939 if (disable) 4940 urtwn_chip_stop(sc); 4941 } 4942 4943 static int 4944 urtwn_reset(struct ifnet *ifp) 4945 { 4946 struct urtwn_softc *sc = ifp->if_softc; 4947 struct ieee80211com *ic = &sc->sc_ic; 4948 4949 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4950 return ENETRESET; 4951 4952 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4953 4954 return 0; 4955 } 4956 4957 static void 4958 urtwn_chip_stop(struct urtwn_softc *sc) 4959 { 4960 uint32_t reg; 4961 bool disabled = true; 4962 4963 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4964 4965 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4966 return; 4967 4968 mutex_enter(&sc->sc_write_mtx); 4969 4970 /* 4971 * RF Off Sequence 4972 */ 4973 /* Pause MAC TX queue */ 4974 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4975 4976 /* Disable RF */ 4977 urtwn_rf_write(sc, 0, 0, 0); 4978 4979 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4980 4981 /* Reset BB state machine */ 4982 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4983 R92C_SYS_FUNC_EN_USBD | 4984 R92C_SYS_FUNC_EN_USBA | 4985 R92C_SYS_FUNC_EN_BB_GLB_RST); 4986 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4987 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4988 4989 /* 4990 * Reset digital sequence 4991 */ 4992 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4993 /* Reset MCU ready status */ 4994 urtwn_write_1(sc, R92C_MCUFWDL, 0); 4995 /* If firmware in ram code, do reset */ 4996 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 4997 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4998 ISSET(sc->chip, URTWN_CHIP_92EU)) 4999 urtwn_r88e_fw_reset(sc); 5000 else 5001 urtwn_fw_reset(sc); 5002 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5003 } 5004 } 5005 5006 /* Reset MAC and Enable 8051 */ 5007 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5008 5009 /* Reset MCU ready status */ 5010 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5011 5012 if (disabled) { 5013 /* Disable MAC clock */ 5014 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5015 /* Disable AFE PLL */ 5016 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5017 /* Gated AFE DIG_CLOCK */ 5018 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5019 /* Isolated digital to PON */ 5020 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5021 } 5022 5023 /* 5024 * Pull GPIO PIN to balance level and LED control 5025 */ 5026 /* 1. Disable GPIO[7:0] */ 5027 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5028 5029 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5030 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5031 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5032 5033 /* Disable GPIO[10:8] */ 5034 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5035 5036 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5037 reg |= (((reg & 0x000f) << 4) | 0x0780); 5038 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5039 5040 /* Disable LED0 & 1 */ 5041 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5042 5043 /* 5044 * Reset digital sequence 5045 */ 5046 if (disabled) { 5047 /* Disable ELDR clock */ 5048 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5049 /* Isolated ELDR to PON */ 5050 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5051 } 5052 5053 /* 5054 * Disable analog sequence 5055 */ 5056 if (disabled) { 5057 /* Disable A15 power */ 5058 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5059 /* Disable digital core power */ 5060 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5061 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5062 ~R92C_LDOV12D_CTRL_LDV12_EN); 5063 } 5064 5065 /* Enter PFM mode */ 5066 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5067 5068 /* Set USB suspend */ 5069 urtwn_write_2(sc, R92C_APS_FSMCO, 5070 R92C_APS_FSMCO_APDM_HOST | 5071 R92C_APS_FSMCO_AFSM_HSUS | 5072 R92C_APS_FSMCO_PFM_ALDN); 5073 5074 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5075 5076 mutex_exit(&sc->sc_write_mtx); 5077 } 5078 5079 static void 5080 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5081 { 5082 if (sc->sc_running == false) 5083 DELAY(ms * 1000); 5084 else 5085 usbd_delay_ms(sc->sc_udev, ms); 5086 } 5087 5088 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 5089 5090 #ifdef _MODULE 5091 #include "ioconf.c" 5092 #endif 5093 5094 static int 5095 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5096 { 5097 int error = 0; 5098 5099 switch (cmd) { 5100 case MODULE_CMD_INIT: 5101 #ifdef _MODULE 5102 error = config_init_component(cfdriver_ioconf_urtwn, 5103 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5104 #endif 5105 return error; 5106 case MODULE_CMD_FINI: 5107 #ifdef _MODULE 5108 error = config_fini_component(cfdriver_ioconf_urtwn, 5109 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5110 #endif 5111 return error; 5112 default: 5113 return ENOTTY; 5114 } 5115 } 5116
Indexes created Thu Oct 02 14:10:14 GMT 2025