if_urtwn.c revision 1.53.2.2
1 /* $NetBSD: if_urtwn.c,v 1.53.2.2 2018/01/31 18:01:54 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.53.2.2 2018/01/31 18:01:54 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 46 #include <sys/bus.h> 47 #include <machine/endian.h> 48 #include <sys/intr.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_inarp.h> 63 64 #include <net80211/ieee80211_netbsd.h> 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_radiotap.h> 67 68 #include <dev/firmload.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 #include <dev/usb/usbdivar.h> 73 #include <dev/usb/usbdi_util.h> 74 #include <dev/usb/usbdevs.h> 75 76 #include <dev/usb/if_urtwnreg.h> 77 #include <dev/usb/if_urtwnvar.h> 78 #include <dev/usb/if_urtwn_data.h> 79 80 /* 81 * The sc_write_mtx locking is to prevent sequences of writes from 82 * being intermingled with each other. I don't know if this is really 83 * needed. I have added it just to be on the safe side. 84 */ 85 86 #ifdef URTWN_DEBUG 87 #define DBG_INIT __BIT(0) 88 #define DBG_FN __BIT(1) 89 #define DBG_TX __BIT(2) 90 #define DBG_RX __BIT(3) 91 #define DBG_STM __BIT(4) 92 #define DBG_RF __BIT(5) 93 #define DBG_REG __BIT(6) 94 #define DBG_ALL 0xffffffffU 95 u_int urtwn_debug = 0; 96 #define DPRINTFN(n, s) \ 97 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 98 #else 99 #define DPRINTFN(n, s) 100 #endif 101 102 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 103 #define URTWN_RTL8188E_DEV(v,p) \ 104 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 105 #define URTWN_RTL8192EU_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 107 static const struct urtwn_dev { 108 struct usb_devno dev; 109 uint32_t flags; 110 #define FLAG_RTL8188E __BIT(0) 111 #define FLAG_RTL8192E __BIT(1) 112 } urtwn_devs[] = { 113 URTWN_DEV(ABOCOM, RTL8188CU_1), 114 URTWN_DEV(ABOCOM, RTL8188CU_2), 115 URTWN_DEV(ABOCOM, RTL8192CU), 116 URTWN_DEV(ASUSTEK, RTL8192CU), 117 URTWN_DEV(ASUSTEK, RTL8192CU_3), 118 URTWN_DEV(ASUSTEK, USBN10NANO), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 121 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 122 URTWN_DEV(AZUREWAVE, RTL8188CU), 123 URTWN_DEV(BELKIN, F7D2102), 124 URTWN_DEV(BELKIN, RTL8188CU), 125 URTWN_DEV(BELKIN, RTL8188CUS), 126 URTWN_DEV(BELKIN, RTL8192CU), 127 URTWN_DEV(BELKIN, RTL8192CU_1), 128 URTWN_DEV(BELKIN, RTL8192CU_2), 129 URTWN_DEV(CHICONY, RTL8188CUS_1), 130 URTWN_DEV(CHICONY, RTL8188CUS_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_3), 132 URTWN_DEV(CHICONY, RTL8188CUS_4), 133 URTWN_DEV(CHICONY, RTL8188CUS_5), 134 URTWN_DEV(CHICONY, RTL8188CUS_6), 135 URTWN_DEV(COMPARE, RTL8192CU), 136 URTWN_DEV(COREGA, RTL8192CU), 137 URTWN_DEV(DLINK, DWA131B), 138 URTWN_DEV(DLINK, RTL8188CU), 139 URTWN_DEV(DLINK, RTL8192CU_1), 140 URTWN_DEV(DLINK, RTL8192CU_2), 141 URTWN_DEV(DLINK, RTL8192CU_3), 142 URTWN_DEV(DLINK, RTL8192CU_4), 143 URTWN_DEV(EDIMAX, RTL8188CU), 144 URTWN_DEV(EDIMAX, RTL8192CU), 145 URTWN_DEV(FEIXUN, RTL8188CU), 146 URTWN_DEV(FEIXUN, RTL8192CU), 147 URTWN_DEV(GUILLEMOT, HWNUP150), 148 URTWN_DEV(GUILLEMOT, RTL8192CU), 149 URTWN_DEV(HAWKING, RTL8192CU), 150 URTWN_DEV(HAWKING, RTL8192CU_2), 151 URTWN_DEV(HP3, RTL8188CU), 152 URTWN_DEV(IODATA, WNG150UM), 153 URTWN_DEV(IODATA, RTL8192CU), 154 URTWN_DEV(NETGEAR, WNA1000M), 155 URTWN_DEV(NETGEAR, RTL8192CU), 156 URTWN_DEV(NETGEAR4, RTL8188CU), 157 URTWN_DEV(NOVATECH, RTL8188CU), 158 URTWN_DEV(PLANEX2, RTL8188CU_1), 159 URTWN_DEV(PLANEX2, RTL8188CU_2), 160 URTWN_DEV(PLANEX2, RTL8192CU), 161 URTWN_DEV(PLANEX2, RTL8188CU_3), 162 URTWN_DEV(PLANEX2, RTL8188CU_4), 163 URTWN_DEV(PLANEX2, RTL8188CUS), 164 URTWN_DEV(REALTEK, RTL8188CE_0), 165 URTWN_DEV(REALTEK, RTL8188CE_1), 166 URTWN_DEV(REALTEK, RTL8188CTV), 167 URTWN_DEV(REALTEK, RTL8188CU_0), 168 URTWN_DEV(REALTEK, RTL8188CU_1), 169 URTWN_DEV(REALTEK, RTL8188CU_2), 170 URTWN_DEV(REALTEK, RTL8188CU_3), 171 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 172 URTWN_DEV(REALTEK, RTL8188CUS), 173 URTWN_DEV(REALTEK, RTL8188RU), 174 URTWN_DEV(REALTEK, RTL8188RU_2), 175 URTWN_DEV(REALTEK, RTL8188RU_3), 176 URTWN_DEV(REALTEK, RTL8191CU), 177 URTWN_DEV(REALTEK, RTL8192CE), 178 URTWN_DEV(REALTEK, RTL8192CU), 179 URTWN_DEV(SITECOMEU, RTL8188CU), 180 URTWN_DEV(SITECOMEU, RTL8188CU_2), 181 URTWN_DEV(SITECOMEU, RTL8192CU), 182 URTWN_DEV(SITECOMEU, RTL8192CUR2), 183 URTWN_DEV(TPLINK, RTL8192CU), 184 URTWN_DEV(TRENDNET, RTL8188CU), 185 URTWN_DEV(TRENDNET, RTL8192CU), 186 URTWN_DEV(ZYXEL, RTL8192CU), 187 188 /* URTWN_RTL8188E */ 189 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 190 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 191 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 192 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 193 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 194 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 195 196 /* URTWN_RTL8192EU */ 197 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 198 }; 199 #undef URTWN_DEV 200 #undef URTWN_RTL8188E_DEV 201 #undef URTWN_RTL8192EU_DEV 202 203 static int urtwn_match(device_t, cfdata_t, void *); 204 static void urtwn_attach(device_t, device_t, void *); 205 static int urtwn_detach(device_t, int); 206 static int urtwn_activate(device_t, enum devact); 207 208 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 209 urtwn_attach, urtwn_detach, urtwn_activate); 210 211 static int urtwn_open_pipes(struct urtwn_softc *); 212 static void urtwn_close_pipes(struct urtwn_softc *); 213 static int urtwn_alloc_rx_list(struct urtwn_softc *); 214 static void urtwn_free_rx_list(struct urtwn_softc *); 215 static int urtwn_alloc_tx_list(struct urtwn_softc *); 216 static void urtwn_free_tx_list(struct urtwn_softc *); 217 static void urtwn_task(void *); 218 static void urtwn_do_async(struct urtwn_softc *, 219 void (*)(struct urtwn_softc *, void *), void *, int); 220 static void urtwn_wait_async(struct urtwn_softc *); 221 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 222 int); 223 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 224 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 225 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 226 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 227 int); 228 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 229 int); 230 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 231 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 232 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 233 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 234 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 235 uint32_t); 236 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 237 uint32_t); 238 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 239 uint32_t); 240 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 241 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 242 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 243 static void urtwn_efuse_read(struct urtwn_softc *); 244 static void urtwn_efuse_switch_power(struct urtwn_softc *); 245 static int urtwn_read_chipid(struct urtwn_softc *); 246 #ifdef URTWN_DEBUG 247 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 248 #endif 249 static void urtwn_read_rom(struct urtwn_softc *); 250 static void urtwn_r88e_read_rom(struct urtwn_softc *); 251 static int urtwn_media_change(struct ifnet *); 252 static int urtwn_ra_init(struct urtwn_softc *); 253 static int urtwn_get_nettype(struct urtwn_softc *); 254 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 255 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 256 static void urtwn_set_led(struct urtwn_softc *, int, int); 257 static void urtwn_calib_to(void *); 258 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 259 static void urtwn_next_scan(void *); 260 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 261 int); 262 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 263 static int urtwn_wme_update(struct ieee80211com *); 264 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 265 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 266 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 267 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 268 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 269 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 270 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 271 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 272 struct ieee80211_node *, struct urtwn_tx_data *); 273 static struct urtwn_tx_data * 274 urtwn_get_tx_data(struct urtwn_softc *, size_t); 275 static void urtwn_start(struct ifnet *); 276 static void urtwn_watchdog(struct ifnet *); 277 static int urtwn_ioctl(struct ifnet *, u_long, void *); 278 static int urtwn_r92c_power_on(struct urtwn_softc *); 279 static int urtwn_r92e_power_on(struct urtwn_softc *); 280 static int urtwn_r88e_power_on(struct urtwn_softc *); 281 static int urtwn_llt_init(struct urtwn_softc *); 282 static void urtwn_fw_reset(struct urtwn_softc *); 283 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 284 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 285 static int urtwn_load_firmware(struct urtwn_softc *); 286 static int urtwn_r92c_dma_init(struct urtwn_softc *); 287 static int urtwn_r88e_dma_init(struct urtwn_softc *); 288 static void urtwn_mac_init(struct urtwn_softc *); 289 static void urtwn_bb_init(struct urtwn_softc *); 290 static void urtwn_rf_init(struct urtwn_softc *); 291 static void urtwn_cam_init(struct urtwn_softc *); 292 static void urtwn_pa_bias_init(struct urtwn_softc *); 293 static void urtwn_rxfilter_init(struct urtwn_softc *); 294 static void urtwn_edca_init(struct urtwn_softc *); 295 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 296 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 297 uint16_t[]); 298 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 299 u_int, uint16_t[]); 300 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 301 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 302 u_int); 303 static void urtwn_iq_calib(struct urtwn_softc *, bool); 304 static void urtwn_lc_calib(struct urtwn_softc *); 305 static void urtwn_temp_calib(struct urtwn_softc *); 306 static int urtwn_init(struct ifnet *); 307 static void urtwn_stop(struct ifnet *, int); 308 static int urtwn_reset(struct ifnet *); 309 static void urtwn_chip_stop(struct urtwn_softc *); 310 static void urtwn_newassoc(struct ieee80211_node *, int); 311 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 312 313 /* Aliases. */ 314 #define urtwn_bb_write urtwn_write_4 315 #define urtwn_bb_read urtwn_read_4 316 317 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 318 319 static const uint16_t addaReg[] = { 320 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 321 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 322 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 323 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 324 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 325 }; 326 327 static int 328 urtwn_match(device_t parent, cfdata_t match, void *aux) 329 { 330 struct usb_attach_arg *uaa = aux; 331 332 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 333 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 334 } 335 336 static void 337 urtwn_attach(device_t parent, device_t self, void *aux) 338 { 339 struct urtwn_softc *sc = device_private(self); 340 struct ieee80211com *ic = &sc->sc_ic; 341 struct ifnet *ifp = &sc->sc_if; 342 struct usb_attach_arg *uaa = aux; 343 char *devinfop; 344 const struct urtwn_dev *dev; 345 usb_device_request_t req; 346 size_t i; 347 int error; 348 349 sc->sc_dev = self; 350 sc->sc_udev = uaa->uaa_device; 351 352 sc->chip = 0; 353 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 354 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 355 SET(sc->chip, URTWN_CHIP_88E); 356 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 357 SET(sc->chip, URTWN_CHIP_92EU); 358 359 aprint_naive("\n"); 360 aprint_normal("\n"); 361 362 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 363 364 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 365 aprint_normal_dev(self, "%s\n", devinfop); 366 usbd_devinfo_free(devinfop); 367 368 req.bmRequestType = UT_WRITE_DEVICE; 369 req.bRequest = UR_SET_FEATURE; 370 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 371 USETW(req.wIndex, UHF_PORT_SUSPEND); 372 USETW(req.wLength, 0); 373 374 (void) usbd_do_request(sc->sc_udev, &req, 0); 375 376 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 377 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 378 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 379 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 380 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 381 382 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 383 384 callout_init(&sc->sc_scan_to, 0); 385 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 386 callout_init(&sc->sc_calib_to, 0); 387 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 388 389 error = usbd_set_config_no(sc->sc_udev, 1, 0); 390 if (error != 0) { 391 aprint_error_dev(self, "failed to set configuration" 392 ", err=%s\n", usbd_errstr(error)); 393 goto fail; 394 } 395 396 /* Get the first interface handle. */ 397 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 398 if (error != 0) { 399 aprint_error_dev(self, "could not get interface handle\n"); 400 goto fail; 401 } 402 403 error = urtwn_read_chipid(sc); 404 if (error != 0) { 405 aprint_error_dev(self, "unsupported test chip\n"); 406 goto fail; 407 } 408 409 /* Determine number of Tx/Rx chains. */ 410 if (sc->chip & URTWN_CHIP_92C) { 411 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 412 sc->nrxchains = 2; 413 } else if (sc->chip & URTWN_CHIP_92EU) { 414 sc->ntxchains = 2; 415 sc->nrxchains = 2; 416 } else { 417 sc->ntxchains = 1; 418 sc->nrxchains = 1; 419 } 420 421 if (ISSET(sc->chip, URTWN_CHIP_88E) || 422 ISSET(sc->chip, URTWN_CHIP_92EU)) 423 urtwn_r88e_read_rom(sc); 424 else 425 urtwn_read_rom(sc); 426 427 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 428 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 429 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 430 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 431 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 432 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 433 "8188CUS", sc->ntxchains, sc->nrxchains, 434 ether_sprintf(ic->ic_myaddr)); 435 436 error = urtwn_open_pipes(sc); 437 if (error != 0) { 438 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 439 goto fail; 440 } 441 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 442 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 443 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 444 445 /* 446 * Setup the 802.11 device. 447 */ 448 ic->ic_ifp = ifp; 449 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 450 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 451 ic->ic_state = IEEE80211_S_INIT; 452 453 /* Set device capabilities. */ 454 ic->ic_caps = 455 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 456 IEEE80211_C_IBSS | /* IBSS mode supported */ 457 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 458 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 459 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 460 IEEE80211_C_WME | /* 802.11e */ 461 IEEE80211_C_WPA; /* 802.11i */ 462 463 /* Set supported .11b and .11g rates. */ 464 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 465 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 466 467 /* Set supported .11b and .11g channels (1 through 14). */ 468 for (i = 1; i <= 14; i++) { 469 ic->ic_channels[i].ic_freq = 470 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 471 ic->ic_channels[i].ic_flags = 472 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 473 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 474 } 475 476 ifp->if_softc = sc; 477 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 478 ifp->if_init = urtwn_init; 479 ifp->if_ioctl = urtwn_ioctl; 480 ifp->if_start = urtwn_start; 481 ifp->if_watchdog = urtwn_watchdog; 482 IFQ_SET_READY(&ifp->if_snd); 483 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 484 485 if_attach(ifp); 486 ieee80211_ifattach(ic); 487 488 /* override default methods */ 489 ic->ic_newassoc = urtwn_newassoc; 490 ic->ic_reset = urtwn_reset; 491 ic->ic_wme.wme_update = urtwn_wme_update; 492 493 /* Override state transition machine. */ 494 sc->sc_newstate = ic->ic_newstate; 495 ic->ic_newstate = urtwn_newstate; 496 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 497 498 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 499 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 500 &sc->sc_drvbpf); 501 502 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 503 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 504 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 505 506 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 507 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 508 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 509 510 ieee80211_announce(ic); 511 512 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 513 514 if (!pmf_device_register(self, NULL, NULL)) 515 aprint_error_dev(self, "couldn't establish power handler\n"); 516 517 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 518 return; 519 520 fail: 521 sc->sc_dying = 1; 522 aprint_error_dev(self, "attach failed\n"); 523 } 524 525 static int 526 urtwn_detach(device_t self, int flags) 527 { 528 struct urtwn_softc *sc = device_private(self); 529 struct ifnet *ifp = &sc->sc_if; 530 int s; 531 532 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 533 534 pmf_device_deregister(self); 535 536 s = splusb(); 537 538 sc->sc_dying = 1; 539 540 callout_stop(&sc->sc_scan_to); 541 callout_stop(&sc->sc_calib_to); 542 543 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 544 usb_rem_task(sc->sc_udev, &sc->sc_task); 545 urtwn_stop(ifp, 0); 546 547 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 548 bpf_detach(ifp); 549 ieee80211_ifdetach(&sc->sc_ic); 550 if_detach(ifp); 551 552 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 553 urtwn_close_pipes(sc); 554 } 555 556 splx(s); 557 558 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 559 560 callout_destroy(&sc->sc_scan_to); 561 callout_destroy(&sc->sc_calib_to); 562 563 mutex_destroy(&sc->sc_write_mtx); 564 mutex_destroy(&sc->sc_fwcmd_mtx); 565 mutex_destroy(&sc->sc_tx_mtx); 566 mutex_destroy(&sc->sc_rx_mtx); 567 mutex_destroy(&sc->sc_task_mtx); 568 569 return 0; 570 } 571 572 static int 573 urtwn_activate(device_t self, enum devact act) 574 { 575 struct urtwn_softc *sc = device_private(self); 576 577 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 578 579 switch (act) { 580 case DVACT_DEACTIVATE: 581 if_deactivate(sc->sc_ic.ic_ifp); 582 return 0; 583 default: 584 return EOPNOTSUPP; 585 } 586 } 587 588 static int 589 urtwn_open_pipes(struct urtwn_softc *sc) 590 { 591 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 592 static uint8_t epaddr[R92C_MAX_EPOUT]; 593 static uint8_t rxepaddr[R92C_MAX_EPIN]; 594 usb_interface_descriptor_t *id; 595 usb_endpoint_descriptor_t *ed; 596 size_t i, ntx = 0, nrx = 0; 597 int error; 598 599 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 600 601 /* Determine the number of bulk-out pipes. */ 602 id = usbd_get_interface_descriptor(sc->sc_iface); 603 for (i = 0; i < id->bNumEndpoints; i++) { 604 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 605 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 606 continue; 607 } 608 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 609 if (ntx < sizeof(epaddr)) 610 epaddr[ntx] = ed->bEndpointAddress; 611 ntx++; 612 } 613 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 614 if (nrx < sizeof(rxepaddr)) 615 rxepaddr[nrx] = ed->bEndpointAddress; 616 nrx++; 617 } 618 } 619 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 620 aprint_error_dev(sc->sc_dev, 621 "%zd: invalid number of Rx bulk pipes\n", nrx); 622 return EIO; 623 } 624 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 625 aprint_error_dev(sc->sc_dev, 626 "%zd: invalid number of Tx bulk pipes\n", ntx); 627 return EIO; 628 } 629 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 630 device_xname(sc->sc_dev), __func__, nrx, ntx)); 631 sc->rx_npipe = nrx; 632 sc->tx_npipe = ntx; 633 634 /* Open bulk-in pipe at address 0x81. */ 635 for (i = 0; i < nrx; i++) { 636 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 637 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 638 if (error != 0) { 639 aprint_error_dev(sc->sc_dev, 640 "could not open Rx bulk pipe 0x%02x: %d\n", 641 rxepaddr[i], error); 642 goto fail; 643 } 644 } 645 646 /* Open bulk-out pipes (up to 3). */ 647 for (i = 0; i < ntx; i++) { 648 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 649 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 650 if (error != 0) { 651 aprint_error_dev(sc->sc_dev, 652 "could not open Tx bulk pipe 0x%02x: %d\n", 653 epaddr[i], error); 654 goto fail; 655 } 656 } 657 658 /* Map 802.11 access categories to USB pipes. */ 659 sc->ac2idx[WME_AC_BK] = 660 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 661 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 662 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 663 664 fail: 665 if (error != 0) 666 urtwn_close_pipes(sc); 667 return error; 668 } 669 670 static void 671 urtwn_close_pipes(struct urtwn_softc *sc) 672 { 673 struct usbd_pipe *pipe; 674 size_t i; 675 676 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 677 678 /* Close Rx pipes. */ 679 CTASSERT(sizeof(pipe) == sizeof(void *)); 680 for (i = 0; i < sc->rx_npipe; i++) { 681 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 682 if (pipe != NULL) { 683 usbd_close_pipe(pipe); 684 } 685 } 686 687 /* Close Tx pipes. */ 688 for (i = 0; i < sc->tx_npipe; i++) { 689 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 690 if (pipe != NULL) { 691 usbd_close_pipe(pipe); 692 } 693 } 694 } 695 696 static int 697 urtwn_alloc_rx_list(struct urtwn_softc *sc) 698 { 699 struct urtwn_rx_data *data; 700 size_t i; 701 int error = 0; 702 703 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 704 705 for (size_t j = 0; j < sc->rx_npipe; j++) { 706 TAILQ_INIT(&sc->rx_free_list[j]); 707 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 708 data = &sc->rx_data[j][i]; 709 710 data->sc = sc; /* Backpointer for callbacks. */ 711 712 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 713 0, 0, &data->xfer); 714 if (error) { 715 aprint_error_dev(sc->sc_dev, 716 "could not allocate xfer\n"); 717 break; 718 } 719 720 data->buf = usbd_get_buffer(data->xfer); 721 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 722 } 723 } 724 if (error != 0) 725 urtwn_free_rx_list(sc); 726 return error; 727 } 728 729 static void 730 urtwn_free_rx_list(struct urtwn_softc *sc) 731 { 732 struct usbd_xfer *xfer; 733 size_t i; 734 735 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 736 737 /* NB: Caller must abort pipe first. */ 738 for (size_t j = 0; j < sc->rx_npipe; j++) { 739 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 740 CTASSERT(sizeof(xfer) == sizeof(void *)); 741 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 742 if (xfer != NULL) 743 usbd_destroy_xfer(xfer); 744 } 745 } 746 } 747 748 static int 749 urtwn_alloc_tx_list(struct urtwn_softc *sc) 750 { 751 struct urtwn_tx_data *data; 752 size_t i; 753 int error = 0; 754 755 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 756 757 mutex_enter(&sc->sc_tx_mtx); 758 for (size_t j = 0; j < sc->tx_npipe; j++) { 759 TAILQ_INIT(&sc->tx_free_list[j]); 760 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 761 data = &sc->tx_data[j][i]; 762 763 data->sc = sc; /* Backpointer for callbacks. */ 764 data->pidx = j; 765 766 error = usbd_create_xfer(sc->tx_pipe[j], 767 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 768 &data->xfer); 769 if (error) { 770 aprint_error_dev(sc->sc_dev, 771 "could not allocate xfer\n"); 772 goto fail; 773 } 774 775 data->buf = usbd_get_buffer(data->xfer); 776 777 /* Append this Tx buffer to our free list. */ 778 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 779 } 780 } 781 mutex_exit(&sc->sc_tx_mtx); 782 return 0; 783 784 fail: 785 urtwn_free_tx_list(sc); 786 mutex_exit(&sc->sc_tx_mtx); 787 return error; 788 } 789 790 static void 791 urtwn_free_tx_list(struct urtwn_softc *sc) 792 { 793 struct usbd_xfer *xfer; 794 size_t i; 795 796 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 797 798 /* NB: Caller must abort pipe first. */ 799 for (size_t j = 0; j < sc->tx_npipe; j++) { 800 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 801 CTASSERT(sizeof(xfer) == sizeof(void *)); 802 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 803 if (xfer != NULL) 804 usbd_destroy_xfer(xfer); 805 } 806 } 807 } 808 809 static void 810 urtwn_task(void *arg) 811 { 812 struct urtwn_softc *sc = arg; 813 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 814 struct urtwn_host_cmd *cmd; 815 int s; 816 817 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 818 819 /* Process host commands. */ 820 s = splusb(); 821 mutex_spin_enter(&sc->sc_task_mtx); 822 while (ring->next != ring->cur) { 823 cmd = &ring->cmd[ring->next]; 824 mutex_spin_exit(&sc->sc_task_mtx); 825 splx(s); 826 /* Invoke callback with kernel lock held. */ 827 cmd->cb(sc, cmd->data); 828 s = splusb(); 829 mutex_spin_enter(&sc->sc_task_mtx); 830 ring->queued--; 831 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 832 } 833 mutex_spin_exit(&sc->sc_task_mtx); 834 wakeup(&sc->cmdq); 835 splx(s); 836 } 837 838 static void 839 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 840 void *arg, int len) 841 { 842 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 843 struct urtwn_host_cmd *cmd; 844 int s; 845 846 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 847 device_xname(sc->sc_dev), __func__, cb, arg, len)); 848 849 s = splusb(); 850 mutex_spin_enter(&sc->sc_task_mtx); 851 cmd = &ring->cmd[ring->cur]; 852 cmd->cb = cb; 853 KASSERT(len <= sizeof(cmd->data)); 854 memcpy(cmd->data, arg, len); 855 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 856 857 /* If there is no pending command already, schedule a task. */ 858 if (!sc->sc_dying && ++ring->queued == 1) { 859 mutex_spin_exit(&sc->sc_task_mtx); 860 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 861 } else 862 mutex_spin_exit(&sc->sc_task_mtx); 863 splx(s); 864 } 865 866 static void 867 urtwn_wait_async(struct urtwn_softc *sc) 868 { 869 870 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 871 872 /* Wait for all queued asynchronous commands to complete. */ 873 while (sc->cmdq.queued > 0) 874 tsleep(&sc->cmdq, 0, "endtask", 0); 875 } 876 877 static int 878 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 879 int len) 880 { 881 usb_device_request_t req; 882 usbd_status error; 883 884 KASSERT(mutex_owned(&sc->sc_write_mtx)); 885 886 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 887 req.bRequest = R92C_REQ_REGS; 888 USETW(req.wValue, addr); 889 USETW(req.wIndex, 0); 890 USETW(req.wLength, len); 891 error = usbd_do_request(sc->sc_udev, &req, buf); 892 if (error != USBD_NORMAL_COMPLETION) { 893 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 894 device_xname(sc->sc_dev), __func__, error, addr, len)); 895 } 896 return error; 897 } 898 899 static void 900 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 901 { 902 903 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 904 device_xname(sc->sc_dev), __func__, addr, val)); 905 906 urtwn_write_region_1(sc, addr, &val, 1); 907 } 908 909 static void 910 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 911 { 912 uint8_t buf[2]; 913 914 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 915 device_xname(sc->sc_dev), __func__, addr, val)); 916 917 buf[0] = (uint8_t)val; 918 buf[1] = (uint8_t)(val >> 8); 919 urtwn_write_region_1(sc, addr, buf, 2); 920 } 921 922 static void 923 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 924 { 925 uint8_t buf[4]; 926 927 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 928 device_xname(sc->sc_dev), __func__, addr, val)); 929 930 buf[0] = (uint8_t)val; 931 buf[1] = (uint8_t)(val >> 8); 932 buf[2] = (uint8_t)(val >> 16); 933 buf[3] = (uint8_t)(val >> 24); 934 urtwn_write_region_1(sc, addr, buf, 4); 935 } 936 937 static int 938 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 939 { 940 941 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 942 device_xname(sc->sc_dev), __func__, addr, len)); 943 944 return urtwn_write_region_1(sc, addr, buf, len); 945 } 946 947 static int 948 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 949 int len) 950 { 951 usb_device_request_t req; 952 usbd_status error; 953 954 req.bmRequestType = UT_READ_VENDOR_DEVICE; 955 req.bRequest = R92C_REQ_REGS; 956 USETW(req.wValue, addr); 957 USETW(req.wIndex, 0); 958 USETW(req.wLength, len); 959 error = usbd_do_request(sc->sc_udev, &req, buf); 960 if (error != USBD_NORMAL_COMPLETION) { 961 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 962 device_xname(sc->sc_dev), __func__, error, addr, len)); 963 } 964 return error; 965 } 966 967 static uint8_t 968 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 969 { 970 uint8_t val; 971 972 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 973 return 0xff; 974 975 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 976 device_xname(sc->sc_dev), __func__, addr, val)); 977 return val; 978 } 979 980 static uint16_t 981 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 982 { 983 uint8_t buf[2]; 984 uint16_t val; 985 986 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 987 return 0xffff; 988 989 val = LE_READ_2(&buf[0]); 990 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 991 device_xname(sc->sc_dev), __func__, addr, val)); 992 return val; 993 } 994 995 static uint32_t 996 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 997 { 998 uint8_t buf[4]; 999 uint32_t val; 1000 1001 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1002 return 0xffffffff; 1003 1004 val = LE_READ_4(&buf[0]); 1005 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1006 device_xname(sc->sc_dev), __func__, addr, val)); 1007 return val; 1008 } 1009 1010 static int 1011 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1012 { 1013 struct r92c_fw_cmd cmd; 1014 uint8_t *cp; 1015 int fwcur; 1016 int ntries; 1017 1018 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1019 device_xname(sc->sc_dev), __func__, id, buf, len)); 1020 1021 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1022 1023 mutex_enter(&sc->sc_fwcmd_mtx); 1024 fwcur = sc->fwcur; 1025 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1026 mutex_exit(&sc->sc_fwcmd_mtx); 1027 1028 /* Wait for current FW box to be empty. */ 1029 for (ntries = 0; ntries < 100; ntries++) { 1030 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1031 break; 1032 DELAY(10); 1033 } 1034 if (ntries == 100) { 1035 aprint_error_dev(sc->sc_dev, 1036 "could not send firmware command %d\n", id); 1037 return ETIMEDOUT; 1038 } 1039 1040 memset(&cmd, 0, sizeof(cmd)); 1041 KASSERT(len <= sizeof(cmd.msg)); 1042 memcpy(cmd.msg, buf, len); 1043 1044 /* Write the first word last since that will trigger the FW. */ 1045 cp = (uint8_t *)&cmd; 1046 cmd.id = id; 1047 if (len >= 4) { 1048 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1049 cmd.id |= R92C_CMD_FLAG_EXT; 1050 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1051 &cp[1], 2); 1052 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1053 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1054 (cp[5] << 24)); 1055 } else { 1056 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1057 &cp[4], 2); 1058 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1059 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1060 (cp[3] << 24)); 1061 } 1062 } else { 1063 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1064 } 1065 1066 return 0; 1067 } 1068 1069 static __inline void 1070 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1071 { 1072 1073 sc->sc_rf_write(sc, chain, addr, val); 1074 } 1075 1076 static void 1077 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1078 uint32_t val) 1079 { 1080 1081 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1082 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1083 } 1084 1085 static void 1086 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1087 uint32_t val) 1088 { 1089 1090 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1091 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1092 } 1093 1094 static void 1095 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1096 uint32_t val) 1097 { 1098 1099 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1100 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1101 } 1102 1103 static uint32_t 1104 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1105 { 1106 uint32_t reg[R92C_MAX_CHAINS], val; 1107 1108 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1109 if (chain != 0) { 1110 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1111 } 1112 1113 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1114 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1115 DELAY(1000); 1116 1117 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1118 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1119 R92C_HSSI_PARAM2_READ_EDGE); 1120 DELAY(1000); 1121 1122 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1123 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1124 DELAY(1000); 1125 1126 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1127 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1128 } else { 1129 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1130 } 1131 return MS(val, R92C_LSSI_READBACK_DATA); 1132 } 1133 1134 static int 1135 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1136 { 1137 int ntries; 1138 1139 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1140 1141 urtwn_write_4(sc, R92C_LLT_INIT, 1142 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1143 SM(R92C_LLT_INIT_ADDR, addr) | 1144 SM(R92C_LLT_INIT_DATA, data)); 1145 /* Wait for write operation to complete. */ 1146 for (ntries = 0; ntries < 20; ntries++) { 1147 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1148 R92C_LLT_INIT_OP_NO_ACTIVE) { 1149 /* Done */ 1150 return 0; 1151 } 1152 DELAY(5); 1153 } 1154 return ETIMEDOUT; 1155 } 1156 1157 static uint8_t 1158 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1159 { 1160 uint32_t reg; 1161 int ntries; 1162 1163 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1164 1165 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1166 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1167 reg &= ~R92C_EFUSE_CTRL_VALID; 1168 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1169 1170 /* Wait for read operation to complete. */ 1171 for (ntries = 0; ntries < 100; ntries++) { 1172 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1173 if (reg & R92C_EFUSE_CTRL_VALID) { 1174 /* Done */ 1175 return MS(reg, R92C_EFUSE_CTRL_DATA); 1176 } 1177 DELAY(5); 1178 } 1179 aprint_error_dev(sc->sc_dev, 1180 "could not read efuse byte at address 0x%04x\n", addr); 1181 return 0xff; 1182 } 1183 1184 static void 1185 urtwn_efuse_read(struct urtwn_softc *sc) 1186 { 1187 uint8_t *rom = (uint8_t *)&sc->rom; 1188 uint32_t reg; 1189 uint16_t addr = 0; 1190 uint8_t off, msk; 1191 size_t i; 1192 1193 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1194 1195 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1196 1197 urtwn_efuse_switch_power(sc); 1198 1199 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1200 while (addr < 512) { 1201 reg = urtwn_efuse_read_1(sc, addr); 1202 if (reg == 0xff) 1203 break; 1204 addr++; 1205 off = reg >> 4; 1206 msk = reg & 0xf; 1207 for (i = 0; i < 4; i++) { 1208 if (msk & (1U << i)) 1209 continue; 1210 1211 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1212 addr++; 1213 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1214 addr++; 1215 } 1216 } 1217 #ifdef URTWN_DEBUG 1218 if (urtwn_debug & DBG_INIT) { 1219 /* Dump ROM content. */ 1220 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1221 for (i = 0; i < (int)sizeof(sc->rom); i++) 1222 printf(":%02x", rom[i]); 1223 printf("\n"); 1224 } 1225 #endif 1226 } 1227 1228 static void 1229 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1230 { 1231 uint32_t reg; 1232 1233 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1234 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1235 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1236 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1237 } 1238 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1239 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1240 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1241 reg | R92C_SYS_FUNC_EN_ELDR); 1242 } 1243 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1244 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1245 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1246 urtwn_write_2(sc, R92C_SYS_CLKR, 1247 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1248 } 1249 } 1250 1251 static int 1252 urtwn_read_chipid(struct urtwn_softc *sc) 1253 { 1254 uint32_t reg; 1255 1256 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1257 1258 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1259 ISSET(sc->chip, URTWN_CHIP_92EU)) 1260 return 0; 1261 1262 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1263 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1264 /* test chip, not supported */ 1265 return EIO; 1266 } 1267 if (reg & R92C_SYS_CFG_TYPE_92C) { 1268 sc->chip |= URTWN_CHIP_92C; 1269 /* Check if it is a castrated 8192C. */ 1270 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1271 R92C_HPON_FSM_CHIP_BONDING_ID) == 1272 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1273 sc->chip |= URTWN_CHIP_92C_1T2R; 1274 } 1275 } 1276 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1277 sc->chip |= URTWN_CHIP_UMC; 1278 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1279 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1280 } 1281 } 1282 return 0; 1283 } 1284 1285 #ifdef URTWN_DEBUG 1286 static void 1287 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1288 { 1289 1290 aprint_normal_dev(sc->sc_dev, 1291 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1292 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1293 1294 aprint_normal_dev(sc->sc_dev, 1295 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1296 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1297 1298 aprint_normal_dev(sc->sc_dev, 1299 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1300 rp->macaddr[0], rp->macaddr[1], 1301 rp->macaddr[2], rp->macaddr[3], 1302 rp->macaddr[4], rp->macaddr[5]); 1303 1304 aprint_normal_dev(sc->sc_dev, 1305 "string %s, subcustomer_id 0x%x\n", 1306 rp->string, rp->subcustomer_id); 1307 1308 aprint_normal_dev(sc->sc_dev, 1309 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1310 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1311 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1312 1313 aprint_normal_dev(sc->sc_dev, 1314 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1315 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1316 rp->ht40_1s_tx_pwr[0][2], 1317 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1318 rp->ht40_1s_tx_pwr[1][2]); 1319 1320 aprint_normal_dev(sc->sc_dev, 1321 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1322 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1323 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1324 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1325 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1326 1327 aprint_normal_dev(sc->sc_dev, 1328 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1329 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1330 rp->ht20_tx_pwr_diff[2] & 0xf, 1331 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1332 rp->ht20_tx_pwr_diff[2] >> 4); 1333 1334 aprint_normal_dev(sc->sc_dev, 1335 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1336 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1337 rp->ofdm_tx_pwr_diff[2] & 0xf, 1338 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1339 rp->ofdm_tx_pwr_diff[2] >> 4); 1340 1341 aprint_normal_dev(sc->sc_dev, 1342 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1343 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1344 rp->ht40_max_pwr[2] & 0xf, 1345 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1346 rp->ht40_max_pwr[2] >> 4); 1347 1348 aprint_normal_dev(sc->sc_dev, 1349 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1350 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1351 rp->ht20_max_pwr[2] & 0xf, 1352 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1353 rp->ht20_max_pwr[2] >> 4); 1354 1355 aprint_normal_dev(sc->sc_dev, 1356 "xtal_calib %d, tssi %d %d, thermal %d\n", 1357 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1358 1359 aprint_normal_dev(sc->sc_dev, 1360 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1361 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1362 1363 aprint_normal_dev(sc->sc_dev, 1364 "channnel_plan %d, version %d customer_id 0x%x\n", 1365 rp->channel_plan, rp->version, rp->curstomer_id); 1366 } 1367 #endif 1368 1369 static void 1370 urtwn_read_rom(struct urtwn_softc *sc) 1371 { 1372 struct ieee80211com *ic = &sc->sc_ic; 1373 struct r92c_rom *rom = &sc->rom; 1374 1375 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1376 1377 mutex_enter(&sc->sc_write_mtx); 1378 1379 /* Read full ROM image. */ 1380 urtwn_efuse_read(sc); 1381 #ifdef URTWN_DEBUG 1382 if (urtwn_debug & DBG_REG) 1383 urtwn_dump_rom(sc, rom); 1384 #endif 1385 1386 /* XXX Weird but this is what the vendor driver does. */ 1387 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1388 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1389 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1390 1391 DPRINTFN(DBG_INIT, 1392 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1393 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1394 sc->board_type, sc->regulatory)); 1395 1396 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1397 1398 sc->sc_rf_write = urtwn_r92c_rf_write; 1399 sc->sc_power_on = urtwn_r92c_power_on; 1400 sc->sc_dma_init = urtwn_r92c_dma_init; 1401 1402 mutex_exit(&sc->sc_write_mtx); 1403 } 1404 1405 static void 1406 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1407 { 1408 struct ieee80211com *ic = &sc->sc_ic; 1409 uint8_t *rom = sc->r88e_rom; 1410 uint32_t reg; 1411 uint16_t addr = 0; 1412 uint8_t off, msk, tmp; 1413 int i; 1414 1415 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1416 1417 mutex_enter(&sc->sc_write_mtx); 1418 1419 off = 0; 1420 urtwn_efuse_switch_power(sc); 1421 1422 /* Read full ROM image. */ 1423 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1424 while (addr < 4096) { 1425 reg = urtwn_efuse_read_1(sc, addr); 1426 if (reg == 0xff) 1427 break; 1428 addr++; 1429 if ((reg & 0x1f) == 0x0f) { 1430 tmp = (reg & 0xe0) >> 5; 1431 reg = urtwn_efuse_read_1(sc, addr); 1432 if ((reg & 0x0f) != 0x0f) 1433 off = ((reg & 0xf0) >> 1) | tmp; 1434 addr++; 1435 } else 1436 off = reg >> 4; 1437 msk = reg & 0xf; 1438 for (i = 0; i < 4; i++) { 1439 if (msk & (1 << i)) 1440 continue; 1441 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1442 addr++; 1443 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1444 addr++; 1445 } 1446 } 1447 #ifdef URTWN_DEBUG 1448 if (urtwn_debug & DBG_REG) { 1449 } 1450 #endif 1451 1452 addr = 0x10; 1453 for (i = 0; i < 6; i++) 1454 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1455 for (i = 0; i < 5; i++) 1456 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1457 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1458 if (sc->bw20_tx_pwr_diff & 0x08) 1459 sc->bw20_tx_pwr_diff |= 0xf0; 1460 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1461 if (sc->ofdm_tx_pwr_diff & 0x08) 1462 sc->ofdm_tx_pwr_diff |= 0xf0; 1463 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1464 1465 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1466 1467 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1468 sc->sc_power_on = urtwn_r92e_power_on; 1469 sc->sc_rf_write = urtwn_r92e_rf_write; 1470 } else { 1471 sc->sc_power_on = urtwn_r88e_power_on; 1472 sc->sc_rf_write = urtwn_r88e_rf_write; 1473 } 1474 sc->sc_dma_init = urtwn_r88e_dma_init; 1475 1476 mutex_exit(&sc->sc_write_mtx); 1477 } 1478 1479 static int 1480 urtwn_media_change(struct ifnet *ifp) 1481 { 1482 #ifdef URTWN_DEBUG 1483 struct urtwn_softc *sc = ifp->if_softc; 1484 #endif 1485 int error; 1486 1487 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1488 1489 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1490 return error; 1491 1492 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1493 (IFF_UP | IFF_RUNNING)) { 1494 urtwn_init(ifp); 1495 } 1496 return 0; 1497 } 1498 1499 /* 1500 * Initialize rate adaptation in firmware. 1501 */ 1502 static int 1503 urtwn_ra_init(struct urtwn_softc *sc) 1504 { 1505 static const uint8_t map[] = { 1506 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1507 }; 1508 struct ieee80211com *ic = &sc->sc_ic; 1509 struct ieee80211_node *ni = ic->ic_bss; 1510 struct ieee80211_rateset *rs = &ni->ni_rates; 1511 struct r92c_fw_cmd_macid_cfg cmd; 1512 uint32_t rates, basicrates; 1513 uint32_t mask, rrsr_mask, rrsr_rate; 1514 uint8_t mode; 1515 size_t maxrate, maxbasicrate, i, j; 1516 int error; 1517 1518 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1519 1520 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1521 1522 /* Get normal and basic rates mask. */ 1523 rates = basicrates = 1; 1524 maxrate = maxbasicrate = 0; 1525 for (i = 0; i < rs->rs_nrates; i++) { 1526 /* Convert 802.11 rate to HW rate index. */ 1527 for (j = 0; j < __arraycount(map); j++) { 1528 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1529 break; 1530 } 1531 } 1532 if (j == __arraycount(map)) { 1533 /* Unknown rate, skip. */ 1534 continue; 1535 } 1536 1537 rates |= 1U << j; 1538 if (j > maxrate) { 1539 maxrate = j; 1540 } 1541 1542 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1543 basicrates |= 1U << j; 1544 if (j > maxbasicrate) { 1545 maxbasicrate = j; 1546 } 1547 } 1548 } 1549 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1550 mode = R92C_RAID_11B; 1551 } else { 1552 mode = R92C_RAID_11BG; 1553 } 1554 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1555 "maxrate=%zx, maxbasicrate=%zx\n", 1556 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1557 maxrate, maxbasicrate)); 1558 1559 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1560 maxbasicrate |= R92C_RATE_SHORTGI; 1561 maxrate |= R92C_RATE_SHORTGI; 1562 } 1563 1564 /* Set rates mask for group addressed frames. */ 1565 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1566 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1567 cmd.macid |= URTWN_MACID_SHORTGI; 1568 1569 mask = (mode << 28) | basicrates; 1570 cmd.mask[0] = (uint8_t)mask; 1571 cmd.mask[1] = (uint8_t)(mask >> 8); 1572 cmd.mask[2] = (uint8_t)(mask >> 16); 1573 cmd.mask[3] = (uint8_t)(mask >> 24); 1574 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1575 if (error != 0) { 1576 aprint_error_dev(sc->sc_dev, 1577 "could not add broadcast station\n"); 1578 return error; 1579 } 1580 /* Set initial MRR rate. */ 1581 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1582 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1583 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1584 1585 /* Set rates mask for unicast frames. */ 1586 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1587 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1588 cmd.macid |= URTWN_MACID_SHORTGI; 1589 1590 mask = (mode << 28) | rates; 1591 cmd.mask[0] = (uint8_t)mask; 1592 cmd.mask[1] = (uint8_t)(mask >> 8); 1593 cmd.mask[2] = (uint8_t)(mask >> 16); 1594 cmd.mask[3] = (uint8_t)(mask >> 24); 1595 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1596 if (error != 0) { 1597 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1598 return error; 1599 } 1600 /* Set initial MRR rate. */ 1601 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1602 __func__, maxrate)); 1603 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1604 1605 rrsr_rate = ic->ic_fixed_rate; 1606 if (rrsr_rate == -1) 1607 rrsr_rate = 11; 1608 1609 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1610 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1611 1612 /* Indicate highest supported rate. */ 1613 ni->ni_txrate = rs->rs_nrates - 1; 1614 1615 return 0; 1616 } 1617 1618 static int 1619 urtwn_get_nettype(struct urtwn_softc *sc) 1620 { 1621 struct ieee80211com *ic = &sc->sc_ic; 1622 int type; 1623 1624 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1625 1626 switch (ic->ic_opmode) { 1627 case IEEE80211_M_STA: 1628 type = R92C_CR_NETTYPE_INFRA; 1629 break; 1630 1631 case IEEE80211_M_IBSS: 1632 type = R92C_CR_NETTYPE_ADHOC; 1633 break; 1634 1635 default: 1636 type = R92C_CR_NETTYPE_NOLINK; 1637 break; 1638 } 1639 1640 return type; 1641 } 1642 1643 static void 1644 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1645 { 1646 uint8_t reg; 1647 1648 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1649 __func__, type)); 1650 1651 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1652 1653 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1654 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1655 } 1656 1657 static void 1658 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1659 { 1660 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1661 uint64_t tsf; 1662 1663 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1664 1665 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1666 1667 /* Enable TSF synchronization. */ 1668 urtwn_write_1(sc, R92C_BCN_CTRL, 1669 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1670 1671 /* Correct TSF */ 1672 urtwn_write_1(sc, R92C_BCN_CTRL, 1673 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1674 1675 /* Set initial TSF. */ 1676 tsf = ni->ni_tstamp.tsf; 1677 tsf = le64toh(tsf); 1678 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1679 tsf -= IEEE80211_DUR_TU; 1680 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1681 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1682 1683 urtwn_write_1(sc, R92C_BCN_CTRL, 1684 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1685 } 1686 1687 static void 1688 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1689 { 1690 uint8_t reg; 1691 1692 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1693 __func__, led, on)); 1694 1695 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1696 1697 if (led == URTWN_LED_LINK) { 1698 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1699 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1700 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1701 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1702 (R92C_LEDCFG0_DIS << 1)); 1703 if (on) { 1704 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1705 R92E_LEDSON; 1706 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1707 } 1708 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1709 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1710 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1711 if (!on) { 1712 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1713 urtwn_write_1(sc, R92C_LEDCFG2, 1714 reg | R92C_LEDCFG0_DIS); 1715 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1716 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1717 reg & 0xfe); 1718 } 1719 } else { 1720 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1721 if (!on) { 1722 reg |= R92C_LEDCFG0_DIS; 1723 } 1724 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1725 } 1726 sc->ledlink = on; /* Save LED state. */ 1727 } 1728 } 1729 1730 static void 1731 urtwn_calib_to(void *arg) 1732 { 1733 struct urtwn_softc *sc = arg; 1734 1735 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1736 1737 if (sc->sc_dying) 1738 return; 1739 1740 /* Do it in a process context. */ 1741 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1742 } 1743 1744 /* ARGSUSED */ 1745 static void 1746 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1747 { 1748 struct r92c_fw_cmd_rssi cmd; 1749 struct r92e_fw_cmd_rssi cmde; 1750 1751 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1752 1753 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1754 goto restart_timer; 1755 1756 mutex_enter(&sc->sc_write_mtx); 1757 if (sc->avg_pwdb != -1) { 1758 /* Indicate Rx signal strength to FW for rate adaptation. */ 1759 memset(&cmd, 0, sizeof(cmd)); 1760 memset(&cmde, 0, sizeof(cmde)); 1761 cmd.macid = 0; /* BSS. */ 1762 cmde.macid = 0; /* BSS. */ 1763 cmd.pwdb = sc->avg_pwdb; 1764 cmde.pwdb = sc->avg_pwdb; 1765 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1766 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1767 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1768 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1769 sizeof(cmd)); 1770 } else { 1771 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1772 sizeof(cmde)); 1773 } 1774 } 1775 1776 /* Do temperature compensation. */ 1777 urtwn_temp_calib(sc); 1778 mutex_exit(&sc->sc_write_mtx); 1779 1780 restart_timer: 1781 if (!sc->sc_dying) { 1782 /* Restart calibration timer. */ 1783 callout_schedule(&sc->sc_calib_to, hz); 1784 } 1785 } 1786 1787 static void 1788 urtwn_next_scan(void *arg) 1789 { 1790 struct urtwn_softc *sc = arg; 1791 int s; 1792 1793 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1794 1795 if (sc->sc_dying) 1796 return; 1797 1798 s = splnet(); 1799 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1800 ieee80211_next_scan(&sc->sc_ic); 1801 splx(s); 1802 } 1803 1804 static void 1805 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1806 { 1807 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1808 ether_sprintf(ni->ni_macaddr))); 1809 /* start with lowest Tx rate */ 1810 ni->ni_txrate = 0; 1811 } 1812 1813 static int 1814 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1815 { 1816 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1817 struct urtwn_cmd_newstate cmd; 1818 1819 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1820 device_xname(sc->sc_dev), __func__, 1821 ieee80211_state_name[nstate], nstate, arg)); 1822 1823 callout_stop(&sc->sc_scan_to); 1824 callout_stop(&sc->sc_calib_to); 1825 1826 /* Do it in a process context. */ 1827 cmd.state = nstate; 1828 cmd.arg = arg; 1829 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1830 return 0; 1831 } 1832 1833 static void 1834 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1835 { 1836 struct urtwn_cmd_newstate *cmd = arg; 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 struct ieee80211_node *ni; 1839 enum ieee80211_state ostate = ic->ic_state; 1840 enum ieee80211_state nstate = cmd->state; 1841 uint32_t reg; 1842 uint8_t sifs_time, msr; 1843 int s; 1844 1845 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1846 device_xname(sc->sc_dev), __func__, 1847 ieee80211_state_name[ostate], ostate, 1848 ieee80211_state_name[nstate], nstate)); 1849 1850 s = splnet(); 1851 mutex_enter(&sc->sc_write_mtx); 1852 1853 callout_stop(&sc->sc_scan_to); 1854 callout_stop(&sc->sc_calib_to); 1855 1856 switch (ostate) { 1857 case IEEE80211_S_INIT: 1858 break; 1859 1860 case IEEE80211_S_SCAN: 1861 if (nstate != IEEE80211_S_SCAN) { 1862 /* 1863 * End of scanning 1864 */ 1865 /* flush 4-AC Queue after site_survey */ 1866 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1867 1868 /* Allow Rx from our BSSID only. */ 1869 urtwn_write_4(sc, R92C_RCR, 1870 urtwn_read_4(sc, R92C_RCR) | 1871 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1872 } 1873 break; 1874 1875 case IEEE80211_S_AUTH: 1876 case IEEE80211_S_ASSOC: 1877 break; 1878 1879 case IEEE80211_S_RUN: 1880 /* Turn link LED off. */ 1881 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1882 1883 /* Set media status to 'No Link'. */ 1884 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1885 1886 /* Stop Rx of data frames. */ 1887 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1888 1889 /* Reset TSF. */ 1890 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1891 1892 /* Disable TSF synchronization. */ 1893 urtwn_write_1(sc, R92C_BCN_CTRL, 1894 urtwn_read_1(sc, R92C_BCN_CTRL) | 1895 R92C_BCN_CTRL_DIS_TSF_UDT0); 1896 1897 /* Back to 20MHz mode */ 1898 urtwn_set_chan(sc, ic->ic_curchan, 1899 IEEE80211_HTINFO_2NDCHAN_NONE); 1900 1901 if (ic->ic_opmode == IEEE80211_M_IBSS || 1902 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1903 /* Stop BCN */ 1904 urtwn_write_1(sc, R92C_BCN_CTRL, 1905 urtwn_read_1(sc, R92C_BCN_CTRL) & 1906 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1907 } 1908 1909 /* Reset EDCA parameters. */ 1910 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1911 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1912 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1913 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1914 1915 /* flush all cam entries */ 1916 urtwn_cam_init(sc); 1917 break; 1918 } 1919 1920 switch (nstate) { 1921 case IEEE80211_S_INIT: 1922 /* Turn link LED off. */ 1923 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1924 break; 1925 1926 case IEEE80211_S_SCAN: 1927 if (ostate != IEEE80211_S_SCAN) { 1928 /* 1929 * Begin of scanning 1930 */ 1931 1932 /* Set gain for scanning. */ 1933 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1934 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1935 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1936 1937 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1938 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1939 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1940 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1941 } 1942 1943 /* Set media status to 'No Link'. */ 1944 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1945 1946 /* Allow Rx from any BSSID. */ 1947 urtwn_write_4(sc, R92C_RCR, 1948 urtwn_read_4(sc, R92C_RCR) & 1949 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1950 1951 /* Stop Rx of data frames. */ 1952 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1953 1954 /* Disable update TSF */ 1955 urtwn_write_1(sc, R92C_BCN_CTRL, 1956 urtwn_read_1(sc, R92C_BCN_CTRL) | 1957 R92C_BCN_CTRL_DIS_TSF_UDT0); 1958 } 1959 1960 /* Make link LED blink during scan. */ 1961 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1962 1963 /* Pause AC Tx queues. */ 1964 urtwn_write_1(sc, R92C_TXPAUSE, 1965 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1966 1967 urtwn_set_chan(sc, ic->ic_curchan, 1968 IEEE80211_HTINFO_2NDCHAN_NONE); 1969 1970 /* Start periodic scan. */ 1971 if (!sc->sc_dying) 1972 callout_schedule(&sc->sc_scan_to, hz / 5); 1973 break; 1974 1975 case IEEE80211_S_AUTH: 1976 /* Set initial gain under link. */ 1977 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1978 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1979 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1980 1981 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1982 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1983 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1984 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1985 } 1986 1987 /* Set media status to 'No Link'. */ 1988 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1989 1990 /* Allow Rx from any BSSID. */ 1991 urtwn_write_4(sc, R92C_RCR, 1992 urtwn_read_4(sc, R92C_RCR) & 1993 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1994 1995 urtwn_set_chan(sc, ic->ic_curchan, 1996 IEEE80211_HTINFO_2NDCHAN_NONE); 1997 break; 1998 1999 case IEEE80211_S_ASSOC: 2000 break; 2001 2002 case IEEE80211_S_RUN: 2003 ni = ic->ic_bss; 2004 2005 /* XXX: Set 20MHz mode */ 2006 urtwn_set_chan(sc, ic->ic_curchan, 2007 IEEE80211_HTINFO_2NDCHAN_NONE); 2008 2009 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2010 /* Back to 20MHz mode */ 2011 urtwn_set_chan(sc, ic->ic_curchan, 2012 IEEE80211_HTINFO_2NDCHAN_NONE); 2013 2014 /* Set media status to 'No Link'. */ 2015 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2016 2017 /* Enable Rx of data frames. */ 2018 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2019 2020 /* Allow Rx from any BSSID. */ 2021 urtwn_write_4(sc, R92C_RCR, 2022 urtwn_read_4(sc, R92C_RCR) & 2023 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2024 2025 /* Accept Rx data/control/management frames */ 2026 urtwn_write_4(sc, R92C_RCR, 2027 urtwn_read_4(sc, R92C_RCR) | 2028 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2029 2030 /* Turn link LED on. */ 2031 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2032 break; 2033 } 2034 2035 /* Set media status to 'Associated'. */ 2036 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2037 2038 /* Set BSSID. */ 2039 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2040 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2041 2042 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2043 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2044 } else { 2045 /* 802.11b/g */ 2046 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2047 } 2048 2049 /* Enable Rx of data frames. */ 2050 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2051 2052 /* Set beacon interval. */ 2053 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2054 2055 msr = urtwn_read_1(sc, R92C_MSR); 2056 msr &= R92C_MSR_MASK; 2057 switch (ic->ic_opmode) { 2058 case IEEE80211_M_STA: 2059 /* Allow Rx from our BSSID only. */ 2060 urtwn_write_4(sc, R92C_RCR, 2061 urtwn_read_4(sc, R92C_RCR) | 2062 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2063 2064 /* Enable TSF synchronization. */ 2065 urtwn_tsf_sync_enable(sc); 2066 2067 msr |= R92C_MSR_INFRA; 2068 break; 2069 case IEEE80211_M_HOSTAP: 2070 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2071 2072 /* Allow Rx from any BSSID. */ 2073 urtwn_write_4(sc, R92C_RCR, 2074 urtwn_read_4(sc, R92C_RCR) & 2075 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2076 2077 /* Reset TSF timer to zero. */ 2078 reg = urtwn_read_4(sc, R92C_TCR); 2079 reg &= ~0x01; 2080 urtwn_write_4(sc, R92C_TCR, reg); 2081 reg |= 0x01; 2082 urtwn_write_4(sc, R92C_TCR, reg); 2083 2084 msr |= R92C_MSR_AP; 2085 break; 2086 default: 2087 msr |= R92C_MSR_ADHOC; 2088 break; 2089 } 2090 urtwn_write_1(sc, R92C_MSR, msr); 2091 2092 sifs_time = 10; 2093 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2094 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2095 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2096 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2097 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2098 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2099 2100 /* Intialize rate adaptation. */ 2101 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2102 ISSET(sc->chip, URTWN_CHIP_92EU)) 2103 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2104 else 2105 urtwn_ra_init(sc); 2106 2107 /* Turn link LED on. */ 2108 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2109 2110 /* Reset average RSSI. */ 2111 sc->avg_pwdb = -1; 2112 2113 /* Reset temperature calibration state machine. */ 2114 sc->thcal_state = 0; 2115 sc->thcal_lctemp = 0; 2116 2117 /* Start periodic calibration. */ 2118 if (!sc->sc_dying) 2119 callout_schedule(&sc->sc_calib_to, hz); 2120 break; 2121 } 2122 2123 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2124 2125 mutex_exit(&sc->sc_write_mtx); 2126 splx(s); 2127 } 2128 2129 static int 2130 urtwn_wme_update(struct ieee80211com *ic) 2131 { 2132 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2133 2134 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2135 2136 /* don't override default WME values if WME is not actually enabled */ 2137 if (!(ic->ic_flags & IEEE80211_F_WME)) 2138 return 0; 2139 2140 /* Do it in a process context. */ 2141 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2142 return 0; 2143 } 2144 2145 static void 2146 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2147 { 2148 static const uint16_t ac2reg[WME_NUM_AC] = { 2149 R92C_EDCA_BE_PARAM, 2150 R92C_EDCA_BK_PARAM, 2151 R92C_EDCA_VI_PARAM, 2152 R92C_EDCA_VO_PARAM 2153 }; 2154 struct ieee80211com *ic = &sc->sc_ic; 2155 const struct wmeParams *wmep; 2156 int ac, aifs, slottime; 2157 int s; 2158 2159 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2160 __func__)); 2161 2162 s = splnet(); 2163 mutex_enter(&sc->sc_write_mtx); 2164 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2165 for (ac = 0; ac < WME_NUM_AC; ac++) { 2166 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2167 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2168 aifs = wmep->wmep_aifsn * slottime + 10; 2169 urtwn_write_4(sc, ac2reg[ac], 2170 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2171 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2172 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2173 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2174 } 2175 mutex_exit(&sc->sc_write_mtx); 2176 splx(s); 2177 } 2178 2179 static void 2180 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2181 { 2182 int pwdb; 2183 2184 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2185 device_xname(sc->sc_dev), __func__, rate, rssi)); 2186 2187 /* Convert antenna signal to percentage. */ 2188 if (rssi <= -100 || rssi >= 20) 2189 pwdb = 0; 2190 else if (rssi >= 0) 2191 pwdb = 100; 2192 else 2193 pwdb = 100 + rssi; 2194 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2195 if (rate <= 3) { 2196 /* CCK gain is smaller than OFDM/MCS gain. */ 2197 pwdb += 6; 2198 if (pwdb > 100) 2199 pwdb = 100; 2200 if (pwdb <= 14) 2201 pwdb -= 4; 2202 else if (pwdb <= 26) 2203 pwdb -= 8; 2204 else if (pwdb <= 34) 2205 pwdb -= 6; 2206 else if (pwdb <= 42) 2207 pwdb -= 2; 2208 } 2209 } 2210 if (sc->avg_pwdb == -1) /* Init. */ 2211 sc->avg_pwdb = pwdb; 2212 else if (sc->avg_pwdb < pwdb) 2213 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2214 else 2215 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2216 2217 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2218 device_xname(sc->sc_dev), __func__, 2219 rate, rssi, pwdb, sc->avg_pwdb)); 2220 } 2221 2222 static int8_t 2223 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2224 { 2225 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2226 struct r92c_rx_phystat *phy; 2227 struct r92c_rx_cck *cck; 2228 uint8_t rpt; 2229 int8_t rssi; 2230 2231 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2232 __func__, rate)); 2233 2234 if (rate <= 3) { 2235 cck = (struct r92c_rx_cck *)physt; 2236 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2237 rpt = (cck->agc_rpt >> 5) & 0x3; 2238 rssi = (cck->agc_rpt & 0x1f) << 1; 2239 } else { 2240 rpt = (cck->agc_rpt >> 6) & 0x3; 2241 rssi = cck->agc_rpt & 0x3e; 2242 } 2243 rssi = cckoff[rpt] - rssi; 2244 } else { /* OFDM/HT. */ 2245 phy = (struct r92c_rx_phystat *)physt; 2246 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2247 } 2248 return rssi; 2249 } 2250 2251 static int8_t 2252 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2253 { 2254 struct r92c_rx_phystat *phy; 2255 struct r88e_rx_cck *cck; 2256 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2257 int8_t rssi; 2258 2259 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2260 __func__, rate)); 2261 2262 rssi = 0; 2263 if (rate <= 3) { 2264 cck = (struct r88e_rx_cck *)physt; 2265 cck_agc_rpt = cck->agc_rpt; 2266 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2267 vga_idx = cck_agc_rpt & 0x1f; 2268 switch (lna_idx) { 2269 case 7: 2270 if (vga_idx <= 27) 2271 rssi = -100 + 2* (27 - vga_idx); 2272 else 2273 rssi = -100; 2274 break; 2275 case 6: 2276 rssi = -48 + 2 * (2 - vga_idx); 2277 break; 2278 case 5: 2279 rssi = -42 + 2 * (7 - vga_idx); 2280 break; 2281 case 4: 2282 rssi = -36 + 2 * (7 - vga_idx); 2283 break; 2284 case 3: 2285 rssi = -24 + 2 * (7 - vga_idx); 2286 break; 2287 case 2: 2288 rssi = -12 + 2 * (5 - vga_idx); 2289 break; 2290 case 1: 2291 rssi = 8 - (2 * vga_idx); 2292 break; 2293 case 0: 2294 rssi = 14 - (2 * vga_idx); 2295 break; 2296 } 2297 rssi += 6; 2298 } else { /* OFDM/HT. */ 2299 phy = (struct r92c_rx_phystat *)physt; 2300 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2301 } 2302 return rssi; 2303 } 2304 2305 static void 2306 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2307 { 2308 struct ieee80211com *ic = &sc->sc_ic; 2309 struct ifnet *ifp = ic->ic_ifp; 2310 struct ieee80211_frame *wh; 2311 struct ieee80211_node *ni; 2312 struct r92c_rx_stat *stat; 2313 uint32_t rxdw0, rxdw3; 2314 struct mbuf *m; 2315 uint8_t rate; 2316 int8_t rssi = 0; 2317 int s, infosz; 2318 2319 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2320 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2321 2322 stat = (struct r92c_rx_stat *)buf; 2323 rxdw0 = le32toh(stat->rxdw0); 2324 rxdw3 = le32toh(stat->rxdw3); 2325 2326 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2327 /* 2328 * This should not happen since we setup our Rx filter 2329 * to not receive these frames. 2330 */ 2331 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2332 device_xname(sc->sc_dev), __func__)); 2333 ifp->if_ierrors++; 2334 return; 2335 } 2336 /* 2337 * XXX: This will drop most control packets. Do we really 2338 * want this in IEEE80211_M_MONITOR mode? 2339 */ 2340 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2341 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2342 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2343 device_xname(sc->sc_dev), __func__, pktlen)); 2344 ic->ic_stats.is_rx_tooshort++; 2345 ifp->if_ierrors++; 2346 return; 2347 } 2348 if (__predict_false(pktlen > MCLBYTES)) { 2349 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2350 device_xname(sc->sc_dev), __func__, pktlen)); 2351 ifp->if_ierrors++; 2352 return; 2353 } 2354 2355 rate = MS(rxdw3, R92C_RXDW3_RATE); 2356 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2357 2358 /* Get RSSI from PHY status descriptor if present. */ 2359 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2360 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2361 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2362 else 2363 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2364 /* Update our average RSSI. */ 2365 urtwn_update_avgrssi(sc, rate, rssi); 2366 } 2367 2368 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2369 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2370 2371 MGETHDR(m, M_DONTWAIT, MT_DATA); 2372 if (__predict_false(m == NULL)) { 2373 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2374 ic->ic_stats.is_rx_nobuf++; 2375 ifp->if_ierrors++; 2376 return; 2377 } 2378 if (pktlen > (int)MHLEN) { 2379 MCLGET(m, M_DONTWAIT); 2380 if (__predict_false(!(m->m_flags & M_EXT))) { 2381 aprint_error_dev(sc->sc_dev, 2382 "couldn't allocate rx mbuf cluster\n"); 2383 m_freem(m); 2384 ic->ic_stats.is_rx_nobuf++; 2385 ifp->if_ierrors++; 2386 return; 2387 } 2388 } 2389 2390 /* Finalize mbuf. */ 2391 m_set_rcvif(m, ifp); 2392 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2393 memcpy(mtod(m, uint8_t *), wh, pktlen); 2394 m->m_pkthdr.len = m->m_len = pktlen; 2395 2396 s = splnet(); 2397 if (__predict_false(sc->sc_drvbpf != NULL)) { 2398 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2399 2400 tap->wr_flags = 0; 2401 if (!(rxdw3 & R92C_RXDW3_HT)) { 2402 switch (rate) { 2403 /* CCK. */ 2404 case 0: tap->wr_rate = 2; break; 2405 case 1: tap->wr_rate = 4; break; 2406 case 2: tap->wr_rate = 11; break; 2407 case 3: tap->wr_rate = 22; break; 2408 /* OFDM. */ 2409 case 4: tap->wr_rate = 12; break; 2410 case 5: tap->wr_rate = 18; break; 2411 case 6: tap->wr_rate = 24; break; 2412 case 7: tap->wr_rate = 36; break; 2413 case 8: tap->wr_rate = 48; break; 2414 case 9: tap->wr_rate = 72; break; 2415 case 10: tap->wr_rate = 96; break; 2416 case 11: tap->wr_rate = 108; break; 2417 } 2418 } else if (rate >= 12) { /* MCS0~15. */ 2419 /* Bit 7 set means HT MCS instead of rate. */ 2420 tap->wr_rate = 0x80 | (rate - 12); 2421 } 2422 tap->wr_dbm_antsignal = rssi; 2423 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2424 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2425 2426 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2427 } 2428 2429 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2430 2431 /* push the frame up to the 802.11 stack */ 2432 ieee80211_input(ic, m, ni, rssi, 0); 2433 2434 /* Node is no longer needed. */ 2435 ieee80211_free_node(ni); 2436 2437 splx(s); 2438 } 2439 2440 static void 2441 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2442 { 2443 struct urtwn_rx_data *data = priv; 2444 struct urtwn_softc *sc = data->sc; 2445 struct r92c_rx_stat *stat; 2446 size_t pidx = data->pidx; 2447 uint32_t rxdw0; 2448 uint8_t *buf; 2449 int len, totlen, pktlen, infosz, npkts; 2450 2451 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2452 device_xname(sc->sc_dev), __func__, status)); 2453 2454 mutex_enter(&sc->sc_rx_mtx); 2455 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2456 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2457 /* Put this Rx buffer back to our free list. */ 2458 mutex_exit(&sc->sc_rx_mtx); 2459 2460 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2461 if (status == USBD_STALLED) 2462 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2463 else if (status != USBD_CANCELLED) 2464 goto resubmit; 2465 return; 2466 } 2467 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2468 2469 if (__predict_false(len < (int)sizeof(*stat))) { 2470 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2471 device_xname(sc->sc_dev), __func__, len)); 2472 goto resubmit; 2473 } 2474 buf = data->buf; 2475 2476 /* Get the number of encapsulated frames. */ 2477 stat = (struct r92c_rx_stat *)buf; 2478 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2479 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2480 device_xname(sc->sc_dev), __func__, npkts)); 2481 2482 /* Process all of them. */ 2483 while (npkts-- > 0) { 2484 if (__predict_false(len < (int)sizeof(*stat))) { 2485 DPRINTFN(DBG_RX, 2486 ("%s: %s: len(%d) is short than header\n", 2487 device_xname(sc->sc_dev), __func__, len)); 2488 break; 2489 } 2490 stat = (struct r92c_rx_stat *)buf; 2491 rxdw0 = le32toh(stat->rxdw0); 2492 2493 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2494 if (__predict_false(pktlen == 0)) { 2495 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2496 device_xname(sc->sc_dev), __func__)); 2497 break; 2498 } 2499 2500 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2501 2502 /* Make sure everything fits in xfer. */ 2503 totlen = sizeof(*stat) + infosz + pktlen; 2504 if (__predict_false(totlen > len)) { 2505 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2506 device_xname(sc->sc_dev), __func__, totlen, 2507 (int)sizeof(*stat), infosz, pktlen, len)); 2508 break; 2509 } 2510 2511 /* Process 802.11 frame. */ 2512 urtwn_rx_frame(sc, buf, pktlen); 2513 2514 /* Next chunk is 128-byte aligned. */ 2515 totlen = roundup2(totlen, 128); 2516 buf += totlen; 2517 len -= totlen; 2518 } 2519 2520 resubmit: 2521 /* Setup a new transfer. */ 2522 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2523 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2524 (void)usbd_transfer(xfer); 2525 } 2526 2527 static void 2528 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2529 { 2530 struct urtwn_tx_data *data = priv; 2531 struct urtwn_softc *sc = data->sc; 2532 struct ifnet *ifp = &sc->sc_if; 2533 size_t pidx = data->pidx; 2534 int s; 2535 2536 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2537 device_xname(sc->sc_dev), __func__, status)); 2538 2539 mutex_enter(&sc->sc_tx_mtx); 2540 /* Put this Tx buffer back to our free list. */ 2541 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2542 mutex_exit(&sc->sc_tx_mtx); 2543 2544 s = splnet(); 2545 sc->tx_timer = 0; 2546 ifp->if_flags &= ~IFF_OACTIVE; 2547 2548 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2549 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2550 if (status == USBD_STALLED) { 2551 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2552 usbd_clear_endpoint_stall_async(pipe); 2553 } 2554 printf("ERROR1\n"); 2555 ifp->if_oerrors++; 2556 } 2557 splx(s); 2558 return; 2559 } 2560 2561 ifp->if_opackets++; 2562 urtwn_start(ifp); 2563 splx(s); 2564 2565 } 2566 2567 static int 2568 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2569 struct urtwn_tx_data *data) 2570 { 2571 struct ieee80211com *ic = &sc->sc_ic; 2572 struct ieee80211_frame *wh; 2573 struct ieee80211_key *k = NULL; 2574 struct r92c_tx_desc *txd; 2575 size_t i, padsize, xferlen, txd_len; 2576 uint16_t seq, sum; 2577 uint8_t raid, type, tid; 2578 int s, hasqos, error; 2579 2580 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2581 2582 wh = mtod(m, struct ieee80211_frame *); 2583 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2584 txd_len = sizeof(*txd); 2585 2586 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2587 txd_len = 32; 2588 2589 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2590 k = ieee80211_crypto_encap(ic, ni, m); 2591 if (k == NULL) 2592 return ENOBUFS; 2593 2594 /* packet header may have moved, reset our local pointer */ 2595 wh = mtod(m, struct ieee80211_frame *); 2596 } 2597 2598 if (__predict_false(sc->sc_drvbpf != NULL)) { 2599 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2600 2601 tap->wt_flags = 0; 2602 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2603 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2604 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2605 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2606 2607 /* XXX: set tap->wt_rate? */ 2608 2609 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2610 } 2611 2612 /* non-qos data frames */ 2613 tid = R92C_TXDW1_QSEL_BE; 2614 if ((hasqos = ieee80211_has_qos(wh))) { 2615 /* data frames in 11n mode */ 2616 struct ieee80211_qosframe *qwh = (void *)wh; 2617 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2618 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2619 tid = R92C_TXDW1_QSEL_MGNT; 2620 } 2621 2622 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2623 padsize = 8; 2624 else 2625 padsize = 0; 2626 2627 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2628 padsize = 0; 2629 2630 /* Fill Tx descriptor. */ 2631 txd = (struct r92c_tx_desc *)data->buf; 2632 memset(txd, 0, txd_len + padsize); 2633 2634 txd->txdw0 |= htole32( 2635 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2636 SM(R92C_TXDW0_OFFSET, txd_len)); 2637 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2638 txd->txdw0 |= htole32( 2639 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2640 } 2641 2642 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2643 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2644 2645 /* fix pad field */ 2646 if (padsize > 0) { 2647 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2648 device_xname(sc->sc_dev), __func__, padsize)); 2649 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2650 } 2651 2652 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2653 type == IEEE80211_FC0_TYPE_DATA) { 2654 if (ic->ic_curmode == IEEE80211_MODE_11B) 2655 raid = R92C_RAID_11B; 2656 else 2657 raid = R92C_RAID_11BG; 2658 DPRINTFN(DBG_TX, 2659 ("%s: %s: data packet: tid=%d, raid=%d\n", 2660 device_xname(sc->sc_dev), __func__, tid, raid)); 2661 2662 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2663 txd->txdw1 |= htole32( 2664 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2665 SM(R92C_TXDW1_QSEL, tid) | 2666 SM(R92C_TXDW1_RAID, raid) | 2667 R92C_TXDW1_AGGBK); 2668 } else 2669 txd->txdw1 |= htole32( 2670 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2671 SM(R92C_TXDW1_QSEL, tid) | 2672 SM(R92C_TXDW1_RAID, raid) | 2673 R92C_TXDW1_AGGBK); 2674 2675 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2676 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2677 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2678 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2679 2680 if (hasqos) { 2681 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2682 } 2683 2684 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2685 /* for 11g */ 2686 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2687 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2688 R92C_TXDW4_HWRTSEN); 2689 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2690 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2691 R92C_TXDW4_HWRTSEN); 2692 } 2693 } 2694 /* Send RTS at OFDM24. */ 2695 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2696 txd->txdw5 |= htole32(0x0001ff00); 2697 /* Send data at OFDM54. */ 2698 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2699 txd->txdw5 |= htole32(0x13 & 0x3f); 2700 else 2701 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2702 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2703 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2704 device_xname(sc->sc_dev), __func__)); 2705 txd->txdw1 |= htole32( 2706 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2707 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2708 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2709 2710 /* Force CCK1. */ 2711 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2712 /* Use 1Mbps */ 2713 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2714 } else { 2715 /* broadcast or multicast packets */ 2716 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2717 device_xname(sc->sc_dev), __func__)); 2718 txd->txdw1 |= htole32( 2719 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2720 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2721 2722 /* Force CCK1. */ 2723 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2724 /* Use 1Mbps */ 2725 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2726 } 2727 /* Set sequence number */ 2728 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2729 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2730 txd->txdseq |= htole16(seq); 2731 2732 if (!hasqos) { 2733 /* Use HW sequence numbering for non-QoS frames. */ 2734 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2735 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2736 } 2737 } else { 2738 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2739 R92E_HWSEQ_SHIFT); 2740 if (!hasqos) { 2741 /* Use HW sequence numbering for non-QoS frames. */ 2742 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2743 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2744 } 2745 } 2746 2747 /* Compute Tx descriptor checksum. */ 2748 sum = 0; 2749 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2750 sum ^= ((uint16_t *)txd)[i]; 2751 txd->txdsum = sum; /* NB: already little endian. */ 2752 2753 xferlen = txd_len + m->m_pkthdr.len + padsize; 2754 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2755 2756 s = splnet(); 2757 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2758 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2759 urtwn_txeof); 2760 error = usbd_transfer(data->xfer); 2761 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2762 error != USBD_IN_PROGRESS)) { 2763 splx(s); 2764 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2765 device_xname(sc->sc_dev), __func__, error)); 2766 return error; 2767 } 2768 splx(s); 2769 return 0; 2770 } 2771 2772 struct urtwn_tx_data * 2773 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2774 { 2775 struct urtwn_tx_data *data = NULL; 2776 2777 mutex_enter(&sc->sc_tx_mtx); 2778 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2779 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2780 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2781 } 2782 mutex_exit(&sc->sc_tx_mtx); 2783 2784 return data; 2785 } 2786 2787 static void 2788 urtwn_start(struct ifnet *ifp) 2789 { 2790 struct urtwn_softc *sc = ifp->if_softc; 2791 struct ieee80211com *ic = &sc->sc_ic; 2792 struct urtwn_tx_data *data; 2793 struct ether_header *eh; 2794 struct ieee80211_node *ni; 2795 struct mbuf *m; 2796 2797 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2798 2799 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2800 return; 2801 2802 data = NULL; 2803 for (;;) { 2804 /* Send pending management frames first. */ 2805 IF_POLL(&ic->ic_mgtq, m); 2806 if (m != NULL) { 2807 /* Use AC_VO for management frames. */ 2808 2809 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2810 2811 if (data == NULL) { 2812 ifp->if_flags |= IFF_OACTIVE; 2813 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2814 device_xname(sc->sc_dev))); 2815 return; 2816 } 2817 IF_DEQUEUE(&ic->ic_mgtq, m); 2818 ni = M_GETCTX(m, struct ieee80211_node *); 2819 M_CLEARCTX(m); 2820 goto sendit; 2821 } 2822 if (ic->ic_state != IEEE80211_S_RUN) 2823 break; 2824 2825 /* Encapsulate and send data frames. */ 2826 IFQ_POLL(&ifp->if_snd, m); 2827 if (m == NULL) 2828 break; 2829 2830 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2831 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2832 uint8_t qid = WME_AC_BE; 2833 if (ieee80211_has_qos(wh)) { 2834 /* data frames in 11n mode */ 2835 struct ieee80211_qosframe *qwh = (void *)wh; 2836 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2837 qid = TID_TO_WME_AC(tid); 2838 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2839 qid = WME_AC_VO; 2840 } 2841 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2842 2843 if (data == NULL) { 2844 ifp->if_flags |= IFF_OACTIVE; 2845 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2846 device_xname(sc->sc_dev))); 2847 return; 2848 } 2849 IFQ_DEQUEUE(&ifp->if_snd, m); 2850 2851 if (m->m_len < (int)sizeof(*eh) && 2852 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2853 printf("ERROR6\n"); 2854 ifp->if_oerrors++; 2855 continue; 2856 } 2857 eh = mtod(m, struct ether_header *); 2858 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2859 if (ni == NULL) { 2860 m_freem(m); 2861 printf("ERROR5\n"); 2862 ifp->if_oerrors++; 2863 continue; 2864 } 2865 2866 bpf_mtap(ifp, m); 2867 2868 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2869 ieee80211_free_node(ni); 2870 printf("ERROR4\n"); 2871 ifp->if_oerrors++; 2872 continue; 2873 } 2874 sendit: 2875 bpf_mtap3(ic->ic_rawbpf, m); 2876 2877 if (urtwn_tx(sc, m, ni, data) != 0) { 2878 m_freem(m); 2879 ieee80211_free_node(ni); 2880 printf("ERROR3\n"); 2881 ifp->if_oerrors++; 2882 continue; 2883 } 2884 m_freem(m); 2885 ieee80211_free_node(ni); 2886 sc->tx_timer = 5; 2887 ifp->if_timer = 1; 2888 } 2889 } 2890 2891 static void 2892 urtwn_watchdog(struct ifnet *ifp) 2893 { 2894 struct urtwn_softc *sc = ifp->if_softc; 2895 2896 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2897 2898 ifp->if_timer = 0; 2899 2900 if (sc->tx_timer > 0) { 2901 if (--sc->tx_timer == 0) { 2902 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2903 /* urtwn_init(ifp); XXX needs a process context! */ 2904 printf("ERROR2\n"); 2905 ifp->if_oerrors++; 2906 return; 2907 } 2908 ifp->if_timer = 1; 2909 } 2910 ieee80211_watchdog(&sc->sc_ic); 2911 } 2912 2913 static int 2914 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2915 { 2916 struct urtwn_softc *sc = ifp->if_softc; 2917 struct ieee80211com *ic = &sc->sc_ic; 2918 int s, error = 0; 2919 2920 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2921 device_xname(sc->sc_dev), __func__, cmd, data)); 2922 2923 s = splnet(); 2924 2925 switch (cmd) { 2926 case SIOCSIFFLAGS: 2927 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2928 break; 2929 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2930 case IFF_UP | IFF_RUNNING: 2931 break; 2932 case IFF_UP: 2933 urtwn_init(ifp); 2934 break; 2935 case IFF_RUNNING: 2936 urtwn_stop(ifp, 1); 2937 break; 2938 case 0: 2939 break; 2940 } 2941 break; 2942 2943 case SIOCADDMULTI: 2944 case SIOCDELMULTI: 2945 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2946 /* setup multicast filter, etc */ 2947 error = 0; 2948 } 2949 break; 2950 2951 default: 2952 error = ieee80211_ioctl(ic, cmd, data); 2953 break; 2954 } 2955 if (error == ENETRESET) { 2956 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2957 (IFF_UP | IFF_RUNNING) && 2958 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2959 urtwn_init(ifp); 2960 } 2961 error = 0; 2962 } 2963 2964 splx(s); 2965 2966 return error; 2967 } 2968 2969 static __inline int 2970 urtwn_power_on(struct urtwn_softc *sc) 2971 { 2972 2973 return sc->sc_power_on(sc); 2974 } 2975 2976 static int 2977 urtwn_r92c_power_on(struct urtwn_softc *sc) 2978 { 2979 uint32_t reg; 2980 int ntries; 2981 2982 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2983 2984 KASSERT(mutex_owned(&sc->sc_write_mtx)); 2985 2986 /* Wait for autoload done bit. */ 2987 for (ntries = 0; ntries < 1000; ntries++) { 2988 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2989 break; 2990 DELAY(5); 2991 } 2992 if (ntries == 1000) { 2993 aprint_error_dev(sc->sc_dev, 2994 "timeout waiting for chip autoload\n"); 2995 return ETIMEDOUT; 2996 } 2997 2998 /* Unlock ISO/CLK/Power control register. */ 2999 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3000 /* Move SPS into PWM mode. */ 3001 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3002 DELAY(5); 3003 3004 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3005 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3006 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3007 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3008 DELAY(100); 3009 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3010 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3011 ~R92C_SYS_ISO_CTRL_MD2PP); 3012 } 3013 3014 /* Auto enable WLAN. */ 3015 urtwn_write_2(sc, R92C_APS_FSMCO, 3016 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3017 for (ntries = 0; ntries < 1000; ntries++) { 3018 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3019 R92C_APS_FSMCO_APFM_ONMAC)) 3020 break; 3021 DELAY(100); 3022 } 3023 if (ntries == 1000) { 3024 aprint_error_dev(sc->sc_dev, 3025 "timeout waiting for MAC auto ON\n"); 3026 return ETIMEDOUT; 3027 } 3028 3029 /* Enable radio, GPIO and LED functions. */ 3030 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3031 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3032 urtwn_write_2(sc, R92C_APS_FSMCO, 3033 R92C_APS_FSMCO_AFSM_HSUS | 3034 R92C_APS_FSMCO_PDN_EN | 3035 R92C_APS_FSMCO_PFM_ALDN); 3036 3037 /* Release RF digital isolation. */ 3038 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3039 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3040 3041 /* Initialize MAC. */ 3042 urtwn_write_1(sc, R92C_APSD_CTRL, 3043 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3044 for (ntries = 0; ntries < 200; ntries++) { 3045 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3046 R92C_APSD_CTRL_OFF_STATUS)) 3047 break; 3048 DELAY(5); 3049 } 3050 if (ntries == 200) { 3051 aprint_error_dev(sc->sc_dev, 3052 "timeout waiting for MAC initialization\n"); 3053 return ETIMEDOUT; 3054 } 3055 3056 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3057 reg = urtwn_read_2(sc, R92C_CR); 3058 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3059 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3060 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3061 R92C_CR_ENSEC; 3062 urtwn_write_2(sc, R92C_CR, reg); 3063 3064 urtwn_write_1(sc, 0xfe10, 0x19); 3065 return 0; 3066 } 3067 3068 static int 3069 urtwn_r92e_power_on(struct urtwn_softc *sc) 3070 { 3071 uint32_t reg; 3072 uint32_t val; 3073 int ntries; 3074 3075 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3076 3077 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3078 3079 /* Enable radio, GPIO and LED functions. */ 3080 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3081 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3082 urtwn_write_2(sc, R92C_APS_FSMCO, 3083 R92C_APS_FSMCO_AFSM_HSUS | 3084 R92C_APS_FSMCO_PDN_EN | 3085 R92C_APS_FSMCO_PFM_ALDN); 3086 3087 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3088 /* LDO. */ 3089 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3090 } 3091 else { 3092 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3093 R92C_SYS_SWR_CTRL2) & 0xffff); 3094 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3095 } 3096 3097 for (ntries = 0; ntries < 2; ntries++) { 3098 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3099 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3100 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3101 R92C_AFE_CTRL4)); 3102 } 3103 3104 /* Reset BB. */ 3105 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3106 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3107 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3108 3109 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3110 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3111 3112 /* Disable HWPDN. */ 3113 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3114 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3115 3116 /* Disable WL suspend. */ 3117 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3118 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3119 R92C_APS_FSMCO_AFSM_HSUS)); 3120 3121 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3122 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3123 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3124 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3125 for (ntries = 0; ntries < 10000; ntries++) { 3126 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3127 R92C_APS_FSMCO_APFM_ONMAC; 3128 if (val == 0x0) 3129 break; 3130 DELAY(10); 3131 } 3132 if (ntries == 10000) { 3133 aprint_error_dev(sc->sc_dev, 3134 "timeout waiting for chip power up\n"); 3135 return ETIMEDOUT; 3136 } 3137 3138 urtwn_write_2(sc, R92C_CR, 0x00); 3139 reg = urtwn_read_2(sc, R92C_CR); 3140 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3141 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3142 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3143 urtwn_write_2(sc, R92C_CR, reg); 3144 3145 return 0; 3146 } 3147 3148 static int 3149 urtwn_r88e_power_on(struct urtwn_softc *sc) 3150 { 3151 uint32_t reg; 3152 uint8_t val; 3153 int ntries; 3154 3155 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3156 3157 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3158 3159 /* Wait for power ready bit. */ 3160 for (ntries = 0; ntries < 5000; ntries++) { 3161 val = urtwn_read_1(sc, 0x6) & 0x2; 3162 if (val == 0x2) 3163 break; 3164 DELAY(10); 3165 } 3166 if (ntries == 5000) { 3167 aprint_error_dev(sc->sc_dev, 3168 "timeout waiting for chip power up\n"); 3169 return ETIMEDOUT; 3170 } 3171 3172 /* Reset BB. */ 3173 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3174 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3175 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3176 3177 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3178 3179 /* Disable HWPDN. */ 3180 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3181 3182 /* Disable WL suspend. */ 3183 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3184 3185 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3186 for (ntries = 0; ntries < 5000; ntries++) { 3187 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3188 break; 3189 DELAY(10); 3190 } 3191 if (ntries == 5000) 3192 return ETIMEDOUT; 3193 3194 /* Enable LDO normal mode. */ 3195 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3196 3197 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3198 urtwn_write_2(sc, R92C_CR, 0); 3199 reg = urtwn_read_2(sc, R92C_CR); 3200 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3201 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3202 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3203 urtwn_write_2(sc, R92C_CR, reg); 3204 3205 return 0; 3206 } 3207 3208 static int 3209 urtwn_llt_init(struct urtwn_softc *sc) 3210 { 3211 size_t i, page_count, pktbuf_count; 3212 uint32_t val; 3213 int error; 3214 3215 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3216 3217 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3218 3219 if (sc->chip & URTWN_CHIP_88E) 3220 page_count = R88E_TX_PAGE_COUNT; 3221 else if (sc->chip & URTWN_CHIP_92EU) 3222 page_count = R92E_TX_PAGE_COUNT; 3223 else 3224 page_count = R92C_TX_PAGE_COUNT; 3225 if (sc->chip & URTWN_CHIP_88E) 3226 pktbuf_count = R88E_TXPKTBUF_COUNT; 3227 else if (sc->chip & URTWN_CHIP_92EU) 3228 pktbuf_count = R88E_TXPKTBUF_COUNT; 3229 else 3230 pktbuf_count = R92C_TXPKTBUF_COUNT; 3231 3232 if (sc->chip & URTWN_CHIP_92EU) { 3233 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3234 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3235 DELAY(100); 3236 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3237 if (val & R92E_AUTO_LLT_EN) 3238 return EIO; 3239 return 0; 3240 } 3241 3242 /* Reserve pages [0; page_count]. */ 3243 for (i = 0; i < page_count; i++) { 3244 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3245 return error; 3246 } 3247 /* NB: 0xff indicates end-of-list. */ 3248 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3249 return error; 3250 /* 3251 * Use pages [page_count + 1; pktbuf_count - 1] 3252 * as ring buffer. 3253 */ 3254 for (++i; i < pktbuf_count - 1; i++) { 3255 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3256 return error; 3257 } 3258 /* Make the last page point to the beginning of the ring buffer. */ 3259 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3260 return error; 3261 } 3262 3263 static void 3264 urtwn_fw_reset(struct urtwn_softc *sc) 3265 { 3266 uint16_t reg; 3267 int ntries; 3268 3269 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3270 3271 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3272 3273 /* Tell 8051 to reset itself. */ 3274 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3275 3276 /* Wait until 8051 resets by itself. */ 3277 for (ntries = 0; ntries < 100; ntries++) { 3278 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3279 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3280 return; 3281 DELAY(50); 3282 } 3283 /* Force 8051 reset. */ 3284 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3285 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3286 } 3287 3288 static void 3289 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3290 { 3291 uint16_t reg; 3292 3293 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3294 3295 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3296 3297 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3298 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3299 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3300 } 3301 DELAY(50); 3302 3303 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3304 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3305 DELAY(50); 3306 3307 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3308 DELAY(50); 3309 3310 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3311 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3312 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3313 } 3314 DELAY(50); 3315 3316 } 3317 3318 static int 3319 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3320 { 3321 uint32_t reg; 3322 int off, mlen, error = 0; 3323 3324 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3325 device_xname(sc->sc_dev), __func__, page, buf, len)); 3326 3327 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3328 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3329 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3330 3331 off = R92C_FW_START_ADDR; 3332 while (len > 0) { 3333 if (len > 196) 3334 mlen = 196; 3335 else if (len > 4) 3336 mlen = 4; 3337 else 3338 mlen = 1; 3339 error = urtwn_write_region(sc, off, buf, mlen); 3340 if (error != 0) 3341 break; 3342 off += mlen; 3343 buf += mlen; 3344 len -= mlen; 3345 } 3346 return error; 3347 } 3348 3349 static int 3350 urtwn_load_firmware(struct urtwn_softc *sc) 3351 { 3352 firmware_handle_t fwh; 3353 const struct r92c_fw_hdr *hdr; 3354 const char *name; 3355 u_char *fw, *ptr; 3356 size_t len; 3357 uint32_t reg; 3358 int mlen, ntries, page, error; 3359 3360 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3361 3362 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3363 3364 /* Read firmware image from the filesystem. */ 3365 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3366 name = "rtl8188eufw.bin"; 3367 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3368 name = "rtl8192eefw.bin"; 3369 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3370 URTWN_CHIP_UMC_A_CUT) 3371 name = "rtl8192cfwU.bin"; 3372 else 3373 name = "rtl8192cfw.bin"; 3374 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3375 aprint_error_dev(sc->sc_dev, 3376 "failed load firmware of file %s (error %d)\n", name, 3377 error); 3378 return error; 3379 } 3380 const size_t fwlen = len = firmware_get_size(fwh); 3381 fw = firmware_malloc(len); 3382 if (fw == NULL) { 3383 aprint_error_dev(sc->sc_dev, 3384 "failed to allocate firmware memory\n"); 3385 firmware_close(fwh); 3386 return ENOMEM; 3387 } 3388 error = firmware_read(fwh, 0, fw, len); 3389 firmware_close(fwh); 3390 if (error != 0) { 3391 aprint_error_dev(sc->sc_dev, 3392 "failed to read firmware (error %d)\n", error); 3393 firmware_free(fw, fwlen); 3394 return error; 3395 } 3396 3397 len = fwlen; 3398 ptr = fw; 3399 hdr = (const struct r92c_fw_hdr *)ptr; 3400 /* Check if there is a valid FW header and skip it. */ 3401 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3402 (le16toh(hdr->signature) >> 4) == 0x88e || 3403 (le16toh(hdr->signature) >> 4) == 0x92e || 3404 (le16toh(hdr->signature) >> 4) == 0x92c) { 3405 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3406 device_xname(sc->sc_dev), __func__, 3407 le16toh(hdr->version), le16toh(hdr->subversion), 3408 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3409 ptr += sizeof(*hdr); 3410 len -= sizeof(*hdr); 3411 } 3412 3413 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3414 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3415 ISSET(sc->chip, URTWN_CHIP_92EU)) 3416 urtwn_r88e_fw_reset(sc); 3417 else 3418 urtwn_fw_reset(sc); 3419 } 3420 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3421 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3422 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3423 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3424 R92C_SYS_FUNC_EN_CPUEN); 3425 } 3426 3427 /* download enabled */ 3428 urtwn_write_1(sc, R92C_MCUFWDL, 3429 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3430 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3431 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3432 3433 /* Reset the FWDL checksum. */ 3434 urtwn_write_1(sc, R92C_MCUFWDL, 3435 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3436 3437 DELAY(50); 3438 /* download firmware */ 3439 for (page = 0; len > 0; page++) { 3440 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3441 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3442 if (error != 0) { 3443 aprint_error_dev(sc->sc_dev, 3444 "could not load firmware page %d\n", page); 3445 goto fail; 3446 } 3447 ptr += mlen; 3448 len -= mlen; 3449 } 3450 3451 /* download disable */ 3452 urtwn_write_1(sc, R92C_MCUFWDL, 3453 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3454 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3455 3456 /* Wait for checksum report. */ 3457 for (ntries = 0; ntries < 1000; ntries++) { 3458 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3459 break; 3460 DELAY(5); 3461 } 3462 if (ntries == 1000) { 3463 aprint_error_dev(sc->sc_dev, 3464 "timeout waiting for checksum report\n"); 3465 error = ETIMEDOUT; 3466 goto fail; 3467 } 3468 3469 /* Wait for firmware readiness. */ 3470 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3471 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3472 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3473 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3474 ISSET(sc->chip, URTWN_CHIP_92EU)) 3475 urtwn_r88e_fw_reset(sc); 3476 for (ntries = 0; ntries < 1000; ntries++) { 3477 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3478 break; 3479 DELAY(5); 3480 } 3481 if (ntries == 1000) { 3482 aprint_error_dev(sc->sc_dev, 3483 "timeout waiting for firmware readiness\n"); 3484 error = ETIMEDOUT; 3485 goto fail; 3486 } 3487 fail: 3488 firmware_free(fw, fwlen); 3489 return error; 3490 } 3491 3492 static __inline int 3493 urtwn_dma_init(struct urtwn_softc *sc) 3494 { 3495 3496 return sc->sc_dma_init(sc); 3497 } 3498 3499 static int 3500 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3501 { 3502 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3503 uint32_t reg; 3504 int error; 3505 3506 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3507 3508 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3509 3510 /* Initialize LLT table. */ 3511 error = urtwn_llt_init(sc); 3512 if (error != 0) 3513 return error; 3514 3515 /* Get Tx queues to USB endpoints mapping. */ 3516 hashq = hasnq = haslq = 0; 3517 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3518 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3519 device_xname(sc->sc_dev), __func__, reg)); 3520 if (MS(reg, R92C_USB_EP_HQ) != 0) 3521 hashq = 1; 3522 if (MS(reg, R92C_USB_EP_NQ) != 0) 3523 hasnq = 1; 3524 if (MS(reg, R92C_USB_EP_LQ) != 0) 3525 haslq = 1; 3526 nqueues = hashq + hasnq + haslq; 3527 if (nqueues == 0) 3528 return EIO; 3529 /* Get the number of pages for each queue. */ 3530 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3531 /* The remaining pages are assigned to the high priority queue. */ 3532 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3533 3534 /* Set number of pages for normal priority queue. */ 3535 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3536 urtwn_write_4(sc, R92C_RQPN, 3537 /* Set number of pages for public queue. */ 3538 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3539 /* Set number of pages for high priority queue. */ 3540 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3541 /* Set number of pages for low priority queue. */ 3542 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3543 /* Load values. */ 3544 R92C_RQPN_LD); 3545 3546 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3547 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3548 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3549 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3550 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3551 3552 /* Set queue to USB pipe mapping. */ 3553 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3554 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3555 if (nqueues == 1) { 3556 if (hashq) { 3557 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3558 } else if (hasnq) { 3559 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3560 } else { 3561 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3562 } 3563 } else if (nqueues == 2) { 3564 /* All 2-endpoints configs have a high priority queue. */ 3565 if (!hashq) { 3566 return EIO; 3567 } 3568 if (hasnq) { 3569 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3570 } else { 3571 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3572 } 3573 } else { 3574 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3575 } 3576 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3577 3578 /* Set Tx/Rx transfer page boundary. */ 3579 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3580 3581 /* Set Tx/Rx transfer page size. */ 3582 urtwn_write_1(sc, R92C_PBP, 3583 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3584 return 0; 3585 } 3586 3587 static int 3588 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3589 { 3590 usb_interface_descriptor_t *id; 3591 uint32_t reg; 3592 int nqueues; 3593 int error; 3594 3595 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3596 3597 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3598 3599 /* Initialize LLT table. */ 3600 error = urtwn_llt_init(sc); 3601 if (error != 0) 3602 return error; 3603 3604 /* Get Tx queues to USB endpoints mapping. */ 3605 id = usbd_get_interface_descriptor(sc->sc_iface); 3606 nqueues = id->bNumEndpoints - 1; 3607 if (nqueues == 0) 3608 return EIO; 3609 3610 /* Set number of pages for normal priority queue. */ 3611 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3612 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3613 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3614 3615 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3616 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3617 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3618 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3619 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3620 3621 /* Set queue to USB pipe mapping. */ 3622 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3623 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3624 if (nqueues == 1) 3625 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3626 else if (nqueues == 2) 3627 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3628 else 3629 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3630 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3631 3632 /* Set Tx/Rx transfer page boundary. */ 3633 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3634 3635 /* Set Tx/Rx transfer page size. */ 3636 urtwn_write_1(sc, R92C_PBP, 3637 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3638 3639 return 0; 3640 } 3641 3642 static void 3643 urtwn_mac_init(struct urtwn_softc *sc) 3644 { 3645 size_t i; 3646 3647 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3648 3649 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3650 3651 /* Write MAC initialization values. */ 3652 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3653 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3654 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3655 rtl8188eu_mac[i].val); 3656 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3657 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3658 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3659 rtl8192eu_mac[i].val); 3660 } else { 3661 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3662 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3663 rtl8192cu_mac[i].val); 3664 } 3665 } 3666 3667 static void 3668 urtwn_bb_init(struct urtwn_softc *sc) 3669 { 3670 const struct urtwn_bb_prog *prog; 3671 uint32_t reg; 3672 uint8_t crystalcap; 3673 size_t i; 3674 3675 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3676 3677 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3678 3679 /* Enable BB and RF. */ 3680 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3681 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3682 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3683 R92C_SYS_FUNC_EN_DIO_RF); 3684 3685 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3686 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3687 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3688 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3689 } 3690 3691 urtwn_write_1(sc, R92C_RF_CTRL, 3692 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3693 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3694 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3695 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3696 3697 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3698 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3699 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3700 urtwn_write_1(sc, 0x15, 0xe9); 3701 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3702 } 3703 3704 /* Select BB programming based on board type. */ 3705 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3706 prog = &rtl8188eu_bb_prog; 3707 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3708 prog = &rtl8192eu_bb_prog; 3709 else if (!(sc->chip & URTWN_CHIP_92C)) { 3710 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3711 prog = &rtl8188ce_bb_prog; 3712 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3713 prog = &rtl8188ru_bb_prog; 3714 } else { 3715 prog = &rtl8188cu_bb_prog; 3716 } 3717 } else { 3718 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3719 prog = &rtl8192ce_bb_prog; 3720 } else { 3721 prog = &rtl8192cu_bb_prog; 3722 } 3723 } 3724 /* Write BB initialization values. */ 3725 for (i = 0; i < prog->count; i++) { 3726 /* additional delay depend on registers */ 3727 switch (prog->regs[i]) { 3728 case 0xfe: 3729 urtwn_delay_ms(sc, 50); 3730 break; 3731 case 0xfd: 3732 urtwn_delay_ms(sc, 5); 3733 break; 3734 case 0xfc: 3735 urtwn_delay_ms(sc, 1); 3736 break; 3737 case 0xfb: 3738 DELAY(50); 3739 break; 3740 case 0xfa: 3741 DELAY(5); 3742 break; 3743 case 0xf9: 3744 DELAY(1); 3745 break; 3746 } 3747 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3748 DELAY(1); 3749 } 3750 3751 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3752 /* 8192C 1T only configuration. */ 3753 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3754 reg = (reg & ~0x00000003) | 0x2; 3755 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3756 3757 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3758 reg = (reg & ~0x00300033) | 0x00200022; 3759 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3760 3761 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3762 reg = (reg & ~0xff000000) | (0x45 << 24); 3763 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3764 3765 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3766 reg = (reg & ~0x000000ff) | 0x23; 3767 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3768 3769 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3770 reg = (reg & ~0x00000030) | (1 << 4); 3771 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3772 3773 reg = urtwn_bb_read(sc, 0xe74); 3774 reg = (reg & ~0x0c000000) | (2 << 26); 3775 urtwn_bb_write(sc, 0xe74, reg); 3776 reg = urtwn_bb_read(sc, 0xe78); 3777 reg = (reg & ~0x0c000000) | (2 << 26); 3778 urtwn_bb_write(sc, 0xe78, reg); 3779 reg = urtwn_bb_read(sc, 0xe7c); 3780 reg = (reg & ~0x0c000000) | (2 << 26); 3781 urtwn_bb_write(sc, 0xe7c, reg); 3782 reg = urtwn_bb_read(sc, 0xe80); 3783 reg = (reg & ~0x0c000000) | (2 << 26); 3784 urtwn_bb_write(sc, 0xe80, reg); 3785 reg = urtwn_bb_read(sc, 0xe88); 3786 reg = (reg & ~0x0c000000) | (2 << 26); 3787 urtwn_bb_write(sc, 0xe88, reg); 3788 } 3789 3790 /* Write AGC values. */ 3791 for (i = 0; i < prog->agccount; i++) { 3792 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3793 DELAY(1); 3794 } 3795 3796 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3797 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3798 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3799 DELAY(1); 3800 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3801 DELAY(1); 3802 3803 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3804 urtwn_write_2(sc, R92C_AFE_CTRL3, urtwn_read_2(sc, 3805 R92C_AFE_CTRL3)); 3806 } 3807 3808 crystalcap = sc->r88e_rom[0xb9]; 3809 if (crystalcap == 0xff) 3810 crystalcap = 0x20; 3811 crystalcap &= 0x3f; 3812 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3813 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3814 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3815 crystalcap | crystalcap << 6)); 3816 } else { 3817 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3818 R92C_HSSI_PARAM2_CCK_HIPWR) { 3819 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3820 } 3821 } 3822 } 3823 3824 static void 3825 urtwn_rf_init(struct urtwn_softc *sc) 3826 { 3827 const struct urtwn_rf_prog *prog; 3828 uint32_t reg, mask, saved; 3829 size_t i, j, idx; 3830 3831 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3832 3833 /* Select RF programming based on board type. */ 3834 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3835 prog = rtl8188eu_rf_prog; 3836 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3837 prog = rtl8192eu_rf_prog; 3838 else if (!(sc->chip & URTWN_CHIP_92C)) { 3839 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3840 prog = rtl8188ce_rf_prog; 3841 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3842 prog = rtl8188ru_rf_prog; 3843 } else { 3844 prog = rtl8188cu_rf_prog; 3845 } 3846 } else { 3847 prog = rtl8192ce_rf_prog; 3848 } 3849 3850 for (i = 0; i < sc->nrxchains; i++) { 3851 /* Save RF_ENV control type. */ 3852 idx = i / 2; 3853 mask = 0xffffU << ((i % 2) * 16); 3854 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3855 3856 /* Set RF_ENV enable. */ 3857 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3858 reg |= 0x100000; 3859 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3860 DELAY(50); 3861 3862 /* Set RF_ENV output high. */ 3863 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3864 reg |= 0x10; 3865 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3866 DELAY(50); 3867 3868 /* Set address and data lengths of RF registers. */ 3869 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3870 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3871 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3872 DELAY(50); 3873 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3874 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3875 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3876 DELAY(50); 3877 3878 /* Write RF initialization values for this chain. */ 3879 for (j = 0; j < prog[i].count; j++) { 3880 if (prog[i].regs[j] >= 0xf9 && 3881 prog[i].regs[j] <= 0xfe) { 3882 /* 3883 * These are fake RF registers offsets that 3884 * indicate a delay is required. 3885 */ 3886 urtwn_delay_ms(sc, 50); 3887 continue; 3888 } 3889 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3890 DELAY(5); 3891 } 3892 3893 /* Restore RF_ENV control type. */ 3894 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3895 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3896 } 3897 3898 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3899 URTWN_CHIP_UMC_A_CUT) { 3900 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3901 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3902 } 3903 3904 /* Cache RF register CHNLBW. */ 3905 for (i = 0; i < 2; i++) { 3906 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3907 } 3908 } 3909 3910 static void 3911 urtwn_cam_init(struct urtwn_softc *sc) 3912 { 3913 uint32_t content, command; 3914 uint8_t idx; 3915 size_t i; 3916 3917 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3918 3919 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3920 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3921 return; 3922 3923 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3924 content = (idx & 3) 3925 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3926 | R92C_CAM_VALID; 3927 3928 command = R92C_CAMCMD_POLLING 3929 | R92C_CAMCMD_WRITE 3930 | R92C_CAM_CTL0(idx); 3931 3932 urtwn_write_4(sc, R92C_CAMWRITE, content); 3933 urtwn_write_4(sc, R92C_CAMCMD, command); 3934 } 3935 3936 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3937 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3938 if (i == 0) { 3939 content = (idx & 3) 3940 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3941 | R92C_CAM_VALID; 3942 } else { 3943 content = 0; 3944 } 3945 3946 command = R92C_CAMCMD_POLLING 3947 | R92C_CAMCMD_WRITE 3948 | R92C_CAM_CTL0(idx) 3949 | i; 3950 3951 urtwn_write_4(sc, R92C_CAMWRITE, content); 3952 urtwn_write_4(sc, R92C_CAMCMD, command); 3953 } 3954 } 3955 3956 /* Invalidate all CAM entries. */ 3957 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3958 } 3959 3960 static void 3961 urtwn_pa_bias_init(struct urtwn_softc *sc) 3962 { 3963 uint8_t reg; 3964 size_t i; 3965 3966 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3967 3968 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3969 3970 for (i = 0; i < sc->nrxchains; i++) { 3971 if (sc->pa_setting & (1U << i)) 3972 continue; 3973 3974 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3975 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3976 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3977 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3978 } 3979 if (!(sc->pa_setting & 0x10)) { 3980 reg = urtwn_read_1(sc, 0x16); 3981 reg = (reg & ~0xf0) | 0x90; 3982 urtwn_write_1(sc, 0x16, reg); 3983 } 3984 } 3985 3986 static void 3987 urtwn_rxfilter_init(struct urtwn_softc *sc) 3988 { 3989 3990 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3991 3992 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3993 3994 /* Initialize Rx filter. */ 3995 /* TODO: use better filter for monitor mode. */ 3996 urtwn_write_4(sc, R92C_RCR, 3997 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3998 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3999 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4000 /* Accept all multicast frames. */ 4001 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4002 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4003 /* Accept all management frames. */ 4004 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4005 /* Reject all control frames. */ 4006 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4007 /* Accept all data frames. */ 4008 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4009 } 4010 4011 static void 4012 urtwn_edca_init(struct urtwn_softc *sc) 4013 { 4014 4015 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4016 4017 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4018 4019 /* set spec SIFS (used in NAV) */ 4020 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4021 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4022 4023 /* set SIFS CCK/OFDM */ 4024 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4025 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4026 4027 /* TXOP */ 4028 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4029 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4030 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4031 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4032 } 4033 4034 static void 4035 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4036 uint16_t power[URTWN_RIDX_COUNT]) 4037 { 4038 uint32_t reg; 4039 4040 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4041 __func__, chain)); 4042 4043 /* Write per-CCK rate Tx power. */ 4044 if (chain == 0) { 4045 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4046 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4047 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4048 4049 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4050 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4051 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4052 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4053 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4054 } else { 4055 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4056 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4057 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4058 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4059 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4060 4061 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4062 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4063 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4064 } 4065 /* Write per-OFDM rate Tx power. */ 4066 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4067 SM(R92C_TXAGC_RATE06, power[ 4]) | 4068 SM(R92C_TXAGC_RATE09, power[ 5]) | 4069 SM(R92C_TXAGC_RATE12, power[ 6]) | 4070 SM(R92C_TXAGC_RATE18, power[ 7])); 4071 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4072 SM(R92C_TXAGC_RATE24, power[ 8]) | 4073 SM(R92C_TXAGC_RATE36, power[ 9]) | 4074 SM(R92C_TXAGC_RATE48, power[10]) | 4075 SM(R92C_TXAGC_RATE54, power[11])); 4076 /* Write per-MCS Tx power. */ 4077 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4078 SM(R92C_TXAGC_MCS00, power[12]) | 4079 SM(R92C_TXAGC_MCS01, power[13]) | 4080 SM(R92C_TXAGC_MCS02, power[14]) | 4081 SM(R92C_TXAGC_MCS03, power[15])); 4082 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4083 SM(R92C_TXAGC_MCS04, power[16]) | 4084 SM(R92C_TXAGC_MCS05, power[17]) | 4085 SM(R92C_TXAGC_MCS06, power[18]) | 4086 SM(R92C_TXAGC_MCS07, power[19])); 4087 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4088 SM(R92C_TXAGC_MCS08, power[20]) | 4089 SM(R92C_TXAGC_MCS09, power[21]) | 4090 SM(R92C_TXAGC_MCS10, power[22]) | 4091 SM(R92C_TXAGC_MCS11, power[23])); 4092 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4093 SM(R92C_TXAGC_MCS12, power[24]) | 4094 SM(R92C_TXAGC_MCS13, power[25]) | 4095 SM(R92C_TXAGC_MCS14, power[26]) | 4096 SM(R92C_TXAGC_MCS15, power[27])); 4097 } 4098 4099 static void 4100 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4101 uint16_t power[URTWN_RIDX_COUNT]) 4102 { 4103 struct r92c_rom *rom = &sc->rom; 4104 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4105 const struct urtwn_txpwr *base; 4106 int ridx, group; 4107 4108 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4109 device_xname(sc->sc_dev), __func__, chain, chan)); 4110 4111 /* Determine channel group. */ 4112 if (chan <= 3) { 4113 group = 0; 4114 } else if (chan <= 9) { 4115 group = 1; 4116 } else { 4117 group = 2; 4118 } 4119 4120 /* Get original Tx power based on board type and RF chain. */ 4121 if (!(sc->chip & URTWN_CHIP_92C)) { 4122 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4123 base = &rtl8188ru_txagc[chain]; 4124 } else { 4125 base = &rtl8192cu_txagc[chain]; 4126 } 4127 } else { 4128 base = &rtl8192cu_txagc[chain]; 4129 } 4130 4131 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4132 if (sc->regulatory == 0) { 4133 for (ridx = 0; ridx <= 3; ridx++) { 4134 power[ridx] = base->pwr[0][ridx]; 4135 } 4136 } 4137 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4138 if (sc->regulatory == 3) { 4139 power[ridx] = base->pwr[0][ridx]; 4140 /* Apply vendor limits. */ 4141 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4142 maxpow = rom->ht40_max_pwr[group]; 4143 } else { 4144 maxpow = rom->ht20_max_pwr[group]; 4145 } 4146 maxpow = (maxpow >> (chain * 4)) & 0xf; 4147 if (power[ridx] > maxpow) { 4148 power[ridx] = maxpow; 4149 } 4150 } else if (sc->regulatory == 1) { 4151 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4152 power[ridx] = base->pwr[group][ridx]; 4153 } 4154 } else if (sc->regulatory != 2) { 4155 power[ridx] = base->pwr[0][ridx]; 4156 } 4157 } 4158 4159 /* Compute per-CCK rate Tx power. */ 4160 cckpow = rom->cck_tx_pwr[chain][group]; 4161 for (ridx = 0; ridx <= 3; ridx++) { 4162 power[ridx] += cckpow; 4163 if (power[ridx] > R92C_MAX_TX_PWR) { 4164 power[ridx] = R92C_MAX_TX_PWR; 4165 } 4166 } 4167 4168 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4169 if (sc->ntxchains > 1) { 4170 /* Apply reduction for 2 spatial streams. */ 4171 diff = rom->ht40_2s_tx_pwr_diff[group]; 4172 diff = (diff >> (chain * 4)) & 0xf; 4173 htpow = (htpow > diff) ? htpow - diff : 0; 4174 } 4175 4176 /* Compute per-OFDM rate Tx power. */ 4177 diff = rom->ofdm_tx_pwr_diff[group]; 4178 diff = (diff >> (chain * 4)) & 0xf; 4179 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4180 for (ridx = 4; ridx <= 11; ridx++) { 4181 power[ridx] += ofdmpow; 4182 if (power[ridx] > R92C_MAX_TX_PWR) { 4183 power[ridx] = R92C_MAX_TX_PWR; 4184 } 4185 } 4186 4187 /* Compute per-MCS Tx power. */ 4188 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4189 diff = rom->ht20_tx_pwr_diff[group]; 4190 diff = (diff >> (chain * 4)) & 0xf; 4191 htpow += diff; /* HT40->HT20 correction. */ 4192 } 4193 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4194 power[ridx] += htpow; 4195 if (power[ridx] > R92C_MAX_TX_PWR) { 4196 power[ridx] = R92C_MAX_TX_PWR; 4197 } 4198 } 4199 #ifdef URTWN_DEBUG 4200 if (urtwn_debug & DBG_RF) { 4201 /* Dump per-rate Tx power values. */ 4202 printf("%s: %s: Tx power for chain %zd:\n", 4203 device_xname(sc->sc_dev), __func__, chain); 4204 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4205 printf("%s: %s: Rate %d = %u\n", 4206 device_xname(sc->sc_dev), __func__, ridx, 4207 power[ridx]); 4208 } 4209 } 4210 #endif 4211 } 4212 4213 void 4214 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4215 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4216 { 4217 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4218 const struct urtwn_r88e_txpwr *base; 4219 int ridx, group; 4220 4221 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4222 device_xname(sc->sc_dev), __func__, chain, chan)); 4223 4224 /* Determine channel group. */ 4225 if (chan <= 2) 4226 group = 0; 4227 else if (chan <= 5) 4228 group = 1; 4229 else if (chan <= 8) 4230 group = 2; 4231 else if (chan <= 11) 4232 group = 3; 4233 else if (chan <= 13) 4234 group = 4; 4235 else 4236 group = 5; 4237 4238 /* Get original Tx power based on board type and RF chain. */ 4239 base = &rtl8188eu_txagc[chain]; 4240 4241 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4242 if (sc->regulatory == 0) { 4243 for (ridx = 0; ridx <= 3; ridx++) 4244 power[ridx] = base->pwr[0][ridx]; 4245 } 4246 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4247 if (sc->regulatory == 3) 4248 power[ridx] = base->pwr[0][ridx]; 4249 else if (sc->regulatory == 1) { 4250 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4251 power[ridx] = base->pwr[group][ridx]; 4252 } else if (sc->regulatory != 2) 4253 power[ridx] = base->pwr[0][ridx]; 4254 } 4255 4256 /* Compute per-CCK rate Tx power. */ 4257 cckpow = sc->cck_tx_pwr[group]; 4258 for (ridx = 0; ridx <= 3; ridx++) { 4259 power[ridx] += cckpow; 4260 if (power[ridx] > R92C_MAX_TX_PWR) 4261 power[ridx] = R92C_MAX_TX_PWR; 4262 } 4263 4264 htpow = sc->ht40_tx_pwr[group]; 4265 4266 /* Compute per-OFDM rate Tx power. */ 4267 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4268 for (ridx = 4; ridx <= 11; ridx++) { 4269 power[ridx] += ofdmpow; 4270 if (power[ridx] > R92C_MAX_TX_PWR) 4271 power[ridx] = R92C_MAX_TX_PWR; 4272 } 4273 4274 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4275 for (ridx = 12; ridx <= 27; ridx++) { 4276 power[ridx] += bw20pow; 4277 if (power[ridx] > R92C_MAX_TX_PWR) 4278 power[ridx] = R92C_MAX_TX_PWR; 4279 } 4280 } 4281 4282 static void 4283 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4284 { 4285 uint16_t power[URTWN_RIDX_COUNT]; 4286 size_t i; 4287 4288 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4289 4290 for (i = 0; i < sc->ntxchains; i++) { 4291 /* Compute per-rate Tx power values. */ 4292 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4293 ISSET(sc->chip, URTWN_CHIP_92EU)) 4294 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4295 else 4296 urtwn_get_txpower(sc, i, chan, ht40m, power); 4297 /* Write per-rate Tx power values to hardware. */ 4298 urtwn_write_txpower(sc, i, power); 4299 } 4300 } 4301 4302 static void 4303 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4304 { 4305 struct ieee80211com *ic = &sc->sc_ic; 4306 u_int chan; 4307 size_t i; 4308 4309 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4310 4311 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4312 __func__, chan)); 4313 4314 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4315 4316 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4317 chan += 2; 4318 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4319 chan -= 2; 4320 } 4321 4322 /* Set Tx power for this new channel. */ 4323 urtwn_set_txpower(sc, chan, ht40m); 4324 4325 for (i = 0; i < sc->nrxchains; i++) { 4326 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4327 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4328 } 4329 4330 if (ht40m) { 4331 /* Is secondary channel below or above primary? */ 4332 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4333 uint32_t reg; 4334 4335 urtwn_write_1(sc, R92C_BWOPMODE, 4336 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4337 4338 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4339 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4340 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4341 4342 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4343 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4344 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4345 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4346 4347 /* Set CCK side band. */ 4348 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4349 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4350 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4351 4352 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4353 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4354 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4355 4356 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4357 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4358 ~R92C_FPGA0_ANAPARAM2_CBW20); 4359 4360 reg = urtwn_bb_read(sc, 0x818); 4361 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4362 urtwn_bb_write(sc, 0x818, reg); 4363 4364 /* Select 40MHz bandwidth. */ 4365 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4366 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4367 } else { 4368 urtwn_write_1(sc, R92C_BWOPMODE, 4369 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4370 4371 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4372 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4373 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4374 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4375 4376 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4377 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4378 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4379 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4380 R92C_FPGA0_ANAPARAM2_CBW20); 4381 } 4382 4383 /* Select 20MHz bandwidth. */ 4384 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4385 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4386 (ISSET(sc->chip, URTWN_CHIP_88E) || 4387 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4388 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4389 } 4390 } 4391 4392 static void 4393 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4394 { 4395 4396 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4397 __func__, inited)); 4398 4399 uint32_t addaBackup[16], iqkBackup[4], piMode; 4400 4401 #ifdef notyet 4402 uint32_t odfm0_agccore_regs[3]; 4403 uint32_t ant_regs[3]; 4404 uint32_t rf_regs[8]; 4405 #endif 4406 uint32_t reg0, reg1, reg2; 4407 int i, attempt; 4408 4409 #ifdef notyet 4410 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4411 R92E_STBC_SETTING + 2)); 4412 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4413 /* Save AGCCORE regs. */ 4414 for (i = 0; i < sc->nrxchains; i++) { 4415 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4416 R92C_OFDM0_AGCCORE1(i)); 4417 } 4418 #endif 4419 /* Save BB regs. */ 4420 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4421 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4422 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4423 4424 /* Save adda regs to be restored when finished. */ 4425 for (i = 0; i < __arraycount(addaReg); i++) 4426 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4427 /* Save mac regs. */ 4428 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4429 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4430 iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF); 4431 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4432 4433 #ifdef notyet 4434 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4435 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4436 4437 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4438 for (i = 0; i < sc->nrxchains; i++) 4439 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4440 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4441 #endif 4442 4443 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4444 R92C_HSSI_PARAM1_PI); 4445 if (piMode == 0) { 4446 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4447 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4448 R92C_HSSI_PARAM1_PI); 4449 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4450 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4451 R92C_HSSI_PARAM1_PI); 4452 } 4453 4454 attempt = 1; 4455 4456 next_attempt: 4457 4458 /* Set mac regs for calibration. */ 4459 for (i = 0; i < __arraycount(addaReg); i++) { 4460 urtwn_bb_write(sc, addaReg[i], 4461 addaReg[__arraycount(addaReg) - 1]); 4462 } 4463 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4464 R92C_CCK0_AFESETTING)); 4465 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4466 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4467 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4468 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4469 4470 if (sc->ntxchains > 1) 4471 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4472 4473 urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL); 4474 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4475 ~R92C_BCN_CTRL_EN_BCN)); 4476 urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8)); 4477 4478 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4479 ~R92C_GPIO_MUXCFG_ENBT)); 4480 4481 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4482 4483 if (sc->ntxchains > 1) 4484 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4485 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4486 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4487 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4488 4489 /* Restore BB regs. */ 4490 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4491 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4492 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4493 4494 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4495 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4496 if (sc->nrxchains > 1) 4497 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4498 4499 if (attempt-- > 0) 4500 goto next_attempt; 4501 4502 /* Restore mode. */ 4503 if (piMode == 0) { 4504 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4505 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4506 ~R92C_HSSI_PARAM1_PI); 4507 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4508 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4509 ~R92C_HSSI_PARAM1_PI); 4510 } 4511 4512 #ifdef notyet 4513 for (i = 0; i < sc->nrxchains; i++) { 4514 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4515 odfm0_agccore_regs[i]); 4516 } 4517 #endif 4518 4519 /* Restore adda regs. */ 4520 for (i = 0; i < __arraycount(addaReg); i++) 4521 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4522 /* Restore mac regs. */ 4523 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4524 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4525 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4526 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4527 4528 #ifdef notyet 4529 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4530 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4531 4532 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4533 for (i = 0; i < sc->nrxchains; i++) 4534 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4535 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4536 #endif 4537 } 4538 4539 static void 4540 urtwn_lc_calib(struct urtwn_softc *sc) 4541 { 4542 uint32_t rf_ac[2]; 4543 uint8_t txmode; 4544 size_t i; 4545 4546 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4547 4548 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4549 4550 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4551 if ((txmode & 0x70) != 0) { 4552 /* Disable all continuous Tx. */ 4553 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4554 4555 /* Set RF mode to standby mode. */ 4556 for (i = 0; i < sc->nrxchains; i++) { 4557 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4558 urtwn_rf_write(sc, i, R92C_RF_AC, 4559 RW(rf_ac[i], R92C_RF_AC_MODE, 4560 R92C_RF_AC_MODE_STANDBY)); 4561 } 4562 } else { 4563 /* Block all Tx queues. */ 4564 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4565 } 4566 /* Start calibration. */ 4567 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4568 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4569 4570 /* Give calibration the time to complete. */ 4571 urtwn_delay_ms(sc, 100); 4572 4573 /* Restore configuration. */ 4574 if ((txmode & 0x70) != 0) { 4575 /* Restore Tx mode. */ 4576 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4577 /* Restore RF mode. */ 4578 for (i = 0; i < sc->nrxchains; i++) { 4579 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4580 } 4581 } else { 4582 /* Unblock all Tx queues. */ 4583 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4584 } 4585 } 4586 4587 static void 4588 urtwn_temp_calib(struct urtwn_softc *sc) 4589 { 4590 int temp, t_meter_reg; 4591 4592 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4593 4594 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4595 4596 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4597 t_meter_reg = R92C_RF_T_METER; 4598 else 4599 t_meter_reg = R92E_RF_T_METER; 4600 4601 if (sc->thcal_state == 0) { 4602 /* Start measuring temperature. */ 4603 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4604 device_xname(sc->sc_dev), __func__)); 4605 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4606 sc->thcal_state = 1; 4607 return; 4608 } 4609 sc->thcal_state = 0; 4610 4611 /* Read measured temperature. */ 4612 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4613 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4614 __func__, temp)); 4615 if (temp == 0) /* Read failed, skip. */ 4616 return; 4617 4618 /* 4619 * Redo LC calibration if temperature changed significantly since 4620 * last calibration. 4621 */ 4622 if (sc->thcal_lctemp == 0) { 4623 /* First LC calibration is performed in urtwn_init(). */ 4624 sc->thcal_lctemp = temp; 4625 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4626 DPRINTFN(DBG_RF, 4627 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4628 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4629 temp)); 4630 urtwn_lc_calib(sc); 4631 /* Record temperature of last LC calibration. */ 4632 sc->thcal_lctemp = temp; 4633 } 4634 } 4635 4636 static int 4637 urtwn_init(struct ifnet *ifp) 4638 { 4639 struct urtwn_softc *sc = ifp->if_softc; 4640 struct ieee80211com *ic = &sc->sc_ic; 4641 struct urtwn_rx_data *data; 4642 uint32_t reg; 4643 size_t i; 4644 int error; 4645 4646 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4647 4648 urtwn_stop(ifp, 0); 4649 4650 mutex_enter(&sc->sc_write_mtx); 4651 4652 mutex_enter(&sc->sc_task_mtx); 4653 /* Init host async commands ring. */ 4654 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4655 mutex_exit(&sc->sc_task_mtx); 4656 4657 mutex_enter(&sc->sc_fwcmd_mtx); 4658 /* Init firmware commands ring. */ 4659 sc->fwcur = 0; 4660 mutex_exit(&sc->sc_fwcmd_mtx); 4661 4662 /* Allocate Tx/Rx buffers. */ 4663 error = urtwn_alloc_rx_list(sc); 4664 if (error != 0) { 4665 aprint_error_dev(sc->sc_dev, 4666 "could not allocate Rx buffers\n"); 4667 goto fail; 4668 } 4669 error = urtwn_alloc_tx_list(sc); 4670 if (error != 0) { 4671 aprint_error_dev(sc->sc_dev, 4672 "could not allocate Tx buffers\n"); 4673 goto fail; 4674 } 4675 4676 /* Power on adapter. */ 4677 error = urtwn_power_on(sc); 4678 if (error != 0) 4679 goto fail; 4680 4681 /* Initialize DMA. */ 4682 error = urtwn_dma_init(sc); 4683 if (error != 0) 4684 goto fail; 4685 4686 /* Set info size in Rx descriptors (in 64-bit words). */ 4687 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4688 4689 /* Init interrupts. */ 4690 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4691 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4692 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4693 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4694 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4695 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4696 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4697 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4698 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4699 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4700 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4701 } 4702 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4703 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4704 } else { 4705 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4706 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4707 } 4708 4709 /* Set MAC address. */ 4710 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4711 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4712 4713 /* Set initial network type. */ 4714 reg = urtwn_read_4(sc, R92C_CR); 4715 switch (ic->ic_opmode) { 4716 case IEEE80211_M_STA: 4717 default: 4718 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4719 break; 4720 4721 case IEEE80211_M_IBSS: 4722 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4723 break; 4724 } 4725 urtwn_write_4(sc, R92C_CR, reg); 4726 4727 /* Set response rate */ 4728 reg = urtwn_read_4(sc, R92C_RRSR); 4729 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4730 urtwn_write_4(sc, R92C_RRSR, reg); 4731 4732 /* SIFS (used in NAV) */ 4733 urtwn_write_2(sc, R92C_SPEC_SIFS, 4734 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4735 4736 /* Set short/long retry limits. */ 4737 urtwn_write_2(sc, R92C_RL, 4738 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4739 4740 /* Initialize EDCA parameters. */ 4741 urtwn_edca_init(sc); 4742 4743 /* Setup rate fallback. */ 4744 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4745 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4746 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4747 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4748 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4749 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4750 } 4751 4752 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4753 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4754 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4755 /* Set ACK timeout. */ 4756 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4757 4758 /* Setup USB aggregation. */ 4759 /* Tx */ 4760 reg = urtwn_read_4(sc, R92C_TDECTRL); 4761 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4762 urtwn_write_4(sc, R92C_TDECTRL, reg); 4763 /* Rx */ 4764 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4765 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4766 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4767 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4768 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4769 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4770 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4771 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4772 ISSET(sc->chip, URTWN_CHIP_92EU)) 4773 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4774 else 4775 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4776 4777 /* Initialize beacon parameters. */ 4778 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4779 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4780 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4781 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4782 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4783 4784 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4785 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4786 /* Setup AMPDU aggregation. */ 4787 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4788 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4789 urtwn_write_2(sc, 0x4ca, 0x0708); 4790 4791 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4792 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4793 } 4794 4795 /* Load 8051 microcode. */ 4796 error = urtwn_load_firmware(sc); 4797 if (error != 0) 4798 goto fail; 4799 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4800 4801 /* Initialize MAC/BB/RF blocks. */ 4802 /* 4803 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4804 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4805 * XXX: This setting should be removed from rtl8192cu_mac[]. 4806 */ 4807 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4808 urtwn_rxfilter_init(sc); // reset R92C_RCR 4809 urtwn_bb_init(sc); 4810 urtwn_rf_init(sc); 4811 4812 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4813 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4814 urtwn_write_2(sc, R92C_CR, 4815 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4816 R92C_CR_MACRXEN); 4817 } 4818 4819 /* Turn CCK and OFDM blocks on. */ 4820 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4821 reg |= R92C_RFMOD_CCK_EN; 4822 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4823 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4824 reg |= R92C_RFMOD_OFDM_EN; 4825 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4826 4827 /* Clear per-station keys table. */ 4828 urtwn_cam_init(sc); 4829 4830 /* Enable hardware sequence numbering. */ 4831 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4832 4833 /* Perform LO and IQ calibrations. */ 4834 urtwn_iq_calib(sc, sc->iqk_inited); 4835 sc->iqk_inited = true; 4836 4837 /* Perform LC calibration. */ 4838 urtwn_lc_calib(sc); 4839 4840 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4841 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4842 /* Fix USB interference issue. */ 4843 urtwn_write_1(sc, 0xfe40, 0xe0); 4844 urtwn_write_1(sc, 0xfe41, 0x8d); 4845 urtwn_write_1(sc, 0xfe42, 0x80); 4846 urtwn_write_4(sc, 0x20c, 0xfd0320); 4847 4848 urtwn_pa_bias_init(sc); 4849 } 4850 4851 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4852 !(sc->chip & URTWN_CHIP_92EU)) { 4853 /* 1T1R */ 4854 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4855 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4856 } 4857 4858 /* Initialize GPIO setting. */ 4859 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4860 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4861 4862 /* Fix for lower temperature. */ 4863 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4864 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4865 urtwn_write_1(sc, 0x15, 0xe9); 4866 4867 /* Set default channel. */ 4868 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4869 4870 /* Queue Rx xfers. */ 4871 for (size_t j = 0; j < sc->rx_npipe; j++) { 4872 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4873 data = &sc->rx_data[j][i]; 4874 usbd_setup_xfer(data->xfer, data, data->buf, 4875 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4876 urtwn_rxeof); 4877 error = usbd_transfer(data->xfer); 4878 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4879 error != USBD_IN_PROGRESS)) 4880 goto fail; 4881 } 4882 } 4883 4884 /* We're ready to go. */ 4885 ifp->if_flags &= ~IFF_OACTIVE; 4886 ifp->if_flags |= IFF_RUNNING; 4887 sc->sc_running = true; 4888 4889 mutex_exit(&sc->sc_write_mtx); 4890 4891 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4892 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4893 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4894 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4895 urtwn_wait_async(sc); 4896 4897 return 0; 4898 4899 fail: 4900 mutex_exit(&sc->sc_write_mtx); 4901 4902 urtwn_stop(ifp, 1); 4903 return error; 4904 } 4905 4906 static void 4907 urtwn_stop(struct ifnet *ifp, int disable) 4908 { 4909 struct urtwn_softc *sc = ifp->if_softc; 4910 struct ieee80211com *ic = &sc->sc_ic; 4911 size_t i; 4912 int s; 4913 4914 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4915 4916 s = splusb(); 4917 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4918 urtwn_wait_async(sc); 4919 splx(s); 4920 4921 sc->tx_timer = 0; 4922 ifp->if_timer = 0; 4923 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4924 4925 callout_stop(&sc->sc_scan_to); 4926 callout_stop(&sc->sc_calib_to); 4927 4928 /* Abort Tx. */ 4929 for (i = 0; i < sc->tx_npipe; i++) { 4930 if (sc->tx_pipe[i] != NULL) 4931 usbd_abort_pipe(sc->tx_pipe[i]); 4932 } 4933 4934 /* Stop Rx pipe. */ 4935 for (i = 0; i < sc->rx_npipe; i++) { 4936 if (sc->rx_pipe[i] != NULL) 4937 usbd_abort_pipe(sc->rx_pipe[i]); 4938 } 4939 4940 /* Free Tx/Rx buffers. */ 4941 urtwn_free_tx_list(sc); 4942 urtwn_free_rx_list(sc); 4943 4944 sc->sc_running = false; 4945 if (disable) 4946 urtwn_chip_stop(sc); 4947 } 4948 4949 static int 4950 urtwn_reset(struct ifnet *ifp) 4951 { 4952 struct urtwn_softc *sc = ifp->if_softc; 4953 struct ieee80211com *ic = &sc->sc_ic; 4954 4955 if (ic->ic_opmode != IEEE80211_M_MONITOR) 4956 return ENETRESET; 4957 4958 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4959 4960 return 0; 4961 } 4962 4963 static void 4964 urtwn_chip_stop(struct urtwn_softc *sc) 4965 { 4966 uint32_t reg; 4967 bool disabled = true; 4968 4969 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4970 4971 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4972 return; 4973 4974 mutex_enter(&sc->sc_write_mtx); 4975 4976 /* 4977 * RF Off Sequence 4978 */ 4979 /* Pause MAC TX queue */ 4980 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 4981 4982 /* Disable RF */ 4983 urtwn_rf_write(sc, 0, 0, 0); 4984 4985 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 4986 4987 /* Reset BB state machine */ 4988 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4989 R92C_SYS_FUNC_EN_USBD | 4990 R92C_SYS_FUNC_EN_USBA | 4991 R92C_SYS_FUNC_EN_BB_GLB_RST); 4992 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4993 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 4994 4995 /* 4996 * Reset digital sequence 4997 */ 4998 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 4999 /* Reset MCU ready status */ 5000 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5001 /* If firmware in ram code, do reset */ 5002 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5003 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5004 ISSET(sc->chip, URTWN_CHIP_92EU)) 5005 urtwn_r88e_fw_reset(sc); 5006 else 5007 urtwn_fw_reset(sc); 5008 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5009 } 5010 } 5011 5012 /* Reset MAC and Enable 8051 */ 5013 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5014 5015 /* Reset MCU ready status */ 5016 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5017 5018 if (disabled) { 5019 /* Disable MAC clock */ 5020 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5021 /* Disable AFE PLL */ 5022 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5023 /* Gated AFE DIG_CLOCK */ 5024 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5025 /* Isolated digital to PON */ 5026 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5027 } 5028 5029 /* 5030 * Pull GPIO PIN to balance level and LED control 5031 */ 5032 /* 1. Disable GPIO[7:0] */ 5033 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5034 5035 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5036 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5037 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5038 5039 /* Disable GPIO[10:8] */ 5040 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5041 5042 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5043 reg |= (((reg & 0x000f) << 4) | 0x0780); 5044 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5045 5046 /* Disable LED0 & 1 */ 5047 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5048 5049 /* 5050 * Reset digital sequence 5051 */ 5052 if (disabled) { 5053 /* Disable ELDR clock */ 5054 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5055 /* Isolated ELDR to PON */ 5056 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5057 } 5058 5059 /* 5060 * Disable analog sequence 5061 */ 5062 if (disabled) { 5063 /* Disable A15 power */ 5064 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5065 /* Disable digital core power */ 5066 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5067 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5068 ~R92C_LDOV12D_CTRL_LDV12_EN); 5069 } 5070 5071 /* Enter PFM mode */ 5072 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5073 5074 /* Set USB suspend */ 5075 urtwn_write_2(sc, R92C_APS_FSMCO, 5076 R92C_APS_FSMCO_APDM_HOST | 5077 R92C_APS_FSMCO_AFSM_HSUS | 5078 R92C_APS_FSMCO_PFM_ALDN); 5079 5080 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5081 5082 mutex_exit(&sc->sc_write_mtx); 5083 } 5084 5085 static void 5086 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5087 { 5088 if (sc->sc_running == false) 5089 DELAY(ms * 1000); 5090 else 5091 usbd_delay_ms(sc->sc_udev, ms); 5092 } 5093 5094 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 5095 5096 #ifdef _MODULE 5097 #include "ioconf.c" 5098 #endif 5099 5100 static int 5101 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5102 { 5103 int error = 0; 5104 5105 switch (cmd) { 5106 case MODULE_CMD_INIT: 5107 #ifdef _MODULE 5108 error = config_init_component(cfdriver_ioconf_urtwn, 5109 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5110 #endif 5111 return error; 5112 case MODULE_CMD_FINI: 5113 #ifdef _MODULE 5114 error = config_fini_component(cfdriver_ioconf_urtwn, 5115 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5116 #endif 5117 return error; 5118 default: 5119 return ENOTTY; 5120 } 5121 } 5122
Indexes created Thu Oct 02 14:10:14 GMT 2025