if_urtwn.c revision 1.59.2.14
1 /* $NetBSD: if_urtwn.c,v 1.59.2.14 2020/04/21 18:42:38 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.14 2020/04/21 18:42:38 martin Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 /* urtwn data */ 227 static const uint8_t urtwn_chan_2ghz[] = 228 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 229 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct ieee80211vap *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 289 int); 290 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ieee80211vap *, u_long); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 /* Functions for wifi refresh */ 340 static struct ieee80211vap * 341 urtwn_vap_create(struct ieee80211com *, 342 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 343 const uint8_t [IEEE80211_ADDR_LEN], 344 const uint8_t [IEEE80211_ADDR_LEN]); 345 static void urtwn_vap_delete(struct ieee80211vap *); 346 static int urtwn_ioctl(struct ifnet *, u_long, void *); 347 static void urtwn_parent(struct ieee80211com *); 348 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 349 struct ieee80211_channel []); 350 static void urtwn_scan_start(struct ieee80211com *); 351 static void urtwn_scan_end(struct ieee80211com *); 352 static void urtwn_set_channel(struct ieee80211com *); 353 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 354 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 355 const struct ieee80211_bpf_params *); 356 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 363 364 static const uint16_t addaReg[] = { 365 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 366 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 367 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 368 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 369 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 370 }; 371 372 static int 373 urtwn_match(device_t parent, cfdata_t match, void *aux) 374 { 375 struct usb_attach_arg *uaa = aux; 376 377 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 378 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 379 } 380 381 static void 382 urtwn_attach(device_t parent, device_t self, void *aux) 383 { 384 struct urtwn_softc *sc = device_private(self); 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct usb_attach_arg *uaa = aux; 387 char *devinfop; 388 const struct urtwn_dev *dev; 389 usb_device_request_t req; 390 // NNN loop below size_t i; 391 int error; 392 393 sc->sc_dev = self; 394 sc->sc_udev = uaa->uaa_device; 395 396 /* Name the ic. */ 397 ic->ic_name = "urtwn"; 398 399 /* Driver Send queue, separate from the if send queue*/ 400 sc->sc_sendq.ifq_maxlen = 32; 401 /* NNN how should this be initialized? */ 402 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 403 sc->sc_sendq.ifq_len = 0; 404 sc->sc_sendq.ifq_drops = 0; 405 IFQ_LOCK_INIT(&sc->sc_sendq); 406 407 sc->chip = 0; 408 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 409 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 410 SET(sc->chip, URTWN_CHIP_88E); 411 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 412 SET(sc->chip, URTWN_CHIP_92EU); 413 414 aprint_naive("\n"); 415 aprint_normal("\n"); 416 417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 418 419 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 420 aprint_normal_dev(self, "%s\n", devinfop); 421 usbd_devinfo_free(devinfop); 422 423 req.bmRequestType = UT_WRITE_DEVICE; 424 req.bRequest = UR_SET_FEATURE; 425 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 426 USETW(req.wIndex, UHF_PORT_SUSPEND); 427 USETW(req.wLength, 0); 428 429 (void) usbd_do_request(sc->sc_udev, &req, 0); 430 431 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 432 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 434 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 435 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 436 437 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 438 439 /* NNN make these callouts use a vap ... in vap create??? */ 440 callout_init(&sc->sc_scan_to, 0); 441 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 442 callout_init(&sc->sc_calib_to, 0); 443 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 444 445 error = usbd_set_config_no(sc->sc_udev, 1, 0); 446 if (error != 0) { 447 aprint_error_dev(self, "failed to set configuration" 448 ", err=%s\n", usbd_errstr(error)); 449 goto fail; 450 } 451 452 /* Get the first interface handle. */ 453 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 454 if (error != 0) { 455 aprint_error_dev(self, "could not get interface handle\n"); 456 goto fail; 457 } 458 459 error = urtwn_read_chipid(sc); 460 if (error != 0) { 461 aprint_error_dev(self, "unsupported test chip\n"); 462 goto fail; 463 } 464 465 /* Determine number of Tx/Rx chains. */ 466 if (sc->chip & URTWN_CHIP_92C) { 467 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 468 sc->nrxchains = 2; 469 } else if (sc->chip & URTWN_CHIP_92EU) { 470 sc->ntxchains = 2; 471 sc->nrxchains = 2; 472 } else { 473 sc->ntxchains = 1; 474 sc->nrxchains = 1; 475 } 476 477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 478 ISSET(sc->chip, URTWN_CHIP_92EU)) 479 urtwn_r88e_read_rom(sc); 480 else 481 urtwn_read_rom(sc); 482 483 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 484 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 485 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 486 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 487 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 488 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 489 "8188CUS", sc->ntxchains, sc->nrxchains, 490 ether_sprintf(ic->ic_macaddr)); 491 492 error = urtwn_open_pipes(sc); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 495 goto fail; 496 } 497 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 498 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 499 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 500 501 /* 502 * Setup the 802.11 device. 503 */ 504 ic->ic_softc = sc; 505 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 506 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 507 508 /* Set device capabilities. */ 509 ic->ic_caps = 510 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 511 IEEE80211_C_IBSS | /* IBSS mode supported */ 512 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 513 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 514 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 515 IEEE80211_C_WME | /* 802.11e */ 516 IEEE80211_C_WPA; /* 802.11i */ 517 518 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 519 520 #ifdef should_delete_NNN 521 /* Set supported .11b and .11g channels (1 through 14). */ 522 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 523 for (i = 0; i < 14; i++) { 524 ic->ic_channels[i].ic_freq = 525 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 526 ic->ic_channels[i].ic_flags = 527 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 528 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 529 } 530 #else 531 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 532 ic->ic_channels); 533 #endif 534 /* XXX issues here ... Figure out proper attach and vap creation */ 535 ieee80211_ifattach(ic); 536 537 /* override default methods NNN Need more here? */ 538 ic->ic_newassoc = urtwn_newassoc; 539 ic->ic_wme.wme_update = urtwn_wme_update; 540 ic->ic_vap_create = urtwn_vap_create; 541 ic->ic_vap_delete = urtwn_vap_delete; 542 ic->ic_parent = urtwn_parent; 543 ic->ic_scan_start = urtwn_scan_start; 544 ic->ic_scan_end = urtwn_scan_end; 545 ic->ic_set_channel = urtwn_set_channel; 546 ic->ic_transmit = urtwn_transmit; 547 // ic->ic_send_mgmt = urtwn_send_mgmt; 548 ic->ic_raw_xmit = urtwn_raw_xmit; 549 ic->ic_getradiocaps = urtwn_getradiocaps; 550 551 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 552 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 553 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 554 555 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 556 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 557 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 558 559 ieee80211_announce(ic); 560 561 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 562 563 if (!pmf_device_register(self, NULL, NULL)) 564 aprint_error_dev(self, "couldn't establish power handler\n"); 565 566 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 567 568 /* Should be called via an IOCTL. Temp call here for now. */ 569 570 struct ieee80211vap *vap = 571 urtwn_vap_create(ic, device_xname(sc->sc_dev), 572 device_unit(sc->sc_dev), IEEE80211_M_STA, 573 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 574 575 if (vap == NULL) { 576 /* Didn't work ... now what! */ 577 printf ("NNN vap_create didn't work ...\n"); 578 ieee80211_ifdetach(ic); 579 goto fail; 580 } 581 582 return; 583 584 fail: 585 sc->sc_dying = 1; 586 aprint_error_dev(self, "attach failed\n"); 587 } 588 589 static int 590 urtwn_detach(device_t self, int flags) 591 { 592 struct urtwn_softc *sc = device_private(self); 593 struct ieee80211com *ic = &sc->sc_ic; 594 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 595 struct ifnet *ifp = vap->iv_ifp; 596 int s; 597 598 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 599 600 pmf_device_deregister(self); 601 602 s = splusb(); 603 604 sc->sc_dying = 1; 605 606 callout_halt(&sc->sc_scan_to, NULL); 607 callout_halt(&sc->sc_calib_to, NULL); 608 609 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 610 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 611 NULL); 612 urtwn_stop(ifp, 0); 613 // vap_detach(...) ?? 614 615 ieee80211_ifdetach(&sc->sc_ic); 616 617 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 618 urtwn_close_pipes(sc); 619 } 620 621 /* sendq destroy */ 622 IFQ_PURGE(&sc->sc_sendq); 623 IFQ_LOCK_DESTROY(&sc->sc_sendq); 624 625 splx(s); 626 627 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 628 629 callout_destroy(&sc->sc_scan_to); 630 callout_destroy(&sc->sc_calib_to); 631 632 mutex_destroy(&sc->sc_write_mtx); 633 mutex_destroy(&sc->sc_fwcmd_mtx); 634 mutex_destroy(&sc->sc_tx_mtx); 635 mutex_destroy(&sc->sc_rx_mtx); 636 mutex_destroy(&sc->sc_task_mtx); 637 638 return 0; 639 } 640 641 static int 642 urtwn_activate(device_t self, enum devact act) 643 { 644 struct urtwn_softc *sc = device_private(self); 645 646 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 647 648 switch (act) { 649 case DVACT_DEACTIVATE: 650 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 651 652 return 0; 653 default: 654 return EOPNOTSUPP; 655 } 656 } 657 658 static int 659 urtwn_open_pipes(struct urtwn_softc *sc) 660 { 661 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 662 static uint8_t epaddr[R92C_MAX_EPOUT]; 663 static uint8_t rxepaddr[R92C_MAX_EPIN]; 664 usb_interface_descriptor_t *id; 665 usb_endpoint_descriptor_t *ed; 666 size_t i, ntx = 0, nrx = 0; 667 int error; 668 669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 670 671 /* Determine the number of bulk-out pipes. */ 672 id = usbd_get_interface_descriptor(sc->sc_iface); 673 for (i = 0; i < id->bNumEndpoints; i++) { 674 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 675 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 676 continue; 677 } 678 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 679 if (ntx < sizeof(epaddr)) 680 epaddr[ntx] = ed->bEndpointAddress; 681 ntx++; 682 } 683 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 684 if (nrx < sizeof(rxepaddr)) 685 rxepaddr[nrx] = ed->bEndpointAddress; 686 nrx++; 687 } 688 } 689 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 690 aprint_error_dev(sc->sc_dev, 691 "%zd: invalid number of Rx bulk pipes\n", nrx); 692 return EIO; 693 } 694 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 695 aprint_error_dev(sc->sc_dev, 696 "%zd: invalid number of Tx bulk pipes\n", ntx); 697 return EIO; 698 } 699 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 700 device_xname(sc->sc_dev), __func__, nrx, ntx)); 701 sc->rx_npipe = nrx; 702 sc->tx_npipe = ntx; 703 704 /* Open bulk-in pipe at address 0x81. */ 705 for (i = 0; i < nrx; i++) { 706 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 707 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 708 if (error != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "could not open Rx bulk pipe 0x%02x: %d\n", 711 rxepaddr[i], error); 712 goto fail; 713 } 714 } 715 716 /* Open bulk-out pipes (up to 3). */ 717 for (i = 0; i < ntx; i++) { 718 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 719 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 720 if (error != 0) { 721 aprint_error_dev(sc->sc_dev, 722 "could not open Tx bulk pipe 0x%02x: %d\n", 723 epaddr[i], error); 724 goto fail; 725 } 726 } 727 728 /* Map 802.11 access categories to USB pipes. */ 729 sc->ac2idx[WME_AC_BK] = 730 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 731 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 732 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 733 734 fail: 735 if (error != 0) 736 urtwn_close_pipes(sc); 737 return error; 738 } 739 740 static void 741 urtwn_close_pipes(struct urtwn_softc *sc) 742 { 743 struct usbd_pipe *pipe; 744 size_t i; 745 746 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 747 748 /* Close Rx pipes. */ 749 CTASSERT(sizeof(pipe) == sizeof(void *)); 750 for (i = 0; i < sc->rx_npipe; i++) { 751 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 752 if (pipe != NULL) { 753 usbd_close_pipe(pipe); 754 } 755 } 756 757 /* Close Tx pipes. */ 758 for (i = 0; i < sc->tx_npipe; i++) { 759 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 760 if (pipe != NULL) { 761 usbd_close_pipe(pipe); 762 } 763 } 764 } 765 766 static int 767 urtwn_alloc_rx_list(struct urtwn_softc *sc) 768 { 769 struct urtwn_rx_data *data; 770 size_t i; 771 int error = 0; 772 773 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 774 775 for (size_t j = 0; j < sc->rx_npipe; j++) { 776 TAILQ_INIT(&sc->rx_free_list[j]); 777 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 778 data = &sc->rx_data[j][i]; 779 780 data->sc = sc; /* Backpointer for callbacks. */ 781 782 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 783 0, 0, &data->xfer); 784 if (error) { 785 aprint_error_dev(sc->sc_dev, 786 "could not allocate xfer\n"); 787 break; 788 } 789 790 data->buf = usbd_get_buffer(data->xfer); 791 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 792 } 793 } 794 if (error != 0) 795 urtwn_free_rx_list(sc); 796 return error; 797 } 798 799 static void 800 urtwn_free_rx_list(struct urtwn_softc *sc) 801 { 802 struct usbd_xfer *xfer; 803 size_t i; 804 805 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 806 807 /* NB: Caller must abort pipe first. */ 808 for (size_t j = 0; j < sc->rx_npipe; j++) { 809 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 810 CTASSERT(sizeof(xfer) == sizeof(void *)); 811 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 812 if (xfer != NULL) 813 usbd_destroy_xfer(xfer); 814 } 815 } 816 } 817 818 static int 819 urtwn_alloc_tx_list(struct urtwn_softc *sc) 820 { 821 struct urtwn_tx_data *data; 822 size_t i; 823 int error = 0; 824 825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 826 827 mutex_enter(&sc->sc_tx_mtx); 828 for (size_t j = 0; j < sc->tx_npipe; j++) { 829 TAILQ_INIT(&sc->tx_free_list[j]); 830 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 831 data = &sc->tx_data[j][i]; 832 833 data->sc = sc; /* Backpointer for callbacks. */ 834 data->pidx = j; 835 836 error = usbd_create_xfer(sc->tx_pipe[j], 837 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 838 &data->xfer); 839 if (error) { 840 aprint_error_dev(sc->sc_dev, 841 "could not allocate xfer\n"); 842 goto fail; 843 } 844 845 data->buf = usbd_get_buffer(data->xfer); 846 847 /* Append this Tx buffer to our free list. */ 848 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 849 } 850 } 851 mutex_exit(&sc->sc_tx_mtx); 852 return 0; 853 854 fail: 855 urtwn_free_tx_list(sc); 856 mutex_exit(&sc->sc_tx_mtx); 857 return error; 858 } 859 860 static void 861 urtwn_free_tx_list(struct urtwn_softc *sc) 862 { 863 struct usbd_xfer *xfer; 864 size_t i; 865 866 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 867 868 /* NB: Caller must abort pipe first. */ 869 for (size_t j = 0; j < sc->tx_npipe; j++) { 870 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 871 CTASSERT(sizeof(xfer) == sizeof(void *)); 872 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 873 if (xfer != NULL) 874 usbd_destroy_xfer(xfer); 875 } 876 } 877 } 878 879 static int 880 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 881 struct ieee80211_node *ni) 882 { 883 struct urtwn_tx_data *data = 884 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 885 return urtwn_tx(sc, m, ni, data); 886 } 887 888 static void 889 urtwn_task(void *arg) 890 { 891 struct urtwn_softc *sc = arg; 892 struct ieee80211com *ic = &sc->sc_ic; 893 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 894 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 895 struct urtwn_host_cmd *cmd; 896 int s; 897 898 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 899 if (vap->iv_state == IEEE80211_S_RUN && 900 (ic->ic_opmode == IEEE80211_M_HOSTAP || 901 ic->ic_opmode == IEEE80211_M_IBSS)) { 902 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 903 if (m == NULL) { 904 aprint_error_dev(sc->sc_dev, 905 "could not allocate beacon"); 906 } 907 908 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 909 m_freem(m); 910 aprint_error_dev(sc->sc_dev, "could not send beacon"); 911 } 912 913 /* beacon is no longer needed */ 914 m_freem(m); 915 } 916 917 /* Process host commands. */ 918 s = splusb(); 919 mutex_spin_enter(&sc->sc_task_mtx); 920 while (ring->next != ring->cur) { 921 cmd = &ring->cmd[ring->next]; 922 mutex_spin_exit(&sc->sc_task_mtx); 923 splx(s); 924 /* Invoke callback with kernel lock held. */ 925 cmd->cb(sc, cmd->data); 926 s = splusb(); 927 mutex_spin_enter(&sc->sc_task_mtx); 928 ring->queued--; 929 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 930 } 931 mutex_spin_exit(&sc->sc_task_mtx); 932 wakeup(&sc->cmdq); 933 splx(s); 934 } 935 936 static void 937 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 938 void *arg, int len) 939 { 940 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 941 struct urtwn_host_cmd *cmd; 942 int s; 943 944 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 945 device_xname(sc->sc_dev), __func__, cb, arg, len)); 946 947 s = splusb(); 948 mutex_spin_enter(&sc->sc_task_mtx); 949 cmd = &ring->cmd[ring->cur]; 950 cmd->cb = cb; 951 KASSERT(len <= sizeof(cmd->data)); 952 memcpy(cmd->data, arg, len); 953 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 954 955 /* If there is no pending command already, schedule a task. */ 956 if (!sc->sc_dying && ++ring->queued == 1) { 957 mutex_spin_exit(&sc->sc_task_mtx); 958 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 959 } else 960 mutex_spin_exit(&sc->sc_task_mtx); 961 splx(s); 962 } 963 964 static void 965 urtwn_wait_async(struct urtwn_softc *sc) 966 { 967 968 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 969 970 /* Wait for all queued asynchronous commands to complete. */ 971 while (sc->cmdq.queued > 0) 972 tsleep(&sc->cmdq, 0, "endtask", 0); 973 } 974 975 static int 976 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 977 int len) 978 { 979 usb_device_request_t req; 980 usbd_status error; 981 982 KASSERT(mutex_owned(&sc->sc_write_mtx)); 983 984 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 985 req.bRequest = R92C_REQ_REGS; 986 USETW(req.wValue, addr); 987 USETW(req.wIndex, 0); 988 USETW(req.wLength, len); 989 error = usbd_do_request(sc->sc_udev, &req, buf); 990 if (error != USBD_NORMAL_COMPLETION) { 991 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 992 device_xname(sc->sc_dev), __func__, error, addr, len)); 993 } 994 return error; 995 } 996 997 static void 998 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 999 { 1000 1001 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1002 device_xname(sc->sc_dev), __func__, addr, val)); 1003 1004 urtwn_write_region_1(sc, addr, &val, 1); 1005 } 1006 1007 static void 1008 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1009 { 1010 uint8_t buf[2]; 1011 1012 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1013 device_xname(sc->sc_dev), __func__, addr, val)); 1014 1015 buf[0] = (uint8_t)val; 1016 buf[1] = (uint8_t)(val >> 8); 1017 urtwn_write_region_1(sc, addr, buf, 2); 1018 } 1019 1020 static void 1021 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1022 { 1023 uint8_t buf[4]; 1024 1025 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1026 device_xname(sc->sc_dev), __func__, addr, val)); 1027 1028 buf[0] = (uint8_t)val; 1029 buf[1] = (uint8_t)(val >> 8); 1030 buf[2] = (uint8_t)(val >> 16); 1031 buf[3] = (uint8_t)(val >> 24); 1032 urtwn_write_region_1(sc, addr, buf, 4); 1033 } 1034 1035 static int 1036 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1037 { 1038 1039 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, len=%#x\n", 1040 device_xname(sc->sc_dev), __func__, addr, len)); 1041 1042 return urtwn_write_region_1(sc, addr, buf, len); 1043 } 1044 1045 static int 1046 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1047 int len) 1048 { 1049 usb_device_request_t req; 1050 usbd_status error; 1051 1052 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1053 req.bRequest = R92C_REQ_REGS; 1054 USETW(req.wValue, addr); 1055 USETW(req.wIndex, 0); 1056 USETW(req.wLength, len); 1057 error = usbd_do_request(sc->sc_udev, &req, buf); 1058 if (error != USBD_NORMAL_COMPLETION) { 1059 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1060 device_xname(sc->sc_dev), __func__, error, addr, len)); 1061 } 1062 return error; 1063 } 1064 1065 static uint8_t 1066 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1067 { 1068 uint8_t val; 1069 1070 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1071 return 0xff; 1072 1073 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1074 device_xname(sc->sc_dev), __func__, addr, val)); 1075 return val; 1076 } 1077 1078 static uint16_t 1079 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1080 { 1081 uint8_t buf[2]; 1082 uint16_t val; 1083 1084 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1085 return 0xffff; 1086 1087 val = LE_READ_2(&buf[0]); 1088 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1089 device_xname(sc->sc_dev), __func__, addr, val)); 1090 return val; 1091 } 1092 1093 static uint32_t 1094 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1095 { 1096 uint8_t buf[4]; 1097 uint32_t val; 1098 1099 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1100 return 0xffffffff; 1101 1102 val = LE_READ_4(&buf[0]); 1103 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1104 device_xname(sc->sc_dev), __func__, addr, val)); 1105 return val; 1106 } 1107 1108 static int 1109 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1110 { 1111 struct r92c_fw_cmd cmd; 1112 uint8_t *cp; 1113 int fwcur; 1114 int ntries; 1115 1116 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1117 device_xname(sc->sc_dev), __func__, id, buf, len)); 1118 1119 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1120 1121 mutex_enter(&sc->sc_fwcmd_mtx); 1122 fwcur = sc->fwcur; 1123 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1124 mutex_exit(&sc->sc_fwcmd_mtx); 1125 1126 /* Wait for current FW box to be empty. */ 1127 for (ntries = 0; ntries < 100; ntries++) { 1128 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1129 break; 1130 DELAY(2000); 1131 } 1132 if (ntries == 100) { 1133 aprint_error_dev(sc->sc_dev, 1134 "could not send firmware command %d\n", id); 1135 return ETIMEDOUT; 1136 } 1137 1138 memset(&cmd, 0, sizeof(cmd)); 1139 KASSERT(len <= sizeof(cmd.msg)); 1140 memcpy(cmd.msg, buf, len); 1141 1142 /* Write the first word last since that will trigger the FW. */ 1143 cp = (uint8_t *)&cmd; 1144 cmd.id = id; 1145 if (len >= 4) { 1146 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1147 cmd.id |= R92C_CMD_FLAG_EXT; 1148 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1149 &cp[1], 2); 1150 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1151 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1152 (cp[5] << 24)); 1153 } else { 1154 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1155 &cp[4], 2); 1156 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1157 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1158 (cp[3] << 24)); 1159 } 1160 } else { 1161 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1162 } 1163 1164 return 0; 1165 } 1166 1167 static __inline void 1168 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1169 { 1170 1171 sc->sc_rf_write(sc, chain, addr, val); 1172 } 1173 1174 static void 1175 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1176 uint32_t val) 1177 { 1178 1179 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1180 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1181 } 1182 1183 static void 1184 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1185 uint32_t val) 1186 { 1187 1188 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1189 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1190 } 1191 1192 static void 1193 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1194 uint32_t val) 1195 { 1196 1197 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1198 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1199 } 1200 1201 static uint32_t 1202 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1203 { 1204 uint32_t reg[R92C_MAX_CHAINS], val; 1205 1206 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1207 if (chain != 0) { 1208 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1209 } 1210 1211 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1212 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1213 DELAY(1000); 1214 1215 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1216 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1217 R92C_HSSI_PARAM2_READ_EDGE); 1218 DELAY(1000); 1219 1220 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1221 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1222 DELAY(1000); 1223 1224 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1225 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1226 } else { 1227 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1228 } 1229 return MS(val, R92C_LSSI_READBACK_DATA); 1230 } 1231 1232 static int 1233 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1234 { 1235 int ntries; 1236 1237 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1238 1239 urtwn_write_4(sc, R92C_LLT_INIT, 1240 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1241 SM(R92C_LLT_INIT_ADDR, addr) | 1242 SM(R92C_LLT_INIT_DATA, data)); 1243 /* Wait for write operation to complete. */ 1244 for (ntries = 0; ntries < 20; ntries++) { 1245 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1246 R92C_LLT_INIT_OP_NO_ACTIVE) { 1247 /* Done */ 1248 return 0; 1249 } 1250 DELAY(5); 1251 } 1252 return ETIMEDOUT; 1253 } 1254 1255 static uint8_t 1256 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1257 { 1258 uint32_t reg; 1259 int ntries; 1260 1261 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1262 1263 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1264 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1265 reg &= ~R92C_EFUSE_CTRL_VALID; 1266 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1267 1268 /* Wait for read operation to complete. */ 1269 for (ntries = 0; ntries < 100; ntries++) { 1270 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1271 if (reg & R92C_EFUSE_CTRL_VALID) { 1272 /* Done */ 1273 return MS(reg, R92C_EFUSE_CTRL_DATA); 1274 } 1275 DELAY(5); 1276 } 1277 aprint_error_dev(sc->sc_dev, 1278 "could not read efuse byte at address 0x%04x\n", addr); 1279 return 0xff; 1280 } 1281 1282 static void 1283 urtwn_efuse_read(struct urtwn_softc *sc) 1284 { 1285 uint8_t *rom = (uint8_t *)&sc->rom; 1286 uint32_t reg; 1287 uint16_t addr = 0; 1288 uint8_t off, msk; 1289 size_t i; 1290 1291 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1292 1293 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1294 1295 urtwn_efuse_switch_power(sc); 1296 1297 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1298 while (addr < 512) { 1299 reg = urtwn_efuse_read_1(sc, addr); 1300 if (reg == 0xff) 1301 break; 1302 addr++; 1303 off = reg >> 4; 1304 msk = reg & 0xf; 1305 for (i = 0; i < 4; i++) { 1306 if (msk & (1U << i)) 1307 continue; 1308 1309 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1310 addr++; 1311 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1312 addr++; 1313 } 1314 } 1315 #ifdef URTWN_DEBUG 1316 if (urtwn_debug & DBG_INIT) { 1317 /* Dump ROM content. */ 1318 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1319 for (i = 0; i < (int)sizeof(sc->rom); i++) 1320 printf(":%02x", rom[i]); 1321 printf("\n"); 1322 } 1323 #endif 1324 } 1325 1326 static void 1327 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1328 { 1329 uint32_t reg; 1330 1331 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1332 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1333 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1334 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1335 } 1336 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1337 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1338 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1339 reg | R92C_SYS_FUNC_EN_ELDR); 1340 } 1341 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1342 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1343 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1344 urtwn_write_2(sc, R92C_SYS_CLKR, 1345 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1346 } 1347 } 1348 1349 static int 1350 urtwn_read_chipid(struct urtwn_softc *sc) 1351 { 1352 uint32_t reg; 1353 1354 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1355 1356 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1357 ISSET(sc->chip, URTWN_CHIP_92EU)) 1358 return 0; 1359 1360 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1361 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1362 /* test chip, not supported */ 1363 return EIO; 1364 } 1365 if (reg & R92C_SYS_CFG_TYPE_92C) { 1366 sc->chip |= URTWN_CHIP_92C; 1367 /* Check if it is a castrated 8192C. */ 1368 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1369 R92C_HPON_FSM_CHIP_BONDING_ID) == 1370 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1371 sc->chip |= URTWN_CHIP_92C_1T2R; 1372 } 1373 } 1374 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1375 sc->chip |= URTWN_CHIP_UMC; 1376 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1377 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1378 } 1379 } 1380 return 0; 1381 } 1382 1383 #ifdef URTWN_DEBUG 1384 static void 1385 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1386 { 1387 1388 aprint_normal_dev(sc->sc_dev, 1389 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1390 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1391 1392 aprint_normal_dev(sc->sc_dev, 1393 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1394 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1395 1396 aprint_normal_dev(sc->sc_dev, 1397 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1398 rp->macaddr[0], rp->macaddr[1], 1399 rp->macaddr[2], rp->macaddr[3], 1400 rp->macaddr[4], rp->macaddr[5]); 1401 1402 aprint_normal_dev(sc->sc_dev, 1403 "string %s, subcustomer_id %#x\n", 1404 rp->string, rp->subcustomer_id); 1405 1406 aprint_normal_dev(sc->sc_dev, 1407 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1408 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1409 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1410 1411 aprint_normal_dev(sc->sc_dev, 1412 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1413 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1414 rp->ht40_1s_tx_pwr[0][2], 1415 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1416 rp->ht40_1s_tx_pwr[1][2]); 1417 1418 aprint_normal_dev(sc->sc_dev, 1419 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1420 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1421 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1422 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1423 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1424 1425 aprint_normal_dev(sc->sc_dev, 1426 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1427 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1428 rp->ht20_tx_pwr_diff[2] & 0xf, 1429 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1430 rp->ht20_tx_pwr_diff[2] >> 4); 1431 1432 aprint_normal_dev(sc->sc_dev, 1433 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1434 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1435 rp->ofdm_tx_pwr_diff[2] & 0xf, 1436 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1437 rp->ofdm_tx_pwr_diff[2] >> 4); 1438 1439 aprint_normal_dev(sc->sc_dev, 1440 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1441 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1442 rp->ht40_max_pwr[2] & 0xf, 1443 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1444 rp->ht40_max_pwr[2] >> 4); 1445 1446 aprint_normal_dev(sc->sc_dev, 1447 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1448 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1449 rp->ht20_max_pwr[2] & 0xf, 1450 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1451 rp->ht20_max_pwr[2] >> 4); 1452 1453 aprint_normal_dev(sc->sc_dev, 1454 "xtal_calib %d, tssi %d %d, thermal %d\n", 1455 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1456 1457 aprint_normal_dev(sc->sc_dev, 1458 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1459 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1460 1461 aprint_normal_dev(sc->sc_dev, 1462 "channnel_plan %d, version %d customer_id %#x\n", 1463 rp->channel_plan, rp->version, rp->curstomer_id); 1464 } 1465 #endif 1466 1467 static void 1468 urtwn_read_rom(struct urtwn_softc *sc) 1469 { 1470 struct ieee80211com *ic = &sc->sc_ic; 1471 struct r92c_rom *rom = &sc->rom; 1472 1473 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1474 1475 mutex_enter(&sc->sc_write_mtx); 1476 1477 /* Read full ROM image. */ 1478 urtwn_efuse_read(sc); 1479 #ifdef URTWN_DEBUG 1480 if (urtwn_debug & DBG_REG) 1481 urtwn_dump_rom(sc, rom); 1482 #endif 1483 1484 /* XXX Weird but this is what the vendor driver does. */ 1485 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1486 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1487 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1488 1489 DPRINTFN(DBG_INIT, 1490 ("%s: %s: PA setting=%#x, board=%#x, regulatory=%d\n", 1491 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1492 sc->board_type, sc->regulatory)); 1493 1494 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1495 1496 sc->sc_rf_write = urtwn_r92c_rf_write; 1497 sc->sc_power_on = urtwn_r92c_power_on; 1498 sc->sc_dma_init = urtwn_r92c_dma_init; 1499 1500 mutex_exit(&sc->sc_write_mtx); 1501 } 1502 1503 static void 1504 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1505 { 1506 struct ieee80211com *ic = &sc->sc_ic; 1507 uint8_t *rom = sc->r88e_rom; 1508 uint32_t reg; 1509 uint16_t addr = 0; 1510 uint8_t off, msk, tmp; 1511 int i; 1512 1513 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1514 1515 mutex_enter(&sc->sc_write_mtx); 1516 1517 off = 0; 1518 urtwn_efuse_switch_power(sc); 1519 1520 /* Read full ROM image. */ 1521 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1522 while (addr < 4096) { 1523 reg = urtwn_efuse_read_1(sc, addr); 1524 if (reg == 0xff) 1525 break; 1526 addr++; 1527 if ((reg & 0x1f) == 0x0f) { 1528 tmp = (reg & 0xe0) >> 5; 1529 reg = urtwn_efuse_read_1(sc, addr); 1530 if ((reg & 0x0f) != 0x0f) 1531 off = ((reg & 0xf0) >> 1) | tmp; 1532 addr++; 1533 } else 1534 off = reg >> 4; 1535 msk = reg & 0xf; 1536 for (i = 0; i < 4; i++) { 1537 if (msk & (1 << i)) 1538 continue; 1539 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1540 addr++; 1541 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1542 addr++; 1543 } 1544 } 1545 #ifdef URTWN_DEBUG 1546 if (urtwn_debug & DBG_REG) { 1547 } 1548 #endif 1549 1550 addr = 0x10; 1551 for (i = 0; i < 6; i++) 1552 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1553 for (i = 0; i < 5; i++) 1554 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1555 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1556 if (sc->bw20_tx_pwr_diff & 0x08) 1557 sc->bw20_tx_pwr_diff |= 0xf0; 1558 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1559 if (sc->ofdm_tx_pwr_diff & 0x08) 1560 sc->ofdm_tx_pwr_diff |= 0xf0; 1561 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1562 1563 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1564 1565 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1566 sc->sc_power_on = urtwn_r92e_power_on; 1567 sc->sc_rf_write = urtwn_r92e_rf_write; 1568 } else { 1569 sc->sc_power_on = urtwn_r88e_power_on; 1570 sc->sc_rf_write = urtwn_r88e_rf_write; 1571 } 1572 sc->sc_dma_init = urtwn_r88e_dma_init; 1573 1574 mutex_exit(&sc->sc_write_mtx); 1575 } 1576 1577 /* NNN Do we need to do something with this? */ 1578 1579 static __unused int 1580 urtwn_media_change(struct ifnet *ifp) 1581 { 1582 #ifdef URTWN_DEBUG 1583 struct ieee80211vap *vap = ifp->if_softc; 1584 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1585 #endif 1586 int error; 1587 1588 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1589 1590 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1591 return error; 1592 1593 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1594 (IFF_UP | IFF_RUNNING)) { 1595 urtwn_init(ifp); 1596 } 1597 return 0; 1598 } 1599 1600 /* 1601 * Initialize rate adaptation in firmware. 1602 */ 1603 static int 1604 urtwn_ra_init(struct ieee80211vap *vap) 1605 { 1606 static const uint8_t map[] = { 1607 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1608 }; 1609 struct ieee80211com *ic = vap->iv_ic; 1610 struct urtwn_softc *sc = ic->ic_softc; 1611 struct ieee80211_node *ni = vap->iv_bss; 1612 struct ieee80211_rateset *rs = &ni->ni_rates; 1613 1614 struct r92c_fw_cmd_macid_cfg cmd; 1615 uint32_t rates, basicrates; 1616 uint32_t rrsr_mask, rrsr_rate; 1617 uint8_t mode; 1618 size_t maxrate, maxbasicrate, i, j; 1619 int error; 1620 1621 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1622 1623 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1624 1625 /* Get normal and basic rates mask. */ 1626 rates = basicrates = 1; 1627 maxrate = maxbasicrate = 0; 1628 for (i = 0; i < rs->rs_nrates; i++) { 1629 /* Convert 802.11 rate to HW rate index. */ 1630 for (j = 0; j < __arraycount(map); j++) { 1631 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1632 break; 1633 } 1634 } 1635 if (j == __arraycount(map)) { 1636 /* Unknown rate, skip. */ 1637 continue; 1638 } 1639 1640 rates |= 1U << j; 1641 if (j > maxrate) { 1642 maxrate = j; 1643 } 1644 1645 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1646 basicrates |= 1U << j; 1647 if (j > maxbasicrate) { 1648 maxbasicrate = j; 1649 } 1650 } 1651 } 1652 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1653 mode = R92C_RAID_11B; 1654 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 1655 mode = R92C_RAID_11BG; 1656 } else /* mode = IEEE80211_MODE_11NG */ 1657 mode = R92C_RAID_11GN; 1658 DPRINTFN(DBG_INIT, ("%s: %s: mode=%#x rates=%#x, basicrates=%#x, " 1659 "maxrate=%zx, maxbasicrate=%zx\n", 1660 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1661 maxrate, maxbasicrate)); 1662 1663 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1664 maxbasicrate |= R92C_RATE_SHORTGI; 1665 maxrate |= R92C_RATE_SHORTGI; 1666 } 1667 1668 /* Set rates mask for group addressed frames. */ 1669 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1670 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1671 cmd.macid |= RTWN_MACID_SHORTGI; 1672 cmd.mask = htole32((mode << 28) | basicrates); 1673 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1674 if (error != 0) { 1675 aprint_error_dev(sc->sc_dev, 1676 "could not add broadcast station\n"); 1677 return error; 1678 } 1679 /* Set initial MRR rate. */ 1680 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1681 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1682 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1683 1684 /* Set rates mask for unicast frames. */ 1685 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1686 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1687 cmd.macid |= RTWN_MACID_SHORTGI; 1688 cmd.mask = htole32((mode << 28) | rates); 1689 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1690 if (error != 0) { 1691 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1692 return error; 1693 } 1694 /* Set initial MRR rate. */ 1695 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1696 __func__, maxrate)); 1697 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1698 1699 #if notyet 1700 /* NNN appears to have no fixed rate anywhere. */ 1701 rrsr_rate = ic->ic_fixed_rate; 1702 if (rrsr_rate == -1) 1703 #endif 1704 rrsr_rate = 11; 1705 1706 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1707 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1708 1709 #if notyet 1710 /* Indicate highest supported rate. */ 1711 ni->ni_txrate = rs->rs_nrates - 1; 1712 #endif 1713 return 0; 1714 } 1715 1716 static int 1717 urtwn_get_nettype(struct urtwn_softc *sc) 1718 { 1719 struct ieee80211com *ic = &sc->sc_ic; 1720 int type; 1721 1722 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1723 1724 switch (ic->ic_opmode) { 1725 case IEEE80211_M_STA: 1726 type = R92C_CR_NETTYPE_INFRA; 1727 break; 1728 1729 case IEEE80211_M_IBSS: 1730 type = R92C_CR_NETTYPE_ADHOC; 1731 break; 1732 1733 default: 1734 type = R92C_CR_NETTYPE_NOLINK; 1735 break; 1736 } 1737 1738 return type; 1739 } 1740 1741 static void 1742 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1743 { 1744 uint8_t reg; 1745 1746 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1747 __func__, type)); 1748 1749 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1750 1751 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1752 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1753 } 1754 1755 static void 1756 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1757 { 1758 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1759 struct ieee80211_node *ni = vap->iv_bss; 1760 uint64_t tsf; 1761 1762 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1763 1764 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1765 1766 /* Enable TSF synchronization. */ 1767 urtwn_write_1(sc, R92C_BCN_CTRL, 1768 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1769 1770 /* Correct TSF */ 1771 urtwn_write_1(sc, R92C_BCN_CTRL, 1772 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1773 1774 /* Set initial TSF. */ 1775 tsf = ni->ni_tstamp.tsf; 1776 tsf = le64toh(tsf); 1777 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1778 tsf -= IEEE80211_DUR_TU; 1779 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1780 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1781 1782 urtwn_write_1(sc, R92C_BCN_CTRL, 1783 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1784 } 1785 1786 static void 1787 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1788 { 1789 uint8_t reg; 1790 1791 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1792 __func__, led, on)); 1793 1794 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1795 1796 if (led == URTWN_LED_LINK) { 1797 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1798 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1799 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1800 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1801 (R92C_LEDCFG0_DIS << 1)); 1802 if (on) { 1803 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1804 R92E_LEDSON; 1805 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1806 } 1807 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1808 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1809 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1810 if (!on) { 1811 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1812 urtwn_write_1(sc, R92C_LEDCFG2, 1813 reg | R92C_LEDCFG0_DIS); 1814 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1815 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1816 reg & 0xfe); 1817 } 1818 } else { 1819 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1820 if (!on) { 1821 reg |= R92C_LEDCFG0_DIS; 1822 } 1823 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1824 } 1825 sc->ledlink = on; /* Save LED state. */ 1826 } 1827 } 1828 1829 static void 1830 urtwn_calib_to(void *arg) 1831 { 1832 struct urtwn_softc *sc = arg; 1833 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1834 1835 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1836 1837 if (sc->sc_dying) 1838 return; 1839 1840 /* Do it in a process context. */ 1841 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1842 } 1843 1844 /* ARGSUSED */ 1845 static void 1846 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1847 { 1848 struct ieee80211vap *vap = arg; 1849 struct r92c_fw_cmd_rssi cmd; 1850 struct r92e_fw_cmd_rssi cmde; 1851 1852 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1853 1854 if (vap->iv_state != IEEE80211_S_RUN) 1855 goto restart_timer; 1856 1857 mutex_enter(&sc->sc_write_mtx); 1858 if (sc->avg_pwdb != -1) { 1859 /* Indicate Rx signal strength to FW for rate adaptation. */ 1860 memset(&cmd, 0, sizeof(cmd)); 1861 memset(&cmde, 0, sizeof(cmde)); 1862 cmd.macid = 0; /* BSS. */ 1863 cmde.macid = 0; /* BSS. */ 1864 cmd.pwdb = sc->avg_pwdb; 1865 cmde.pwdb = sc->avg_pwdb; 1866 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1867 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1868 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1869 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1870 sizeof(cmd)); 1871 } else { 1872 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1873 sizeof(cmde)); 1874 } 1875 } 1876 1877 /* Do temperature compensation. */ 1878 urtwn_temp_calib(sc); 1879 mutex_exit(&sc->sc_write_mtx); 1880 1881 restart_timer: 1882 if (!sc->sc_dying) { 1883 /* Restart calibration timer. */ 1884 callout_schedule(&sc->sc_calib_to, hz); 1885 } 1886 } 1887 1888 static void 1889 urtwn_next_scan(void *arg) 1890 { 1891 printf ("NNN urtwn_next_scan called....\n"); 1892 #ifdef notyet 1893 struct urtwn_softc *sc = arg; 1894 int s; 1895 1896 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1897 1898 if (sc->sc_dying) 1899 return; 1900 1901 s = splnet(); 1902 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1903 ieee80211_next_scan(&sc->sc_ic); 1904 splx(s); 1905 #endif 1906 } 1907 1908 static void 1909 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1910 { 1911 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1912 ether_sprintf(ni->ni_macaddr))); 1913 1914 /* start with lowest Tx rate */ 1915 ni->ni_txrate = 0; 1916 } 1917 1918 #if OLDSTUFF 1919 static int 1920 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1921 { 1922 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1923 struct urtwn_cmd_newstate cmd; 1924 1925 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1926 device_xname(sc->sc_dev), __func__, 1927 ieee80211_state_name[nstate], nstate, arg)); 1928 1929 callout_stop(&sc->sc_scan_to); 1930 callout_stop(&sc->sc_calib_to); 1931 1932 /* Do it in a process context. */ 1933 cmd.state = nstate; 1934 cmd.arg = arg; 1935 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1936 return 0; 1937 } 1938 1939 static void 1940 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1941 { 1942 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1943 struct urtwn_cmd_newstate *cmd = arg; 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 struct ieee80211_node *ni; 1946 enum ieee80211_state ostate = vap->iv_state; 1947 enum ieee80211_state nstate = cmd->state; 1948 uint32_t reg; 1949 uint8_t sifs_time, msr; 1950 int s; 1951 1952 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1953 device_xname(sc->sc_dev), __func__, 1954 ieee80211_state_name[ostate], ostate, 1955 ieee80211_state_name[nstate], nstate)); 1956 1957 s = splnet(); 1958 mutex_enter(&sc->sc_write_mtx); 1959 1960 callout_stop(&sc->sc_scan_to); 1961 callout_stop(&sc->sc_calib_to); 1962 1963 switch (ostate) { 1964 case IEEE80211_S_INIT: 1965 break; 1966 1967 case IEEE80211_S_SCAN: 1968 if (nstate != IEEE80211_S_SCAN) { 1969 /* 1970 * End of scanning 1971 */ 1972 /* flush 4-AC Queue after site_survey */ 1973 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1974 1975 /* Allow Rx from our BSSID only. */ 1976 urtwn_write_4(sc, R92C_RCR, 1977 urtwn_read_4(sc, R92C_RCR) | 1978 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1979 } 1980 break; 1981 1982 case IEEE80211_S_AUTH: 1983 case IEEE80211_S_ASSOC: 1984 break; 1985 1986 case IEEE80211_S_RUN: 1987 /* Turn link LED off. */ 1988 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1989 1990 /* Set media status to 'No Link'. */ 1991 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1992 1993 /* Stop Rx of data frames. */ 1994 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1995 1996 /* Reset TSF. */ 1997 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1998 1999 /* Disable TSF synchronization. */ 2000 urtwn_write_1(sc, R92C_BCN_CTRL, 2001 urtwn_read_1(sc, R92C_BCN_CTRL) | 2002 R92C_BCN_CTRL_DIS_TSF_UDT0); 2003 2004 /* Back to 20MHz mode */ 2005 urtwn_set_chan(sc, ic->ic_curchan, 2006 IEEE80211_HTINFO_2NDCHAN_NONE); 2007 2008 if (ic->ic_opmode == IEEE80211_M_IBSS || 2009 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2010 /* Stop BCN */ 2011 urtwn_write_1(sc, R92C_BCN_CTRL, 2012 urtwn_read_1(sc, R92C_BCN_CTRL) & 2013 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2014 } 2015 2016 /* Reset EDCA parameters. */ 2017 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2018 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2019 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2020 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2021 2022 /* flush all cam entries */ 2023 urtwn_cam_init(sc); 2024 break; 2025 case IEEE80211_S_CAC: 2026 case IEEE80211_S_CSA: 2027 case IEEE80211_S_SLEEP: 2028 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2029 /* NNN what do we do in these states? XXX */ 2030 break; 2031 } 2032 2033 switch (nstate) { 2034 case IEEE80211_S_INIT: 2035 /* Turn link LED off. */ 2036 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2037 break; 2038 2039 case IEEE80211_S_SCAN: 2040 if (ostate != IEEE80211_S_SCAN) { 2041 /* 2042 * Begin of scanning 2043 */ 2044 2045 /* Set gain for scanning. */ 2046 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2047 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2048 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2049 2050 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2051 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2052 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2053 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2054 } 2055 2056 /* Set media status to 'No Link'. */ 2057 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2058 2059 /* Allow Rx from any BSSID. */ 2060 urtwn_write_4(sc, R92C_RCR, 2061 urtwn_read_4(sc, R92C_RCR) & 2062 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2063 2064 /* Stop Rx of data frames. */ 2065 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2066 2067 /* Disable update TSF */ 2068 urtwn_write_1(sc, R92C_BCN_CTRL, 2069 urtwn_read_1(sc, R92C_BCN_CTRL) | 2070 R92C_BCN_CTRL_DIS_TSF_UDT0); 2071 } 2072 2073 /* Make link LED blink during scan. */ 2074 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2075 2076 /* Pause AC Tx queues. */ 2077 urtwn_write_1(sc, R92C_TXPAUSE, 2078 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2079 2080 urtwn_set_chan(sc, ic->ic_curchan, 2081 IEEE80211_HTINFO_2NDCHAN_NONE); 2082 2083 /* Start periodic scan. */ 2084 if (!sc->sc_dying) 2085 callout_schedule(&sc->sc_scan_to, hz / 5); 2086 break; 2087 2088 case IEEE80211_S_AUTH: 2089 /* Set initial gain under link. */ 2090 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2091 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2092 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2093 2094 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2095 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2096 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2097 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2098 } 2099 2100 /* Set media status to 'No Link'. */ 2101 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2102 2103 /* Allow Rx from any BSSID. */ 2104 urtwn_write_4(sc, R92C_RCR, 2105 urtwn_read_4(sc, R92C_RCR) & 2106 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2107 2108 urtwn_set_chan(sc, ic->ic_curchan, 2109 IEEE80211_HTINFO_2NDCHAN_NONE); 2110 break; 2111 2112 case IEEE80211_S_ASSOC: 2113 break; 2114 2115 case IEEE80211_S_RUN: 2116 ni = vap->iv_bss; 2117 2118 /* XXX: Set 20MHz mode */ 2119 urtwn_set_chan(sc, ic->ic_curchan, 2120 IEEE80211_HTINFO_2NDCHAN_NONE); 2121 2122 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2123 /* Back to 20MHz mode */ 2124 urtwn_set_chan(sc, ic->ic_curchan, 2125 IEEE80211_HTINFO_2NDCHAN_NONE); 2126 2127 /* Set media status to 'No Link'. */ 2128 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2129 2130 /* Enable Rx of data frames. */ 2131 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2132 2133 /* Allow Rx from any BSSID. */ 2134 urtwn_write_4(sc, R92C_RCR, 2135 urtwn_read_4(sc, R92C_RCR) & 2136 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2137 2138 /* Accept Rx data/control/management frames */ 2139 urtwn_write_4(sc, R92C_RCR, 2140 urtwn_read_4(sc, R92C_RCR) | 2141 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2142 2143 /* Turn link LED on. */ 2144 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2145 break; 2146 } 2147 2148 /* Set media status to 'Associated'. */ 2149 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2150 2151 /* Set BSSID. */ 2152 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2153 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2154 2155 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2156 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2157 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2158 /* 802.11b/g */ 2159 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2160 } else /* IEEE_MODE_11NG */ 2161 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2162 2163 /* Enable Rx of data frames. */ 2164 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2165 2166 /* Set beacon interval. */ 2167 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2168 2169 msr = urtwn_read_1(sc, R92C_MSR); 2170 msr &= R92C_MSR_MASK; 2171 switch (ic->ic_opmode) { 2172 case IEEE80211_M_STA: 2173 /* Allow Rx from our BSSID only. */ 2174 urtwn_write_4(sc, R92C_RCR, 2175 urtwn_read_4(sc, R92C_RCR) | 2176 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2177 2178 /* Enable TSF synchronization. */ 2179 urtwn_tsf_sync_enable(sc); 2180 2181 msr |= R92C_MSR_INFRA; 2182 break; 2183 case IEEE80211_M_HOSTAP: 2184 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2185 2186 /* Allow Rx from any BSSID. */ 2187 urtwn_write_4(sc, R92C_RCR, 2188 urtwn_read_4(sc, R92C_RCR) & 2189 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2190 2191 /* Reset TSF timer to zero. */ 2192 reg = urtwn_read_4(sc, R92C_TCR); 2193 reg &= ~0x01; 2194 urtwn_write_4(sc, R92C_TCR, reg); 2195 reg |= 0x01; 2196 urtwn_write_4(sc, R92C_TCR, reg); 2197 2198 msr |= R92C_MSR_AP; 2199 break; 2200 default: 2201 msr |= R92C_MSR_ADHOC; 2202 break; 2203 } 2204 urtwn_write_1(sc, R92C_MSR, msr); 2205 2206 sifs_time = 10; 2207 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2208 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2209 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2210 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2211 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2212 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2213 2214 /* Initialize rate adaptation. */ 2215 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2216 ISSET(sc->chip, URTWN_CHIP_92EU)) 2217 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2218 else 2219 urtwn_ra_init(vap); 2220 2221 /* Turn link LED on. */ 2222 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2223 2224 /* Reset average RSSI. */ 2225 sc->avg_pwdb = -1; 2226 2227 /* Reset temperature calibration state machine. */ 2228 sc->thcal_state = 0; 2229 sc->thcal_lctemp = 0; 2230 2231 /* Start periodic calibration. */ 2232 if (!sc->sc_dying) 2233 callout_schedule(&sc->sc_calib_to, hz); 2234 break; 2235 case IEEE80211_S_CAC: 2236 case IEEE80211_S_CSA: 2237 case IEEE80211_S_SLEEP: 2238 /* NNN what do we do in these states? XXX */ 2239 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2240 break; 2241 } 2242 /* newstate functions expect the ic to be locked. */ 2243 IEEE80211_LOCK(ic); 2244 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2245 IEEE80211_UNLOCK(ic); 2246 2247 mutex_exit(&sc->sc_write_mtx); 2248 splx(s); 2249 } 2250 #endif 2251 2252 static int 2253 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2254 { 2255 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2256 struct ieee80211com *ic = &sc->sc_ic; 2257 struct ieee80211_node *ni; 2258 enum ieee80211_state ostate = vap->iv_state; 2259 uint32_t reg; 2260 uint8_t sifs_time, msr; 2261 int s; 2262 int error; 2263 2264 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2265 device_xname(sc->sc_dev), __func__, 2266 ieee80211_state_name[ostate], ostate, 2267 ieee80211_state_name[nstate], nstate)); 2268 2269 s = splnet(); 2270 mutex_enter(&sc->sc_write_mtx); 2271 2272 callout_stop(&sc->sc_scan_to); 2273 callout_stop(&sc->sc_calib_to); 2274 2275 switch (ostate) { 2276 case IEEE80211_S_INIT: 2277 break; 2278 2279 case IEEE80211_S_SCAN: 2280 if (nstate != IEEE80211_S_SCAN) { 2281 /* 2282 * End of scanning 2283 */ 2284 /* flush 4-AC Queue after site_survey */ 2285 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2286 2287 /* Allow Rx from our BSSID only. */ 2288 urtwn_write_4(sc, R92C_RCR, 2289 urtwn_read_4(sc, R92C_RCR) | 2290 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2291 } 2292 break; 2293 2294 case IEEE80211_S_AUTH: 2295 case IEEE80211_S_ASSOC: 2296 break; 2297 2298 case IEEE80211_S_RUN: 2299 /* Turn link LED off. */ 2300 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2301 2302 /* Set media status to 'No Link'. */ 2303 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2304 2305 /* Stop Rx of data frames. */ 2306 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2307 2308 /* Reset TSF. */ 2309 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2310 2311 /* Disable TSF synchronization. */ 2312 urtwn_write_1(sc, R92C_BCN_CTRL, 2313 urtwn_read_1(sc, R92C_BCN_CTRL) | 2314 R92C_BCN_CTRL_DIS_TSF_UDT0); 2315 2316 /* Back to 20MHz mode */ 2317 urtwn_set_chan(sc, ic->ic_curchan, 2318 IEEE80211_HTINFO_2NDCHAN_NONE); 2319 2320 if (ic->ic_opmode == IEEE80211_M_IBSS || 2321 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2322 /* Stop BCN */ 2323 urtwn_write_1(sc, R92C_BCN_CTRL, 2324 urtwn_read_1(sc, R92C_BCN_CTRL) & 2325 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2326 } 2327 2328 /* Reset EDCA parameters. */ 2329 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2330 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2331 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2332 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2333 2334 /* flush all cam entries */ 2335 urtwn_cam_init(sc); 2336 break; 2337 case IEEE80211_S_CAC: 2338 case IEEE80211_S_CSA: 2339 case IEEE80211_S_SLEEP: 2340 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2341 /* NNN what do we do in these states? XXX */ 2342 break; 2343 } 2344 2345 switch (nstate) { 2346 case IEEE80211_S_INIT: 2347 /* Turn link LED off. */ 2348 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2349 break; 2350 2351 case IEEE80211_S_SCAN: 2352 if (ostate != IEEE80211_S_SCAN) { 2353 /* 2354 * Begin of scanning 2355 */ 2356 2357 /* Set gain for scanning. */ 2358 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2359 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2360 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2361 2362 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2363 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2364 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2365 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2366 } 2367 2368 /* Set media status to 'No Link'. */ 2369 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2370 2371 /* Allow Rx from any BSSID. */ 2372 urtwn_write_4(sc, R92C_RCR, 2373 urtwn_read_4(sc, R92C_RCR) & 2374 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2375 2376 /* Stop Rx of data frames. */ 2377 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2378 2379 /* Disable update TSF */ 2380 urtwn_write_1(sc, R92C_BCN_CTRL, 2381 urtwn_read_1(sc, R92C_BCN_CTRL) | 2382 R92C_BCN_CTRL_DIS_TSF_UDT0); 2383 } 2384 2385 /* Make link LED blink during scan. */ 2386 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2387 2388 /* Pause AC Tx queues. */ 2389 urtwn_write_1(sc, R92C_TXPAUSE, 2390 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2391 2392 urtwn_set_chan(sc, ic->ic_curchan, 2393 IEEE80211_HTINFO_2NDCHAN_NONE); 2394 2395 /* Start periodic scan. */ 2396 if (!sc->sc_dying) 2397 callout_schedule(&sc->sc_scan_to, hz / 5); 2398 break; 2399 2400 case IEEE80211_S_AUTH: 2401 /* Set initial gain under link. */ 2402 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2403 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2404 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2405 2406 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2407 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2408 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2409 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2410 } 2411 2412 /* Set media status to 'No Link'. */ 2413 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2414 2415 /* Allow Rx from any BSSID. */ 2416 urtwn_write_4(sc, R92C_RCR, 2417 urtwn_read_4(sc, R92C_RCR) & 2418 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2419 2420 urtwn_set_chan(sc, ic->ic_curchan, 2421 IEEE80211_HTINFO_2NDCHAN_NONE); 2422 break; 2423 2424 case IEEE80211_S_ASSOC: 2425 break; 2426 2427 case IEEE80211_S_RUN: 2428 ni = vap->iv_bss; 2429 2430 /* XXX: Set 20MHz mode */ 2431 urtwn_set_chan(sc, ic->ic_curchan, 2432 IEEE80211_HTINFO_2NDCHAN_NONE); 2433 2434 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2435 /* Back to 20MHz mode */ 2436 urtwn_set_chan(sc, ic->ic_curchan, 2437 IEEE80211_HTINFO_2NDCHAN_NONE); 2438 2439 /* Set media status to 'No Link'. */ 2440 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2441 2442 /* Enable Rx of data frames. */ 2443 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2444 2445 /* Allow Rx from any BSSID. */ 2446 urtwn_write_4(sc, R92C_RCR, 2447 urtwn_read_4(sc, R92C_RCR) & 2448 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2449 2450 /* Accept Rx data/control/management frames */ 2451 urtwn_write_4(sc, R92C_RCR, 2452 urtwn_read_4(sc, R92C_RCR) | 2453 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2454 2455 /* Turn link LED on. */ 2456 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2457 break; 2458 } 2459 2460 /* Set media status to 'Associated'. */ 2461 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2462 2463 /* Set BSSID. */ 2464 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2465 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2466 2467 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2468 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2469 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2470 /* 802.11b/g */ 2471 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2472 } else /* IEEE_MODE_11NG */ 2473 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2474 2475 /* Enable Rx of data frames. */ 2476 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2477 2478 /* Set beacon interval. */ 2479 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2480 2481 msr = urtwn_read_1(sc, R92C_MSR); 2482 msr &= R92C_MSR_MASK; 2483 switch (ic->ic_opmode) { 2484 case IEEE80211_M_STA: 2485 /* Allow Rx from our BSSID only. */ 2486 urtwn_write_4(sc, R92C_RCR, 2487 urtwn_read_4(sc, R92C_RCR) | 2488 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2489 2490 /* Enable TSF synchronization. */ 2491 urtwn_tsf_sync_enable(sc); 2492 2493 msr |= R92C_MSR_INFRA; 2494 break; 2495 case IEEE80211_M_HOSTAP: 2496 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2497 2498 /* Allow Rx from any BSSID. */ 2499 urtwn_write_4(sc, R92C_RCR, 2500 urtwn_read_4(sc, R92C_RCR) & 2501 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2502 2503 /* Reset TSF timer to zero. */ 2504 reg = urtwn_read_4(sc, R92C_TCR); 2505 reg &= ~0x01; 2506 urtwn_write_4(sc, R92C_TCR, reg); 2507 reg |= 0x01; 2508 urtwn_write_4(sc, R92C_TCR, reg); 2509 2510 msr |= R92C_MSR_AP; 2511 break; 2512 default: 2513 msr |= R92C_MSR_ADHOC; 2514 break; 2515 } 2516 urtwn_write_1(sc, R92C_MSR, msr); 2517 2518 sifs_time = 10; 2519 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2520 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2521 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2522 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2523 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2524 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2525 2526 /* Initialize rate adaptation. */ 2527 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2528 ISSET(sc->chip, URTWN_CHIP_92EU)) 2529 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2530 else 2531 urtwn_ra_init(vap); 2532 2533 /* Turn link LED on. */ 2534 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2535 2536 /* Reset average RSSI. */ 2537 sc->avg_pwdb = -1; 2538 2539 /* Reset temperature calibration state machine. */ 2540 sc->thcal_state = 0; 2541 sc->thcal_lctemp = 0; 2542 2543 /* Start periodic calibration. */ 2544 if (!sc->sc_dying) 2545 callout_schedule(&sc->sc_calib_to, hz); 2546 break; 2547 case IEEE80211_S_CAC: 2548 case IEEE80211_S_CSA: 2549 case IEEE80211_S_SLEEP: 2550 /* NNN what do we do in these states? XXX */ 2551 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2552 break; 2553 } 2554 mutex_exit(&sc->sc_write_mtx); 2555 2556 /* newstate functions expect the ic to be locked. */ 2557 error = (*sc->sc_newstate)(vap, nstate, arg); 2558 2559 splx(s); 2560 return error; 2561 } 2562 2563 static int 2564 urtwn_wme_update(struct ieee80211com *ic) 2565 { 2566 struct urtwn_softc *sc = ic->ic_softc; 2567 2568 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2569 2570 /* don't override default WME values if WME is not actually enabled */ 2571 if (!(ic->ic_flags & IEEE80211_F_WME)) 2572 return 0; 2573 2574 /* Do it in a process context. */ 2575 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2576 return 0; 2577 } 2578 2579 static void 2580 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2581 { 2582 static const uint16_t ac2reg[WME_NUM_AC] = { 2583 R92C_EDCA_BE_PARAM, 2584 R92C_EDCA_BK_PARAM, 2585 R92C_EDCA_VI_PARAM, 2586 R92C_EDCA_VO_PARAM 2587 }; 2588 struct ieee80211com *ic = &sc->sc_ic; 2589 const struct wmeParams *wmep; 2590 int ac, aifs, slottime; 2591 int s; 2592 2593 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2594 __func__)); 2595 2596 s = splnet(); 2597 mutex_enter(&sc->sc_write_mtx); 2598 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2599 for (ac = 0; ac < WME_NUM_AC; ac++) { 2600 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2601 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2602 aifs = wmep->wmep_aifsn * slottime + 10; 2603 urtwn_write_4(sc, ac2reg[ac], 2604 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2605 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2606 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2607 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2608 } 2609 mutex_exit(&sc->sc_write_mtx); 2610 splx(s); 2611 } 2612 2613 static void 2614 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2615 { 2616 int pwdb; 2617 2618 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2619 device_xname(sc->sc_dev), __func__, rate, rssi)); 2620 2621 /* Convert antenna signal to percentage. */ 2622 if (rssi <= -100 || rssi >= 20) 2623 pwdb = 0; 2624 else if (rssi >= 0) 2625 pwdb = 100; 2626 else 2627 pwdb = 100 + rssi; 2628 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2629 if (rate <= 3) { 2630 /* CCK gain is smaller than OFDM/MCS gain. */ 2631 pwdb += 6; 2632 if (pwdb > 100) 2633 pwdb = 100; 2634 if (pwdb <= 14) 2635 pwdb -= 4; 2636 else if (pwdb <= 26) 2637 pwdb -= 8; 2638 else if (pwdb <= 34) 2639 pwdb -= 6; 2640 else if (pwdb <= 42) 2641 pwdb -= 2; 2642 } 2643 } 2644 if (sc->avg_pwdb == -1) /* Init. */ 2645 sc->avg_pwdb = pwdb; 2646 else if (sc->avg_pwdb < pwdb) 2647 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2648 else 2649 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2650 2651 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2652 device_xname(sc->sc_dev), __func__, 2653 rate, rssi, pwdb, sc->avg_pwdb)); 2654 } 2655 2656 static int8_t 2657 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2658 { 2659 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2660 struct r92c_rx_phystat *phy; 2661 struct r92c_rx_cck *cck; 2662 uint8_t rpt; 2663 int8_t rssi; 2664 2665 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2666 __func__, rate)); 2667 2668 if (rate <= 3) { 2669 cck = (struct r92c_rx_cck *)physt; 2670 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2671 rpt = (cck->agc_rpt >> 5) & 0x3; 2672 rssi = (cck->agc_rpt & 0x1f) << 1; 2673 } else { 2674 rpt = (cck->agc_rpt >> 6) & 0x3; 2675 rssi = cck->agc_rpt & 0x3e; 2676 } 2677 rssi = cckoff[rpt] - rssi; 2678 } else { /* OFDM/HT. */ 2679 phy = (struct r92c_rx_phystat *)physt; 2680 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2681 } 2682 return rssi; 2683 } 2684 2685 static int8_t 2686 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2687 { 2688 struct r92c_rx_phystat *phy; 2689 struct r88e_rx_cck *cck; 2690 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2691 int8_t rssi; 2692 2693 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2694 __func__, rate)); 2695 2696 rssi = 0; 2697 if (rate <= 3) { 2698 cck = (struct r88e_rx_cck *)physt; 2699 cck_agc_rpt = cck->agc_rpt; 2700 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2701 vga_idx = cck_agc_rpt & 0x1f; 2702 switch (lna_idx) { 2703 case 7: 2704 if (vga_idx <= 27) 2705 rssi = -100 + 2* (27 - vga_idx); 2706 else 2707 rssi = -100; 2708 break; 2709 case 6: 2710 rssi = -48 + 2 * (2 - vga_idx); 2711 break; 2712 case 5: 2713 rssi = -42 + 2 * (7 - vga_idx); 2714 break; 2715 case 4: 2716 rssi = -36 + 2 * (7 - vga_idx); 2717 break; 2718 case 3: 2719 rssi = -24 + 2 * (7 - vga_idx); 2720 break; 2721 case 2: 2722 rssi = -12 + 2 * (5 - vga_idx); 2723 break; 2724 case 1: 2725 rssi = 8 - (2 * vga_idx); 2726 break; 2727 case 0: 2728 rssi = 14 - (2 * vga_idx); 2729 break; 2730 } 2731 rssi += 6; 2732 } else { /* OFDM/HT. */ 2733 phy = (struct r92c_rx_phystat *)physt; 2734 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2735 } 2736 return rssi; 2737 } 2738 2739 static void 2740 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2741 { 2742 struct ieee80211com *ic = &sc->sc_ic; 2743 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2744 struct ifnet *ifp = vap->iv_ifp; 2745 struct ieee80211_frame *wh; 2746 struct ieee80211_node *ni; 2747 struct r92c_rx_desc_usb *stat; 2748 uint32_t rxdw0, rxdw3; 2749 struct mbuf *m; 2750 uint8_t rate; 2751 int8_t rssi = 0; 2752 int s, infosz; 2753 2754 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2755 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2756 2757 stat = (struct r92c_rx_desc_usb *)buf; 2758 rxdw0 = le32toh(stat->rxdw0); 2759 rxdw3 = le32toh(stat->rxdw3); 2760 2761 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2762 /* 2763 * This should not happen since we setup our Rx filter 2764 * to not receive these frames. 2765 */ 2766 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2767 device_xname(sc->sc_dev), __func__)); 2768 if_statinc(ifp, if_ierrors); 2769 return; 2770 } 2771 2772 /* 2773 * XXX: This will drop most control packets. Do we really 2774 * want this in IEEE80211_M_MONITOR mode? 2775 */ 2776 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2777 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2778 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2779 device_xname(sc->sc_dev), __func__, pktlen)); 2780 vap->iv_stats.is_rx_tooshort++; 2781 if_statinc(ifp,if_ierrors); 2782 return; 2783 } 2784 if (__predict_false(pktlen > MCLBYTES)) { 2785 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2786 device_xname(sc->sc_dev), __func__, pktlen)); 2787 if_statinc(ifp, if_ierrors); 2788 return; 2789 } 2790 2791 rate = MS(rxdw3, R92C_RXDW3_RATE); 2792 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2793 2794 /* Get RSSI from PHY status descriptor if present. */ 2795 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2796 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2797 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2798 else 2799 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2800 /* Update our average RSSI. */ 2801 urtwn_update_avgrssi(sc, rate, rssi); 2802 } 2803 2804 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2805 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2806 2807 MGETHDR(m, M_DONTWAIT, MT_DATA); 2808 if (__predict_false(m == NULL)) { 2809 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2810 vap->iv_stats.is_rx_nobuf++; 2811 if_statinc(ifp, if_ierrors); 2812 return; 2813 } 2814 if (pktlen > (int)MHLEN) { 2815 MCLGET(m, M_DONTWAIT); 2816 if (__predict_false(!(m->m_flags & M_EXT))) { 2817 aprint_error_dev(sc->sc_dev, 2818 "couldn't allocate rx mbuf cluster\n"); 2819 m_freem(m); 2820 vap->iv_stats.is_rx_nobuf++; 2821 if_statinc(ifp, if_ierrors); 2822 return; 2823 } 2824 } 2825 2826 /* Finalize mbuf. */ 2827 m_set_rcvif(m, ifp); 2828 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2829 2830 memcpy(mtod(m, uint8_t *), wh, pktlen); 2831 m->m_pkthdr.len = m->m_len = pktlen; 2832 2833 s = splnet(); 2834 if (__predict_false(sc->sc_drvbpf != NULL)) { 2835 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2836 2837 tap->wr_flags = 0; 2838 if (!(rxdw3 & R92C_RXDW3_HT)) { 2839 switch (rate) { 2840 /* CCK. */ 2841 case 0: tap->wr_rate = 2; break; 2842 case 1: tap->wr_rate = 4; break; 2843 case 2: tap->wr_rate = 11; break; 2844 case 3: tap->wr_rate = 22; break; 2845 /* OFDM. */ 2846 case 4: tap->wr_rate = 12; break; 2847 case 5: tap->wr_rate = 18; break; 2848 case 6: tap->wr_rate = 24; break; 2849 case 7: tap->wr_rate = 36; break; 2850 case 8: tap->wr_rate = 48; break; 2851 case 9: tap->wr_rate = 72; break; 2852 case 10: tap->wr_rate = 96; break; 2853 case 11: tap->wr_rate = 108; break; 2854 } 2855 } else if (rate >= 12) { /* MCS0~15. */ 2856 /* Bit 7 set means HT MCS instead of rate. */ 2857 tap->wr_rate = 0x80 | (rate - 12); 2858 } 2859 tap->wr_dbm_antsignal = rssi; 2860 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2861 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2862 2863 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2864 } 2865 2866 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2867 2868 if (ni != NULL) { 2869 if (ni->ni_vap != NULL) { 2870 2871 } else { 2872 splx(s); 2873 return; 2874 } 2875 /* push the frame up to the 802.11 stack */ 2876 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2877 ieee80211_input(ni, m, rssi+90, 0); 2878 2879 /* Node is no longer needed. */ 2880 ieee80211_free_node(ni); 2881 2882 } else { 2883 2884 /* No node found ... process differently. */ 2885 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2886 } 2887 2888 splx(s); 2889 } 2890 2891 static void 2892 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2893 { 2894 struct urtwn_rx_data *data = priv; 2895 struct urtwn_softc *sc = data->sc; 2896 struct r92c_rx_desc_usb *stat; 2897 size_t pidx = data->pidx; 2898 uint32_t rxdw0; 2899 uint8_t *buf; 2900 int len, totlen, pktlen, infosz, npkts; 2901 2902 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2903 device_xname(sc->sc_dev), __func__, status)); 2904 2905 mutex_enter(&sc->sc_rx_mtx); 2906 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2907 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2908 /* Put this Rx buffer back to our free list. */ 2909 mutex_exit(&sc->sc_rx_mtx); 2910 2911 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2912 if (status == USBD_STALLED) 2913 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2914 else if (status != USBD_CANCELLED) 2915 goto resubmit; 2916 return; 2917 } 2918 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2919 2920 if (__predict_false(len < (int)sizeof(*stat))) { 2921 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2922 device_xname(sc->sc_dev), __func__, len)); 2923 goto resubmit; 2924 } 2925 buf = data->buf; 2926 2927 /* Get the number of encapsulated frames. */ 2928 stat = (struct r92c_rx_desc_usb *)buf; 2929 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2930 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2931 else 2932 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2933 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2934 device_xname(sc->sc_dev), __func__, npkts)); 2935 2936 /* Process all of them. */ 2937 while (npkts-- > 0) { 2938 if (__predict_false(len < (int)sizeof(*stat))) { 2939 DPRINTFN(DBG_RX, 2940 ("%s: %s: len(%d) is short than header\n", 2941 device_xname(sc->sc_dev), __func__, len)); 2942 break; 2943 } 2944 stat = (struct r92c_rx_desc_usb *)buf; 2945 rxdw0 = le32toh(stat->rxdw0); 2946 2947 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2948 if (__predict_false(pktlen == 0)) { 2949 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2950 device_xname(sc->sc_dev), __func__)); 2951 break; 2952 } 2953 2954 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2955 2956 /* Make sure everything fits in xfer. */ 2957 totlen = sizeof(*stat) + infosz + pktlen; 2958 if (__predict_false(totlen > len)) { 2959 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2960 device_xname(sc->sc_dev), __func__, totlen, 2961 (int)sizeof(*stat), infosz, pktlen, len)); 2962 break; 2963 } 2964 2965 /* Process 802.11 frame. */ 2966 urtwn_rx_frame(sc, buf, pktlen); 2967 2968 /* Next chunk is 128-byte aligned. */ 2969 totlen = roundup2(totlen, 128); 2970 buf += totlen; 2971 len -= totlen; 2972 } 2973 2974 resubmit: 2975 /* Setup a new transfer. */ 2976 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2977 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2978 (void)usbd_transfer(xfer); 2979 } 2980 2981 static void 2982 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2983 { 2984 struct urtwn_tx_data *data = priv; 2985 struct urtwn_softc *sc = data->sc; 2986 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 2987 size_t pidx = data->pidx; 2988 int s; 2989 2990 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2991 device_xname(sc->sc_dev), __func__, status)); 2992 2993 mutex_enter(&sc->sc_tx_mtx); 2994 /* Put this Tx buffer back to our free list. */ 2995 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2996 mutex_exit(&sc->sc_tx_mtx); 2997 2998 s = splnet(); 2999 sc->tx_timer = 0; 3000 ifp->if_flags &= ~IFF_OACTIVE; 3001 3002 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 3003 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 3004 if (status == USBD_STALLED) { 3005 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 3006 usbd_clear_endpoint_stall_async(pipe); 3007 } 3008 printf("ERROR1\n"); 3009 if_statinc(ifp, if_oerrors); 3010 } 3011 splx(s); 3012 return; 3013 } 3014 3015 if_statinc(ifp, if_opackets); 3016 urtwn_start(ifp); 3017 splx(s); 3018 3019 } 3020 3021 static int 3022 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3023 struct urtwn_tx_data *data) 3024 { 3025 struct ieee80211com *ic = &sc->sc_ic; 3026 struct ieee80211_frame *wh; 3027 struct ieee80211_key *k = NULL; 3028 struct r92c_tx_desc_usb *txd; 3029 size_t i, padsize, xferlen, txd_len; 3030 uint16_t seq, sum; 3031 uint8_t raid, type, tid; 3032 int s, hasqos, error; 3033 3034 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3035 3036 wh = mtod(m, struct ieee80211_frame *); 3037 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3038 txd_len = sizeof(*txd); 3039 3040 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3041 txd_len = 32; 3042 3043 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3044 k = ieee80211_crypto_encap(ni, m); 3045 if (k == NULL) 3046 return ENOBUFS; 3047 3048 /* packet header may have moved, reset our local pointer */ 3049 wh = mtod(m, struct ieee80211_frame *); 3050 } 3051 3052 if (__predict_false(sc->sc_drvbpf != NULL)) { 3053 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3054 3055 tap->wt_flags = 0; 3056 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3057 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3058 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3059 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3060 3061 /* XXX: set tap->wt_rate? */ 3062 3063 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3064 } 3065 3066 /* non-qos data frames */ 3067 tid = R92C_TXDW1_QSEL_BE; 3068 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3069 /* data frames in 11n mode */ 3070 struct ieee80211_qosframe *qwh = (void *)wh; 3071 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3072 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3073 tid = R92C_TXDW1_QSEL_MGNT; 3074 } 3075 3076 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3077 padsize = 8; 3078 else 3079 padsize = 0; 3080 3081 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3082 padsize = 0; 3083 3084 /* Fill Tx descriptor. */ 3085 txd = (struct r92c_tx_desc_usb *)data->buf; 3086 memset(txd, 0, txd_len + padsize); 3087 3088 txd->txdw0 |= htole32( 3089 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3090 SM(R92C_TXDW0_OFFSET, txd_len)); 3091 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3092 txd->txdw0 |= htole32( 3093 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3094 } 3095 3096 if (ic->ic_curmode == IEEE80211_MODE_11NG) 3097 txd->txdw5 |= htole32(R92C_TXDW5_SGI); 3098 3099 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3100 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3101 3102 /* fix pad field */ 3103 if (padsize > 0) { 3104 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3105 device_xname(sc->sc_dev), __func__, padsize)); 3106 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3107 } 3108 3109 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3110 type == IEEE80211_FC0_TYPE_DATA) { 3111 if (ic->ic_curmode == IEEE80211_MODE_11B) 3112 raid = R92C_RAID_11B; 3113 else if (ic->ic_curmode == IEEE80211_MODE_11G) 3114 raid = R92C_RAID_11BG; 3115 else /* IEEE80211_MODE_11NG */ 3116 raid = R92C_RAID_11GN; 3117 DPRINTFN(DBG_TX, 3118 ("%s: %s: data packet: tid=%d, raid=%d\n", 3119 device_xname(sc->sc_dev), __func__, tid, raid)); 3120 3121 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3122 txd->txdw1 |= htole32( 3123 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3124 SM(R92C_TXDW1_QSEL, tid) | 3125 SM(R92C_TXDW1_RAID, raid) | 3126 R92C_TXDW1_AGGBK); 3127 } else 3128 txd->txdw1 |= htole32( 3129 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3130 SM(R92C_TXDW1_QSEL, tid) | 3131 SM(R92C_TXDW1_RAID, raid) | 3132 R92C_TXDW1_AGGBK); 3133 3134 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3135 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3136 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3137 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3138 3139 if (hasqos) { 3140 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3141 } 3142 3143 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3144 /* for 11g */ 3145 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3146 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3147 R92C_TXDW4_HWRTSEN); 3148 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3149 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3150 R92C_TXDW4_HWRTSEN); 3151 } 3152 } 3153 /* Send RTS at OFDM24. */ 3154 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3155 txd->txdw5 |= htole32(0x0001ff00); 3156 /* Send data at OFDM54. */ 3157 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3158 txd->txdw5 |= htole32(0x13 & 0x3f); 3159 else 3160 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3161 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3162 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3163 device_xname(sc->sc_dev), __func__)); 3164 txd->txdw1 |= htole32( 3165 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3166 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3167 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3168 3169 /* Force CCK1. */ 3170 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3171 /* Use 1Mbps */ 3172 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3173 } else { 3174 /* broadcast or multicast packets */ 3175 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3176 device_xname(sc->sc_dev), __func__)); 3177 txd->txdw1 |= htole32( 3178 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3179 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3180 3181 /* Force CCK1. */ 3182 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3183 /* Use 1Mbps */ 3184 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3185 } 3186 /* Set sequence number */ 3187 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3188 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3189 txd->txdseq |= htole16(seq); 3190 3191 if (!hasqos) { 3192 /* Use HW sequence numbering for non-QoS frames. */ 3193 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3194 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3195 } 3196 } else { 3197 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3198 R92E_HWSEQ_SHIFT); 3199 if (!hasqos) { 3200 /* Use HW sequence numbering for non-QoS frames. */ 3201 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3202 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3203 } 3204 } 3205 3206 /* Compute Tx descriptor checksum. */ 3207 sum = 0; 3208 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3209 sum ^= ((uint16_t *)txd)[i]; 3210 txd->txdsum = sum; /* NB: already little endian. */ 3211 3212 xferlen = txd_len + m->m_pkthdr.len + padsize; 3213 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3214 3215 if (data->xfer == NULL) { 3216 /* NNN Don't crash ... but what is going on! */ 3217 printf ("urtwn_tx: data->xfer is NULL\n"); 3218 m_print(m,"", printf); 3219 return -1; 3220 } 3221 3222 s = splnet(); 3223 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3224 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3225 urtwn_txeof); 3226 error = usbd_transfer(data->xfer); 3227 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3228 error != USBD_IN_PROGRESS)) { 3229 splx(s); 3230 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3231 device_xname(sc->sc_dev), __func__, error)); 3232 return error; 3233 } 3234 splx(s); 3235 return 0; 3236 } 3237 3238 struct urtwn_tx_data * 3239 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3240 { 3241 struct urtwn_tx_data *data = NULL; 3242 3243 mutex_enter(&sc->sc_tx_mtx); 3244 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3245 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3246 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3247 } 3248 mutex_exit(&sc->sc_tx_mtx); 3249 3250 return data; 3251 } 3252 3253 static void 3254 urtwn_start(struct ifnet *ifp) 3255 { 3256 struct ieee80211vap *vap = ifp->if_softc; 3257 struct ieee80211com *ic = vap->iv_ic; 3258 struct urtwn_softc *sc = ic->ic_softc; 3259 struct urtwn_tx_data *data; 3260 struct ether_header *eh; 3261 struct ieee80211_node *ni; 3262 struct mbuf *m; 3263 3264 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3265 3266 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3267 return; 3268 3269 data = NULL; 3270 for (;;) { 3271 /* Send pending management frames first. */ 3272 IF_POLL(&ic->ic_mgtq, m); 3273 if (m != NULL) { 3274 /* Use AC_VO for management frames. */ 3275 3276 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3277 3278 if (data == NULL) { 3279 ifp->if_flags |= IFF_OACTIVE; 3280 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3281 device_xname(sc->sc_dev))); 3282 return; 3283 } 3284 IF_DEQUEUE(&ic->ic_mgtq, m); 3285 ni = M_GETCTX(m, struct ieee80211_node *); 3286 M_CLEARCTX(m); 3287 goto sendit; 3288 } 3289 3290 if (vap->iv_state != IEEE80211_S_RUN) 3291 break; 3292 3293 /* Encapsulate and send data frames. */ 3294 IFQ_POLL(&sc->sc_sendq, m); 3295 if (m == NULL) 3296 break; 3297 3298 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3299 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3300 uint8_t qid = WME_AC_BE; 3301 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3302 /* data frames in 11n mode */ 3303 struct ieee80211_qosframe *qwh = (void *)wh; 3304 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3305 qid = TID_TO_WME_AC(tid); 3306 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3307 qid = WME_AC_VO; 3308 } 3309 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3310 3311 if (data == NULL) { 3312 ifp->if_flags |= IFF_OACTIVE; 3313 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3314 device_xname(sc->sc_dev))); 3315 return; 3316 } 3317 IFQ_DEQUEUE(&sc->sc_sendq, m); 3318 3319 if (m->m_len < (int)sizeof(*eh) && 3320 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3321 printf("ERROR6\n"); 3322 if_statinc(ifp, if_oerrors); 3323 continue; 3324 } 3325 eh = mtod(m, struct ether_header *); 3326 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3327 if (ni == NULL) { 3328 m_freem(m); 3329 printf("ERROR5\n"); 3330 if_statinc(ifp, if_oerrors); 3331 continue; 3332 } 3333 3334 //bpf_mtap(ifp, m, BPF_D_OUT); 3335 3336 sendit: 3337 if (urtwn_tx(sc, m, ni, data) != 0) { 3338 m_freem(m); 3339 ieee80211_free_node(ni); 3340 printf("ERROR3\n"); 3341 if_statinc(ifp, if_oerrors); 3342 continue; 3343 } 3344 m_freem(m); 3345 ieee80211_free_node(ni); 3346 sc->tx_timer = 5; 3347 ifp->if_timer = 1; 3348 } 3349 } 3350 3351 static __unused void 3352 urtwn_watchdog(struct ifnet *ifp) 3353 { 3354 struct ieee80211vap *vap = ifp->if_softc; 3355 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3356 3357 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3358 3359 ifp->if_timer = 0; 3360 3361 if (sc->tx_timer > 0) { 3362 if (--sc->tx_timer == 0) { 3363 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3364 /* urtwn_init(ifp); XXX needs a process context! */ 3365 printf("ERROR2\n"); 3366 if_statinc(ifp, if_oerrors); 3367 return; 3368 } 3369 ifp->if_timer = 1; 3370 } 3371 // ieee80211_watchdog(&sc->sc_ic); 3372 } 3373 3374 /* 3375 * Create a VAP node for use with the urtwn driver. 3376 */ 3377 3378 static struct ieee80211vap * 3379 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3380 int unit, enum ieee80211_opmode opmode, int flags, 3381 const uint8_t bssid[IEEE80211_ADDR_LEN], 3382 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3383 { 3384 struct urtwn_softc *sc = ic->ic_softc; 3385 struct ifnet *ifp; 3386 struct ieee80211vap *vap; 3387 3388 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3389 3390 /* Allow only one VAP for the urtwn driver. */ 3391 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3392 return NULL; 3393 3394 /* Allocate the vap and setup. */ 3395 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3396 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3397 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3398 kmem_free(vap, sizeof(struct ieee80211vap)); 3399 return NULL; 3400 } 3401 3402 /* Local setup */ 3403 vap->iv_reset = urtwn_reset; 3404 3405 ifp = vap->iv_ifp; 3406 if_initialize(ifp); 3407 ifp->if_init = urtwn_init; 3408 ifp->if_ioctl = urtwn_ioctl; 3409 ifp->if_start = urtwn_start; 3410 // ifp->if_watchdog = urtwn_watchdog; NNN 3411 ifp->if_extflags |= IFEF_MPSAFE; 3412 // IFQ_SET_READY(&ifp->if_snd); 3413 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3414 3415 ifp->if_percpuq = if_percpuq_create(ifp); 3416 3417 /* Override state transition machine. */ 3418 /* NNN --- many possible newstate machines ... issue! */ 3419 sc->sc_newstate = vap->iv_newstate; 3420 vap->iv_newstate = urtwn_newstate; 3421 3422 /* Finish setup */ 3423 ieee80211_vap_attach(vap, urtwn_media_change, 3424 ieee80211_media_status, macaddr); 3425 ic->ic_opmode = opmode; 3426 3427 /* Attach the packet filter */ 3428 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3429 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3430 &sc->sc_drvbpf); 3431 3432 return vap; 3433 } 3434 3435 static void 3436 urtwn_vap_delete(struct ieee80211vap *vap) 3437 { 3438 struct ifnet *ifp = vap->iv_ifp; 3439 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3440 3441 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3442 3443 urtwn_stop(ifp, 0); 3444 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3445 bpf_detach(ifp); 3446 if_detach(ifp); 3447 kmem_free(vap, sizeof(struct ieee80211vap)); 3448 } 3449 3450 static void 3451 urtwn_parent(struct ieee80211com *ic) 3452 { 3453 struct urtwn_softc *sc __unused = ic->ic_softc; 3454 3455 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3456 3457 /* Not sure what to do here yet. */ 3458 } 3459 3460 static void 3461 urtwn_scan_start(struct ieee80211com *ic) 3462 { 3463 #ifdef URTWN_DEBUG 3464 struct urtwn_softc *sc = ic->ic_softc; 3465 #endif 3466 //uint32_t reg; 3467 //int s; 3468 3469 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3470 3471 /* 3472 * Not sure what to do here yet. Try #1: do what was in the 3473 * state machine. NNN 3474 */ 3475 #if NOTWITHSTATEMACHINEOVERRIDE 3476 /* 3477 * Begin of scanning 3478 */ 3479 3480 s = splnet(); 3481 mutex_enter(&sc->sc_write_mtx); 3482 3483 /* Set gain for scanning. */ 3484 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3485 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3486 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3487 3488 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3489 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3490 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3491 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3492 } 3493 3494 /* Set media status to 'No Link'. */ 3495 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3496 3497 /* Allow Rx from any BSSID. */ 3498 urtwn_write_4(sc, R92C_RCR, 3499 urtwn_read_4(sc, R92C_RCR) & 3500 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3501 3502 /* Stop Rx of data frames. */ 3503 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3504 3505 /* Disable update TSF */ 3506 urtwn_write_1(sc, R92C_BCN_CTRL, 3507 urtwn_read_1(sc, R92C_BCN_CTRL) | 3508 R92C_BCN_CTRL_DIS_TSF_UDT0); 3509 3510 /* Make link LED blink during scan. */ 3511 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3512 3513 /* Pause AC Tx queues. */ 3514 urtwn_write_1(sc, R92C_TXPAUSE, 3515 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3516 3517 urtwn_set_chan(sc, ic->ic_curchan, 3518 IEEE80211_HTINFO_2NDCHAN_NONE); 3519 3520 mutex_exit(&sc->sc_write_mtx); 3521 splx(s); 3522 #endif 3523 } 3524 3525 static void 3526 urtwn_scan_end(struct ieee80211com *ic) 3527 { 3528 #ifdef URTWN_DEBUG 3529 struct urtwn_softc *sc = ic->ic_softc; 3530 #endif 3531 3532 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3533 3534 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3535 /* 3536 * End of scanning 3537 */ 3538 3539 mutex_enter(&sc->sc_write_mtx); 3540 3541 /* flush 4-AC Queue after site_survey */ 3542 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3543 3544 /* Allow Rx from our BSSID only. */ 3545 urtwn_write_4(sc, R92C_RCR, 3546 urtwn_read_4(sc, R92C_RCR) | 3547 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3548 3549 /* Turn link LED off. */ 3550 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3551 3552 mutex_exit(&sc->sc_write_mtx); 3553 #endif 3554 } 3555 3556 static void 3557 urtwn_set_channel(struct ieee80211com *ic) 3558 { 3559 struct urtwn_softc *sc = ic->ic_softc; 3560 3561 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3562 3563 mutex_enter(&sc->sc_write_mtx); 3564 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3565 mutex_exit(&sc->sc_write_mtx); 3566 } 3567 3568 static int 3569 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3570 { 3571 struct urtwn_softc *sc = ic->ic_softc; 3572 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3573 int s; 3574 size_t pktlen = m->m_pkthdr.len; 3575 bool mcast = (m->m_flags & M_MCAST) != 0; 3576 3577 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3578 3579 s = splnet(); 3580 3581 IF_ENQUEUE(&sc->sc_sendq, m); 3582 3583 if_statadd(vap->iv_ifp, if_obytes, pktlen); 3584 if (mcast) 3585 if_statinc(vap->iv_ifp, if_omcasts); 3586 3587 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3588 if_start_lock(vap->iv_ifp); 3589 splx(s); 3590 3591 urtwn_start(vap->iv_ifp); 3592 3593 return 0; 3594 } 3595 3596 #if 0 3597 static int 3598 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3599 #ifdef URTWN_DEBUG 3600 // struct ieee80211vap *vap = ni->ni_vap; 3601 struct ieee80211com *ic = ni->ni_ic; 3602 struct urtwn_softc *sc = ic->ic_softc; 3603 #endif 3604 3605 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3606 3607 /* Don't know what to do right now. */ 3608 return ENOTTY; 3609 } 3610 #endif 3611 3612 3613 static int 3614 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3615 const struct ieee80211_bpf_params *bpfp) 3616 { 3617 struct ieee80211vap *vap = ni->ni_vap; 3618 struct ieee80211com *ic = ni->ni_ic; 3619 struct urtwn_softc *sc = ic->ic_softc; 3620 struct urtwn_tx_data *data; 3621 int error; 3622 3623 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3624 3625 KASSERT(vap != NULL); /* NNN need these? */ 3626 KASSERT(ic != NULL); 3627 KASSERT(sc != NULL); 3628 KASSERT(m != NULL); 3629 3630 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3631 3632 if (data == NULL) { 3633 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3634 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3635 device_xname(sc->sc_dev))); 3636 return ENOBUFS; 3637 } 3638 3639 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3640 3641 error = urtwn_tx(sc, m, ni, data); 3642 if (error != 0) { 3643 printf("ERROR3\n"); 3644 if_statinc(vap->iv_ifp, if_oerrors); 3645 } else { 3646 sc->tx_timer = 5; 3647 vap->iv_ifp->if_timer = 1; 3648 } 3649 m_freem(m); 3650 ieee80211_free_node(ni); 3651 return error; 3652 } 3653 3654 static void 3655 urtwn_getradiocaps(struct ieee80211com *ic, 3656 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3657 { 3658 uint8_t bands[IEEE80211_MODE_BYTES]; 3659 3660 /* 3661 * NNN Should be able to do something based on chip if 3662 * a chip has more bands .... eg. N ... but for the future. 3663 */ 3664 3665 memset(bands, 0, sizeof(bands)); 3666 setbit(bands, IEEE80211_MODE_11B); 3667 setbit(bands, IEEE80211_MODE_11G); 3668 setbit(bands, IEEE80211_MODE_11NG); 3669 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3670 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 3671 } 3672 3673 3674 static int 3675 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3676 { 3677 3678 struct ieee80211vap *vap = ifp->if_softc; 3679 struct ieee80211com *ic = vap->iv_ic; 3680 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3681 int s, error = 0; 3682 3683 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3684 device_xname(sc->sc_dev), __func__, cmd, data)); 3685 3686 s = splnet(); 3687 3688 switch (cmd) { 3689 case SIOCSIFFLAGS: 3690 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3691 break; 3692 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3693 case IFF_UP | IFF_RUNNING: 3694 break; 3695 case IFF_UP: 3696 urtwn_init(ifp); 3697 break; 3698 case IFF_RUNNING: 3699 urtwn_stop(ifp, 1); 3700 break; 3701 case 0: 3702 break; 3703 } 3704 break; 3705 3706 case SIOCADDMULTI: 3707 case SIOCDELMULTI: 3708 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3709 /* setup multicast filter, etc */ 3710 error = 0; 3711 } 3712 break; 3713 3714 case SIOCS80211CHANNEL: 3715 /* 3716 * This allows for fast channel switching in monitor mode 3717 * (used by kismet). In IBSS mode, we must explicitly reset 3718 * the interface to generate a new beacon frame. 3719 */ 3720 error = ieee80211_ioctl(ifp, cmd, data); 3721 if (error == ENETRESET && 3722 ic->ic_opmode == IEEE80211_M_MONITOR) { 3723 urtwn_set_chan(sc, ic->ic_curchan, 3724 IEEE80211_HTINFO_2NDCHAN_NONE); 3725 error = 0; 3726 } 3727 break; 3728 3729 default: 3730 error = ieee80211_ioctl(ifp, cmd, data); 3731 break; 3732 } 3733 if (error == ENETRESET) { 3734 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3735 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3736 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3737 urtwn_init(ifp); 3738 } 3739 error = 0; 3740 } 3741 3742 splx(s); 3743 3744 return error; 3745 } 3746 3747 static __inline int 3748 urtwn_power_on(struct urtwn_softc *sc) 3749 { 3750 3751 return sc->sc_power_on(sc); 3752 } 3753 3754 static int 3755 urtwn_r92c_power_on(struct urtwn_softc *sc) 3756 { 3757 uint32_t reg; 3758 int ntries; 3759 3760 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3761 3762 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3763 3764 /* Wait for autoload done bit. */ 3765 for (ntries = 0; ntries < 1000; ntries++) { 3766 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3767 break; 3768 DELAY(5); 3769 } 3770 if (ntries == 1000) { 3771 aprint_error_dev(sc->sc_dev, 3772 "timeout waiting for chip autoload\n"); 3773 return ETIMEDOUT; 3774 } 3775 3776 /* Unlock ISO/CLK/Power control register. */ 3777 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3778 /* Move SPS into PWM mode. */ 3779 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3780 DELAY(5); 3781 3782 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3783 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3784 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3785 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3786 DELAY(100); 3787 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3788 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3789 ~R92C_SYS_ISO_CTRL_MD2PP); 3790 } 3791 3792 /* Auto enable WLAN. */ 3793 urtwn_write_2(sc, R92C_APS_FSMCO, 3794 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3795 for (ntries = 0; ntries < 1000; ntries++) { 3796 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3797 R92C_APS_FSMCO_APFM_ONMAC)) 3798 break; 3799 DELAY(100); 3800 } 3801 if (ntries == 1000) { 3802 aprint_error_dev(sc->sc_dev, 3803 "timeout waiting for MAC auto ON\n"); 3804 return ETIMEDOUT; 3805 } 3806 3807 /* Enable radio, GPIO and LED functions. */ 3808 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3809 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3810 urtwn_write_2(sc, R92C_APS_FSMCO, 3811 R92C_APS_FSMCO_AFSM_HSUS | 3812 R92C_APS_FSMCO_PDN_EN | 3813 R92C_APS_FSMCO_PFM_ALDN); 3814 3815 /* Release RF digital isolation. */ 3816 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3817 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3818 3819 /* Initialize MAC. */ 3820 urtwn_write_1(sc, R92C_APSD_CTRL, 3821 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3822 for (ntries = 0; ntries < 200; ntries++) { 3823 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3824 R92C_APSD_CTRL_OFF_STATUS)) 3825 break; 3826 DELAY(5); 3827 } 3828 if (ntries == 200) { 3829 aprint_error_dev(sc->sc_dev, 3830 "timeout waiting for MAC initialization\n"); 3831 return ETIMEDOUT; 3832 } 3833 3834 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3835 reg = urtwn_read_2(sc, R92C_CR); 3836 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3837 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3838 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3839 R92C_CR_ENSEC; 3840 urtwn_write_2(sc, R92C_CR, reg); 3841 3842 urtwn_write_1(sc, 0xfe10, 0x19); 3843 return 0; 3844 } 3845 3846 static int 3847 urtwn_r92e_power_on(struct urtwn_softc *sc) 3848 { 3849 uint32_t reg; 3850 uint32_t val; 3851 int ntries; 3852 3853 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3854 3855 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3856 3857 /* Enable radio, GPIO and LED functions. */ 3858 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3859 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3860 urtwn_write_2(sc, R92C_APS_FSMCO, 3861 R92C_APS_FSMCO_AFSM_HSUS | 3862 R92C_APS_FSMCO_PDN_EN | 3863 R92C_APS_FSMCO_PFM_ALDN); 3864 3865 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3866 /* LDO. */ 3867 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3868 } 3869 else { 3870 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3871 R92C_SYS_SWR_CTRL2) & 0xffff); 3872 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3873 } 3874 3875 for (ntries = 0; ntries < 2; ntries++) { 3876 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3877 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3878 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3879 R92C_AFE_CTRL4)); 3880 } 3881 3882 /* Reset BB. */ 3883 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3884 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3885 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3886 3887 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3888 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3889 3890 /* Disable HWPDN. */ 3891 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3892 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3893 3894 /* Disable WL suspend. */ 3895 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3896 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3897 R92C_APS_FSMCO_AFSM_HSUS)); 3898 3899 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3900 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3901 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3902 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3903 for (ntries = 0; ntries < 10000; ntries++) { 3904 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3905 R92C_APS_FSMCO_APFM_ONMAC; 3906 if (val == 0x0) 3907 break; 3908 DELAY(10); 3909 } 3910 if (ntries == 10000) { 3911 aprint_error_dev(sc->sc_dev, 3912 "timeout waiting for chip power up\n"); 3913 return ETIMEDOUT; 3914 } 3915 3916 urtwn_write_2(sc, R92C_CR, 0x00); 3917 reg = urtwn_read_2(sc, R92C_CR); 3918 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3919 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3920 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3921 urtwn_write_2(sc, R92C_CR, reg); 3922 3923 return 0; 3924 } 3925 3926 static int 3927 urtwn_r88e_power_on(struct urtwn_softc *sc) 3928 { 3929 uint32_t reg; 3930 uint8_t val; 3931 int ntries; 3932 3933 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3934 3935 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3936 3937 /* Wait for power ready bit. */ 3938 for (ntries = 0; ntries < 5000; ntries++) { 3939 val = urtwn_read_1(sc, 0x6) & 0x2; 3940 if (val == 0x2) 3941 break; 3942 DELAY(10); 3943 } 3944 if (ntries == 5000) { 3945 aprint_error_dev(sc->sc_dev, 3946 "timeout waiting for chip power up\n"); 3947 return ETIMEDOUT; 3948 } 3949 3950 /* Reset BB. */ 3951 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3952 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3953 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3954 3955 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3956 3957 /* Disable HWPDN. */ 3958 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3959 3960 /* Disable WL suspend. */ 3961 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3962 3963 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3964 for (ntries = 0; ntries < 5000; ntries++) { 3965 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3966 break; 3967 DELAY(10); 3968 } 3969 if (ntries == 5000) 3970 return ETIMEDOUT; 3971 3972 /* Enable LDO normal mode. */ 3973 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3974 3975 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3976 urtwn_write_2(sc, R92C_CR, 0); 3977 reg = urtwn_read_2(sc, R92C_CR); 3978 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3979 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3980 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3981 urtwn_write_2(sc, R92C_CR, reg); 3982 3983 return 0; 3984 } 3985 3986 static int 3987 urtwn_llt_init(struct urtwn_softc *sc) 3988 { 3989 size_t i, page_count, pktbuf_count; 3990 uint32_t val; 3991 int error; 3992 3993 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3994 3995 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3996 3997 if (sc->chip & URTWN_CHIP_88E) 3998 page_count = R88E_TX_PAGE_COUNT; 3999 else if (sc->chip & URTWN_CHIP_92EU) 4000 page_count = R92E_TX_PAGE_COUNT; 4001 else 4002 page_count = R92C_TX_PAGE_COUNT; 4003 if (sc->chip & URTWN_CHIP_88E) 4004 pktbuf_count = R88E_TXPKTBUF_COUNT; 4005 else if (sc->chip & URTWN_CHIP_92EU) 4006 pktbuf_count = R88E_TXPKTBUF_COUNT; 4007 else 4008 pktbuf_count = R92C_TXPKTBUF_COUNT; 4009 4010 if (sc->chip & URTWN_CHIP_92EU) { 4011 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 4012 urtwn_write_4(sc, R92E_AUTO_LLT, val); 4013 DELAY(100); 4014 val = urtwn_read_4(sc, R92E_AUTO_LLT); 4015 if (val & R92E_AUTO_LLT_EN) 4016 return EIO; 4017 return 0; 4018 } 4019 4020 /* Reserve pages [0; page_count]. */ 4021 for (i = 0; i < page_count; i++) { 4022 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4023 return error; 4024 } 4025 /* NB: 0xff indicates end-of-list. */ 4026 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4027 return error; 4028 /* 4029 * Use pages [page_count + 1; pktbuf_count - 1] 4030 * as ring buffer. 4031 */ 4032 for (++i; i < pktbuf_count - 1; i++) { 4033 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4034 return error; 4035 } 4036 /* Make the last page point to the beginning of the ring buffer. */ 4037 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4038 return error; 4039 } 4040 4041 static __unused void 4042 urtwn_fw_reset(struct urtwn_softc *sc) 4043 { 4044 uint16_t reg; 4045 int ntries; 4046 4047 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4048 4049 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4050 4051 /* Tell 8051 to reset itself. */ 4052 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4053 4054 /* Wait until 8051 resets by itself. */ 4055 for (ntries = 0; ntries < 100; ntries++) { 4056 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4057 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4058 return; 4059 DELAY(50); 4060 } 4061 /* Force 8051 reset. */ 4062 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4063 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4064 } 4065 4066 static void 4067 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4068 { 4069 uint16_t reg; 4070 4071 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4072 4073 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4074 4075 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4076 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4077 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4078 } 4079 DELAY(50); 4080 4081 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4082 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4083 DELAY(50); 4084 4085 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4086 DELAY(50); 4087 4088 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4089 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4090 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4091 } 4092 DELAY(50); 4093 4094 } 4095 4096 static int 4097 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4098 { 4099 uint32_t reg; 4100 int off, mlen, error = 0; 4101 4102 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4103 device_xname(sc->sc_dev), __func__, page, buf, len)); 4104 4105 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4106 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4107 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4108 4109 off = R92C_FW_START_ADDR; 4110 while (len > 0) { 4111 if (len > 196) 4112 mlen = 196; 4113 else if (len > 4) 4114 mlen = 4; 4115 else 4116 mlen = 1; 4117 error = urtwn_write_region(sc, off, buf, mlen); 4118 if (error != 0) 4119 break; 4120 off += mlen; 4121 buf += mlen; 4122 len -= mlen; 4123 } 4124 return error; 4125 } 4126 4127 static int 4128 urtwn_load_firmware(struct urtwn_softc *sc) 4129 { 4130 firmware_handle_t fwh; 4131 const struct r92c_fw_hdr *hdr; 4132 const char *name; 4133 u_char *fw, *ptr; 4134 size_t len; 4135 uint32_t reg; 4136 int mlen, ntries, page, error; 4137 4138 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4139 4140 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4141 4142 /* Read firmware image from the filesystem. */ 4143 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4144 name = "rtl8188eufw.bin"; 4145 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4146 name = "rtl8192eefw.bin"; 4147 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4148 URTWN_CHIP_UMC_A_CUT) 4149 name = "rtl8192cfwU.bin"; 4150 else 4151 name = "rtl8192cfw.bin"; 4152 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4153 aprint_error_dev(sc->sc_dev, 4154 "failed load firmware of file %s (error %d)\n", name, 4155 error); 4156 return error; 4157 } 4158 const size_t fwlen = len = firmware_get_size(fwh); 4159 fw = firmware_malloc(len); 4160 if (fw == NULL) { 4161 aprint_error_dev(sc->sc_dev, 4162 "failed to allocate firmware memory\n"); 4163 firmware_close(fwh); 4164 return ENOMEM; 4165 } 4166 error = firmware_read(fwh, 0, fw, len); 4167 firmware_close(fwh); 4168 if (error != 0) { 4169 aprint_error_dev(sc->sc_dev, 4170 "failed to read firmware (error %d)\n", error); 4171 firmware_free(fw, fwlen); 4172 return error; 4173 } 4174 4175 len = fwlen; 4176 ptr = fw; 4177 hdr = (const struct r92c_fw_hdr *)ptr; 4178 /* Check if there is a valid FW header and skip it. */ 4179 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4180 (le16toh(hdr->signature) >> 4) == 0x88e || 4181 (le16toh(hdr->signature) >> 4) == 0x92e || 4182 (le16toh(hdr->signature) >> 4) == 0x92c) { 4183 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4184 device_xname(sc->sc_dev), __func__, 4185 le16toh(hdr->version), le16toh(hdr->subversion), 4186 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4187 ptr += sizeof(*hdr); 4188 len -= sizeof(*hdr); 4189 } 4190 4191 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4192 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4193 ISSET(sc->chip, URTWN_CHIP_92EU)) 4194 urtwn_r88e_fw_reset(sc); 4195 else 4196 urtwn_fw_reset(sc); 4197 } 4198 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4199 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4200 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4201 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4202 R92C_SYS_FUNC_EN_CPUEN); 4203 } 4204 4205 /* download enabled */ 4206 urtwn_write_1(sc, R92C_MCUFWDL, 4207 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4208 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4209 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4210 4211 /* Reset the FWDL checksum. */ 4212 urtwn_write_1(sc, R92C_MCUFWDL, 4213 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4214 4215 DELAY(50); 4216 /* download firmware */ 4217 for (page = 0; len > 0; page++) { 4218 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4219 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4220 if (error != 0) { 4221 aprint_error_dev(sc->sc_dev, 4222 "could not load firmware page %d\n", page); 4223 goto fail; 4224 } 4225 ptr += mlen; 4226 len -= mlen; 4227 } 4228 4229 /* download disable */ 4230 urtwn_write_1(sc, R92C_MCUFWDL, 4231 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4232 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4233 4234 /* Wait for checksum report. */ 4235 for (ntries = 0; ntries < 1000; ntries++) { 4236 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4237 break; 4238 DELAY(5); 4239 } 4240 if (ntries == 1000) { 4241 aprint_error_dev(sc->sc_dev, 4242 "timeout waiting for checksum report\n"); 4243 error = ETIMEDOUT; 4244 goto fail; 4245 } 4246 4247 /* Wait for firmware readiness. */ 4248 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4249 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4250 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4251 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4252 ISSET(sc->chip, URTWN_CHIP_92EU)) 4253 urtwn_r88e_fw_reset(sc); 4254 for (ntries = 0; ntries < 6000; ntries++) { 4255 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4256 break; 4257 DELAY(5); 4258 } 4259 if (ntries == 6000) { 4260 aprint_error_dev(sc->sc_dev, 4261 "timeout waiting for firmware readiness\n"); 4262 error = ETIMEDOUT; 4263 goto fail; 4264 } 4265 fail: 4266 firmware_free(fw, fwlen); 4267 return error; 4268 } 4269 4270 static __inline int 4271 urtwn_dma_init(struct urtwn_softc *sc) 4272 { 4273 4274 return sc->sc_dma_init(sc); 4275 } 4276 4277 static int 4278 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4279 { 4280 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4281 uint32_t reg; 4282 int error; 4283 4284 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4285 4286 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4287 4288 /* Initialize LLT table. */ 4289 error = urtwn_llt_init(sc); 4290 if (error != 0) 4291 return error; 4292 4293 /* Get Tx queues to USB endpoints mapping. */ 4294 hashq = hasnq = haslq = 0; 4295 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4296 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping %#x\n", 4297 device_xname(sc->sc_dev), __func__, reg)); 4298 if (MS(reg, R92C_USB_EP_HQ) != 0) 4299 hashq = 1; 4300 if (MS(reg, R92C_USB_EP_NQ) != 0) 4301 hasnq = 1; 4302 if (MS(reg, R92C_USB_EP_LQ) != 0) 4303 haslq = 1; 4304 nqueues = hashq + hasnq + haslq; 4305 if (nqueues == 0) 4306 return EIO; 4307 /* Get the number of pages for each queue. */ 4308 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4309 /* The remaining pages are assigned to the high priority queue. */ 4310 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4311 4312 /* Set number of pages for normal priority queue. */ 4313 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4314 urtwn_write_4(sc, R92C_RQPN, 4315 /* Set number of pages for public queue. */ 4316 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4317 /* Set number of pages for high priority queue. */ 4318 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4319 /* Set number of pages for low priority queue. */ 4320 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4321 /* Load values. */ 4322 R92C_RQPN_LD); 4323 4324 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4325 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4326 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4327 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4328 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4329 4330 /* Set queue to USB pipe mapping. */ 4331 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4332 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4333 if (nqueues == 1) { 4334 if (hashq) { 4335 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4336 } else if (hasnq) { 4337 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4338 } else { 4339 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4340 } 4341 } else if (nqueues == 2) { 4342 /* All 2-endpoints configs have a high priority queue. */ 4343 if (!hashq) { 4344 return EIO; 4345 } 4346 if (hasnq) { 4347 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4348 } else { 4349 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4350 } 4351 } else { 4352 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4353 } 4354 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4355 4356 /* Set Tx/Rx transfer page boundary. */ 4357 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4358 4359 /* Set Tx/Rx transfer page size. */ 4360 urtwn_write_1(sc, R92C_PBP, 4361 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4362 return 0; 4363 } 4364 4365 static int 4366 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4367 { 4368 usb_interface_descriptor_t *id; 4369 uint32_t reg; 4370 int nqueues; 4371 int error; 4372 4373 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4374 4375 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4376 4377 /* Initialize LLT table. */ 4378 error = urtwn_llt_init(sc); 4379 if (error != 0) 4380 return error; 4381 4382 /* Get Tx queues to USB endpoints mapping. */ 4383 id = usbd_get_interface_descriptor(sc->sc_iface); 4384 nqueues = id->bNumEndpoints - 1; 4385 if (nqueues == 0) 4386 return EIO; 4387 4388 /* Set number of pages for normal priority queue. */ 4389 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4390 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4391 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4392 4393 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4394 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4395 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4396 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4397 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4398 4399 /* Set queue to USB pipe mapping. */ 4400 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4401 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4402 if (nqueues == 1) 4403 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4404 else if (nqueues == 2) 4405 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4406 else 4407 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4408 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4409 4410 /* Set Tx/Rx transfer page boundary. */ 4411 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4412 4413 /* Set Tx/Rx transfer page size. */ 4414 urtwn_write_1(sc, R92C_PBP, 4415 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4416 4417 return 0; 4418 } 4419 4420 static void 4421 urtwn_mac_init(struct urtwn_softc *sc) 4422 { 4423 size_t i; 4424 4425 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4426 4427 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4428 4429 /* Write MAC initialization values. */ 4430 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4431 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4432 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4433 rtl8188eu_mac[i].val); 4434 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4435 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4436 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4437 rtl8192eu_mac[i].val); 4438 } else { 4439 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4440 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4441 rtl8192cu_mac[i].val); 4442 } 4443 } 4444 4445 static void 4446 urtwn_bb_init(struct urtwn_softc *sc) 4447 { 4448 const struct rtwn_bb_prog *prog; 4449 uint32_t reg; 4450 uint8_t crystalcap; 4451 size_t i; 4452 4453 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4454 4455 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4456 4457 /* Enable BB and RF. */ 4458 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4459 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4460 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4461 R92C_SYS_FUNC_EN_DIO_RF); 4462 4463 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4464 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4465 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4466 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4467 } 4468 4469 urtwn_write_1(sc, R92C_RF_CTRL, 4470 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4471 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4472 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4473 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4474 4475 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4476 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4477 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4478 urtwn_write_1(sc, 0x15, 0xe9); 4479 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4480 } 4481 4482 /* Select BB programming based on board type. */ 4483 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4484 prog = &rtl8188eu_bb_prog; 4485 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4486 prog = &rtl8192eu_bb_prog; 4487 else if (!(sc->chip & URTWN_CHIP_92C)) { 4488 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4489 prog = &rtl8188ce_bb_prog; 4490 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4491 prog = &rtl8188ru_bb_prog; 4492 } else { 4493 prog = &rtl8188cu_bb_prog; 4494 } 4495 } else { 4496 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4497 prog = &rtl8192ce_bb_prog; 4498 } else { 4499 prog = &rtl8192cu_bb_prog; 4500 } 4501 } 4502 /* Write BB initialization values. */ 4503 for (i = 0; i < prog->count; i++) { 4504 /* additional delay depend on registers */ 4505 switch (prog->regs[i]) { 4506 case 0xfe: 4507 urtwn_delay_ms(sc, 50); 4508 break; 4509 case 0xfd: 4510 urtwn_delay_ms(sc, 5); 4511 break; 4512 case 0xfc: 4513 urtwn_delay_ms(sc, 1); 4514 break; 4515 case 0xfb: 4516 DELAY(50); 4517 break; 4518 case 0xfa: 4519 DELAY(5); 4520 break; 4521 case 0xf9: 4522 DELAY(1); 4523 break; 4524 } 4525 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4526 DELAY(1); 4527 } 4528 4529 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4530 /* 8192C 1T only configuration. */ 4531 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4532 reg = (reg & ~0x00000003) | 0x2; 4533 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4534 4535 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4536 reg = (reg & ~0x00300033) | 0x00200022; 4537 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4538 4539 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4540 reg = (reg & ~0xff000000) | (0x45 << 24); 4541 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4542 4543 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4544 reg = (reg & ~0x000000ff) | 0x23; 4545 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4546 4547 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4548 reg = (reg & ~0x00000030) | (1 << 4); 4549 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4550 4551 reg = urtwn_bb_read(sc, 0xe74); 4552 reg = (reg & ~0x0c000000) | (2 << 26); 4553 urtwn_bb_write(sc, 0xe74, reg); 4554 reg = urtwn_bb_read(sc, 0xe78); 4555 reg = (reg & ~0x0c000000) | (2 << 26); 4556 urtwn_bb_write(sc, 0xe78, reg); 4557 reg = urtwn_bb_read(sc, 0xe7c); 4558 reg = (reg & ~0x0c000000) | (2 << 26); 4559 urtwn_bb_write(sc, 0xe7c, reg); 4560 reg = urtwn_bb_read(sc, 0xe80); 4561 reg = (reg & ~0x0c000000) | (2 << 26); 4562 urtwn_bb_write(sc, 0xe80, reg); 4563 reg = urtwn_bb_read(sc, 0xe88); 4564 reg = (reg & ~0x0c000000) | (2 << 26); 4565 urtwn_bb_write(sc, 0xe88, reg); 4566 } 4567 4568 /* Write AGC values. */ 4569 for (i = 0; i < prog->agccount; i++) { 4570 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4571 DELAY(1); 4572 } 4573 4574 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4575 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4576 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4577 DELAY(1); 4578 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4579 DELAY(1); 4580 } 4581 4582 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4583 crystalcap = sc->r88e_rom[0xb9]; 4584 if (crystalcap == 0x00) 4585 crystalcap = 0x20; 4586 crystalcap &= 0x3f; 4587 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4588 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4589 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4590 crystalcap | crystalcap << 6)); 4591 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4592 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4593 crystalcap = sc->r88e_rom[0xb9]; 4594 if (crystalcap == 0xff) 4595 crystalcap = 0x20; 4596 crystalcap &= 0x3f; 4597 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4598 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4599 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4600 crystalcap | crystalcap << 6)); 4601 } else { 4602 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4603 R92C_HSSI_PARAM2_CCK_HIPWR) { 4604 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4605 } 4606 } 4607 } 4608 4609 static void 4610 urtwn_rf_init(struct urtwn_softc *sc) 4611 { 4612 const struct rtwn_rf_prog *prog; 4613 uint32_t reg, mask, saved; 4614 size_t i, j, idx; 4615 4616 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4617 4618 /* Select RF programming based on board type. */ 4619 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4620 prog = rtl8188eu_rf_prog; 4621 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4622 prog = rtl8192eu_rf_prog; 4623 else if (!(sc->chip & URTWN_CHIP_92C)) { 4624 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4625 prog = rtl8188ce_rf_prog; 4626 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4627 prog = rtl8188ru_rf_prog; 4628 } else { 4629 prog = rtl8188cu_rf_prog; 4630 } 4631 } else { 4632 prog = rtl8192ce_rf_prog; 4633 } 4634 4635 for (i = 0; i < sc->nrxchains; i++) { 4636 /* Save RF_ENV control type. */ 4637 idx = i / 2; 4638 mask = 0xffffU << ((i % 2) * 16); 4639 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4640 4641 /* Set RF_ENV enable. */ 4642 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4643 reg |= 0x100000; 4644 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4645 DELAY(50); 4646 4647 /* Set RF_ENV output high. */ 4648 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4649 reg |= 0x10; 4650 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4651 DELAY(50); 4652 4653 /* Set address and data lengths of RF registers. */ 4654 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4655 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4656 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4657 DELAY(50); 4658 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4659 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4660 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4661 DELAY(50); 4662 4663 /* Write RF initialization values for this chain. */ 4664 for (j = 0; j < prog[i].count; j++) { 4665 if (prog[i].regs[j] >= 0xf9 && 4666 prog[i].regs[j] <= 0xfe) { 4667 /* 4668 * These are fake RF registers offsets that 4669 * indicate a delay is required. 4670 */ 4671 urtwn_delay_ms(sc, 50); 4672 continue; 4673 } 4674 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4675 DELAY(5); 4676 } 4677 4678 /* Restore RF_ENV control type. */ 4679 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4680 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4681 } 4682 4683 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4684 URTWN_CHIP_UMC_A_CUT) { 4685 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4686 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4687 } 4688 4689 /* Cache RF register CHNLBW. */ 4690 for (i = 0; i < 2; i++) { 4691 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4692 } 4693 } 4694 4695 static void 4696 urtwn_cam_init(struct urtwn_softc *sc) 4697 { 4698 uint32_t content, command; 4699 uint8_t idx; 4700 size_t i; 4701 4702 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4703 4704 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4705 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4706 return; 4707 4708 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4709 content = (idx & 3) 4710 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4711 | R92C_CAM_VALID; 4712 4713 command = R92C_CAMCMD_POLLING 4714 | R92C_CAMCMD_WRITE 4715 | R92C_CAM_CTL0(idx); 4716 4717 urtwn_write_4(sc, R92C_CAMWRITE, content); 4718 urtwn_write_4(sc, R92C_CAMCMD, command); 4719 } 4720 4721 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4722 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4723 if (i == 0) { 4724 content = (idx & 3) 4725 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4726 | R92C_CAM_VALID; 4727 } else { 4728 content = 0; 4729 } 4730 4731 command = R92C_CAMCMD_POLLING 4732 | R92C_CAMCMD_WRITE 4733 | R92C_CAM_CTL0(idx) 4734 | i; 4735 4736 urtwn_write_4(sc, R92C_CAMWRITE, content); 4737 urtwn_write_4(sc, R92C_CAMCMD, command); 4738 } 4739 } 4740 4741 /* Invalidate all CAM entries. */ 4742 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4743 } 4744 4745 static void 4746 urtwn_pa_bias_init(struct urtwn_softc *sc) 4747 { 4748 uint8_t reg; 4749 size_t i; 4750 4751 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4752 4753 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4754 4755 for (i = 0; i < sc->nrxchains; i++) { 4756 if (sc->pa_setting & (1U << i)) 4757 continue; 4758 4759 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4760 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4761 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4762 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4763 } 4764 if (!(sc->pa_setting & 0x10)) { 4765 reg = urtwn_read_1(sc, 0x16); 4766 reg = (reg & ~0xf0) | 0x90; 4767 urtwn_write_1(sc, 0x16, reg); 4768 } 4769 } 4770 4771 static void 4772 urtwn_rxfilter_init(struct urtwn_softc *sc) 4773 { 4774 4775 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4776 4777 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4778 4779 /* Initialize Rx filter. */ 4780 /* TODO: use better filter for monitor mode. */ 4781 urtwn_write_4(sc, R92C_RCR, 4782 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4783 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4784 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4785 /* Accept all multicast frames. */ 4786 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4787 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4788 /* Accept all management frames. */ 4789 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4790 /* Reject all control frames. */ 4791 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4792 /* Accept all data frames. */ 4793 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4794 } 4795 4796 static void 4797 urtwn_edca_init(struct urtwn_softc *sc) 4798 { 4799 4800 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4801 4802 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4803 4804 /* set spec SIFS (used in NAV) */ 4805 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4806 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4807 4808 /* set SIFS CCK/OFDM */ 4809 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4810 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4811 4812 /* TXOP */ 4813 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4814 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4815 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4816 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4817 } 4818 4819 static void 4820 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4821 uint16_t power[URTWN_RIDX_COUNT]) 4822 { 4823 uint32_t reg; 4824 4825 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4826 __func__, chain)); 4827 4828 /* Write per-CCK rate Tx power. */ 4829 if (chain == 0) { 4830 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4831 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4832 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4833 4834 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4835 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4836 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4837 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4838 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4839 } else { 4840 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4841 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4842 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4843 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4844 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4845 4846 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4847 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4848 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4849 } 4850 /* Write per-OFDM rate Tx power. */ 4851 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4852 SM(R92C_TXAGC_RATE06, power[ 4]) | 4853 SM(R92C_TXAGC_RATE09, power[ 5]) | 4854 SM(R92C_TXAGC_RATE12, power[ 6]) | 4855 SM(R92C_TXAGC_RATE18, power[ 7])); 4856 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4857 SM(R92C_TXAGC_RATE24, power[ 8]) | 4858 SM(R92C_TXAGC_RATE36, power[ 9]) | 4859 SM(R92C_TXAGC_RATE48, power[10]) | 4860 SM(R92C_TXAGC_RATE54, power[11])); 4861 /* Write per-MCS Tx power. */ 4862 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4863 SM(R92C_TXAGC_MCS00, power[12]) | 4864 SM(R92C_TXAGC_MCS01, power[13]) | 4865 SM(R92C_TXAGC_MCS02, power[14]) | 4866 SM(R92C_TXAGC_MCS03, power[15])); 4867 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4868 SM(R92C_TXAGC_MCS04, power[16]) | 4869 SM(R92C_TXAGC_MCS05, power[17]) | 4870 SM(R92C_TXAGC_MCS06, power[18]) | 4871 SM(R92C_TXAGC_MCS07, power[19])); 4872 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4873 SM(R92C_TXAGC_MCS08, power[20]) | 4874 SM(R92C_TXAGC_MCS09, power[21]) | 4875 SM(R92C_TXAGC_MCS10, power[22]) | 4876 SM(R92C_TXAGC_MCS11, power[23])); 4877 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4878 SM(R92C_TXAGC_MCS12, power[24]) | 4879 SM(R92C_TXAGC_MCS13, power[25]) | 4880 SM(R92C_TXAGC_MCS14, power[26]) | 4881 SM(R92C_TXAGC_MCS15, power[27])); 4882 } 4883 4884 static void 4885 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4886 uint16_t power[URTWN_RIDX_COUNT]) 4887 { 4888 struct r92c_rom *rom = &sc->rom; 4889 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4890 const struct rtwn_txpwr *base; 4891 int ridx, group; 4892 4893 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4894 device_xname(sc->sc_dev), __func__, chain, chan)); 4895 4896 /* Determine channel group. */ 4897 if (chan <= 3) { 4898 group = 0; 4899 } else if (chan <= 9) { 4900 group = 1; 4901 } else { 4902 group = 2; 4903 } 4904 4905 /* Get original Tx power based on board type and RF chain. */ 4906 if (!(sc->chip & URTWN_CHIP_92C)) { 4907 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4908 base = &rtl8188ru_txagc[chain]; 4909 } else { 4910 base = &rtl8192cu_txagc[chain]; 4911 } 4912 } else { 4913 base = &rtl8192cu_txagc[chain]; 4914 } 4915 4916 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4917 if (sc->regulatory == 0) { 4918 for (ridx = 0; ridx <= 3; ridx++) { 4919 power[ridx] = base->pwr[0][ridx]; 4920 } 4921 } 4922 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4923 if (sc->regulatory == 3) { 4924 power[ridx] = base->pwr[0][ridx]; 4925 /* Apply vendor limits. */ 4926 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4927 maxpow = rom->ht40_max_pwr[group]; 4928 } else { 4929 maxpow = rom->ht20_max_pwr[group]; 4930 } 4931 maxpow = (maxpow >> (chain * 4)) & 0xf; 4932 if (power[ridx] > maxpow) { 4933 power[ridx] = maxpow; 4934 } 4935 } else if (sc->regulatory == 1) { 4936 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4937 power[ridx] = base->pwr[group][ridx]; 4938 } 4939 } else if (sc->regulatory != 2) { 4940 power[ridx] = base->pwr[0][ridx]; 4941 } 4942 } 4943 4944 /* Compute per-CCK rate Tx power. */ 4945 cckpow = rom->cck_tx_pwr[chain][group]; 4946 for (ridx = 0; ridx <= 3; ridx++) { 4947 power[ridx] += cckpow; 4948 if (power[ridx] > R92C_MAX_TX_PWR) { 4949 power[ridx] = R92C_MAX_TX_PWR; 4950 } 4951 } 4952 4953 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4954 if (sc->ntxchains > 1) { 4955 /* Apply reduction for 2 spatial streams. */ 4956 diff = rom->ht40_2s_tx_pwr_diff[group]; 4957 diff = (diff >> (chain * 4)) & 0xf; 4958 htpow = (htpow > diff) ? htpow - diff : 0; 4959 } 4960 4961 /* Compute per-OFDM rate Tx power. */ 4962 diff = rom->ofdm_tx_pwr_diff[group]; 4963 diff = (diff >> (chain * 4)) & 0xf; 4964 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4965 for (ridx = 4; ridx <= 11; ridx++) { 4966 power[ridx] += ofdmpow; 4967 if (power[ridx] > R92C_MAX_TX_PWR) { 4968 power[ridx] = R92C_MAX_TX_PWR; 4969 } 4970 } 4971 4972 /* Compute per-MCS Tx power. */ 4973 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4974 diff = rom->ht20_tx_pwr_diff[group]; 4975 diff = (diff >> (chain * 4)) & 0xf; 4976 htpow += diff; /* HT40->HT20 correction. */ 4977 } 4978 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4979 power[ridx] += htpow; 4980 if (power[ridx] > R92C_MAX_TX_PWR) { 4981 power[ridx] = R92C_MAX_TX_PWR; 4982 } 4983 } 4984 #ifdef URTWN_DEBUG 4985 if (urtwn_debug & DBG_RF) { 4986 /* Dump per-rate Tx power values. */ 4987 printf("%s: %s: Tx power for chain %zd:\n", 4988 device_xname(sc->sc_dev), __func__, chain); 4989 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4990 printf("%s: %s: Rate %d = %u\n", 4991 device_xname(sc->sc_dev), __func__, ridx, 4992 power[ridx]); 4993 } 4994 } 4995 #endif 4996 } 4997 4998 void 4999 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 5000 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 5001 { 5002 uint16_t cckpow, ofdmpow, bw20pow, htpow; 5003 const struct rtwn_r88e_txpwr *base; 5004 int ridx, group; 5005 5006 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 5007 device_xname(sc->sc_dev), __func__, chain, chan)); 5008 5009 /* Determine channel group. */ 5010 if (chan <= 2) 5011 group = 0; 5012 else if (chan <= 5) 5013 group = 1; 5014 else if (chan <= 8) 5015 group = 2; 5016 else if (chan <= 11) 5017 group = 3; 5018 else if (chan <= 13) 5019 group = 4; 5020 else 5021 group = 5; 5022 5023 /* Get original Tx power based on board type and RF chain. */ 5024 base = &rtl8188eu_txagc[chain]; 5025 5026 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5027 if (sc->regulatory == 0) { 5028 for (ridx = 0; ridx <= 3; ridx++) 5029 power[ridx] = base->pwr[0][ridx]; 5030 } 5031 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5032 if (sc->regulatory == 3) 5033 power[ridx] = base->pwr[0][ridx]; 5034 else if (sc->regulatory == 1) { 5035 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5036 power[ridx] = base->pwr[group][ridx]; 5037 } else if (sc->regulatory != 2) 5038 power[ridx] = base->pwr[0][ridx]; 5039 } 5040 5041 /* Compute per-CCK rate Tx power. */ 5042 cckpow = sc->cck_tx_pwr[group]; 5043 for (ridx = 0; ridx <= 3; ridx++) { 5044 power[ridx] += cckpow; 5045 if (power[ridx] > R92C_MAX_TX_PWR) 5046 power[ridx] = R92C_MAX_TX_PWR; 5047 } 5048 5049 htpow = sc->ht40_tx_pwr[group]; 5050 5051 /* Compute per-OFDM rate Tx power. */ 5052 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5053 for (ridx = 4; ridx <= 11; ridx++) { 5054 power[ridx] += ofdmpow; 5055 if (power[ridx] > R92C_MAX_TX_PWR) 5056 power[ridx] = R92C_MAX_TX_PWR; 5057 } 5058 5059 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5060 for (ridx = 12; ridx <= 27; ridx++) { 5061 power[ridx] += bw20pow; 5062 if (power[ridx] > R92C_MAX_TX_PWR) 5063 power[ridx] = R92C_MAX_TX_PWR; 5064 } 5065 } 5066 5067 static void 5068 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5069 { 5070 uint16_t power[URTWN_RIDX_COUNT]; 5071 size_t i; 5072 5073 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5074 5075 for (i = 0; i < sc->ntxchains; i++) { 5076 /* Compute per-rate Tx power values. */ 5077 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5078 ISSET(sc->chip, URTWN_CHIP_92EU)) 5079 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5080 else 5081 urtwn_get_txpower(sc, i, chan, ht40m, power); 5082 /* Write per-rate Tx power values to hardware. */ 5083 urtwn_write_txpower(sc, i, power); 5084 } 5085 } 5086 5087 static void 5088 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5089 { 5090 struct ieee80211com *ic = &sc->sc_ic; 5091 u_int chan; 5092 size_t i; 5093 5094 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5095 5096 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5097 __func__, chan)); 5098 5099 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5100 5101 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5102 chan += 2; 5103 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5104 chan -= 2; 5105 } 5106 5107 /* Set Tx power for this new channel. */ 5108 urtwn_set_txpower(sc, chan, ht40m); 5109 5110 for (i = 0; i < sc->nrxchains; i++) { 5111 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5112 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5113 } 5114 5115 if (ht40m) { 5116 /* Is secondary channel below or above primary? */ 5117 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5118 uint32_t reg; 5119 5120 urtwn_write_1(sc, R92C_BWOPMODE, 5121 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5122 5123 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5124 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5125 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5126 5127 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5128 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5129 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5130 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5131 5132 /* Set CCK side band. */ 5133 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5134 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5135 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5136 5137 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5138 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5139 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5140 5141 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5142 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5143 ~R92C_FPGA0_ANAPARAM2_CBW20); 5144 5145 reg = urtwn_bb_read(sc, 0x818); 5146 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5147 urtwn_bb_write(sc, 0x818, reg); 5148 5149 /* Select 40MHz bandwidth. */ 5150 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5151 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5152 } else { 5153 urtwn_write_1(sc, R92C_BWOPMODE, 5154 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5155 5156 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5157 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5158 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5159 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5160 5161 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5162 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5163 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5164 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5165 R92C_FPGA0_ANAPARAM2_CBW20); 5166 } 5167 5168 /* Select 20MHz bandwidth. */ 5169 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5170 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5171 (ISSET(sc->chip, URTWN_CHIP_88E) || 5172 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5173 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5174 } 5175 } 5176 5177 static void 5178 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5179 { 5180 5181 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5182 __func__, inited)); 5183 5184 uint32_t addaBackup[16], iqkBackup[4], piMode; 5185 5186 #ifdef notyet 5187 uint32_t odfm0_agccore_regs[3]; 5188 uint32_t ant_regs[3]; 5189 uint32_t rf_regs[8]; 5190 #endif 5191 uint32_t reg0, reg1, reg2; 5192 int i, attempt; 5193 5194 #ifdef notyet 5195 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5196 R92E_STBC_SETTING + 2)); 5197 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5198 /* Save AGCCORE regs. */ 5199 for (i = 0; i < sc->nrxchains; i++) { 5200 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5201 R92C_OFDM0_AGCCORE1(i)); 5202 } 5203 #endif 5204 /* Save BB regs. */ 5205 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5206 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5207 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5208 5209 /* Save adda regs to be restored when finished. */ 5210 for (i = 0; i < __arraycount(addaReg); i++) 5211 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5212 /* Save mac regs. */ 5213 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5214 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5215 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5216 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5217 5218 #ifdef notyet 5219 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5220 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5221 5222 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5223 for (i = 0; i < sc->nrxchains; i++) 5224 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5225 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5226 #endif 5227 5228 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5229 R92C_HSSI_PARAM1_PI); 5230 if (piMode == 0) { 5231 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5232 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5233 R92C_HSSI_PARAM1_PI); 5234 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5235 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5236 R92C_HSSI_PARAM1_PI); 5237 } 5238 5239 attempt = 1; 5240 5241 next_attempt: 5242 5243 /* Set mac regs for calibration. */ 5244 for (i = 0; i < __arraycount(addaReg); i++) { 5245 urtwn_bb_write(sc, addaReg[i], 5246 addaReg[__arraycount(addaReg) - 1]); 5247 } 5248 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5249 R92C_CCK0_AFESETTING)); 5250 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5251 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5252 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5253 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5254 5255 if (sc->ntxchains > 1) 5256 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5257 5258 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5259 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5260 ~R92C_BCN_CTRL_EN_BCN)); 5261 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5262 ~R92C_BCN_CTRL_EN_BCN)); 5263 5264 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5265 ~R92C_GPIO_MUXCFG_ENBT)); 5266 5267 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5268 5269 if (sc->ntxchains > 1) 5270 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5271 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5272 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5273 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5274 5275 /* Restore BB regs. */ 5276 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5277 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5278 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5279 5280 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5281 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5282 if (sc->nrxchains > 1) 5283 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5284 5285 if (attempt-- > 0) 5286 goto next_attempt; 5287 5288 /* Restore mode. */ 5289 if (piMode == 0) { 5290 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5291 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5292 ~R92C_HSSI_PARAM1_PI); 5293 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5294 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5295 ~R92C_HSSI_PARAM1_PI); 5296 } 5297 5298 #ifdef notyet 5299 for (i = 0; i < sc->nrxchains; i++) { 5300 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5301 odfm0_agccore_regs[i]); 5302 } 5303 #endif 5304 5305 /* Restore adda regs. */ 5306 for (i = 0; i < __arraycount(addaReg); i++) 5307 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5308 /* Restore mac regs. */ 5309 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5310 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5311 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5312 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5313 5314 #ifdef notyet 5315 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5316 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5317 5318 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5319 for (i = 0; i < sc->nrxchains; i++) 5320 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5321 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5322 #endif 5323 } 5324 5325 static void 5326 urtwn_lc_calib(struct urtwn_softc *sc) 5327 { 5328 uint32_t rf_ac[2]; 5329 uint8_t txmode; 5330 size_t i; 5331 5332 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5333 5334 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5335 5336 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5337 if ((txmode & 0x70) != 0) { 5338 /* Disable all continuous Tx. */ 5339 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5340 5341 /* Set RF mode to standby mode. */ 5342 for (i = 0; i < sc->nrxchains; i++) { 5343 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5344 urtwn_rf_write(sc, i, R92C_RF_AC, 5345 RW(rf_ac[i], R92C_RF_AC_MODE, 5346 R92C_RF_AC_MODE_STANDBY)); 5347 } 5348 } else { 5349 /* Block all Tx queues. */ 5350 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5351 } 5352 /* Start calibration. */ 5353 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5354 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5355 5356 /* Give calibration the time to complete. */ 5357 urtwn_delay_ms(sc, 100); 5358 5359 /* Restore configuration. */ 5360 if ((txmode & 0x70) != 0) { 5361 /* Restore Tx mode. */ 5362 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5363 /* Restore RF mode. */ 5364 for (i = 0; i < sc->nrxchains; i++) { 5365 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5366 } 5367 } else { 5368 /* Unblock all Tx queues. */ 5369 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5370 } 5371 } 5372 5373 static void 5374 urtwn_temp_calib(struct urtwn_softc *sc) 5375 { 5376 int temp, t_meter_reg; 5377 5378 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5379 5380 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5381 5382 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5383 t_meter_reg = R92C_RF_T_METER; 5384 else 5385 t_meter_reg = R92E_RF_T_METER; 5386 5387 if (sc->thcal_state == 0) { 5388 /* Start measuring temperature. */ 5389 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5390 device_xname(sc->sc_dev), __func__)); 5391 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5392 sc->thcal_state = 1; 5393 return; 5394 } 5395 sc->thcal_state = 0; 5396 5397 /* Read measured temperature. */ 5398 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5399 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5400 __func__, temp)); 5401 if (temp == 0) /* Read failed, skip. */ 5402 return; 5403 5404 /* 5405 * Redo LC calibration if temperature changed significantly since 5406 * last calibration. 5407 */ 5408 if (sc->thcal_lctemp == 0) { 5409 /* First LC calibration is performed in urtwn_init(). */ 5410 sc->thcal_lctemp = temp; 5411 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5412 DPRINTFN(DBG_RF, 5413 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5414 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5415 temp)); 5416 urtwn_lc_calib(sc); 5417 /* Record temperature of last LC calibration. */ 5418 sc->thcal_lctemp = temp; 5419 } 5420 } 5421 5422 static int 5423 urtwn_init(struct ifnet *ifp) 5424 { 5425 struct ieee80211vap *vap = ifp->if_softc; 5426 struct ieee80211com *ic = vap->iv_ic; 5427 struct urtwn_softc *sc = ic->ic_softc; 5428 struct urtwn_rx_data *data; 5429 uint32_t reg; 5430 size_t i; 5431 int error; 5432 5433 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5434 5435 urtwn_stop(ifp, 0); 5436 5437 mutex_enter(&sc->sc_write_mtx); 5438 5439 mutex_enter(&sc->sc_task_mtx); 5440 /* Init host async commands ring. */ 5441 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5442 mutex_exit(&sc->sc_task_mtx); 5443 5444 mutex_enter(&sc->sc_fwcmd_mtx); 5445 /* Init firmware commands ring. */ 5446 sc->fwcur = 0; 5447 mutex_exit(&sc->sc_fwcmd_mtx); 5448 5449 /* Allocate Tx/Rx buffers. */ 5450 error = urtwn_alloc_rx_list(sc); 5451 if (error != 0) { 5452 aprint_error_dev(sc->sc_dev, 5453 "could not allocate Rx buffers\n"); 5454 goto fail; 5455 } 5456 error = urtwn_alloc_tx_list(sc); 5457 if (error != 0) { 5458 aprint_error_dev(sc->sc_dev, 5459 "could not allocate Tx buffers\n"); 5460 goto fail; 5461 } 5462 5463 /* Power on adapter. */ 5464 error = urtwn_power_on(sc); 5465 if (error != 0) 5466 goto fail; 5467 5468 /* Initialize DMA. */ 5469 error = urtwn_dma_init(sc); 5470 if (error != 0) 5471 goto fail; 5472 5473 /* Set info size in Rx descriptors (in 64-bit words). */ 5474 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5475 5476 /* Init interrupts. */ 5477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5478 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5479 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5480 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5481 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5482 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5483 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5484 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5485 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5486 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5487 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5488 } 5489 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5490 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5491 } else { 5492 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5493 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5494 } 5495 5496 /* Set MAC address. */ 5497 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5498 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5499 5500 /* Set initial network type. */ 5501 reg = urtwn_read_4(sc, R92C_CR); 5502 switch (ic->ic_opmode) { 5503 case IEEE80211_M_STA: 5504 default: 5505 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5506 break; 5507 5508 case IEEE80211_M_IBSS: 5509 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5510 break; 5511 } 5512 urtwn_write_4(sc, R92C_CR, reg); 5513 5514 /* Set response rate */ 5515 reg = urtwn_read_4(sc, R92C_RRSR); 5516 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5517 urtwn_write_4(sc, R92C_RRSR, reg); 5518 5519 /* SIFS (used in NAV) */ 5520 urtwn_write_2(sc, R92C_SPEC_SIFS, 5521 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5522 5523 /* Set short/long retry limits. */ 5524 urtwn_write_2(sc, R92C_RL, 5525 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5526 5527 /* Initialize EDCA parameters. */ 5528 urtwn_edca_init(sc); 5529 5530 /* Setup rate fallback. */ 5531 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5532 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5533 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5534 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5535 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5536 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5537 } 5538 5539 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5540 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5541 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5542 /* Set ACK timeout. */ 5543 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5544 5545 /* Setup USB aggregation. */ 5546 /* Tx */ 5547 reg = urtwn_read_4(sc, R92C_TDECTRL); 5548 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5549 urtwn_write_4(sc, R92C_TDECTRL, reg); 5550 /* Rx */ 5551 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5552 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5553 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5554 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5555 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5556 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5557 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5558 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5559 ISSET(sc->chip, URTWN_CHIP_92EU)) 5560 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5561 else 5562 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5563 5564 /* Initialize beacon parameters. */ 5565 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5566 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5567 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5568 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5569 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5570 5571 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5572 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5573 /* Setup AMPDU aggregation. */ 5574 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5575 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5576 urtwn_write_2(sc, 0x4ca, 0x0708); 5577 5578 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5579 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5580 } 5581 5582 /* Load 8051 microcode. */ 5583 error = urtwn_load_firmware(sc); 5584 if (error != 0) 5585 goto fail; 5586 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5587 5588 /* Initialize MAC/BB/RF blocks. */ 5589 /* 5590 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5591 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5592 * XXX: This setting should be removed from rtl8192cu_mac[]. 5593 */ 5594 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5595 urtwn_rxfilter_init(sc); // reset R92C_RCR 5596 urtwn_bb_init(sc); 5597 urtwn_rf_init(sc); 5598 5599 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5600 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5601 urtwn_write_2(sc, R92C_CR, 5602 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5603 R92C_CR_MACRXEN); 5604 } 5605 5606 /* Turn CCK and OFDM blocks on. */ 5607 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5608 reg |= R92C_RFMOD_CCK_EN; 5609 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5610 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5611 reg |= R92C_RFMOD_OFDM_EN; 5612 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5613 5614 /* Clear per-station keys table. */ 5615 urtwn_cam_init(sc); 5616 5617 /* Enable hardware sequence numbering. */ 5618 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5619 5620 /* Perform LO and IQ calibrations. */ 5621 urtwn_iq_calib(sc, sc->iqk_inited); 5622 sc->iqk_inited = true; 5623 5624 /* Perform LC calibration. */ 5625 urtwn_lc_calib(sc); 5626 5627 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5628 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5629 /* Fix USB interference issue. */ 5630 urtwn_write_1(sc, 0xfe40, 0xe0); 5631 urtwn_write_1(sc, 0xfe41, 0x8d); 5632 urtwn_write_1(sc, 0xfe42, 0x80); 5633 urtwn_write_4(sc, 0x20c, 0xfd0320); 5634 5635 urtwn_pa_bias_init(sc); 5636 } 5637 5638 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5639 !(sc->chip & URTWN_CHIP_92EU)) { 5640 /* 1T1R */ 5641 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5642 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5643 } 5644 5645 /* Initialize GPIO setting. */ 5646 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5647 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5648 5649 /* Fix for lower temperature. */ 5650 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5651 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5652 urtwn_write_1(sc, 0x15, 0xe9); 5653 5654 /* Set default channel. */ 5655 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5656 5657 /* Queue Rx xfers. */ 5658 for (size_t j = 0; j < sc->rx_npipe; j++) { 5659 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5660 data = &sc->rx_data[j][i]; 5661 usbd_setup_xfer(data->xfer, data, data->buf, 5662 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5663 urtwn_rxeof); 5664 error = usbd_transfer(data->xfer); 5665 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5666 error != USBD_IN_PROGRESS)) 5667 goto fail; 5668 } 5669 } 5670 5671 /* We're ready to go. */ 5672 ifp->if_flags &= ~IFF_OACTIVE; 5673 ifp->if_flags |= IFF_RUNNING; 5674 sc->sc_running = true; 5675 5676 mutex_exit(&sc->sc_write_mtx); 5677 5678 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5679 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5680 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5681 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5682 urtwn_wait_async(sc); 5683 5684 /* Init the rest of the 802.11 stuff */ 5685 ieee80211_init(ifp); 5686 5687 return 0; 5688 5689 fail: 5690 mutex_exit(&sc->sc_write_mtx); 5691 5692 urtwn_stop(ifp, 1); 5693 return error; 5694 } 5695 5696 static void 5697 urtwn_stop(struct ifnet *ifp, int disable) 5698 { 5699 struct ieee80211vap *vap = ifp->if_softc; 5700 struct ieee80211com *ic = vap->iv_ic; 5701 struct urtwn_softc *sc = ic->ic_softc; 5702 size_t i; 5703 int s; 5704 5705 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5706 5707 s = splusb(); 5708 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5709 urtwn_wait_async(sc); 5710 splx(s); 5711 5712 sc->tx_timer = 0; 5713 ifp->if_timer = 0; 5714 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5715 5716 callout_stop(&sc->sc_scan_to); 5717 callout_stop(&sc->sc_calib_to); 5718 5719 /* Abort Tx. */ 5720 for (i = 0; i < sc->tx_npipe; i++) { 5721 if (sc->tx_pipe[i] != NULL) 5722 usbd_abort_pipe(sc->tx_pipe[i]); 5723 } 5724 5725 /* Stop Rx pipe. */ 5726 for (i = 0; i < sc->rx_npipe; i++) { 5727 if (sc->rx_pipe[i] != NULL) 5728 usbd_abort_pipe(sc->rx_pipe[i]); 5729 } 5730 5731 /* Free Tx/Rx buffers. */ 5732 urtwn_free_tx_list(sc); 5733 urtwn_free_rx_list(sc); 5734 5735 sc->sc_running = false; 5736 if (disable) 5737 urtwn_chip_stop(sc); 5738 } 5739 5740 static int 5741 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5742 { 5743 struct ifnet *ifp = vap->iv_ifp; 5744 struct urtwn_softc *sc = ifp->if_softc; 5745 struct ieee80211com *ic = &sc->sc_ic; 5746 5747 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5748 return ENETRESET; 5749 5750 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5751 5752 return 0; 5753 } 5754 5755 static void 5756 urtwn_chip_stop(struct urtwn_softc *sc) 5757 { 5758 uint32_t reg; 5759 bool disabled = true; 5760 5761 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5762 5763 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5764 ISSET(sc->chip, URTWN_CHIP_92EU)) 5765 return; 5766 5767 mutex_enter(&sc->sc_write_mtx); 5768 5769 /* 5770 * RF Off Sequence 5771 */ 5772 /* Pause MAC TX queue */ 5773 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5774 5775 /* Disable RF */ 5776 urtwn_rf_write(sc, 0, 0, 0); 5777 5778 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5779 5780 /* Reset BB state machine */ 5781 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5782 R92C_SYS_FUNC_EN_USBD | 5783 R92C_SYS_FUNC_EN_USBA | 5784 R92C_SYS_FUNC_EN_BB_GLB_RST); 5785 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5786 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5787 5788 /* 5789 * Reset digital sequence 5790 */ 5791 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5792 /* Reset MCU ready status */ 5793 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5794 /* If firmware in ram code, do reset */ 5795 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5796 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5797 ISSET(sc->chip, URTWN_CHIP_92EU)) 5798 urtwn_r88e_fw_reset(sc); 5799 else 5800 urtwn_fw_reset(sc); 5801 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5802 } 5803 } 5804 5805 /* Reset MAC and Enable 8051 */ 5806 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5807 5808 /* Reset MCU ready status */ 5809 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5810 5811 if (disabled) { 5812 /* Disable MAC clock */ 5813 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5814 /* Disable AFE PLL */ 5815 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5816 /* Gated AFE DIG_CLOCK */ 5817 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5818 /* Isolated digital to PON */ 5819 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5820 } 5821 5822 /* 5823 * Pull GPIO PIN to balance level and LED control 5824 */ 5825 /* 1. Disable GPIO[7:0] */ 5826 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5827 5828 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5829 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5830 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5831 5832 /* Disable GPIO[10:8] */ 5833 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5834 5835 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5836 reg |= (((reg & 0x000f) << 4) | 0x0780); 5837 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5838 5839 /* Disable LED0 & 1 */ 5840 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5841 5842 /* 5843 * Reset digital sequence 5844 */ 5845 if (disabled) { 5846 /* Disable ELDR clock */ 5847 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5848 /* Isolated ELDR to PON */ 5849 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5850 } 5851 5852 /* 5853 * Disable analog sequence 5854 */ 5855 if (disabled) { 5856 /* Disable A15 power */ 5857 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5858 /* Disable digital core power */ 5859 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5860 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5861 ~R92C_LDOV12D_CTRL_LDV12_EN); 5862 } 5863 5864 /* Enter PFM mode */ 5865 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5866 5867 /* Set USB suspend */ 5868 urtwn_write_2(sc, R92C_APS_FSMCO, 5869 R92C_APS_FSMCO_APDM_HOST | 5870 R92C_APS_FSMCO_AFSM_HSUS | 5871 R92C_APS_FSMCO_PFM_ALDN); 5872 5873 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5874 5875 mutex_exit(&sc->sc_write_mtx); 5876 } 5877 5878 static void 5879 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5880 { 5881 if (sc->sc_running == false) 5882 DELAY(ms * 1000); 5883 else 5884 usbd_delay_ms(sc->sc_udev, ms); 5885 } 5886 5887 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5888 5889 #ifdef _MODULE 5890 #include "ioconf.c" 5891 #endif 5892 5893 static int 5894 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5895 { 5896 int error = 0; 5897 5898 switch (cmd) { 5899 case MODULE_CMD_INIT: 5900 #ifdef _MODULE 5901 error = config_init_component(cfdriver_ioconf_urtwn, 5902 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5903 #endif 5904 return error; 5905 case MODULE_CMD_FINI: 5906 #ifdef _MODULE 5907 error = config_fini_component(cfdriver_ioconf_urtwn, 5908 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5909 #endif 5910 return error; 5911 default: 5912 return ENOTTY; 5913 } 5914 } 5915
Indexes created Thu Oct 02 14:10:14 GMT 2025