if_urtwn.c revision 1.59.2.15
1 /* $NetBSD: if_urtwn.c,v 1.59.2.15 2020/04/25 09:32:16 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.15 2020/04/25 09:32:16 nat Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 /* urtwn data */ 227 static const uint8_t urtwn_chan_2ghz[] = 228 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 229 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct ieee80211vap *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 289 int); 290 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ieee80211vap *, u_long); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 /* Functions for wifi refresh */ 340 static struct ieee80211vap * 341 urtwn_vap_create(struct ieee80211com *, 342 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 343 const uint8_t [IEEE80211_ADDR_LEN], 344 const uint8_t [IEEE80211_ADDR_LEN]); 345 static void urtwn_vap_delete(struct ieee80211vap *); 346 static int urtwn_ioctl(struct ifnet *, u_long, void *); 347 static void urtwn_parent(struct ieee80211com *); 348 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 349 struct ieee80211_channel []); 350 static void urtwn_scan_start(struct ieee80211com *); 351 static void urtwn_scan_end(struct ieee80211com *); 352 static void urtwn_set_channel(struct ieee80211com *); 353 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 354 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 355 const struct ieee80211_bpf_params *); 356 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 363 364 static const uint16_t addaReg[] = { 365 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 366 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 367 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 368 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 369 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 370 }; 371 372 static int 373 urtwn_match(device_t parent, cfdata_t match, void *aux) 374 { 375 struct usb_attach_arg *uaa = aux; 376 377 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 378 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 379 } 380 381 static void 382 urtwn_attach(device_t parent, device_t self, void *aux) 383 { 384 struct urtwn_softc *sc = device_private(self); 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct usb_attach_arg *uaa = aux; 387 char *devinfop; 388 const struct urtwn_dev *dev; 389 usb_device_request_t req; 390 // NNN loop below size_t i; 391 int error; 392 393 sc->sc_dev = self; 394 sc->sc_udev = uaa->uaa_device; 395 396 /* Name the ic. */ 397 ic->ic_name = "urtwn"; 398 399 /* Driver Send queue, separate from the if send queue*/ 400 sc->sc_sendq.ifq_maxlen = 32; 401 /* NNN how should this be initialized? */ 402 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 403 sc->sc_sendq.ifq_len = 0; 404 sc->sc_sendq.ifq_drops = 0; 405 IFQ_LOCK_INIT(&sc->sc_sendq); 406 407 sc->chip = 0; 408 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 409 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 410 SET(sc->chip, URTWN_CHIP_88E); 411 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 412 SET(sc->chip, URTWN_CHIP_92EU); 413 414 aprint_naive("\n"); 415 aprint_normal("\n"); 416 417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 418 419 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 420 aprint_normal_dev(self, "%s\n", devinfop); 421 usbd_devinfo_free(devinfop); 422 423 req.bmRequestType = UT_WRITE_DEVICE; 424 req.bRequest = UR_SET_FEATURE; 425 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 426 USETW(req.wIndex, UHF_PORT_SUSPEND); 427 USETW(req.wLength, 0); 428 429 (void) usbd_do_request(sc->sc_udev, &req, 0); 430 431 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 432 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 434 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 435 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 436 437 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 438 439 /* NNN make these callouts use a vap ... in vap create??? */ 440 callout_init(&sc->sc_scan_to, 0); 441 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 442 callout_init(&sc->sc_calib_to, 0); 443 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 444 445 error = usbd_set_config_no(sc->sc_udev, 1, 0); 446 if (error != 0) { 447 aprint_error_dev(self, "failed to set configuration" 448 ", err=%s\n", usbd_errstr(error)); 449 goto fail; 450 } 451 452 /* Get the first interface handle. */ 453 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 454 if (error != 0) { 455 aprint_error_dev(self, "could not get interface handle\n"); 456 goto fail; 457 } 458 459 error = urtwn_read_chipid(sc); 460 if (error != 0) { 461 aprint_error_dev(self, "unsupported test chip\n"); 462 goto fail; 463 } 464 465 /* Determine number of Tx/Rx chains. */ 466 if (sc->chip & URTWN_CHIP_92C) { 467 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 468 sc->nrxchains = 2; 469 } else if (sc->chip & URTWN_CHIP_92EU) { 470 sc->ntxchains = 2; 471 sc->nrxchains = 2; 472 } else { 473 sc->ntxchains = 1; 474 sc->nrxchains = 1; 475 } 476 477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 478 ISSET(sc->chip, URTWN_CHIP_92EU)) 479 urtwn_r88e_read_rom(sc); 480 else 481 urtwn_read_rom(sc); 482 483 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 484 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 485 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 486 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 487 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 488 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 489 "8188CUS", sc->ntxchains, sc->nrxchains, 490 ether_sprintf(ic->ic_macaddr)); 491 492 error = urtwn_open_pipes(sc); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 495 goto fail; 496 } 497 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 498 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 499 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 500 501 /* 502 * Setup the 802.11 device. 503 */ 504 ic->ic_softc = sc; 505 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 506 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 507 508 /* Set device capabilities. */ 509 ic->ic_caps = 510 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 511 IEEE80211_C_IBSS | /* IBSS mode supported */ 512 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 513 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 514 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 515 IEEE80211_C_WME | /* 802.11e */ 516 IEEE80211_C_WPA; /* 802.11i */ 517 518 ic->ic_htcaps = 519 IEEE80211_HTC_HT | 520 IEEE80211_HTCAP_SHORTGI20 | /* short GI in 20MHz */ 521 #if 0 522 IEEE80211_HTCAP_MAXAMSDU_3839 | /* max A-MSDU length */ 523 #endif 524 IEEE80211_HTCAP_SMPS_OFF; /* SM PS mode disabled */ 525 #if 0 526 IEEE80211_HTCAP_CHWIDTH40 | /* 40 MHz channel width */ 527 IEEE80211_HTCAP_SHORTGI40; /* short GI in 40MHz */ 528 #endif 529 530 ic->ic_txstream = sc->ntxchains; 531 ic->ic_rxstream = sc->nrxchains; 532 533 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 534 535 #ifdef should_delete_NNN 536 /* Set supported .11b and .11g channels (1 through 14). */ 537 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 538 for (i = 0; i < 14; i++) { 539 ic->ic_channels[i].ic_freq = 540 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 541 ic->ic_channels[i].ic_flags = 542 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 543 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 544 } 545 #else 546 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 547 ic->ic_channels); 548 #endif 549 /* XXX issues here ... Figure out proper attach and vap creation */ 550 ieee80211_ifattach(ic); 551 552 /* override default methods NNN Need more here? */ 553 ic->ic_newassoc = urtwn_newassoc; 554 ic->ic_wme.wme_update = urtwn_wme_update; 555 ic->ic_vap_create = urtwn_vap_create; 556 ic->ic_vap_delete = urtwn_vap_delete; 557 ic->ic_parent = urtwn_parent; 558 ic->ic_scan_start = urtwn_scan_start; 559 ic->ic_scan_end = urtwn_scan_end; 560 ic->ic_set_channel = urtwn_set_channel; 561 ic->ic_transmit = urtwn_transmit; 562 // ic->ic_send_mgmt = urtwn_send_mgmt; 563 ic->ic_raw_xmit = urtwn_raw_xmit; 564 ic->ic_getradiocaps = urtwn_getradiocaps; 565 566 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 567 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 568 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 569 570 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 571 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 572 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 573 574 ieee80211_announce(ic); 575 576 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 577 578 if (!pmf_device_register(self, NULL, NULL)) 579 aprint_error_dev(self, "couldn't establish power handler\n"); 580 581 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 582 583 /* Should be called via an IOCTL. Temp call here for now. */ 584 585 struct ieee80211vap *vap = 586 urtwn_vap_create(ic, device_xname(sc->sc_dev), 587 device_unit(sc->sc_dev), IEEE80211_M_STA, 588 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 589 590 if (vap == NULL) { 591 /* Didn't work ... now what! */ 592 printf ("NNN vap_create didn't work ...\n"); 593 ieee80211_ifdetach(ic); 594 goto fail; 595 } 596 597 return; 598 599 fail: 600 sc->sc_dying = 1; 601 aprint_error_dev(self, "attach failed\n"); 602 } 603 604 static int 605 urtwn_detach(device_t self, int flags) 606 { 607 struct urtwn_softc *sc = device_private(self); 608 struct ieee80211com *ic = &sc->sc_ic; 609 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 610 struct ifnet *ifp = vap->iv_ifp; 611 int s; 612 613 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 614 615 pmf_device_deregister(self); 616 617 s = splusb(); 618 619 sc->sc_dying = 1; 620 621 callout_halt(&sc->sc_scan_to, NULL); 622 callout_halt(&sc->sc_calib_to, NULL); 623 624 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 625 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 626 NULL); 627 urtwn_stop(ifp, 0); 628 // vap_detach(...) ?? 629 630 ieee80211_ifdetach(&sc->sc_ic); 631 632 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 633 urtwn_close_pipes(sc); 634 } 635 636 /* sendq destroy */ 637 IFQ_PURGE(&sc->sc_sendq); 638 IFQ_LOCK_DESTROY(&sc->sc_sendq); 639 640 splx(s); 641 642 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 643 644 callout_destroy(&sc->sc_scan_to); 645 callout_destroy(&sc->sc_calib_to); 646 647 mutex_destroy(&sc->sc_write_mtx); 648 mutex_destroy(&sc->sc_fwcmd_mtx); 649 mutex_destroy(&sc->sc_tx_mtx); 650 mutex_destroy(&sc->sc_rx_mtx); 651 mutex_destroy(&sc->sc_task_mtx); 652 653 return 0; 654 } 655 656 static int 657 urtwn_activate(device_t self, enum devact act) 658 { 659 struct urtwn_softc *sc = device_private(self); 660 661 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 662 663 switch (act) { 664 case DVACT_DEACTIVATE: 665 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 666 667 return 0; 668 default: 669 return EOPNOTSUPP; 670 } 671 } 672 673 static int 674 urtwn_open_pipes(struct urtwn_softc *sc) 675 { 676 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 677 static uint8_t epaddr[R92C_MAX_EPOUT]; 678 static uint8_t rxepaddr[R92C_MAX_EPIN]; 679 usb_interface_descriptor_t *id; 680 usb_endpoint_descriptor_t *ed; 681 size_t i, ntx = 0, nrx = 0; 682 int error; 683 684 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 685 686 /* Determine the number of bulk-out pipes. */ 687 id = usbd_get_interface_descriptor(sc->sc_iface); 688 for (i = 0; i < id->bNumEndpoints; i++) { 689 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 690 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 691 continue; 692 } 693 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 694 if (ntx < sizeof(epaddr)) 695 epaddr[ntx] = ed->bEndpointAddress; 696 ntx++; 697 } 698 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 699 if (nrx < sizeof(rxepaddr)) 700 rxepaddr[nrx] = ed->bEndpointAddress; 701 nrx++; 702 } 703 } 704 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 705 aprint_error_dev(sc->sc_dev, 706 "%zd: invalid number of Rx bulk pipes\n", nrx); 707 return EIO; 708 } 709 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 710 aprint_error_dev(sc->sc_dev, 711 "%zd: invalid number of Tx bulk pipes\n", ntx); 712 return EIO; 713 } 714 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 715 device_xname(sc->sc_dev), __func__, nrx, ntx)); 716 sc->rx_npipe = nrx; 717 sc->tx_npipe = ntx; 718 719 /* Open bulk-in pipe at address 0x81. */ 720 for (i = 0; i < nrx; i++) { 721 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 722 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 723 if (error != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "could not open Rx bulk pipe 0x%02x: %d\n", 726 rxepaddr[i], error); 727 goto fail; 728 } 729 } 730 731 /* Open bulk-out pipes (up to 3). */ 732 for (i = 0; i < ntx; i++) { 733 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 734 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 735 if (error != 0) { 736 aprint_error_dev(sc->sc_dev, 737 "could not open Tx bulk pipe 0x%02x: %d\n", 738 epaddr[i], error); 739 goto fail; 740 } 741 } 742 743 /* Map 802.11 access categories to USB pipes. */ 744 sc->ac2idx[WME_AC_BK] = 745 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 746 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 747 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 748 749 fail: 750 if (error != 0) 751 urtwn_close_pipes(sc); 752 return error; 753 } 754 755 static void 756 urtwn_close_pipes(struct urtwn_softc *sc) 757 { 758 struct usbd_pipe *pipe; 759 size_t i; 760 761 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 762 763 /* Close Rx pipes. */ 764 CTASSERT(sizeof(pipe) == sizeof(void *)); 765 for (i = 0; i < sc->rx_npipe; i++) { 766 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 767 if (pipe != NULL) { 768 usbd_close_pipe(pipe); 769 } 770 } 771 772 /* Close Tx pipes. */ 773 for (i = 0; i < sc->tx_npipe; i++) { 774 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 775 if (pipe != NULL) { 776 usbd_close_pipe(pipe); 777 } 778 } 779 } 780 781 static int 782 urtwn_alloc_rx_list(struct urtwn_softc *sc) 783 { 784 struct urtwn_rx_data *data; 785 size_t i; 786 int error = 0; 787 788 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 789 790 for (size_t j = 0; j < sc->rx_npipe; j++) { 791 TAILQ_INIT(&sc->rx_free_list[j]); 792 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 793 data = &sc->rx_data[j][i]; 794 795 data->sc = sc; /* Backpointer for callbacks. */ 796 797 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 798 0, 0, &data->xfer); 799 if (error) { 800 aprint_error_dev(sc->sc_dev, 801 "could not allocate xfer\n"); 802 break; 803 } 804 805 data->buf = usbd_get_buffer(data->xfer); 806 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 807 } 808 } 809 if (error != 0) 810 urtwn_free_rx_list(sc); 811 return error; 812 } 813 814 static void 815 urtwn_free_rx_list(struct urtwn_softc *sc) 816 { 817 struct usbd_xfer *xfer; 818 size_t i; 819 820 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 821 822 /* NB: Caller must abort pipe first. */ 823 for (size_t j = 0; j < sc->rx_npipe; j++) { 824 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 825 CTASSERT(sizeof(xfer) == sizeof(void *)); 826 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 827 if (xfer != NULL) 828 usbd_destroy_xfer(xfer); 829 } 830 } 831 } 832 833 static int 834 urtwn_alloc_tx_list(struct urtwn_softc *sc) 835 { 836 struct urtwn_tx_data *data; 837 size_t i; 838 int error = 0; 839 840 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 841 842 mutex_enter(&sc->sc_tx_mtx); 843 for (size_t j = 0; j < sc->tx_npipe; j++) { 844 TAILQ_INIT(&sc->tx_free_list[j]); 845 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 846 data = &sc->tx_data[j][i]; 847 848 data->sc = sc; /* Backpointer for callbacks. */ 849 data->pidx = j; 850 851 error = usbd_create_xfer(sc->tx_pipe[j], 852 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 853 &data->xfer); 854 if (error) { 855 aprint_error_dev(sc->sc_dev, 856 "could not allocate xfer\n"); 857 goto fail; 858 } 859 860 data->buf = usbd_get_buffer(data->xfer); 861 862 /* Append this Tx buffer to our free list. */ 863 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 864 } 865 } 866 mutex_exit(&sc->sc_tx_mtx); 867 return 0; 868 869 fail: 870 urtwn_free_tx_list(sc); 871 mutex_exit(&sc->sc_tx_mtx); 872 return error; 873 } 874 875 static void 876 urtwn_free_tx_list(struct urtwn_softc *sc) 877 { 878 struct usbd_xfer *xfer; 879 size_t i; 880 881 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 882 883 /* NB: Caller must abort pipe first. */ 884 for (size_t j = 0; j < sc->tx_npipe; j++) { 885 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 886 CTASSERT(sizeof(xfer) == sizeof(void *)); 887 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 888 if (xfer != NULL) 889 usbd_destroy_xfer(xfer); 890 } 891 } 892 } 893 894 static int 895 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 896 struct ieee80211_node *ni) 897 { 898 struct urtwn_tx_data *data = 899 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 900 return urtwn_tx(sc, m, ni, data); 901 } 902 903 static void 904 urtwn_task(void *arg) 905 { 906 struct urtwn_softc *sc = arg; 907 struct ieee80211com *ic = &sc->sc_ic; 908 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 909 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 910 struct urtwn_host_cmd *cmd; 911 int s; 912 913 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 914 if (vap->iv_state == IEEE80211_S_RUN && 915 (ic->ic_opmode == IEEE80211_M_HOSTAP || 916 ic->ic_opmode == IEEE80211_M_IBSS)) { 917 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 918 if (m == NULL) { 919 aprint_error_dev(sc->sc_dev, 920 "could not allocate beacon"); 921 } 922 923 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 924 m_freem(m); 925 aprint_error_dev(sc->sc_dev, "could not send beacon"); 926 } 927 928 /* beacon is no longer needed */ 929 m_freem(m); 930 } 931 932 /* Process host commands. */ 933 s = splusb(); 934 mutex_spin_enter(&sc->sc_task_mtx); 935 while (ring->next != ring->cur) { 936 cmd = &ring->cmd[ring->next]; 937 mutex_spin_exit(&sc->sc_task_mtx); 938 splx(s); 939 /* Invoke callback with kernel lock held. */ 940 cmd->cb(sc, cmd->data); 941 s = splusb(); 942 mutex_spin_enter(&sc->sc_task_mtx); 943 ring->queued--; 944 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 945 } 946 mutex_spin_exit(&sc->sc_task_mtx); 947 wakeup(&sc->cmdq); 948 splx(s); 949 } 950 951 static void 952 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 953 void *arg, int len) 954 { 955 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 956 struct urtwn_host_cmd *cmd; 957 int s; 958 959 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 960 device_xname(sc->sc_dev), __func__, cb, arg, len)); 961 962 s = splusb(); 963 mutex_spin_enter(&sc->sc_task_mtx); 964 cmd = &ring->cmd[ring->cur]; 965 cmd->cb = cb; 966 KASSERT(len <= sizeof(cmd->data)); 967 memcpy(cmd->data, arg, len); 968 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 969 970 /* If there is no pending command already, schedule a task. */ 971 if (!sc->sc_dying && ++ring->queued == 1) { 972 mutex_spin_exit(&sc->sc_task_mtx); 973 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 974 } else 975 mutex_spin_exit(&sc->sc_task_mtx); 976 splx(s); 977 } 978 979 static void 980 urtwn_wait_async(struct urtwn_softc *sc) 981 { 982 983 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 984 985 /* Wait for all queued asynchronous commands to complete. */ 986 while (sc->cmdq.queued > 0) 987 tsleep(&sc->cmdq, 0, "endtask", 0); 988 } 989 990 static int 991 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 992 int len) 993 { 994 usb_device_request_t req; 995 usbd_status error; 996 997 KASSERT(mutex_owned(&sc->sc_write_mtx)); 998 999 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1000 req.bRequest = R92C_REQ_REGS; 1001 USETW(req.wValue, addr); 1002 USETW(req.wIndex, 0); 1003 USETW(req.wLength, len); 1004 error = usbd_do_request(sc->sc_udev, &req, buf); 1005 if (error != USBD_NORMAL_COMPLETION) { 1006 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1007 device_xname(sc->sc_dev), __func__, error, addr, len)); 1008 } 1009 return error; 1010 } 1011 1012 static void 1013 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1014 { 1015 1016 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1017 device_xname(sc->sc_dev), __func__, addr, val)); 1018 1019 urtwn_write_region_1(sc, addr, &val, 1); 1020 } 1021 1022 static void 1023 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1024 { 1025 uint8_t buf[2]; 1026 1027 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1028 device_xname(sc->sc_dev), __func__, addr, val)); 1029 1030 buf[0] = (uint8_t)val; 1031 buf[1] = (uint8_t)(val >> 8); 1032 urtwn_write_region_1(sc, addr, buf, 2); 1033 } 1034 1035 static void 1036 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1037 { 1038 uint8_t buf[4]; 1039 1040 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1041 device_xname(sc->sc_dev), __func__, addr, val)); 1042 1043 buf[0] = (uint8_t)val; 1044 buf[1] = (uint8_t)(val >> 8); 1045 buf[2] = (uint8_t)(val >> 16); 1046 buf[3] = (uint8_t)(val >> 24); 1047 urtwn_write_region_1(sc, addr, buf, 4); 1048 } 1049 1050 static int 1051 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1052 { 1053 1054 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, len=%#x\n", 1055 device_xname(sc->sc_dev), __func__, addr, len)); 1056 1057 return urtwn_write_region_1(sc, addr, buf, len); 1058 } 1059 1060 static int 1061 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1062 int len) 1063 { 1064 usb_device_request_t req; 1065 usbd_status error; 1066 1067 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1068 req.bRequest = R92C_REQ_REGS; 1069 USETW(req.wValue, addr); 1070 USETW(req.wIndex, 0); 1071 USETW(req.wLength, len); 1072 error = usbd_do_request(sc->sc_udev, &req, buf); 1073 if (error != USBD_NORMAL_COMPLETION) { 1074 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1075 device_xname(sc->sc_dev), __func__, error, addr, len)); 1076 } 1077 return error; 1078 } 1079 1080 static uint8_t 1081 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1082 { 1083 uint8_t val; 1084 1085 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1086 return 0xff; 1087 1088 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1089 device_xname(sc->sc_dev), __func__, addr, val)); 1090 return val; 1091 } 1092 1093 static uint16_t 1094 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1095 { 1096 uint8_t buf[2]; 1097 uint16_t val; 1098 1099 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1100 return 0xffff; 1101 1102 val = LE_READ_2(&buf[0]); 1103 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1104 device_xname(sc->sc_dev), __func__, addr, val)); 1105 return val; 1106 } 1107 1108 static uint32_t 1109 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1110 { 1111 uint8_t buf[4]; 1112 uint32_t val; 1113 1114 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1115 return 0xffffffff; 1116 1117 val = LE_READ_4(&buf[0]); 1118 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1119 device_xname(sc->sc_dev), __func__, addr, val)); 1120 return val; 1121 } 1122 1123 static int 1124 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1125 { 1126 struct r92c_fw_cmd cmd; 1127 uint8_t *cp; 1128 int fwcur; 1129 int ntries; 1130 1131 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1132 device_xname(sc->sc_dev), __func__, id, buf, len)); 1133 1134 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1135 1136 mutex_enter(&sc->sc_fwcmd_mtx); 1137 fwcur = sc->fwcur; 1138 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1139 mutex_exit(&sc->sc_fwcmd_mtx); 1140 1141 /* Wait for current FW box to be empty. */ 1142 for (ntries = 0; ntries < 100; ntries++) { 1143 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1144 break; 1145 DELAY(2000); 1146 } 1147 if (ntries == 100) { 1148 aprint_error_dev(sc->sc_dev, 1149 "could not send firmware command %d\n", id); 1150 return ETIMEDOUT; 1151 } 1152 1153 memset(&cmd, 0, sizeof(cmd)); 1154 KASSERT(len <= sizeof(cmd.msg)); 1155 memcpy(cmd.msg, buf, len); 1156 1157 /* Write the first word last since that will trigger the FW. */ 1158 cp = (uint8_t *)&cmd; 1159 cmd.id = id; 1160 if (len >= 4) { 1161 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1162 cmd.id |= R92C_CMD_FLAG_EXT; 1163 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1164 &cp[1], 2); 1165 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1166 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1167 (cp[5] << 24)); 1168 } else { 1169 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1170 &cp[4], 2); 1171 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1172 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1173 (cp[3] << 24)); 1174 } 1175 } else { 1176 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1177 } 1178 1179 return 0; 1180 } 1181 1182 static __inline void 1183 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1184 { 1185 1186 sc->sc_rf_write(sc, chain, addr, val); 1187 } 1188 1189 static void 1190 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1191 uint32_t val) 1192 { 1193 1194 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1195 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1196 } 1197 1198 static void 1199 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1200 uint32_t val) 1201 { 1202 1203 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1204 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1205 } 1206 1207 static void 1208 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1209 uint32_t val) 1210 { 1211 1212 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1213 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1214 } 1215 1216 static uint32_t 1217 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1218 { 1219 uint32_t reg[R92C_MAX_CHAINS], val; 1220 1221 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1222 if (chain != 0) { 1223 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1224 } 1225 1226 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1227 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1228 DELAY(1000); 1229 1230 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1231 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1232 R92C_HSSI_PARAM2_READ_EDGE); 1233 DELAY(1000); 1234 1235 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1236 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1237 DELAY(1000); 1238 1239 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1240 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1241 } else { 1242 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1243 } 1244 return MS(val, R92C_LSSI_READBACK_DATA); 1245 } 1246 1247 static int 1248 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1249 { 1250 int ntries; 1251 1252 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1253 1254 urtwn_write_4(sc, R92C_LLT_INIT, 1255 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1256 SM(R92C_LLT_INIT_ADDR, addr) | 1257 SM(R92C_LLT_INIT_DATA, data)); 1258 /* Wait for write operation to complete. */ 1259 for (ntries = 0; ntries < 20; ntries++) { 1260 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1261 R92C_LLT_INIT_OP_NO_ACTIVE) { 1262 /* Done */ 1263 return 0; 1264 } 1265 DELAY(5); 1266 } 1267 return ETIMEDOUT; 1268 } 1269 1270 static uint8_t 1271 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1272 { 1273 uint32_t reg; 1274 int ntries; 1275 1276 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1277 1278 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1279 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1280 reg &= ~R92C_EFUSE_CTRL_VALID; 1281 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1282 1283 /* Wait for read operation to complete. */ 1284 for (ntries = 0; ntries < 100; ntries++) { 1285 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1286 if (reg & R92C_EFUSE_CTRL_VALID) { 1287 /* Done */ 1288 return MS(reg, R92C_EFUSE_CTRL_DATA); 1289 } 1290 DELAY(5); 1291 } 1292 aprint_error_dev(sc->sc_dev, 1293 "could not read efuse byte at address 0x%04x\n", addr); 1294 return 0xff; 1295 } 1296 1297 static void 1298 urtwn_efuse_read(struct urtwn_softc *sc) 1299 { 1300 uint8_t *rom = (uint8_t *)&sc->rom; 1301 uint32_t reg; 1302 uint16_t addr = 0; 1303 uint8_t off, msk; 1304 size_t i; 1305 1306 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1307 1308 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1309 1310 urtwn_efuse_switch_power(sc); 1311 1312 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1313 while (addr < 512) { 1314 reg = urtwn_efuse_read_1(sc, addr); 1315 if (reg == 0xff) 1316 break; 1317 addr++; 1318 off = reg >> 4; 1319 msk = reg & 0xf; 1320 for (i = 0; i < 4; i++) { 1321 if (msk & (1U << i)) 1322 continue; 1323 1324 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1325 addr++; 1326 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1327 addr++; 1328 } 1329 } 1330 #ifdef URTWN_DEBUG 1331 if (urtwn_debug & DBG_INIT) { 1332 /* Dump ROM content. */ 1333 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1334 for (i = 0; i < (int)sizeof(sc->rom); i++) 1335 printf(":%02x", rom[i]); 1336 printf("\n"); 1337 } 1338 #endif 1339 } 1340 1341 static void 1342 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1343 { 1344 uint32_t reg; 1345 1346 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1347 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1348 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1349 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1350 } 1351 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1352 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1353 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1354 reg | R92C_SYS_FUNC_EN_ELDR); 1355 } 1356 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1357 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1358 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1359 urtwn_write_2(sc, R92C_SYS_CLKR, 1360 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1361 } 1362 } 1363 1364 static int 1365 urtwn_read_chipid(struct urtwn_softc *sc) 1366 { 1367 uint32_t reg; 1368 1369 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1370 1371 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1372 ISSET(sc->chip, URTWN_CHIP_92EU)) 1373 return 0; 1374 1375 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1376 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1377 /* test chip, not supported */ 1378 return EIO; 1379 } 1380 if (reg & R92C_SYS_CFG_TYPE_92C) { 1381 sc->chip |= URTWN_CHIP_92C; 1382 /* Check if it is a castrated 8192C. */ 1383 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1384 R92C_HPON_FSM_CHIP_BONDING_ID) == 1385 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1386 sc->chip |= URTWN_CHIP_92C_1T2R; 1387 } 1388 } 1389 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1390 sc->chip |= URTWN_CHIP_UMC; 1391 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1392 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1393 } 1394 } 1395 return 0; 1396 } 1397 1398 #ifdef URTWN_DEBUG 1399 static void 1400 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1401 { 1402 1403 aprint_normal_dev(sc->sc_dev, 1404 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1405 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1406 1407 aprint_normal_dev(sc->sc_dev, 1408 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1409 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1410 1411 aprint_normal_dev(sc->sc_dev, 1412 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1413 rp->macaddr[0], rp->macaddr[1], 1414 rp->macaddr[2], rp->macaddr[3], 1415 rp->macaddr[4], rp->macaddr[5]); 1416 1417 aprint_normal_dev(sc->sc_dev, 1418 "string %s, subcustomer_id %#x\n", 1419 rp->string, rp->subcustomer_id); 1420 1421 aprint_normal_dev(sc->sc_dev, 1422 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1423 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1424 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1425 1426 aprint_normal_dev(sc->sc_dev, 1427 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1428 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1429 rp->ht40_1s_tx_pwr[0][2], 1430 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1431 rp->ht40_1s_tx_pwr[1][2]); 1432 1433 aprint_normal_dev(sc->sc_dev, 1434 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1435 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1436 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1437 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1438 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1439 1440 aprint_normal_dev(sc->sc_dev, 1441 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1442 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1443 rp->ht20_tx_pwr_diff[2] & 0xf, 1444 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1445 rp->ht20_tx_pwr_diff[2] >> 4); 1446 1447 aprint_normal_dev(sc->sc_dev, 1448 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1449 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1450 rp->ofdm_tx_pwr_diff[2] & 0xf, 1451 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1452 rp->ofdm_tx_pwr_diff[2] >> 4); 1453 1454 aprint_normal_dev(sc->sc_dev, 1455 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1456 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1457 rp->ht40_max_pwr[2] & 0xf, 1458 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1459 rp->ht40_max_pwr[2] >> 4); 1460 1461 aprint_normal_dev(sc->sc_dev, 1462 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1463 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1464 rp->ht20_max_pwr[2] & 0xf, 1465 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1466 rp->ht20_max_pwr[2] >> 4); 1467 1468 aprint_normal_dev(sc->sc_dev, 1469 "xtal_calib %d, tssi %d %d, thermal %d\n", 1470 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1471 1472 aprint_normal_dev(sc->sc_dev, 1473 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1474 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1475 1476 aprint_normal_dev(sc->sc_dev, 1477 "channnel_plan %d, version %d customer_id %#x\n", 1478 rp->channel_plan, rp->version, rp->curstomer_id); 1479 } 1480 #endif 1481 1482 static void 1483 urtwn_read_rom(struct urtwn_softc *sc) 1484 { 1485 struct ieee80211com *ic = &sc->sc_ic; 1486 struct r92c_rom *rom = &sc->rom; 1487 1488 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1489 1490 mutex_enter(&sc->sc_write_mtx); 1491 1492 /* Read full ROM image. */ 1493 urtwn_efuse_read(sc); 1494 #ifdef URTWN_DEBUG 1495 if (urtwn_debug & DBG_REG) 1496 urtwn_dump_rom(sc, rom); 1497 #endif 1498 1499 /* XXX Weird but this is what the vendor driver does. */ 1500 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1501 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1502 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1503 1504 DPRINTFN(DBG_INIT, 1505 ("%s: %s: PA setting=%#x, board=%#x, regulatory=%d\n", 1506 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1507 sc->board_type, sc->regulatory)); 1508 1509 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1510 1511 sc->sc_rf_write = urtwn_r92c_rf_write; 1512 sc->sc_power_on = urtwn_r92c_power_on; 1513 sc->sc_dma_init = urtwn_r92c_dma_init; 1514 1515 mutex_exit(&sc->sc_write_mtx); 1516 } 1517 1518 static void 1519 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1520 { 1521 struct ieee80211com *ic = &sc->sc_ic; 1522 uint8_t *rom = sc->r88e_rom; 1523 uint32_t reg; 1524 uint16_t addr = 0; 1525 uint8_t off, msk, tmp; 1526 int i; 1527 1528 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1529 1530 mutex_enter(&sc->sc_write_mtx); 1531 1532 off = 0; 1533 urtwn_efuse_switch_power(sc); 1534 1535 /* Read full ROM image. */ 1536 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1537 while (addr < 4096) { 1538 reg = urtwn_efuse_read_1(sc, addr); 1539 if (reg == 0xff) 1540 break; 1541 addr++; 1542 if ((reg & 0x1f) == 0x0f) { 1543 tmp = (reg & 0xe0) >> 5; 1544 reg = urtwn_efuse_read_1(sc, addr); 1545 if ((reg & 0x0f) != 0x0f) 1546 off = ((reg & 0xf0) >> 1) | tmp; 1547 addr++; 1548 } else 1549 off = reg >> 4; 1550 msk = reg & 0xf; 1551 for (i = 0; i < 4; i++) { 1552 if (msk & (1 << i)) 1553 continue; 1554 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1555 addr++; 1556 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1557 addr++; 1558 } 1559 } 1560 #ifdef URTWN_DEBUG 1561 if (urtwn_debug & DBG_REG) { 1562 } 1563 #endif 1564 1565 addr = 0x10; 1566 for (i = 0; i < 6; i++) 1567 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1568 for (i = 0; i < 5; i++) 1569 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1570 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1571 if (sc->bw20_tx_pwr_diff & 0x08) 1572 sc->bw20_tx_pwr_diff |= 0xf0; 1573 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1574 if (sc->ofdm_tx_pwr_diff & 0x08) 1575 sc->ofdm_tx_pwr_diff |= 0xf0; 1576 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1577 1578 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1579 1580 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1581 sc->sc_power_on = urtwn_r92e_power_on; 1582 sc->sc_rf_write = urtwn_r92e_rf_write; 1583 } else { 1584 sc->sc_power_on = urtwn_r88e_power_on; 1585 sc->sc_rf_write = urtwn_r88e_rf_write; 1586 } 1587 sc->sc_dma_init = urtwn_r88e_dma_init; 1588 1589 mutex_exit(&sc->sc_write_mtx); 1590 } 1591 1592 /* NNN Do we need to do something with this? */ 1593 1594 static __unused int 1595 urtwn_media_change(struct ifnet *ifp) 1596 { 1597 #ifdef URTWN_DEBUG 1598 struct ieee80211vap *vap = ifp->if_softc; 1599 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1600 #endif 1601 int error; 1602 1603 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1604 1605 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1606 return error; 1607 1608 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1609 (IFF_UP | IFF_RUNNING)) { 1610 urtwn_init(ifp); 1611 } 1612 return 0; 1613 } 1614 1615 /* 1616 * Initialize rate adaptation in firmware. 1617 */ 1618 static int 1619 urtwn_ra_init(struct ieee80211vap *vap) 1620 { 1621 static const uint8_t map[] = { 1622 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1623 }; 1624 struct ieee80211com *ic = vap->iv_ic; 1625 struct urtwn_softc *sc = ic->ic_softc; 1626 struct ieee80211_node *ni = vap->iv_bss; 1627 struct ieee80211_rateset *rs = &ni->ni_rates; 1628 1629 struct r92c_fw_cmd_macid_cfg cmd; 1630 uint32_t rates, basicrates; 1631 uint32_t rrsr_mask, rrsr_rate; 1632 uint8_t mode; 1633 size_t maxrate, maxbasicrate, i, j; 1634 int error; 1635 1636 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1637 1638 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1639 1640 /* Get normal and basic rates mask. */ 1641 rates = basicrates = 1; 1642 maxrate = maxbasicrate = 0; 1643 for (i = 0; i < rs->rs_nrates; i++) { 1644 /* Convert 802.11 rate to HW rate index. */ 1645 for (j = 0; j < __arraycount(map); j++) { 1646 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1647 break; 1648 } 1649 } 1650 if (j == __arraycount(map)) { 1651 /* Unknown rate, skip. */ 1652 continue; 1653 } 1654 1655 rates |= 1U << j; 1656 if (j > maxrate) { 1657 maxrate = j; 1658 } 1659 1660 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1661 basicrates |= 1U << j; 1662 if (j > maxbasicrate) { 1663 maxbasicrate = j; 1664 } 1665 } 1666 } 1667 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1668 mode = R92C_RAID_11B; 1669 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 1670 mode = R92C_RAID_11BG; 1671 } else /* mode = IEEE80211_MODE_11NG */ 1672 mode = R92C_RAID_11GN; 1673 DPRINTFN(DBG_INIT, ("%s: %s: mode=%#x rates=%#x, basicrates=%#x, " 1674 "maxrate=%zx, maxbasicrate=%zx\n", 1675 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1676 maxrate, maxbasicrate)); 1677 1678 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1679 maxbasicrate |= R92C_RATE_SHORTGI; 1680 maxrate |= R92C_RATE_SHORTGI; 1681 } 1682 1683 /* Set rates mask for group addressed frames. */ 1684 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1685 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1686 cmd.macid |= RTWN_MACID_SHORTGI; 1687 cmd.mask = htole32((mode << 28) | basicrates); 1688 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1689 if (error != 0) { 1690 aprint_error_dev(sc->sc_dev, 1691 "could not add broadcast station\n"); 1692 return error; 1693 } 1694 /* Set initial MRR rate. */ 1695 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1696 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1697 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1698 1699 /* Set rates mask for unicast frames. */ 1700 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1701 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1702 cmd.macid |= RTWN_MACID_SHORTGI; 1703 cmd.mask = htole32((mode << 28) | rates); 1704 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1705 if (error != 0) { 1706 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1707 return error; 1708 } 1709 /* Set initial MRR rate. */ 1710 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1711 __func__, maxrate)); 1712 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1713 1714 #if notyet 1715 /* NNN appears to have no fixed rate anywhere. */ 1716 rrsr_rate = ic->ic_fixed_rate; 1717 if (rrsr_rate == -1) 1718 #endif 1719 rrsr_rate = 11; 1720 1721 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1722 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1723 1724 #if notyet 1725 /* Indicate highest supported rate. */ 1726 ni->ni_txrate = rs->rs_nrates - 1; 1727 #endif 1728 return 0; 1729 } 1730 1731 static int 1732 urtwn_get_nettype(struct urtwn_softc *sc) 1733 { 1734 struct ieee80211com *ic = &sc->sc_ic; 1735 int type; 1736 1737 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1738 1739 switch (ic->ic_opmode) { 1740 case IEEE80211_M_STA: 1741 type = R92C_CR_NETTYPE_INFRA; 1742 break; 1743 1744 case IEEE80211_M_IBSS: 1745 type = R92C_CR_NETTYPE_ADHOC; 1746 break; 1747 1748 default: 1749 type = R92C_CR_NETTYPE_NOLINK; 1750 break; 1751 } 1752 1753 return type; 1754 } 1755 1756 static void 1757 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1758 { 1759 uint8_t reg; 1760 1761 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1762 __func__, type)); 1763 1764 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1765 1766 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1767 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1768 } 1769 1770 static void 1771 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1772 { 1773 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1774 struct ieee80211_node *ni = vap->iv_bss; 1775 uint64_t tsf; 1776 1777 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1778 1779 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1780 1781 /* Enable TSF synchronization. */ 1782 urtwn_write_1(sc, R92C_BCN_CTRL, 1783 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1784 1785 /* Correct TSF */ 1786 urtwn_write_1(sc, R92C_BCN_CTRL, 1787 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1788 1789 /* Set initial TSF. */ 1790 tsf = ni->ni_tstamp.tsf; 1791 tsf = le64toh(tsf); 1792 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1793 tsf -= IEEE80211_DUR_TU; 1794 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1795 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1796 1797 urtwn_write_1(sc, R92C_BCN_CTRL, 1798 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1799 } 1800 1801 static void 1802 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1803 { 1804 uint8_t reg; 1805 1806 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1807 __func__, led, on)); 1808 1809 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1810 1811 if (led == URTWN_LED_LINK) { 1812 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1813 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1814 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1815 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1816 (R92C_LEDCFG0_DIS << 1)); 1817 if (on) { 1818 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1819 R92E_LEDSON; 1820 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1821 } 1822 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1823 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1824 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1825 if (!on) { 1826 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1827 urtwn_write_1(sc, R92C_LEDCFG2, 1828 reg | R92C_LEDCFG0_DIS); 1829 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1830 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1831 reg & 0xfe); 1832 } 1833 } else { 1834 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1835 if (!on) { 1836 reg |= R92C_LEDCFG0_DIS; 1837 } 1838 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1839 } 1840 sc->ledlink = on; /* Save LED state. */ 1841 } 1842 } 1843 1844 static void 1845 urtwn_calib_to(void *arg) 1846 { 1847 struct urtwn_softc *sc = arg; 1848 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1849 1850 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1851 1852 if (sc->sc_dying) 1853 return; 1854 1855 /* Do it in a process context. */ 1856 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1857 } 1858 1859 /* ARGSUSED */ 1860 static void 1861 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1862 { 1863 struct ieee80211vap *vap = arg; 1864 struct r92c_fw_cmd_rssi cmd; 1865 struct r92e_fw_cmd_rssi cmde; 1866 1867 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1868 1869 if (vap->iv_state != IEEE80211_S_RUN) 1870 goto restart_timer; 1871 1872 mutex_enter(&sc->sc_write_mtx); 1873 if (sc->avg_pwdb != -1) { 1874 /* Indicate Rx signal strength to FW for rate adaptation. */ 1875 memset(&cmd, 0, sizeof(cmd)); 1876 memset(&cmde, 0, sizeof(cmde)); 1877 cmd.macid = 0; /* BSS. */ 1878 cmde.macid = 0; /* BSS. */ 1879 cmd.pwdb = sc->avg_pwdb; 1880 cmde.pwdb = sc->avg_pwdb; 1881 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1882 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1883 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1884 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1885 sizeof(cmd)); 1886 } else { 1887 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1888 sizeof(cmde)); 1889 } 1890 } 1891 1892 /* Do temperature compensation. */ 1893 urtwn_temp_calib(sc); 1894 mutex_exit(&sc->sc_write_mtx); 1895 1896 restart_timer: 1897 if (!sc->sc_dying) { 1898 /* Restart calibration timer. */ 1899 callout_schedule(&sc->sc_calib_to, hz); 1900 } 1901 } 1902 1903 static void 1904 urtwn_next_scan(void *arg) 1905 { 1906 printf ("NNN urtwn_next_scan called....\n"); 1907 #ifdef notyet 1908 struct urtwn_softc *sc = arg; 1909 int s; 1910 1911 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1912 1913 if (sc->sc_dying) 1914 return; 1915 1916 s = splnet(); 1917 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1918 ieee80211_next_scan(&sc->sc_ic); 1919 splx(s); 1920 #endif 1921 } 1922 1923 static void 1924 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1925 { 1926 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1927 ether_sprintf(ni->ni_macaddr))); 1928 1929 /* start with lowest Tx rate */ 1930 ni->ni_txrate = 0; 1931 } 1932 1933 #if OLDSTUFF 1934 static int 1935 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1936 { 1937 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1938 struct urtwn_cmd_newstate cmd; 1939 1940 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1941 device_xname(sc->sc_dev), __func__, 1942 ieee80211_state_name[nstate], nstate, arg)); 1943 1944 callout_stop(&sc->sc_scan_to); 1945 callout_stop(&sc->sc_calib_to); 1946 1947 /* Do it in a process context. */ 1948 cmd.state = nstate; 1949 cmd.arg = arg; 1950 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1951 return 0; 1952 } 1953 1954 static void 1955 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1956 { 1957 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1958 struct urtwn_cmd_newstate *cmd = arg; 1959 struct ieee80211com *ic = &sc->sc_ic; 1960 struct ieee80211_node *ni; 1961 enum ieee80211_state ostate = vap->iv_state; 1962 enum ieee80211_state nstate = cmd->state; 1963 uint32_t reg; 1964 uint8_t sifs_time, msr; 1965 int s; 1966 1967 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1968 device_xname(sc->sc_dev), __func__, 1969 ieee80211_state_name[ostate], ostate, 1970 ieee80211_state_name[nstate], nstate)); 1971 1972 s = splnet(); 1973 mutex_enter(&sc->sc_write_mtx); 1974 1975 callout_stop(&sc->sc_scan_to); 1976 callout_stop(&sc->sc_calib_to); 1977 1978 switch (ostate) { 1979 case IEEE80211_S_INIT: 1980 break; 1981 1982 case IEEE80211_S_SCAN: 1983 if (nstate != IEEE80211_S_SCAN) { 1984 /* 1985 * End of scanning 1986 */ 1987 /* flush 4-AC Queue after site_survey */ 1988 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1989 1990 /* Allow Rx from our BSSID only. */ 1991 urtwn_write_4(sc, R92C_RCR, 1992 urtwn_read_4(sc, R92C_RCR) | 1993 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1994 } 1995 break; 1996 1997 case IEEE80211_S_AUTH: 1998 case IEEE80211_S_ASSOC: 1999 break; 2000 2001 case IEEE80211_S_RUN: 2002 /* Turn link LED off. */ 2003 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2004 2005 /* Set media status to 'No Link'. */ 2006 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2007 2008 /* Stop Rx of data frames. */ 2009 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2010 2011 /* Reset TSF. */ 2012 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2013 2014 /* Disable TSF synchronization. */ 2015 urtwn_write_1(sc, R92C_BCN_CTRL, 2016 urtwn_read_1(sc, R92C_BCN_CTRL) | 2017 R92C_BCN_CTRL_DIS_TSF_UDT0); 2018 2019 /* Back to 20MHz mode */ 2020 urtwn_set_chan(sc, ic->ic_curchan, 2021 IEEE80211_HTINFO_2NDCHAN_NONE); 2022 2023 if (ic->ic_opmode == IEEE80211_M_IBSS || 2024 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2025 /* Stop BCN */ 2026 urtwn_write_1(sc, R92C_BCN_CTRL, 2027 urtwn_read_1(sc, R92C_BCN_CTRL) & 2028 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2029 } 2030 2031 /* Reset EDCA parameters. */ 2032 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2033 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2034 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2035 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2036 2037 /* flush all cam entries */ 2038 urtwn_cam_init(sc); 2039 break; 2040 case IEEE80211_S_CAC: 2041 case IEEE80211_S_CSA: 2042 case IEEE80211_S_SLEEP: 2043 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2044 /* NNN what do we do in these states? XXX */ 2045 break; 2046 } 2047 2048 switch (nstate) { 2049 case IEEE80211_S_INIT: 2050 /* Turn link LED off. */ 2051 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2052 break; 2053 2054 case IEEE80211_S_SCAN: 2055 if (ostate != IEEE80211_S_SCAN) { 2056 /* 2057 * Begin of scanning 2058 */ 2059 2060 /* Set gain for scanning. */ 2061 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2062 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2063 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2064 2065 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2066 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2067 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2068 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2069 } 2070 2071 /* Set media status to 'No Link'. */ 2072 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2073 2074 /* Allow Rx from any BSSID. */ 2075 urtwn_write_4(sc, R92C_RCR, 2076 urtwn_read_4(sc, R92C_RCR) & 2077 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2078 2079 /* Stop Rx of data frames. */ 2080 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2081 2082 /* Disable update TSF */ 2083 urtwn_write_1(sc, R92C_BCN_CTRL, 2084 urtwn_read_1(sc, R92C_BCN_CTRL) | 2085 R92C_BCN_CTRL_DIS_TSF_UDT0); 2086 } 2087 2088 /* Make link LED blink during scan. */ 2089 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2090 2091 /* Pause AC Tx queues. */ 2092 urtwn_write_1(sc, R92C_TXPAUSE, 2093 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2094 2095 urtwn_set_chan(sc, ic->ic_curchan, 2096 IEEE80211_HTINFO_2NDCHAN_NONE); 2097 2098 /* Start periodic scan. */ 2099 if (!sc->sc_dying) 2100 callout_schedule(&sc->sc_scan_to, hz / 5); 2101 break; 2102 2103 case IEEE80211_S_AUTH: 2104 /* Set initial gain under link. */ 2105 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2106 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2107 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2108 2109 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2110 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2111 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2112 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2113 } 2114 2115 /* Set media status to 'No Link'. */ 2116 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2117 2118 /* Allow Rx from any BSSID. */ 2119 urtwn_write_4(sc, R92C_RCR, 2120 urtwn_read_4(sc, R92C_RCR) & 2121 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2122 2123 urtwn_set_chan(sc, ic->ic_curchan, 2124 IEEE80211_HTINFO_2NDCHAN_NONE); 2125 break; 2126 2127 case IEEE80211_S_ASSOC: 2128 break; 2129 2130 case IEEE80211_S_RUN: 2131 ni = vap->iv_bss; 2132 2133 /* XXX: Set 20MHz mode */ 2134 urtwn_set_chan(sc, ic->ic_curchan, 2135 IEEE80211_HTINFO_2NDCHAN_NONE); 2136 2137 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2138 /* Back to 20MHz mode */ 2139 urtwn_set_chan(sc, ic->ic_curchan, 2140 IEEE80211_HTINFO_2NDCHAN_NONE); 2141 2142 /* Set media status to 'No Link'. */ 2143 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2144 2145 /* Enable Rx of data frames. */ 2146 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2147 2148 /* Allow Rx from any BSSID. */ 2149 urtwn_write_4(sc, R92C_RCR, 2150 urtwn_read_4(sc, R92C_RCR) & 2151 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2152 2153 /* Accept Rx data/control/management frames */ 2154 urtwn_write_4(sc, R92C_RCR, 2155 urtwn_read_4(sc, R92C_RCR) | 2156 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2157 2158 /* Turn link LED on. */ 2159 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2160 break; 2161 } 2162 2163 /* Set media status to 'Associated'. */ 2164 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2165 2166 /* Set BSSID. */ 2167 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2168 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2169 2170 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2171 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2172 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2173 /* 802.11b/g */ 2174 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2175 } else /* IEEE_MODE_11NG */ 2176 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2177 2178 /* Enable Rx of data frames. */ 2179 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2180 2181 /* Set beacon interval. */ 2182 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2183 2184 msr = urtwn_read_1(sc, R92C_MSR); 2185 msr &= R92C_MSR_MASK; 2186 switch (ic->ic_opmode) { 2187 case IEEE80211_M_STA: 2188 /* Allow Rx from our BSSID only. */ 2189 urtwn_write_4(sc, R92C_RCR, 2190 urtwn_read_4(sc, R92C_RCR) | 2191 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2192 2193 /* Enable TSF synchronization. */ 2194 urtwn_tsf_sync_enable(sc); 2195 2196 msr |= R92C_MSR_INFRA; 2197 break; 2198 case IEEE80211_M_HOSTAP: 2199 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2200 2201 /* Allow Rx from any BSSID. */ 2202 urtwn_write_4(sc, R92C_RCR, 2203 urtwn_read_4(sc, R92C_RCR) & 2204 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2205 2206 /* Reset TSF timer to zero. */ 2207 reg = urtwn_read_4(sc, R92C_TCR); 2208 reg &= ~0x01; 2209 urtwn_write_4(sc, R92C_TCR, reg); 2210 reg |= 0x01; 2211 urtwn_write_4(sc, R92C_TCR, reg); 2212 2213 msr |= R92C_MSR_AP; 2214 break; 2215 default: 2216 msr |= R92C_MSR_ADHOC; 2217 break; 2218 } 2219 urtwn_write_1(sc, R92C_MSR, msr); 2220 2221 sifs_time = 10; 2222 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2223 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2224 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2225 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2226 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2227 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2228 2229 /* Initialize rate adaptation. */ 2230 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2231 ISSET(sc->chip, URTWN_CHIP_92EU)) 2232 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2233 else 2234 urtwn_ra_init(vap); 2235 2236 /* Turn link LED on. */ 2237 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2238 2239 /* Reset average RSSI. */ 2240 sc->avg_pwdb = -1; 2241 2242 /* Reset temperature calibration state machine. */ 2243 sc->thcal_state = 0; 2244 sc->thcal_lctemp = 0; 2245 2246 /* Start periodic calibration. */ 2247 if (!sc->sc_dying) 2248 callout_schedule(&sc->sc_calib_to, hz); 2249 break; 2250 case IEEE80211_S_CAC: 2251 case IEEE80211_S_CSA: 2252 case IEEE80211_S_SLEEP: 2253 /* NNN what do we do in these states? XXX */ 2254 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2255 break; 2256 } 2257 /* newstate functions expect the ic to be locked. */ 2258 IEEE80211_LOCK(ic); 2259 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2260 IEEE80211_UNLOCK(ic); 2261 2262 mutex_exit(&sc->sc_write_mtx); 2263 splx(s); 2264 } 2265 #endif 2266 2267 static int 2268 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2269 { 2270 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2271 struct ieee80211com *ic = &sc->sc_ic; 2272 struct ieee80211_node *ni; 2273 enum ieee80211_state ostate = vap->iv_state; 2274 uint32_t reg; 2275 uint8_t sifs_time, msr; 2276 int s; 2277 int error; 2278 2279 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2280 device_xname(sc->sc_dev), __func__, 2281 ieee80211_state_name[ostate], ostate, 2282 ieee80211_state_name[nstate], nstate)); 2283 2284 s = splnet(); 2285 mutex_enter(&sc->sc_write_mtx); 2286 2287 callout_stop(&sc->sc_scan_to); 2288 callout_stop(&sc->sc_calib_to); 2289 2290 switch (ostate) { 2291 case IEEE80211_S_INIT: 2292 break; 2293 2294 case IEEE80211_S_SCAN: 2295 if (nstate != IEEE80211_S_SCAN) { 2296 /* 2297 * End of scanning 2298 */ 2299 /* flush 4-AC Queue after site_survey */ 2300 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2301 2302 /* Allow Rx from our BSSID only. */ 2303 urtwn_write_4(sc, R92C_RCR, 2304 urtwn_read_4(sc, R92C_RCR) | 2305 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2306 } 2307 break; 2308 2309 case IEEE80211_S_AUTH: 2310 case IEEE80211_S_ASSOC: 2311 break; 2312 2313 case IEEE80211_S_RUN: 2314 /* Turn link LED off. */ 2315 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2316 2317 /* Set media status to 'No Link'. */ 2318 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2319 2320 /* Stop Rx of data frames. */ 2321 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2322 2323 /* Reset TSF. */ 2324 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2325 2326 /* Disable TSF synchronization. */ 2327 urtwn_write_1(sc, R92C_BCN_CTRL, 2328 urtwn_read_1(sc, R92C_BCN_CTRL) | 2329 R92C_BCN_CTRL_DIS_TSF_UDT0); 2330 2331 /* Back to 20MHz mode */ 2332 urtwn_set_chan(sc, ic->ic_curchan, 2333 IEEE80211_HTINFO_2NDCHAN_NONE); 2334 2335 if (ic->ic_opmode == IEEE80211_M_IBSS || 2336 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2337 /* Stop BCN */ 2338 urtwn_write_1(sc, R92C_BCN_CTRL, 2339 urtwn_read_1(sc, R92C_BCN_CTRL) & 2340 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2341 } 2342 2343 /* Reset EDCA parameters. */ 2344 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2345 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2346 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2347 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2348 2349 /* flush all cam entries */ 2350 urtwn_cam_init(sc); 2351 break; 2352 case IEEE80211_S_CAC: 2353 case IEEE80211_S_CSA: 2354 case IEEE80211_S_SLEEP: 2355 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2356 /* NNN what do we do in these states? XXX */ 2357 break; 2358 } 2359 2360 switch (nstate) { 2361 case IEEE80211_S_INIT: 2362 /* Turn link LED off. */ 2363 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2364 break; 2365 2366 case IEEE80211_S_SCAN: 2367 if (ostate != IEEE80211_S_SCAN) { 2368 /* 2369 * Begin of scanning 2370 */ 2371 2372 /* Set gain for scanning. */ 2373 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2374 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2375 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2376 2377 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2378 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2379 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2380 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2381 } 2382 2383 /* Set media status to 'No Link'. */ 2384 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2385 2386 /* Allow Rx from any BSSID. */ 2387 urtwn_write_4(sc, R92C_RCR, 2388 urtwn_read_4(sc, R92C_RCR) & 2389 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2390 2391 /* Stop Rx of data frames. */ 2392 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2393 2394 /* Disable update TSF */ 2395 urtwn_write_1(sc, R92C_BCN_CTRL, 2396 urtwn_read_1(sc, R92C_BCN_CTRL) | 2397 R92C_BCN_CTRL_DIS_TSF_UDT0); 2398 } 2399 2400 /* Make link LED blink during scan. */ 2401 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2402 2403 /* Pause AC Tx queues. */ 2404 urtwn_write_1(sc, R92C_TXPAUSE, 2405 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2406 2407 urtwn_set_chan(sc, ic->ic_curchan, 2408 IEEE80211_HTINFO_2NDCHAN_NONE); 2409 2410 /* Start periodic scan. */ 2411 if (!sc->sc_dying) 2412 callout_schedule(&sc->sc_scan_to, hz / 5); 2413 break; 2414 2415 case IEEE80211_S_AUTH: 2416 /* Set initial gain under link. */ 2417 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2418 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2419 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2420 2421 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2422 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2423 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2424 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2425 } 2426 2427 /* Set media status to 'No Link'. */ 2428 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2429 2430 /* Allow Rx from any BSSID. */ 2431 urtwn_write_4(sc, R92C_RCR, 2432 urtwn_read_4(sc, R92C_RCR) & 2433 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2434 2435 urtwn_set_chan(sc, ic->ic_curchan, 2436 IEEE80211_HTINFO_2NDCHAN_NONE); 2437 break; 2438 2439 case IEEE80211_S_ASSOC: 2440 break; 2441 2442 case IEEE80211_S_RUN: 2443 ni = vap->iv_bss; 2444 2445 /* XXX: Set 20MHz mode */ 2446 urtwn_set_chan(sc, ic->ic_curchan, 2447 IEEE80211_HTINFO_2NDCHAN_NONE); 2448 2449 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2450 /* Back to 20MHz mode */ 2451 urtwn_set_chan(sc, ic->ic_curchan, 2452 IEEE80211_HTINFO_2NDCHAN_NONE); 2453 2454 /* Set media status to 'No Link'. */ 2455 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2456 2457 /* Enable Rx of data frames. */ 2458 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2459 2460 /* Allow Rx from any BSSID. */ 2461 urtwn_write_4(sc, R92C_RCR, 2462 urtwn_read_4(sc, R92C_RCR) & 2463 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2464 2465 /* Accept Rx data/control/management frames */ 2466 urtwn_write_4(sc, R92C_RCR, 2467 urtwn_read_4(sc, R92C_RCR) | 2468 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2469 2470 /* Turn link LED on. */ 2471 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2472 break; 2473 } 2474 2475 /* Set media status to 'Associated'. */ 2476 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2477 2478 /* Set BSSID. */ 2479 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2480 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2481 2482 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2483 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2484 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2485 /* 802.11b/g */ 2486 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2487 } else /* IEEE_MODE_11NG */ 2488 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2489 2490 /* Enable Rx of data frames. */ 2491 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2492 2493 /* Set beacon interval. */ 2494 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2495 2496 msr = urtwn_read_1(sc, R92C_MSR); 2497 msr &= R92C_MSR_MASK; 2498 switch (ic->ic_opmode) { 2499 case IEEE80211_M_STA: 2500 /* Allow Rx from our BSSID only. */ 2501 urtwn_write_4(sc, R92C_RCR, 2502 urtwn_read_4(sc, R92C_RCR) | 2503 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2504 2505 /* Enable TSF synchronization. */ 2506 urtwn_tsf_sync_enable(sc); 2507 2508 msr |= R92C_MSR_INFRA; 2509 break; 2510 case IEEE80211_M_HOSTAP: 2511 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2512 2513 /* Allow Rx from any BSSID. */ 2514 urtwn_write_4(sc, R92C_RCR, 2515 urtwn_read_4(sc, R92C_RCR) & 2516 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2517 2518 /* Reset TSF timer to zero. */ 2519 reg = urtwn_read_4(sc, R92C_TCR); 2520 reg &= ~0x01; 2521 urtwn_write_4(sc, R92C_TCR, reg); 2522 reg |= 0x01; 2523 urtwn_write_4(sc, R92C_TCR, reg); 2524 2525 msr |= R92C_MSR_AP; 2526 break; 2527 default: 2528 msr |= R92C_MSR_ADHOC; 2529 break; 2530 } 2531 urtwn_write_1(sc, R92C_MSR, msr); 2532 2533 sifs_time = 10; 2534 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2535 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2536 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2537 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2538 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2539 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2540 2541 /* Initialize rate adaptation. */ 2542 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2543 ISSET(sc->chip, URTWN_CHIP_92EU)) 2544 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2545 else 2546 urtwn_ra_init(vap); 2547 2548 /* Turn link LED on. */ 2549 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2550 2551 /* Reset average RSSI. */ 2552 sc->avg_pwdb = -1; 2553 2554 /* Reset temperature calibration state machine. */ 2555 sc->thcal_state = 0; 2556 sc->thcal_lctemp = 0; 2557 2558 /* Start periodic calibration. */ 2559 if (!sc->sc_dying) 2560 callout_schedule(&sc->sc_calib_to, hz); 2561 break; 2562 case IEEE80211_S_CAC: 2563 case IEEE80211_S_CSA: 2564 case IEEE80211_S_SLEEP: 2565 /* NNN what do we do in these states? XXX */ 2566 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2567 break; 2568 } 2569 mutex_exit(&sc->sc_write_mtx); 2570 2571 /* newstate functions expect the ic to be locked. */ 2572 error = (*sc->sc_newstate)(vap, nstate, arg); 2573 2574 splx(s); 2575 return error; 2576 } 2577 2578 static int 2579 urtwn_wme_update(struct ieee80211com *ic) 2580 { 2581 struct urtwn_softc *sc = ic->ic_softc; 2582 2583 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2584 2585 /* don't override default WME values if WME is not actually enabled */ 2586 if (!(ic->ic_flags & IEEE80211_F_WME)) 2587 return 0; 2588 2589 /* Do it in a process context. */ 2590 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2591 return 0; 2592 } 2593 2594 static void 2595 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2596 { 2597 static const uint16_t ac2reg[WME_NUM_AC] = { 2598 R92C_EDCA_BE_PARAM, 2599 R92C_EDCA_BK_PARAM, 2600 R92C_EDCA_VI_PARAM, 2601 R92C_EDCA_VO_PARAM 2602 }; 2603 struct ieee80211com *ic = &sc->sc_ic; 2604 const struct wmeParams *wmep; 2605 int ac, aifs, slottime; 2606 int s; 2607 2608 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2609 __func__)); 2610 2611 s = splnet(); 2612 mutex_enter(&sc->sc_write_mtx); 2613 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2614 for (ac = 0; ac < WME_NUM_AC; ac++) { 2615 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2616 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2617 aifs = wmep->wmep_aifsn * slottime + 10; 2618 urtwn_write_4(sc, ac2reg[ac], 2619 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2620 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2621 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2622 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2623 } 2624 mutex_exit(&sc->sc_write_mtx); 2625 splx(s); 2626 } 2627 2628 static void 2629 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2630 { 2631 int pwdb; 2632 2633 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2634 device_xname(sc->sc_dev), __func__, rate, rssi)); 2635 2636 /* Convert antenna signal to percentage. */ 2637 if (rssi <= -100 || rssi >= 20) 2638 pwdb = 0; 2639 else if (rssi >= 0) 2640 pwdb = 100; 2641 else 2642 pwdb = 100 + rssi; 2643 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2644 if (rate <= 3) { 2645 /* CCK gain is smaller than OFDM/MCS gain. */ 2646 pwdb += 6; 2647 if (pwdb > 100) 2648 pwdb = 100; 2649 if (pwdb <= 14) 2650 pwdb -= 4; 2651 else if (pwdb <= 26) 2652 pwdb -= 8; 2653 else if (pwdb <= 34) 2654 pwdb -= 6; 2655 else if (pwdb <= 42) 2656 pwdb -= 2; 2657 } 2658 } 2659 if (sc->avg_pwdb == -1) /* Init. */ 2660 sc->avg_pwdb = pwdb; 2661 else if (sc->avg_pwdb < pwdb) 2662 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2663 else 2664 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2665 2666 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2667 device_xname(sc->sc_dev), __func__, 2668 rate, rssi, pwdb, sc->avg_pwdb)); 2669 } 2670 2671 static int8_t 2672 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2673 { 2674 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2675 struct r92c_rx_phystat *phy; 2676 struct r92c_rx_cck *cck; 2677 uint8_t rpt; 2678 int8_t rssi; 2679 2680 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2681 __func__, rate)); 2682 2683 if (rate <= 3) { 2684 cck = (struct r92c_rx_cck *)physt; 2685 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2686 rpt = (cck->agc_rpt >> 5) & 0x3; 2687 rssi = (cck->agc_rpt & 0x1f) << 1; 2688 } else { 2689 rpt = (cck->agc_rpt >> 6) & 0x3; 2690 rssi = cck->agc_rpt & 0x3e; 2691 } 2692 rssi = cckoff[rpt] - rssi; 2693 } else { /* OFDM/HT. */ 2694 phy = (struct r92c_rx_phystat *)physt; 2695 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2696 } 2697 return rssi; 2698 } 2699 2700 static int8_t 2701 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2702 { 2703 struct r92c_rx_phystat *phy; 2704 struct r88e_rx_cck *cck; 2705 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2706 int8_t rssi; 2707 2708 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2709 __func__, rate)); 2710 2711 rssi = 0; 2712 if (rate <= 3) { 2713 cck = (struct r88e_rx_cck *)physt; 2714 cck_agc_rpt = cck->agc_rpt; 2715 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2716 vga_idx = cck_agc_rpt & 0x1f; 2717 switch (lna_idx) { 2718 case 7: 2719 if (vga_idx <= 27) 2720 rssi = -100 + 2* (27 - vga_idx); 2721 else 2722 rssi = -100; 2723 break; 2724 case 6: 2725 rssi = -48 + 2 * (2 - vga_idx); 2726 break; 2727 case 5: 2728 rssi = -42 + 2 * (7 - vga_idx); 2729 break; 2730 case 4: 2731 rssi = -36 + 2 * (7 - vga_idx); 2732 break; 2733 case 3: 2734 rssi = -24 + 2 * (7 - vga_idx); 2735 break; 2736 case 2: 2737 rssi = -12 + 2 * (5 - vga_idx); 2738 break; 2739 case 1: 2740 rssi = 8 - (2 * vga_idx); 2741 break; 2742 case 0: 2743 rssi = 14 - (2 * vga_idx); 2744 break; 2745 } 2746 rssi += 6; 2747 } else { /* OFDM/HT. */ 2748 phy = (struct r92c_rx_phystat *)physt; 2749 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2750 } 2751 return rssi; 2752 } 2753 2754 static void 2755 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2756 { 2757 struct ieee80211com *ic = &sc->sc_ic; 2758 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2759 struct ifnet *ifp = vap->iv_ifp; 2760 struct ieee80211_frame *wh; 2761 struct ieee80211_node *ni; 2762 struct r92c_rx_desc_usb *stat; 2763 uint32_t rxdw0, rxdw3; 2764 struct mbuf *m; 2765 uint8_t rate; 2766 int8_t rssi = 0; 2767 int s, infosz; 2768 2769 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2770 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2771 2772 stat = (struct r92c_rx_desc_usb *)buf; 2773 rxdw0 = le32toh(stat->rxdw0); 2774 rxdw3 = le32toh(stat->rxdw3); 2775 2776 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2777 /* 2778 * This should not happen since we setup our Rx filter 2779 * to not receive these frames. 2780 */ 2781 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2782 device_xname(sc->sc_dev), __func__)); 2783 if_statinc(ifp, if_ierrors); 2784 return; 2785 } 2786 2787 /* 2788 * XXX: This will drop most control packets. Do we really 2789 * want this in IEEE80211_M_MONITOR mode? 2790 */ 2791 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2792 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2793 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2794 device_xname(sc->sc_dev), __func__, pktlen)); 2795 vap->iv_stats.is_rx_tooshort++; 2796 if_statinc(ifp,if_ierrors); 2797 return; 2798 } 2799 if (__predict_false(pktlen > MCLBYTES)) { 2800 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2801 device_xname(sc->sc_dev), __func__, pktlen)); 2802 if_statinc(ifp, if_ierrors); 2803 return; 2804 } 2805 2806 rate = MS(rxdw3, R92C_RXDW3_RATE); 2807 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2808 2809 /* Get RSSI from PHY status descriptor if present. */ 2810 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2811 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2812 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2813 else 2814 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2815 /* Update our average RSSI. */ 2816 urtwn_update_avgrssi(sc, rate, rssi); 2817 } 2818 2819 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2820 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2821 2822 MGETHDR(m, M_DONTWAIT, MT_DATA); 2823 if (__predict_false(m == NULL)) { 2824 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2825 vap->iv_stats.is_rx_nobuf++; 2826 if_statinc(ifp, if_ierrors); 2827 return; 2828 } 2829 if (pktlen > (int)MHLEN) { 2830 MCLGET(m, M_DONTWAIT); 2831 if (__predict_false(!(m->m_flags & M_EXT))) { 2832 aprint_error_dev(sc->sc_dev, 2833 "couldn't allocate rx mbuf cluster\n"); 2834 m_freem(m); 2835 vap->iv_stats.is_rx_nobuf++; 2836 if_statinc(ifp, if_ierrors); 2837 return; 2838 } 2839 } 2840 2841 /* Finalize mbuf. */ 2842 m_set_rcvif(m, ifp); 2843 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2844 2845 memcpy(mtod(m, uint8_t *), wh, pktlen); 2846 m->m_pkthdr.len = m->m_len = pktlen; 2847 2848 s = splnet(); 2849 if (__predict_false(sc->sc_drvbpf != NULL)) { 2850 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2851 2852 tap->wr_flags = 0; 2853 if (!(rxdw3 & R92C_RXDW3_HT)) { 2854 switch (rate) { 2855 /* CCK. */ 2856 case 0: tap->wr_rate = 2; break; 2857 case 1: tap->wr_rate = 4; break; 2858 case 2: tap->wr_rate = 11; break; 2859 case 3: tap->wr_rate = 22; break; 2860 /* OFDM. */ 2861 case 4: tap->wr_rate = 12; break; 2862 case 5: tap->wr_rate = 18; break; 2863 case 6: tap->wr_rate = 24; break; 2864 case 7: tap->wr_rate = 36; break; 2865 case 8: tap->wr_rate = 48; break; 2866 case 9: tap->wr_rate = 72; break; 2867 case 10: tap->wr_rate = 96; break; 2868 case 11: tap->wr_rate = 108; break; 2869 } 2870 } else if (rate >= 12) { /* MCS0~15. */ 2871 /* Bit 7 set means HT MCS instead of rate. */ 2872 tap->wr_rate = 0x80 | (rate - 12); 2873 } 2874 tap->wr_dbm_antsignal = rssi; 2875 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2876 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2877 2878 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2879 } 2880 2881 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2882 2883 if (ni != NULL) { 2884 if (ni->ni_vap != NULL) { 2885 2886 } else { 2887 splx(s); 2888 return; 2889 } 2890 /* push the frame up to the 802.11 stack */ 2891 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2892 ieee80211_input(ni, m, rssi+90, 0); 2893 2894 /* Node is no longer needed. */ 2895 ieee80211_free_node(ni); 2896 2897 } else { 2898 2899 /* No node found ... process differently. */ 2900 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2901 } 2902 2903 splx(s); 2904 } 2905 2906 static void 2907 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2908 { 2909 struct urtwn_rx_data *data = priv; 2910 struct urtwn_softc *sc = data->sc; 2911 struct r92c_rx_desc_usb *stat; 2912 size_t pidx = data->pidx; 2913 uint32_t rxdw0; 2914 uint8_t *buf; 2915 int len, totlen, pktlen, infosz, npkts; 2916 2917 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2918 device_xname(sc->sc_dev), __func__, status)); 2919 2920 mutex_enter(&sc->sc_rx_mtx); 2921 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2922 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2923 /* Put this Rx buffer back to our free list. */ 2924 mutex_exit(&sc->sc_rx_mtx); 2925 2926 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2927 if (status == USBD_STALLED) 2928 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2929 else if (status != USBD_CANCELLED) 2930 goto resubmit; 2931 return; 2932 } 2933 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2934 2935 if (__predict_false(len < (int)sizeof(*stat))) { 2936 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2937 device_xname(sc->sc_dev), __func__, len)); 2938 goto resubmit; 2939 } 2940 buf = data->buf; 2941 2942 /* Get the number of encapsulated frames. */ 2943 stat = (struct r92c_rx_desc_usb *)buf; 2944 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2945 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2946 else 2947 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2948 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2949 device_xname(sc->sc_dev), __func__, npkts)); 2950 2951 /* Process all of them. */ 2952 while (npkts-- > 0) { 2953 if (__predict_false(len < (int)sizeof(*stat))) { 2954 DPRINTFN(DBG_RX, 2955 ("%s: %s: len(%d) is short than header\n", 2956 device_xname(sc->sc_dev), __func__, len)); 2957 break; 2958 } 2959 stat = (struct r92c_rx_desc_usb *)buf; 2960 rxdw0 = le32toh(stat->rxdw0); 2961 2962 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2963 if (__predict_false(pktlen == 0)) { 2964 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2965 device_xname(sc->sc_dev), __func__)); 2966 break; 2967 } 2968 2969 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2970 2971 /* Make sure everything fits in xfer. */ 2972 totlen = sizeof(*stat) + infosz + pktlen; 2973 if (__predict_false(totlen > len)) { 2974 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2975 device_xname(sc->sc_dev), __func__, totlen, 2976 (int)sizeof(*stat), infosz, pktlen, len)); 2977 break; 2978 } 2979 2980 /* Process 802.11 frame. */ 2981 urtwn_rx_frame(sc, buf, pktlen); 2982 2983 /* Next chunk is 128-byte aligned. */ 2984 totlen = roundup2(totlen, 128); 2985 buf += totlen; 2986 len -= totlen; 2987 } 2988 2989 resubmit: 2990 /* Setup a new transfer. */ 2991 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2992 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2993 (void)usbd_transfer(xfer); 2994 } 2995 2996 static void 2997 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2998 { 2999 struct urtwn_tx_data *data = priv; 3000 struct urtwn_softc *sc = data->sc; 3001 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 3002 size_t pidx = data->pidx; 3003 int s; 3004 3005 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 3006 device_xname(sc->sc_dev), __func__, status)); 3007 3008 mutex_enter(&sc->sc_tx_mtx); 3009 /* Put this Tx buffer back to our free list. */ 3010 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 3011 mutex_exit(&sc->sc_tx_mtx); 3012 3013 s = splnet(); 3014 sc->tx_timer = 0; 3015 ifp->if_flags &= ~IFF_OACTIVE; 3016 3017 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 3018 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 3019 if (status == USBD_STALLED) { 3020 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 3021 usbd_clear_endpoint_stall_async(pipe); 3022 } 3023 printf("ERROR1\n"); 3024 if_statinc(ifp, if_oerrors); 3025 } 3026 splx(s); 3027 return; 3028 } 3029 3030 if_statinc(ifp, if_opackets); 3031 urtwn_start(ifp); 3032 splx(s); 3033 3034 } 3035 3036 static int 3037 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3038 struct urtwn_tx_data *data) 3039 { 3040 struct ieee80211com *ic = &sc->sc_ic; 3041 struct ieee80211_frame *wh; 3042 struct ieee80211_key *k = NULL; 3043 struct r92c_tx_desc_usb *txd; 3044 size_t i, padsize, xferlen, txd_len; 3045 uint16_t seq, sum; 3046 uint8_t raid, type, tid; 3047 int s, hasqos, error; 3048 3049 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3050 3051 wh = mtod(m, struct ieee80211_frame *); 3052 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3053 txd_len = sizeof(*txd); 3054 3055 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3056 txd_len = 32; 3057 3058 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3059 k = ieee80211_crypto_encap(ni, m); 3060 if (k == NULL) 3061 return ENOBUFS; 3062 3063 /* packet header may have moved, reset our local pointer */ 3064 wh = mtod(m, struct ieee80211_frame *); 3065 } 3066 3067 if (__predict_false(sc->sc_drvbpf != NULL)) { 3068 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3069 3070 tap->wt_flags = 0; 3071 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3072 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3073 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3074 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3075 3076 /* XXX: set tap->wt_rate? */ 3077 3078 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3079 } 3080 3081 /* non-qos data frames */ 3082 tid = R92C_TXDW1_QSEL_BE; 3083 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3084 /* data frames in 11n mode */ 3085 struct ieee80211_qosframe *qwh = (void *)wh; 3086 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3087 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3088 tid = R92C_TXDW1_QSEL_MGNT; 3089 } 3090 3091 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3092 padsize = 8; 3093 else 3094 padsize = 0; 3095 3096 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3097 padsize = 0; 3098 3099 /* Fill Tx descriptor. */ 3100 txd = (struct r92c_tx_desc_usb *)data->buf; 3101 memset(txd, 0, txd_len + padsize); 3102 3103 txd->txdw0 |= htole32( 3104 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3105 SM(R92C_TXDW0_OFFSET, txd_len)); 3106 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3107 txd->txdw0 |= htole32( 3108 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3109 } 3110 3111 if (ic->ic_curmode == IEEE80211_MODE_11NG) 3112 txd->txdw5 |= htole32(R92C_TXDW5_SGI); 3113 3114 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3115 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3116 3117 /* fix pad field */ 3118 if (padsize > 0) { 3119 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3120 device_xname(sc->sc_dev), __func__, padsize)); 3121 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3122 } 3123 3124 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3125 type == IEEE80211_FC0_TYPE_DATA) { 3126 if (ic->ic_curmode == IEEE80211_MODE_11B) 3127 raid = R92C_RAID_11B; 3128 else if (ic->ic_curmode == IEEE80211_MODE_11G) 3129 raid = R92C_RAID_11BG; 3130 else /* IEEE80211_MODE_11NG */ 3131 raid = R92C_RAID_11GN; 3132 DPRINTFN(DBG_TX, 3133 ("%s: %s: data packet: tid=%d, raid=%d\n", 3134 device_xname(sc->sc_dev), __func__, tid, raid)); 3135 3136 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3137 txd->txdw1 |= htole32( 3138 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3139 SM(R92C_TXDW1_QSEL, tid) | 3140 SM(R92C_TXDW1_RAID, raid) | 3141 R92C_TXDW1_AGGBK); 3142 } else 3143 txd->txdw1 |= htole32( 3144 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3145 SM(R92C_TXDW1_QSEL, tid) | 3146 SM(R92C_TXDW1_RAID, raid) | 3147 R92C_TXDW1_AGGBK); 3148 3149 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3150 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3151 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3152 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3153 3154 if (hasqos) { 3155 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3156 } 3157 3158 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3159 /* for 11g */ 3160 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3161 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3162 R92C_TXDW4_HWRTSEN); 3163 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3164 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3165 R92C_TXDW4_HWRTSEN); 3166 } 3167 } 3168 /* Send RTS at OFDM24. */ 3169 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3170 txd->txdw5 |= htole32(0x0001ff00); 3171 /* Send data at OFDM54. */ 3172 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3173 txd->txdw5 |= htole32(0x13 & 0x3f); 3174 else 3175 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3176 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3177 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3178 device_xname(sc->sc_dev), __func__)); 3179 txd->txdw1 |= htole32( 3180 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3181 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3182 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3183 3184 /* Force CCK1. */ 3185 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3186 /* Use 1Mbps */ 3187 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3188 } else { 3189 /* broadcast or multicast packets */ 3190 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3191 device_xname(sc->sc_dev), __func__)); 3192 txd->txdw1 |= htole32( 3193 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3194 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3195 3196 /* Force CCK1. */ 3197 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3198 /* Use 1Mbps */ 3199 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3200 } 3201 /* Set sequence number */ 3202 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3203 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3204 txd->txdseq |= htole16(seq); 3205 3206 if (!hasqos) { 3207 /* Use HW sequence numbering for non-QoS frames. */ 3208 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3209 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3210 } 3211 } else { 3212 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3213 R92E_HWSEQ_SHIFT); 3214 if (!hasqos) { 3215 /* Use HW sequence numbering for non-QoS frames. */ 3216 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3217 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3218 } 3219 } 3220 3221 /* Compute Tx descriptor checksum. */ 3222 sum = 0; 3223 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3224 sum ^= ((uint16_t *)txd)[i]; 3225 txd->txdsum = sum; /* NB: already little endian. */ 3226 3227 xferlen = txd_len + m->m_pkthdr.len + padsize; 3228 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3229 3230 if (data->xfer == NULL) { 3231 /* NNN Don't crash ... but what is going on! */ 3232 printf ("urtwn_tx: data->xfer is NULL\n"); 3233 m_print(m,"", printf); 3234 return -1; 3235 } 3236 3237 s = splnet(); 3238 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3239 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3240 urtwn_txeof); 3241 error = usbd_transfer(data->xfer); 3242 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3243 error != USBD_IN_PROGRESS)) { 3244 splx(s); 3245 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3246 device_xname(sc->sc_dev), __func__, error)); 3247 return error; 3248 } 3249 splx(s); 3250 return 0; 3251 } 3252 3253 struct urtwn_tx_data * 3254 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3255 { 3256 struct urtwn_tx_data *data = NULL; 3257 3258 mutex_enter(&sc->sc_tx_mtx); 3259 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3260 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3261 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3262 } 3263 mutex_exit(&sc->sc_tx_mtx); 3264 3265 return data; 3266 } 3267 3268 static void 3269 urtwn_start(struct ifnet *ifp) 3270 { 3271 struct ieee80211vap *vap = ifp->if_softc; 3272 struct ieee80211com *ic = vap->iv_ic; 3273 struct urtwn_softc *sc = ic->ic_softc; 3274 struct urtwn_tx_data *data; 3275 struct ether_header *eh; 3276 struct ieee80211_node *ni; 3277 struct mbuf *m; 3278 3279 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3280 3281 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3282 return; 3283 3284 data = NULL; 3285 for (;;) { 3286 /* Send pending management frames first. */ 3287 IF_POLL(&ic->ic_mgtq, m); 3288 if (m != NULL) { 3289 /* Use AC_VO for management frames. */ 3290 3291 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3292 3293 if (data == NULL) { 3294 ifp->if_flags |= IFF_OACTIVE; 3295 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3296 device_xname(sc->sc_dev))); 3297 return; 3298 } 3299 IF_DEQUEUE(&ic->ic_mgtq, m); 3300 ni = M_GETCTX(m, struct ieee80211_node *); 3301 M_CLEARCTX(m); 3302 goto sendit; 3303 } 3304 3305 if (vap->iv_state != IEEE80211_S_RUN) 3306 break; 3307 3308 /* Encapsulate and send data frames. */ 3309 IFQ_POLL(&sc->sc_sendq, m); 3310 if (m == NULL) 3311 break; 3312 3313 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3314 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3315 uint8_t qid = WME_AC_BE; 3316 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3317 /* data frames in 11n mode */ 3318 struct ieee80211_qosframe *qwh = (void *)wh; 3319 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3320 qid = TID_TO_WME_AC(tid); 3321 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3322 qid = WME_AC_VO; 3323 } 3324 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3325 3326 if (data == NULL) { 3327 ifp->if_flags |= IFF_OACTIVE; 3328 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3329 device_xname(sc->sc_dev))); 3330 return; 3331 } 3332 IFQ_DEQUEUE(&sc->sc_sendq, m); 3333 3334 if (m->m_len < (int)sizeof(*eh) && 3335 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3336 printf("ERROR6\n"); 3337 if_statinc(ifp, if_oerrors); 3338 continue; 3339 } 3340 eh = mtod(m, struct ether_header *); 3341 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3342 if (ni == NULL) { 3343 m_freem(m); 3344 printf("ERROR5\n"); 3345 if_statinc(ifp, if_oerrors); 3346 continue; 3347 } 3348 3349 //bpf_mtap(ifp, m, BPF_D_OUT); 3350 3351 sendit: 3352 if (urtwn_tx(sc, m, ni, data) != 0) { 3353 m_freem(m); 3354 ieee80211_free_node(ni); 3355 printf("ERROR3\n"); 3356 if_statinc(ifp, if_oerrors); 3357 continue; 3358 } 3359 m_freem(m); 3360 ieee80211_free_node(ni); 3361 sc->tx_timer = 5; 3362 ifp->if_timer = 1; 3363 } 3364 } 3365 3366 static __unused void 3367 urtwn_watchdog(struct ifnet *ifp) 3368 { 3369 struct ieee80211vap *vap = ifp->if_softc; 3370 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3371 3372 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3373 3374 ifp->if_timer = 0; 3375 3376 if (sc->tx_timer > 0) { 3377 if (--sc->tx_timer == 0) { 3378 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3379 /* urtwn_init(ifp); XXX needs a process context! */ 3380 printf("ERROR2\n"); 3381 if_statinc(ifp, if_oerrors); 3382 return; 3383 } 3384 ifp->if_timer = 1; 3385 } 3386 // ieee80211_watchdog(&sc->sc_ic); 3387 } 3388 3389 /* 3390 * Create a VAP node for use with the urtwn driver. 3391 */ 3392 3393 static struct ieee80211vap * 3394 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3395 int unit, enum ieee80211_opmode opmode, int flags, 3396 const uint8_t bssid[IEEE80211_ADDR_LEN], 3397 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3398 { 3399 struct urtwn_softc *sc = ic->ic_softc; 3400 struct ifnet *ifp; 3401 struct ieee80211vap *vap; 3402 3403 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3404 3405 /* Allow only one VAP for the urtwn driver. */ 3406 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3407 return NULL; 3408 3409 /* Allocate the vap and setup. */ 3410 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3411 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3412 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3413 kmem_free(vap, sizeof(struct ieee80211vap)); 3414 return NULL; 3415 } 3416 3417 /* Local setup */ 3418 vap->iv_reset = urtwn_reset; 3419 3420 ifp = vap->iv_ifp; 3421 if_initialize(ifp); 3422 ifp->if_init = urtwn_init; 3423 ifp->if_ioctl = urtwn_ioctl; 3424 ifp->if_start = urtwn_start; 3425 // ifp->if_watchdog = urtwn_watchdog; NNN 3426 ifp->if_extflags |= IFEF_MPSAFE; 3427 // IFQ_SET_READY(&ifp->if_snd); 3428 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3429 3430 ifp->if_percpuq = if_percpuq_create(ifp); 3431 3432 /* Override state transition machine. */ 3433 /* NNN --- many possible newstate machines ... issue! */ 3434 sc->sc_newstate = vap->iv_newstate; 3435 vap->iv_newstate = urtwn_newstate; 3436 3437 /* Finish setup */ 3438 ieee80211_vap_attach(vap, urtwn_media_change, 3439 ieee80211_media_status, macaddr); 3440 ic->ic_opmode = opmode; 3441 3442 /* Attach the packet filter */ 3443 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3444 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3445 &sc->sc_drvbpf); 3446 3447 return vap; 3448 } 3449 3450 static void 3451 urtwn_vap_delete(struct ieee80211vap *vap) 3452 { 3453 struct ifnet *ifp = vap->iv_ifp; 3454 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3455 3456 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3457 3458 urtwn_stop(ifp, 0); 3459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3460 bpf_detach(ifp); 3461 if_detach(ifp); 3462 kmem_free(vap, sizeof(struct ieee80211vap)); 3463 } 3464 3465 static void 3466 urtwn_parent(struct ieee80211com *ic) 3467 { 3468 struct urtwn_softc *sc __unused = ic->ic_softc; 3469 3470 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3471 3472 /* Not sure what to do here yet. */ 3473 } 3474 3475 static void 3476 urtwn_scan_start(struct ieee80211com *ic) 3477 { 3478 #ifdef URTWN_DEBUG 3479 struct urtwn_softc *sc = ic->ic_softc; 3480 #endif 3481 //uint32_t reg; 3482 //int s; 3483 3484 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3485 3486 /* 3487 * Not sure what to do here yet. Try #1: do what was in the 3488 * state machine. NNN 3489 */ 3490 #if NOTWITHSTATEMACHINEOVERRIDE 3491 /* 3492 * Begin of scanning 3493 */ 3494 3495 s = splnet(); 3496 mutex_enter(&sc->sc_write_mtx); 3497 3498 /* Set gain for scanning. */ 3499 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3500 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3501 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3502 3503 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3504 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3505 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3506 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3507 } 3508 3509 /* Set media status to 'No Link'. */ 3510 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3511 3512 /* Allow Rx from any BSSID. */ 3513 urtwn_write_4(sc, R92C_RCR, 3514 urtwn_read_4(sc, R92C_RCR) & 3515 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3516 3517 /* Stop Rx of data frames. */ 3518 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3519 3520 /* Disable update TSF */ 3521 urtwn_write_1(sc, R92C_BCN_CTRL, 3522 urtwn_read_1(sc, R92C_BCN_CTRL) | 3523 R92C_BCN_CTRL_DIS_TSF_UDT0); 3524 3525 /* Make link LED blink during scan. */ 3526 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3527 3528 /* Pause AC Tx queues. */ 3529 urtwn_write_1(sc, R92C_TXPAUSE, 3530 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3531 3532 urtwn_set_chan(sc, ic->ic_curchan, 3533 IEEE80211_HTINFO_2NDCHAN_NONE); 3534 3535 mutex_exit(&sc->sc_write_mtx); 3536 splx(s); 3537 #endif 3538 } 3539 3540 static void 3541 urtwn_scan_end(struct ieee80211com *ic) 3542 { 3543 #ifdef URTWN_DEBUG 3544 struct urtwn_softc *sc = ic->ic_softc; 3545 #endif 3546 3547 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3548 3549 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3550 /* 3551 * End of scanning 3552 */ 3553 3554 mutex_enter(&sc->sc_write_mtx); 3555 3556 /* flush 4-AC Queue after site_survey */ 3557 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3558 3559 /* Allow Rx from our BSSID only. */ 3560 urtwn_write_4(sc, R92C_RCR, 3561 urtwn_read_4(sc, R92C_RCR) | 3562 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3563 3564 /* Turn link LED off. */ 3565 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3566 3567 mutex_exit(&sc->sc_write_mtx); 3568 #endif 3569 } 3570 3571 static void 3572 urtwn_set_channel(struct ieee80211com *ic) 3573 { 3574 struct urtwn_softc *sc = ic->ic_softc; 3575 3576 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3577 3578 mutex_enter(&sc->sc_write_mtx); 3579 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3580 mutex_exit(&sc->sc_write_mtx); 3581 } 3582 3583 static int 3584 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3585 { 3586 struct urtwn_softc *sc = ic->ic_softc; 3587 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3588 int s; 3589 size_t pktlen = m->m_pkthdr.len; 3590 bool mcast = (m->m_flags & M_MCAST) != 0; 3591 3592 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3593 3594 s = splnet(); 3595 3596 IF_ENQUEUE(&sc->sc_sendq, m); 3597 3598 if_statadd(vap->iv_ifp, if_obytes, pktlen); 3599 if (mcast) 3600 if_statinc(vap->iv_ifp, if_omcasts); 3601 3602 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3603 if_start_lock(vap->iv_ifp); 3604 splx(s); 3605 3606 urtwn_start(vap->iv_ifp); 3607 3608 return 0; 3609 } 3610 3611 #if 0 3612 static int 3613 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3614 #ifdef URTWN_DEBUG 3615 // struct ieee80211vap *vap = ni->ni_vap; 3616 struct ieee80211com *ic = ni->ni_ic; 3617 struct urtwn_softc *sc = ic->ic_softc; 3618 #endif 3619 3620 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3621 3622 /* Don't know what to do right now. */ 3623 return ENOTTY; 3624 } 3625 #endif 3626 3627 3628 static int 3629 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3630 const struct ieee80211_bpf_params *bpfp) 3631 { 3632 struct ieee80211vap *vap = ni->ni_vap; 3633 struct ieee80211com *ic = ni->ni_ic; 3634 struct urtwn_softc *sc = ic->ic_softc; 3635 struct urtwn_tx_data *data; 3636 int error; 3637 3638 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3639 3640 KASSERT(vap != NULL); /* NNN need these? */ 3641 KASSERT(ic != NULL); 3642 KASSERT(sc != NULL); 3643 KASSERT(m != NULL); 3644 3645 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3646 3647 if (data == NULL) { 3648 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3649 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3650 device_xname(sc->sc_dev))); 3651 return ENOBUFS; 3652 } 3653 3654 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3655 3656 error = urtwn_tx(sc, m, ni, data); 3657 if (error != 0) { 3658 printf("ERROR3\n"); 3659 if_statinc(vap->iv_ifp, if_oerrors); 3660 } else { 3661 sc->tx_timer = 5; 3662 vap->iv_ifp->if_timer = 1; 3663 } 3664 m_freem(m); 3665 ieee80211_free_node(ni); 3666 return error; 3667 } 3668 3669 static void 3670 urtwn_getradiocaps(struct ieee80211com *ic, 3671 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3672 { 3673 uint8_t bands[IEEE80211_MODE_BYTES]; 3674 3675 /* 3676 * NNN Should be able to do something based on chip if 3677 * a chip has more bands .... eg. N ... but for the future. 3678 */ 3679 3680 memset(bands, 0, sizeof(bands)); 3681 setbit(bands, IEEE80211_MODE_11B); 3682 setbit(bands, IEEE80211_MODE_11G); 3683 setbit(bands, IEEE80211_MODE_11NG); 3684 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3685 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, IEEE80211_CHAN_HT20 | 3686 IEEE80211_CHAN_HT40U | IEEE80211_CHAN_HT40D); 3687 } 3688 3689 3690 static int 3691 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3692 { 3693 3694 struct ieee80211vap *vap = ifp->if_softc; 3695 struct ieee80211com *ic = vap->iv_ic; 3696 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3697 int s, error = 0; 3698 3699 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3700 device_xname(sc->sc_dev), __func__, cmd, data)); 3701 3702 s = splnet(); 3703 3704 switch (cmd) { 3705 case SIOCSIFFLAGS: 3706 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3707 break; 3708 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3709 case IFF_UP | IFF_RUNNING: 3710 break; 3711 case IFF_UP: 3712 urtwn_init(ifp); 3713 break; 3714 case IFF_RUNNING: 3715 urtwn_stop(ifp, 1); 3716 break; 3717 case 0: 3718 break; 3719 } 3720 break; 3721 3722 case SIOCADDMULTI: 3723 case SIOCDELMULTI: 3724 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3725 /* setup multicast filter, etc */ 3726 error = 0; 3727 } 3728 break; 3729 3730 case SIOCS80211CHANNEL: 3731 /* 3732 * This allows for fast channel switching in monitor mode 3733 * (used by kismet). In IBSS mode, we must explicitly reset 3734 * the interface to generate a new beacon frame. 3735 */ 3736 error = ieee80211_ioctl(ifp, cmd, data); 3737 if (error == ENETRESET && 3738 ic->ic_opmode == IEEE80211_M_MONITOR) { 3739 urtwn_set_chan(sc, ic->ic_curchan, 3740 IEEE80211_HTINFO_2NDCHAN_NONE); 3741 error = 0; 3742 } 3743 break; 3744 3745 default: 3746 error = ieee80211_ioctl(ifp, cmd, data); 3747 break; 3748 } 3749 if (error == ENETRESET) { 3750 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3751 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3752 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3753 urtwn_init(ifp); 3754 } 3755 error = 0; 3756 } 3757 3758 splx(s); 3759 3760 return error; 3761 } 3762 3763 static __inline int 3764 urtwn_power_on(struct urtwn_softc *sc) 3765 { 3766 3767 return sc->sc_power_on(sc); 3768 } 3769 3770 static int 3771 urtwn_r92c_power_on(struct urtwn_softc *sc) 3772 { 3773 uint32_t reg; 3774 int ntries; 3775 3776 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3777 3778 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3779 3780 /* Wait for autoload done bit. */ 3781 for (ntries = 0; ntries < 1000; ntries++) { 3782 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3783 break; 3784 DELAY(5); 3785 } 3786 if (ntries == 1000) { 3787 aprint_error_dev(sc->sc_dev, 3788 "timeout waiting for chip autoload\n"); 3789 return ETIMEDOUT; 3790 } 3791 3792 /* Unlock ISO/CLK/Power control register. */ 3793 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3794 /* Move SPS into PWM mode. */ 3795 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3796 DELAY(5); 3797 3798 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3799 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3800 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3801 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3802 DELAY(100); 3803 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3804 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3805 ~R92C_SYS_ISO_CTRL_MD2PP); 3806 } 3807 3808 /* Auto enable WLAN. */ 3809 urtwn_write_2(sc, R92C_APS_FSMCO, 3810 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3811 for (ntries = 0; ntries < 1000; ntries++) { 3812 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3813 R92C_APS_FSMCO_APFM_ONMAC)) 3814 break; 3815 DELAY(100); 3816 } 3817 if (ntries == 1000) { 3818 aprint_error_dev(sc->sc_dev, 3819 "timeout waiting for MAC auto ON\n"); 3820 return ETIMEDOUT; 3821 } 3822 3823 /* Enable radio, GPIO and LED functions. */ 3824 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3825 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3826 urtwn_write_2(sc, R92C_APS_FSMCO, 3827 R92C_APS_FSMCO_AFSM_HSUS | 3828 R92C_APS_FSMCO_PDN_EN | 3829 R92C_APS_FSMCO_PFM_ALDN); 3830 3831 /* Release RF digital isolation. */ 3832 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3833 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3834 3835 /* Initialize MAC. */ 3836 urtwn_write_1(sc, R92C_APSD_CTRL, 3837 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3838 for (ntries = 0; ntries < 200; ntries++) { 3839 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3840 R92C_APSD_CTRL_OFF_STATUS)) 3841 break; 3842 DELAY(5); 3843 } 3844 if (ntries == 200) { 3845 aprint_error_dev(sc->sc_dev, 3846 "timeout waiting for MAC initialization\n"); 3847 return ETIMEDOUT; 3848 } 3849 3850 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3851 reg = urtwn_read_2(sc, R92C_CR); 3852 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3853 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3854 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3855 R92C_CR_ENSEC; 3856 urtwn_write_2(sc, R92C_CR, reg); 3857 3858 urtwn_write_1(sc, 0xfe10, 0x19); 3859 return 0; 3860 } 3861 3862 static int 3863 urtwn_r92e_power_on(struct urtwn_softc *sc) 3864 { 3865 uint32_t reg; 3866 uint32_t val; 3867 int ntries; 3868 3869 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3870 3871 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3872 3873 /* Enable radio, GPIO and LED functions. */ 3874 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3875 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3876 urtwn_write_2(sc, R92C_APS_FSMCO, 3877 R92C_APS_FSMCO_AFSM_HSUS | 3878 R92C_APS_FSMCO_PDN_EN | 3879 R92C_APS_FSMCO_PFM_ALDN); 3880 3881 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3882 /* LDO. */ 3883 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3884 } 3885 else { 3886 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3887 R92C_SYS_SWR_CTRL2) & 0xffff); 3888 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3889 } 3890 3891 for (ntries = 0; ntries < 2; ntries++) { 3892 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3893 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3894 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3895 R92C_AFE_CTRL4)); 3896 } 3897 3898 /* Reset BB. */ 3899 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3900 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3901 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3902 3903 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3904 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3905 3906 /* Disable HWPDN. */ 3907 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3908 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3909 3910 /* Disable WL suspend. */ 3911 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3912 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3913 R92C_APS_FSMCO_AFSM_HSUS)); 3914 3915 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3916 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3917 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3918 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3919 for (ntries = 0; ntries < 10000; ntries++) { 3920 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3921 R92C_APS_FSMCO_APFM_ONMAC; 3922 if (val == 0x0) 3923 break; 3924 DELAY(10); 3925 } 3926 if (ntries == 10000) { 3927 aprint_error_dev(sc->sc_dev, 3928 "timeout waiting for chip power up\n"); 3929 return ETIMEDOUT; 3930 } 3931 3932 urtwn_write_2(sc, R92C_CR, 0x00); 3933 reg = urtwn_read_2(sc, R92C_CR); 3934 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3935 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3936 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3937 urtwn_write_2(sc, R92C_CR, reg); 3938 3939 return 0; 3940 } 3941 3942 static int 3943 urtwn_r88e_power_on(struct urtwn_softc *sc) 3944 { 3945 uint32_t reg; 3946 uint8_t val; 3947 int ntries; 3948 3949 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3950 3951 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3952 3953 /* Wait for power ready bit. */ 3954 for (ntries = 0; ntries < 5000; ntries++) { 3955 val = urtwn_read_1(sc, 0x6) & 0x2; 3956 if (val == 0x2) 3957 break; 3958 DELAY(10); 3959 } 3960 if (ntries == 5000) { 3961 aprint_error_dev(sc->sc_dev, 3962 "timeout waiting for chip power up\n"); 3963 return ETIMEDOUT; 3964 } 3965 3966 /* Reset BB. */ 3967 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3968 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3969 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3970 3971 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3972 3973 /* Disable HWPDN. */ 3974 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3975 3976 /* Disable WL suspend. */ 3977 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3978 3979 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3980 for (ntries = 0; ntries < 5000; ntries++) { 3981 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3982 break; 3983 DELAY(10); 3984 } 3985 if (ntries == 5000) 3986 return ETIMEDOUT; 3987 3988 /* Enable LDO normal mode. */ 3989 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3990 3991 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3992 urtwn_write_2(sc, R92C_CR, 0); 3993 reg = urtwn_read_2(sc, R92C_CR); 3994 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3995 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3996 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3997 urtwn_write_2(sc, R92C_CR, reg); 3998 3999 return 0; 4000 } 4001 4002 static int 4003 urtwn_llt_init(struct urtwn_softc *sc) 4004 { 4005 size_t i, page_count, pktbuf_count; 4006 uint32_t val; 4007 int error; 4008 4009 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4010 4011 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4012 4013 if (sc->chip & URTWN_CHIP_88E) 4014 page_count = R88E_TX_PAGE_COUNT; 4015 else if (sc->chip & URTWN_CHIP_92EU) 4016 page_count = R92E_TX_PAGE_COUNT; 4017 else 4018 page_count = R92C_TX_PAGE_COUNT; 4019 if (sc->chip & URTWN_CHIP_88E) 4020 pktbuf_count = R88E_TXPKTBUF_COUNT; 4021 else if (sc->chip & URTWN_CHIP_92EU) 4022 pktbuf_count = R88E_TXPKTBUF_COUNT; 4023 else 4024 pktbuf_count = R92C_TXPKTBUF_COUNT; 4025 4026 if (sc->chip & URTWN_CHIP_92EU) { 4027 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 4028 urtwn_write_4(sc, R92E_AUTO_LLT, val); 4029 DELAY(100); 4030 val = urtwn_read_4(sc, R92E_AUTO_LLT); 4031 if (val & R92E_AUTO_LLT_EN) 4032 return EIO; 4033 return 0; 4034 } 4035 4036 /* Reserve pages [0; page_count]. */ 4037 for (i = 0; i < page_count; i++) { 4038 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4039 return error; 4040 } 4041 /* NB: 0xff indicates end-of-list. */ 4042 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4043 return error; 4044 /* 4045 * Use pages [page_count + 1; pktbuf_count - 1] 4046 * as ring buffer. 4047 */ 4048 for (++i; i < pktbuf_count - 1; i++) { 4049 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4050 return error; 4051 } 4052 /* Make the last page point to the beginning of the ring buffer. */ 4053 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4054 return error; 4055 } 4056 4057 static __unused void 4058 urtwn_fw_reset(struct urtwn_softc *sc) 4059 { 4060 uint16_t reg; 4061 int ntries; 4062 4063 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4064 4065 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4066 4067 /* Tell 8051 to reset itself. */ 4068 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4069 4070 /* Wait until 8051 resets by itself. */ 4071 for (ntries = 0; ntries < 100; ntries++) { 4072 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4073 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4074 return; 4075 DELAY(50); 4076 } 4077 /* Force 8051 reset. */ 4078 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4079 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4080 } 4081 4082 static void 4083 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4084 { 4085 uint16_t reg; 4086 4087 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4088 4089 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4090 4091 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4092 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4093 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4094 } 4095 DELAY(50); 4096 4097 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4098 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4099 DELAY(50); 4100 4101 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4102 DELAY(50); 4103 4104 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4105 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4106 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4107 } 4108 DELAY(50); 4109 4110 } 4111 4112 static int 4113 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4114 { 4115 uint32_t reg; 4116 int off, mlen, error = 0; 4117 4118 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4119 device_xname(sc->sc_dev), __func__, page, buf, len)); 4120 4121 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4122 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4123 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4124 4125 off = R92C_FW_START_ADDR; 4126 while (len > 0) { 4127 if (len > 196) 4128 mlen = 196; 4129 else if (len > 4) 4130 mlen = 4; 4131 else 4132 mlen = 1; 4133 error = urtwn_write_region(sc, off, buf, mlen); 4134 if (error != 0) 4135 break; 4136 off += mlen; 4137 buf += mlen; 4138 len -= mlen; 4139 } 4140 return error; 4141 } 4142 4143 static int 4144 urtwn_load_firmware(struct urtwn_softc *sc) 4145 { 4146 firmware_handle_t fwh; 4147 const struct r92c_fw_hdr *hdr; 4148 const char *name; 4149 u_char *fw, *ptr; 4150 size_t len; 4151 uint32_t reg; 4152 int mlen, ntries, page, error; 4153 4154 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4155 4156 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4157 4158 /* Read firmware image from the filesystem. */ 4159 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4160 name = "rtl8188eufw.bin"; 4161 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4162 name = "rtl8192eefw.bin"; 4163 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4164 URTWN_CHIP_UMC_A_CUT) 4165 name = "rtl8192cfwU.bin"; 4166 else 4167 name = "rtl8192cfw.bin"; 4168 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4169 aprint_error_dev(sc->sc_dev, 4170 "failed load firmware of file %s (error %d)\n", name, 4171 error); 4172 return error; 4173 } 4174 const size_t fwlen = len = firmware_get_size(fwh); 4175 fw = firmware_malloc(len); 4176 if (fw == NULL) { 4177 aprint_error_dev(sc->sc_dev, 4178 "failed to allocate firmware memory\n"); 4179 firmware_close(fwh); 4180 return ENOMEM; 4181 } 4182 error = firmware_read(fwh, 0, fw, len); 4183 firmware_close(fwh); 4184 if (error != 0) { 4185 aprint_error_dev(sc->sc_dev, 4186 "failed to read firmware (error %d)\n", error); 4187 firmware_free(fw, fwlen); 4188 return error; 4189 } 4190 4191 len = fwlen; 4192 ptr = fw; 4193 hdr = (const struct r92c_fw_hdr *)ptr; 4194 /* Check if there is a valid FW header and skip it. */ 4195 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4196 (le16toh(hdr->signature) >> 4) == 0x88e || 4197 (le16toh(hdr->signature) >> 4) == 0x92e || 4198 (le16toh(hdr->signature) >> 4) == 0x92c) { 4199 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4200 device_xname(sc->sc_dev), __func__, 4201 le16toh(hdr->version), le16toh(hdr->subversion), 4202 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4203 ptr += sizeof(*hdr); 4204 len -= sizeof(*hdr); 4205 } 4206 4207 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4208 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4209 ISSET(sc->chip, URTWN_CHIP_92EU)) 4210 urtwn_r88e_fw_reset(sc); 4211 else 4212 urtwn_fw_reset(sc); 4213 } 4214 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4215 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4216 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4217 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4218 R92C_SYS_FUNC_EN_CPUEN); 4219 } 4220 4221 /* download enabled */ 4222 urtwn_write_1(sc, R92C_MCUFWDL, 4223 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4224 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4225 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4226 4227 /* Reset the FWDL checksum. */ 4228 urtwn_write_1(sc, R92C_MCUFWDL, 4229 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4230 4231 DELAY(50); 4232 /* download firmware */ 4233 for (page = 0; len > 0; page++) { 4234 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4235 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4236 if (error != 0) { 4237 aprint_error_dev(sc->sc_dev, 4238 "could not load firmware page %d\n", page); 4239 goto fail; 4240 } 4241 ptr += mlen; 4242 len -= mlen; 4243 } 4244 4245 /* download disable */ 4246 urtwn_write_1(sc, R92C_MCUFWDL, 4247 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4248 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4249 4250 /* Wait for checksum report. */ 4251 for (ntries = 0; ntries < 1000; ntries++) { 4252 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4253 break; 4254 DELAY(5); 4255 } 4256 if (ntries == 1000) { 4257 aprint_error_dev(sc->sc_dev, 4258 "timeout waiting for checksum report\n"); 4259 error = ETIMEDOUT; 4260 goto fail; 4261 } 4262 4263 /* Wait for firmware readiness. */ 4264 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4265 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4266 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4267 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4268 ISSET(sc->chip, URTWN_CHIP_92EU)) 4269 urtwn_r88e_fw_reset(sc); 4270 for (ntries = 0; ntries < 6000; ntries++) { 4271 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4272 break; 4273 DELAY(5); 4274 } 4275 if (ntries == 6000) { 4276 aprint_error_dev(sc->sc_dev, 4277 "timeout waiting for firmware readiness\n"); 4278 error = ETIMEDOUT; 4279 goto fail; 4280 } 4281 fail: 4282 firmware_free(fw, fwlen); 4283 return error; 4284 } 4285 4286 static __inline int 4287 urtwn_dma_init(struct urtwn_softc *sc) 4288 { 4289 4290 return sc->sc_dma_init(sc); 4291 } 4292 4293 static int 4294 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4295 { 4296 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4297 uint32_t reg; 4298 int error; 4299 4300 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4301 4302 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4303 4304 /* Initialize LLT table. */ 4305 error = urtwn_llt_init(sc); 4306 if (error != 0) 4307 return error; 4308 4309 /* Get Tx queues to USB endpoints mapping. */ 4310 hashq = hasnq = haslq = 0; 4311 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4312 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping %#x\n", 4313 device_xname(sc->sc_dev), __func__, reg)); 4314 if (MS(reg, R92C_USB_EP_HQ) != 0) 4315 hashq = 1; 4316 if (MS(reg, R92C_USB_EP_NQ) != 0) 4317 hasnq = 1; 4318 if (MS(reg, R92C_USB_EP_LQ) != 0) 4319 haslq = 1; 4320 nqueues = hashq + hasnq + haslq; 4321 if (nqueues == 0) 4322 return EIO; 4323 /* Get the number of pages for each queue. */ 4324 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4325 /* The remaining pages are assigned to the high priority queue. */ 4326 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4327 4328 /* Set number of pages for normal priority queue. */ 4329 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4330 urtwn_write_4(sc, R92C_RQPN, 4331 /* Set number of pages for public queue. */ 4332 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4333 /* Set number of pages for high priority queue. */ 4334 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4335 /* Set number of pages for low priority queue. */ 4336 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4337 /* Load values. */ 4338 R92C_RQPN_LD); 4339 4340 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4341 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4342 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4343 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4344 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4345 4346 /* Set queue to USB pipe mapping. */ 4347 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4348 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4349 if (nqueues == 1) { 4350 if (hashq) { 4351 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4352 } else if (hasnq) { 4353 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4354 } else { 4355 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4356 } 4357 } else if (nqueues == 2) { 4358 /* All 2-endpoints configs have a high priority queue. */ 4359 if (!hashq) { 4360 return EIO; 4361 } 4362 if (hasnq) { 4363 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4364 } else { 4365 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4366 } 4367 } else { 4368 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4369 } 4370 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4371 4372 /* Set Tx/Rx transfer page boundary. */ 4373 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4374 4375 /* Set Tx/Rx transfer page size. */ 4376 urtwn_write_1(sc, R92C_PBP, 4377 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4378 return 0; 4379 } 4380 4381 static int 4382 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4383 { 4384 usb_interface_descriptor_t *id; 4385 uint32_t reg; 4386 int nqueues; 4387 int error; 4388 4389 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4390 4391 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4392 4393 /* Initialize LLT table. */ 4394 error = urtwn_llt_init(sc); 4395 if (error != 0) 4396 return error; 4397 4398 /* Get Tx queues to USB endpoints mapping. */ 4399 id = usbd_get_interface_descriptor(sc->sc_iface); 4400 nqueues = id->bNumEndpoints - 1; 4401 if (nqueues == 0) 4402 return EIO; 4403 4404 /* Set number of pages for normal priority queue. */ 4405 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4406 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4407 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4408 4409 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4410 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4411 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4412 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4413 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4414 4415 /* Set queue to USB pipe mapping. */ 4416 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4417 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4418 if (nqueues == 1) 4419 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4420 else if (nqueues == 2) 4421 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4422 else 4423 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4424 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4425 4426 /* Set Tx/Rx transfer page boundary. */ 4427 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4428 4429 /* Set Tx/Rx transfer page size. */ 4430 urtwn_write_1(sc, R92C_PBP, 4431 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4432 4433 return 0; 4434 } 4435 4436 static void 4437 urtwn_mac_init(struct urtwn_softc *sc) 4438 { 4439 size_t i; 4440 4441 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4442 4443 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4444 4445 /* Write MAC initialization values. */ 4446 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4447 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4448 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4449 rtl8188eu_mac[i].val); 4450 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4451 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4452 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4453 rtl8192eu_mac[i].val); 4454 } else { 4455 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4456 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4457 rtl8192cu_mac[i].val); 4458 } 4459 } 4460 4461 static void 4462 urtwn_bb_init(struct urtwn_softc *sc) 4463 { 4464 const struct rtwn_bb_prog *prog; 4465 uint32_t reg; 4466 uint8_t crystalcap; 4467 size_t i; 4468 4469 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4470 4471 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4472 4473 /* Enable BB and RF. */ 4474 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4475 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4476 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4477 R92C_SYS_FUNC_EN_DIO_RF); 4478 4479 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4480 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4481 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4482 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4483 } 4484 4485 urtwn_write_1(sc, R92C_RF_CTRL, 4486 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4487 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4488 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4489 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4490 4491 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4492 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4493 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4494 urtwn_write_1(sc, 0x15, 0xe9); 4495 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4496 } 4497 4498 /* Select BB programming based on board type. */ 4499 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4500 prog = &rtl8188eu_bb_prog; 4501 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4502 prog = &rtl8192eu_bb_prog; 4503 else if (!(sc->chip & URTWN_CHIP_92C)) { 4504 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4505 prog = &rtl8188ce_bb_prog; 4506 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4507 prog = &rtl8188ru_bb_prog; 4508 } else { 4509 prog = &rtl8188cu_bb_prog; 4510 } 4511 } else { 4512 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4513 prog = &rtl8192ce_bb_prog; 4514 } else { 4515 prog = &rtl8192cu_bb_prog; 4516 } 4517 } 4518 /* Write BB initialization values. */ 4519 for (i = 0; i < prog->count; i++) { 4520 /* additional delay depend on registers */ 4521 switch (prog->regs[i]) { 4522 case 0xfe: 4523 urtwn_delay_ms(sc, 50); 4524 break; 4525 case 0xfd: 4526 urtwn_delay_ms(sc, 5); 4527 break; 4528 case 0xfc: 4529 urtwn_delay_ms(sc, 1); 4530 break; 4531 case 0xfb: 4532 DELAY(50); 4533 break; 4534 case 0xfa: 4535 DELAY(5); 4536 break; 4537 case 0xf9: 4538 DELAY(1); 4539 break; 4540 } 4541 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4542 DELAY(1); 4543 } 4544 4545 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4546 /* 8192C 1T only configuration. */ 4547 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4548 reg = (reg & ~0x00000003) | 0x2; 4549 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4550 4551 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4552 reg = (reg & ~0x00300033) | 0x00200022; 4553 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4554 4555 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4556 reg = (reg & ~0xff000000) | (0x45 << 24); 4557 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4558 4559 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4560 reg = (reg & ~0x000000ff) | 0x23; 4561 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4562 4563 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4564 reg = (reg & ~0x00000030) | (1 << 4); 4565 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4566 4567 reg = urtwn_bb_read(sc, 0xe74); 4568 reg = (reg & ~0x0c000000) | (2 << 26); 4569 urtwn_bb_write(sc, 0xe74, reg); 4570 reg = urtwn_bb_read(sc, 0xe78); 4571 reg = (reg & ~0x0c000000) | (2 << 26); 4572 urtwn_bb_write(sc, 0xe78, reg); 4573 reg = urtwn_bb_read(sc, 0xe7c); 4574 reg = (reg & ~0x0c000000) | (2 << 26); 4575 urtwn_bb_write(sc, 0xe7c, reg); 4576 reg = urtwn_bb_read(sc, 0xe80); 4577 reg = (reg & ~0x0c000000) | (2 << 26); 4578 urtwn_bb_write(sc, 0xe80, reg); 4579 reg = urtwn_bb_read(sc, 0xe88); 4580 reg = (reg & ~0x0c000000) | (2 << 26); 4581 urtwn_bb_write(sc, 0xe88, reg); 4582 } 4583 4584 /* Write AGC values. */ 4585 for (i = 0; i < prog->agccount; i++) { 4586 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4587 DELAY(1); 4588 } 4589 4590 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4591 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4592 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4593 DELAY(1); 4594 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4595 DELAY(1); 4596 } 4597 4598 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4599 crystalcap = sc->r88e_rom[0xb9]; 4600 if (crystalcap == 0x00) 4601 crystalcap = 0x20; 4602 crystalcap &= 0x3f; 4603 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4604 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4605 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4606 crystalcap | crystalcap << 6)); 4607 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4608 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4609 crystalcap = sc->r88e_rom[0xb9]; 4610 if (crystalcap == 0xff) 4611 crystalcap = 0x20; 4612 crystalcap &= 0x3f; 4613 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4614 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4615 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4616 crystalcap | crystalcap << 6)); 4617 } else { 4618 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4619 R92C_HSSI_PARAM2_CCK_HIPWR) { 4620 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4621 } 4622 } 4623 } 4624 4625 static void 4626 urtwn_rf_init(struct urtwn_softc *sc) 4627 { 4628 const struct rtwn_rf_prog *prog; 4629 uint32_t reg, mask, saved; 4630 size_t i, j, idx; 4631 4632 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4633 4634 /* Select RF programming based on board type. */ 4635 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4636 prog = rtl8188eu_rf_prog; 4637 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4638 prog = rtl8192eu_rf_prog; 4639 else if (!(sc->chip & URTWN_CHIP_92C)) { 4640 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4641 prog = rtl8188ce_rf_prog; 4642 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4643 prog = rtl8188ru_rf_prog; 4644 } else { 4645 prog = rtl8188cu_rf_prog; 4646 } 4647 } else { 4648 prog = rtl8192ce_rf_prog; 4649 } 4650 4651 for (i = 0; i < sc->nrxchains; i++) { 4652 /* Save RF_ENV control type. */ 4653 idx = i / 2; 4654 mask = 0xffffU << ((i % 2) * 16); 4655 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4656 4657 /* Set RF_ENV enable. */ 4658 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4659 reg |= 0x100000; 4660 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4661 DELAY(50); 4662 4663 /* Set RF_ENV output high. */ 4664 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4665 reg |= 0x10; 4666 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4667 DELAY(50); 4668 4669 /* Set address and data lengths of RF registers. */ 4670 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4671 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4672 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4673 DELAY(50); 4674 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4675 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4676 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4677 DELAY(50); 4678 4679 /* Write RF initialization values for this chain. */ 4680 for (j = 0; j < prog[i].count; j++) { 4681 if (prog[i].regs[j] >= 0xf9 && 4682 prog[i].regs[j] <= 0xfe) { 4683 /* 4684 * These are fake RF registers offsets that 4685 * indicate a delay is required. 4686 */ 4687 urtwn_delay_ms(sc, 50); 4688 continue; 4689 } 4690 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4691 DELAY(5); 4692 } 4693 4694 /* Restore RF_ENV control type. */ 4695 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4696 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4697 } 4698 4699 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4700 URTWN_CHIP_UMC_A_CUT) { 4701 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4702 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4703 } 4704 4705 /* Cache RF register CHNLBW. */ 4706 for (i = 0; i < 2; i++) { 4707 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4708 } 4709 } 4710 4711 static void 4712 urtwn_cam_init(struct urtwn_softc *sc) 4713 { 4714 uint32_t content, command; 4715 uint8_t idx; 4716 size_t i; 4717 4718 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4719 4720 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4721 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4722 return; 4723 4724 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4725 content = (idx & 3) 4726 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4727 | R92C_CAM_VALID; 4728 4729 command = R92C_CAMCMD_POLLING 4730 | R92C_CAMCMD_WRITE 4731 | R92C_CAM_CTL0(idx); 4732 4733 urtwn_write_4(sc, R92C_CAMWRITE, content); 4734 urtwn_write_4(sc, R92C_CAMCMD, command); 4735 } 4736 4737 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4738 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4739 if (i == 0) { 4740 content = (idx & 3) 4741 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4742 | R92C_CAM_VALID; 4743 } else { 4744 content = 0; 4745 } 4746 4747 command = R92C_CAMCMD_POLLING 4748 | R92C_CAMCMD_WRITE 4749 | R92C_CAM_CTL0(idx) 4750 | i; 4751 4752 urtwn_write_4(sc, R92C_CAMWRITE, content); 4753 urtwn_write_4(sc, R92C_CAMCMD, command); 4754 } 4755 } 4756 4757 /* Invalidate all CAM entries. */ 4758 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4759 } 4760 4761 static void 4762 urtwn_pa_bias_init(struct urtwn_softc *sc) 4763 { 4764 uint8_t reg; 4765 size_t i; 4766 4767 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4768 4769 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4770 4771 for (i = 0; i < sc->nrxchains; i++) { 4772 if (sc->pa_setting & (1U << i)) 4773 continue; 4774 4775 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4776 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4777 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4778 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4779 } 4780 if (!(sc->pa_setting & 0x10)) { 4781 reg = urtwn_read_1(sc, 0x16); 4782 reg = (reg & ~0xf0) | 0x90; 4783 urtwn_write_1(sc, 0x16, reg); 4784 } 4785 } 4786 4787 static void 4788 urtwn_rxfilter_init(struct urtwn_softc *sc) 4789 { 4790 4791 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4792 4793 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4794 4795 /* Initialize Rx filter. */ 4796 /* TODO: use better filter for monitor mode. */ 4797 urtwn_write_4(sc, R92C_RCR, 4798 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4799 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4800 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4801 /* Accept all multicast frames. */ 4802 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4803 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4804 /* Accept all management frames. */ 4805 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4806 /* Reject all control frames. */ 4807 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4808 /* Accept all data frames. */ 4809 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4810 } 4811 4812 static void 4813 urtwn_edca_init(struct urtwn_softc *sc) 4814 { 4815 4816 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4817 4818 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4819 4820 /* set spec SIFS (used in NAV) */ 4821 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4822 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4823 4824 /* set SIFS CCK/OFDM */ 4825 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4826 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4827 4828 /* TXOP */ 4829 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4830 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4831 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4832 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4833 } 4834 4835 static void 4836 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4837 uint16_t power[URTWN_RIDX_COUNT]) 4838 { 4839 uint32_t reg; 4840 4841 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4842 __func__, chain)); 4843 4844 /* Write per-CCK rate Tx power. */ 4845 if (chain == 0) { 4846 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4847 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4848 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4849 4850 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4851 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4852 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4853 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4854 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4855 } else { 4856 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4857 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4858 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4859 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4860 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4861 4862 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4863 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4864 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4865 } 4866 /* Write per-OFDM rate Tx power. */ 4867 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4868 SM(R92C_TXAGC_RATE06, power[ 4]) | 4869 SM(R92C_TXAGC_RATE09, power[ 5]) | 4870 SM(R92C_TXAGC_RATE12, power[ 6]) | 4871 SM(R92C_TXAGC_RATE18, power[ 7])); 4872 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4873 SM(R92C_TXAGC_RATE24, power[ 8]) | 4874 SM(R92C_TXAGC_RATE36, power[ 9]) | 4875 SM(R92C_TXAGC_RATE48, power[10]) | 4876 SM(R92C_TXAGC_RATE54, power[11])); 4877 /* Write per-MCS Tx power. */ 4878 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4879 SM(R92C_TXAGC_MCS00, power[12]) | 4880 SM(R92C_TXAGC_MCS01, power[13]) | 4881 SM(R92C_TXAGC_MCS02, power[14]) | 4882 SM(R92C_TXAGC_MCS03, power[15])); 4883 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4884 SM(R92C_TXAGC_MCS04, power[16]) | 4885 SM(R92C_TXAGC_MCS05, power[17]) | 4886 SM(R92C_TXAGC_MCS06, power[18]) | 4887 SM(R92C_TXAGC_MCS07, power[19])); 4888 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4889 SM(R92C_TXAGC_MCS08, power[20]) | 4890 SM(R92C_TXAGC_MCS09, power[21]) | 4891 SM(R92C_TXAGC_MCS10, power[22]) | 4892 SM(R92C_TXAGC_MCS11, power[23])); 4893 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4894 SM(R92C_TXAGC_MCS12, power[24]) | 4895 SM(R92C_TXAGC_MCS13, power[25]) | 4896 SM(R92C_TXAGC_MCS14, power[26]) | 4897 SM(R92C_TXAGC_MCS15, power[27])); 4898 } 4899 4900 static void 4901 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4902 uint16_t power[URTWN_RIDX_COUNT]) 4903 { 4904 struct r92c_rom *rom = &sc->rom; 4905 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4906 const struct rtwn_txpwr *base; 4907 int ridx, group; 4908 4909 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4910 device_xname(sc->sc_dev), __func__, chain, chan)); 4911 4912 /* Determine channel group. */ 4913 if (chan <= 3) { 4914 group = 0; 4915 } else if (chan <= 9) { 4916 group = 1; 4917 } else { 4918 group = 2; 4919 } 4920 4921 /* Get original Tx power based on board type and RF chain. */ 4922 if (!(sc->chip & URTWN_CHIP_92C)) { 4923 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4924 base = &rtl8188ru_txagc[chain]; 4925 } else { 4926 base = &rtl8192cu_txagc[chain]; 4927 } 4928 } else { 4929 base = &rtl8192cu_txagc[chain]; 4930 } 4931 4932 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4933 if (sc->regulatory == 0) { 4934 for (ridx = 0; ridx <= 3; ridx++) { 4935 power[ridx] = base->pwr[0][ridx]; 4936 } 4937 } 4938 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4939 if (sc->regulatory == 3) { 4940 power[ridx] = base->pwr[0][ridx]; 4941 /* Apply vendor limits. */ 4942 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4943 maxpow = rom->ht40_max_pwr[group]; 4944 } else { 4945 maxpow = rom->ht20_max_pwr[group]; 4946 } 4947 maxpow = (maxpow >> (chain * 4)) & 0xf; 4948 if (power[ridx] > maxpow) { 4949 power[ridx] = maxpow; 4950 } 4951 } else if (sc->regulatory == 1) { 4952 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4953 power[ridx] = base->pwr[group][ridx]; 4954 } 4955 } else if (sc->regulatory != 2) { 4956 power[ridx] = base->pwr[0][ridx]; 4957 } 4958 } 4959 4960 /* Compute per-CCK rate Tx power. */ 4961 cckpow = rom->cck_tx_pwr[chain][group]; 4962 for (ridx = 0; ridx <= 3; ridx++) { 4963 power[ridx] += cckpow; 4964 if (power[ridx] > R92C_MAX_TX_PWR) { 4965 power[ridx] = R92C_MAX_TX_PWR; 4966 } 4967 } 4968 4969 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4970 if (sc->ntxchains > 1) { 4971 /* Apply reduction for 2 spatial streams. */ 4972 diff = rom->ht40_2s_tx_pwr_diff[group]; 4973 diff = (diff >> (chain * 4)) & 0xf; 4974 htpow = (htpow > diff) ? htpow - diff : 0; 4975 } 4976 4977 /* Compute per-OFDM rate Tx power. */ 4978 diff = rom->ofdm_tx_pwr_diff[group]; 4979 diff = (diff >> (chain * 4)) & 0xf; 4980 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4981 for (ridx = 4; ridx <= 11; ridx++) { 4982 power[ridx] += ofdmpow; 4983 if (power[ridx] > R92C_MAX_TX_PWR) { 4984 power[ridx] = R92C_MAX_TX_PWR; 4985 } 4986 } 4987 4988 /* Compute per-MCS Tx power. */ 4989 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4990 diff = rom->ht20_tx_pwr_diff[group]; 4991 diff = (diff >> (chain * 4)) & 0xf; 4992 htpow += diff; /* HT40->HT20 correction. */ 4993 } 4994 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4995 power[ridx] += htpow; 4996 if (power[ridx] > R92C_MAX_TX_PWR) { 4997 power[ridx] = R92C_MAX_TX_PWR; 4998 } 4999 } 5000 #ifdef URTWN_DEBUG 5001 if (urtwn_debug & DBG_RF) { 5002 /* Dump per-rate Tx power values. */ 5003 printf("%s: %s: Tx power for chain %zd:\n", 5004 device_xname(sc->sc_dev), __func__, chain); 5005 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 5006 printf("%s: %s: Rate %d = %u\n", 5007 device_xname(sc->sc_dev), __func__, ridx, 5008 power[ridx]); 5009 } 5010 } 5011 #endif 5012 } 5013 5014 void 5015 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 5016 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 5017 { 5018 uint16_t cckpow, ofdmpow, bw20pow, htpow; 5019 const struct rtwn_r88e_txpwr *base; 5020 int ridx, group; 5021 5022 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 5023 device_xname(sc->sc_dev), __func__, chain, chan)); 5024 5025 /* Determine channel group. */ 5026 if (chan <= 2) 5027 group = 0; 5028 else if (chan <= 5) 5029 group = 1; 5030 else if (chan <= 8) 5031 group = 2; 5032 else if (chan <= 11) 5033 group = 3; 5034 else if (chan <= 13) 5035 group = 4; 5036 else 5037 group = 5; 5038 5039 /* Get original Tx power based on board type and RF chain. */ 5040 base = &rtl8188eu_txagc[chain]; 5041 5042 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5043 if (sc->regulatory == 0) { 5044 for (ridx = 0; ridx <= 3; ridx++) 5045 power[ridx] = base->pwr[0][ridx]; 5046 } 5047 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5048 if (sc->regulatory == 3) 5049 power[ridx] = base->pwr[0][ridx]; 5050 else if (sc->regulatory == 1) { 5051 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5052 power[ridx] = base->pwr[group][ridx]; 5053 } else if (sc->regulatory != 2) 5054 power[ridx] = base->pwr[0][ridx]; 5055 } 5056 5057 /* Compute per-CCK rate Tx power. */ 5058 cckpow = sc->cck_tx_pwr[group]; 5059 for (ridx = 0; ridx <= 3; ridx++) { 5060 power[ridx] += cckpow; 5061 if (power[ridx] > R92C_MAX_TX_PWR) 5062 power[ridx] = R92C_MAX_TX_PWR; 5063 } 5064 5065 htpow = sc->ht40_tx_pwr[group]; 5066 5067 /* Compute per-OFDM rate Tx power. */ 5068 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5069 for (ridx = 4; ridx <= 11; ridx++) { 5070 power[ridx] += ofdmpow; 5071 if (power[ridx] > R92C_MAX_TX_PWR) 5072 power[ridx] = R92C_MAX_TX_PWR; 5073 } 5074 5075 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5076 for (ridx = 12; ridx <= 27; ridx++) { 5077 power[ridx] += bw20pow; 5078 if (power[ridx] > R92C_MAX_TX_PWR) 5079 power[ridx] = R92C_MAX_TX_PWR; 5080 } 5081 } 5082 5083 static void 5084 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5085 { 5086 uint16_t power[URTWN_RIDX_COUNT]; 5087 size_t i; 5088 5089 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5090 5091 for (i = 0; i < sc->ntxchains; i++) { 5092 /* Compute per-rate Tx power values. */ 5093 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5094 ISSET(sc->chip, URTWN_CHIP_92EU)) 5095 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5096 else 5097 urtwn_get_txpower(sc, i, chan, ht40m, power); 5098 /* Write per-rate Tx power values to hardware. */ 5099 urtwn_write_txpower(sc, i, power); 5100 } 5101 } 5102 5103 static void 5104 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5105 { 5106 struct ieee80211com *ic = &sc->sc_ic; 5107 u_int chan; 5108 size_t i; 5109 5110 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5111 5112 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5113 __func__, chan)); 5114 5115 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5116 5117 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5118 chan += 2; 5119 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5120 chan -= 2; 5121 } 5122 5123 /* Set Tx power for this new channel. */ 5124 urtwn_set_txpower(sc, chan, ht40m); 5125 5126 for (i = 0; i < sc->nrxchains; i++) { 5127 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5128 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5129 } 5130 5131 if (ht40m) { 5132 /* Is secondary channel below or above primary? */ 5133 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5134 uint32_t reg; 5135 5136 urtwn_write_1(sc, R92C_BWOPMODE, 5137 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5138 5139 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5140 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5141 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5142 5143 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5144 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5145 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5146 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5147 5148 /* Set CCK side band. */ 5149 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5150 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5151 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5152 5153 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5154 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5155 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5156 5157 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5158 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5159 ~R92C_FPGA0_ANAPARAM2_CBW20); 5160 5161 reg = urtwn_bb_read(sc, 0x818); 5162 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5163 urtwn_bb_write(sc, 0x818, reg); 5164 5165 /* Select 40MHz bandwidth. */ 5166 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5167 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5168 } else { 5169 urtwn_write_1(sc, R92C_BWOPMODE, 5170 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5171 5172 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5173 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5174 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5175 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5176 5177 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5178 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5179 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5180 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5181 R92C_FPGA0_ANAPARAM2_CBW20); 5182 } 5183 5184 /* Select 20MHz bandwidth. */ 5185 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5186 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5187 (ISSET(sc->chip, URTWN_CHIP_88E) || 5188 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5189 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5190 } 5191 } 5192 5193 static void 5194 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5195 { 5196 5197 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5198 __func__, inited)); 5199 5200 uint32_t addaBackup[16], iqkBackup[4], piMode; 5201 5202 #ifdef notyet 5203 uint32_t odfm0_agccore_regs[3]; 5204 uint32_t ant_regs[3]; 5205 uint32_t rf_regs[8]; 5206 #endif 5207 uint32_t reg0, reg1, reg2; 5208 int i, attempt; 5209 5210 #ifdef notyet 5211 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5212 R92E_STBC_SETTING + 2)); 5213 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5214 /* Save AGCCORE regs. */ 5215 for (i = 0; i < sc->nrxchains; i++) { 5216 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5217 R92C_OFDM0_AGCCORE1(i)); 5218 } 5219 #endif 5220 /* Save BB regs. */ 5221 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5222 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5223 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5224 5225 /* Save adda regs to be restored when finished. */ 5226 for (i = 0; i < __arraycount(addaReg); i++) 5227 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5228 /* Save mac regs. */ 5229 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5230 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5231 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5232 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5233 5234 #ifdef notyet 5235 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5236 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5237 5238 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5239 for (i = 0; i < sc->nrxchains; i++) 5240 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5241 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5242 #endif 5243 5244 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5245 R92C_HSSI_PARAM1_PI); 5246 if (piMode == 0) { 5247 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5248 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5249 R92C_HSSI_PARAM1_PI); 5250 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5251 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5252 R92C_HSSI_PARAM1_PI); 5253 } 5254 5255 attempt = 1; 5256 5257 next_attempt: 5258 5259 /* Set mac regs for calibration. */ 5260 for (i = 0; i < __arraycount(addaReg); i++) { 5261 urtwn_bb_write(sc, addaReg[i], 5262 addaReg[__arraycount(addaReg) - 1]); 5263 } 5264 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5265 R92C_CCK0_AFESETTING)); 5266 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5267 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5268 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5269 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5270 5271 if (sc->ntxchains > 1) 5272 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5273 5274 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5275 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5276 ~R92C_BCN_CTRL_EN_BCN)); 5277 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5278 ~R92C_BCN_CTRL_EN_BCN)); 5279 5280 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5281 ~R92C_GPIO_MUXCFG_ENBT)); 5282 5283 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5284 5285 if (sc->ntxchains > 1) 5286 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5287 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5288 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5289 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5290 5291 /* Restore BB regs. */ 5292 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5293 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5294 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5295 5296 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5297 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5298 if (sc->nrxchains > 1) 5299 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5300 5301 if (attempt-- > 0) 5302 goto next_attempt; 5303 5304 /* Restore mode. */ 5305 if (piMode == 0) { 5306 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5307 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5308 ~R92C_HSSI_PARAM1_PI); 5309 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5310 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5311 ~R92C_HSSI_PARAM1_PI); 5312 } 5313 5314 #ifdef notyet 5315 for (i = 0; i < sc->nrxchains; i++) { 5316 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5317 odfm0_agccore_regs[i]); 5318 } 5319 #endif 5320 5321 /* Restore adda regs. */ 5322 for (i = 0; i < __arraycount(addaReg); i++) 5323 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5324 /* Restore mac regs. */ 5325 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5326 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5327 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5328 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5329 5330 #ifdef notyet 5331 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5332 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5333 5334 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5335 for (i = 0; i < sc->nrxchains; i++) 5336 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5337 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5338 #endif 5339 } 5340 5341 static void 5342 urtwn_lc_calib(struct urtwn_softc *sc) 5343 { 5344 uint32_t rf_ac[2]; 5345 uint8_t txmode; 5346 size_t i; 5347 5348 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5349 5350 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5351 5352 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5353 if ((txmode & 0x70) != 0) { 5354 /* Disable all continuous Tx. */ 5355 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5356 5357 /* Set RF mode to standby mode. */ 5358 for (i = 0; i < sc->nrxchains; i++) { 5359 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5360 urtwn_rf_write(sc, i, R92C_RF_AC, 5361 RW(rf_ac[i], R92C_RF_AC_MODE, 5362 R92C_RF_AC_MODE_STANDBY)); 5363 } 5364 } else { 5365 /* Block all Tx queues. */ 5366 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5367 } 5368 /* Start calibration. */ 5369 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5370 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5371 5372 /* Give calibration the time to complete. */ 5373 urtwn_delay_ms(sc, 100); 5374 5375 /* Restore configuration. */ 5376 if ((txmode & 0x70) != 0) { 5377 /* Restore Tx mode. */ 5378 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5379 /* Restore RF mode. */ 5380 for (i = 0; i < sc->nrxchains; i++) { 5381 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5382 } 5383 } else { 5384 /* Unblock all Tx queues. */ 5385 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5386 } 5387 } 5388 5389 static void 5390 urtwn_temp_calib(struct urtwn_softc *sc) 5391 { 5392 int temp, t_meter_reg; 5393 5394 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5395 5396 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5397 5398 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5399 t_meter_reg = R92C_RF_T_METER; 5400 else 5401 t_meter_reg = R92E_RF_T_METER; 5402 5403 if (sc->thcal_state == 0) { 5404 /* Start measuring temperature. */ 5405 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5406 device_xname(sc->sc_dev), __func__)); 5407 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5408 sc->thcal_state = 1; 5409 return; 5410 } 5411 sc->thcal_state = 0; 5412 5413 /* Read measured temperature. */ 5414 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5415 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5416 __func__, temp)); 5417 if (temp == 0) /* Read failed, skip. */ 5418 return; 5419 5420 /* 5421 * Redo LC calibration if temperature changed significantly since 5422 * last calibration. 5423 */ 5424 if (sc->thcal_lctemp == 0) { 5425 /* First LC calibration is performed in urtwn_init(). */ 5426 sc->thcal_lctemp = temp; 5427 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5428 DPRINTFN(DBG_RF, 5429 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5430 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5431 temp)); 5432 urtwn_lc_calib(sc); 5433 /* Record temperature of last LC calibration. */ 5434 sc->thcal_lctemp = temp; 5435 } 5436 } 5437 5438 static int 5439 urtwn_init(struct ifnet *ifp) 5440 { 5441 struct ieee80211vap *vap = ifp->if_softc; 5442 struct ieee80211com *ic = vap->iv_ic; 5443 struct urtwn_softc *sc = ic->ic_softc; 5444 struct urtwn_rx_data *data; 5445 uint32_t reg; 5446 size_t i; 5447 int error; 5448 5449 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5450 5451 urtwn_stop(ifp, 0); 5452 5453 mutex_enter(&sc->sc_write_mtx); 5454 5455 mutex_enter(&sc->sc_task_mtx); 5456 /* Init host async commands ring. */ 5457 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5458 mutex_exit(&sc->sc_task_mtx); 5459 5460 mutex_enter(&sc->sc_fwcmd_mtx); 5461 /* Init firmware commands ring. */ 5462 sc->fwcur = 0; 5463 mutex_exit(&sc->sc_fwcmd_mtx); 5464 5465 /* Allocate Tx/Rx buffers. */ 5466 error = urtwn_alloc_rx_list(sc); 5467 if (error != 0) { 5468 aprint_error_dev(sc->sc_dev, 5469 "could not allocate Rx buffers\n"); 5470 goto fail; 5471 } 5472 error = urtwn_alloc_tx_list(sc); 5473 if (error != 0) { 5474 aprint_error_dev(sc->sc_dev, 5475 "could not allocate Tx buffers\n"); 5476 goto fail; 5477 } 5478 5479 /* Power on adapter. */ 5480 error = urtwn_power_on(sc); 5481 if (error != 0) 5482 goto fail; 5483 5484 /* Initialize DMA. */ 5485 error = urtwn_dma_init(sc); 5486 if (error != 0) 5487 goto fail; 5488 5489 /* Set info size in Rx descriptors (in 64-bit words). */ 5490 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5491 5492 /* Init interrupts. */ 5493 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5494 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5495 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5496 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5497 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5498 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5499 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5500 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5501 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5502 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5503 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5504 } 5505 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5506 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5507 } else { 5508 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5509 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5510 } 5511 5512 /* Set MAC address. */ 5513 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5514 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5515 5516 /* Set initial network type. */ 5517 reg = urtwn_read_4(sc, R92C_CR); 5518 switch (ic->ic_opmode) { 5519 case IEEE80211_M_STA: 5520 default: 5521 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5522 break; 5523 5524 case IEEE80211_M_IBSS: 5525 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5526 break; 5527 } 5528 urtwn_write_4(sc, R92C_CR, reg); 5529 5530 /* Set response rate */ 5531 reg = urtwn_read_4(sc, R92C_RRSR); 5532 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5533 urtwn_write_4(sc, R92C_RRSR, reg); 5534 5535 /* SIFS (used in NAV) */ 5536 urtwn_write_2(sc, R92C_SPEC_SIFS, 5537 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5538 5539 /* Set short/long retry limits. */ 5540 urtwn_write_2(sc, R92C_RL, 5541 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5542 5543 /* Initialize EDCA parameters. */ 5544 urtwn_edca_init(sc); 5545 5546 /* Setup rate fallback. */ 5547 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5548 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5549 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5550 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5551 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5552 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5553 } 5554 5555 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5556 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5557 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5558 /* Set ACK timeout. */ 5559 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5560 5561 /* Setup USB aggregation. */ 5562 /* Tx */ 5563 reg = urtwn_read_4(sc, R92C_TDECTRL); 5564 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5565 urtwn_write_4(sc, R92C_TDECTRL, reg); 5566 /* Rx */ 5567 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5568 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5569 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5570 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5571 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5572 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5573 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5574 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5575 ISSET(sc->chip, URTWN_CHIP_92EU)) 5576 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5577 else 5578 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5579 5580 /* Initialize beacon parameters. */ 5581 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5582 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5583 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5584 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5585 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5586 5587 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5588 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5589 /* Setup AMPDU aggregation. */ 5590 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5591 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5592 urtwn_write_2(sc, 0x4ca, 0x0708); 5593 5594 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5595 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5596 } 5597 5598 /* Load 8051 microcode. */ 5599 error = urtwn_load_firmware(sc); 5600 if (error != 0) 5601 goto fail; 5602 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5603 5604 /* Initialize MAC/BB/RF blocks. */ 5605 /* 5606 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5607 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5608 * XXX: This setting should be removed from rtl8192cu_mac[]. 5609 */ 5610 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5611 urtwn_rxfilter_init(sc); // reset R92C_RCR 5612 urtwn_bb_init(sc); 5613 urtwn_rf_init(sc); 5614 5615 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5616 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5617 urtwn_write_2(sc, R92C_CR, 5618 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5619 R92C_CR_MACRXEN); 5620 } 5621 5622 /* Turn CCK and OFDM blocks on. */ 5623 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5624 reg |= R92C_RFMOD_CCK_EN; 5625 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5626 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5627 reg |= R92C_RFMOD_OFDM_EN; 5628 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5629 5630 /* Clear per-station keys table. */ 5631 urtwn_cam_init(sc); 5632 5633 /* Enable hardware sequence numbering. */ 5634 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5635 5636 /* Perform LO and IQ calibrations. */ 5637 urtwn_iq_calib(sc, sc->iqk_inited); 5638 sc->iqk_inited = true; 5639 5640 /* Perform LC calibration. */ 5641 urtwn_lc_calib(sc); 5642 5643 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5644 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5645 /* Fix USB interference issue. */ 5646 urtwn_write_1(sc, 0xfe40, 0xe0); 5647 urtwn_write_1(sc, 0xfe41, 0x8d); 5648 urtwn_write_1(sc, 0xfe42, 0x80); 5649 urtwn_write_4(sc, 0x20c, 0xfd0320); 5650 5651 urtwn_pa_bias_init(sc); 5652 } 5653 5654 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5655 !(sc->chip & URTWN_CHIP_92EU)) { 5656 /* 1T1R */ 5657 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5658 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5659 } 5660 5661 /* Initialize GPIO setting. */ 5662 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5663 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5664 5665 /* Fix for lower temperature. */ 5666 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5667 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5668 urtwn_write_1(sc, 0x15, 0xe9); 5669 5670 /* Set default channel. */ 5671 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5672 5673 /* Queue Rx xfers. */ 5674 for (size_t j = 0; j < sc->rx_npipe; j++) { 5675 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5676 data = &sc->rx_data[j][i]; 5677 usbd_setup_xfer(data->xfer, data, data->buf, 5678 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5679 urtwn_rxeof); 5680 error = usbd_transfer(data->xfer); 5681 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5682 error != USBD_IN_PROGRESS)) 5683 goto fail; 5684 } 5685 } 5686 5687 /* We're ready to go. */ 5688 ifp->if_flags &= ~IFF_OACTIVE; 5689 ifp->if_flags |= IFF_RUNNING; 5690 sc->sc_running = true; 5691 5692 mutex_exit(&sc->sc_write_mtx); 5693 5694 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5695 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5696 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5697 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5698 urtwn_wait_async(sc); 5699 5700 /* Init the rest of the 802.11 stuff */ 5701 ieee80211_init(ifp); 5702 5703 return 0; 5704 5705 fail: 5706 mutex_exit(&sc->sc_write_mtx); 5707 5708 urtwn_stop(ifp, 1); 5709 return error; 5710 } 5711 5712 static void 5713 urtwn_stop(struct ifnet *ifp, int disable) 5714 { 5715 struct ieee80211vap *vap = ifp->if_softc; 5716 struct ieee80211com *ic = vap->iv_ic; 5717 struct urtwn_softc *sc = ic->ic_softc; 5718 size_t i; 5719 int s; 5720 5721 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5722 5723 s = splusb(); 5724 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5725 urtwn_wait_async(sc); 5726 splx(s); 5727 5728 sc->tx_timer = 0; 5729 ifp->if_timer = 0; 5730 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5731 5732 callout_stop(&sc->sc_scan_to); 5733 callout_stop(&sc->sc_calib_to); 5734 5735 /* Abort Tx. */ 5736 for (i = 0; i < sc->tx_npipe; i++) { 5737 if (sc->tx_pipe[i] != NULL) 5738 usbd_abort_pipe(sc->tx_pipe[i]); 5739 } 5740 5741 /* Stop Rx pipe. */ 5742 for (i = 0; i < sc->rx_npipe; i++) { 5743 if (sc->rx_pipe[i] != NULL) 5744 usbd_abort_pipe(sc->rx_pipe[i]); 5745 } 5746 5747 /* Free Tx/Rx buffers. */ 5748 urtwn_free_tx_list(sc); 5749 urtwn_free_rx_list(sc); 5750 5751 sc->sc_running = false; 5752 if (disable) 5753 urtwn_chip_stop(sc); 5754 } 5755 5756 static int 5757 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5758 { 5759 struct ifnet *ifp = vap->iv_ifp; 5760 struct urtwn_softc *sc = ifp->if_softc; 5761 struct ieee80211com *ic = &sc->sc_ic; 5762 5763 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5764 return ENETRESET; 5765 5766 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5767 5768 return 0; 5769 } 5770 5771 static void 5772 urtwn_chip_stop(struct urtwn_softc *sc) 5773 { 5774 uint32_t reg; 5775 bool disabled = true; 5776 5777 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5778 5779 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5780 ISSET(sc->chip, URTWN_CHIP_92EU)) 5781 return; 5782 5783 mutex_enter(&sc->sc_write_mtx); 5784 5785 /* 5786 * RF Off Sequence 5787 */ 5788 /* Pause MAC TX queue */ 5789 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5790 5791 /* Disable RF */ 5792 urtwn_rf_write(sc, 0, 0, 0); 5793 5794 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5795 5796 /* Reset BB state machine */ 5797 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5798 R92C_SYS_FUNC_EN_USBD | 5799 R92C_SYS_FUNC_EN_USBA | 5800 R92C_SYS_FUNC_EN_BB_GLB_RST); 5801 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5802 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5803 5804 /* 5805 * Reset digital sequence 5806 */ 5807 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5808 /* Reset MCU ready status */ 5809 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5810 /* If firmware in ram code, do reset */ 5811 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5812 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5813 ISSET(sc->chip, URTWN_CHIP_92EU)) 5814 urtwn_r88e_fw_reset(sc); 5815 else 5816 urtwn_fw_reset(sc); 5817 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5818 } 5819 } 5820 5821 /* Reset MAC and Enable 8051 */ 5822 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5823 5824 /* Reset MCU ready status */ 5825 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5826 5827 if (disabled) { 5828 /* Disable MAC clock */ 5829 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5830 /* Disable AFE PLL */ 5831 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5832 /* Gated AFE DIG_CLOCK */ 5833 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5834 /* Isolated digital to PON */ 5835 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5836 } 5837 5838 /* 5839 * Pull GPIO PIN to balance level and LED control 5840 */ 5841 /* 1. Disable GPIO[7:0] */ 5842 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5843 5844 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5845 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5846 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5847 5848 /* Disable GPIO[10:8] */ 5849 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5850 5851 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5852 reg |= (((reg & 0x000f) << 4) | 0x0780); 5853 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5854 5855 /* Disable LED0 & 1 */ 5856 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5857 5858 /* 5859 * Reset digital sequence 5860 */ 5861 if (disabled) { 5862 /* Disable ELDR clock */ 5863 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5864 /* Isolated ELDR to PON */ 5865 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5866 } 5867 5868 /* 5869 * Disable analog sequence 5870 */ 5871 if (disabled) { 5872 /* Disable A15 power */ 5873 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5874 /* Disable digital core power */ 5875 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5876 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5877 ~R92C_LDOV12D_CTRL_LDV12_EN); 5878 } 5879 5880 /* Enter PFM mode */ 5881 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5882 5883 /* Set USB suspend */ 5884 urtwn_write_2(sc, R92C_APS_FSMCO, 5885 R92C_APS_FSMCO_APDM_HOST | 5886 R92C_APS_FSMCO_AFSM_HSUS | 5887 R92C_APS_FSMCO_PFM_ALDN); 5888 5889 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5890 5891 mutex_exit(&sc->sc_write_mtx); 5892 } 5893 5894 static void 5895 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5896 { 5897 if (sc->sc_running == false) 5898 DELAY(ms * 1000); 5899 else 5900 usbd_delay_ms(sc->sc_udev, ms); 5901 } 5902 5903 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5904 5905 #ifdef _MODULE 5906 #include "ioconf.c" 5907 #endif 5908 5909 static int 5910 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5911 { 5912 int error = 0; 5913 5914 switch (cmd) { 5915 case MODULE_CMD_INIT: 5916 #ifdef _MODULE 5917 error = config_init_component(cfdriver_ioconf_urtwn, 5918 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5919 #endif 5920 return error; 5921 case MODULE_CMD_FINI: 5922 #ifdef _MODULE 5923 error = config_fini_component(cfdriver_ioconf_urtwn, 5924 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5925 #endif 5926 return error; 5927 default: 5928 return ENOTTY; 5929 } 5930 } 5931
Indexes created Fri Oct 03 02:09:57 GMT 2025