if_urtwn.c revision 1.59.2.17
1 /* $NetBSD: if_urtwn.c,v 1.59.2.17 2020/04/27 07:37:01 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.17 2020/04/27 07:37:01 nat Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 /* urtwn data */ 227 static const uint8_t urtwn_chan_2ghz[] = 228 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 229 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct ieee80211vap *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 289 int); 290 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ieee80211vap *, u_long); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 /* Functions for wifi refresh */ 340 static struct ieee80211vap * 341 urtwn_vap_create(struct ieee80211com *, 342 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 343 const uint8_t [IEEE80211_ADDR_LEN], 344 const uint8_t [IEEE80211_ADDR_LEN]); 345 static void urtwn_vap_delete(struct ieee80211vap *); 346 static int urtwn_ioctl(struct ifnet *, u_long, void *); 347 static void urtwn_parent(struct ieee80211com *); 348 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 349 struct ieee80211_channel []); 350 static void urtwn_scan_start(struct ieee80211com *); 351 static void urtwn_scan_end(struct ieee80211com *); 352 static void urtwn_set_channel(struct ieee80211com *); 353 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 354 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 355 const struct ieee80211_bpf_params *); 356 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 363 364 static const uint16_t addaReg[] = { 365 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 366 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 367 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 368 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 369 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 370 }; 371 372 static int 373 urtwn_match(device_t parent, cfdata_t match, void *aux) 374 { 375 struct usb_attach_arg *uaa = aux; 376 377 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 378 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 379 } 380 381 static void 382 urtwn_attach(device_t parent, device_t self, void *aux) 383 { 384 struct urtwn_softc *sc = device_private(self); 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct usb_attach_arg *uaa = aux; 387 char *devinfop; 388 const struct urtwn_dev *dev; 389 usb_device_request_t req; 390 // NNN loop below size_t i; 391 int error; 392 393 sc->sc_dev = self; 394 sc->sc_udev = uaa->uaa_device; 395 396 /* Name the ic. */ 397 ic->ic_name = "urtwn"; 398 399 /* Driver Send queue, separate from the if send queue*/ 400 sc->sc_sendq.ifq_maxlen = 32; 401 /* NNN how should this be initialized? */ 402 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 403 sc->sc_sendq.ifq_len = 0; 404 sc->sc_sendq.ifq_drops = 0; 405 IFQ_LOCK_INIT(&sc->sc_sendq); 406 407 sc->chip = 0; 408 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 409 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 410 SET(sc->chip, URTWN_CHIP_88E); 411 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 412 SET(sc->chip, URTWN_CHIP_92EU); 413 414 aprint_naive("\n"); 415 aprint_normal("\n"); 416 417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 418 419 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 420 aprint_normal_dev(self, "%s\n", devinfop); 421 usbd_devinfo_free(devinfop); 422 423 req.bmRequestType = UT_WRITE_DEVICE; 424 req.bRequest = UR_SET_FEATURE; 425 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 426 USETW(req.wIndex, UHF_PORT_SUSPEND); 427 USETW(req.wLength, 0); 428 429 (void) usbd_do_request(sc->sc_udev, &req, 0); 430 431 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 432 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 434 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 435 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 436 437 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 438 439 /* NNN make these callouts use a vap ... in vap create??? */ 440 callout_init(&sc->sc_scan_to, 0); 441 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 442 callout_init(&sc->sc_calib_to, 0); 443 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 444 445 error = usbd_set_config_no(sc->sc_udev, 1, 0); 446 if (error != 0) { 447 aprint_error_dev(self, "failed to set configuration" 448 ", err=%s\n", usbd_errstr(error)); 449 goto fail; 450 } 451 452 /* Get the first interface handle. */ 453 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 454 if (error != 0) { 455 aprint_error_dev(self, "could not get interface handle\n"); 456 goto fail; 457 } 458 459 error = urtwn_read_chipid(sc); 460 if (error != 0) { 461 aprint_error_dev(self, "unsupported test chip\n"); 462 goto fail; 463 } 464 465 /* Determine number of Tx/Rx chains. */ 466 if (sc->chip & URTWN_CHIP_92C) { 467 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 468 sc->nrxchains = 2; 469 } else if (sc->chip & URTWN_CHIP_92EU) { 470 sc->ntxchains = 2; 471 sc->nrxchains = 2; 472 } else { 473 sc->ntxchains = 1; 474 sc->nrxchains = 1; 475 } 476 477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 478 ISSET(sc->chip, URTWN_CHIP_92EU)) 479 urtwn_r88e_read_rom(sc); 480 else 481 urtwn_read_rom(sc); 482 483 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 484 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 485 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 486 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 487 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 488 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 489 "8188CUS", sc->ntxchains, sc->nrxchains, 490 ether_sprintf(ic->ic_macaddr)); 491 492 error = urtwn_open_pipes(sc); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 495 goto fail; 496 } 497 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 498 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 499 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 500 501 /* 502 * Setup the 802.11 device. 503 */ 504 ic->ic_softc = sc; 505 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 506 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 507 508 /* Set device capabilities. */ 509 ic->ic_caps = 510 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 511 IEEE80211_C_IBSS | /* IBSS mode supported */ 512 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 513 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 514 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 515 IEEE80211_C_WME | /* 802.11e */ 516 IEEE80211_C_WPA; /* 802.11i */ 517 518 ic->ic_htcaps = 519 IEEE80211_HTC_HT | 520 IEEE80211_HTCAP_SHORTGI20 | /* short GI in 20MHz */ 521 #if 0 522 IEEE80211_HTCAP_MAXAMSDU_3839 | /* max A-MSDU length */ 523 #endif 524 IEEE80211_HTCAP_SMPS_OFF; /* SM PS mode disabled */ 525 #if 0 526 IEEE80211_HTCAP_CHWIDTH40 | /* 40 MHz channel width */ 527 IEEE80211_HTCAP_SHORTGI40; /* short GI in 40MHz */ 528 #endif 529 530 ic->ic_txstream = sc->ntxchains; 531 ic->ic_rxstream = sc->nrxchains; 532 533 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 534 535 #ifdef should_delete_NNN 536 /* Set supported .11b and .11g channels (1 through 14). */ 537 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 538 for (i = 0; i < 14; i++) { 539 ic->ic_channels[i].ic_freq = 540 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 541 ic->ic_channels[i].ic_flags = 542 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 543 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 544 } 545 #else 546 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 547 ic->ic_channels); 548 #endif 549 /* XXX issues here ... Figure out proper attach and vap creation */ 550 ieee80211_ifattach(ic); 551 552 /* override default methods NNN Need more here? */ 553 ic->ic_newassoc = urtwn_newassoc; 554 ic->ic_wme.wme_update = urtwn_wme_update; 555 ic->ic_vap_create = urtwn_vap_create; 556 ic->ic_vap_delete = urtwn_vap_delete; 557 ic->ic_parent = urtwn_parent; 558 ic->ic_scan_start = urtwn_scan_start; 559 ic->ic_scan_end = urtwn_scan_end; 560 ic->ic_set_channel = urtwn_set_channel; 561 ic->ic_transmit = urtwn_transmit; 562 // ic->ic_send_mgmt = urtwn_send_mgmt; 563 ic->ic_raw_xmit = urtwn_raw_xmit; 564 ic->ic_getradiocaps = urtwn_getradiocaps; 565 566 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 567 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 568 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 569 570 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 571 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 572 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 573 574 ieee80211_announce(ic); 575 576 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 577 578 if (!pmf_device_register(self, NULL, NULL)) 579 aprint_error_dev(self, "couldn't establish power handler\n"); 580 581 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 582 583 /* Should be called via an IOCTL. Temp call here for now. */ 584 585 struct ieee80211vap *vap = 586 urtwn_vap_create(ic, device_xname(sc->sc_dev), 587 device_unit(sc->sc_dev), IEEE80211_M_STA, 588 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 589 590 if (vap == NULL) { 591 /* Didn't work ... now what! */ 592 printf ("NNN vap_create didn't work ...\n"); 593 ieee80211_ifdetach(ic); 594 goto fail; 595 } 596 597 return; 598 599 fail: 600 sc->sc_dying = 1; 601 aprint_error_dev(self, "attach failed\n"); 602 } 603 604 static int 605 urtwn_detach(device_t self, int flags) 606 { 607 struct urtwn_softc *sc = device_private(self); 608 struct ieee80211com *ic = &sc->sc_ic; 609 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 610 struct ifnet *ifp = vap->iv_ifp; 611 int s; 612 613 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 614 615 pmf_device_deregister(self); 616 617 s = splusb(); 618 619 sc->sc_dying = 1; 620 621 callout_halt(&sc->sc_scan_to, NULL); 622 callout_halt(&sc->sc_calib_to, NULL); 623 624 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 625 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 626 NULL); 627 urtwn_stop(ifp, 0); 628 // vap_detach(...) ?? 629 630 ieee80211_ifdetach(&sc->sc_ic); 631 632 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 633 urtwn_close_pipes(sc); 634 } 635 636 /* sendq destroy */ 637 IFQ_PURGE(&sc->sc_sendq); 638 IFQ_LOCK_DESTROY(&sc->sc_sendq); 639 640 splx(s); 641 642 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 643 644 callout_destroy(&sc->sc_scan_to); 645 callout_destroy(&sc->sc_calib_to); 646 647 mutex_destroy(&sc->sc_write_mtx); 648 mutex_destroy(&sc->sc_fwcmd_mtx); 649 mutex_destroy(&sc->sc_tx_mtx); 650 mutex_destroy(&sc->sc_rx_mtx); 651 mutex_destroy(&sc->sc_task_mtx); 652 653 return 0; 654 } 655 656 static int 657 urtwn_activate(device_t self, enum devact act) 658 { 659 struct urtwn_softc *sc = device_private(self); 660 661 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 662 663 switch (act) { 664 case DVACT_DEACTIVATE: 665 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 666 667 return 0; 668 default: 669 return EOPNOTSUPP; 670 } 671 } 672 673 static int 674 urtwn_open_pipes(struct urtwn_softc *sc) 675 { 676 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 677 static uint8_t epaddr[R92C_MAX_EPOUT]; 678 static uint8_t rxepaddr[R92C_MAX_EPIN]; 679 usb_interface_descriptor_t *id; 680 usb_endpoint_descriptor_t *ed; 681 size_t i, ntx = 0, nrx = 0; 682 int error; 683 684 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 685 686 /* Determine the number of bulk-out pipes. */ 687 id = usbd_get_interface_descriptor(sc->sc_iface); 688 for (i = 0; i < id->bNumEndpoints; i++) { 689 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 690 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 691 continue; 692 } 693 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 694 if (ntx < sizeof(epaddr)) 695 epaddr[ntx] = ed->bEndpointAddress; 696 ntx++; 697 } 698 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 699 if (nrx < sizeof(rxepaddr)) 700 rxepaddr[nrx] = ed->bEndpointAddress; 701 nrx++; 702 } 703 } 704 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 705 aprint_error_dev(sc->sc_dev, 706 "%zd: invalid number of Rx bulk pipes\n", nrx); 707 return EIO; 708 } 709 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 710 aprint_error_dev(sc->sc_dev, 711 "%zd: invalid number of Tx bulk pipes\n", ntx); 712 return EIO; 713 } 714 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 715 device_xname(sc->sc_dev), __func__, nrx, ntx)); 716 sc->rx_npipe = nrx; 717 sc->tx_npipe = ntx; 718 719 /* Open bulk-in pipe at address 0x81. */ 720 for (i = 0; i < nrx; i++) { 721 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 722 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 723 if (error != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "could not open Rx bulk pipe 0x%02x: %d\n", 726 rxepaddr[i], error); 727 goto fail; 728 } 729 } 730 731 /* Open bulk-out pipes (up to 3). */ 732 for (i = 0; i < ntx; i++) { 733 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 734 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 735 if (error != 0) { 736 aprint_error_dev(sc->sc_dev, 737 "could not open Tx bulk pipe 0x%02x: %d\n", 738 epaddr[i], error); 739 goto fail; 740 } 741 } 742 743 /* Map 802.11 access categories to USB pipes. */ 744 sc->ac2idx[WME_AC_BK] = 745 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 746 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 747 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 748 749 fail: 750 if (error != 0) 751 urtwn_close_pipes(sc); 752 return error; 753 } 754 755 static void 756 urtwn_close_pipes(struct urtwn_softc *sc) 757 { 758 struct usbd_pipe *pipe; 759 size_t i; 760 761 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 762 763 /* Close Rx pipes. */ 764 CTASSERT(sizeof(pipe) == sizeof(void *)); 765 for (i = 0; i < sc->rx_npipe; i++) { 766 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 767 if (pipe != NULL) { 768 usbd_close_pipe(pipe); 769 } 770 } 771 772 /* Close Tx pipes. */ 773 for (i = 0; i < sc->tx_npipe; i++) { 774 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 775 if (pipe != NULL) { 776 usbd_close_pipe(pipe); 777 } 778 } 779 } 780 781 static int 782 urtwn_alloc_rx_list(struct urtwn_softc *sc) 783 { 784 struct urtwn_rx_data *data; 785 size_t i; 786 int error = 0; 787 788 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 789 790 for (size_t j = 0; j < sc->rx_npipe; j++) { 791 TAILQ_INIT(&sc->rx_free_list[j]); 792 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 793 data = &sc->rx_data[j][i]; 794 795 data->sc = sc; /* Backpointer for callbacks. */ 796 797 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 798 0, 0, &data->xfer); 799 if (error) { 800 aprint_error_dev(sc->sc_dev, 801 "could not allocate xfer\n"); 802 break; 803 } 804 805 data->buf = usbd_get_buffer(data->xfer); 806 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 807 } 808 } 809 if (error != 0) 810 urtwn_free_rx_list(sc); 811 return error; 812 } 813 814 static void 815 urtwn_free_rx_list(struct urtwn_softc *sc) 816 { 817 struct urtwn_rx_data *data = NULL; 818 struct usbd_xfer *xfer; 819 820 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 821 822 /* NB: Caller must abort pipe first. */ 823 for (size_t j = 0; j < sc->rx_npipe; j++) { 824 mutex_enter(&sc->sc_rx_mtx); 825 while (!TAILQ_EMPTY(&sc->rx_free_list[j])) { 826 data = TAILQ_FIRST(&sc->rx_free_list[j]); 827 TAILQ_REMOVE(&sc->rx_free_list[j], data, next); 828 CTASSERT(sizeof(xfer) == sizeof(void *)); 829 xfer = atomic_swap_ptr(&data->xfer, NULL); 830 if (xfer != NULL) 831 usbd_destroy_xfer(xfer); 832 } 833 mutex_exit(&sc->sc_rx_mtx); 834 } 835 } 836 837 static int 838 urtwn_alloc_tx_list(struct urtwn_softc *sc) 839 { 840 struct urtwn_tx_data *data; 841 size_t i; 842 int error = 0; 843 844 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 845 846 mutex_enter(&sc->sc_tx_mtx); 847 for (size_t j = 0; j < sc->tx_npipe; j++) { 848 TAILQ_INIT(&sc->tx_free_list[j]); 849 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 850 data = &sc->tx_data[j][i]; 851 852 data->sc = sc; /* Backpointer for callbacks. */ 853 data->pidx = j; 854 855 error = usbd_create_xfer(sc->tx_pipe[j], 856 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 857 &data->xfer); 858 if (error) { 859 aprint_error_dev(sc->sc_dev, 860 "could not allocate xfer\n"); 861 goto fail; 862 } 863 864 data->buf = usbd_get_buffer(data->xfer); 865 866 /* Append this Tx buffer to our free list. */ 867 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 868 } 869 } 870 mutex_exit(&sc->sc_tx_mtx); 871 return 0; 872 873 fail: 874 urtwn_free_tx_list(sc); 875 mutex_exit(&sc->sc_tx_mtx); 876 return error; 877 } 878 879 static void 880 urtwn_free_tx_list(struct urtwn_softc *sc) 881 { 882 struct urtwn_tx_data *data = NULL; 883 struct usbd_xfer *xfer; 884 885 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 886 887 /* NB: Caller must abort pipe first. */ 888 for (size_t j = 0; j < sc->tx_npipe; j++) { 889 mutex_enter(&sc->sc_tx_mtx); 890 while (!TAILQ_EMPTY(&sc->tx_free_list[j])) { 891 data = TAILQ_FIRST(&sc->tx_free_list[j]); 892 TAILQ_REMOVE(&sc->tx_free_list[j], data, next); 893 CTASSERT(sizeof(xfer) == sizeof(void *)); 894 xfer = atomic_swap_ptr(&data->xfer, NULL); 895 if (xfer != NULL) 896 usbd_destroy_xfer(xfer); 897 } 898 mutex_exit(&sc->sc_tx_mtx); 899 } 900 } 901 902 static int 903 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 904 struct ieee80211_node *ni) 905 { 906 struct urtwn_tx_data *data = 907 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 908 return urtwn_tx(sc, m, ni, data); 909 } 910 911 static void 912 urtwn_task(void *arg) 913 { 914 struct urtwn_softc *sc = arg; 915 struct ieee80211com *ic = &sc->sc_ic; 916 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 917 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 918 struct urtwn_host_cmd *cmd; 919 int s; 920 921 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 922 if (vap->iv_state == IEEE80211_S_RUN && 923 (ic->ic_opmode == IEEE80211_M_HOSTAP || 924 ic->ic_opmode == IEEE80211_M_IBSS)) { 925 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 926 if (m == NULL) { 927 aprint_error_dev(sc->sc_dev, 928 "could not allocate beacon"); 929 } 930 931 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 932 m_freem(m); 933 aprint_error_dev(sc->sc_dev, "could not send beacon"); 934 } 935 936 /* beacon is no longer needed */ 937 m_freem(m); 938 } 939 940 /* Process host commands. */ 941 s = splusb(); 942 mutex_spin_enter(&sc->sc_task_mtx); 943 while (ring->next != ring->cur) { 944 cmd = &ring->cmd[ring->next]; 945 mutex_spin_exit(&sc->sc_task_mtx); 946 splx(s); 947 /* Invoke callback with kernel lock held. */ 948 cmd->cb(sc, cmd->data); 949 s = splusb(); 950 mutex_spin_enter(&sc->sc_task_mtx); 951 ring->queued--; 952 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 953 } 954 mutex_spin_exit(&sc->sc_task_mtx); 955 wakeup(&sc->cmdq); 956 splx(s); 957 } 958 959 static void 960 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 961 void *arg, int len) 962 { 963 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 964 struct urtwn_host_cmd *cmd; 965 int s; 966 967 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 968 device_xname(sc->sc_dev), __func__, cb, arg, len)); 969 970 s = splusb(); 971 mutex_spin_enter(&sc->sc_task_mtx); 972 cmd = &ring->cmd[ring->cur]; 973 cmd->cb = cb; 974 KASSERT(len <= sizeof(cmd->data)); 975 memcpy(cmd->data, arg, len); 976 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 977 978 /* If there is no pending command already, schedule a task. */ 979 if (!sc->sc_dying && ++ring->queued == 1) { 980 mutex_spin_exit(&sc->sc_task_mtx); 981 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 982 } else 983 mutex_spin_exit(&sc->sc_task_mtx); 984 splx(s); 985 } 986 987 static void 988 urtwn_wait_async(struct urtwn_softc *sc) 989 { 990 991 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 992 993 /* Wait for all queued asynchronous commands to complete. */ 994 while (sc->cmdq.queued > 0) 995 tsleep(&sc->cmdq, 0, "endtask", 0); 996 } 997 998 static int 999 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1000 int len) 1001 { 1002 usb_device_request_t req; 1003 usbd_status error; 1004 1005 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1006 1007 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1008 req.bRequest = R92C_REQ_REGS; 1009 USETW(req.wValue, addr); 1010 USETW(req.wIndex, 0); 1011 USETW(req.wLength, len); 1012 error = usbd_do_request(sc->sc_udev, &req, buf); 1013 if (error != USBD_NORMAL_COMPLETION) { 1014 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1015 device_xname(sc->sc_dev), __func__, error, addr, len)); 1016 } 1017 return error; 1018 } 1019 1020 static void 1021 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1022 { 1023 1024 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1025 device_xname(sc->sc_dev), __func__, addr, val)); 1026 1027 urtwn_write_region_1(sc, addr, &val, 1); 1028 } 1029 1030 static void 1031 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1032 { 1033 uint8_t buf[2]; 1034 1035 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1036 device_xname(sc->sc_dev), __func__, addr, val)); 1037 1038 buf[0] = (uint8_t)val; 1039 buf[1] = (uint8_t)(val >> 8); 1040 urtwn_write_region_1(sc, addr, buf, 2); 1041 } 1042 1043 static void 1044 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1045 { 1046 uint8_t buf[4]; 1047 1048 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1049 device_xname(sc->sc_dev), __func__, addr, val)); 1050 1051 buf[0] = (uint8_t)val; 1052 buf[1] = (uint8_t)(val >> 8); 1053 buf[2] = (uint8_t)(val >> 16); 1054 buf[3] = (uint8_t)(val >> 24); 1055 urtwn_write_region_1(sc, addr, buf, 4); 1056 } 1057 1058 static int 1059 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1060 { 1061 1062 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, len=%#x\n", 1063 device_xname(sc->sc_dev), __func__, addr, len)); 1064 1065 return urtwn_write_region_1(sc, addr, buf, len); 1066 } 1067 1068 static int 1069 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1070 int len) 1071 { 1072 usb_device_request_t req; 1073 usbd_status error; 1074 1075 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1076 req.bRequest = R92C_REQ_REGS; 1077 USETW(req.wValue, addr); 1078 USETW(req.wIndex, 0); 1079 USETW(req.wLength, len); 1080 error = usbd_do_request(sc->sc_udev, &req, buf); 1081 if (error != USBD_NORMAL_COMPLETION) { 1082 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1083 device_xname(sc->sc_dev), __func__, error, addr, len)); 1084 } 1085 return error; 1086 } 1087 1088 static uint8_t 1089 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1090 { 1091 uint8_t val; 1092 1093 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1094 return 0xff; 1095 1096 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1097 device_xname(sc->sc_dev), __func__, addr, val)); 1098 return val; 1099 } 1100 1101 static uint16_t 1102 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1103 { 1104 uint8_t buf[2]; 1105 uint16_t val; 1106 1107 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1108 return 0xffff; 1109 1110 val = LE_READ_2(&buf[0]); 1111 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1112 device_xname(sc->sc_dev), __func__, addr, val)); 1113 return val; 1114 } 1115 1116 static uint32_t 1117 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1118 { 1119 uint8_t buf[4]; 1120 uint32_t val; 1121 1122 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1123 return 0xffffffff; 1124 1125 val = LE_READ_4(&buf[0]); 1126 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1127 device_xname(sc->sc_dev), __func__, addr, val)); 1128 return val; 1129 } 1130 1131 static int 1132 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1133 { 1134 struct r92c_fw_cmd cmd; 1135 uint8_t *cp; 1136 int fwcur; 1137 int ntries; 1138 1139 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1140 device_xname(sc->sc_dev), __func__, id, buf, len)); 1141 1142 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1143 1144 mutex_enter(&sc->sc_fwcmd_mtx); 1145 fwcur = sc->fwcur; 1146 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1147 mutex_exit(&sc->sc_fwcmd_mtx); 1148 1149 /* Wait for current FW box to be empty. */ 1150 for (ntries = 0; ntries < 100; ntries++) { 1151 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1152 break; 1153 DELAY(2000); 1154 } 1155 if (ntries == 100) { 1156 aprint_error_dev(sc->sc_dev, 1157 "could not send firmware command %d\n", id); 1158 return ETIMEDOUT; 1159 } 1160 1161 memset(&cmd, 0, sizeof(cmd)); 1162 KASSERT(len <= sizeof(cmd.msg)); 1163 memcpy(cmd.msg, buf, len); 1164 1165 /* Write the first word last since that will trigger the FW. */ 1166 cp = (uint8_t *)&cmd; 1167 cmd.id = id; 1168 if (len >= 4) { 1169 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1170 cmd.id |= R92C_CMD_FLAG_EXT; 1171 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1172 &cp[1], 2); 1173 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1174 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1175 (cp[5] << 24)); 1176 } else { 1177 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1178 &cp[4], 2); 1179 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1180 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1181 (cp[3] << 24)); 1182 } 1183 } else { 1184 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1185 } 1186 1187 return 0; 1188 } 1189 1190 static __inline void 1191 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1192 { 1193 1194 sc->sc_rf_write(sc, chain, addr, val); 1195 } 1196 1197 static void 1198 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1199 uint32_t val) 1200 { 1201 1202 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1203 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1204 } 1205 1206 static void 1207 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1208 uint32_t val) 1209 { 1210 1211 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1212 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1213 } 1214 1215 static void 1216 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1217 uint32_t val) 1218 { 1219 1220 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1221 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1222 } 1223 1224 static uint32_t 1225 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1226 { 1227 uint32_t reg[R92C_MAX_CHAINS], val; 1228 1229 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1230 if (chain != 0) { 1231 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1232 } 1233 1234 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1235 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1236 DELAY(1000); 1237 1238 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1239 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1240 R92C_HSSI_PARAM2_READ_EDGE); 1241 DELAY(1000); 1242 1243 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1244 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1245 DELAY(1000); 1246 1247 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1248 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1249 } else { 1250 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1251 } 1252 return MS(val, R92C_LSSI_READBACK_DATA); 1253 } 1254 1255 static int 1256 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1257 { 1258 int ntries; 1259 1260 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1261 1262 urtwn_write_4(sc, R92C_LLT_INIT, 1263 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1264 SM(R92C_LLT_INIT_ADDR, addr) | 1265 SM(R92C_LLT_INIT_DATA, data)); 1266 /* Wait for write operation to complete. */ 1267 for (ntries = 0; ntries < 20; ntries++) { 1268 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1269 R92C_LLT_INIT_OP_NO_ACTIVE) { 1270 /* Done */ 1271 return 0; 1272 } 1273 DELAY(5); 1274 } 1275 return ETIMEDOUT; 1276 } 1277 1278 static uint8_t 1279 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1280 { 1281 uint32_t reg; 1282 int ntries; 1283 1284 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1285 1286 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1287 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1288 reg &= ~R92C_EFUSE_CTRL_VALID; 1289 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1290 1291 /* Wait for read operation to complete. */ 1292 for (ntries = 0; ntries < 100; ntries++) { 1293 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1294 if (reg & R92C_EFUSE_CTRL_VALID) { 1295 /* Done */ 1296 return MS(reg, R92C_EFUSE_CTRL_DATA); 1297 } 1298 DELAY(5); 1299 } 1300 aprint_error_dev(sc->sc_dev, 1301 "could not read efuse byte at address 0x%04x\n", addr); 1302 return 0xff; 1303 } 1304 1305 static void 1306 urtwn_efuse_read(struct urtwn_softc *sc) 1307 { 1308 uint8_t *rom = (uint8_t *)&sc->rom; 1309 uint32_t reg; 1310 uint16_t addr = 0; 1311 uint8_t off, msk; 1312 size_t i; 1313 1314 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1315 1316 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1317 1318 urtwn_efuse_switch_power(sc); 1319 1320 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1321 while (addr < 512) { 1322 reg = urtwn_efuse_read_1(sc, addr); 1323 if (reg == 0xff) 1324 break; 1325 addr++; 1326 off = reg >> 4; 1327 msk = reg & 0xf; 1328 for (i = 0; i < 4; i++) { 1329 if (msk & (1U << i)) 1330 continue; 1331 1332 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1333 addr++; 1334 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1335 addr++; 1336 } 1337 } 1338 #ifdef URTWN_DEBUG 1339 if (urtwn_debug & DBG_INIT) { 1340 /* Dump ROM content. */ 1341 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1342 for (i = 0; i < (int)sizeof(sc->rom); i++) 1343 printf(":%02x", rom[i]); 1344 printf("\n"); 1345 } 1346 #endif 1347 } 1348 1349 static void 1350 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1351 { 1352 uint32_t reg; 1353 1354 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1355 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1356 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1357 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1358 } 1359 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1360 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1361 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1362 reg | R92C_SYS_FUNC_EN_ELDR); 1363 } 1364 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1365 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1366 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1367 urtwn_write_2(sc, R92C_SYS_CLKR, 1368 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1369 } 1370 } 1371 1372 static int 1373 urtwn_read_chipid(struct urtwn_softc *sc) 1374 { 1375 uint32_t reg; 1376 1377 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1378 1379 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1380 ISSET(sc->chip, URTWN_CHIP_92EU)) 1381 return 0; 1382 1383 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1384 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1385 /* test chip, not supported */ 1386 return EIO; 1387 } 1388 if (reg & R92C_SYS_CFG_TYPE_92C) { 1389 sc->chip |= URTWN_CHIP_92C; 1390 /* Check if it is a castrated 8192C. */ 1391 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1392 R92C_HPON_FSM_CHIP_BONDING_ID) == 1393 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1394 sc->chip |= URTWN_CHIP_92C_1T2R; 1395 } 1396 } 1397 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1398 sc->chip |= URTWN_CHIP_UMC; 1399 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1400 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1401 } 1402 } 1403 return 0; 1404 } 1405 1406 #ifdef URTWN_DEBUG 1407 static void 1408 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1409 { 1410 1411 aprint_normal_dev(sc->sc_dev, 1412 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1413 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1414 1415 aprint_normal_dev(sc->sc_dev, 1416 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1417 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1418 1419 aprint_normal_dev(sc->sc_dev, 1420 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1421 rp->macaddr[0], rp->macaddr[1], 1422 rp->macaddr[2], rp->macaddr[3], 1423 rp->macaddr[4], rp->macaddr[5]); 1424 1425 aprint_normal_dev(sc->sc_dev, 1426 "string %s, subcustomer_id %#x\n", 1427 rp->string, rp->subcustomer_id); 1428 1429 aprint_normal_dev(sc->sc_dev, 1430 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1431 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1432 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1433 1434 aprint_normal_dev(sc->sc_dev, 1435 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1436 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1437 rp->ht40_1s_tx_pwr[0][2], 1438 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1439 rp->ht40_1s_tx_pwr[1][2]); 1440 1441 aprint_normal_dev(sc->sc_dev, 1442 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1443 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1444 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1445 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1446 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1447 1448 aprint_normal_dev(sc->sc_dev, 1449 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1450 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1451 rp->ht20_tx_pwr_diff[2] & 0xf, 1452 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1453 rp->ht20_tx_pwr_diff[2] >> 4); 1454 1455 aprint_normal_dev(sc->sc_dev, 1456 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1457 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1458 rp->ofdm_tx_pwr_diff[2] & 0xf, 1459 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1460 rp->ofdm_tx_pwr_diff[2] >> 4); 1461 1462 aprint_normal_dev(sc->sc_dev, 1463 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1464 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1465 rp->ht40_max_pwr[2] & 0xf, 1466 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1467 rp->ht40_max_pwr[2] >> 4); 1468 1469 aprint_normal_dev(sc->sc_dev, 1470 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1471 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1472 rp->ht20_max_pwr[2] & 0xf, 1473 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1474 rp->ht20_max_pwr[2] >> 4); 1475 1476 aprint_normal_dev(sc->sc_dev, 1477 "xtal_calib %d, tssi %d %d, thermal %d\n", 1478 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1479 1480 aprint_normal_dev(sc->sc_dev, 1481 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1482 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1483 1484 aprint_normal_dev(sc->sc_dev, 1485 "channnel_plan %d, version %d customer_id %#x\n", 1486 rp->channel_plan, rp->version, rp->curstomer_id); 1487 } 1488 #endif 1489 1490 static void 1491 urtwn_read_rom(struct urtwn_softc *sc) 1492 { 1493 struct ieee80211com *ic = &sc->sc_ic; 1494 struct r92c_rom *rom = &sc->rom; 1495 1496 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1497 1498 mutex_enter(&sc->sc_write_mtx); 1499 1500 /* Read full ROM image. */ 1501 urtwn_efuse_read(sc); 1502 #ifdef URTWN_DEBUG 1503 if (urtwn_debug & DBG_REG) 1504 urtwn_dump_rom(sc, rom); 1505 #endif 1506 1507 /* XXX Weird but this is what the vendor driver does. */ 1508 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1509 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1510 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1511 1512 DPRINTFN(DBG_INIT, 1513 ("%s: %s: PA setting=%#x, board=%#x, regulatory=%d\n", 1514 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1515 sc->board_type, sc->regulatory)); 1516 1517 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1518 1519 sc->sc_rf_write = urtwn_r92c_rf_write; 1520 sc->sc_power_on = urtwn_r92c_power_on; 1521 sc->sc_dma_init = urtwn_r92c_dma_init; 1522 1523 mutex_exit(&sc->sc_write_mtx); 1524 } 1525 1526 static void 1527 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1528 { 1529 struct ieee80211com *ic = &sc->sc_ic; 1530 uint8_t *rom = sc->r88e_rom; 1531 uint32_t reg; 1532 uint16_t addr = 0; 1533 uint8_t off, msk, tmp; 1534 int i; 1535 1536 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1537 1538 mutex_enter(&sc->sc_write_mtx); 1539 1540 off = 0; 1541 urtwn_efuse_switch_power(sc); 1542 1543 /* Read full ROM image. */ 1544 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1545 while (addr < 4096) { 1546 reg = urtwn_efuse_read_1(sc, addr); 1547 if (reg == 0xff) 1548 break; 1549 addr++; 1550 if ((reg & 0x1f) == 0x0f) { 1551 tmp = (reg & 0xe0) >> 5; 1552 reg = urtwn_efuse_read_1(sc, addr); 1553 if ((reg & 0x0f) != 0x0f) 1554 off = ((reg & 0xf0) >> 1) | tmp; 1555 addr++; 1556 } else 1557 off = reg >> 4; 1558 msk = reg & 0xf; 1559 for (i = 0; i < 4; i++) { 1560 if (msk & (1 << i)) 1561 continue; 1562 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1563 addr++; 1564 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1565 addr++; 1566 } 1567 } 1568 #ifdef URTWN_DEBUG 1569 if (urtwn_debug & DBG_REG) { 1570 } 1571 #endif 1572 1573 addr = 0x10; 1574 for (i = 0; i < 6; i++) 1575 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1576 for (i = 0; i < 5; i++) 1577 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1578 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1579 if (sc->bw20_tx_pwr_diff & 0x08) 1580 sc->bw20_tx_pwr_diff |= 0xf0; 1581 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1582 if (sc->ofdm_tx_pwr_diff & 0x08) 1583 sc->ofdm_tx_pwr_diff |= 0xf0; 1584 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1585 1586 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1587 1588 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1589 sc->sc_power_on = urtwn_r92e_power_on; 1590 sc->sc_rf_write = urtwn_r92e_rf_write; 1591 } else { 1592 sc->sc_power_on = urtwn_r88e_power_on; 1593 sc->sc_rf_write = urtwn_r88e_rf_write; 1594 } 1595 sc->sc_dma_init = urtwn_r88e_dma_init; 1596 1597 mutex_exit(&sc->sc_write_mtx); 1598 } 1599 1600 /* NNN Do we need to do something with this? */ 1601 1602 static __unused int 1603 urtwn_media_change(struct ifnet *ifp) 1604 { 1605 #ifdef URTWN_DEBUG 1606 struct ieee80211vap *vap = ifp->if_softc; 1607 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1608 #endif 1609 int error; 1610 1611 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1612 1613 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1614 return error; 1615 1616 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1617 (IFF_UP | IFF_RUNNING)) { 1618 urtwn_init(ifp); 1619 } 1620 return 0; 1621 } 1622 1623 /* 1624 * Initialize rate adaptation in firmware. 1625 */ 1626 static int 1627 urtwn_ra_init(struct ieee80211vap *vap) 1628 { 1629 static const uint8_t map[] = { 1630 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1631 }; 1632 struct ieee80211com *ic = vap->iv_ic; 1633 struct urtwn_softc *sc = ic->ic_softc; 1634 struct ieee80211_node *ni = vap->iv_bss; 1635 struct ieee80211_rateset *rs = &ni->ni_rates; 1636 1637 struct r92c_fw_cmd_macid_cfg cmd; 1638 uint32_t rates, basicrates; 1639 uint32_t rrsr_mask, rrsr_rate; 1640 uint8_t mode; 1641 size_t maxrate, maxbasicrate, i, j; 1642 int error; 1643 1644 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1645 1646 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1647 1648 /* Get normal and basic rates mask. */ 1649 rates = basicrates = 1; 1650 maxrate = maxbasicrate = 0; 1651 for (i = 0; i < rs->rs_nrates; i++) { 1652 /* Convert 802.11 rate to HW rate index. */ 1653 for (j = 0; j < __arraycount(map); j++) { 1654 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1655 break; 1656 } 1657 } 1658 if (j == __arraycount(map)) { 1659 /* Unknown rate, skip. */ 1660 continue; 1661 } 1662 1663 rates |= 1U << j; 1664 if (j > maxrate) { 1665 maxrate = j; 1666 } 1667 1668 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1669 basicrates |= 1U << j; 1670 if (j > maxbasicrate) { 1671 maxbasicrate = j; 1672 } 1673 } 1674 } 1675 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1676 mode = R92C_RAID_11B; 1677 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 1678 mode = R92C_RAID_11BG; 1679 } else /* mode = IEEE80211_MODE_11NG */ 1680 mode = R92C_RAID_11GN; 1681 DPRINTFN(DBG_INIT, ("%s: %s: mode=%#x rates=%#x, basicrates=%#x, " 1682 "maxrate=%zx, maxbasicrate=%zx\n", 1683 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1684 maxrate, maxbasicrate)); 1685 1686 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1687 maxbasicrate |= R92C_RATE_SHORTGI; 1688 maxrate |= R92C_RATE_SHORTGI; 1689 } 1690 1691 /* Set rates mask for group addressed frames. */ 1692 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1693 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1694 cmd.macid |= RTWN_MACID_SHORTGI; 1695 cmd.mask = htole32((mode << 28) | basicrates); 1696 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1697 if (error != 0) { 1698 aprint_error_dev(sc->sc_dev, 1699 "could not add broadcast station\n"); 1700 return error; 1701 } 1702 /* Set initial MRR rate. */ 1703 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1704 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1705 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1706 1707 /* Set rates mask for unicast frames. */ 1708 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1709 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1710 cmd.macid |= RTWN_MACID_SHORTGI; 1711 cmd.mask = htole32((mode << 28) | rates); 1712 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1713 if (error != 0) { 1714 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1715 return error; 1716 } 1717 /* Set initial MRR rate. */ 1718 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1719 __func__, maxrate)); 1720 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1721 1722 #if notyet 1723 /* NNN appears to have no fixed rate anywhere. */ 1724 rrsr_rate = ic->ic_fixed_rate; 1725 if (rrsr_rate == -1) 1726 #endif 1727 rrsr_rate = 11; 1728 1729 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1730 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1731 1732 #if notyet 1733 /* Indicate highest supported rate. */ 1734 ni->ni_txrate = rs->rs_nrates - 1; 1735 #endif 1736 return 0; 1737 } 1738 1739 static int 1740 urtwn_get_nettype(struct urtwn_softc *sc) 1741 { 1742 struct ieee80211com *ic = &sc->sc_ic; 1743 int type; 1744 1745 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1746 1747 switch (ic->ic_opmode) { 1748 case IEEE80211_M_STA: 1749 type = R92C_CR_NETTYPE_INFRA; 1750 break; 1751 1752 case IEEE80211_M_IBSS: 1753 type = R92C_CR_NETTYPE_ADHOC; 1754 break; 1755 1756 default: 1757 type = R92C_CR_NETTYPE_NOLINK; 1758 break; 1759 } 1760 1761 return type; 1762 } 1763 1764 static void 1765 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1766 { 1767 uint8_t reg; 1768 1769 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1770 __func__, type)); 1771 1772 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1773 1774 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1775 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1776 } 1777 1778 static void 1779 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1780 { 1781 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1782 struct ieee80211_node *ni = vap->iv_bss; 1783 uint64_t tsf; 1784 1785 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1786 1787 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1788 1789 /* Enable TSF synchronization. */ 1790 urtwn_write_1(sc, R92C_BCN_CTRL, 1791 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1792 1793 /* Correct TSF */ 1794 urtwn_write_1(sc, R92C_BCN_CTRL, 1795 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1796 1797 /* Set initial TSF. */ 1798 tsf = ni->ni_tstamp.tsf; 1799 tsf = le64toh(tsf); 1800 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1801 tsf -= IEEE80211_DUR_TU; 1802 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1803 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1804 1805 urtwn_write_1(sc, R92C_BCN_CTRL, 1806 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1807 } 1808 1809 static void 1810 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1811 { 1812 uint8_t reg; 1813 1814 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1815 __func__, led, on)); 1816 1817 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1818 1819 if (led == URTWN_LED_LINK) { 1820 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1821 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1822 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1823 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1824 (R92C_LEDCFG0_DIS << 1)); 1825 if (on) { 1826 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1827 R92E_LEDSON; 1828 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1829 } 1830 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1831 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1832 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1833 if (!on) { 1834 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1835 urtwn_write_1(sc, R92C_LEDCFG2, 1836 reg | R92C_LEDCFG0_DIS); 1837 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1838 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1839 reg & 0xfe); 1840 } 1841 } else { 1842 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1843 if (!on) { 1844 reg |= R92C_LEDCFG0_DIS; 1845 } 1846 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1847 } 1848 sc->ledlink = on; /* Save LED state. */ 1849 } 1850 } 1851 1852 static void 1853 urtwn_calib_to(void *arg) 1854 { 1855 struct urtwn_softc *sc = arg; 1856 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1857 1858 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1859 1860 if (sc->sc_dying) 1861 return; 1862 1863 /* Do it in a process context. */ 1864 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1865 } 1866 1867 /* ARGSUSED */ 1868 static void 1869 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1870 { 1871 struct ieee80211vap *vap = arg; 1872 struct r92c_fw_cmd_rssi cmd; 1873 struct r92e_fw_cmd_rssi cmde; 1874 1875 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1876 1877 if (vap->iv_state != IEEE80211_S_RUN) 1878 goto restart_timer; 1879 1880 mutex_enter(&sc->sc_write_mtx); 1881 if (sc->avg_pwdb != -1) { 1882 /* Indicate Rx signal strength to FW for rate adaptation. */ 1883 memset(&cmd, 0, sizeof(cmd)); 1884 memset(&cmde, 0, sizeof(cmde)); 1885 cmd.macid = 0; /* BSS. */ 1886 cmde.macid = 0; /* BSS. */ 1887 cmd.pwdb = sc->avg_pwdb; 1888 cmde.pwdb = sc->avg_pwdb; 1889 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1890 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1891 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1892 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1893 sizeof(cmd)); 1894 } else { 1895 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1896 sizeof(cmde)); 1897 } 1898 } 1899 1900 /* Do temperature compensation. */ 1901 urtwn_temp_calib(sc); 1902 mutex_exit(&sc->sc_write_mtx); 1903 1904 restart_timer: 1905 if (!sc->sc_dying) { 1906 /* Restart calibration timer. */ 1907 callout_schedule(&sc->sc_calib_to, hz); 1908 } 1909 } 1910 1911 static void 1912 urtwn_next_scan(void *arg) 1913 { 1914 printf ("NNN urtwn_next_scan called....\n"); 1915 #ifdef notyet 1916 struct urtwn_softc *sc = arg; 1917 int s; 1918 1919 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1920 1921 if (sc->sc_dying) 1922 return; 1923 1924 s = splnet(); 1925 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1926 ieee80211_next_scan(&sc->sc_ic); 1927 splx(s); 1928 #endif 1929 } 1930 1931 static void 1932 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1933 { 1934 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1935 ether_sprintf(ni->ni_macaddr))); 1936 1937 /* start with lowest Tx rate */ 1938 ni->ni_txrate = 0; 1939 } 1940 1941 #if OLDSTUFF 1942 static int 1943 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1944 { 1945 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1946 struct urtwn_cmd_newstate cmd; 1947 1948 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1949 device_xname(sc->sc_dev), __func__, 1950 ieee80211_state_name[nstate], nstate, arg)); 1951 1952 callout_stop(&sc->sc_scan_to); 1953 callout_stop(&sc->sc_calib_to); 1954 1955 /* Do it in a process context. */ 1956 cmd.state = nstate; 1957 cmd.arg = arg; 1958 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1959 return 0; 1960 } 1961 1962 static void 1963 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1964 { 1965 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1966 struct urtwn_cmd_newstate *cmd = arg; 1967 struct ieee80211com *ic = &sc->sc_ic; 1968 struct ieee80211_node *ni; 1969 enum ieee80211_state ostate = vap->iv_state; 1970 enum ieee80211_state nstate = cmd->state; 1971 uint32_t reg; 1972 uint8_t sifs_time, msr; 1973 int s; 1974 1975 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1976 device_xname(sc->sc_dev), __func__, 1977 ieee80211_state_name[ostate], ostate, 1978 ieee80211_state_name[nstate], nstate)); 1979 1980 s = splnet(); 1981 mutex_enter(&sc->sc_write_mtx); 1982 1983 callout_stop(&sc->sc_scan_to); 1984 callout_stop(&sc->sc_calib_to); 1985 1986 switch (ostate) { 1987 case IEEE80211_S_INIT: 1988 break; 1989 1990 case IEEE80211_S_SCAN: 1991 if (nstate != IEEE80211_S_SCAN) { 1992 /* 1993 * End of scanning 1994 */ 1995 /* flush 4-AC Queue after site_survey */ 1996 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1997 1998 /* Allow Rx from our BSSID only. */ 1999 urtwn_write_4(sc, R92C_RCR, 2000 urtwn_read_4(sc, R92C_RCR) | 2001 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2002 } 2003 break; 2004 2005 case IEEE80211_S_AUTH: 2006 case IEEE80211_S_ASSOC: 2007 break; 2008 2009 case IEEE80211_S_RUN: 2010 /* Turn link LED off. */ 2011 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2012 2013 /* Set media status to 'No Link'. */ 2014 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2015 2016 /* Stop Rx of data frames. */ 2017 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2018 2019 /* Reset TSF. */ 2020 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2021 2022 /* Disable TSF synchronization. */ 2023 urtwn_write_1(sc, R92C_BCN_CTRL, 2024 urtwn_read_1(sc, R92C_BCN_CTRL) | 2025 R92C_BCN_CTRL_DIS_TSF_UDT0); 2026 2027 /* Back to 20MHz mode */ 2028 urtwn_set_chan(sc, ic->ic_curchan, 2029 IEEE80211_HTINFO_2NDCHAN_NONE); 2030 2031 if (ic->ic_opmode == IEEE80211_M_IBSS || 2032 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2033 /* Stop BCN */ 2034 urtwn_write_1(sc, R92C_BCN_CTRL, 2035 urtwn_read_1(sc, R92C_BCN_CTRL) & 2036 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2037 } 2038 2039 /* Reset EDCA parameters. */ 2040 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2041 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2042 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2043 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2044 2045 /* flush all cam entries */ 2046 urtwn_cam_init(sc); 2047 break; 2048 case IEEE80211_S_CAC: 2049 case IEEE80211_S_CSA: 2050 case IEEE80211_S_SLEEP: 2051 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2052 /* NNN what do we do in these states? XXX */ 2053 break; 2054 } 2055 2056 switch (nstate) { 2057 case IEEE80211_S_INIT: 2058 /* Turn link LED off. */ 2059 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2060 break; 2061 2062 case IEEE80211_S_SCAN: 2063 if (ostate != IEEE80211_S_SCAN) { 2064 /* 2065 * Begin of scanning 2066 */ 2067 2068 /* Set gain for scanning. */ 2069 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2070 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2071 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2072 2073 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2074 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2075 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2076 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2077 } 2078 2079 /* Set media status to 'No Link'. */ 2080 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2081 2082 /* Allow Rx from any BSSID. */ 2083 urtwn_write_4(sc, R92C_RCR, 2084 urtwn_read_4(sc, R92C_RCR) & 2085 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2086 2087 /* Stop Rx of data frames. */ 2088 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2089 2090 /* Disable update TSF */ 2091 urtwn_write_1(sc, R92C_BCN_CTRL, 2092 urtwn_read_1(sc, R92C_BCN_CTRL) | 2093 R92C_BCN_CTRL_DIS_TSF_UDT0); 2094 } 2095 2096 /* Make link LED blink during scan. */ 2097 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2098 2099 /* Pause AC Tx queues. */ 2100 urtwn_write_1(sc, R92C_TXPAUSE, 2101 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2102 2103 urtwn_set_chan(sc, ic->ic_curchan, 2104 IEEE80211_HTINFO_2NDCHAN_NONE); 2105 2106 /* Start periodic scan. */ 2107 if (!sc->sc_dying) 2108 callout_schedule(&sc->sc_scan_to, hz / 5); 2109 break; 2110 2111 case IEEE80211_S_AUTH: 2112 /* Set initial gain under link. */ 2113 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2114 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2115 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2116 2117 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2118 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2119 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2120 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2121 } 2122 2123 /* Set media status to 'No Link'. */ 2124 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2125 2126 /* Allow Rx from any BSSID. */ 2127 urtwn_write_4(sc, R92C_RCR, 2128 urtwn_read_4(sc, R92C_RCR) & 2129 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2130 2131 urtwn_set_chan(sc, ic->ic_curchan, 2132 IEEE80211_HTINFO_2NDCHAN_NONE); 2133 break; 2134 2135 case IEEE80211_S_ASSOC: 2136 break; 2137 2138 case IEEE80211_S_RUN: 2139 ni = vap->iv_bss; 2140 2141 /* XXX: Set 20MHz mode */ 2142 urtwn_set_chan(sc, ic->ic_curchan, 2143 IEEE80211_HTINFO_2NDCHAN_NONE); 2144 2145 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2146 /* Back to 20MHz mode */ 2147 urtwn_set_chan(sc, ic->ic_curchan, 2148 IEEE80211_HTINFO_2NDCHAN_NONE); 2149 2150 /* Set media status to 'No Link'. */ 2151 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2152 2153 /* Enable Rx of data frames. */ 2154 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2155 2156 /* Allow Rx from any BSSID. */ 2157 urtwn_write_4(sc, R92C_RCR, 2158 urtwn_read_4(sc, R92C_RCR) & 2159 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2160 2161 /* Accept Rx data/control/management frames */ 2162 urtwn_write_4(sc, R92C_RCR, 2163 urtwn_read_4(sc, R92C_RCR) | 2164 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2165 2166 /* Turn link LED on. */ 2167 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2168 break; 2169 } 2170 2171 /* Set media status to 'Associated'. */ 2172 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2173 2174 /* Set BSSID. */ 2175 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2176 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2177 2178 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2179 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2180 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2181 /* 802.11b/g */ 2182 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2183 } else /* IEEE_MODE_11NG */ 2184 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 11); 2185 2186 /* Enable Rx of data frames. */ 2187 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2188 2189 /* Set beacon interval. */ 2190 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2191 2192 msr = urtwn_read_1(sc, R92C_MSR); 2193 msr &= R92C_MSR_MASK; 2194 switch (ic->ic_opmode) { 2195 case IEEE80211_M_STA: 2196 /* Allow Rx from our BSSID only. */ 2197 urtwn_write_4(sc, R92C_RCR, 2198 urtwn_read_4(sc, R92C_RCR) | 2199 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2200 2201 /* Enable TSF synchronization. */ 2202 urtwn_tsf_sync_enable(sc); 2203 2204 msr |= R92C_MSR_INFRA; 2205 break; 2206 case IEEE80211_M_HOSTAP: 2207 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2208 2209 /* Allow Rx from any BSSID. */ 2210 urtwn_write_4(sc, R92C_RCR, 2211 urtwn_read_4(sc, R92C_RCR) & 2212 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2213 2214 /* Reset TSF timer to zero. */ 2215 reg = urtwn_read_4(sc, R92C_TCR); 2216 reg &= ~0x01; 2217 urtwn_write_4(sc, R92C_TCR, reg); 2218 reg |= 0x01; 2219 urtwn_write_4(sc, R92C_TCR, reg); 2220 2221 msr |= R92C_MSR_AP; 2222 break; 2223 default: 2224 msr |= R92C_MSR_ADHOC; 2225 break; 2226 } 2227 urtwn_write_1(sc, R92C_MSR, msr); 2228 2229 sifs_time = 10; 2230 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2231 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2232 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2233 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2234 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2235 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2236 2237 /* Initialize rate adaptation. */ 2238 if (1 || ISSET(sc->chip, URTWN_CHIP_88E) || 2239 ISSET(sc->chip, URTWN_CHIP_92EU)) 2240 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2241 else 2242 urtwn_ra_init(vap); 2243 2244 /* Turn link LED on. */ 2245 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2246 2247 /* Reset average RSSI. */ 2248 sc->avg_pwdb = -1; 2249 2250 /* Reset temperature calibration state machine. */ 2251 sc->thcal_state = 0; 2252 sc->thcal_lctemp = 0; 2253 2254 /* Start periodic calibration. */ 2255 if (!sc->sc_dying) 2256 callout_schedule(&sc->sc_calib_to, hz); 2257 break; 2258 case IEEE80211_S_CAC: 2259 case IEEE80211_S_CSA: 2260 case IEEE80211_S_SLEEP: 2261 /* NNN what do we do in these states? XXX */ 2262 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2263 break; 2264 } 2265 /* newstate functions expect the ic to be locked. */ 2266 IEEE80211_LOCK(ic); 2267 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2268 IEEE80211_UNLOCK(ic); 2269 2270 mutex_exit(&sc->sc_write_mtx); 2271 splx(s); 2272 } 2273 #endif 2274 2275 static int 2276 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2277 { 2278 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2279 struct ieee80211com *ic = &sc->sc_ic; 2280 struct ieee80211_node *ni; 2281 enum ieee80211_state ostate = vap->iv_state; 2282 uint32_t reg; 2283 uint8_t sifs_time, msr; 2284 int s; 2285 int error; 2286 2287 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2288 device_xname(sc->sc_dev), __func__, 2289 ieee80211_state_name[ostate], ostate, 2290 ieee80211_state_name[nstate], nstate)); 2291 2292 s = splnet(); 2293 mutex_enter(&sc->sc_write_mtx); 2294 2295 callout_stop(&sc->sc_scan_to); 2296 callout_stop(&sc->sc_calib_to); 2297 2298 switch (ostate) { 2299 case IEEE80211_S_INIT: 2300 break; 2301 2302 case IEEE80211_S_SCAN: 2303 if (nstate != IEEE80211_S_SCAN) { 2304 /* 2305 * End of scanning 2306 */ 2307 /* flush 4-AC Queue after site_survey */ 2308 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2309 2310 /* Allow Rx from our BSSID only. */ 2311 urtwn_write_4(sc, R92C_RCR, 2312 urtwn_read_4(sc, R92C_RCR) | 2313 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2314 } 2315 break; 2316 2317 case IEEE80211_S_AUTH: 2318 case IEEE80211_S_ASSOC: 2319 break; 2320 2321 case IEEE80211_S_RUN: 2322 if (nstate == IEEE80211_S_RUN) 2323 break; 2324 /* Turn link LED off. */ 2325 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2326 2327 /* Set media status to 'No Link'. */ 2328 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2329 2330 /* Stop Rx of data frames. */ 2331 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2332 2333 /* Reset TSF. */ 2334 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2335 2336 /* Disable TSF synchronization. */ 2337 urtwn_write_1(sc, R92C_BCN_CTRL, 2338 urtwn_read_1(sc, R92C_BCN_CTRL) | 2339 R92C_BCN_CTRL_DIS_TSF_UDT0); 2340 2341 #if 0 2342 /* Back to 20MHz mode */ 2343 urtwn_set_chan(sc, ic->ic_curchan, 2344 IEEE80211_HTINFO_2NDCHAN_NONE); 2345 #endif 2346 2347 if (ic->ic_opmode == IEEE80211_M_IBSS || 2348 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2349 /* Stop BCN */ 2350 urtwn_write_1(sc, R92C_BCN_CTRL, 2351 urtwn_read_1(sc, R92C_BCN_CTRL) & 2352 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2353 } 2354 2355 /* Reset EDCA parameters. */ 2356 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2357 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2358 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2359 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2360 2361 /* flush all cam entries */ 2362 urtwn_cam_init(sc); 2363 break; 2364 case IEEE80211_S_CAC: 2365 case IEEE80211_S_CSA: 2366 case IEEE80211_S_SLEEP: 2367 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2368 /* NNN what do we do in these states? XXX */ 2369 break; 2370 } 2371 2372 switch (nstate) { 2373 case IEEE80211_S_INIT: 2374 /* Turn link LED off. */ 2375 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2376 break; 2377 2378 case IEEE80211_S_SCAN: 2379 if (ostate == IEEE80211_S_SCAN) 2380 break; 2381 if (ostate != IEEE80211_S_SCAN) { 2382 /* 2383 * Begin of scanning 2384 */ 2385 2386 /* Set gain for scanning. */ 2387 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2388 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2389 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2390 2391 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2392 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2393 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2394 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2395 } 2396 2397 /* Set media status to 'No Link'. */ 2398 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2399 2400 /* Allow Rx from any BSSID. */ 2401 urtwn_write_4(sc, R92C_RCR, 2402 urtwn_read_4(sc, R92C_RCR) & 2403 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2404 2405 /* Stop Rx of data frames. */ 2406 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2407 2408 /* Disable update TSF */ 2409 urtwn_write_1(sc, R92C_BCN_CTRL, 2410 urtwn_read_1(sc, R92C_BCN_CTRL) | 2411 R92C_BCN_CTRL_DIS_TSF_UDT0); 2412 } 2413 2414 /* Make link LED blink during scan. */ 2415 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2416 2417 /* Pause AC Tx queues. */ 2418 urtwn_write_1(sc, R92C_TXPAUSE, 2419 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2420 2421 #if 0 2422 urtwn_set_chan(sc, ic->ic_curchan, 2423 IEEE80211_HTINFO_2NDCHAN_NONE); 2424 #endif 2425 2426 /* Start periodic scan. */ 2427 if (!sc->sc_dying) 2428 callout_schedule(&sc->sc_scan_to, hz / 5); 2429 break; 2430 2431 case IEEE80211_S_AUTH: 2432 if (ostate == IEEE80211_S_AUTH) 2433 break; 2434 /* Set initial gain under link. */ 2435 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2436 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2437 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2438 2439 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2440 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2441 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2442 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2443 } 2444 2445 /* Set media status to 'No Link'. */ 2446 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2447 2448 /* Allow Rx from any BSSID. */ 2449 urtwn_write_4(sc, R92C_RCR, 2450 urtwn_read_4(sc, R92C_RCR) & 2451 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2452 2453 #if 0 2454 urtwn_set_chan(sc, ic->ic_curchan, 2455 IEEE80211_HTINFO_2NDCHAN_NONE); 2456 #endif 2457 break; 2458 2459 case IEEE80211_S_ASSOC: 2460 break; 2461 2462 case IEEE80211_S_RUN: 2463 if (ostate == IEEE80211_S_RUN) 2464 break; 2465 ni = vap->iv_bss; 2466 2467 #if 0 2468 /* XXX: Set 20MHz mode */ 2469 urtwn_set_chan(sc, ic->ic_curchan, 2470 IEEE80211_HTINFO_2NDCHAN_NONE); 2471 #endif 2472 2473 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2474 #if 0 2475 /* Back to 20MHz mode */ 2476 urtwn_set_chan(sc, ic->ic_curchan, 2477 IEEE80211_HTINFO_2NDCHAN_NONE); 2478 #endif 2479 2480 /* Set media status to 'No Link'. */ 2481 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2482 2483 /* Enable Rx of data frames. */ 2484 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2485 2486 /* Allow Rx from any BSSID. */ 2487 urtwn_write_4(sc, R92C_RCR, 2488 urtwn_read_4(sc, R92C_RCR) & 2489 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2490 2491 /* Accept Rx data/control/management frames */ 2492 urtwn_write_4(sc, R92C_RCR, 2493 urtwn_read_4(sc, R92C_RCR) | 2494 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2495 2496 /* Turn link LED on. */ 2497 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2498 break; 2499 } 2500 2501 /* Set media status to 'Associated'. */ 2502 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2503 2504 /* Set BSSID. */ 2505 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2506 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2507 2508 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2509 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2510 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2511 /* 802.11b/g */ 2512 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2513 } else /* IEEE_MODE_11NG */ 2514 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2515 2516 /* Enable Rx of data frames. */ 2517 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2518 2519 /* Set beacon interval. */ 2520 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2521 2522 msr = urtwn_read_1(sc, R92C_MSR); 2523 msr &= R92C_MSR_MASK; 2524 switch (ic->ic_opmode) { 2525 case IEEE80211_M_STA: 2526 /* Allow Rx from our BSSID only. */ 2527 urtwn_write_4(sc, R92C_RCR, 2528 urtwn_read_4(sc, R92C_RCR) | 2529 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2530 2531 /* Enable TSF synchronization. */ 2532 urtwn_tsf_sync_enable(sc); 2533 2534 msr |= R92C_MSR_INFRA; 2535 break; 2536 case IEEE80211_M_HOSTAP: 2537 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2538 2539 /* Allow Rx from any BSSID. */ 2540 urtwn_write_4(sc, R92C_RCR, 2541 urtwn_read_4(sc, R92C_RCR) & 2542 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2543 2544 /* Reset TSF timer to zero. */ 2545 reg = urtwn_read_4(sc, R92C_TCR); 2546 reg &= ~0x01; 2547 urtwn_write_4(sc, R92C_TCR, reg); 2548 reg |= 0x01; 2549 urtwn_write_4(sc, R92C_TCR, reg); 2550 2551 msr |= R92C_MSR_AP; 2552 break; 2553 default: 2554 msr |= R92C_MSR_ADHOC; 2555 break; 2556 } 2557 urtwn_write_1(sc, R92C_MSR, msr); 2558 2559 sifs_time = 10; 2560 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2561 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2562 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2563 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2564 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2565 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2566 2567 /* Initialize rate adaptation. */ 2568 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2569 ISSET(sc->chip, URTWN_CHIP_92EU)) 2570 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2571 else 2572 urtwn_ra_init(vap); 2573 2574 /* Turn link LED on. */ 2575 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2576 2577 /* Reset average RSSI. */ 2578 sc->avg_pwdb = -1; 2579 2580 /* Reset temperature calibration state machine. */ 2581 sc->thcal_state = 0; 2582 sc->thcal_lctemp = 0; 2583 2584 /* Start periodic calibration. */ 2585 if (!sc->sc_dying) 2586 callout_schedule(&sc->sc_calib_to, hz); 2587 break; 2588 case IEEE80211_S_CAC: 2589 case IEEE80211_S_CSA: 2590 case IEEE80211_S_SLEEP: 2591 /* NNN what do we do in these states? XXX */ 2592 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2593 break; 2594 } 2595 mutex_exit(&sc->sc_write_mtx); 2596 2597 /* newstate functions expect the ic to be locked. */ 2598 error = (*sc->sc_newstate)(vap, nstate, arg); 2599 2600 splx(s); 2601 return error; 2602 } 2603 2604 static int 2605 urtwn_wme_update(struct ieee80211com *ic) 2606 { 2607 struct urtwn_softc *sc = ic->ic_softc; 2608 2609 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2610 2611 /* don't override default WME values if WME is not actually enabled */ 2612 if (!(ic->ic_flags & IEEE80211_F_WME)) 2613 return 0; 2614 2615 /* Do it in a process context. */ 2616 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2617 return 0; 2618 } 2619 2620 static void 2621 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2622 { 2623 static const uint16_t ac2reg[WME_NUM_AC] = { 2624 R92C_EDCA_BE_PARAM, 2625 R92C_EDCA_BK_PARAM, 2626 R92C_EDCA_VI_PARAM, 2627 R92C_EDCA_VO_PARAM 2628 }; 2629 struct ieee80211com *ic = &sc->sc_ic; 2630 const struct wmeParams *wmep; 2631 int ac, aifs, slottime; 2632 int s; 2633 2634 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2635 __func__)); 2636 2637 s = splnet(); 2638 mutex_enter(&sc->sc_write_mtx); 2639 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2640 for (ac = 0; ac < WME_NUM_AC; ac++) { 2641 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2642 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2643 aifs = wmep->wmep_aifsn * slottime + 10; 2644 urtwn_write_4(sc, ac2reg[ac], 2645 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2646 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2647 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2648 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2649 } 2650 mutex_exit(&sc->sc_write_mtx); 2651 splx(s); 2652 } 2653 2654 static void 2655 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2656 { 2657 int pwdb; 2658 2659 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2660 device_xname(sc->sc_dev), __func__, rate, rssi)); 2661 2662 /* Convert antenna signal to percentage. */ 2663 if (rssi <= -100 || rssi >= 20) 2664 pwdb = 0; 2665 else if (rssi >= 0) 2666 pwdb = 100; 2667 else 2668 pwdb = 100 + rssi; 2669 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2670 if (rate <= 3) { 2671 /* CCK gain is smaller than OFDM/MCS gain. */ 2672 pwdb += 6; 2673 if (pwdb > 100) 2674 pwdb = 100; 2675 if (pwdb <= 14) 2676 pwdb -= 4; 2677 else if (pwdb <= 26) 2678 pwdb -= 8; 2679 else if (pwdb <= 34) 2680 pwdb -= 6; 2681 else if (pwdb <= 42) 2682 pwdb -= 2; 2683 } 2684 } 2685 if (sc->avg_pwdb == -1) /* Init. */ 2686 sc->avg_pwdb = pwdb; 2687 else if (sc->avg_pwdb < pwdb) 2688 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2689 else 2690 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2691 2692 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2693 device_xname(sc->sc_dev), __func__, 2694 rate, rssi, pwdb, sc->avg_pwdb)); 2695 } 2696 2697 static int8_t 2698 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2699 { 2700 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2701 struct r92c_rx_phystat *phy; 2702 struct r92c_rx_cck *cck; 2703 uint8_t rpt; 2704 int8_t rssi; 2705 2706 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2707 __func__, rate)); 2708 2709 if (rate <= 3) { 2710 cck = (struct r92c_rx_cck *)physt; 2711 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2712 rpt = (cck->agc_rpt >> 5) & 0x3; 2713 rssi = (cck->agc_rpt & 0x1f) << 1; 2714 } else { 2715 rpt = (cck->agc_rpt >> 6) & 0x3; 2716 rssi = cck->agc_rpt & 0x3e; 2717 } 2718 rssi = cckoff[rpt] - rssi; 2719 } else { /* OFDM/HT. */ 2720 phy = (struct r92c_rx_phystat *)physt; 2721 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2722 } 2723 return rssi; 2724 } 2725 2726 static int8_t 2727 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2728 { 2729 struct r92c_rx_phystat *phy; 2730 struct r88e_rx_cck *cck; 2731 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2732 int8_t rssi; 2733 2734 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2735 __func__, rate)); 2736 2737 rssi = 0; 2738 if (rate <= 3) { 2739 cck = (struct r88e_rx_cck *)physt; 2740 cck_agc_rpt = cck->agc_rpt; 2741 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2742 vga_idx = cck_agc_rpt & 0x1f; 2743 switch (lna_idx) { 2744 case 7: 2745 if (vga_idx <= 27) 2746 rssi = -100 + 2* (27 - vga_idx); 2747 else 2748 rssi = -100; 2749 break; 2750 case 6: 2751 rssi = -48 + 2 * (2 - vga_idx); 2752 break; 2753 case 5: 2754 rssi = -42 + 2 * (7 - vga_idx); 2755 break; 2756 case 4: 2757 rssi = -36 + 2 * (7 - vga_idx); 2758 break; 2759 case 3: 2760 rssi = -24 + 2 * (7 - vga_idx); 2761 break; 2762 case 2: 2763 rssi = -12 + 2 * (5 - vga_idx); 2764 break; 2765 case 1: 2766 rssi = 8 - (2 * vga_idx); 2767 break; 2768 case 0: 2769 rssi = 14 - (2 * vga_idx); 2770 break; 2771 } 2772 rssi += 6; 2773 } else { /* OFDM/HT. */ 2774 phy = (struct r92c_rx_phystat *)physt; 2775 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2776 } 2777 return rssi; 2778 } 2779 2780 static void 2781 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2782 { 2783 struct ieee80211com *ic = &sc->sc_ic; 2784 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2785 struct ifnet *ifp = vap->iv_ifp; 2786 struct ieee80211_frame *wh; 2787 struct ieee80211_node *ni; 2788 struct r92c_rx_desc_usb *stat; 2789 uint32_t rxdw0, rxdw3; 2790 struct mbuf *m; 2791 uint8_t rate; 2792 int8_t rssi = 0; 2793 int s, infosz; 2794 2795 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2796 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2797 2798 stat = (struct r92c_rx_desc_usb *)buf; 2799 rxdw0 = le32toh(stat->rxdw0); 2800 rxdw3 = le32toh(stat->rxdw3); 2801 2802 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2803 /* 2804 * This should not happen since we setup our Rx filter 2805 * to not receive these frames. 2806 */ 2807 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2808 device_xname(sc->sc_dev), __func__)); 2809 if_statinc(ifp, if_ierrors); 2810 return; 2811 } 2812 2813 /* 2814 * XXX: This will drop most control packets. Do we really 2815 * want this in IEEE80211_M_MONITOR mode? 2816 */ 2817 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2818 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2819 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2820 device_xname(sc->sc_dev), __func__, pktlen)); 2821 vap->iv_stats.is_rx_tooshort++; 2822 if_statinc(ifp,if_ierrors); 2823 return; 2824 } 2825 if (__predict_false(pktlen > MCLBYTES)) { 2826 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2827 device_xname(sc->sc_dev), __func__, pktlen)); 2828 if_statinc(ifp, if_ierrors); 2829 return; 2830 } 2831 2832 rate = MS(rxdw3, R92C_RXDW3_RATE); 2833 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2834 2835 /* Get RSSI from PHY status descriptor if present. */ 2836 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2837 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2838 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2839 else 2840 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2841 /* Update our average RSSI. */ 2842 urtwn_update_avgrssi(sc, rate, rssi); 2843 } 2844 2845 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2846 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2847 2848 MGETHDR(m, M_DONTWAIT, MT_DATA); 2849 if (__predict_false(m == NULL)) { 2850 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2851 vap->iv_stats.is_rx_nobuf++; 2852 if_statinc(ifp, if_ierrors); 2853 return; 2854 } 2855 if (pktlen > (int)MHLEN) { 2856 MCLGET(m, M_DONTWAIT); 2857 if (__predict_false(!(m->m_flags & M_EXT))) { 2858 aprint_error_dev(sc->sc_dev, 2859 "couldn't allocate rx mbuf cluster\n"); 2860 m_freem(m); 2861 vap->iv_stats.is_rx_nobuf++; 2862 if_statinc(ifp, if_ierrors); 2863 return; 2864 } 2865 } 2866 2867 /* Finalize mbuf. */ 2868 m_set_rcvif(m, ifp); 2869 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2870 2871 memcpy(mtod(m, uint8_t *), wh, pktlen); 2872 m->m_pkthdr.len = m->m_len = pktlen; 2873 2874 s = splnet(); 2875 if (__predict_false(sc->sc_drvbpf != NULL)) { 2876 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2877 2878 tap->wr_flags = 0; 2879 if (!(rxdw3 & R92C_RXDW3_HT)) { 2880 switch (rate) { 2881 /* CCK. */ 2882 case 0: tap->wr_rate = 2; break; 2883 case 1: tap->wr_rate = 4; break; 2884 case 2: tap->wr_rate = 11; break; 2885 case 3: tap->wr_rate = 22; break; 2886 /* OFDM. */ 2887 case 4: tap->wr_rate = 12; break; 2888 case 5: tap->wr_rate = 18; break; 2889 case 6: tap->wr_rate = 24; break; 2890 case 7: tap->wr_rate = 36; break; 2891 case 8: tap->wr_rate = 48; break; 2892 case 9: tap->wr_rate = 72; break; 2893 case 10: tap->wr_rate = 96; break; 2894 case 11: tap->wr_rate = 108; break; 2895 } 2896 } else if (rate >= 12) { /* MCS0~15. */ 2897 /* Bit 7 set means HT MCS instead of rate. */ 2898 tap->wr_rate = 0x80 | (rate - 12); 2899 } 2900 tap->wr_dbm_antsignal = rssi; 2901 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2902 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2903 2904 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2905 } 2906 2907 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2908 2909 if (ni != NULL) { 2910 if (ni->ni_vap != NULL) { 2911 2912 } else { 2913 splx(s); 2914 return; 2915 } 2916 /* push the frame up to the 802.11 stack */ 2917 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2918 ieee80211_input(ni, m, rssi+90, 0); 2919 2920 /* Node is no longer needed. */ 2921 ieee80211_free_node(ni); 2922 2923 } else { 2924 2925 /* No node found ... process differently. */ 2926 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2927 } 2928 2929 splx(s); 2930 } 2931 2932 static void 2933 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2934 { 2935 struct urtwn_rx_data *data = priv; 2936 struct urtwn_softc *sc = data->sc; 2937 struct r92c_rx_desc_usb *stat; 2938 size_t pidx = data->pidx; 2939 uint32_t rxdw0; 2940 uint8_t *buf; 2941 int len, totlen, pktlen, infosz, npkts; 2942 2943 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2944 device_xname(sc->sc_dev), __func__, status)); 2945 2946 mutex_enter(&sc->sc_rx_mtx); 2947 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2948 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2949 /* Put this Rx buffer back to our free list. */ 2950 mutex_exit(&sc->sc_rx_mtx); 2951 2952 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2953 if (status == USBD_STALLED) 2954 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2955 else if (status != USBD_CANCELLED) 2956 goto resubmit; 2957 return; 2958 } 2959 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2960 2961 if (__predict_false(len < (int)sizeof(*stat))) { 2962 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2963 device_xname(sc->sc_dev), __func__, len)); 2964 goto resubmit; 2965 } 2966 buf = data->buf; 2967 2968 /* Get the number of encapsulated frames. */ 2969 stat = (struct r92c_rx_desc_usb *)buf; 2970 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2971 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2972 else 2973 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2974 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2975 device_xname(sc->sc_dev), __func__, npkts)); 2976 2977 /* Process all of them. */ 2978 while (npkts-- > 0) { 2979 if (__predict_false(len < (int)sizeof(*stat))) { 2980 DPRINTFN(DBG_RX, 2981 ("%s: %s: len(%d) is short than header\n", 2982 device_xname(sc->sc_dev), __func__, len)); 2983 break; 2984 } 2985 stat = (struct r92c_rx_desc_usb *)buf; 2986 rxdw0 = le32toh(stat->rxdw0); 2987 2988 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2989 if (__predict_false(pktlen == 0)) { 2990 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2991 device_xname(sc->sc_dev), __func__)); 2992 break; 2993 } 2994 2995 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2996 2997 /* Make sure everything fits in xfer. */ 2998 totlen = sizeof(*stat) + infosz + pktlen; 2999 if (__predict_false(totlen > len)) { 3000 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 3001 device_xname(sc->sc_dev), __func__, totlen, 3002 (int)sizeof(*stat), infosz, pktlen, len)); 3003 break; 3004 } 3005 3006 /* Process 802.11 frame. */ 3007 urtwn_rx_frame(sc, buf, pktlen); 3008 3009 /* Next chunk is 128-byte aligned. */ 3010 totlen = roundup2(totlen, 128); 3011 buf += totlen; 3012 len -= totlen; 3013 } 3014 3015 resubmit: 3016 /* Setup a new transfer. */ 3017 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 3018 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 3019 (void)usbd_transfer(xfer); 3020 } 3021 3022 static void 3023 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3024 { 3025 struct urtwn_tx_data *data = priv; 3026 struct urtwn_softc *sc = data->sc; 3027 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 3028 size_t pidx = data->pidx; 3029 int s; 3030 3031 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 3032 device_xname(sc->sc_dev), __func__, status)); 3033 3034 mutex_enter(&sc->sc_tx_mtx); 3035 /* Put this Tx buffer back to our free list. */ 3036 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 3037 mutex_exit(&sc->sc_tx_mtx); 3038 3039 s = splnet(); 3040 sc->tx_timer = 0; 3041 ifp->if_flags &= ~IFF_OACTIVE; 3042 3043 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 3044 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 3045 if (status == USBD_STALLED) { 3046 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 3047 usbd_clear_endpoint_stall_async(pipe); 3048 } 3049 printf("ERROR1\n"); 3050 if_statinc(ifp, if_oerrors); 3051 } 3052 splx(s); 3053 return; 3054 } 3055 3056 if_statinc(ifp, if_opackets); 3057 urtwn_start(ifp); 3058 splx(s); 3059 3060 } 3061 3062 static int 3063 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3064 struct urtwn_tx_data *data) 3065 { 3066 struct ieee80211com *ic = &sc->sc_ic; 3067 struct ieee80211_frame *wh; 3068 struct ieee80211_key *k = NULL; 3069 struct r92c_tx_desc_usb *txd; 3070 size_t i, padsize, xferlen, txd_len; 3071 uint16_t seq, sum; 3072 uint8_t raid, type, tid; 3073 int s, hasqos, error; 3074 3075 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3076 3077 wh = mtod(m, struct ieee80211_frame *); 3078 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3079 txd_len = sizeof(*txd); 3080 3081 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3082 txd_len = 32; 3083 3084 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3085 k = ieee80211_crypto_encap(ni, m); 3086 if (k == NULL) 3087 return ENOBUFS; 3088 3089 /* packet header may have moved, reset our local pointer */ 3090 wh = mtod(m, struct ieee80211_frame *); 3091 } 3092 3093 if (__predict_false(sc->sc_drvbpf != NULL)) { 3094 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3095 3096 tap->wt_flags = 0; 3097 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3098 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3099 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3100 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3101 3102 /* XXX: set tap->wt_rate? */ 3103 3104 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3105 } 3106 3107 /* non-qos data frames */ 3108 tid = R92C_TXDW1_QSEL_BE; 3109 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3110 /* data frames in 11n mode */ 3111 struct ieee80211_qosframe *qwh = (void *)wh; 3112 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3113 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3114 tid = R92C_TXDW1_QSEL_MGNT; 3115 } 3116 3117 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3118 padsize = 8; 3119 else 3120 padsize = 0; 3121 3122 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3123 padsize = 0; 3124 3125 /* Fill Tx descriptor. */ 3126 txd = (struct r92c_tx_desc_usb *)data->buf; 3127 memset(txd, 0, txd_len + padsize); 3128 3129 txd->txdw0 |= htole32( 3130 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3131 SM(R92C_TXDW0_OFFSET, txd_len)); 3132 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3133 txd->txdw0 |= htole32( 3134 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3135 } 3136 3137 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3138 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3139 3140 /* fix pad field */ 3141 if (padsize > 0) { 3142 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3143 device_xname(sc->sc_dev), __func__, padsize)); 3144 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3145 } 3146 if (ic->ic_curmode == IEEE80211_MODE_11B) { 3147 raid = R92C_RAID_11B; 3148 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3149 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 3150 raid = R92C_RAID_11BG; 3151 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3152 } else { /* IEEE80211_MODE_11NG */ 3153 raid = R92C_RAID_11GN; 3154 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 19)); 3155 txd->txdw5 |= htole32(R92C_TXDW5_SGI); 3156 } 3157 3158 3159 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3160 type == IEEE80211_FC0_TYPE_DATA) { 3161 DPRINTFN(DBG_TX, 3162 ("%s: %s: data packet: tid=%d, raid=%d\n", 3163 device_xname(sc->sc_dev), __func__, tid, raid)); 3164 3165 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3166 txd->txdw1 |= htole32( 3167 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3168 SM(R92C_TXDW1_QSEL, tid) | 3169 SM(R92C_TXDW1_RAID, raid) | 3170 R92C_TXDW1_AGGBK); 3171 } else 3172 txd->txdw1 |= htole32( 3173 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3174 SM(R92C_TXDW1_QSEL, tid) | 3175 SM(R92C_TXDW1_RAID, raid) | 3176 R92C_TXDW1_AGGBK); 3177 3178 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3179 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3180 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3181 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3182 3183 if (hasqos) { 3184 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3185 } 3186 3187 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3188 /* for 11g */ 3189 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3190 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3191 R92C_TXDW4_HWRTSEN); 3192 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3193 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3194 R92C_TXDW4_HWRTSEN); 3195 } 3196 } 3197 /* Send RTS at OFDM24. */ 3198 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3199 txd->txdw5 |= htole32(0x0001ff00); 3200 /* Send data at OFDM54. */ 3201 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3202 txd->txdw5 |= htole32(0x13 & 0x3f); 3203 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3204 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3205 device_xname(sc->sc_dev), __func__)); 3206 txd->txdw1 |= htole32( 3207 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3208 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3209 SM(R92C_TXDW1_RAID, raid)); 3210 3211 #if 0 3212 /* Force CCK1. */ 3213 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3214 #endif 3215 } else { 3216 /* broadcast or multicast packets */ 3217 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3218 device_xname(sc->sc_dev), __func__)); 3219 txd->txdw1 |= htole32( 3220 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3221 SM(R92C_TXDW1_RAID, raid)); 3222 3223 #if 0 3224 /* Force CCK1. */ 3225 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3226 #endif 3227 } 3228 /* Set sequence number */ 3229 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3230 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3231 txd->txdseq |= htole16(seq); 3232 3233 if (!hasqos) { 3234 /* Use HW sequence numbering for non-QoS frames. */ 3235 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3236 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3237 } 3238 } else { 3239 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3240 R92E_HWSEQ_SHIFT); 3241 if (!hasqos) { 3242 /* Use HW sequence numbering for non-QoS frames. */ 3243 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3244 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3245 } 3246 } 3247 3248 /* Compute Tx descriptor checksum. */ 3249 sum = 0; 3250 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3251 sum ^= ((uint16_t *)txd)[i]; 3252 txd->txdsum = sum; /* NB: already little endian. */ 3253 3254 xferlen = txd_len + m->m_pkthdr.len + padsize; 3255 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3256 3257 if (data->xfer == NULL) { 3258 /* NNN Don't crash ... but what is going on! */ 3259 printf ("urtwn_tx: data->xfer is NULL\n"); 3260 m_print(m,"", printf); 3261 return -1; 3262 } 3263 3264 s = splnet(); 3265 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3266 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3267 urtwn_txeof); 3268 error = usbd_transfer(data->xfer); 3269 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3270 error != USBD_IN_PROGRESS)) { 3271 splx(s); 3272 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3273 device_xname(sc->sc_dev), __func__, error)); 3274 return error; 3275 } 3276 splx(s); 3277 return 0; 3278 } 3279 3280 struct urtwn_tx_data * 3281 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3282 { 3283 struct urtwn_tx_data *data = NULL; 3284 3285 mutex_enter(&sc->sc_tx_mtx); 3286 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3287 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3288 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3289 } 3290 mutex_exit(&sc->sc_tx_mtx); 3291 3292 return data; 3293 } 3294 3295 static void 3296 urtwn_start(struct ifnet *ifp) 3297 { 3298 struct ieee80211vap *vap = ifp->if_softc; 3299 struct ieee80211com *ic = vap->iv_ic; 3300 struct urtwn_softc *sc = ic->ic_softc; 3301 struct urtwn_tx_data *data; 3302 struct ether_header *eh; 3303 struct ieee80211_node *ni; 3304 struct mbuf *m; 3305 3306 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3307 3308 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3309 return; 3310 3311 data = NULL; 3312 for (;;) { 3313 /* Send pending management frames first. */ 3314 IF_POLL(&ic->ic_mgtq, m); 3315 if (m != NULL) { 3316 /* Use AC_VO for management frames. */ 3317 3318 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3319 3320 if (data == NULL) { 3321 ifp->if_flags |= IFF_OACTIVE; 3322 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3323 device_xname(sc->sc_dev))); 3324 return; 3325 } 3326 IF_DEQUEUE(&ic->ic_mgtq, m); 3327 ni = M_GETCTX(m, struct ieee80211_node *); 3328 M_CLEARCTX(m); 3329 goto sendit; 3330 } 3331 3332 if (vap->iv_state != IEEE80211_S_RUN) 3333 break; 3334 3335 /* Encapsulate and send data frames. */ 3336 IFQ_POLL(&sc->sc_sendq, m); 3337 if (m == NULL) 3338 break; 3339 3340 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3341 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3342 uint8_t qid = WME_AC_BE; 3343 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3344 /* data frames in 11n mode */ 3345 struct ieee80211_qosframe *qwh = (void *)wh; 3346 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3347 qid = TID_TO_WME_AC(tid); 3348 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3349 qid = WME_AC_VO; 3350 } 3351 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3352 3353 if (data == NULL) { 3354 ifp->if_flags |= IFF_OACTIVE; 3355 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3356 device_xname(sc->sc_dev))); 3357 return; 3358 } 3359 IFQ_DEQUEUE(&sc->sc_sendq, m); 3360 3361 if (m->m_len < (int)sizeof(*eh) && 3362 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3363 printf("ERROR6\n"); 3364 if_statinc(ifp, if_oerrors); 3365 continue; 3366 } 3367 eh = mtod(m, struct ether_header *); 3368 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3369 if (ni == NULL) { 3370 m_freem(m); 3371 printf("ERROR5\n"); 3372 if_statinc(ifp, if_oerrors); 3373 continue; 3374 } 3375 3376 //bpf_mtap(ifp, m, BPF_D_OUT); 3377 3378 sendit: 3379 if (urtwn_tx(sc, m, ni, data) != 0) { 3380 m_freem(m); 3381 ieee80211_free_node(ni); 3382 printf("ERROR3\n"); 3383 if_statinc(ifp, if_oerrors); 3384 continue; 3385 } 3386 m_freem(m); 3387 ieee80211_free_node(ni); 3388 sc->tx_timer = 5; 3389 ifp->if_timer = 1; 3390 } 3391 } 3392 3393 static __unused void 3394 urtwn_watchdog(struct ifnet *ifp) 3395 { 3396 struct ieee80211vap *vap = ifp->if_softc; 3397 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3398 3399 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3400 3401 ifp->if_timer = 0; 3402 3403 if (sc->tx_timer > 0) { 3404 if (--sc->tx_timer == 0) { 3405 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3406 /* urtwn_init(ifp); XXX needs a process context! */ 3407 printf("ERROR2\n"); 3408 if_statinc(ifp, if_oerrors); 3409 return; 3410 } 3411 ifp->if_timer = 1; 3412 } 3413 // ieee80211_watchdog(&sc->sc_ic); 3414 } 3415 3416 /* 3417 * Create a VAP node for use with the urtwn driver. 3418 */ 3419 3420 static struct ieee80211vap * 3421 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3422 int unit, enum ieee80211_opmode opmode, int flags, 3423 const uint8_t bssid[IEEE80211_ADDR_LEN], 3424 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3425 { 3426 struct urtwn_softc *sc = ic->ic_softc; 3427 struct ifnet *ifp; 3428 struct ieee80211vap *vap; 3429 3430 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3431 3432 /* Allow only one VAP for the urtwn driver. */ 3433 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3434 return NULL; 3435 3436 /* Allocate the vap and setup. */ 3437 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3438 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3439 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3440 kmem_free(vap, sizeof(struct ieee80211vap)); 3441 return NULL; 3442 } 3443 3444 /* Local setup */ 3445 vap->iv_reset = urtwn_reset; 3446 3447 ifp = vap->iv_ifp; 3448 if_initialize(ifp); 3449 ifp->if_init = urtwn_init; 3450 ifp->if_ioctl = urtwn_ioctl; 3451 ifp->if_start = urtwn_start; 3452 // ifp->if_watchdog = urtwn_watchdog; NNN 3453 ifp->if_extflags |= IFEF_MPSAFE; 3454 // IFQ_SET_READY(&ifp->if_snd); 3455 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3456 3457 //ifp->if_percpuq = if_percpuq_create(ifp); 3458 3459 /* Override state transition machine. */ 3460 /* NNN --- many possible newstate machines ... issue! */ 3461 sc->sc_newstate = vap->iv_newstate; 3462 vap->iv_newstate = urtwn_newstate; 3463 3464 /* Finish setup */ 3465 ieee80211_vap_attach(vap, urtwn_media_change, 3466 ieee80211_media_status, macaddr); 3467 ic->ic_opmode = opmode; 3468 3469 /* Attach the packet filter */ 3470 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3471 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3472 &sc->sc_drvbpf); 3473 3474 return vap; 3475 } 3476 3477 static void 3478 urtwn_vap_delete(struct ieee80211vap *vap) 3479 { 3480 struct ifnet *ifp = vap->iv_ifp; 3481 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3482 3483 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3484 3485 urtwn_stop(ifp, 0); 3486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3487 bpf_detach(ifp); 3488 if_detach(ifp); 3489 kmem_free(vap, sizeof(struct ieee80211vap)); 3490 } 3491 3492 static void 3493 urtwn_parent(struct ieee80211com *ic) 3494 { 3495 struct urtwn_softc *sc __unused = ic->ic_softc; 3496 3497 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3498 3499 /* Not sure what to do here yet. */ 3500 } 3501 3502 static void 3503 urtwn_scan_start(struct ieee80211com *ic) 3504 { 3505 #ifdef URTWN_DEBUG 3506 struct urtwn_softc *sc = ic->ic_softc; 3507 #endif 3508 //uint32_t reg; 3509 //int s; 3510 3511 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3512 3513 /* 3514 * Not sure what to do here yet. Try #1: do what was in the 3515 * state machine. NNN 3516 */ 3517 #if NOTWITHSTATEMACHINEOVERRIDE 3518 /* 3519 * Begin of scanning 3520 */ 3521 3522 s = splnet(); 3523 mutex_enter(&sc->sc_write_mtx); 3524 3525 /* Set gain for scanning. */ 3526 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3527 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3528 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3529 3530 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3531 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3532 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3533 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3534 } 3535 3536 /* Set media status to 'No Link'. */ 3537 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3538 3539 /* Allow Rx from any BSSID. */ 3540 urtwn_write_4(sc, R92C_RCR, 3541 urtwn_read_4(sc, R92C_RCR) & 3542 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3543 3544 /* Stop Rx of data frames. */ 3545 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3546 3547 /* Disable update TSF */ 3548 urtwn_write_1(sc, R92C_BCN_CTRL, 3549 urtwn_read_1(sc, R92C_BCN_CTRL) | 3550 R92C_BCN_CTRL_DIS_TSF_UDT0); 3551 3552 /* Make link LED blink during scan. */ 3553 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3554 3555 /* Pause AC Tx queues. */ 3556 urtwn_write_1(sc, R92C_TXPAUSE, 3557 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3558 3559 urtwn_set_chan(sc, ic->ic_curchan, 3560 IEEE80211_HTINFO_2NDCHAN_NONE); 3561 3562 mutex_exit(&sc->sc_write_mtx); 3563 splx(s); 3564 #endif 3565 } 3566 3567 static void 3568 urtwn_scan_end(struct ieee80211com *ic) 3569 { 3570 #ifdef URTWN_DEBUG 3571 struct urtwn_softc *sc = ic->ic_softc; 3572 #endif 3573 3574 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3575 3576 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3577 /* 3578 * End of scanning 3579 */ 3580 3581 mutex_enter(&sc->sc_write_mtx); 3582 3583 /* flush 4-AC Queue after site_survey */ 3584 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3585 3586 /* Allow Rx from our BSSID only. */ 3587 urtwn_write_4(sc, R92C_RCR, 3588 urtwn_read_4(sc, R92C_RCR) | 3589 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3590 3591 /* Turn link LED off. */ 3592 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3593 3594 mutex_exit(&sc->sc_write_mtx); 3595 #endif 3596 } 3597 3598 static void 3599 urtwn_set_channel(struct ieee80211com *ic) 3600 { 3601 struct urtwn_softc *sc = ic->ic_softc; 3602 3603 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3604 3605 mutex_enter(&sc->sc_write_mtx); 3606 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3607 mutex_exit(&sc->sc_write_mtx); 3608 } 3609 3610 static int 3611 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3612 { 3613 struct urtwn_softc *sc = ic->ic_softc; 3614 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3615 int s; 3616 size_t pktlen = m->m_pkthdr.len; 3617 bool mcast = (m->m_flags & M_MCAST) != 0; 3618 3619 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3620 3621 s = splnet(); 3622 3623 IF_ENQUEUE(&sc->sc_sendq, m); 3624 3625 if_statadd(vap->iv_ifp, if_obytes, pktlen); 3626 if (mcast) 3627 if_statinc(vap->iv_ifp, if_omcasts); 3628 3629 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3630 if_start_lock(vap->iv_ifp); 3631 splx(s); 3632 3633 urtwn_start(vap->iv_ifp); 3634 3635 return 0; 3636 } 3637 3638 #if 0 3639 static int 3640 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3641 #ifdef URTWN_DEBUG 3642 // struct ieee80211vap *vap = ni->ni_vap; 3643 struct ieee80211com *ic = ni->ni_ic; 3644 struct urtwn_softc *sc = ic->ic_softc; 3645 #endif 3646 3647 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3648 3649 /* Don't know what to do right now. */ 3650 return ENOTTY; 3651 } 3652 #endif 3653 3654 3655 static int 3656 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3657 const struct ieee80211_bpf_params *bpfp) 3658 { 3659 struct ieee80211vap *vap = ni->ni_vap; 3660 struct ieee80211com *ic = ni->ni_ic; 3661 struct urtwn_softc *sc = ic->ic_softc; 3662 struct urtwn_tx_data *data; 3663 int error; 3664 3665 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3666 3667 KASSERT(vap != NULL); /* NNN need these? */ 3668 KASSERT(ic != NULL); 3669 KASSERT(sc != NULL); 3670 KASSERT(m != NULL); 3671 3672 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3673 3674 if (data == NULL) { 3675 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3676 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3677 device_xname(sc->sc_dev))); 3678 return ENOBUFS; 3679 } 3680 3681 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3682 3683 error = urtwn_tx(sc, m, ni, data); 3684 if (error != 0) { 3685 printf("ERROR3\n"); 3686 if_statinc(vap->iv_ifp, if_oerrors); 3687 } else { 3688 sc->tx_timer = 5; 3689 vap->iv_ifp->if_timer = 1; 3690 } 3691 m_freem(m); 3692 ieee80211_free_node(ni); 3693 return error; 3694 } 3695 3696 static void 3697 urtwn_getradiocaps(struct ieee80211com *ic, 3698 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3699 { 3700 uint8_t bands[IEEE80211_MODE_BYTES]; 3701 3702 /* 3703 * NNN Should be able to do something based on chip if 3704 * a chip has more bands .... eg. N ... but for the future. 3705 */ 3706 3707 memset(bands, 0, sizeof(bands)); 3708 setbit(bands, IEEE80211_MODE_11B); 3709 setbit(bands, IEEE80211_MODE_11G); 3710 setbit(bands, IEEE80211_MODE_11NG); 3711 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3712 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, IEEE80211_CHAN_HT20); 3713 } 3714 3715 3716 static int 3717 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3718 { 3719 3720 struct ieee80211vap *vap = ifp->if_softc; 3721 struct ieee80211com *ic = vap->iv_ic; 3722 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3723 int s, error = 0; 3724 3725 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3726 device_xname(sc->sc_dev), __func__, cmd, data)); 3727 3728 s = splnet(); 3729 3730 switch (cmd) { 3731 case SIOCSIFFLAGS: 3732 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3733 break; 3734 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3735 case IFF_UP | IFF_RUNNING: 3736 break; 3737 case IFF_UP: 3738 urtwn_init(ifp); 3739 break; 3740 case IFF_RUNNING: 3741 urtwn_stop(ifp, 1); 3742 break; 3743 case 0: 3744 break; 3745 } 3746 break; 3747 3748 case SIOCADDMULTI: 3749 case SIOCDELMULTI: 3750 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3751 /* setup multicast filter, etc */ 3752 error = 0; 3753 } 3754 break; 3755 3756 case SIOCS80211CHANNEL: 3757 /* 3758 * This allows for fast channel switching in monitor mode 3759 * (used by kismet). In IBSS mode, we must explicitly reset 3760 * the interface to generate a new beacon frame. 3761 */ 3762 error = ieee80211_ioctl(ifp, cmd, data); 3763 if (error == ENETRESET && 3764 ic->ic_opmode == IEEE80211_M_MONITOR) { 3765 urtwn_set_chan(sc, ic->ic_curchan, 3766 IEEE80211_HTINFO_2NDCHAN_NONE); 3767 error = 0; 3768 } 3769 break; 3770 3771 default: 3772 error = ieee80211_ioctl(ifp, cmd, data); 3773 break; 3774 } 3775 if (error == ENETRESET) { 3776 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3777 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3778 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3779 urtwn_init(ifp); 3780 } 3781 error = 0; 3782 } 3783 3784 splx(s); 3785 3786 return error; 3787 } 3788 3789 static __inline int 3790 urtwn_power_on(struct urtwn_softc *sc) 3791 { 3792 3793 return sc->sc_power_on(sc); 3794 } 3795 3796 static int 3797 urtwn_r92c_power_on(struct urtwn_softc *sc) 3798 { 3799 uint32_t reg; 3800 int ntries; 3801 3802 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3803 3804 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3805 3806 /* Wait for autoload done bit. */ 3807 for (ntries = 0; ntries < 1000; ntries++) { 3808 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3809 break; 3810 DELAY(5); 3811 } 3812 if (ntries == 1000) { 3813 aprint_error_dev(sc->sc_dev, 3814 "timeout waiting for chip autoload\n"); 3815 return ETIMEDOUT; 3816 } 3817 3818 /* Unlock ISO/CLK/Power control register. */ 3819 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3820 /* Move SPS into PWM mode. */ 3821 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3822 DELAY(5); 3823 3824 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3825 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3826 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3827 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3828 DELAY(100); 3829 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3830 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3831 ~R92C_SYS_ISO_CTRL_MD2PP); 3832 } 3833 3834 /* Auto enable WLAN. */ 3835 urtwn_write_2(sc, R92C_APS_FSMCO, 3836 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3837 for (ntries = 0; ntries < 1000; ntries++) { 3838 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3839 R92C_APS_FSMCO_APFM_ONMAC)) 3840 break; 3841 DELAY(100); 3842 } 3843 if (ntries == 1000) { 3844 aprint_error_dev(sc->sc_dev, 3845 "timeout waiting for MAC auto ON\n"); 3846 return ETIMEDOUT; 3847 } 3848 3849 /* Enable radio, GPIO and LED functions. */ 3850 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3851 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3852 urtwn_write_2(sc, R92C_APS_FSMCO, 3853 R92C_APS_FSMCO_AFSM_HSUS | 3854 R92C_APS_FSMCO_PDN_EN | 3855 R92C_APS_FSMCO_PFM_ALDN); 3856 3857 /* Release RF digital isolation. */ 3858 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3859 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3860 3861 /* Initialize MAC. */ 3862 urtwn_write_1(sc, R92C_APSD_CTRL, 3863 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3864 for (ntries = 0; ntries < 200; ntries++) { 3865 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3866 R92C_APSD_CTRL_OFF_STATUS)) 3867 break; 3868 DELAY(5); 3869 } 3870 if (ntries == 200) { 3871 aprint_error_dev(sc->sc_dev, 3872 "timeout waiting for MAC initialization\n"); 3873 return ETIMEDOUT; 3874 } 3875 3876 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3877 reg = urtwn_read_2(sc, R92C_CR); 3878 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3879 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3880 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3881 R92C_CR_ENSEC; 3882 urtwn_write_2(sc, R92C_CR, reg); 3883 3884 urtwn_write_1(sc, 0xfe10, 0x19); 3885 return 0; 3886 } 3887 3888 static int 3889 urtwn_r92e_power_on(struct urtwn_softc *sc) 3890 { 3891 uint32_t reg; 3892 uint32_t val; 3893 int ntries; 3894 3895 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3896 3897 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3898 3899 /* Enable radio, GPIO and LED functions. */ 3900 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3901 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3902 urtwn_write_2(sc, R92C_APS_FSMCO, 3903 R92C_APS_FSMCO_AFSM_HSUS | 3904 R92C_APS_FSMCO_PDN_EN | 3905 R92C_APS_FSMCO_PFM_ALDN); 3906 3907 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3908 /* LDO. */ 3909 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3910 } 3911 else { 3912 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3913 R92C_SYS_SWR_CTRL2) & 0xffff); 3914 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3915 } 3916 3917 for (ntries = 0; ntries < 2; ntries++) { 3918 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3919 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3920 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3921 R92C_AFE_CTRL4)); 3922 } 3923 3924 /* Reset BB. */ 3925 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3926 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3927 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3928 3929 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3930 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3931 3932 /* Disable HWPDN. */ 3933 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3934 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3935 3936 /* Disable WL suspend. */ 3937 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3938 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3939 R92C_APS_FSMCO_AFSM_HSUS)); 3940 3941 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3942 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3943 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3944 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3945 for (ntries = 0; ntries < 10000; ntries++) { 3946 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3947 R92C_APS_FSMCO_APFM_ONMAC; 3948 if (val == 0x0) 3949 break; 3950 DELAY(10); 3951 } 3952 if (ntries == 10000) { 3953 aprint_error_dev(sc->sc_dev, 3954 "timeout waiting for chip power up\n"); 3955 return ETIMEDOUT; 3956 } 3957 3958 urtwn_write_2(sc, R92C_CR, 0x00); 3959 reg = urtwn_read_2(sc, R92C_CR); 3960 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3961 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3962 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3963 urtwn_write_2(sc, R92C_CR, reg); 3964 3965 return 0; 3966 } 3967 3968 static int 3969 urtwn_r88e_power_on(struct urtwn_softc *sc) 3970 { 3971 uint32_t reg; 3972 uint8_t val; 3973 int ntries; 3974 3975 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3976 3977 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3978 3979 /* Wait for power ready bit. */ 3980 for (ntries = 0; ntries < 5000; ntries++) { 3981 val = urtwn_read_1(sc, 0x6) & 0x2; 3982 if (val == 0x2) 3983 break; 3984 DELAY(10); 3985 } 3986 if (ntries == 5000) { 3987 aprint_error_dev(sc->sc_dev, 3988 "timeout waiting for chip power up\n"); 3989 return ETIMEDOUT; 3990 } 3991 3992 /* Reset BB. */ 3993 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3994 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3995 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3996 3997 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3998 3999 /* Disable HWPDN. */ 4000 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 4001 4002 /* Disable WL suspend. */ 4003 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 4004 4005 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 4006 for (ntries = 0; ntries < 5000; ntries++) { 4007 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 4008 break; 4009 DELAY(10); 4010 } 4011 if (ntries == 5000) 4012 return ETIMEDOUT; 4013 4014 /* Enable LDO normal mode. */ 4015 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 4016 4017 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 4018 urtwn_write_2(sc, R92C_CR, 0); 4019 reg = urtwn_read_2(sc, R92C_CR); 4020 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 4021 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 4022 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 4023 urtwn_write_2(sc, R92C_CR, reg); 4024 4025 return 0; 4026 } 4027 4028 static int 4029 urtwn_llt_init(struct urtwn_softc *sc) 4030 { 4031 size_t i, page_count, pktbuf_count; 4032 uint32_t val; 4033 int error; 4034 4035 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4036 4037 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4038 4039 if (sc->chip & URTWN_CHIP_88E) 4040 page_count = R88E_TX_PAGE_COUNT; 4041 else if (sc->chip & URTWN_CHIP_92EU) 4042 page_count = R92E_TX_PAGE_COUNT; 4043 else 4044 page_count = R92C_TX_PAGE_COUNT; 4045 if (sc->chip & URTWN_CHIP_88E) 4046 pktbuf_count = R88E_TXPKTBUF_COUNT; 4047 else if (sc->chip & URTWN_CHIP_92EU) 4048 pktbuf_count = R88E_TXPKTBUF_COUNT; 4049 else 4050 pktbuf_count = R92C_TXPKTBUF_COUNT; 4051 4052 if (sc->chip & URTWN_CHIP_92EU) { 4053 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 4054 urtwn_write_4(sc, R92E_AUTO_LLT, val); 4055 DELAY(100); 4056 val = urtwn_read_4(sc, R92E_AUTO_LLT); 4057 if (val & R92E_AUTO_LLT_EN) 4058 return EIO; 4059 return 0; 4060 } 4061 4062 /* Reserve pages [0; page_count]. */ 4063 for (i = 0; i < page_count; i++) { 4064 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4065 return error; 4066 } 4067 /* NB: 0xff indicates end-of-list. */ 4068 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4069 return error; 4070 /* 4071 * Use pages [page_count + 1; pktbuf_count - 1] 4072 * as ring buffer. 4073 */ 4074 for (++i; i < pktbuf_count - 1; i++) { 4075 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4076 return error; 4077 } 4078 /* Make the last page point to the beginning of the ring buffer. */ 4079 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4080 return error; 4081 } 4082 4083 static void 4084 urtwn_fw_reset(struct urtwn_softc *sc) 4085 { 4086 uint16_t reg; 4087 int ntries; 4088 4089 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4090 4091 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4092 4093 /* Tell 8051 to reset itself. */ 4094 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4095 4096 /* Wait until 8051 resets by itself. */ 4097 for (ntries = 0; ntries < 100; ntries++) { 4098 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4099 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4100 return; 4101 DELAY(50); 4102 } 4103 /* Force 8051 reset. */ 4104 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4105 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4106 } 4107 4108 static void 4109 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4110 { 4111 uint16_t reg; 4112 4113 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4114 4115 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4116 4117 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4118 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4119 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4120 } 4121 DELAY(50); 4122 4123 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4124 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4125 DELAY(50); 4126 4127 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4128 DELAY(50); 4129 4130 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4131 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4132 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4133 } 4134 DELAY(50); 4135 4136 } 4137 4138 static int 4139 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4140 { 4141 uint32_t reg; 4142 int off, mlen, error = 0; 4143 4144 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4145 device_xname(sc->sc_dev), __func__, page, buf, len)); 4146 4147 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4148 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4149 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4150 4151 off = R92C_FW_START_ADDR; 4152 while (len > 0) { 4153 if (len > 196) 4154 mlen = 196; 4155 else if (len > 4) 4156 mlen = 4; 4157 else 4158 mlen = 1; 4159 error = urtwn_write_region(sc, off, buf, mlen); 4160 if (error != 0) 4161 break; 4162 off += mlen; 4163 buf += mlen; 4164 len -= mlen; 4165 } 4166 return error; 4167 } 4168 4169 static int 4170 urtwn_load_firmware(struct urtwn_softc *sc) 4171 { 4172 firmware_handle_t fwh; 4173 const struct r92c_fw_hdr *hdr; 4174 const char *name; 4175 u_char *fw, *ptr; 4176 size_t len; 4177 uint32_t reg; 4178 int mlen, ntries, page, error; 4179 4180 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4181 4182 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4183 4184 /* Read firmware image from the filesystem. */ 4185 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4186 name = "rtl8188eufw.bin"; 4187 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4188 name = "rtl8192eefw.bin"; 4189 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4190 URTWN_CHIP_UMC_A_CUT) 4191 name = "rtl8192cfwU.bin"; 4192 else 4193 name = "rtl8192cfw.bin"; 4194 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4195 aprint_error_dev(sc->sc_dev, 4196 "failed load firmware of file %s (error %d)\n", name, 4197 error); 4198 return error; 4199 } 4200 const size_t fwlen = len = firmware_get_size(fwh); 4201 fw = firmware_malloc(len); 4202 if (fw == NULL) { 4203 aprint_error_dev(sc->sc_dev, 4204 "failed to allocate firmware memory\n"); 4205 firmware_close(fwh); 4206 return ENOMEM; 4207 } 4208 error = firmware_read(fwh, 0, fw, len); 4209 firmware_close(fwh); 4210 if (error != 0) { 4211 aprint_error_dev(sc->sc_dev, 4212 "failed to read firmware (error %d)\n", error); 4213 firmware_free(fw, fwlen); 4214 return error; 4215 } 4216 4217 len = fwlen; 4218 ptr = fw; 4219 hdr = (const struct r92c_fw_hdr *)ptr; 4220 /* Check if there is a valid FW header and skip it. */ 4221 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4222 (le16toh(hdr->signature) >> 4) == 0x88e || 4223 (le16toh(hdr->signature) >> 4) == 0x92e || 4224 (le16toh(hdr->signature) >> 4) == 0x92c) { 4225 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4226 device_xname(sc->sc_dev), __func__, 4227 le16toh(hdr->version), le16toh(hdr->subversion), 4228 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4229 ptr += sizeof(*hdr); 4230 len -= sizeof(*hdr); 4231 } 4232 4233 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4234 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4235 ISSET(sc->chip, URTWN_CHIP_92EU)) 4236 urtwn_r88e_fw_reset(sc); 4237 else 4238 urtwn_fw_reset(sc); 4239 } 4240 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4241 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4242 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4243 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4244 R92C_SYS_FUNC_EN_CPUEN); 4245 } 4246 4247 /* download enabled */ 4248 urtwn_write_1(sc, R92C_MCUFWDL, 4249 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4250 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4251 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4252 4253 /* Reset the FWDL checksum. */ 4254 urtwn_write_1(sc, R92C_MCUFWDL, 4255 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4256 4257 DELAY(50); 4258 /* download firmware */ 4259 for (page = 0; len > 0; page++) { 4260 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4261 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4262 if (error != 0) { 4263 aprint_error_dev(sc->sc_dev, 4264 "could not load firmware page %d\n", page); 4265 goto fail; 4266 } 4267 ptr += mlen; 4268 len -= mlen; 4269 } 4270 4271 /* download disable */ 4272 urtwn_write_1(sc, R92C_MCUFWDL, 4273 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4274 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4275 4276 /* Wait for checksum report. */ 4277 for (ntries = 0; ntries < 1000; ntries++) { 4278 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4279 break; 4280 DELAY(5); 4281 } 4282 if (ntries == 1000) { 4283 aprint_error_dev(sc->sc_dev, 4284 "timeout waiting for checksum report\n"); 4285 error = ETIMEDOUT; 4286 goto fail; 4287 } 4288 4289 /* Wait for firmware readiness. */ 4290 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4291 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4292 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4293 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4294 ISSET(sc->chip, URTWN_CHIP_92EU)) 4295 urtwn_r88e_fw_reset(sc); 4296 else 4297 urtwn_fw_reset(sc); 4298 for (ntries = 0; ntries < 6000; ntries++) { 4299 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4300 break; 4301 DELAY(5); 4302 } 4303 if (ntries == 6000) { 4304 aprint_error_dev(sc->sc_dev, 4305 "timeout waiting for firmware readiness\n"); 4306 error = ETIMEDOUT; 4307 goto fail; 4308 } 4309 fail: 4310 firmware_free(fw, fwlen); 4311 return error; 4312 } 4313 4314 static __inline int 4315 urtwn_dma_init(struct urtwn_softc *sc) 4316 { 4317 4318 return sc->sc_dma_init(sc); 4319 } 4320 4321 static int 4322 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4323 { 4324 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4325 uint32_t reg; 4326 int error; 4327 4328 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4329 4330 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4331 4332 /* Initialize LLT table. */ 4333 error = urtwn_llt_init(sc); 4334 if (error != 0) 4335 return error; 4336 4337 /* Get Tx queues to USB endpoints mapping. */ 4338 hashq = hasnq = haslq = 0; 4339 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4340 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping %#x\n", 4341 device_xname(sc->sc_dev), __func__, reg)); 4342 if (MS(reg, R92C_USB_EP_HQ) != 0) 4343 hashq = 1; 4344 if (MS(reg, R92C_USB_EP_NQ) != 0) 4345 hasnq = 1; 4346 if (MS(reg, R92C_USB_EP_LQ) != 0) 4347 haslq = 1; 4348 nqueues = hashq + hasnq + haslq; 4349 if (nqueues == 0) 4350 return EIO; 4351 /* Get the number of pages for each queue. */ 4352 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4353 /* The remaining pages are assigned to the high priority queue. */ 4354 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4355 4356 /* Set number of pages for normal priority queue. */ 4357 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4358 urtwn_write_4(sc, R92C_RQPN, 4359 /* Set number of pages for public queue. */ 4360 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4361 /* Set number of pages for high priority queue. */ 4362 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4363 /* Set number of pages for low priority queue. */ 4364 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4365 /* Load values. */ 4366 R92C_RQPN_LD); 4367 4368 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4369 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4370 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4371 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4372 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4373 4374 /* Set queue to USB pipe mapping. */ 4375 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4376 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4377 if (nqueues == 1) { 4378 if (hashq) { 4379 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4380 } else if (hasnq) { 4381 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4382 } else { 4383 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4384 } 4385 } else if (nqueues == 2) { 4386 /* All 2-endpoints configs have a high priority queue. */ 4387 if (!hashq) { 4388 return EIO; 4389 } 4390 if (hasnq) { 4391 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4392 } else { 4393 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4394 } 4395 } else { 4396 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4397 } 4398 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4399 4400 /* Set Tx/Rx transfer page boundary. */ 4401 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4402 4403 /* Set Tx/Rx transfer page size. */ 4404 urtwn_write_1(sc, R92C_PBP, 4405 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4406 return 0; 4407 } 4408 4409 static int 4410 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4411 { 4412 usb_interface_descriptor_t *id; 4413 uint32_t reg; 4414 int nqueues; 4415 int error; 4416 4417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4418 4419 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4420 4421 /* Initialize LLT table. */ 4422 error = urtwn_llt_init(sc); 4423 if (error != 0) 4424 return error; 4425 4426 /* Get Tx queues to USB endpoints mapping. */ 4427 id = usbd_get_interface_descriptor(sc->sc_iface); 4428 nqueues = id->bNumEndpoints - 1; 4429 if (nqueues == 0) 4430 return EIO; 4431 4432 /* Set number of pages for normal priority queue. */ 4433 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4434 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4435 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4436 4437 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4438 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4439 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4440 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4441 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4442 4443 /* Set queue to USB pipe mapping. */ 4444 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4445 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4446 if (nqueues == 1) 4447 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4448 else if (nqueues == 2) 4449 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4450 else 4451 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4452 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4453 4454 /* Set Tx/Rx transfer page boundary. */ 4455 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4456 4457 /* Set Tx/Rx transfer page size. */ 4458 urtwn_write_1(sc, R92C_PBP, 4459 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4460 4461 return 0; 4462 } 4463 4464 static void 4465 urtwn_mac_init(struct urtwn_softc *sc) 4466 { 4467 size_t i; 4468 4469 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4470 4471 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4472 4473 /* Write MAC initialization values. */ 4474 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4475 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4476 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4477 rtl8188eu_mac[i].val); 4478 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4479 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4480 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4481 rtl8192eu_mac[i].val); 4482 } else { 4483 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4484 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4485 rtl8192cu_mac[i].val); 4486 } 4487 } 4488 4489 static void 4490 urtwn_bb_init(struct urtwn_softc *sc) 4491 { 4492 const struct rtwn_bb_prog *prog; 4493 uint32_t reg; 4494 uint8_t crystalcap; 4495 size_t i; 4496 4497 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4498 4499 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4500 4501 /* Enable BB and RF. */ 4502 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4503 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4504 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4505 R92C_SYS_FUNC_EN_DIO_RF); 4506 4507 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4508 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4509 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4510 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4511 } 4512 4513 urtwn_write_1(sc, R92C_RF_CTRL, 4514 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4515 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4516 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4517 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4518 4519 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4520 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4521 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4522 urtwn_write_1(sc, 0x15, 0xe9); 4523 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4524 } 4525 4526 /* Select BB programming based on board type. */ 4527 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4528 prog = &rtl8188eu_bb_prog; 4529 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4530 prog = &rtl8192eu_bb_prog; 4531 else if (!(sc->chip & URTWN_CHIP_92C)) { 4532 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4533 prog = &rtl8188ce_bb_prog; 4534 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4535 prog = &rtl8188ru_bb_prog; 4536 } else { 4537 prog = &rtl8188cu_bb_prog; 4538 } 4539 } else { 4540 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4541 prog = &rtl8192ce_bb_prog; 4542 } else { 4543 prog = &rtl8192cu_bb_prog; 4544 } 4545 } 4546 /* Write BB initialization values. */ 4547 for (i = 0; i < prog->count; i++) { 4548 /* additional delay depend on registers */ 4549 switch (prog->regs[i]) { 4550 case 0xfe: 4551 urtwn_delay_ms(sc, 50); 4552 break; 4553 case 0xfd: 4554 urtwn_delay_ms(sc, 5); 4555 break; 4556 case 0xfc: 4557 urtwn_delay_ms(sc, 1); 4558 break; 4559 case 0xfb: 4560 DELAY(50); 4561 break; 4562 case 0xfa: 4563 DELAY(5); 4564 break; 4565 case 0xf9: 4566 DELAY(1); 4567 break; 4568 } 4569 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4570 DELAY(1); 4571 } 4572 4573 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4574 /* 8192C 1T only configuration. */ 4575 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4576 reg = (reg & ~0x00000003) | 0x2; 4577 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4578 4579 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4580 reg = (reg & ~0x00300033) | 0x00200022; 4581 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4582 4583 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4584 reg = (reg & ~0xff000000) | (0x45 << 24); 4585 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4586 4587 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4588 reg = (reg & ~0x000000ff) | 0x23; 4589 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4590 4591 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4592 reg = (reg & ~0x00000030) | (1 << 4); 4593 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4594 4595 reg = urtwn_bb_read(sc, 0xe74); 4596 reg = (reg & ~0x0c000000) | (2 << 26); 4597 urtwn_bb_write(sc, 0xe74, reg); 4598 reg = urtwn_bb_read(sc, 0xe78); 4599 reg = (reg & ~0x0c000000) | (2 << 26); 4600 urtwn_bb_write(sc, 0xe78, reg); 4601 reg = urtwn_bb_read(sc, 0xe7c); 4602 reg = (reg & ~0x0c000000) | (2 << 26); 4603 urtwn_bb_write(sc, 0xe7c, reg); 4604 reg = urtwn_bb_read(sc, 0xe80); 4605 reg = (reg & ~0x0c000000) | (2 << 26); 4606 urtwn_bb_write(sc, 0xe80, reg); 4607 reg = urtwn_bb_read(sc, 0xe88); 4608 reg = (reg & ~0x0c000000) | (2 << 26); 4609 urtwn_bb_write(sc, 0xe88, reg); 4610 } 4611 4612 /* Write AGC values. */ 4613 for (i = 0; i < prog->agccount; i++) { 4614 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4615 DELAY(1); 4616 } 4617 4618 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4619 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4620 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4621 DELAY(1); 4622 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4623 DELAY(1); 4624 } 4625 4626 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4627 crystalcap = sc->r88e_rom[0xb9]; 4628 if (crystalcap == 0x00) 4629 crystalcap = 0x20; 4630 crystalcap &= 0x3f; 4631 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4632 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4633 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4634 crystalcap | crystalcap << 6)); 4635 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4636 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4637 crystalcap = sc->r88e_rom[0xb9]; 4638 if (crystalcap == 0xff) 4639 crystalcap = 0x20; 4640 crystalcap &= 0x3f; 4641 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4642 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4643 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4644 crystalcap | crystalcap << 6)); 4645 } else { 4646 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4647 R92C_HSSI_PARAM2_CCK_HIPWR) { 4648 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4649 } 4650 } 4651 } 4652 4653 static void 4654 urtwn_rf_init(struct urtwn_softc *sc) 4655 { 4656 const struct rtwn_rf_prog *prog; 4657 uint32_t reg, mask, saved; 4658 size_t i, j, idx; 4659 4660 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4661 4662 /* Select RF programming based on board type. */ 4663 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4664 prog = rtl8188eu_rf_prog; 4665 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4666 prog = rtl8192eu_rf_prog; 4667 else if (!(sc->chip & URTWN_CHIP_92C)) { 4668 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4669 prog = rtl8188ce_rf_prog; 4670 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4671 prog = rtl8188ru_rf_prog; 4672 } else { 4673 prog = rtl8188cu_rf_prog; 4674 } 4675 } else { 4676 prog = rtl8192ce_rf_prog; 4677 } 4678 4679 for (i = 0; i < sc->nrxchains; i++) { 4680 /* Save RF_ENV control type. */ 4681 idx = i / 2; 4682 mask = 0xffffU << ((i % 2) * 16); 4683 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4684 4685 /* Set RF_ENV enable. */ 4686 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4687 reg |= 0x100000; 4688 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4689 DELAY(50); 4690 4691 /* Set RF_ENV output high. */ 4692 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4693 reg |= 0x10; 4694 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4695 DELAY(50); 4696 4697 /* Set address and data lengths of RF registers. */ 4698 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4699 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4700 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4701 DELAY(50); 4702 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4703 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4704 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4705 DELAY(50); 4706 4707 /* Write RF initialization values for this chain. */ 4708 for (j = 0; j < prog[i].count; j++) { 4709 if (prog[i].regs[j] >= 0xf9 && 4710 prog[i].regs[j] <= 0xfe) { 4711 /* 4712 * These are fake RF registers offsets that 4713 * indicate a delay is required. 4714 */ 4715 urtwn_delay_ms(sc, 50); 4716 continue; 4717 } 4718 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4719 DELAY(5); 4720 } 4721 4722 /* Restore RF_ENV control type. */ 4723 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4724 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4725 } 4726 4727 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4728 URTWN_CHIP_UMC_A_CUT) { 4729 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4730 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4731 } 4732 4733 /* Cache RF register CHNLBW. */ 4734 for (i = 0; i < 2; i++) { 4735 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4736 } 4737 } 4738 4739 static void 4740 urtwn_cam_init(struct urtwn_softc *sc) 4741 { 4742 uint32_t content, command; 4743 uint8_t idx; 4744 size_t i; 4745 4746 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4747 4748 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4749 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4750 return; 4751 4752 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4753 content = (idx & 3) 4754 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4755 | R92C_CAM_VALID; 4756 4757 command = R92C_CAMCMD_POLLING 4758 | R92C_CAMCMD_WRITE 4759 | R92C_CAM_CTL0(idx); 4760 4761 urtwn_write_4(sc, R92C_CAMWRITE, content); 4762 urtwn_write_4(sc, R92C_CAMCMD, command); 4763 } 4764 4765 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4766 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4767 if (i == 0) { 4768 content = (idx & 3) 4769 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4770 | R92C_CAM_VALID; 4771 } else { 4772 content = 0; 4773 } 4774 4775 command = R92C_CAMCMD_POLLING 4776 | R92C_CAMCMD_WRITE 4777 | R92C_CAM_CTL0(idx) 4778 | i; 4779 4780 urtwn_write_4(sc, R92C_CAMWRITE, content); 4781 urtwn_write_4(sc, R92C_CAMCMD, command); 4782 } 4783 } 4784 4785 /* Invalidate all CAM entries. */ 4786 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4787 } 4788 4789 static void 4790 urtwn_pa_bias_init(struct urtwn_softc *sc) 4791 { 4792 uint8_t reg; 4793 size_t i; 4794 4795 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4796 4797 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4798 4799 for (i = 0; i < sc->nrxchains; i++) { 4800 if (sc->pa_setting & (1U << i)) 4801 continue; 4802 4803 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4804 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4805 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4806 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4807 } 4808 if (!(sc->pa_setting & 0x10)) { 4809 reg = urtwn_read_1(sc, 0x16); 4810 reg = (reg & ~0xf0) | 0x90; 4811 urtwn_write_1(sc, 0x16, reg); 4812 } 4813 } 4814 4815 static void 4816 urtwn_rxfilter_init(struct urtwn_softc *sc) 4817 { 4818 4819 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4820 4821 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4822 4823 /* Initialize Rx filter. */ 4824 /* TODO: use better filter for monitor mode. */ 4825 urtwn_write_4(sc, R92C_RCR, 4826 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4827 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4828 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4829 /* Accept all multicast frames. */ 4830 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4831 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4832 /* Accept all management frames. */ 4833 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4834 /* Reject all control frames. */ 4835 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4836 /* Accept all data frames. */ 4837 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4838 } 4839 4840 static void 4841 urtwn_edca_init(struct urtwn_softc *sc) 4842 { 4843 4844 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4845 4846 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4847 4848 /* set spec SIFS (used in NAV) */ 4849 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4850 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4851 4852 /* set SIFS CCK/OFDM */ 4853 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4854 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4855 4856 /* TXOP */ 4857 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4858 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4859 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4860 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4861 } 4862 4863 static void 4864 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4865 uint16_t power[URTWN_RIDX_COUNT]) 4866 { 4867 uint32_t reg; 4868 4869 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4870 __func__, chain)); 4871 4872 /* Write per-CCK rate Tx power. */ 4873 if (chain == 0) { 4874 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4875 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4876 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4877 4878 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4879 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4880 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4881 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4882 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4883 } else { 4884 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4885 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4886 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4887 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4888 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4889 4890 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4891 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4892 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4893 } 4894 /* Write per-OFDM rate Tx power. */ 4895 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4896 SM(R92C_TXAGC_RATE06, power[ 4]) | 4897 SM(R92C_TXAGC_RATE09, power[ 5]) | 4898 SM(R92C_TXAGC_RATE12, power[ 6]) | 4899 SM(R92C_TXAGC_RATE18, power[ 7])); 4900 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4901 SM(R92C_TXAGC_RATE24, power[ 8]) | 4902 SM(R92C_TXAGC_RATE36, power[ 9]) | 4903 SM(R92C_TXAGC_RATE48, power[10]) | 4904 SM(R92C_TXAGC_RATE54, power[11])); 4905 /* Write per-MCS Tx power. */ 4906 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4907 SM(R92C_TXAGC_MCS00, power[12]) | 4908 SM(R92C_TXAGC_MCS01, power[13]) | 4909 SM(R92C_TXAGC_MCS02, power[14]) | 4910 SM(R92C_TXAGC_MCS03, power[15])); 4911 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4912 SM(R92C_TXAGC_MCS04, power[16]) | 4913 SM(R92C_TXAGC_MCS05, power[17]) | 4914 SM(R92C_TXAGC_MCS06, power[18]) | 4915 SM(R92C_TXAGC_MCS07, power[19])); 4916 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4917 SM(R92C_TXAGC_MCS08, power[20]) | 4918 SM(R92C_TXAGC_MCS09, power[21]) | 4919 SM(R92C_TXAGC_MCS10, power[22]) | 4920 SM(R92C_TXAGC_MCS11, power[23])); 4921 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4922 SM(R92C_TXAGC_MCS12, power[24]) | 4923 SM(R92C_TXAGC_MCS13, power[25]) | 4924 SM(R92C_TXAGC_MCS14, power[26]) | 4925 SM(R92C_TXAGC_MCS15, power[27])); 4926 } 4927 4928 static void 4929 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4930 uint16_t power[URTWN_RIDX_COUNT]) 4931 { 4932 struct r92c_rom *rom = &sc->rom; 4933 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4934 const struct rtwn_txpwr *base; 4935 int ridx, group; 4936 4937 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4938 device_xname(sc->sc_dev), __func__, chain, chan)); 4939 4940 /* Determine channel group. */ 4941 if (chan <= 3) { 4942 group = 0; 4943 } else if (chan <= 9) { 4944 group = 1; 4945 } else { 4946 group = 2; 4947 } 4948 4949 /* Get original Tx power based on board type and RF chain. */ 4950 if (!(sc->chip & URTWN_CHIP_92C)) { 4951 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4952 base = &rtl8188ru_txagc[chain]; 4953 } else { 4954 base = &rtl8192cu_txagc[chain]; 4955 } 4956 } else { 4957 base = &rtl8192cu_txagc[chain]; 4958 } 4959 4960 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4961 if (sc->regulatory == 0) { 4962 for (ridx = 0; ridx <= 3; ridx++) { 4963 power[ridx] = base->pwr[0][ridx]; 4964 } 4965 } 4966 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4967 if (sc->regulatory == 3) { 4968 power[ridx] = base->pwr[0][ridx]; 4969 /* Apply vendor limits. */ 4970 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4971 maxpow = rom->ht40_max_pwr[group]; 4972 } else { 4973 maxpow = rom->ht20_max_pwr[group]; 4974 } 4975 maxpow = (maxpow >> (chain * 4)) & 0xf; 4976 if (power[ridx] > maxpow) { 4977 power[ridx] = maxpow; 4978 } 4979 } else if (sc->regulatory == 1) { 4980 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4981 power[ridx] = base->pwr[group][ridx]; 4982 } 4983 } else if (sc->regulatory != 2) { 4984 power[ridx] = base->pwr[0][ridx]; 4985 } 4986 } 4987 4988 /* Compute per-CCK rate Tx power. */ 4989 cckpow = rom->cck_tx_pwr[chain][group]; 4990 for (ridx = 0; ridx <= 3; ridx++) { 4991 power[ridx] += cckpow; 4992 if (power[ridx] > R92C_MAX_TX_PWR) { 4993 power[ridx] = R92C_MAX_TX_PWR; 4994 } 4995 } 4996 4997 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4998 if (sc->ntxchains > 1) { 4999 /* Apply reduction for 2 spatial streams. */ 5000 diff = rom->ht40_2s_tx_pwr_diff[group]; 5001 diff = (diff >> (chain * 4)) & 0xf; 5002 htpow = (htpow > diff) ? htpow - diff : 0; 5003 } 5004 5005 /* Compute per-OFDM rate Tx power. */ 5006 diff = rom->ofdm_tx_pwr_diff[group]; 5007 diff = (diff >> (chain * 4)) & 0xf; 5008 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 5009 for (ridx = 4; ridx <= 11; ridx++) { 5010 power[ridx] += ofdmpow; 5011 if (power[ridx] > R92C_MAX_TX_PWR) { 5012 power[ridx] = R92C_MAX_TX_PWR; 5013 } 5014 } 5015 5016 /* Compute per-MCS Tx power. */ 5017 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 5018 diff = rom->ht20_tx_pwr_diff[group]; 5019 diff = (diff >> (chain * 4)) & 0xf; 5020 htpow += diff; /* HT40->HT20 correction. */ 5021 } 5022 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 5023 power[ridx] += htpow; 5024 if (power[ridx] > R92C_MAX_TX_PWR) { 5025 power[ridx] = R92C_MAX_TX_PWR; 5026 } 5027 } 5028 #ifdef URTWN_DEBUG 5029 if (urtwn_debug & DBG_RF) { 5030 /* Dump per-rate Tx power values. */ 5031 printf("%s: %s: Tx power for chain %zd:\n", 5032 device_xname(sc->sc_dev), __func__, chain); 5033 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 5034 printf("%s: %s: Rate %d = %u\n", 5035 device_xname(sc->sc_dev), __func__, ridx, 5036 power[ridx]); 5037 } 5038 } 5039 #endif 5040 } 5041 5042 void 5043 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 5044 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 5045 { 5046 uint16_t cckpow, ofdmpow, bw20pow, htpow; 5047 const struct rtwn_r88e_txpwr *base; 5048 int ridx, group; 5049 5050 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 5051 device_xname(sc->sc_dev), __func__, chain, chan)); 5052 5053 /* Determine channel group. */ 5054 if (chan <= 2) 5055 group = 0; 5056 else if (chan <= 5) 5057 group = 1; 5058 else if (chan <= 8) 5059 group = 2; 5060 else if (chan <= 11) 5061 group = 3; 5062 else if (chan <= 13) 5063 group = 4; 5064 else 5065 group = 5; 5066 5067 /* Get original Tx power based on board type and RF chain. */ 5068 base = &rtl8188eu_txagc[chain]; 5069 5070 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5071 if (sc->regulatory == 0) { 5072 for (ridx = 0; ridx <= 3; ridx++) 5073 power[ridx] = base->pwr[0][ridx]; 5074 } 5075 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5076 if (sc->regulatory == 3) 5077 power[ridx] = base->pwr[0][ridx]; 5078 else if (sc->regulatory == 1) { 5079 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5080 power[ridx] = base->pwr[group][ridx]; 5081 } else if (sc->regulatory != 2) 5082 power[ridx] = base->pwr[0][ridx]; 5083 } 5084 5085 /* Compute per-CCK rate Tx power. */ 5086 cckpow = sc->cck_tx_pwr[group]; 5087 for (ridx = 0; ridx <= 3; ridx++) { 5088 power[ridx] += cckpow; 5089 if (power[ridx] > R92C_MAX_TX_PWR) 5090 power[ridx] = R92C_MAX_TX_PWR; 5091 } 5092 5093 htpow = sc->ht40_tx_pwr[group]; 5094 5095 /* Compute per-OFDM rate Tx power. */ 5096 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5097 for (ridx = 4; ridx <= 11; ridx++) { 5098 power[ridx] += ofdmpow; 5099 if (power[ridx] > R92C_MAX_TX_PWR) 5100 power[ridx] = R92C_MAX_TX_PWR; 5101 } 5102 5103 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5104 for (ridx = 12; ridx <= 27; ridx++) { 5105 power[ridx] += bw20pow; 5106 if (power[ridx] > R92C_MAX_TX_PWR) 5107 power[ridx] = R92C_MAX_TX_PWR; 5108 } 5109 } 5110 5111 static void 5112 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5113 { 5114 uint16_t power[URTWN_RIDX_COUNT]; 5115 size_t i; 5116 5117 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5118 5119 for (i = 0; i < sc->ntxchains; i++) { 5120 /* Compute per-rate Tx power values. */ 5121 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5122 ISSET(sc->chip, URTWN_CHIP_92EU)) 5123 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5124 else 5125 urtwn_get_txpower(sc, i, chan, ht40m, power); 5126 /* Write per-rate Tx power values to hardware. */ 5127 urtwn_write_txpower(sc, i, power); 5128 } 5129 } 5130 5131 static void 5132 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5133 { 5134 struct ieee80211com *ic = &sc->sc_ic; 5135 u_int chan; 5136 size_t i; 5137 5138 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5139 5140 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5141 __func__, chan)); 5142 5143 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5144 5145 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5146 chan += 2; 5147 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5148 chan -= 2; 5149 } 5150 5151 /* Set Tx power for this new channel. */ 5152 urtwn_set_txpower(sc, chan, ht40m); 5153 5154 for (i = 0; i < sc->nrxchains; i++) { 5155 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5156 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5157 } 5158 5159 if (ht40m) { 5160 /* Is secondary channel below or above primary? */ 5161 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5162 uint32_t reg; 5163 5164 urtwn_write_1(sc, R92C_BWOPMODE, 5165 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5166 5167 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5168 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5169 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5170 5171 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5172 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5173 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5174 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5175 5176 /* Set CCK side band. */ 5177 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5178 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5179 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5180 5181 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5182 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5183 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5184 5185 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5186 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5187 ~R92C_FPGA0_ANAPARAM2_CBW20); 5188 5189 reg = urtwn_bb_read(sc, 0x818); 5190 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5191 urtwn_bb_write(sc, 0x818, reg); 5192 5193 /* Select 40MHz bandwidth. */ 5194 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5195 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5196 } else { 5197 urtwn_write_1(sc, R92C_BWOPMODE, 5198 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5199 5200 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5201 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5202 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5203 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5204 5205 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5206 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5207 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5208 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5209 R92C_FPGA0_ANAPARAM2_CBW20); 5210 } 5211 5212 /* Select 20MHz bandwidth. */ 5213 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5214 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5215 (ISSET(sc->chip, URTWN_CHIP_88E) || 5216 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5217 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5218 } 5219 } 5220 5221 static void 5222 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5223 { 5224 5225 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5226 __func__, inited)); 5227 5228 uint32_t addaBackup[16], iqkBackup[4], piMode; 5229 5230 #ifdef notyet 5231 uint32_t odfm0_agccore_regs[3]; 5232 uint32_t ant_regs[3]; 5233 uint32_t rf_regs[8]; 5234 #endif 5235 uint32_t reg0, reg1, reg2; 5236 int i, attempt; 5237 5238 #ifdef notyet 5239 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5240 R92E_STBC_SETTING + 2)); 5241 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5242 /* Save AGCCORE regs. */ 5243 for (i = 0; i < sc->nrxchains; i++) { 5244 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5245 R92C_OFDM0_AGCCORE1(i)); 5246 } 5247 #endif 5248 /* Save BB regs. */ 5249 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5250 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5251 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5252 5253 /* Save adda regs to be restored when finished. */ 5254 for (i = 0; i < __arraycount(addaReg); i++) 5255 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5256 /* Save mac regs. */ 5257 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5258 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5259 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5260 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5261 5262 #ifdef notyet 5263 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5264 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5265 5266 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5267 for (i = 0; i < sc->nrxchains; i++) 5268 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5269 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5270 #endif 5271 5272 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5273 R92C_HSSI_PARAM1_PI); 5274 if (piMode == 0) { 5275 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5276 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5277 R92C_HSSI_PARAM1_PI); 5278 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5279 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5280 R92C_HSSI_PARAM1_PI); 5281 } 5282 5283 attempt = 1; 5284 5285 next_attempt: 5286 5287 /* Set mac regs for calibration. */ 5288 for (i = 0; i < __arraycount(addaReg); i++) { 5289 urtwn_bb_write(sc, addaReg[i], 5290 addaReg[__arraycount(addaReg) - 1]); 5291 } 5292 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5293 R92C_CCK0_AFESETTING)); 5294 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5295 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5296 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5297 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5298 5299 if (sc->ntxchains > 1) 5300 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5301 5302 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5303 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5304 ~R92C_BCN_CTRL_EN_BCN)); 5305 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5306 ~R92C_BCN_CTRL_EN_BCN)); 5307 5308 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5309 ~R92C_GPIO_MUXCFG_ENBT)); 5310 5311 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5312 5313 if (sc->ntxchains > 1) 5314 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5315 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5316 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5317 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5318 5319 /* Restore BB regs. */ 5320 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5321 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5322 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5323 5324 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5325 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5326 if (sc->nrxchains > 1) 5327 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5328 5329 if (attempt-- > 0) 5330 goto next_attempt; 5331 5332 /* Restore mode. */ 5333 if (piMode == 0) { 5334 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5335 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5336 ~R92C_HSSI_PARAM1_PI); 5337 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5338 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5339 ~R92C_HSSI_PARAM1_PI); 5340 } 5341 5342 #ifdef notyet 5343 for (i = 0; i < sc->nrxchains; i++) { 5344 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5345 odfm0_agccore_regs[i]); 5346 } 5347 #endif 5348 5349 /* Restore adda regs. */ 5350 for (i = 0; i < __arraycount(addaReg); i++) 5351 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5352 /* Restore mac regs. */ 5353 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5354 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5355 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5356 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5357 5358 #ifdef notyet 5359 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5360 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5361 5362 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5363 for (i = 0; i < sc->nrxchains; i++) 5364 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5365 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5366 #endif 5367 } 5368 5369 static void 5370 urtwn_lc_calib(struct urtwn_softc *sc) 5371 { 5372 uint32_t rf_ac[2]; 5373 uint8_t txmode; 5374 size_t i; 5375 5376 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5377 5378 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5379 5380 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5381 if ((txmode & 0x70) != 0) { 5382 /* Disable all continuous Tx. */ 5383 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5384 5385 /* Set RF mode to standby mode. */ 5386 for (i = 0; i < sc->nrxchains; i++) { 5387 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5388 urtwn_rf_write(sc, i, R92C_RF_AC, 5389 RW(rf_ac[i], R92C_RF_AC_MODE, 5390 R92C_RF_AC_MODE_STANDBY)); 5391 } 5392 } else { 5393 /* Block all Tx queues. */ 5394 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5395 } 5396 /* Start calibration. */ 5397 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5398 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5399 5400 /* Give calibration the time to complete. */ 5401 urtwn_delay_ms(sc, 100); 5402 5403 /* Restore configuration. */ 5404 if ((txmode & 0x70) != 0) { 5405 /* Restore Tx mode. */ 5406 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5407 /* Restore RF mode. */ 5408 for (i = 0; i < sc->nrxchains; i++) { 5409 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5410 } 5411 } else { 5412 /* Unblock all Tx queues. */ 5413 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5414 } 5415 } 5416 5417 static void 5418 urtwn_temp_calib(struct urtwn_softc *sc) 5419 { 5420 int temp, t_meter_reg; 5421 5422 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5423 5424 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5425 5426 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5427 t_meter_reg = R92C_RF_T_METER; 5428 else 5429 t_meter_reg = R92E_RF_T_METER; 5430 5431 if (sc->thcal_state == 0) { 5432 /* Start measuring temperature. */ 5433 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5434 device_xname(sc->sc_dev), __func__)); 5435 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5436 sc->thcal_state = 1; 5437 return; 5438 } 5439 sc->thcal_state = 0; 5440 5441 /* Read measured temperature. */ 5442 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5443 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5444 __func__, temp)); 5445 if (temp == 0) /* Read failed, skip. */ 5446 return; 5447 5448 /* 5449 * Redo LC calibration if temperature changed significantly since 5450 * last calibration. 5451 */ 5452 if (sc->thcal_lctemp == 0) { 5453 /* First LC calibration is performed in urtwn_init(). */ 5454 sc->thcal_lctemp = temp; 5455 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5456 DPRINTFN(DBG_RF, 5457 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5458 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5459 temp)); 5460 urtwn_lc_calib(sc); 5461 /* Record temperature of last LC calibration. */ 5462 sc->thcal_lctemp = temp; 5463 } 5464 } 5465 5466 static int 5467 urtwn_init(struct ifnet *ifp) 5468 { 5469 struct ieee80211vap *vap = ifp->if_softc; 5470 struct ieee80211com *ic = vap->iv_ic; 5471 struct urtwn_softc *sc = ic->ic_softc; 5472 struct urtwn_rx_data *data; 5473 uint32_t reg; 5474 size_t i; 5475 int error; 5476 5477 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5478 5479 urtwn_stop(ifp, 0); 5480 5481 mutex_enter(&sc->sc_write_mtx); 5482 5483 mutex_enter(&sc->sc_task_mtx); 5484 /* Init host async commands ring. */ 5485 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5486 mutex_exit(&sc->sc_task_mtx); 5487 5488 mutex_enter(&sc->sc_fwcmd_mtx); 5489 /* Init firmware commands ring. */ 5490 sc->fwcur = 0; 5491 mutex_exit(&sc->sc_fwcmd_mtx); 5492 5493 /* Allocate Tx/Rx buffers. */ 5494 error = urtwn_alloc_rx_list(sc); 5495 if (error != 0) { 5496 aprint_error_dev(sc->sc_dev, 5497 "could not allocate Rx buffers\n"); 5498 goto fail; 5499 } 5500 error = urtwn_alloc_tx_list(sc); 5501 if (error != 0) { 5502 aprint_error_dev(sc->sc_dev, 5503 "could not allocate Tx buffers\n"); 5504 goto fail; 5505 } 5506 5507 /* Power on adapter. */ 5508 error = urtwn_power_on(sc); 5509 if (error != 0) 5510 goto fail; 5511 5512 /* Initialize DMA. */ 5513 error = urtwn_dma_init(sc); 5514 if (error != 0) 5515 goto fail; 5516 5517 /* Set info size in Rx descriptors (in 64-bit words). */ 5518 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5519 5520 /* Init interrupts. */ 5521 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5522 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5523 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5524 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5525 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5526 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5527 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5528 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5529 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5530 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5531 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5532 } 5533 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5534 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5535 } else { 5536 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5537 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5538 } 5539 5540 /* Set MAC address. */ 5541 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5542 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5543 5544 /* Set initial network type. */ 5545 reg = urtwn_read_4(sc, R92C_CR); 5546 switch (ic->ic_opmode) { 5547 case IEEE80211_M_STA: 5548 default: 5549 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5550 break; 5551 5552 case IEEE80211_M_IBSS: 5553 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5554 break; 5555 } 5556 urtwn_write_4(sc, R92C_CR, reg); 5557 5558 /* Set response rate */ 5559 reg = urtwn_read_4(sc, R92C_RRSR); 5560 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5561 urtwn_write_4(sc, R92C_RRSR, reg); 5562 5563 /* SIFS (used in NAV) */ 5564 urtwn_write_2(sc, R92C_SPEC_SIFS, 5565 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5566 5567 /* Set short/long retry limits. */ 5568 urtwn_write_2(sc, R92C_RL, 5569 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5570 5571 /* Initialize EDCA parameters. */ 5572 urtwn_edca_init(sc); 5573 5574 /* Setup rate fallback. */ 5575 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5576 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5577 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5578 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5579 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5580 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5581 } 5582 5583 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5584 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5585 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5586 /* Set ACK timeout. */ 5587 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5588 5589 /* Setup USB aggregation. */ 5590 /* Tx */ 5591 reg = urtwn_read_4(sc, R92C_TDECTRL); 5592 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5593 urtwn_write_4(sc, R92C_TDECTRL, reg); 5594 /* Rx */ 5595 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5596 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5597 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5598 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5599 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5600 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5601 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5602 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5603 ISSET(sc->chip, URTWN_CHIP_92EU)) 5604 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5605 else 5606 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5607 5608 /* Initialize beacon parameters. */ 5609 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5610 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5611 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5612 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5613 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5614 5615 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5616 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5617 /* Setup AMPDU aggregation. */ 5618 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5619 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5620 urtwn_write_2(sc, 0x4ca, 0x0708); 5621 5622 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5623 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5624 } 5625 5626 /* Load 8051 microcode. */ 5627 error = urtwn_load_firmware(sc); 5628 if (error != 0) 5629 goto fail; 5630 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5631 5632 /* Initialize MAC/BB/RF blocks. */ 5633 /* 5634 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5635 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5636 * XXX: This setting should be removed from rtl8192cu_mac[]. 5637 */ 5638 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5639 urtwn_rxfilter_init(sc); // reset R92C_RCR 5640 urtwn_bb_init(sc); 5641 urtwn_rf_init(sc); 5642 5643 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5644 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5645 urtwn_write_2(sc, R92C_CR, 5646 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5647 R92C_CR_MACRXEN); 5648 } 5649 5650 /* Turn CCK and OFDM blocks on. */ 5651 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5652 reg |= R92C_RFMOD_CCK_EN; 5653 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5654 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5655 reg |= R92C_RFMOD_OFDM_EN; 5656 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5657 5658 /* Clear per-station keys table. */ 5659 urtwn_cam_init(sc); 5660 5661 /* Enable hardware sequence numbering. */ 5662 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5663 5664 /* Perform LO and IQ calibrations. */ 5665 urtwn_iq_calib(sc, sc->iqk_inited); 5666 sc->iqk_inited = true; 5667 5668 /* Perform LC calibration. */ 5669 urtwn_lc_calib(sc); 5670 5671 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5672 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5673 /* Fix USB interference issue. */ 5674 urtwn_write_1(sc, 0xfe40, 0xe0); 5675 urtwn_write_1(sc, 0xfe41, 0x8d); 5676 urtwn_write_1(sc, 0xfe42, 0x80); 5677 urtwn_write_4(sc, 0x20c, 0xfd0320); 5678 5679 urtwn_pa_bias_init(sc); 5680 } 5681 5682 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5683 !(sc->chip & URTWN_CHIP_92EU)) { 5684 /* 1T1R */ 5685 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5686 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5687 } 5688 5689 /* Initialize GPIO setting. */ 5690 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5691 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5692 5693 /* Fix for lower temperature. */ 5694 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5695 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5696 urtwn_write_1(sc, 0x15, 0xe9); 5697 5698 /* Set default channel. */ 5699 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5700 5701 /* Queue Rx xfers. */ 5702 for (size_t j = 0; j < sc->rx_npipe; j++) { 5703 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5704 data = &sc->rx_data[j][i]; 5705 usbd_setup_xfer(data->xfer, data, data->buf, 5706 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5707 urtwn_rxeof); 5708 error = usbd_transfer(data->xfer); 5709 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5710 error != USBD_IN_PROGRESS)) 5711 goto fail; 5712 } 5713 } 5714 5715 /* We're ready to go. */ 5716 ifp->if_flags &= ~IFF_OACTIVE; 5717 ifp->if_flags |= IFF_RUNNING; 5718 sc->sc_running = true; 5719 5720 mutex_exit(&sc->sc_write_mtx); 5721 5722 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5723 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5724 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5725 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5726 urtwn_wait_async(sc); 5727 5728 /* Init the rest of the 802.11 stuff */ 5729 ieee80211_init(ifp); 5730 5731 return 0; 5732 5733 fail: 5734 mutex_exit(&sc->sc_write_mtx); 5735 5736 urtwn_stop(ifp, 1); 5737 return error; 5738 } 5739 5740 static void 5741 urtwn_stop(struct ifnet *ifp, int disable) 5742 { 5743 struct ieee80211vap *vap = ifp->if_softc; 5744 struct ieee80211com *ic = vap->iv_ic; 5745 struct urtwn_softc *sc = ic->ic_softc; 5746 size_t i; 5747 int s; 5748 5749 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5750 5751 s = splusb(); 5752 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5753 urtwn_wait_async(sc); 5754 splx(s); 5755 5756 sc->tx_timer = 0; 5757 ifp->if_timer = 0; 5758 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5759 5760 callout_stop(&sc->sc_scan_to); 5761 callout_stop(&sc->sc_calib_to); 5762 5763 /* Abort Tx. */ 5764 for (i = 0; i < sc->tx_npipe; i++) { 5765 if (sc->tx_pipe[i] != NULL) 5766 usbd_abort_pipe(sc->tx_pipe[i]); 5767 } 5768 5769 /* Stop Rx pipe. */ 5770 for (i = 0; i < sc->rx_npipe; i++) { 5771 if (sc->rx_pipe[i] != NULL) 5772 usbd_abort_pipe(sc->rx_pipe[i]); 5773 } 5774 5775 /* Free Tx/Rx buffers. */ 5776 urtwn_free_tx_list(sc); 5777 urtwn_free_rx_list(sc); 5778 5779 sc->sc_running = false; 5780 if (disable) 5781 urtwn_chip_stop(sc); 5782 } 5783 5784 static int 5785 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5786 { 5787 struct ifnet *ifp = vap->iv_ifp; 5788 struct urtwn_softc *sc = ifp->if_softc; 5789 struct ieee80211com *ic = &sc->sc_ic; 5790 5791 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5792 return ENETRESET; 5793 5794 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5795 5796 return 0; 5797 } 5798 5799 static void 5800 urtwn_chip_stop(struct urtwn_softc *sc) 5801 { 5802 uint32_t reg; 5803 bool disabled = true; 5804 5805 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5806 5807 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5808 ISSET(sc->chip, URTWN_CHIP_92EU)) 5809 return; 5810 5811 mutex_enter(&sc->sc_write_mtx); 5812 5813 /* 5814 * RF Off Sequence 5815 */ 5816 /* Pause MAC TX queue */ 5817 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5818 5819 /* Disable RF */ 5820 urtwn_rf_write(sc, 0, 0, 0); 5821 5822 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5823 5824 /* Reset BB state machine */ 5825 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5826 R92C_SYS_FUNC_EN_USBD | 5827 R92C_SYS_FUNC_EN_USBA | 5828 R92C_SYS_FUNC_EN_BB_GLB_RST); 5829 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5830 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5831 5832 /* 5833 * Reset digital sequence 5834 */ 5835 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5836 /* Reset MCU ready status */ 5837 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5838 /* If firmware in ram code, do reset */ 5839 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5840 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5841 ISSET(sc->chip, URTWN_CHIP_92EU)) 5842 urtwn_r88e_fw_reset(sc); 5843 else 5844 urtwn_fw_reset(sc); 5845 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5846 } 5847 } 5848 5849 /* Reset MAC and Enable 8051 */ 5850 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5851 5852 /* Reset MCU ready status */ 5853 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5854 5855 if (disabled) { 5856 /* Disable MAC clock */ 5857 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5858 /* Disable AFE PLL */ 5859 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5860 /* Gated AFE DIG_CLOCK */ 5861 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5862 /* Isolated digital to PON */ 5863 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5864 } 5865 5866 /* 5867 * Pull GPIO PIN to balance level and LED control 5868 */ 5869 /* 1. Disable GPIO[7:0] */ 5870 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5871 5872 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5873 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5874 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5875 5876 /* Disable GPIO[10:8] */ 5877 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5878 5879 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5880 reg |= (((reg & 0x000f) << 4) | 0x0780); 5881 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5882 5883 /* Disable LED0 & 1 */ 5884 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5885 5886 /* 5887 * Reset digital sequence 5888 */ 5889 if (disabled) { 5890 /* Disable ELDR clock */ 5891 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5892 /* Isolated ELDR to PON */ 5893 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5894 } 5895 5896 /* 5897 * Disable analog sequence 5898 */ 5899 if (disabled) { 5900 /* Disable A15 power */ 5901 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5902 /* Disable digital core power */ 5903 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5904 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5905 ~R92C_LDOV12D_CTRL_LDV12_EN); 5906 } 5907 5908 /* Enter PFM mode */ 5909 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5910 5911 /* Set USB suspend */ 5912 urtwn_write_2(sc, R92C_APS_FSMCO, 5913 R92C_APS_FSMCO_APDM_HOST | 5914 R92C_APS_FSMCO_AFSM_HSUS | 5915 R92C_APS_FSMCO_PFM_ALDN); 5916 5917 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5918 5919 mutex_exit(&sc->sc_write_mtx); 5920 } 5921 5922 static void 5923 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5924 { 5925 if (sc->sc_running == false) 5926 DELAY(ms * 1000); 5927 else 5928 usbd_delay_ms(sc->sc_udev, ms); 5929 } 5930 5931 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5932 5933 #ifdef _MODULE 5934 #include "ioconf.c" 5935 #endif 5936 5937 static int 5938 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5939 { 5940 int error = 0; 5941 5942 switch (cmd) { 5943 case MODULE_CMD_INIT: 5944 #ifdef _MODULE 5945 error = config_init_component(cfdriver_ioconf_urtwn, 5946 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5947 #endif 5948 return error; 5949 case MODULE_CMD_FINI: 5950 #ifdef _MODULE 5951 error = config_fini_component(cfdriver_ioconf_urtwn, 5952 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5953 #endif 5954 return error; 5955 default: 5956 return ENOTTY; 5957 } 5958 } 5959
Indexes created Fri Oct 03 02:09:57 GMT 2025