if_urtwn.c revision 1.59.2.18
1 /* $NetBSD: if_urtwn.c,v 1.59.2.18 2020/04/27 07:38:25 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.18 2020/04/27 07:38:25 nat Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 /* urtwn data */ 227 static const uint8_t urtwn_chan_2ghz[] = 228 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 229 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct ieee80211vap *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 289 int); 290 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ieee80211vap *, u_long); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 /* Functions for wifi refresh */ 340 static struct ieee80211vap * 341 urtwn_vap_create(struct ieee80211com *, 342 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 343 const uint8_t [IEEE80211_ADDR_LEN], 344 const uint8_t [IEEE80211_ADDR_LEN]); 345 static void urtwn_vap_delete(struct ieee80211vap *); 346 static int urtwn_ioctl(struct ifnet *, u_long, void *); 347 static void urtwn_parent(struct ieee80211com *); 348 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 349 struct ieee80211_channel []); 350 static void urtwn_scan_start(struct ieee80211com *); 351 static void urtwn_scan_end(struct ieee80211com *); 352 static void urtwn_set_channel(struct ieee80211com *); 353 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 354 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 355 const struct ieee80211_bpf_params *); 356 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 363 364 static const uint16_t addaReg[] = { 365 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 366 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 367 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 368 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 369 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 370 }; 371 372 static int 373 urtwn_match(device_t parent, cfdata_t match, void *aux) 374 { 375 struct usb_attach_arg *uaa = aux; 376 377 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 378 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 379 } 380 381 static void 382 urtwn_attach(device_t parent, device_t self, void *aux) 383 { 384 struct urtwn_softc *sc = device_private(self); 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct usb_attach_arg *uaa = aux; 387 char *devinfop; 388 const struct urtwn_dev *dev; 389 usb_device_request_t req; 390 // NNN loop below size_t i; 391 int error; 392 393 sc->sc_dev = self; 394 sc->sc_udev = uaa->uaa_device; 395 396 /* Name the ic. */ 397 ic->ic_name = "urtwn"; 398 399 /* Driver Send queue, separate from the if send queue*/ 400 sc->sc_sendq.ifq_maxlen = 32; 401 /* NNN how should this be initialized? */ 402 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 403 sc->sc_sendq.ifq_len = 0; 404 sc->sc_sendq.ifq_drops = 0; 405 IFQ_LOCK_INIT(&sc->sc_sendq); 406 407 sc->chip = 0; 408 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 409 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 410 SET(sc->chip, URTWN_CHIP_88E); 411 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 412 SET(sc->chip, URTWN_CHIP_92EU); 413 414 aprint_naive("\n"); 415 aprint_normal("\n"); 416 417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 418 419 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 420 aprint_normal_dev(self, "%s\n", devinfop); 421 usbd_devinfo_free(devinfop); 422 423 req.bmRequestType = UT_WRITE_DEVICE; 424 req.bRequest = UR_SET_FEATURE; 425 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 426 USETW(req.wIndex, UHF_PORT_SUSPEND); 427 USETW(req.wLength, 0); 428 429 (void) usbd_do_request(sc->sc_udev, &req, 0); 430 431 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 432 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 434 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 435 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 436 437 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 438 439 /* NNN make these callouts use a vap ... in vap create??? */ 440 callout_init(&sc->sc_scan_to, 0); 441 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 442 callout_init(&sc->sc_calib_to, 0); 443 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 444 445 error = usbd_set_config_no(sc->sc_udev, 1, 0); 446 if (error != 0) { 447 aprint_error_dev(self, "failed to set configuration" 448 ", err=%s\n", usbd_errstr(error)); 449 goto fail; 450 } 451 452 /* Get the first interface handle. */ 453 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 454 if (error != 0) { 455 aprint_error_dev(self, "could not get interface handle\n"); 456 goto fail; 457 } 458 459 error = urtwn_read_chipid(sc); 460 if (error != 0) { 461 aprint_error_dev(self, "unsupported test chip\n"); 462 goto fail; 463 } 464 465 /* Determine number of Tx/Rx chains. */ 466 if (sc->chip & URTWN_CHIP_92C) { 467 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 468 sc->nrxchains = 2; 469 } else if (sc->chip & URTWN_CHIP_92EU) { 470 sc->ntxchains = 2; 471 sc->nrxchains = 2; 472 } else { 473 sc->ntxchains = 1; 474 sc->nrxchains = 1; 475 } 476 477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 478 ISSET(sc->chip, URTWN_CHIP_92EU)) 479 urtwn_r88e_read_rom(sc); 480 else 481 urtwn_read_rom(sc); 482 483 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 484 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 485 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 486 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 487 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 488 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 489 "8188CUS", sc->ntxchains, sc->nrxchains, 490 ether_sprintf(ic->ic_macaddr)); 491 492 error = urtwn_open_pipes(sc); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 495 goto fail; 496 } 497 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 498 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 499 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 500 501 /* 502 * Setup the 802.11 device. 503 */ 504 ic->ic_softc = sc; 505 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 506 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 507 508 /* Set device capabilities. */ 509 ic->ic_caps = 510 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 511 IEEE80211_C_IBSS | /* IBSS mode supported */ 512 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 513 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 514 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 515 IEEE80211_C_WME | /* 802.11e */ 516 IEEE80211_C_WPA; /* 802.11i */ 517 518 ic->ic_htcaps = 519 IEEE80211_HTC_HT | 520 IEEE80211_HTCAP_SHORTGI20 | /* short GI in 20MHz */ 521 #if 0 522 IEEE80211_HTCAP_MAXAMSDU_3839 | /* max A-MSDU length */ 523 #endif 524 IEEE80211_HTCAP_SMPS_OFF; /* SM PS mode disabled */ 525 #if 0 526 IEEE80211_HTCAP_CHWIDTH40 | /* 40 MHz channel width */ 527 IEEE80211_HTCAP_SHORTGI40; /* short GI in 40MHz */ 528 #endif 529 530 ic->ic_cryptocaps = 531 IEEE80211_CRYPTO_WEP | 532 IEEE80211_CRYPTO_TKIP | 533 IEEE80211_CRYPTO_AES_CCM; 534 535 ic->ic_txstream = sc->ntxchains; 536 ic->ic_rxstream = sc->nrxchains; 537 538 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 539 540 #ifdef should_delete_NNN 541 /* Set supported .11b and .11g channels (1 through 14). */ 542 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 543 for (i = 0; i < 14; i++) { 544 ic->ic_channels[i].ic_freq = 545 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 546 ic->ic_channels[i].ic_flags = 547 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 548 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 549 } 550 #else 551 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 552 ic->ic_channels); 553 #endif 554 /* XXX issues here ... Figure out proper attach and vap creation */ 555 ieee80211_ifattach(ic); 556 557 /* override default methods NNN Need more here? */ 558 ic->ic_newassoc = urtwn_newassoc; 559 ic->ic_wme.wme_update = urtwn_wme_update; 560 ic->ic_vap_create = urtwn_vap_create; 561 ic->ic_vap_delete = urtwn_vap_delete; 562 ic->ic_parent = urtwn_parent; 563 ic->ic_scan_start = urtwn_scan_start; 564 ic->ic_scan_end = urtwn_scan_end; 565 ic->ic_set_channel = urtwn_set_channel; 566 ic->ic_transmit = urtwn_transmit; 567 // ic->ic_send_mgmt = urtwn_send_mgmt; 568 ic->ic_raw_xmit = urtwn_raw_xmit; 569 ic->ic_getradiocaps = urtwn_getradiocaps; 570 571 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 572 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 573 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 574 575 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 576 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 577 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 578 579 ieee80211_announce(ic); 580 581 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 582 583 if (!pmf_device_register(self, NULL, NULL)) 584 aprint_error_dev(self, "couldn't establish power handler\n"); 585 586 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 587 588 /* Should be called via an IOCTL. Temp call here for now. */ 589 590 struct ieee80211vap *vap = 591 urtwn_vap_create(ic, device_xname(sc->sc_dev), 592 device_unit(sc->sc_dev), IEEE80211_M_STA, 593 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 594 595 if (vap == NULL) { 596 /* Didn't work ... now what! */ 597 printf ("NNN vap_create didn't work ...\n"); 598 ieee80211_ifdetach(ic); 599 goto fail; 600 } 601 602 return; 603 604 fail: 605 sc->sc_dying = 1; 606 aprint_error_dev(self, "attach failed\n"); 607 } 608 609 static int 610 urtwn_detach(device_t self, int flags) 611 { 612 struct urtwn_softc *sc = device_private(self); 613 struct ieee80211com *ic = &sc->sc_ic; 614 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 615 struct ifnet *ifp = vap->iv_ifp; 616 int s; 617 618 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 619 620 pmf_device_deregister(self); 621 622 s = splusb(); 623 624 sc->sc_dying = 1; 625 626 callout_halt(&sc->sc_scan_to, NULL); 627 callout_halt(&sc->sc_calib_to, NULL); 628 629 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 630 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 631 NULL); 632 urtwn_stop(ifp, 0); 633 // vap_detach(...) ?? 634 635 ieee80211_ifdetach(&sc->sc_ic); 636 637 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 638 urtwn_close_pipes(sc); 639 } 640 641 /* sendq destroy */ 642 IFQ_PURGE(&sc->sc_sendq); 643 IFQ_LOCK_DESTROY(&sc->sc_sendq); 644 645 splx(s); 646 647 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 648 649 callout_destroy(&sc->sc_scan_to); 650 callout_destroy(&sc->sc_calib_to); 651 652 mutex_destroy(&sc->sc_write_mtx); 653 mutex_destroy(&sc->sc_fwcmd_mtx); 654 mutex_destroy(&sc->sc_tx_mtx); 655 mutex_destroy(&sc->sc_rx_mtx); 656 mutex_destroy(&sc->sc_task_mtx); 657 658 return 0; 659 } 660 661 static int 662 urtwn_activate(device_t self, enum devact act) 663 { 664 struct urtwn_softc *sc = device_private(self); 665 666 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 667 668 switch (act) { 669 case DVACT_DEACTIVATE: 670 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 671 672 return 0; 673 default: 674 return EOPNOTSUPP; 675 } 676 } 677 678 static int 679 urtwn_open_pipes(struct urtwn_softc *sc) 680 { 681 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 682 static uint8_t epaddr[R92C_MAX_EPOUT]; 683 static uint8_t rxepaddr[R92C_MAX_EPIN]; 684 usb_interface_descriptor_t *id; 685 usb_endpoint_descriptor_t *ed; 686 size_t i, ntx = 0, nrx = 0; 687 int error; 688 689 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 690 691 /* Determine the number of bulk-out pipes. */ 692 id = usbd_get_interface_descriptor(sc->sc_iface); 693 for (i = 0; i < id->bNumEndpoints; i++) { 694 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 695 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 696 continue; 697 } 698 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 699 if (ntx < sizeof(epaddr)) 700 epaddr[ntx] = ed->bEndpointAddress; 701 ntx++; 702 } 703 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 704 if (nrx < sizeof(rxepaddr)) 705 rxepaddr[nrx] = ed->bEndpointAddress; 706 nrx++; 707 } 708 } 709 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 710 aprint_error_dev(sc->sc_dev, 711 "%zd: invalid number of Rx bulk pipes\n", nrx); 712 return EIO; 713 } 714 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 715 aprint_error_dev(sc->sc_dev, 716 "%zd: invalid number of Tx bulk pipes\n", ntx); 717 return EIO; 718 } 719 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 720 device_xname(sc->sc_dev), __func__, nrx, ntx)); 721 sc->rx_npipe = nrx; 722 sc->tx_npipe = ntx; 723 724 /* Open bulk-in pipe at address 0x81. */ 725 for (i = 0; i < nrx; i++) { 726 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 727 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 728 if (error != 0) { 729 aprint_error_dev(sc->sc_dev, 730 "could not open Rx bulk pipe 0x%02x: %d\n", 731 rxepaddr[i], error); 732 goto fail; 733 } 734 } 735 736 /* Open bulk-out pipes (up to 3). */ 737 for (i = 0; i < ntx; i++) { 738 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 739 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 740 if (error != 0) { 741 aprint_error_dev(sc->sc_dev, 742 "could not open Tx bulk pipe 0x%02x: %d\n", 743 epaddr[i], error); 744 goto fail; 745 } 746 } 747 748 /* Map 802.11 access categories to USB pipes. */ 749 sc->ac2idx[WME_AC_BK] = 750 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 751 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 752 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 753 754 fail: 755 if (error != 0) 756 urtwn_close_pipes(sc); 757 return error; 758 } 759 760 static void 761 urtwn_close_pipes(struct urtwn_softc *sc) 762 { 763 struct usbd_pipe *pipe; 764 size_t i; 765 766 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 767 768 /* Close Rx pipes. */ 769 CTASSERT(sizeof(pipe) == sizeof(void *)); 770 for (i = 0; i < sc->rx_npipe; i++) { 771 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 772 if (pipe != NULL) { 773 usbd_close_pipe(pipe); 774 } 775 } 776 777 /* Close Tx pipes. */ 778 for (i = 0; i < sc->tx_npipe; i++) { 779 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 780 if (pipe != NULL) { 781 usbd_close_pipe(pipe); 782 } 783 } 784 } 785 786 static int 787 urtwn_alloc_rx_list(struct urtwn_softc *sc) 788 { 789 struct urtwn_rx_data *data; 790 size_t i; 791 int error = 0; 792 793 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 794 795 for (size_t j = 0; j < sc->rx_npipe; j++) { 796 TAILQ_INIT(&sc->rx_free_list[j]); 797 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 798 data = &sc->rx_data[j][i]; 799 800 data->sc = sc; /* Backpointer for callbacks. */ 801 802 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 803 0, 0, &data->xfer); 804 if (error) { 805 aprint_error_dev(sc->sc_dev, 806 "could not allocate xfer\n"); 807 break; 808 } 809 810 data->buf = usbd_get_buffer(data->xfer); 811 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 812 } 813 } 814 if (error != 0) 815 urtwn_free_rx_list(sc); 816 return error; 817 } 818 819 static void 820 urtwn_free_rx_list(struct urtwn_softc *sc) 821 { 822 struct urtwn_rx_data *data = NULL; 823 struct usbd_xfer *xfer; 824 825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 826 827 /* NB: Caller must abort pipe first. */ 828 for (size_t j = 0; j < sc->rx_npipe; j++) { 829 mutex_enter(&sc->sc_rx_mtx); 830 while (!TAILQ_EMPTY(&sc->rx_free_list[j])) { 831 data = TAILQ_FIRST(&sc->rx_free_list[j]); 832 TAILQ_REMOVE(&sc->rx_free_list[j], data, next); 833 CTASSERT(sizeof(xfer) == sizeof(void *)); 834 xfer = atomic_swap_ptr(&data->xfer, NULL); 835 if (xfer != NULL) 836 usbd_destroy_xfer(xfer); 837 } 838 mutex_exit(&sc->sc_rx_mtx); 839 } 840 } 841 842 static int 843 urtwn_alloc_tx_list(struct urtwn_softc *sc) 844 { 845 struct urtwn_tx_data *data; 846 size_t i; 847 int error = 0; 848 849 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 850 851 mutex_enter(&sc->sc_tx_mtx); 852 for (size_t j = 0; j < sc->tx_npipe; j++) { 853 TAILQ_INIT(&sc->tx_free_list[j]); 854 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 855 data = &sc->tx_data[j][i]; 856 857 data->sc = sc; /* Backpointer for callbacks. */ 858 data->pidx = j; 859 860 error = usbd_create_xfer(sc->tx_pipe[j], 861 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 862 &data->xfer); 863 if (error) { 864 aprint_error_dev(sc->sc_dev, 865 "could not allocate xfer\n"); 866 goto fail; 867 } 868 869 data->buf = usbd_get_buffer(data->xfer); 870 871 /* Append this Tx buffer to our free list. */ 872 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 873 } 874 } 875 mutex_exit(&sc->sc_tx_mtx); 876 return 0; 877 878 fail: 879 urtwn_free_tx_list(sc); 880 mutex_exit(&sc->sc_tx_mtx); 881 return error; 882 } 883 884 static void 885 urtwn_free_tx_list(struct urtwn_softc *sc) 886 { 887 struct urtwn_tx_data *data = NULL; 888 struct usbd_xfer *xfer; 889 890 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 891 892 /* NB: Caller must abort pipe first. */ 893 for (size_t j = 0; j < sc->tx_npipe; j++) { 894 mutex_enter(&sc->sc_tx_mtx); 895 while (!TAILQ_EMPTY(&sc->tx_free_list[j])) { 896 data = TAILQ_FIRST(&sc->tx_free_list[j]); 897 TAILQ_REMOVE(&sc->tx_free_list[j], data, next); 898 CTASSERT(sizeof(xfer) == sizeof(void *)); 899 xfer = atomic_swap_ptr(&data->xfer, NULL); 900 if (xfer != NULL) 901 usbd_destroy_xfer(xfer); 902 } 903 mutex_exit(&sc->sc_tx_mtx); 904 } 905 } 906 907 static int 908 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 909 struct ieee80211_node *ni) 910 { 911 struct urtwn_tx_data *data = 912 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 913 return urtwn_tx(sc, m, ni, data); 914 } 915 916 static void 917 urtwn_task(void *arg) 918 { 919 struct urtwn_softc *sc = arg; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 922 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 923 struct urtwn_host_cmd *cmd; 924 int s; 925 926 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 927 if (vap->iv_state == IEEE80211_S_RUN && 928 (ic->ic_opmode == IEEE80211_M_HOSTAP || 929 ic->ic_opmode == IEEE80211_M_IBSS)) { 930 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 931 if (m == NULL) { 932 aprint_error_dev(sc->sc_dev, 933 "could not allocate beacon"); 934 } 935 936 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 937 m_freem(m); 938 aprint_error_dev(sc->sc_dev, "could not send beacon"); 939 } 940 941 /* beacon is no longer needed */ 942 m_freem(m); 943 } 944 945 /* Process host commands. */ 946 s = splusb(); 947 mutex_spin_enter(&sc->sc_task_mtx); 948 while (ring->next != ring->cur) { 949 cmd = &ring->cmd[ring->next]; 950 mutex_spin_exit(&sc->sc_task_mtx); 951 splx(s); 952 /* Invoke callback with kernel lock held. */ 953 cmd->cb(sc, cmd->data); 954 s = splusb(); 955 mutex_spin_enter(&sc->sc_task_mtx); 956 ring->queued--; 957 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 958 } 959 mutex_spin_exit(&sc->sc_task_mtx); 960 wakeup(&sc->cmdq); 961 splx(s); 962 } 963 964 static void 965 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 966 void *arg, int len) 967 { 968 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 969 struct urtwn_host_cmd *cmd; 970 int s; 971 972 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 973 device_xname(sc->sc_dev), __func__, cb, arg, len)); 974 975 s = splusb(); 976 mutex_spin_enter(&sc->sc_task_mtx); 977 cmd = &ring->cmd[ring->cur]; 978 cmd->cb = cb; 979 KASSERT(len <= sizeof(cmd->data)); 980 memcpy(cmd->data, arg, len); 981 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 982 983 /* If there is no pending command already, schedule a task. */ 984 if (!sc->sc_dying && ++ring->queued == 1) { 985 mutex_spin_exit(&sc->sc_task_mtx); 986 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 987 } else 988 mutex_spin_exit(&sc->sc_task_mtx); 989 splx(s); 990 } 991 992 static void 993 urtwn_wait_async(struct urtwn_softc *sc) 994 { 995 996 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 997 998 /* Wait for all queued asynchronous commands to complete. */ 999 while (sc->cmdq.queued > 0) 1000 tsleep(&sc->cmdq, 0, "endtask", 0); 1001 } 1002 1003 static int 1004 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1005 int len) 1006 { 1007 usb_device_request_t req; 1008 usbd_status error; 1009 1010 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1011 1012 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1013 req.bRequest = R92C_REQ_REGS; 1014 USETW(req.wValue, addr); 1015 USETW(req.wIndex, 0); 1016 USETW(req.wLength, len); 1017 error = usbd_do_request(sc->sc_udev, &req, buf); 1018 if (error != USBD_NORMAL_COMPLETION) { 1019 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1020 device_xname(sc->sc_dev), __func__, error, addr, len)); 1021 } 1022 return error; 1023 } 1024 1025 static void 1026 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1027 { 1028 1029 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1030 device_xname(sc->sc_dev), __func__, addr, val)); 1031 1032 urtwn_write_region_1(sc, addr, &val, 1); 1033 } 1034 1035 static void 1036 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1037 { 1038 uint8_t buf[2]; 1039 1040 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1041 device_xname(sc->sc_dev), __func__, addr, val)); 1042 1043 buf[0] = (uint8_t)val; 1044 buf[1] = (uint8_t)(val >> 8); 1045 urtwn_write_region_1(sc, addr, buf, 2); 1046 } 1047 1048 static void 1049 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1050 { 1051 uint8_t buf[4]; 1052 1053 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1054 device_xname(sc->sc_dev), __func__, addr, val)); 1055 1056 buf[0] = (uint8_t)val; 1057 buf[1] = (uint8_t)(val >> 8); 1058 buf[2] = (uint8_t)(val >> 16); 1059 buf[3] = (uint8_t)(val >> 24); 1060 urtwn_write_region_1(sc, addr, buf, 4); 1061 } 1062 1063 static int 1064 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1065 { 1066 1067 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, len=%#x\n", 1068 device_xname(sc->sc_dev), __func__, addr, len)); 1069 1070 return urtwn_write_region_1(sc, addr, buf, len); 1071 } 1072 1073 static int 1074 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1075 int len) 1076 { 1077 usb_device_request_t req; 1078 usbd_status error; 1079 1080 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1081 req.bRequest = R92C_REQ_REGS; 1082 USETW(req.wValue, addr); 1083 USETW(req.wIndex, 0); 1084 USETW(req.wLength, len); 1085 error = usbd_do_request(sc->sc_udev, &req, buf); 1086 if (error != USBD_NORMAL_COMPLETION) { 1087 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1088 device_xname(sc->sc_dev), __func__, error, addr, len)); 1089 } 1090 return error; 1091 } 1092 1093 static uint8_t 1094 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1095 { 1096 uint8_t val; 1097 1098 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1099 return 0xff; 1100 1101 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1102 device_xname(sc->sc_dev), __func__, addr, val)); 1103 return val; 1104 } 1105 1106 static uint16_t 1107 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1108 { 1109 uint8_t buf[2]; 1110 uint16_t val; 1111 1112 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1113 return 0xffff; 1114 1115 val = LE_READ_2(&buf[0]); 1116 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1117 device_xname(sc->sc_dev), __func__, addr, val)); 1118 return val; 1119 } 1120 1121 static uint32_t 1122 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1123 { 1124 uint8_t buf[4]; 1125 uint32_t val; 1126 1127 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1128 return 0xffffffff; 1129 1130 val = LE_READ_4(&buf[0]); 1131 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1132 device_xname(sc->sc_dev), __func__, addr, val)); 1133 return val; 1134 } 1135 1136 static int 1137 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1138 { 1139 struct r92c_fw_cmd cmd; 1140 uint8_t *cp; 1141 int fwcur; 1142 int ntries; 1143 1144 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1145 device_xname(sc->sc_dev), __func__, id, buf, len)); 1146 1147 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1148 1149 mutex_enter(&sc->sc_fwcmd_mtx); 1150 fwcur = sc->fwcur; 1151 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1152 mutex_exit(&sc->sc_fwcmd_mtx); 1153 1154 /* Wait for current FW box to be empty. */ 1155 for (ntries = 0; ntries < 100; ntries++) { 1156 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1157 break; 1158 DELAY(2000); 1159 } 1160 if (ntries == 100) { 1161 aprint_error_dev(sc->sc_dev, 1162 "could not send firmware command %d\n", id); 1163 return ETIMEDOUT; 1164 } 1165 1166 memset(&cmd, 0, sizeof(cmd)); 1167 KASSERT(len <= sizeof(cmd.msg)); 1168 memcpy(cmd.msg, buf, len); 1169 1170 /* Write the first word last since that will trigger the FW. */ 1171 cp = (uint8_t *)&cmd; 1172 cmd.id = id; 1173 if (len >= 4) { 1174 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1175 cmd.id |= R92C_CMD_FLAG_EXT; 1176 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1177 &cp[1], 2); 1178 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1179 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1180 (cp[5] << 24)); 1181 } else { 1182 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1183 &cp[4], 2); 1184 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1185 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1186 (cp[3] << 24)); 1187 } 1188 } else { 1189 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1190 } 1191 1192 return 0; 1193 } 1194 1195 static __inline void 1196 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1197 { 1198 1199 sc->sc_rf_write(sc, chain, addr, val); 1200 } 1201 1202 static void 1203 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1204 uint32_t val) 1205 { 1206 1207 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1208 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1209 } 1210 1211 static void 1212 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1213 uint32_t val) 1214 { 1215 1216 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1217 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1218 } 1219 1220 static void 1221 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1222 uint32_t val) 1223 { 1224 1225 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1226 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1227 } 1228 1229 static uint32_t 1230 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1231 { 1232 uint32_t reg[R92C_MAX_CHAINS], val; 1233 1234 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1235 if (chain != 0) { 1236 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1237 } 1238 1239 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1240 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1241 DELAY(1000); 1242 1243 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1244 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1245 R92C_HSSI_PARAM2_READ_EDGE); 1246 DELAY(1000); 1247 1248 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1249 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1250 DELAY(1000); 1251 1252 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1253 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1254 } else { 1255 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1256 } 1257 return MS(val, R92C_LSSI_READBACK_DATA); 1258 } 1259 1260 static int 1261 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1262 { 1263 int ntries; 1264 1265 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1266 1267 urtwn_write_4(sc, R92C_LLT_INIT, 1268 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1269 SM(R92C_LLT_INIT_ADDR, addr) | 1270 SM(R92C_LLT_INIT_DATA, data)); 1271 /* Wait for write operation to complete. */ 1272 for (ntries = 0; ntries < 20; ntries++) { 1273 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1274 R92C_LLT_INIT_OP_NO_ACTIVE) { 1275 /* Done */ 1276 return 0; 1277 } 1278 DELAY(5); 1279 } 1280 return ETIMEDOUT; 1281 } 1282 1283 static uint8_t 1284 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1285 { 1286 uint32_t reg; 1287 int ntries; 1288 1289 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1290 1291 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1292 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1293 reg &= ~R92C_EFUSE_CTRL_VALID; 1294 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1295 1296 /* Wait for read operation to complete. */ 1297 for (ntries = 0; ntries < 100; ntries++) { 1298 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1299 if (reg & R92C_EFUSE_CTRL_VALID) { 1300 /* Done */ 1301 return MS(reg, R92C_EFUSE_CTRL_DATA); 1302 } 1303 DELAY(5); 1304 } 1305 aprint_error_dev(sc->sc_dev, 1306 "could not read efuse byte at address 0x%04x\n", addr); 1307 return 0xff; 1308 } 1309 1310 static void 1311 urtwn_efuse_read(struct urtwn_softc *sc) 1312 { 1313 uint8_t *rom = (uint8_t *)&sc->rom; 1314 uint32_t reg; 1315 uint16_t addr = 0; 1316 uint8_t off, msk; 1317 size_t i; 1318 1319 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1320 1321 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1322 1323 urtwn_efuse_switch_power(sc); 1324 1325 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1326 while (addr < 512) { 1327 reg = urtwn_efuse_read_1(sc, addr); 1328 if (reg == 0xff) 1329 break; 1330 addr++; 1331 off = reg >> 4; 1332 msk = reg & 0xf; 1333 for (i = 0; i < 4; i++) { 1334 if (msk & (1U << i)) 1335 continue; 1336 1337 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1338 addr++; 1339 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1340 addr++; 1341 } 1342 } 1343 #ifdef URTWN_DEBUG 1344 if (urtwn_debug & DBG_INIT) { 1345 /* Dump ROM content. */ 1346 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1347 for (i = 0; i < (int)sizeof(sc->rom); i++) 1348 printf(":%02x", rom[i]); 1349 printf("\n"); 1350 } 1351 #endif 1352 } 1353 1354 static void 1355 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1356 { 1357 uint32_t reg; 1358 1359 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1360 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1361 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1362 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1363 } 1364 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1365 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1366 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1367 reg | R92C_SYS_FUNC_EN_ELDR); 1368 } 1369 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1370 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1371 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1372 urtwn_write_2(sc, R92C_SYS_CLKR, 1373 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1374 } 1375 } 1376 1377 static int 1378 urtwn_read_chipid(struct urtwn_softc *sc) 1379 { 1380 uint32_t reg; 1381 1382 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1383 1384 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1385 ISSET(sc->chip, URTWN_CHIP_92EU)) 1386 return 0; 1387 1388 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1389 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1390 /* test chip, not supported */ 1391 return EIO; 1392 } 1393 if (reg & R92C_SYS_CFG_TYPE_92C) { 1394 sc->chip |= URTWN_CHIP_92C; 1395 /* Check if it is a castrated 8192C. */ 1396 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1397 R92C_HPON_FSM_CHIP_BONDING_ID) == 1398 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1399 sc->chip |= URTWN_CHIP_92C_1T2R; 1400 } 1401 } 1402 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1403 sc->chip |= URTWN_CHIP_UMC; 1404 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1405 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1406 } 1407 } 1408 return 0; 1409 } 1410 1411 #ifdef URTWN_DEBUG 1412 static void 1413 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1414 { 1415 1416 aprint_normal_dev(sc->sc_dev, 1417 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1418 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1419 1420 aprint_normal_dev(sc->sc_dev, 1421 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1422 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1423 1424 aprint_normal_dev(sc->sc_dev, 1425 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1426 rp->macaddr[0], rp->macaddr[1], 1427 rp->macaddr[2], rp->macaddr[3], 1428 rp->macaddr[4], rp->macaddr[5]); 1429 1430 aprint_normal_dev(sc->sc_dev, 1431 "string %s, subcustomer_id %#x\n", 1432 rp->string, rp->subcustomer_id); 1433 1434 aprint_normal_dev(sc->sc_dev, 1435 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1436 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1437 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1438 1439 aprint_normal_dev(sc->sc_dev, 1440 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1441 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1442 rp->ht40_1s_tx_pwr[0][2], 1443 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1444 rp->ht40_1s_tx_pwr[1][2]); 1445 1446 aprint_normal_dev(sc->sc_dev, 1447 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1448 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1449 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1450 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1451 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1452 1453 aprint_normal_dev(sc->sc_dev, 1454 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1455 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1456 rp->ht20_tx_pwr_diff[2] & 0xf, 1457 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1458 rp->ht20_tx_pwr_diff[2] >> 4); 1459 1460 aprint_normal_dev(sc->sc_dev, 1461 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1462 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1463 rp->ofdm_tx_pwr_diff[2] & 0xf, 1464 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1465 rp->ofdm_tx_pwr_diff[2] >> 4); 1466 1467 aprint_normal_dev(sc->sc_dev, 1468 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1469 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1470 rp->ht40_max_pwr[2] & 0xf, 1471 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1472 rp->ht40_max_pwr[2] >> 4); 1473 1474 aprint_normal_dev(sc->sc_dev, 1475 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1476 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1477 rp->ht20_max_pwr[2] & 0xf, 1478 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1479 rp->ht20_max_pwr[2] >> 4); 1480 1481 aprint_normal_dev(sc->sc_dev, 1482 "xtal_calib %d, tssi %d %d, thermal %d\n", 1483 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1484 1485 aprint_normal_dev(sc->sc_dev, 1486 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1487 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1488 1489 aprint_normal_dev(sc->sc_dev, 1490 "channnel_plan %d, version %d customer_id %#x\n", 1491 rp->channel_plan, rp->version, rp->curstomer_id); 1492 } 1493 #endif 1494 1495 static void 1496 urtwn_read_rom(struct urtwn_softc *sc) 1497 { 1498 struct ieee80211com *ic = &sc->sc_ic; 1499 struct r92c_rom *rom = &sc->rom; 1500 1501 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1502 1503 mutex_enter(&sc->sc_write_mtx); 1504 1505 /* Read full ROM image. */ 1506 urtwn_efuse_read(sc); 1507 #ifdef URTWN_DEBUG 1508 if (urtwn_debug & DBG_REG) 1509 urtwn_dump_rom(sc, rom); 1510 #endif 1511 1512 /* XXX Weird but this is what the vendor driver does. */ 1513 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1514 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1515 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1516 1517 DPRINTFN(DBG_INIT, 1518 ("%s: %s: PA setting=%#x, board=%#x, regulatory=%d\n", 1519 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1520 sc->board_type, sc->regulatory)); 1521 1522 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1523 1524 sc->sc_rf_write = urtwn_r92c_rf_write; 1525 sc->sc_power_on = urtwn_r92c_power_on; 1526 sc->sc_dma_init = urtwn_r92c_dma_init; 1527 1528 mutex_exit(&sc->sc_write_mtx); 1529 } 1530 1531 static void 1532 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1533 { 1534 struct ieee80211com *ic = &sc->sc_ic; 1535 uint8_t *rom = sc->r88e_rom; 1536 uint32_t reg; 1537 uint16_t addr = 0; 1538 uint8_t off, msk, tmp; 1539 int i; 1540 1541 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1542 1543 mutex_enter(&sc->sc_write_mtx); 1544 1545 off = 0; 1546 urtwn_efuse_switch_power(sc); 1547 1548 /* Read full ROM image. */ 1549 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1550 while (addr < 4096) { 1551 reg = urtwn_efuse_read_1(sc, addr); 1552 if (reg == 0xff) 1553 break; 1554 addr++; 1555 if ((reg & 0x1f) == 0x0f) { 1556 tmp = (reg & 0xe0) >> 5; 1557 reg = urtwn_efuse_read_1(sc, addr); 1558 if ((reg & 0x0f) != 0x0f) 1559 off = ((reg & 0xf0) >> 1) | tmp; 1560 addr++; 1561 } else 1562 off = reg >> 4; 1563 msk = reg & 0xf; 1564 for (i = 0; i < 4; i++) { 1565 if (msk & (1 << i)) 1566 continue; 1567 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1568 addr++; 1569 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1570 addr++; 1571 } 1572 } 1573 #ifdef URTWN_DEBUG 1574 if (urtwn_debug & DBG_REG) { 1575 } 1576 #endif 1577 1578 addr = 0x10; 1579 for (i = 0; i < 6; i++) 1580 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1581 for (i = 0; i < 5; i++) 1582 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1583 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1584 if (sc->bw20_tx_pwr_diff & 0x08) 1585 sc->bw20_tx_pwr_diff |= 0xf0; 1586 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1587 if (sc->ofdm_tx_pwr_diff & 0x08) 1588 sc->ofdm_tx_pwr_diff |= 0xf0; 1589 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1590 1591 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1592 1593 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1594 sc->sc_power_on = urtwn_r92e_power_on; 1595 sc->sc_rf_write = urtwn_r92e_rf_write; 1596 } else { 1597 sc->sc_power_on = urtwn_r88e_power_on; 1598 sc->sc_rf_write = urtwn_r88e_rf_write; 1599 } 1600 sc->sc_dma_init = urtwn_r88e_dma_init; 1601 1602 mutex_exit(&sc->sc_write_mtx); 1603 } 1604 1605 /* NNN Do we need to do something with this? */ 1606 1607 static __unused int 1608 urtwn_media_change(struct ifnet *ifp) 1609 { 1610 #ifdef URTWN_DEBUG 1611 struct ieee80211vap *vap = ifp->if_softc; 1612 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1613 #endif 1614 int error; 1615 1616 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1617 1618 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1619 return error; 1620 1621 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1622 (IFF_UP | IFF_RUNNING)) { 1623 urtwn_init(ifp); 1624 } 1625 return 0; 1626 } 1627 1628 /* 1629 * Initialize rate adaptation in firmware. 1630 */ 1631 static int 1632 urtwn_ra_init(struct ieee80211vap *vap) 1633 { 1634 static const uint8_t map[] = { 1635 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1636 }; 1637 struct ieee80211com *ic = vap->iv_ic; 1638 struct urtwn_softc *sc = ic->ic_softc; 1639 struct ieee80211_node *ni = vap->iv_bss; 1640 struct ieee80211_rateset *rs = &ni->ni_rates; 1641 1642 struct r92c_fw_cmd_macid_cfg cmd; 1643 uint32_t rates, basicrates; 1644 uint32_t rrsr_mask, rrsr_rate; 1645 uint8_t mode; 1646 size_t maxrate, maxbasicrate, i, j; 1647 int error; 1648 1649 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1650 1651 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1652 1653 /* Get normal and basic rates mask. */ 1654 rates = basicrates = 1; 1655 maxrate = maxbasicrate = 0; 1656 for (i = 0; i < rs->rs_nrates; i++) { 1657 /* Convert 802.11 rate to HW rate index. */ 1658 for (j = 0; j < __arraycount(map); j++) { 1659 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1660 break; 1661 } 1662 } 1663 if (j == __arraycount(map)) { 1664 /* Unknown rate, skip. */ 1665 continue; 1666 } 1667 1668 rates |= 1U << j; 1669 if (j > maxrate) { 1670 maxrate = j; 1671 } 1672 1673 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1674 basicrates |= 1U << j; 1675 if (j > maxbasicrate) { 1676 maxbasicrate = j; 1677 } 1678 } 1679 } 1680 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1681 mode = R92C_RAID_11B; 1682 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 1683 mode = R92C_RAID_11BG; 1684 } else /* mode = IEEE80211_MODE_11NG */ 1685 mode = R92C_RAID_11GN; 1686 DPRINTFN(DBG_INIT, ("%s: %s: mode=%#x rates=%#x, basicrates=%#x, " 1687 "maxrate=%zx, maxbasicrate=%zx\n", 1688 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1689 maxrate, maxbasicrate)); 1690 1691 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1692 maxbasicrate |= R92C_RATE_SHORTGI; 1693 maxrate |= R92C_RATE_SHORTGI; 1694 } 1695 1696 /* Set rates mask for group addressed frames. */ 1697 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1698 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1699 cmd.macid |= RTWN_MACID_SHORTGI; 1700 cmd.mask = htole32((mode << 28) | basicrates); 1701 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1702 if (error != 0) { 1703 aprint_error_dev(sc->sc_dev, 1704 "could not add broadcast station\n"); 1705 return error; 1706 } 1707 /* Set initial MRR rate. */ 1708 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1709 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1710 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1711 1712 /* Set rates mask for unicast frames. */ 1713 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1714 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1715 cmd.macid |= RTWN_MACID_SHORTGI; 1716 cmd.mask = htole32((mode << 28) | rates); 1717 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1718 if (error != 0) { 1719 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1720 return error; 1721 } 1722 /* Set initial MRR rate. */ 1723 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1724 __func__, maxrate)); 1725 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1726 1727 #if notyet 1728 /* NNN appears to have no fixed rate anywhere. */ 1729 rrsr_rate = ic->ic_fixed_rate; 1730 if (rrsr_rate == -1) 1731 #endif 1732 rrsr_rate = 11; 1733 1734 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1735 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1736 1737 #if notyet 1738 /* Indicate highest supported rate. */ 1739 ni->ni_txrate = rs->rs_nrates - 1; 1740 #endif 1741 return 0; 1742 } 1743 1744 static int 1745 urtwn_get_nettype(struct urtwn_softc *sc) 1746 { 1747 struct ieee80211com *ic = &sc->sc_ic; 1748 int type; 1749 1750 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1751 1752 switch (ic->ic_opmode) { 1753 case IEEE80211_M_STA: 1754 type = R92C_CR_NETTYPE_INFRA; 1755 break; 1756 1757 case IEEE80211_M_IBSS: 1758 type = R92C_CR_NETTYPE_ADHOC; 1759 break; 1760 1761 default: 1762 type = R92C_CR_NETTYPE_NOLINK; 1763 break; 1764 } 1765 1766 return type; 1767 } 1768 1769 static void 1770 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1771 { 1772 uint8_t reg; 1773 1774 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1775 __func__, type)); 1776 1777 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1778 1779 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1780 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1781 } 1782 1783 static void 1784 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1785 { 1786 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1787 struct ieee80211_node *ni = vap->iv_bss; 1788 uint64_t tsf; 1789 1790 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1791 1792 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1793 1794 /* Enable TSF synchronization. */ 1795 urtwn_write_1(sc, R92C_BCN_CTRL, 1796 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1797 1798 /* Correct TSF */ 1799 urtwn_write_1(sc, R92C_BCN_CTRL, 1800 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1801 1802 /* Set initial TSF. */ 1803 tsf = ni->ni_tstamp.tsf; 1804 tsf = le64toh(tsf); 1805 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1806 tsf -= IEEE80211_DUR_TU; 1807 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1808 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1809 1810 urtwn_write_1(sc, R92C_BCN_CTRL, 1811 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1812 } 1813 1814 static void 1815 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1816 { 1817 uint8_t reg; 1818 1819 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1820 __func__, led, on)); 1821 1822 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1823 1824 if (led == URTWN_LED_LINK) { 1825 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1826 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1827 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1828 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1829 (R92C_LEDCFG0_DIS << 1)); 1830 if (on) { 1831 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1832 R92E_LEDSON; 1833 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1834 } 1835 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1836 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1837 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1838 if (!on) { 1839 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1840 urtwn_write_1(sc, R92C_LEDCFG2, 1841 reg | R92C_LEDCFG0_DIS); 1842 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1843 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1844 reg & 0xfe); 1845 } 1846 } else { 1847 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1848 if (!on) { 1849 reg |= R92C_LEDCFG0_DIS; 1850 } 1851 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1852 } 1853 sc->ledlink = on; /* Save LED state. */ 1854 } 1855 } 1856 1857 static void 1858 urtwn_calib_to(void *arg) 1859 { 1860 struct urtwn_softc *sc = arg; 1861 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1862 1863 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1864 1865 if (sc->sc_dying) 1866 return; 1867 1868 /* Do it in a process context. */ 1869 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1870 } 1871 1872 /* ARGSUSED */ 1873 static void 1874 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1875 { 1876 struct ieee80211vap *vap = arg; 1877 struct r92c_fw_cmd_rssi cmd; 1878 struct r92e_fw_cmd_rssi cmde; 1879 1880 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1881 1882 if (vap->iv_state != IEEE80211_S_RUN) 1883 goto restart_timer; 1884 1885 mutex_enter(&sc->sc_write_mtx); 1886 if (sc->avg_pwdb != -1) { 1887 /* Indicate Rx signal strength to FW for rate adaptation. */ 1888 memset(&cmd, 0, sizeof(cmd)); 1889 memset(&cmde, 0, sizeof(cmde)); 1890 cmd.macid = 0; /* BSS. */ 1891 cmde.macid = 0; /* BSS. */ 1892 cmd.pwdb = sc->avg_pwdb; 1893 cmde.pwdb = sc->avg_pwdb; 1894 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1895 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1896 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1897 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1898 sizeof(cmd)); 1899 } else { 1900 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1901 sizeof(cmde)); 1902 } 1903 } 1904 1905 /* Do temperature compensation. */ 1906 urtwn_temp_calib(sc); 1907 mutex_exit(&sc->sc_write_mtx); 1908 1909 restart_timer: 1910 if (!sc->sc_dying) { 1911 /* Restart calibration timer. */ 1912 callout_schedule(&sc->sc_calib_to, hz); 1913 } 1914 } 1915 1916 static void 1917 urtwn_next_scan(void *arg) 1918 { 1919 printf ("NNN urtwn_next_scan called....\n"); 1920 #ifdef notyet 1921 struct urtwn_softc *sc = arg; 1922 int s; 1923 1924 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1925 1926 if (sc->sc_dying) 1927 return; 1928 1929 s = splnet(); 1930 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1931 ieee80211_next_scan(&sc->sc_ic); 1932 splx(s); 1933 #endif 1934 } 1935 1936 static void 1937 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1938 { 1939 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1940 ether_sprintf(ni->ni_macaddr))); 1941 1942 /* start with lowest Tx rate */ 1943 ni->ni_txrate = 0; 1944 } 1945 1946 #if OLDSTUFF 1947 static int 1948 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1949 { 1950 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1951 struct urtwn_cmd_newstate cmd; 1952 1953 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1954 device_xname(sc->sc_dev), __func__, 1955 ieee80211_state_name[nstate], nstate, arg)); 1956 1957 callout_stop(&sc->sc_scan_to); 1958 callout_stop(&sc->sc_calib_to); 1959 1960 /* Do it in a process context. */ 1961 cmd.state = nstate; 1962 cmd.arg = arg; 1963 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1964 return 0; 1965 } 1966 1967 static void 1968 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1969 { 1970 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1971 struct urtwn_cmd_newstate *cmd = arg; 1972 struct ieee80211com *ic = &sc->sc_ic; 1973 struct ieee80211_node *ni; 1974 enum ieee80211_state ostate = vap->iv_state; 1975 enum ieee80211_state nstate = cmd->state; 1976 uint32_t reg; 1977 uint8_t sifs_time, msr; 1978 int s; 1979 1980 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1981 device_xname(sc->sc_dev), __func__, 1982 ieee80211_state_name[ostate], ostate, 1983 ieee80211_state_name[nstate], nstate)); 1984 1985 s = splnet(); 1986 mutex_enter(&sc->sc_write_mtx); 1987 1988 callout_stop(&sc->sc_scan_to); 1989 callout_stop(&sc->sc_calib_to); 1990 1991 switch (ostate) { 1992 case IEEE80211_S_INIT: 1993 break; 1994 1995 case IEEE80211_S_SCAN: 1996 if (nstate != IEEE80211_S_SCAN) { 1997 /* 1998 * End of scanning 1999 */ 2000 /* flush 4-AC Queue after site_survey */ 2001 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2002 2003 /* Allow Rx from our BSSID only. */ 2004 urtwn_write_4(sc, R92C_RCR, 2005 urtwn_read_4(sc, R92C_RCR) | 2006 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2007 } 2008 break; 2009 2010 case IEEE80211_S_AUTH: 2011 case IEEE80211_S_ASSOC: 2012 break; 2013 2014 case IEEE80211_S_RUN: 2015 /* Turn link LED off. */ 2016 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2017 2018 /* Set media status to 'No Link'. */ 2019 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2020 2021 /* Stop Rx of data frames. */ 2022 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2023 2024 /* Reset TSF. */ 2025 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2026 2027 /* Disable TSF synchronization. */ 2028 urtwn_write_1(sc, R92C_BCN_CTRL, 2029 urtwn_read_1(sc, R92C_BCN_CTRL) | 2030 R92C_BCN_CTRL_DIS_TSF_UDT0); 2031 2032 /* Back to 20MHz mode */ 2033 urtwn_set_chan(sc, ic->ic_curchan, 2034 IEEE80211_HTINFO_2NDCHAN_NONE); 2035 2036 if (ic->ic_opmode == IEEE80211_M_IBSS || 2037 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2038 /* Stop BCN */ 2039 urtwn_write_1(sc, R92C_BCN_CTRL, 2040 urtwn_read_1(sc, R92C_BCN_CTRL) & 2041 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2042 } 2043 2044 /* Reset EDCA parameters. */ 2045 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2046 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2047 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2048 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2049 2050 /* flush all cam entries */ 2051 urtwn_cam_init(sc); 2052 break; 2053 case IEEE80211_S_CAC: 2054 case IEEE80211_S_CSA: 2055 case IEEE80211_S_SLEEP: 2056 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2057 /* NNN what do we do in these states? XXX */ 2058 break; 2059 } 2060 2061 switch (nstate) { 2062 case IEEE80211_S_INIT: 2063 /* Turn link LED off. */ 2064 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2065 break; 2066 2067 case IEEE80211_S_SCAN: 2068 if (ostate != IEEE80211_S_SCAN) { 2069 /* 2070 * Begin of scanning 2071 */ 2072 2073 /* Set gain for scanning. */ 2074 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2075 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2076 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2077 2078 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2079 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2080 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2081 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2082 } 2083 2084 /* Set media status to 'No Link'. */ 2085 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2086 2087 /* Allow Rx from any BSSID. */ 2088 urtwn_write_4(sc, R92C_RCR, 2089 urtwn_read_4(sc, R92C_RCR) & 2090 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2091 2092 /* Stop Rx of data frames. */ 2093 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2094 2095 /* Disable update TSF */ 2096 urtwn_write_1(sc, R92C_BCN_CTRL, 2097 urtwn_read_1(sc, R92C_BCN_CTRL) | 2098 R92C_BCN_CTRL_DIS_TSF_UDT0); 2099 } 2100 2101 /* Make link LED blink during scan. */ 2102 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2103 2104 /* Pause AC Tx queues. */ 2105 urtwn_write_1(sc, R92C_TXPAUSE, 2106 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2107 2108 urtwn_set_chan(sc, ic->ic_curchan, 2109 IEEE80211_HTINFO_2NDCHAN_NONE); 2110 2111 /* Start periodic scan. */ 2112 if (!sc->sc_dying) 2113 callout_schedule(&sc->sc_scan_to, hz / 5); 2114 break; 2115 2116 case IEEE80211_S_AUTH: 2117 /* Set initial gain under link. */ 2118 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2119 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2120 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2121 2122 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2123 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2124 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2125 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2126 } 2127 2128 /* Set media status to 'No Link'. */ 2129 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2130 2131 /* Allow Rx from any BSSID. */ 2132 urtwn_write_4(sc, R92C_RCR, 2133 urtwn_read_4(sc, R92C_RCR) & 2134 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2135 2136 urtwn_set_chan(sc, ic->ic_curchan, 2137 IEEE80211_HTINFO_2NDCHAN_NONE); 2138 break; 2139 2140 case IEEE80211_S_ASSOC: 2141 break; 2142 2143 case IEEE80211_S_RUN: 2144 ni = vap->iv_bss; 2145 2146 /* XXX: Set 20MHz mode */ 2147 urtwn_set_chan(sc, ic->ic_curchan, 2148 IEEE80211_HTINFO_2NDCHAN_NONE); 2149 2150 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2151 /* Back to 20MHz mode */ 2152 urtwn_set_chan(sc, ic->ic_curchan, 2153 IEEE80211_HTINFO_2NDCHAN_NONE); 2154 2155 /* Set media status to 'No Link'. */ 2156 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2157 2158 /* Enable Rx of data frames. */ 2159 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2160 2161 /* Allow Rx from any BSSID. */ 2162 urtwn_write_4(sc, R92C_RCR, 2163 urtwn_read_4(sc, R92C_RCR) & 2164 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2165 2166 /* Accept Rx data/control/management frames */ 2167 urtwn_write_4(sc, R92C_RCR, 2168 urtwn_read_4(sc, R92C_RCR) | 2169 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2170 2171 /* Turn link LED on. */ 2172 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2173 break; 2174 } 2175 2176 /* Set media status to 'Associated'. */ 2177 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2178 2179 /* Set BSSID. */ 2180 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2181 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2182 2183 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2184 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2185 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2186 /* 802.11b/g */ 2187 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2188 } else /* IEEE_MODE_11NG */ 2189 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 11); 2190 2191 /* Enable Rx of data frames. */ 2192 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2193 2194 /* Set beacon interval. */ 2195 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2196 2197 msr = urtwn_read_1(sc, R92C_MSR); 2198 msr &= R92C_MSR_MASK; 2199 switch (ic->ic_opmode) { 2200 case IEEE80211_M_STA: 2201 /* Allow Rx from our BSSID only. */ 2202 urtwn_write_4(sc, R92C_RCR, 2203 urtwn_read_4(sc, R92C_RCR) | 2204 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2205 2206 /* Enable TSF synchronization. */ 2207 urtwn_tsf_sync_enable(sc); 2208 2209 msr |= R92C_MSR_INFRA; 2210 break; 2211 case IEEE80211_M_HOSTAP: 2212 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2213 2214 /* Allow Rx from any BSSID. */ 2215 urtwn_write_4(sc, R92C_RCR, 2216 urtwn_read_4(sc, R92C_RCR) & 2217 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2218 2219 /* Reset TSF timer to zero. */ 2220 reg = urtwn_read_4(sc, R92C_TCR); 2221 reg &= ~0x01; 2222 urtwn_write_4(sc, R92C_TCR, reg); 2223 reg |= 0x01; 2224 urtwn_write_4(sc, R92C_TCR, reg); 2225 2226 msr |= R92C_MSR_AP; 2227 break; 2228 default: 2229 msr |= R92C_MSR_ADHOC; 2230 break; 2231 } 2232 urtwn_write_1(sc, R92C_MSR, msr); 2233 2234 sifs_time = 10; 2235 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2236 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2237 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2238 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2239 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2240 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2241 2242 /* Initialize rate adaptation. */ 2243 if (1 || ISSET(sc->chip, URTWN_CHIP_88E) || 2244 ISSET(sc->chip, URTWN_CHIP_92EU)) 2245 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2246 else 2247 urtwn_ra_init(vap); 2248 2249 /* Turn link LED on. */ 2250 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2251 2252 /* Reset average RSSI. */ 2253 sc->avg_pwdb = -1; 2254 2255 /* Reset temperature calibration state machine. */ 2256 sc->thcal_state = 0; 2257 sc->thcal_lctemp = 0; 2258 2259 /* Start periodic calibration. */ 2260 if (!sc->sc_dying) 2261 callout_schedule(&sc->sc_calib_to, hz); 2262 break; 2263 case IEEE80211_S_CAC: 2264 case IEEE80211_S_CSA: 2265 case IEEE80211_S_SLEEP: 2266 /* NNN what do we do in these states? XXX */ 2267 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2268 break; 2269 } 2270 /* newstate functions expect the ic to be locked. */ 2271 IEEE80211_LOCK(ic); 2272 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2273 IEEE80211_UNLOCK(ic); 2274 2275 mutex_exit(&sc->sc_write_mtx); 2276 splx(s); 2277 } 2278 #endif 2279 2280 static int 2281 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2282 { 2283 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2284 struct ieee80211com *ic = &sc->sc_ic; 2285 struct ieee80211_node *ni; 2286 enum ieee80211_state ostate = vap->iv_state; 2287 uint32_t reg; 2288 uint8_t sifs_time, msr; 2289 int s; 2290 int error; 2291 2292 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2293 device_xname(sc->sc_dev), __func__, 2294 ieee80211_state_name[ostate], ostate, 2295 ieee80211_state_name[nstate], nstate)); 2296 2297 s = splnet(); 2298 mutex_enter(&sc->sc_write_mtx); 2299 2300 callout_stop(&sc->sc_scan_to); 2301 callout_stop(&sc->sc_calib_to); 2302 2303 switch (ostate) { 2304 case IEEE80211_S_INIT: 2305 break; 2306 2307 case IEEE80211_S_SCAN: 2308 if (nstate != IEEE80211_S_SCAN) { 2309 /* 2310 * End of scanning 2311 */ 2312 /* flush 4-AC Queue after site_survey */ 2313 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2314 2315 /* Allow Rx from our BSSID only. */ 2316 urtwn_write_4(sc, R92C_RCR, 2317 urtwn_read_4(sc, R92C_RCR) | 2318 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2319 } 2320 break; 2321 2322 case IEEE80211_S_AUTH: 2323 case IEEE80211_S_ASSOC: 2324 break; 2325 2326 case IEEE80211_S_RUN: 2327 if (nstate == IEEE80211_S_RUN) 2328 break; 2329 /* Turn link LED off. */ 2330 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2331 2332 /* Set media status to 'No Link'. */ 2333 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2334 2335 /* Stop Rx of data frames. */ 2336 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2337 2338 /* Reset TSF. */ 2339 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2340 2341 /* Disable TSF synchronization. */ 2342 urtwn_write_1(sc, R92C_BCN_CTRL, 2343 urtwn_read_1(sc, R92C_BCN_CTRL) | 2344 R92C_BCN_CTRL_DIS_TSF_UDT0); 2345 2346 #if 0 2347 /* Back to 20MHz mode */ 2348 urtwn_set_chan(sc, ic->ic_curchan, 2349 IEEE80211_HTINFO_2NDCHAN_NONE); 2350 #endif 2351 2352 if (ic->ic_opmode == IEEE80211_M_IBSS || 2353 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2354 /* Stop BCN */ 2355 urtwn_write_1(sc, R92C_BCN_CTRL, 2356 urtwn_read_1(sc, R92C_BCN_CTRL) & 2357 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2358 } 2359 2360 /* Reset EDCA parameters. */ 2361 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2362 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2363 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2364 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2365 2366 /* flush all cam entries */ 2367 urtwn_cam_init(sc); 2368 break; 2369 case IEEE80211_S_CAC: 2370 case IEEE80211_S_CSA: 2371 case IEEE80211_S_SLEEP: 2372 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2373 /* NNN what do we do in these states? XXX */ 2374 break; 2375 } 2376 2377 switch (nstate) { 2378 case IEEE80211_S_INIT: 2379 /* Turn link LED off. */ 2380 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2381 break; 2382 2383 case IEEE80211_S_SCAN: 2384 if (ostate == IEEE80211_S_SCAN) 2385 break; 2386 if (ostate != IEEE80211_S_SCAN) { 2387 /* 2388 * Begin of scanning 2389 */ 2390 2391 /* Set gain for scanning. */ 2392 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2393 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2394 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2395 2396 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2397 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2398 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2399 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2400 } 2401 2402 /* Set media status to 'No Link'. */ 2403 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2404 2405 /* Allow Rx from any BSSID. */ 2406 urtwn_write_4(sc, R92C_RCR, 2407 urtwn_read_4(sc, R92C_RCR) & 2408 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2409 2410 /* Stop Rx of data frames. */ 2411 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2412 2413 /* Disable update TSF */ 2414 urtwn_write_1(sc, R92C_BCN_CTRL, 2415 urtwn_read_1(sc, R92C_BCN_CTRL) | 2416 R92C_BCN_CTRL_DIS_TSF_UDT0); 2417 } 2418 2419 /* Make link LED blink during scan. */ 2420 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2421 2422 /* Pause AC Tx queues. */ 2423 urtwn_write_1(sc, R92C_TXPAUSE, 2424 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2425 2426 #if 0 2427 urtwn_set_chan(sc, ic->ic_curchan, 2428 IEEE80211_HTINFO_2NDCHAN_NONE); 2429 #endif 2430 2431 /* Start periodic scan. */ 2432 if (!sc->sc_dying) 2433 callout_schedule(&sc->sc_scan_to, hz / 5); 2434 break; 2435 2436 case IEEE80211_S_AUTH: 2437 if (ostate == IEEE80211_S_AUTH) 2438 break; 2439 /* Set initial gain under link. */ 2440 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2441 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2442 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2443 2444 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2445 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2446 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2447 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2448 } 2449 2450 /* Set media status to 'No Link'. */ 2451 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2452 2453 /* Allow Rx from any BSSID. */ 2454 urtwn_write_4(sc, R92C_RCR, 2455 urtwn_read_4(sc, R92C_RCR) & 2456 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2457 2458 #if 0 2459 urtwn_set_chan(sc, ic->ic_curchan, 2460 IEEE80211_HTINFO_2NDCHAN_NONE); 2461 #endif 2462 break; 2463 2464 case IEEE80211_S_ASSOC: 2465 break; 2466 2467 case IEEE80211_S_RUN: 2468 if (ostate == IEEE80211_S_RUN) 2469 break; 2470 ni = vap->iv_bss; 2471 2472 #if 0 2473 /* XXX: Set 20MHz mode */ 2474 urtwn_set_chan(sc, ic->ic_curchan, 2475 IEEE80211_HTINFO_2NDCHAN_NONE); 2476 #endif 2477 2478 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2479 #if 0 2480 /* Back to 20MHz mode */ 2481 urtwn_set_chan(sc, ic->ic_curchan, 2482 IEEE80211_HTINFO_2NDCHAN_NONE); 2483 #endif 2484 2485 /* Set media status to 'No Link'. */ 2486 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2487 2488 /* Enable Rx of data frames. */ 2489 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2490 2491 /* Allow Rx from any BSSID. */ 2492 urtwn_write_4(sc, R92C_RCR, 2493 urtwn_read_4(sc, R92C_RCR) & 2494 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2495 2496 /* Accept Rx data/control/management frames */ 2497 urtwn_write_4(sc, R92C_RCR, 2498 urtwn_read_4(sc, R92C_RCR) | 2499 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2500 2501 /* Turn link LED on. */ 2502 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2503 break; 2504 } 2505 2506 /* Set media status to 'Associated'. */ 2507 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2508 2509 /* Set BSSID. */ 2510 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2511 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2512 2513 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2514 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2515 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 2516 /* 802.11b/g */ 2517 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2518 } else /* IEEE_MODE_11NG */ 2519 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 12); /* MCS 0 */ 2520 2521 /* Enable Rx of data frames. */ 2522 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2523 2524 /* Set beacon interval. */ 2525 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2526 2527 msr = urtwn_read_1(sc, R92C_MSR); 2528 msr &= R92C_MSR_MASK; 2529 switch (ic->ic_opmode) { 2530 case IEEE80211_M_STA: 2531 /* Allow Rx from our BSSID only. */ 2532 urtwn_write_4(sc, R92C_RCR, 2533 urtwn_read_4(sc, R92C_RCR) | 2534 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2535 2536 /* Enable TSF synchronization. */ 2537 urtwn_tsf_sync_enable(sc); 2538 2539 msr |= R92C_MSR_INFRA; 2540 break; 2541 case IEEE80211_M_HOSTAP: 2542 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2543 2544 /* Allow Rx from any BSSID. */ 2545 urtwn_write_4(sc, R92C_RCR, 2546 urtwn_read_4(sc, R92C_RCR) & 2547 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2548 2549 /* Reset TSF timer to zero. */ 2550 reg = urtwn_read_4(sc, R92C_TCR); 2551 reg &= ~0x01; 2552 urtwn_write_4(sc, R92C_TCR, reg); 2553 reg |= 0x01; 2554 urtwn_write_4(sc, R92C_TCR, reg); 2555 2556 msr |= R92C_MSR_AP; 2557 break; 2558 default: 2559 msr |= R92C_MSR_ADHOC; 2560 break; 2561 } 2562 urtwn_write_1(sc, R92C_MSR, msr); 2563 2564 sifs_time = 10; 2565 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2566 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2567 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2568 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2569 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2570 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2571 2572 /* Initialize rate adaptation. */ 2573 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2574 ISSET(sc->chip, URTWN_CHIP_92EU)) 2575 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2576 else 2577 urtwn_ra_init(vap); 2578 2579 /* Turn link LED on. */ 2580 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2581 2582 /* Reset average RSSI. */ 2583 sc->avg_pwdb = -1; 2584 2585 /* Reset temperature calibration state machine. */ 2586 sc->thcal_state = 0; 2587 sc->thcal_lctemp = 0; 2588 2589 /* Start periodic calibration. */ 2590 if (!sc->sc_dying) 2591 callout_schedule(&sc->sc_calib_to, hz); 2592 break; 2593 case IEEE80211_S_CAC: 2594 case IEEE80211_S_CSA: 2595 case IEEE80211_S_SLEEP: 2596 /* NNN what do we do in these states? XXX */ 2597 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2598 break; 2599 } 2600 mutex_exit(&sc->sc_write_mtx); 2601 2602 /* newstate functions expect the ic to be locked. */ 2603 error = (*sc->sc_newstate)(vap, nstate, arg); 2604 2605 splx(s); 2606 return error; 2607 } 2608 2609 static int 2610 urtwn_wme_update(struct ieee80211com *ic) 2611 { 2612 struct urtwn_softc *sc = ic->ic_softc; 2613 2614 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2615 2616 /* don't override default WME values if WME is not actually enabled */ 2617 if (!(ic->ic_flags & IEEE80211_F_WME)) 2618 return 0; 2619 2620 /* Do it in a process context. */ 2621 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2622 return 0; 2623 } 2624 2625 static void 2626 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2627 { 2628 static const uint16_t ac2reg[WME_NUM_AC] = { 2629 R92C_EDCA_BE_PARAM, 2630 R92C_EDCA_BK_PARAM, 2631 R92C_EDCA_VI_PARAM, 2632 R92C_EDCA_VO_PARAM 2633 }; 2634 struct ieee80211com *ic = &sc->sc_ic; 2635 const struct wmeParams *wmep; 2636 int ac, aifs, slottime; 2637 int s; 2638 2639 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2640 __func__)); 2641 2642 s = splnet(); 2643 mutex_enter(&sc->sc_write_mtx); 2644 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2645 for (ac = 0; ac < WME_NUM_AC; ac++) { 2646 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2647 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2648 aifs = wmep->wmep_aifsn * slottime + 10; 2649 urtwn_write_4(sc, ac2reg[ac], 2650 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2651 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2652 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2653 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2654 } 2655 mutex_exit(&sc->sc_write_mtx); 2656 splx(s); 2657 } 2658 2659 static void 2660 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2661 { 2662 int pwdb; 2663 2664 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2665 device_xname(sc->sc_dev), __func__, rate, rssi)); 2666 2667 /* Convert antenna signal to percentage. */ 2668 if (rssi <= -100 || rssi >= 20) 2669 pwdb = 0; 2670 else if (rssi >= 0) 2671 pwdb = 100; 2672 else 2673 pwdb = 100 + rssi; 2674 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2675 if (rate <= 3) { 2676 /* CCK gain is smaller than OFDM/MCS gain. */ 2677 pwdb += 6; 2678 if (pwdb > 100) 2679 pwdb = 100; 2680 if (pwdb <= 14) 2681 pwdb -= 4; 2682 else if (pwdb <= 26) 2683 pwdb -= 8; 2684 else if (pwdb <= 34) 2685 pwdb -= 6; 2686 else if (pwdb <= 42) 2687 pwdb -= 2; 2688 } 2689 } 2690 if (sc->avg_pwdb == -1) /* Init. */ 2691 sc->avg_pwdb = pwdb; 2692 else if (sc->avg_pwdb < pwdb) 2693 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2694 else 2695 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2696 2697 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2698 device_xname(sc->sc_dev), __func__, 2699 rate, rssi, pwdb, sc->avg_pwdb)); 2700 } 2701 2702 static int8_t 2703 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2704 { 2705 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2706 struct r92c_rx_phystat *phy; 2707 struct r92c_rx_cck *cck; 2708 uint8_t rpt; 2709 int8_t rssi; 2710 2711 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2712 __func__, rate)); 2713 2714 if (rate <= 3) { 2715 cck = (struct r92c_rx_cck *)physt; 2716 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2717 rpt = (cck->agc_rpt >> 5) & 0x3; 2718 rssi = (cck->agc_rpt & 0x1f) << 1; 2719 } else { 2720 rpt = (cck->agc_rpt >> 6) & 0x3; 2721 rssi = cck->agc_rpt & 0x3e; 2722 } 2723 rssi = cckoff[rpt] - rssi; 2724 } else { /* OFDM/HT. */ 2725 phy = (struct r92c_rx_phystat *)physt; 2726 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2727 } 2728 return rssi; 2729 } 2730 2731 static int8_t 2732 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2733 { 2734 struct r92c_rx_phystat *phy; 2735 struct r88e_rx_cck *cck; 2736 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2737 int8_t rssi; 2738 2739 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2740 __func__, rate)); 2741 2742 rssi = 0; 2743 if (rate <= 3) { 2744 cck = (struct r88e_rx_cck *)physt; 2745 cck_agc_rpt = cck->agc_rpt; 2746 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2747 vga_idx = cck_agc_rpt & 0x1f; 2748 switch (lna_idx) { 2749 case 7: 2750 if (vga_idx <= 27) 2751 rssi = -100 + 2* (27 - vga_idx); 2752 else 2753 rssi = -100; 2754 break; 2755 case 6: 2756 rssi = -48 + 2 * (2 - vga_idx); 2757 break; 2758 case 5: 2759 rssi = -42 + 2 * (7 - vga_idx); 2760 break; 2761 case 4: 2762 rssi = -36 + 2 * (7 - vga_idx); 2763 break; 2764 case 3: 2765 rssi = -24 + 2 * (7 - vga_idx); 2766 break; 2767 case 2: 2768 rssi = -12 + 2 * (5 - vga_idx); 2769 break; 2770 case 1: 2771 rssi = 8 - (2 * vga_idx); 2772 break; 2773 case 0: 2774 rssi = 14 - (2 * vga_idx); 2775 break; 2776 } 2777 rssi += 6; 2778 } else { /* OFDM/HT. */ 2779 phy = (struct r92c_rx_phystat *)physt; 2780 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2781 } 2782 return rssi; 2783 } 2784 2785 static void 2786 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2787 { 2788 struct ieee80211com *ic = &sc->sc_ic; 2789 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2790 struct ifnet *ifp = vap->iv_ifp; 2791 struct ieee80211_frame *wh; 2792 struct ieee80211_node *ni; 2793 struct r92c_rx_desc_usb *stat; 2794 uint32_t rxdw0, rxdw3; 2795 struct mbuf *m; 2796 uint8_t rate; 2797 int8_t rssi = 0; 2798 int s, infosz; 2799 2800 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2801 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2802 2803 stat = (struct r92c_rx_desc_usb *)buf; 2804 rxdw0 = le32toh(stat->rxdw0); 2805 rxdw3 = le32toh(stat->rxdw3); 2806 2807 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2808 /* 2809 * This should not happen since we setup our Rx filter 2810 * to not receive these frames. 2811 */ 2812 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2813 device_xname(sc->sc_dev), __func__)); 2814 if_statinc(ifp, if_ierrors); 2815 return; 2816 } 2817 2818 /* 2819 * XXX: This will drop most control packets. Do we really 2820 * want this in IEEE80211_M_MONITOR mode? 2821 */ 2822 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2823 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2824 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2825 device_xname(sc->sc_dev), __func__, pktlen)); 2826 vap->iv_stats.is_rx_tooshort++; 2827 if_statinc(ifp,if_ierrors); 2828 return; 2829 } 2830 if (__predict_false(pktlen > MCLBYTES)) { 2831 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2832 device_xname(sc->sc_dev), __func__, pktlen)); 2833 if_statinc(ifp, if_ierrors); 2834 return; 2835 } 2836 2837 rate = MS(rxdw3, R92C_RXDW3_RATE); 2838 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2839 2840 /* Get RSSI from PHY status descriptor if present. */ 2841 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2842 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2843 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2844 else 2845 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2846 /* Update our average RSSI. */ 2847 urtwn_update_avgrssi(sc, rate, rssi); 2848 } 2849 2850 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2851 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2852 2853 MGETHDR(m, M_DONTWAIT, MT_DATA); 2854 if (__predict_false(m == NULL)) { 2855 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2856 vap->iv_stats.is_rx_nobuf++; 2857 if_statinc(ifp, if_ierrors); 2858 return; 2859 } 2860 if (pktlen > (int)MHLEN) { 2861 MCLGET(m, M_DONTWAIT); 2862 if (__predict_false(!(m->m_flags & M_EXT))) { 2863 aprint_error_dev(sc->sc_dev, 2864 "couldn't allocate rx mbuf cluster\n"); 2865 m_freem(m); 2866 vap->iv_stats.is_rx_nobuf++; 2867 if_statinc(ifp, if_ierrors); 2868 return; 2869 } 2870 } 2871 2872 /* Finalize mbuf. */ 2873 m_set_rcvif(m, ifp); 2874 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2875 2876 memcpy(mtod(m, uint8_t *), wh, pktlen); 2877 m->m_pkthdr.len = m->m_len = pktlen; 2878 2879 s = splnet(); 2880 if (__predict_false(sc->sc_drvbpf != NULL)) { 2881 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2882 2883 tap->wr_flags = 0; 2884 if (!(rxdw3 & R92C_RXDW3_HT)) { 2885 switch (rate) { 2886 /* CCK. */ 2887 case 0: tap->wr_rate = 2; break; 2888 case 1: tap->wr_rate = 4; break; 2889 case 2: tap->wr_rate = 11; break; 2890 case 3: tap->wr_rate = 22; break; 2891 /* OFDM. */ 2892 case 4: tap->wr_rate = 12; break; 2893 case 5: tap->wr_rate = 18; break; 2894 case 6: tap->wr_rate = 24; break; 2895 case 7: tap->wr_rate = 36; break; 2896 case 8: tap->wr_rate = 48; break; 2897 case 9: tap->wr_rate = 72; break; 2898 case 10: tap->wr_rate = 96; break; 2899 case 11: tap->wr_rate = 108; break; 2900 } 2901 } else if (rate >= 12) { /* MCS0~15. */ 2902 /* Bit 7 set means HT MCS instead of rate. */ 2903 tap->wr_rate = 0x80 | (rate - 12); 2904 } 2905 tap->wr_dbm_antsignal = rssi; 2906 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2907 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2908 2909 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2910 } 2911 2912 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2913 2914 if (ni != NULL) { 2915 if (ni->ni_vap != NULL) { 2916 2917 } else { 2918 splx(s); 2919 return; 2920 } 2921 /* push the frame up to the 802.11 stack */ 2922 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2923 ieee80211_input(ni, m, rssi+90, 0); 2924 2925 /* Node is no longer needed. */ 2926 ieee80211_free_node(ni); 2927 2928 } else { 2929 2930 /* No node found ... process differently. */ 2931 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2932 } 2933 2934 splx(s); 2935 } 2936 2937 static void 2938 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2939 { 2940 struct urtwn_rx_data *data = priv; 2941 struct urtwn_softc *sc = data->sc; 2942 struct r92c_rx_desc_usb *stat; 2943 size_t pidx = data->pidx; 2944 uint32_t rxdw0; 2945 uint8_t *buf; 2946 int len, totlen, pktlen, infosz, npkts; 2947 2948 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2949 device_xname(sc->sc_dev), __func__, status)); 2950 2951 mutex_enter(&sc->sc_rx_mtx); 2952 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2953 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2954 /* Put this Rx buffer back to our free list. */ 2955 mutex_exit(&sc->sc_rx_mtx); 2956 2957 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2958 if (status == USBD_STALLED) 2959 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2960 else if (status != USBD_CANCELLED) 2961 goto resubmit; 2962 return; 2963 } 2964 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2965 2966 if (__predict_false(len < (int)sizeof(*stat))) { 2967 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2968 device_xname(sc->sc_dev), __func__, len)); 2969 goto resubmit; 2970 } 2971 buf = data->buf; 2972 2973 /* Get the number of encapsulated frames. */ 2974 stat = (struct r92c_rx_desc_usb *)buf; 2975 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2976 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2977 else 2978 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2979 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2980 device_xname(sc->sc_dev), __func__, npkts)); 2981 2982 /* Process all of them. */ 2983 while (npkts-- > 0) { 2984 if (__predict_false(len < (int)sizeof(*stat))) { 2985 DPRINTFN(DBG_RX, 2986 ("%s: %s: len(%d) is short than header\n", 2987 device_xname(sc->sc_dev), __func__, len)); 2988 break; 2989 } 2990 stat = (struct r92c_rx_desc_usb *)buf; 2991 rxdw0 = le32toh(stat->rxdw0); 2992 2993 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2994 if (__predict_false(pktlen == 0)) { 2995 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2996 device_xname(sc->sc_dev), __func__)); 2997 break; 2998 } 2999 3000 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 3001 3002 /* Make sure everything fits in xfer. */ 3003 totlen = sizeof(*stat) + infosz + pktlen; 3004 if (__predict_false(totlen > len)) { 3005 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 3006 device_xname(sc->sc_dev), __func__, totlen, 3007 (int)sizeof(*stat), infosz, pktlen, len)); 3008 break; 3009 } 3010 3011 /* Process 802.11 frame. */ 3012 urtwn_rx_frame(sc, buf, pktlen); 3013 3014 /* Next chunk is 128-byte aligned. */ 3015 totlen = roundup2(totlen, 128); 3016 buf += totlen; 3017 len -= totlen; 3018 } 3019 3020 resubmit: 3021 /* Setup a new transfer. */ 3022 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 3023 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 3024 (void)usbd_transfer(xfer); 3025 } 3026 3027 static void 3028 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3029 { 3030 struct urtwn_tx_data *data = priv; 3031 struct urtwn_softc *sc = data->sc; 3032 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 3033 size_t pidx = data->pidx; 3034 int s; 3035 3036 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 3037 device_xname(sc->sc_dev), __func__, status)); 3038 3039 mutex_enter(&sc->sc_tx_mtx); 3040 /* Put this Tx buffer back to our free list. */ 3041 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 3042 mutex_exit(&sc->sc_tx_mtx); 3043 3044 s = splnet(); 3045 sc->tx_timer = 0; 3046 ifp->if_flags &= ~IFF_OACTIVE; 3047 3048 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 3049 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 3050 if (status == USBD_STALLED) { 3051 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 3052 usbd_clear_endpoint_stall_async(pipe); 3053 } 3054 printf("ERROR1\n"); 3055 if_statinc(ifp, if_oerrors); 3056 } 3057 splx(s); 3058 return; 3059 } 3060 3061 if_statinc(ifp, if_opackets); 3062 urtwn_start(ifp); 3063 splx(s); 3064 3065 } 3066 3067 static int 3068 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3069 struct urtwn_tx_data *data) 3070 { 3071 struct ieee80211com *ic = &sc->sc_ic; 3072 struct ieee80211_frame *wh; 3073 struct ieee80211_key *k = NULL; 3074 struct r92c_tx_desc_usb *txd; 3075 size_t i, padsize, xferlen, txd_len; 3076 uint16_t seq, sum; 3077 uint8_t raid, type, tid; 3078 int s, hasqos, error; 3079 3080 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3081 3082 wh = mtod(m, struct ieee80211_frame *); 3083 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3084 txd_len = sizeof(*txd); 3085 3086 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3087 txd_len = 32; 3088 3089 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3090 k = ieee80211_crypto_encap(ni, m); 3091 if (k == NULL) 3092 return ENOBUFS; 3093 3094 /* packet header may have moved, reset our local pointer */ 3095 wh = mtod(m, struct ieee80211_frame *); 3096 } 3097 3098 if (__predict_false(sc->sc_drvbpf != NULL)) { 3099 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3100 3101 tap->wt_flags = 0; 3102 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3103 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3104 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3105 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3106 3107 /* XXX: set tap->wt_rate? */ 3108 3109 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3110 } 3111 3112 /* non-qos data frames */ 3113 tid = R92C_TXDW1_QSEL_BE; 3114 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3115 /* data frames in 11n mode */ 3116 struct ieee80211_qosframe *qwh = (void *)wh; 3117 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3118 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3119 tid = R92C_TXDW1_QSEL_MGNT; 3120 } 3121 3122 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3123 padsize = 8; 3124 else 3125 padsize = 0; 3126 3127 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3128 padsize = 0; 3129 3130 /* Fill Tx descriptor. */ 3131 txd = (struct r92c_tx_desc_usb *)data->buf; 3132 memset(txd, 0, txd_len + padsize); 3133 3134 txd->txdw0 |= htole32( 3135 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3136 SM(R92C_TXDW0_OFFSET, txd_len)); 3137 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3138 txd->txdw0 |= htole32( 3139 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3140 } 3141 3142 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3143 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3144 3145 /* fix pad field */ 3146 if (padsize > 0) { 3147 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3148 device_xname(sc->sc_dev), __func__, padsize)); 3149 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3150 } 3151 if (ic->ic_curmode == IEEE80211_MODE_11B) { 3152 raid = R92C_RAID_11B; 3153 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3154 } else if (ic->ic_curmode == IEEE80211_MODE_11G) { 3155 raid = R92C_RAID_11BG; 3156 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3157 } else { /* IEEE80211_MODE_11NG */ 3158 raid = R92C_RAID_11GN; 3159 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 19)); 3160 txd->txdw5 |= htole32(R92C_TXDW5_SGI); 3161 } 3162 3163 3164 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3165 type == IEEE80211_FC0_TYPE_DATA) { 3166 DPRINTFN(DBG_TX, 3167 ("%s: %s: data packet: tid=%d, raid=%d\n", 3168 device_xname(sc->sc_dev), __func__, tid, raid)); 3169 3170 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3171 txd->txdw1 |= htole32( 3172 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3173 SM(R92C_TXDW1_QSEL, tid) | 3174 SM(R92C_TXDW1_RAID, raid) | 3175 R92C_TXDW1_AGGBK); 3176 } else 3177 txd->txdw1 |= htole32( 3178 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3179 SM(R92C_TXDW1_QSEL, tid) | 3180 SM(R92C_TXDW1_RAID, raid) | 3181 R92C_TXDW1_AGGBK); 3182 3183 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3184 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3185 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3186 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3187 3188 if (hasqos) { 3189 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3190 } 3191 3192 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3193 /* for 11g */ 3194 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3195 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3196 R92C_TXDW4_HWRTSEN); 3197 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3198 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3199 R92C_TXDW4_HWRTSEN); 3200 } 3201 } 3202 /* Send RTS at OFDM24. */ 3203 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3204 txd->txdw5 |= htole32(0x0001ff00); 3205 /* Send data at OFDM54. */ 3206 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3207 txd->txdw5 |= htole32(0x13 & 0x3f); 3208 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3209 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3210 device_xname(sc->sc_dev), __func__)); 3211 txd->txdw1 |= htole32( 3212 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3213 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3214 SM(R92C_TXDW1_RAID, raid)); 3215 3216 #if 0 3217 /* Force CCK1. */ 3218 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3219 #endif 3220 } else { 3221 /* broadcast or multicast packets */ 3222 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3223 device_xname(sc->sc_dev), __func__)); 3224 txd->txdw1 |= htole32( 3225 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3226 SM(R92C_TXDW1_RAID, raid)); 3227 3228 #if 0 3229 /* Force CCK1. */ 3230 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3231 #endif 3232 } 3233 /* Set sequence number */ 3234 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3235 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3236 txd->txdseq |= htole16(seq); 3237 3238 if (!hasqos) { 3239 /* Use HW sequence numbering for non-QoS frames. */ 3240 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3241 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3242 } 3243 } else { 3244 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3245 R92E_HWSEQ_SHIFT); 3246 if (!hasqos) { 3247 /* Use HW sequence numbering for non-QoS frames. */ 3248 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3249 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3250 } 3251 } 3252 3253 /* Compute Tx descriptor checksum. */ 3254 sum = 0; 3255 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3256 sum ^= ((uint16_t *)txd)[i]; 3257 txd->txdsum = sum; /* NB: already little endian. */ 3258 3259 xferlen = txd_len + m->m_pkthdr.len + padsize; 3260 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3261 3262 if (data->xfer == NULL) { 3263 /* NNN Don't crash ... but what is going on! */ 3264 printf ("urtwn_tx: data->xfer is NULL\n"); 3265 m_print(m,"", printf); 3266 return -1; 3267 } 3268 3269 s = splnet(); 3270 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3271 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3272 urtwn_txeof); 3273 error = usbd_transfer(data->xfer); 3274 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3275 error != USBD_IN_PROGRESS)) { 3276 splx(s); 3277 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3278 device_xname(sc->sc_dev), __func__, error)); 3279 return error; 3280 } 3281 splx(s); 3282 return 0; 3283 } 3284 3285 struct urtwn_tx_data * 3286 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3287 { 3288 struct urtwn_tx_data *data = NULL; 3289 3290 mutex_enter(&sc->sc_tx_mtx); 3291 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3292 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3293 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3294 } 3295 mutex_exit(&sc->sc_tx_mtx); 3296 3297 return data; 3298 } 3299 3300 static void 3301 urtwn_start(struct ifnet *ifp) 3302 { 3303 struct ieee80211vap *vap = ifp->if_softc; 3304 struct ieee80211com *ic = vap->iv_ic; 3305 struct urtwn_softc *sc = ic->ic_softc; 3306 struct urtwn_tx_data *data; 3307 struct ether_header *eh; 3308 struct ieee80211_node *ni; 3309 struct mbuf *m; 3310 3311 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3312 3313 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3314 return; 3315 3316 data = NULL; 3317 for (;;) { 3318 /* Send pending management frames first. */ 3319 IF_POLL(&ic->ic_mgtq, m); 3320 if (m != NULL) { 3321 /* Use AC_VO for management frames. */ 3322 3323 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3324 3325 if (data == NULL) { 3326 ifp->if_flags |= IFF_OACTIVE; 3327 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3328 device_xname(sc->sc_dev))); 3329 return; 3330 } 3331 IF_DEQUEUE(&ic->ic_mgtq, m); 3332 ni = M_GETCTX(m, struct ieee80211_node *); 3333 M_CLEARCTX(m); 3334 goto sendit; 3335 } 3336 3337 if (vap->iv_state != IEEE80211_S_RUN) 3338 break; 3339 3340 /* Encapsulate and send data frames. */ 3341 IFQ_POLL(&sc->sc_sendq, m); 3342 if (m == NULL) 3343 break; 3344 3345 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3346 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3347 uint8_t qid = WME_AC_BE; 3348 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3349 /* data frames in 11n mode */ 3350 struct ieee80211_qosframe *qwh = (void *)wh; 3351 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3352 qid = TID_TO_WME_AC(tid); 3353 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3354 qid = WME_AC_VO; 3355 } 3356 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3357 3358 if (data == NULL) { 3359 ifp->if_flags |= IFF_OACTIVE; 3360 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3361 device_xname(sc->sc_dev))); 3362 return; 3363 } 3364 IFQ_DEQUEUE(&sc->sc_sendq, m); 3365 3366 if (m->m_len < (int)sizeof(*eh) && 3367 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3368 printf("ERROR6\n"); 3369 if_statinc(ifp, if_oerrors); 3370 continue; 3371 } 3372 eh = mtod(m, struct ether_header *); 3373 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3374 if (ni == NULL) { 3375 m_freem(m); 3376 printf("ERROR5\n"); 3377 if_statinc(ifp, if_oerrors); 3378 continue; 3379 } 3380 3381 //bpf_mtap(ifp, m, BPF_D_OUT); 3382 3383 sendit: 3384 if (urtwn_tx(sc, m, ni, data) != 0) { 3385 m_freem(m); 3386 ieee80211_free_node(ni); 3387 printf("ERROR3\n"); 3388 if_statinc(ifp, if_oerrors); 3389 continue; 3390 } 3391 m_freem(m); 3392 ieee80211_free_node(ni); 3393 sc->tx_timer = 5; 3394 ifp->if_timer = 1; 3395 } 3396 } 3397 3398 static __unused void 3399 urtwn_watchdog(struct ifnet *ifp) 3400 { 3401 struct ieee80211vap *vap = ifp->if_softc; 3402 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3403 3404 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3405 3406 ifp->if_timer = 0; 3407 3408 if (sc->tx_timer > 0) { 3409 if (--sc->tx_timer == 0) { 3410 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3411 /* urtwn_init(ifp); XXX needs a process context! */ 3412 printf("ERROR2\n"); 3413 if_statinc(ifp, if_oerrors); 3414 return; 3415 } 3416 ifp->if_timer = 1; 3417 } 3418 // ieee80211_watchdog(&sc->sc_ic); 3419 } 3420 3421 /* 3422 * Create a VAP node for use with the urtwn driver. 3423 */ 3424 3425 static struct ieee80211vap * 3426 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3427 int unit, enum ieee80211_opmode opmode, int flags, 3428 const uint8_t bssid[IEEE80211_ADDR_LEN], 3429 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3430 { 3431 struct urtwn_softc *sc = ic->ic_softc; 3432 struct ifnet *ifp; 3433 struct ieee80211vap *vap; 3434 3435 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3436 3437 /* Allow only one VAP for the urtwn driver. */ 3438 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3439 return NULL; 3440 3441 /* Allocate the vap and setup. */ 3442 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3443 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3444 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3445 kmem_free(vap, sizeof(struct ieee80211vap)); 3446 return NULL; 3447 } 3448 3449 /* Local setup */ 3450 vap->iv_reset = urtwn_reset; 3451 3452 ifp = vap->iv_ifp; 3453 if_initialize(ifp); 3454 ifp->if_init = urtwn_init; 3455 ifp->if_ioctl = urtwn_ioctl; 3456 ifp->if_start = urtwn_start; 3457 // ifp->if_watchdog = urtwn_watchdog; NNN 3458 ifp->if_extflags |= IFEF_MPSAFE; 3459 // IFQ_SET_READY(&ifp->if_snd); 3460 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3461 3462 //ifp->if_percpuq = if_percpuq_create(ifp); 3463 3464 /* Override state transition machine. */ 3465 /* NNN --- many possible newstate machines ... issue! */ 3466 sc->sc_newstate = vap->iv_newstate; 3467 vap->iv_newstate = urtwn_newstate; 3468 3469 /* Finish setup */ 3470 ieee80211_vap_attach(vap, urtwn_media_change, 3471 ieee80211_media_status, macaddr); 3472 ic->ic_opmode = opmode; 3473 3474 /* Attach the packet filter */ 3475 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3476 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3477 &sc->sc_drvbpf); 3478 3479 return vap; 3480 } 3481 3482 static void 3483 urtwn_vap_delete(struct ieee80211vap *vap) 3484 { 3485 struct ifnet *ifp = vap->iv_ifp; 3486 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3487 3488 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3489 3490 urtwn_stop(ifp, 0); 3491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3492 bpf_detach(ifp); 3493 if_detach(ifp); 3494 kmem_free(vap, sizeof(struct ieee80211vap)); 3495 } 3496 3497 static void 3498 urtwn_parent(struct ieee80211com *ic) 3499 { 3500 struct urtwn_softc *sc __unused = ic->ic_softc; 3501 3502 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3503 3504 /* Not sure what to do here yet. */ 3505 } 3506 3507 static void 3508 urtwn_scan_start(struct ieee80211com *ic) 3509 { 3510 #ifdef URTWN_DEBUG 3511 struct urtwn_softc *sc = ic->ic_softc; 3512 #endif 3513 //uint32_t reg; 3514 //int s; 3515 3516 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3517 3518 /* 3519 * Not sure what to do here yet. Try #1: do what was in the 3520 * state machine. NNN 3521 */ 3522 #if NOTWITHSTATEMACHINEOVERRIDE 3523 /* 3524 * Begin of scanning 3525 */ 3526 3527 s = splnet(); 3528 mutex_enter(&sc->sc_write_mtx); 3529 3530 /* Set gain for scanning. */ 3531 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3532 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3533 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3534 3535 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3536 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3537 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3538 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3539 } 3540 3541 /* Set media status to 'No Link'. */ 3542 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3543 3544 /* Allow Rx from any BSSID. */ 3545 urtwn_write_4(sc, R92C_RCR, 3546 urtwn_read_4(sc, R92C_RCR) & 3547 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3548 3549 /* Stop Rx of data frames. */ 3550 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3551 3552 /* Disable update TSF */ 3553 urtwn_write_1(sc, R92C_BCN_CTRL, 3554 urtwn_read_1(sc, R92C_BCN_CTRL) | 3555 R92C_BCN_CTRL_DIS_TSF_UDT0); 3556 3557 /* Make link LED blink during scan. */ 3558 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3559 3560 /* Pause AC Tx queues. */ 3561 urtwn_write_1(sc, R92C_TXPAUSE, 3562 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3563 3564 urtwn_set_chan(sc, ic->ic_curchan, 3565 IEEE80211_HTINFO_2NDCHAN_NONE); 3566 3567 mutex_exit(&sc->sc_write_mtx); 3568 splx(s); 3569 #endif 3570 } 3571 3572 static void 3573 urtwn_scan_end(struct ieee80211com *ic) 3574 { 3575 #ifdef URTWN_DEBUG 3576 struct urtwn_softc *sc = ic->ic_softc; 3577 #endif 3578 3579 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3580 3581 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3582 /* 3583 * End of scanning 3584 */ 3585 3586 mutex_enter(&sc->sc_write_mtx); 3587 3588 /* flush 4-AC Queue after site_survey */ 3589 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3590 3591 /* Allow Rx from our BSSID only. */ 3592 urtwn_write_4(sc, R92C_RCR, 3593 urtwn_read_4(sc, R92C_RCR) | 3594 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3595 3596 /* Turn link LED off. */ 3597 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3598 3599 mutex_exit(&sc->sc_write_mtx); 3600 #endif 3601 } 3602 3603 static void 3604 urtwn_set_channel(struct ieee80211com *ic) 3605 { 3606 struct urtwn_softc *sc = ic->ic_softc; 3607 3608 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3609 3610 mutex_enter(&sc->sc_write_mtx); 3611 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3612 mutex_exit(&sc->sc_write_mtx); 3613 } 3614 3615 static int 3616 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3617 { 3618 struct urtwn_softc *sc = ic->ic_softc; 3619 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3620 int s; 3621 size_t pktlen = m->m_pkthdr.len; 3622 bool mcast = (m->m_flags & M_MCAST) != 0; 3623 3624 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3625 3626 s = splnet(); 3627 3628 IF_ENQUEUE(&sc->sc_sendq, m); 3629 3630 if_statadd(vap->iv_ifp, if_obytes, pktlen); 3631 if (mcast) 3632 if_statinc(vap->iv_ifp, if_omcasts); 3633 3634 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3635 if_start_lock(vap->iv_ifp); 3636 splx(s); 3637 3638 urtwn_start(vap->iv_ifp); 3639 3640 return 0; 3641 } 3642 3643 #if 0 3644 static int 3645 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3646 #ifdef URTWN_DEBUG 3647 // struct ieee80211vap *vap = ni->ni_vap; 3648 struct ieee80211com *ic = ni->ni_ic; 3649 struct urtwn_softc *sc = ic->ic_softc; 3650 #endif 3651 3652 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3653 3654 /* Don't know what to do right now. */ 3655 return ENOTTY; 3656 } 3657 #endif 3658 3659 3660 static int 3661 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3662 const struct ieee80211_bpf_params *bpfp) 3663 { 3664 struct ieee80211vap *vap = ni->ni_vap; 3665 struct ieee80211com *ic = ni->ni_ic; 3666 struct urtwn_softc *sc = ic->ic_softc; 3667 struct urtwn_tx_data *data; 3668 int error; 3669 3670 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3671 3672 KASSERT(vap != NULL); /* NNN need these? */ 3673 KASSERT(ic != NULL); 3674 KASSERT(sc != NULL); 3675 KASSERT(m != NULL); 3676 3677 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3678 3679 if (data == NULL) { 3680 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3681 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3682 device_xname(sc->sc_dev))); 3683 return ENOBUFS; 3684 } 3685 3686 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3687 3688 error = urtwn_tx(sc, m, ni, data); 3689 if (error != 0) { 3690 printf("ERROR3\n"); 3691 if_statinc(vap->iv_ifp, if_oerrors); 3692 } else { 3693 sc->tx_timer = 5; 3694 vap->iv_ifp->if_timer = 1; 3695 } 3696 m_freem(m); 3697 ieee80211_free_node(ni); 3698 return error; 3699 } 3700 3701 static void 3702 urtwn_getradiocaps(struct ieee80211com *ic, 3703 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3704 { 3705 uint8_t bands[IEEE80211_MODE_BYTES]; 3706 3707 /* 3708 * NNN Should be able to do something based on chip if 3709 * a chip has more bands .... eg. N ... but for the future. 3710 */ 3711 3712 memset(bands, 0, sizeof(bands)); 3713 setbit(bands, IEEE80211_MODE_11B); 3714 setbit(bands, IEEE80211_MODE_11G); 3715 setbit(bands, IEEE80211_MODE_11NG); 3716 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3717 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, IEEE80211_CHAN_HT20); 3718 } 3719 3720 3721 static int 3722 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3723 { 3724 3725 struct ieee80211vap *vap = ifp->if_softc; 3726 struct ieee80211com *ic = vap->iv_ic; 3727 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3728 int s, error = 0; 3729 3730 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3731 device_xname(sc->sc_dev), __func__, cmd, data)); 3732 3733 s = splnet(); 3734 3735 switch (cmd) { 3736 case SIOCSIFFLAGS: 3737 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3738 break; 3739 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3740 case IFF_UP | IFF_RUNNING: 3741 break; 3742 case IFF_UP: 3743 urtwn_init(ifp); 3744 break; 3745 case IFF_RUNNING: 3746 urtwn_stop(ifp, 1); 3747 break; 3748 case 0: 3749 break; 3750 } 3751 break; 3752 3753 case SIOCADDMULTI: 3754 case SIOCDELMULTI: 3755 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3756 /* setup multicast filter, etc */ 3757 error = 0; 3758 } 3759 break; 3760 3761 case SIOCS80211CHANNEL: 3762 /* 3763 * This allows for fast channel switching in monitor mode 3764 * (used by kismet). In IBSS mode, we must explicitly reset 3765 * the interface to generate a new beacon frame. 3766 */ 3767 error = ieee80211_ioctl(ifp, cmd, data); 3768 if (error == ENETRESET && 3769 ic->ic_opmode == IEEE80211_M_MONITOR) { 3770 urtwn_set_chan(sc, ic->ic_curchan, 3771 IEEE80211_HTINFO_2NDCHAN_NONE); 3772 error = 0; 3773 } 3774 break; 3775 3776 default: 3777 error = ieee80211_ioctl(ifp, cmd, data); 3778 break; 3779 } 3780 if (error == ENETRESET) { 3781 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3782 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3783 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3784 urtwn_init(ifp); 3785 } 3786 error = 0; 3787 } 3788 3789 splx(s); 3790 3791 return error; 3792 } 3793 3794 static __inline int 3795 urtwn_power_on(struct urtwn_softc *sc) 3796 { 3797 3798 return sc->sc_power_on(sc); 3799 } 3800 3801 static int 3802 urtwn_r92c_power_on(struct urtwn_softc *sc) 3803 { 3804 uint32_t reg; 3805 int ntries; 3806 3807 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3808 3809 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3810 3811 /* Wait for autoload done bit. */ 3812 for (ntries = 0; ntries < 1000; ntries++) { 3813 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3814 break; 3815 DELAY(5); 3816 } 3817 if (ntries == 1000) { 3818 aprint_error_dev(sc->sc_dev, 3819 "timeout waiting for chip autoload\n"); 3820 return ETIMEDOUT; 3821 } 3822 3823 /* Unlock ISO/CLK/Power control register. */ 3824 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3825 /* Move SPS into PWM mode. */ 3826 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3827 DELAY(5); 3828 3829 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3830 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3831 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3832 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3833 DELAY(100); 3834 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3835 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3836 ~R92C_SYS_ISO_CTRL_MD2PP); 3837 } 3838 3839 /* Auto enable WLAN. */ 3840 urtwn_write_2(sc, R92C_APS_FSMCO, 3841 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3842 for (ntries = 0; ntries < 1000; ntries++) { 3843 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3844 R92C_APS_FSMCO_APFM_ONMAC)) 3845 break; 3846 DELAY(100); 3847 } 3848 if (ntries == 1000) { 3849 aprint_error_dev(sc->sc_dev, 3850 "timeout waiting for MAC auto ON\n"); 3851 return ETIMEDOUT; 3852 } 3853 3854 /* Enable radio, GPIO and LED functions. */ 3855 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3856 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3857 urtwn_write_2(sc, R92C_APS_FSMCO, 3858 R92C_APS_FSMCO_AFSM_HSUS | 3859 R92C_APS_FSMCO_PDN_EN | 3860 R92C_APS_FSMCO_PFM_ALDN); 3861 3862 /* Release RF digital isolation. */ 3863 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3864 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3865 3866 /* Initialize MAC. */ 3867 urtwn_write_1(sc, R92C_APSD_CTRL, 3868 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3869 for (ntries = 0; ntries < 200; ntries++) { 3870 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3871 R92C_APSD_CTRL_OFF_STATUS)) 3872 break; 3873 DELAY(5); 3874 } 3875 if (ntries == 200) { 3876 aprint_error_dev(sc->sc_dev, 3877 "timeout waiting for MAC initialization\n"); 3878 return ETIMEDOUT; 3879 } 3880 3881 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3882 reg = urtwn_read_2(sc, R92C_CR); 3883 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3884 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3885 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3886 R92C_CR_ENSEC; 3887 urtwn_write_2(sc, R92C_CR, reg); 3888 3889 urtwn_write_1(sc, 0xfe10, 0x19); 3890 return 0; 3891 } 3892 3893 static int 3894 urtwn_r92e_power_on(struct urtwn_softc *sc) 3895 { 3896 uint32_t reg; 3897 uint32_t val; 3898 int ntries; 3899 3900 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3901 3902 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3903 3904 /* Enable radio, GPIO and LED functions. */ 3905 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3906 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3907 urtwn_write_2(sc, R92C_APS_FSMCO, 3908 R92C_APS_FSMCO_AFSM_HSUS | 3909 R92C_APS_FSMCO_PDN_EN | 3910 R92C_APS_FSMCO_PFM_ALDN); 3911 3912 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3913 /* LDO. */ 3914 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3915 } 3916 else { 3917 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3918 R92C_SYS_SWR_CTRL2) & 0xffff); 3919 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3920 } 3921 3922 for (ntries = 0; ntries < 2; ntries++) { 3923 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3924 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3925 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3926 R92C_AFE_CTRL4)); 3927 } 3928 3929 /* Reset BB. */ 3930 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3931 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3932 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3933 3934 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3935 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3936 3937 /* Disable HWPDN. */ 3938 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3939 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3940 3941 /* Disable WL suspend. */ 3942 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3943 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3944 R92C_APS_FSMCO_AFSM_HSUS)); 3945 3946 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3947 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3948 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3949 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3950 for (ntries = 0; ntries < 10000; ntries++) { 3951 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3952 R92C_APS_FSMCO_APFM_ONMAC; 3953 if (val == 0x0) 3954 break; 3955 DELAY(10); 3956 } 3957 if (ntries == 10000) { 3958 aprint_error_dev(sc->sc_dev, 3959 "timeout waiting for chip power up\n"); 3960 return ETIMEDOUT; 3961 } 3962 3963 urtwn_write_2(sc, R92C_CR, 0x00); 3964 reg = urtwn_read_2(sc, R92C_CR); 3965 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3966 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3967 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3968 urtwn_write_2(sc, R92C_CR, reg); 3969 3970 return 0; 3971 } 3972 3973 static int 3974 urtwn_r88e_power_on(struct urtwn_softc *sc) 3975 { 3976 uint32_t reg; 3977 uint8_t val; 3978 int ntries; 3979 3980 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3981 3982 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3983 3984 /* Wait for power ready bit. */ 3985 for (ntries = 0; ntries < 5000; ntries++) { 3986 val = urtwn_read_1(sc, 0x6) & 0x2; 3987 if (val == 0x2) 3988 break; 3989 DELAY(10); 3990 } 3991 if (ntries == 5000) { 3992 aprint_error_dev(sc->sc_dev, 3993 "timeout waiting for chip power up\n"); 3994 return ETIMEDOUT; 3995 } 3996 3997 /* Reset BB. */ 3998 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3999 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 4000 R92C_SYS_FUNC_EN_BB_GLB_RST)); 4001 4002 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 4003 4004 /* Disable HWPDN. */ 4005 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 4006 4007 /* Disable WL suspend. */ 4008 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 4009 4010 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 4011 for (ntries = 0; ntries < 5000; ntries++) { 4012 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 4013 break; 4014 DELAY(10); 4015 } 4016 if (ntries == 5000) 4017 return ETIMEDOUT; 4018 4019 /* Enable LDO normal mode. */ 4020 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 4021 4022 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 4023 urtwn_write_2(sc, R92C_CR, 0); 4024 reg = urtwn_read_2(sc, R92C_CR); 4025 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 4026 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 4027 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 4028 urtwn_write_2(sc, R92C_CR, reg); 4029 4030 return 0; 4031 } 4032 4033 static int 4034 urtwn_llt_init(struct urtwn_softc *sc) 4035 { 4036 size_t i, page_count, pktbuf_count; 4037 uint32_t val; 4038 int error; 4039 4040 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4041 4042 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4043 4044 if (sc->chip & URTWN_CHIP_88E) 4045 page_count = R88E_TX_PAGE_COUNT; 4046 else if (sc->chip & URTWN_CHIP_92EU) 4047 page_count = R92E_TX_PAGE_COUNT; 4048 else 4049 page_count = R92C_TX_PAGE_COUNT; 4050 if (sc->chip & URTWN_CHIP_88E) 4051 pktbuf_count = R88E_TXPKTBUF_COUNT; 4052 else if (sc->chip & URTWN_CHIP_92EU) 4053 pktbuf_count = R88E_TXPKTBUF_COUNT; 4054 else 4055 pktbuf_count = R92C_TXPKTBUF_COUNT; 4056 4057 if (sc->chip & URTWN_CHIP_92EU) { 4058 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 4059 urtwn_write_4(sc, R92E_AUTO_LLT, val); 4060 DELAY(100); 4061 val = urtwn_read_4(sc, R92E_AUTO_LLT); 4062 if (val & R92E_AUTO_LLT_EN) 4063 return EIO; 4064 return 0; 4065 } 4066 4067 /* Reserve pages [0; page_count]. */ 4068 for (i = 0; i < page_count; i++) { 4069 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4070 return error; 4071 } 4072 /* NB: 0xff indicates end-of-list. */ 4073 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4074 return error; 4075 /* 4076 * Use pages [page_count + 1; pktbuf_count - 1] 4077 * as ring buffer. 4078 */ 4079 for (++i; i < pktbuf_count - 1; i++) { 4080 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4081 return error; 4082 } 4083 /* Make the last page point to the beginning of the ring buffer. */ 4084 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4085 return error; 4086 } 4087 4088 static void 4089 urtwn_fw_reset(struct urtwn_softc *sc) 4090 { 4091 uint16_t reg; 4092 int ntries; 4093 4094 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4095 4096 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4097 4098 /* Tell 8051 to reset itself. */ 4099 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4100 4101 /* Wait until 8051 resets by itself. */ 4102 for (ntries = 0; ntries < 100; ntries++) { 4103 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4104 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4105 return; 4106 DELAY(50); 4107 } 4108 /* Force 8051 reset. */ 4109 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4110 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4111 } 4112 4113 static void 4114 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4115 { 4116 uint16_t reg; 4117 4118 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4119 4120 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4121 4122 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4123 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4124 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4125 } 4126 DELAY(50); 4127 4128 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4129 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4130 DELAY(50); 4131 4132 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4133 DELAY(50); 4134 4135 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4136 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4137 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4138 } 4139 DELAY(50); 4140 4141 } 4142 4143 static int 4144 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4145 { 4146 uint32_t reg; 4147 int off, mlen, error = 0; 4148 4149 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4150 device_xname(sc->sc_dev), __func__, page, buf, len)); 4151 4152 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4153 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4154 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4155 4156 off = R92C_FW_START_ADDR; 4157 while (len > 0) { 4158 if (len > 196) 4159 mlen = 196; 4160 else if (len > 4) 4161 mlen = 4; 4162 else 4163 mlen = 1; 4164 error = urtwn_write_region(sc, off, buf, mlen); 4165 if (error != 0) 4166 break; 4167 off += mlen; 4168 buf += mlen; 4169 len -= mlen; 4170 } 4171 return error; 4172 } 4173 4174 static int 4175 urtwn_load_firmware(struct urtwn_softc *sc) 4176 { 4177 firmware_handle_t fwh; 4178 const struct r92c_fw_hdr *hdr; 4179 const char *name; 4180 u_char *fw, *ptr; 4181 size_t len; 4182 uint32_t reg; 4183 int mlen, ntries, page, error; 4184 4185 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4186 4187 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4188 4189 /* Read firmware image from the filesystem. */ 4190 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4191 name = "rtl8188eufw.bin"; 4192 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4193 name = "rtl8192eefw.bin"; 4194 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4195 URTWN_CHIP_UMC_A_CUT) 4196 name = "rtl8192cfwU.bin"; 4197 else 4198 name = "rtl8192cfw.bin"; 4199 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4200 aprint_error_dev(sc->sc_dev, 4201 "failed load firmware of file %s (error %d)\n", name, 4202 error); 4203 return error; 4204 } 4205 const size_t fwlen = len = firmware_get_size(fwh); 4206 fw = firmware_malloc(len); 4207 if (fw == NULL) { 4208 aprint_error_dev(sc->sc_dev, 4209 "failed to allocate firmware memory\n"); 4210 firmware_close(fwh); 4211 return ENOMEM; 4212 } 4213 error = firmware_read(fwh, 0, fw, len); 4214 firmware_close(fwh); 4215 if (error != 0) { 4216 aprint_error_dev(sc->sc_dev, 4217 "failed to read firmware (error %d)\n", error); 4218 firmware_free(fw, fwlen); 4219 return error; 4220 } 4221 4222 len = fwlen; 4223 ptr = fw; 4224 hdr = (const struct r92c_fw_hdr *)ptr; 4225 /* Check if there is a valid FW header and skip it. */ 4226 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4227 (le16toh(hdr->signature) >> 4) == 0x88e || 4228 (le16toh(hdr->signature) >> 4) == 0x92e || 4229 (le16toh(hdr->signature) >> 4) == 0x92c) { 4230 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4231 device_xname(sc->sc_dev), __func__, 4232 le16toh(hdr->version), le16toh(hdr->subversion), 4233 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4234 ptr += sizeof(*hdr); 4235 len -= sizeof(*hdr); 4236 } 4237 4238 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4239 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4240 ISSET(sc->chip, URTWN_CHIP_92EU)) 4241 urtwn_r88e_fw_reset(sc); 4242 else 4243 urtwn_fw_reset(sc); 4244 } 4245 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4246 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4247 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4248 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4249 R92C_SYS_FUNC_EN_CPUEN); 4250 } 4251 4252 /* download enabled */ 4253 urtwn_write_1(sc, R92C_MCUFWDL, 4254 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4255 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4256 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4257 4258 /* Reset the FWDL checksum. */ 4259 urtwn_write_1(sc, R92C_MCUFWDL, 4260 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4261 4262 DELAY(50); 4263 /* download firmware */ 4264 for (page = 0; len > 0; page++) { 4265 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4266 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4267 if (error != 0) { 4268 aprint_error_dev(sc->sc_dev, 4269 "could not load firmware page %d\n", page); 4270 goto fail; 4271 } 4272 ptr += mlen; 4273 len -= mlen; 4274 } 4275 4276 /* download disable */ 4277 urtwn_write_1(sc, R92C_MCUFWDL, 4278 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4279 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4280 4281 /* Wait for checksum report. */ 4282 for (ntries = 0; ntries < 1000; ntries++) { 4283 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4284 break; 4285 DELAY(5); 4286 } 4287 if (ntries == 1000) { 4288 aprint_error_dev(sc->sc_dev, 4289 "timeout waiting for checksum report\n"); 4290 error = ETIMEDOUT; 4291 goto fail; 4292 } 4293 4294 /* Wait for firmware readiness. */ 4295 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4296 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4297 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4298 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4299 ISSET(sc->chip, URTWN_CHIP_92EU)) 4300 urtwn_r88e_fw_reset(sc); 4301 else 4302 urtwn_fw_reset(sc); 4303 for (ntries = 0; ntries < 6000; ntries++) { 4304 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4305 break; 4306 DELAY(5); 4307 } 4308 if (ntries == 6000) { 4309 aprint_error_dev(sc->sc_dev, 4310 "timeout waiting for firmware readiness\n"); 4311 error = ETIMEDOUT; 4312 goto fail; 4313 } 4314 fail: 4315 firmware_free(fw, fwlen); 4316 return error; 4317 } 4318 4319 static __inline int 4320 urtwn_dma_init(struct urtwn_softc *sc) 4321 { 4322 4323 return sc->sc_dma_init(sc); 4324 } 4325 4326 static int 4327 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4328 { 4329 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4330 uint32_t reg; 4331 int error; 4332 4333 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4334 4335 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4336 4337 /* Initialize LLT table. */ 4338 error = urtwn_llt_init(sc); 4339 if (error != 0) 4340 return error; 4341 4342 /* Get Tx queues to USB endpoints mapping. */ 4343 hashq = hasnq = haslq = 0; 4344 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4345 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping %#x\n", 4346 device_xname(sc->sc_dev), __func__, reg)); 4347 if (MS(reg, R92C_USB_EP_HQ) != 0) 4348 hashq = 1; 4349 if (MS(reg, R92C_USB_EP_NQ) != 0) 4350 hasnq = 1; 4351 if (MS(reg, R92C_USB_EP_LQ) != 0) 4352 haslq = 1; 4353 nqueues = hashq + hasnq + haslq; 4354 if (nqueues == 0) 4355 return EIO; 4356 /* Get the number of pages for each queue. */ 4357 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4358 /* The remaining pages are assigned to the high priority queue. */ 4359 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4360 4361 /* Set number of pages for normal priority queue. */ 4362 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4363 urtwn_write_4(sc, R92C_RQPN, 4364 /* Set number of pages for public queue. */ 4365 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4366 /* Set number of pages for high priority queue. */ 4367 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4368 /* Set number of pages for low priority queue. */ 4369 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4370 /* Load values. */ 4371 R92C_RQPN_LD); 4372 4373 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4374 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4375 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4376 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4377 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4378 4379 /* Set queue to USB pipe mapping. */ 4380 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4381 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4382 if (nqueues == 1) { 4383 if (hashq) { 4384 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4385 } else if (hasnq) { 4386 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4387 } else { 4388 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4389 } 4390 } else if (nqueues == 2) { 4391 /* All 2-endpoints configs have a high priority queue. */ 4392 if (!hashq) { 4393 return EIO; 4394 } 4395 if (hasnq) { 4396 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4397 } else { 4398 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4399 } 4400 } else { 4401 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4402 } 4403 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4404 4405 /* Set Tx/Rx transfer page boundary. */ 4406 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4407 4408 /* Set Tx/Rx transfer page size. */ 4409 urtwn_write_1(sc, R92C_PBP, 4410 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4411 return 0; 4412 } 4413 4414 static int 4415 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4416 { 4417 usb_interface_descriptor_t *id; 4418 uint32_t reg; 4419 int nqueues; 4420 int error; 4421 4422 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4423 4424 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4425 4426 /* Initialize LLT table. */ 4427 error = urtwn_llt_init(sc); 4428 if (error != 0) 4429 return error; 4430 4431 /* Get Tx queues to USB endpoints mapping. */ 4432 id = usbd_get_interface_descriptor(sc->sc_iface); 4433 nqueues = id->bNumEndpoints - 1; 4434 if (nqueues == 0) 4435 return EIO; 4436 4437 /* Set number of pages for normal priority queue. */ 4438 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4439 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4440 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4441 4442 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4443 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4444 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4445 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4446 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4447 4448 /* Set queue to USB pipe mapping. */ 4449 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4450 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4451 if (nqueues == 1) 4452 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4453 else if (nqueues == 2) 4454 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4455 else 4456 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4457 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4458 4459 /* Set Tx/Rx transfer page boundary. */ 4460 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4461 4462 /* Set Tx/Rx transfer page size. */ 4463 urtwn_write_1(sc, R92C_PBP, 4464 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4465 4466 return 0; 4467 } 4468 4469 static void 4470 urtwn_mac_init(struct urtwn_softc *sc) 4471 { 4472 size_t i; 4473 4474 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4475 4476 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4477 4478 /* Write MAC initialization values. */ 4479 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4480 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4481 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4482 rtl8188eu_mac[i].val); 4483 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4484 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4485 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4486 rtl8192eu_mac[i].val); 4487 } else { 4488 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4489 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4490 rtl8192cu_mac[i].val); 4491 } 4492 } 4493 4494 static void 4495 urtwn_bb_init(struct urtwn_softc *sc) 4496 { 4497 const struct rtwn_bb_prog *prog; 4498 uint32_t reg; 4499 uint8_t crystalcap; 4500 size_t i; 4501 4502 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4503 4504 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4505 4506 /* Enable BB and RF. */ 4507 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4508 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4509 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4510 R92C_SYS_FUNC_EN_DIO_RF); 4511 4512 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4513 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4514 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4515 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4516 } 4517 4518 urtwn_write_1(sc, R92C_RF_CTRL, 4519 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4520 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4521 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4522 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4523 4524 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4525 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4526 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4527 urtwn_write_1(sc, 0x15, 0xe9); 4528 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4529 } 4530 4531 /* Select BB programming based on board type. */ 4532 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4533 prog = &rtl8188eu_bb_prog; 4534 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4535 prog = &rtl8192eu_bb_prog; 4536 else if (!(sc->chip & URTWN_CHIP_92C)) { 4537 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4538 prog = &rtl8188ce_bb_prog; 4539 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4540 prog = &rtl8188ru_bb_prog; 4541 } else { 4542 prog = &rtl8188cu_bb_prog; 4543 } 4544 } else { 4545 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4546 prog = &rtl8192ce_bb_prog; 4547 } else { 4548 prog = &rtl8192cu_bb_prog; 4549 } 4550 } 4551 /* Write BB initialization values. */ 4552 for (i = 0; i < prog->count; i++) { 4553 /* additional delay depend on registers */ 4554 switch (prog->regs[i]) { 4555 case 0xfe: 4556 urtwn_delay_ms(sc, 50); 4557 break; 4558 case 0xfd: 4559 urtwn_delay_ms(sc, 5); 4560 break; 4561 case 0xfc: 4562 urtwn_delay_ms(sc, 1); 4563 break; 4564 case 0xfb: 4565 DELAY(50); 4566 break; 4567 case 0xfa: 4568 DELAY(5); 4569 break; 4570 case 0xf9: 4571 DELAY(1); 4572 break; 4573 } 4574 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4575 DELAY(1); 4576 } 4577 4578 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4579 /* 8192C 1T only configuration. */ 4580 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4581 reg = (reg & ~0x00000003) | 0x2; 4582 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4583 4584 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4585 reg = (reg & ~0x00300033) | 0x00200022; 4586 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4587 4588 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4589 reg = (reg & ~0xff000000) | (0x45 << 24); 4590 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4591 4592 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4593 reg = (reg & ~0x000000ff) | 0x23; 4594 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4595 4596 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4597 reg = (reg & ~0x00000030) | (1 << 4); 4598 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4599 4600 reg = urtwn_bb_read(sc, 0xe74); 4601 reg = (reg & ~0x0c000000) | (2 << 26); 4602 urtwn_bb_write(sc, 0xe74, reg); 4603 reg = urtwn_bb_read(sc, 0xe78); 4604 reg = (reg & ~0x0c000000) | (2 << 26); 4605 urtwn_bb_write(sc, 0xe78, reg); 4606 reg = urtwn_bb_read(sc, 0xe7c); 4607 reg = (reg & ~0x0c000000) | (2 << 26); 4608 urtwn_bb_write(sc, 0xe7c, reg); 4609 reg = urtwn_bb_read(sc, 0xe80); 4610 reg = (reg & ~0x0c000000) | (2 << 26); 4611 urtwn_bb_write(sc, 0xe80, reg); 4612 reg = urtwn_bb_read(sc, 0xe88); 4613 reg = (reg & ~0x0c000000) | (2 << 26); 4614 urtwn_bb_write(sc, 0xe88, reg); 4615 } 4616 4617 /* Write AGC values. */ 4618 for (i = 0; i < prog->agccount; i++) { 4619 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4620 DELAY(1); 4621 } 4622 4623 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4624 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4625 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4626 DELAY(1); 4627 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4628 DELAY(1); 4629 } 4630 4631 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4632 crystalcap = sc->r88e_rom[0xb9]; 4633 if (crystalcap == 0x00) 4634 crystalcap = 0x20; 4635 crystalcap &= 0x3f; 4636 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4637 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4638 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4639 crystalcap | crystalcap << 6)); 4640 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4641 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4642 crystalcap = sc->r88e_rom[0xb9]; 4643 if (crystalcap == 0xff) 4644 crystalcap = 0x20; 4645 crystalcap &= 0x3f; 4646 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4647 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4648 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4649 crystalcap | crystalcap << 6)); 4650 } else { 4651 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4652 R92C_HSSI_PARAM2_CCK_HIPWR) { 4653 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4654 } 4655 } 4656 } 4657 4658 static void 4659 urtwn_rf_init(struct urtwn_softc *sc) 4660 { 4661 const struct rtwn_rf_prog *prog; 4662 uint32_t reg, mask, saved; 4663 size_t i, j, idx; 4664 4665 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4666 4667 /* Select RF programming based on board type. */ 4668 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4669 prog = rtl8188eu_rf_prog; 4670 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4671 prog = rtl8192eu_rf_prog; 4672 else if (!(sc->chip & URTWN_CHIP_92C)) { 4673 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4674 prog = rtl8188ce_rf_prog; 4675 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4676 prog = rtl8188ru_rf_prog; 4677 } else { 4678 prog = rtl8188cu_rf_prog; 4679 } 4680 } else { 4681 prog = rtl8192ce_rf_prog; 4682 } 4683 4684 for (i = 0; i < sc->nrxchains; i++) { 4685 /* Save RF_ENV control type. */ 4686 idx = i / 2; 4687 mask = 0xffffU << ((i % 2) * 16); 4688 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4689 4690 /* Set RF_ENV enable. */ 4691 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4692 reg |= 0x100000; 4693 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4694 DELAY(50); 4695 4696 /* Set RF_ENV output high. */ 4697 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4698 reg |= 0x10; 4699 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4700 DELAY(50); 4701 4702 /* Set address and data lengths of RF registers. */ 4703 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4704 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4705 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4706 DELAY(50); 4707 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4708 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4709 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4710 DELAY(50); 4711 4712 /* Write RF initialization values for this chain. */ 4713 for (j = 0; j < prog[i].count; j++) { 4714 if (prog[i].regs[j] >= 0xf9 && 4715 prog[i].regs[j] <= 0xfe) { 4716 /* 4717 * These are fake RF registers offsets that 4718 * indicate a delay is required. 4719 */ 4720 urtwn_delay_ms(sc, 50); 4721 continue; 4722 } 4723 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4724 DELAY(5); 4725 } 4726 4727 /* Restore RF_ENV control type. */ 4728 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4729 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4730 } 4731 4732 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4733 URTWN_CHIP_UMC_A_CUT) { 4734 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4735 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4736 } 4737 4738 /* Cache RF register CHNLBW. */ 4739 for (i = 0; i < 2; i++) { 4740 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4741 } 4742 } 4743 4744 static void 4745 urtwn_cam_init(struct urtwn_softc *sc) 4746 { 4747 uint32_t content, command; 4748 uint8_t idx; 4749 size_t i; 4750 4751 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4752 4753 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4754 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4755 return; 4756 4757 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4758 content = (idx & 3) 4759 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4760 | R92C_CAM_VALID; 4761 4762 command = R92C_CAMCMD_POLLING 4763 | R92C_CAMCMD_WRITE 4764 | R92C_CAM_CTL0(idx); 4765 4766 urtwn_write_4(sc, R92C_CAMWRITE, content); 4767 urtwn_write_4(sc, R92C_CAMCMD, command); 4768 } 4769 4770 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4771 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4772 if (i == 0) { 4773 content = (idx & 3) 4774 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4775 | R92C_CAM_VALID; 4776 } else { 4777 content = 0; 4778 } 4779 4780 command = R92C_CAMCMD_POLLING 4781 | R92C_CAMCMD_WRITE 4782 | R92C_CAM_CTL0(idx) 4783 | i; 4784 4785 urtwn_write_4(sc, R92C_CAMWRITE, content); 4786 urtwn_write_4(sc, R92C_CAMCMD, command); 4787 } 4788 } 4789 4790 /* Invalidate all CAM entries. */ 4791 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4792 } 4793 4794 static void 4795 urtwn_pa_bias_init(struct urtwn_softc *sc) 4796 { 4797 uint8_t reg; 4798 size_t i; 4799 4800 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4801 4802 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4803 4804 for (i = 0; i < sc->nrxchains; i++) { 4805 if (sc->pa_setting & (1U << i)) 4806 continue; 4807 4808 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4809 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4810 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4811 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4812 } 4813 if (!(sc->pa_setting & 0x10)) { 4814 reg = urtwn_read_1(sc, 0x16); 4815 reg = (reg & ~0xf0) | 0x90; 4816 urtwn_write_1(sc, 0x16, reg); 4817 } 4818 } 4819 4820 static void 4821 urtwn_rxfilter_init(struct urtwn_softc *sc) 4822 { 4823 4824 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4825 4826 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4827 4828 /* Initialize Rx filter. */ 4829 /* TODO: use better filter for monitor mode. */ 4830 urtwn_write_4(sc, R92C_RCR, 4831 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4832 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4833 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4834 /* Accept all multicast frames. */ 4835 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4836 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4837 /* Accept all management frames. */ 4838 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4839 /* Reject all control frames. */ 4840 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4841 /* Accept all data frames. */ 4842 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4843 } 4844 4845 static void 4846 urtwn_edca_init(struct urtwn_softc *sc) 4847 { 4848 4849 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4850 4851 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4852 4853 /* set spec SIFS (used in NAV) */ 4854 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4855 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4856 4857 /* set SIFS CCK/OFDM */ 4858 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4859 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4860 4861 /* TXOP */ 4862 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4863 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4864 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4865 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4866 } 4867 4868 static void 4869 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4870 uint16_t power[URTWN_RIDX_COUNT]) 4871 { 4872 uint32_t reg; 4873 4874 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4875 __func__, chain)); 4876 4877 /* Write per-CCK rate Tx power. */ 4878 if (chain == 0) { 4879 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4880 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4881 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4882 4883 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4884 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4885 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4886 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4887 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4888 } else { 4889 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4890 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4891 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4892 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4893 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4894 4895 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4896 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4897 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4898 } 4899 /* Write per-OFDM rate Tx power. */ 4900 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4901 SM(R92C_TXAGC_RATE06, power[ 4]) | 4902 SM(R92C_TXAGC_RATE09, power[ 5]) | 4903 SM(R92C_TXAGC_RATE12, power[ 6]) | 4904 SM(R92C_TXAGC_RATE18, power[ 7])); 4905 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4906 SM(R92C_TXAGC_RATE24, power[ 8]) | 4907 SM(R92C_TXAGC_RATE36, power[ 9]) | 4908 SM(R92C_TXAGC_RATE48, power[10]) | 4909 SM(R92C_TXAGC_RATE54, power[11])); 4910 /* Write per-MCS Tx power. */ 4911 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4912 SM(R92C_TXAGC_MCS00, power[12]) | 4913 SM(R92C_TXAGC_MCS01, power[13]) | 4914 SM(R92C_TXAGC_MCS02, power[14]) | 4915 SM(R92C_TXAGC_MCS03, power[15])); 4916 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4917 SM(R92C_TXAGC_MCS04, power[16]) | 4918 SM(R92C_TXAGC_MCS05, power[17]) | 4919 SM(R92C_TXAGC_MCS06, power[18]) | 4920 SM(R92C_TXAGC_MCS07, power[19])); 4921 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4922 SM(R92C_TXAGC_MCS08, power[20]) | 4923 SM(R92C_TXAGC_MCS09, power[21]) | 4924 SM(R92C_TXAGC_MCS10, power[22]) | 4925 SM(R92C_TXAGC_MCS11, power[23])); 4926 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4927 SM(R92C_TXAGC_MCS12, power[24]) | 4928 SM(R92C_TXAGC_MCS13, power[25]) | 4929 SM(R92C_TXAGC_MCS14, power[26]) | 4930 SM(R92C_TXAGC_MCS15, power[27])); 4931 } 4932 4933 static void 4934 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4935 uint16_t power[URTWN_RIDX_COUNT]) 4936 { 4937 struct r92c_rom *rom = &sc->rom; 4938 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4939 const struct rtwn_txpwr *base; 4940 int ridx, group; 4941 4942 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4943 device_xname(sc->sc_dev), __func__, chain, chan)); 4944 4945 /* Determine channel group. */ 4946 if (chan <= 3) { 4947 group = 0; 4948 } else if (chan <= 9) { 4949 group = 1; 4950 } else { 4951 group = 2; 4952 } 4953 4954 /* Get original Tx power based on board type and RF chain. */ 4955 if (!(sc->chip & URTWN_CHIP_92C)) { 4956 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4957 base = &rtl8188ru_txagc[chain]; 4958 } else { 4959 base = &rtl8192cu_txagc[chain]; 4960 } 4961 } else { 4962 base = &rtl8192cu_txagc[chain]; 4963 } 4964 4965 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4966 if (sc->regulatory == 0) { 4967 for (ridx = 0; ridx <= 3; ridx++) { 4968 power[ridx] = base->pwr[0][ridx]; 4969 } 4970 } 4971 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4972 if (sc->regulatory == 3) { 4973 power[ridx] = base->pwr[0][ridx]; 4974 /* Apply vendor limits. */ 4975 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4976 maxpow = rom->ht40_max_pwr[group]; 4977 } else { 4978 maxpow = rom->ht20_max_pwr[group]; 4979 } 4980 maxpow = (maxpow >> (chain * 4)) & 0xf; 4981 if (power[ridx] > maxpow) { 4982 power[ridx] = maxpow; 4983 } 4984 } else if (sc->regulatory == 1) { 4985 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4986 power[ridx] = base->pwr[group][ridx]; 4987 } 4988 } else if (sc->regulatory != 2) { 4989 power[ridx] = base->pwr[0][ridx]; 4990 } 4991 } 4992 4993 /* Compute per-CCK rate Tx power. */ 4994 cckpow = rom->cck_tx_pwr[chain][group]; 4995 for (ridx = 0; ridx <= 3; ridx++) { 4996 power[ridx] += cckpow; 4997 if (power[ridx] > R92C_MAX_TX_PWR) { 4998 power[ridx] = R92C_MAX_TX_PWR; 4999 } 5000 } 5001 5002 htpow = rom->ht40_1s_tx_pwr[chain][group]; 5003 if (sc->ntxchains > 1) { 5004 /* Apply reduction for 2 spatial streams. */ 5005 diff = rom->ht40_2s_tx_pwr_diff[group]; 5006 diff = (diff >> (chain * 4)) & 0xf; 5007 htpow = (htpow > diff) ? htpow - diff : 0; 5008 } 5009 5010 /* Compute per-OFDM rate Tx power. */ 5011 diff = rom->ofdm_tx_pwr_diff[group]; 5012 diff = (diff >> (chain * 4)) & 0xf; 5013 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 5014 for (ridx = 4; ridx <= 11; ridx++) { 5015 power[ridx] += ofdmpow; 5016 if (power[ridx] > R92C_MAX_TX_PWR) { 5017 power[ridx] = R92C_MAX_TX_PWR; 5018 } 5019 } 5020 5021 /* Compute per-MCS Tx power. */ 5022 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 5023 diff = rom->ht20_tx_pwr_diff[group]; 5024 diff = (diff >> (chain * 4)) & 0xf; 5025 htpow += diff; /* HT40->HT20 correction. */ 5026 } 5027 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 5028 power[ridx] += htpow; 5029 if (power[ridx] > R92C_MAX_TX_PWR) { 5030 power[ridx] = R92C_MAX_TX_PWR; 5031 } 5032 } 5033 #ifdef URTWN_DEBUG 5034 if (urtwn_debug & DBG_RF) { 5035 /* Dump per-rate Tx power values. */ 5036 printf("%s: %s: Tx power for chain %zd:\n", 5037 device_xname(sc->sc_dev), __func__, chain); 5038 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 5039 printf("%s: %s: Rate %d = %u\n", 5040 device_xname(sc->sc_dev), __func__, ridx, 5041 power[ridx]); 5042 } 5043 } 5044 #endif 5045 } 5046 5047 void 5048 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 5049 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 5050 { 5051 uint16_t cckpow, ofdmpow, bw20pow, htpow; 5052 const struct rtwn_r88e_txpwr *base; 5053 int ridx, group; 5054 5055 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 5056 device_xname(sc->sc_dev), __func__, chain, chan)); 5057 5058 /* Determine channel group. */ 5059 if (chan <= 2) 5060 group = 0; 5061 else if (chan <= 5) 5062 group = 1; 5063 else if (chan <= 8) 5064 group = 2; 5065 else if (chan <= 11) 5066 group = 3; 5067 else if (chan <= 13) 5068 group = 4; 5069 else 5070 group = 5; 5071 5072 /* Get original Tx power based on board type and RF chain. */ 5073 base = &rtl8188eu_txagc[chain]; 5074 5075 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5076 if (sc->regulatory == 0) { 5077 for (ridx = 0; ridx <= 3; ridx++) 5078 power[ridx] = base->pwr[0][ridx]; 5079 } 5080 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5081 if (sc->regulatory == 3) 5082 power[ridx] = base->pwr[0][ridx]; 5083 else if (sc->regulatory == 1) { 5084 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5085 power[ridx] = base->pwr[group][ridx]; 5086 } else if (sc->regulatory != 2) 5087 power[ridx] = base->pwr[0][ridx]; 5088 } 5089 5090 /* Compute per-CCK rate Tx power. */ 5091 cckpow = sc->cck_tx_pwr[group]; 5092 for (ridx = 0; ridx <= 3; ridx++) { 5093 power[ridx] += cckpow; 5094 if (power[ridx] > R92C_MAX_TX_PWR) 5095 power[ridx] = R92C_MAX_TX_PWR; 5096 } 5097 5098 htpow = sc->ht40_tx_pwr[group]; 5099 5100 /* Compute per-OFDM rate Tx power. */ 5101 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5102 for (ridx = 4; ridx <= 11; ridx++) { 5103 power[ridx] += ofdmpow; 5104 if (power[ridx] > R92C_MAX_TX_PWR) 5105 power[ridx] = R92C_MAX_TX_PWR; 5106 } 5107 5108 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5109 for (ridx = 12; ridx <= 27; ridx++) { 5110 power[ridx] += bw20pow; 5111 if (power[ridx] > R92C_MAX_TX_PWR) 5112 power[ridx] = R92C_MAX_TX_PWR; 5113 } 5114 } 5115 5116 static void 5117 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5118 { 5119 uint16_t power[URTWN_RIDX_COUNT]; 5120 size_t i; 5121 5122 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5123 5124 for (i = 0; i < sc->ntxchains; i++) { 5125 /* Compute per-rate Tx power values. */ 5126 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5127 ISSET(sc->chip, URTWN_CHIP_92EU)) 5128 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5129 else 5130 urtwn_get_txpower(sc, i, chan, ht40m, power); 5131 /* Write per-rate Tx power values to hardware. */ 5132 urtwn_write_txpower(sc, i, power); 5133 } 5134 } 5135 5136 static void 5137 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5138 { 5139 struct ieee80211com *ic = &sc->sc_ic; 5140 u_int chan; 5141 size_t i; 5142 5143 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5144 5145 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5146 __func__, chan)); 5147 5148 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5149 5150 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5151 chan += 2; 5152 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5153 chan -= 2; 5154 } 5155 5156 /* Set Tx power for this new channel. */ 5157 urtwn_set_txpower(sc, chan, ht40m); 5158 5159 for (i = 0; i < sc->nrxchains; i++) { 5160 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5161 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5162 } 5163 5164 if (ht40m) { 5165 /* Is secondary channel below or above primary? */ 5166 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5167 uint32_t reg; 5168 5169 urtwn_write_1(sc, R92C_BWOPMODE, 5170 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5171 5172 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5173 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5174 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5175 5176 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5177 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5178 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5179 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5180 5181 /* Set CCK side band. */ 5182 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5183 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5184 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5185 5186 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5187 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5188 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5189 5190 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5191 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5192 ~R92C_FPGA0_ANAPARAM2_CBW20); 5193 5194 reg = urtwn_bb_read(sc, 0x818); 5195 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5196 urtwn_bb_write(sc, 0x818, reg); 5197 5198 /* Select 40MHz bandwidth. */ 5199 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5200 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5201 } else { 5202 urtwn_write_1(sc, R92C_BWOPMODE, 5203 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5204 5205 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5206 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5207 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5208 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5209 5210 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5211 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5212 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5213 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5214 R92C_FPGA0_ANAPARAM2_CBW20); 5215 } 5216 5217 /* Select 20MHz bandwidth. */ 5218 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5219 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5220 (ISSET(sc->chip, URTWN_CHIP_88E) || 5221 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5222 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5223 } 5224 } 5225 5226 static void 5227 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5228 { 5229 5230 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5231 __func__, inited)); 5232 5233 uint32_t addaBackup[16], iqkBackup[4], piMode; 5234 5235 #ifdef notyet 5236 uint32_t odfm0_agccore_regs[3]; 5237 uint32_t ant_regs[3]; 5238 uint32_t rf_regs[8]; 5239 #endif 5240 uint32_t reg0, reg1, reg2; 5241 int i, attempt; 5242 5243 #ifdef notyet 5244 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5245 R92E_STBC_SETTING + 2)); 5246 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5247 /* Save AGCCORE regs. */ 5248 for (i = 0; i < sc->nrxchains; i++) { 5249 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5250 R92C_OFDM0_AGCCORE1(i)); 5251 } 5252 #endif 5253 /* Save BB regs. */ 5254 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5255 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5256 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5257 5258 /* Save adda regs to be restored when finished. */ 5259 for (i = 0; i < __arraycount(addaReg); i++) 5260 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5261 /* Save mac regs. */ 5262 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5263 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5264 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5265 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5266 5267 #ifdef notyet 5268 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5269 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5270 5271 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5272 for (i = 0; i < sc->nrxchains; i++) 5273 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5274 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5275 #endif 5276 5277 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5278 R92C_HSSI_PARAM1_PI); 5279 if (piMode == 0) { 5280 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5281 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5282 R92C_HSSI_PARAM1_PI); 5283 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5284 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5285 R92C_HSSI_PARAM1_PI); 5286 } 5287 5288 attempt = 1; 5289 5290 next_attempt: 5291 5292 /* Set mac regs for calibration. */ 5293 for (i = 0; i < __arraycount(addaReg); i++) { 5294 urtwn_bb_write(sc, addaReg[i], 5295 addaReg[__arraycount(addaReg) - 1]); 5296 } 5297 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5298 R92C_CCK0_AFESETTING)); 5299 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5300 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5301 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5302 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5303 5304 if (sc->ntxchains > 1) 5305 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5306 5307 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5308 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5309 ~R92C_BCN_CTRL_EN_BCN)); 5310 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5311 ~R92C_BCN_CTRL_EN_BCN)); 5312 5313 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5314 ~R92C_GPIO_MUXCFG_ENBT)); 5315 5316 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5317 5318 if (sc->ntxchains > 1) 5319 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5320 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5321 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5322 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5323 5324 /* Restore BB regs. */ 5325 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5326 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5327 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5328 5329 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5330 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5331 if (sc->nrxchains > 1) 5332 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5333 5334 if (attempt-- > 0) 5335 goto next_attempt; 5336 5337 /* Restore mode. */ 5338 if (piMode == 0) { 5339 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5340 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5341 ~R92C_HSSI_PARAM1_PI); 5342 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5343 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5344 ~R92C_HSSI_PARAM1_PI); 5345 } 5346 5347 #ifdef notyet 5348 for (i = 0; i < sc->nrxchains; i++) { 5349 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5350 odfm0_agccore_regs[i]); 5351 } 5352 #endif 5353 5354 /* Restore adda regs. */ 5355 for (i = 0; i < __arraycount(addaReg); i++) 5356 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5357 /* Restore mac regs. */ 5358 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5359 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5360 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5361 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5362 5363 #ifdef notyet 5364 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5365 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5366 5367 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5368 for (i = 0; i < sc->nrxchains; i++) 5369 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5370 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5371 #endif 5372 } 5373 5374 static void 5375 urtwn_lc_calib(struct urtwn_softc *sc) 5376 { 5377 uint32_t rf_ac[2]; 5378 uint8_t txmode; 5379 size_t i; 5380 5381 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5382 5383 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5384 5385 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5386 if ((txmode & 0x70) != 0) { 5387 /* Disable all continuous Tx. */ 5388 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5389 5390 /* Set RF mode to standby mode. */ 5391 for (i = 0; i < sc->nrxchains; i++) { 5392 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5393 urtwn_rf_write(sc, i, R92C_RF_AC, 5394 RW(rf_ac[i], R92C_RF_AC_MODE, 5395 R92C_RF_AC_MODE_STANDBY)); 5396 } 5397 } else { 5398 /* Block all Tx queues. */ 5399 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5400 } 5401 /* Start calibration. */ 5402 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5403 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5404 5405 /* Give calibration the time to complete. */ 5406 urtwn_delay_ms(sc, 100); 5407 5408 /* Restore configuration. */ 5409 if ((txmode & 0x70) != 0) { 5410 /* Restore Tx mode. */ 5411 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5412 /* Restore RF mode. */ 5413 for (i = 0; i < sc->nrxchains; i++) { 5414 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5415 } 5416 } else { 5417 /* Unblock all Tx queues. */ 5418 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5419 } 5420 } 5421 5422 static void 5423 urtwn_temp_calib(struct urtwn_softc *sc) 5424 { 5425 int temp, t_meter_reg; 5426 5427 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5428 5429 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5430 5431 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5432 t_meter_reg = R92C_RF_T_METER; 5433 else 5434 t_meter_reg = R92E_RF_T_METER; 5435 5436 if (sc->thcal_state == 0) { 5437 /* Start measuring temperature. */ 5438 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5439 device_xname(sc->sc_dev), __func__)); 5440 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5441 sc->thcal_state = 1; 5442 return; 5443 } 5444 sc->thcal_state = 0; 5445 5446 /* Read measured temperature. */ 5447 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5448 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5449 __func__, temp)); 5450 if (temp == 0) /* Read failed, skip. */ 5451 return; 5452 5453 /* 5454 * Redo LC calibration if temperature changed significantly since 5455 * last calibration. 5456 */ 5457 if (sc->thcal_lctemp == 0) { 5458 /* First LC calibration is performed in urtwn_init(). */ 5459 sc->thcal_lctemp = temp; 5460 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5461 DPRINTFN(DBG_RF, 5462 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5463 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5464 temp)); 5465 urtwn_lc_calib(sc); 5466 /* Record temperature of last LC calibration. */ 5467 sc->thcal_lctemp = temp; 5468 } 5469 } 5470 5471 static int 5472 urtwn_init(struct ifnet *ifp) 5473 { 5474 struct ieee80211vap *vap = ifp->if_softc; 5475 struct ieee80211com *ic = vap->iv_ic; 5476 struct urtwn_softc *sc = ic->ic_softc; 5477 struct urtwn_rx_data *data; 5478 uint32_t reg; 5479 size_t i; 5480 int error; 5481 5482 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5483 5484 urtwn_stop(ifp, 0); 5485 5486 mutex_enter(&sc->sc_write_mtx); 5487 5488 mutex_enter(&sc->sc_task_mtx); 5489 /* Init host async commands ring. */ 5490 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5491 mutex_exit(&sc->sc_task_mtx); 5492 5493 mutex_enter(&sc->sc_fwcmd_mtx); 5494 /* Init firmware commands ring. */ 5495 sc->fwcur = 0; 5496 mutex_exit(&sc->sc_fwcmd_mtx); 5497 5498 /* Allocate Tx/Rx buffers. */ 5499 error = urtwn_alloc_rx_list(sc); 5500 if (error != 0) { 5501 aprint_error_dev(sc->sc_dev, 5502 "could not allocate Rx buffers\n"); 5503 goto fail; 5504 } 5505 error = urtwn_alloc_tx_list(sc); 5506 if (error != 0) { 5507 aprint_error_dev(sc->sc_dev, 5508 "could not allocate Tx buffers\n"); 5509 goto fail; 5510 } 5511 5512 /* Power on adapter. */ 5513 error = urtwn_power_on(sc); 5514 if (error != 0) 5515 goto fail; 5516 5517 /* Initialize DMA. */ 5518 error = urtwn_dma_init(sc); 5519 if (error != 0) 5520 goto fail; 5521 5522 /* Set info size in Rx descriptors (in 64-bit words). */ 5523 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5524 5525 /* Init interrupts. */ 5526 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5527 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5528 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5529 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5530 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5531 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5532 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5533 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5534 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5535 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5536 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5537 } 5538 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5539 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5540 } else { 5541 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5542 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5543 } 5544 5545 /* Set MAC address. */ 5546 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5547 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5548 5549 /* Set initial network type. */ 5550 reg = urtwn_read_4(sc, R92C_CR); 5551 switch (ic->ic_opmode) { 5552 case IEEE80211_M_STA: 5553 default: 5554 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5555 break; 5556 5557 case IEEE80211_M_IBSS: 5558 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5559 break; 5560 } 5561 urtwn_write_4(sc, R92C_CR, reg); 5562 5563 /* Set response rate */ 5564 reg = urtwn_read_4(sc, R92C_RRSR); 5565 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5566 urtwn_write_4(sc, R92C_RRSR, reg); 5567 5568 /* SIFS (used in NAV) */ 5569 urtwn_write_2(sc, R92C_SPEC_SIFS, 5570 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5571 5572 /* Set short/long retry limits. */ 5573 urtwn_write_2(sc, R92C_RL, 5574 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5575 5576 /* Initialize EDCA parameters. */ 5577 urtwn_edca_init(sc); 5578 5579 /* Setup rate fallback. */ 5580 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5581 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5582 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5583 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5584 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5585 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5586 } 5587 5588 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5589 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5590 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5591 /* Set ACK timeout. */ 5592 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5593 5594 /* Setup USB aggregation. */ 5595 /* Tx */ 5596 reg = urtwn_read_4(sc, R92C_TDECTRL); 5597 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5598 urtwn_write_4(sc, R92C_TDECTRL, reg); 5599 /* Rx */ 5600 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5601 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5602 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5603 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5604 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5605 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5606 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5607 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5608 ISSET(sc->chip, URTWN_CHIP_92EU)) 5609 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5610 else 5611 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5612 5613 /* Initialize beacon parameters. */ 5614 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5615 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5616 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5617 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5618 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5619 5620 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5621 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5622 /* Setup AMPDU aggregation. */ 5623 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5624 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5625 urtwn_write_2(sc, 0x4ca, 0x0708); 5626 5627 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5628 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5629 } 5630 5631 /* Load 8051 microcode. */ 5632 error = urtwn_load_firmware(sc); 5633 if (error != 0) 5634 goto fail; 5635 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5636 5637 /* Initialize MAC/BB/RF blocks. */ 5638 /* 5639 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5640 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5641 * XXX: This setting should be removed from rtl8192cu_mac[]. 5642 */ 5643 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5644 urtwn_rxfilter_init(sc); // reset R92C_RCR 5645 urtwn_bb_init(sc); 5646 urtwn_rf_init(sc); 5647 5648 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5649 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5650 urtwn_write_2(sc, R92C_CR, 5651 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5652 R92C_CR_MACRXEN); 5653 } 5654 5655 /* Turn CCK and OFDM blocks on. */ 5656 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5657 reg |= R92C_RFMOD_CCK_EN; 5658 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5659 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5660 reg |= R92C_RFMOD_OFDM_EN; 5661 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5662 5663 /* Clear per-station keys table. */ 5664 urtwn_cam_init(sc); 5665 5666 /* Enable hardware sequence numbering. */ 5667 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5668 5669 /* Perform LO and IQ calibrations. */ 5670 urtwn_iq_calib(sc, sc->iqk_inited); 5671 sc->iqk_inited = true; 5672 5673 /* Perform LC calibration. */ 5674 urtwn_lc_calib(sc); 5675 5676 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5677 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5678 /* Fix USB interference issue. */ 5679 urtwn_write_1(sc, 0xfe40, 0xe0); 5680 urtwn_write_1(sc, 0xfe41, 0x8d); 5681 urtwn_write_1(sc, 0xfe42, 0x80); 5682 urtwn_write_4(sc, 0x20c, 0xfd0320); 5683 5684 urtwn_pa_bias_init(sc); 5685 } 5686 5687 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5688 !(sc->chip & URTWN_CHIP_92EU)) { 5689 /* 1T1R */ 5690 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5691 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5692 } 5693 5694 /* Initialize GPIO setting. */ 5695 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5696 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5697 5698 /* Fix for lower temperature. */ 5699 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5700 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5701 urtwn_write_1(sc, 0x15, 0xe9); 5702 5703 /* Set default channel. */ 5704 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5705 5706 /* Queue Rx xfers. */ 5707 for (size_t j = 0; j < sc->rx_npipe; j++) { 5708 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5709 data = &sc->rx_data[j][i]; 5710 usbd_setup_xfer(data->xfer, data, data->buf, 5711 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5712 urtwn_rxeof); 5713 error = usbd_transfer(data->xfer); 5714 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5715 error != USBD_IN_PROGRESS)) 5716 goto fail; 5717 } 5718 } 5719 5720 /* We're ready to go. */ 5721 ifp->if_flags &= ~IFF_OACTIVE; 5722 ifp->if_flags |= IFF_RUNNING; 5723 sc->sc_running = true; 5724 5725 mutex_exit(&sc->sc_write_mtx); 5726 5727 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5728 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5729 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5730 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5731 urtwn_wait_async(sc); 5732 5733 /* Init the rest of the 802.11 stuff */ 5734 ieee80211_init(ifp); 5735 5736 return 0; 5737 5738 fail: 5739 mutex_exit(&sc->sc_write_mtx); 5740 5741 urtwn_stop(ifp, 1); 5742 return error; 5743 } 5744 5745 static void 5746 urtwn_stop(struct ifnet *ifp, int disable) 5747 { 5748 struct ieee80211vap *vap = ifp->if_softc; 5749 struct ieee80211com *ic = vap->iv_ic; 5750 struct urtwn_softc *sc = ic->ic_softc; 5751 size_t i; 5752 int s; 5753 5754 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5755 5756 s = splusb(); 5757 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5758 urtwn_wait_async(sc); 5759 splx(s); 5760 5761 sc->tx_timer = 0; 5762 ifp->if_timer = 0; 5763 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5764 5765 callout_stop(&sc->sc_scan_to); 5766 callout_stop(&sc->sc_calib_to); 5767 5768 /* Abort Tx. */ 5769 for (i = 0; i < sc->tx_npipe; i++) { 5770 if (sc->tx_pipe[i] != NULL) 5771 usbd_abort_pipe(sc->tx_pipe[i]); 5772 } 5773 5774 /* Stop Rx pipe. */ 5775 for (i = 0; i < sc->rx_npipe; i++) { 5776 if (sc->rx_pipe[i] != NULL) 5777 usbd_abort_pipe(sc->rx_pipe[i]); 5778 } 5779 5780 /* Free Tx/Rx buffers. */ 5781 urtwn_free_tx_list(sc); 5782 urtwn_free_rx_list(sc); 5783 5784 sc->sc_running = false; 5785 if (disable) 5786 urtwn_chip_stop(sc); 5787 } 5788 5789 static int 5790 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5791 { 5792 struct ifnet *ifp = vap->iv_ifp; 5793 struct urtwn_softc *sc = ifp->if_softc; 5794 struct ieee80211com *ic = &sc->sc_ic; 5795 5796 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5797 return ENETRESET; 5798 5799 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5800 5801 return 0; 5802 } 5803 5804 static void 5805 urtwn_chip_stop(struct urtwn_softc *sc) 5806 { 5807 uint32_t reg; 5808 bool disabled = true; 5809 5810 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5811 5812 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5813 ISSET(sc->chip, URTWN_CHIP_92EU)) 5814 return; 5815 5816 mutex_enter(&sc->sc_write_mtx); 5817 5818 /* 5819 * RF Off Sequence 5820 */ 5821 /* Pause MAC TX queue */ 5822 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5823 5824 /* Disable RF */ 5825 urtwn_rf_write(sc, 0, 0, 0); 5826 5827 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5828 5829 /* Reset BB state machine */ 5830 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5831 R92C_SYS_FUNC_EN_USBD | 5832 R92C_SYS_FUNC_EN_USBA | 5833 R92C_SYS_FUNC_EN_BB_GLB_RST); 5834 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5835 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5836 5837 /* 5838 * Reset digital sequence 5839 */ 5840 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5841 /* Reset MCU ready status */ 5842 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5843 /* If firmware in ram code, do reset */ 5844 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5845 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5846 ISSET(sc->chip, URTWN_CHIP_92EU)) 5847 urtwn_r88e_fw_reset(sc); 5848 else 5849 urtwn_fw_reset(sc); 5850 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5851 } 5852 } 5853 5854 /* Reset MAC and Enable 8051 */ 5855 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5856 5857 /* Reset MCU ready status */ 5858 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5859 5860 if (disabled) { 5861 /* Disable MAC clock */ 5862 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5863 /* Disable AFE PLL */ 5864 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5865 /* Gated AFE DIG_CLOCK */ 5866 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5867 /* Isolated digital to PON */ 5868 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5869 } 5870 5871 /* 5872 * Pull GPIO PIN to balance level and LED control 5873 */ 5874 /* 1. Disable GPIO[7:0] */ 5875 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5876 5877 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5878 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5879 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5880 5881 /* Disable GPIO[10:8] */ 5882 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5883 5884 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5885 reg |= (((reg & 0x000f) << 4) | 0x0780); 5886 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5887 5888 /* Disable LED0 & 1 */ 5889 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5890 5891 /* 5892 * Reset digital sequence 5893 */ 5894 if (disabled) { 5895 /* Disable ELDR clock */ 5896 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5897 /* Isolated ELDR to PON */ 5898 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5899 } 5900 5901 /* 5902 * Disable analog sequence 5903 */ 5904 if (disabled) { 5905 /* Disable A15 power */ 5906 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5907 /* Disable digital core power */ 5908 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5909 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5910 ~R92C_LDOV12D_CTRL_LDV12_EN); 5911 } 5912 5913 /* Enter PFM mode */ 5914 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5915 5916 /* Set USB suspend */ 5917 urtwn_write_2(sc, R92C_APS_FSMCO, 5918 R92C_APS_FSMCO_APDM_HOST | 5919 R92C_APS_FSMCO_AFSM_HSUS | 5920 R92C_APS_FSMCO_PFM_ALDN); 5921 5922 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5923 5924 mutex_exit(&sc->sc_write_mtx); 5925 } 5926 5927 static void 5928 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5929 { 5930 if (sc->sc_running == false) 5931 DELAY(ms * 1000); 5932 else 5933 usbd_delay_ms(sc->sc_udev, ms); 5934 } 5935 5936 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5937 5938 #ifdef _MODULE 5939 #include "ioconf.c" 5940 #endif 5941 5942 static int 5943 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5944 { 5945 int error = 0; 5946 5947 switch (cmd) { 5948 case MODULE_CMD_INIT: 5949 #ifdef _MODULE 5950 error = config_init_component(cfdriver_ioconf_urtwn, 5951 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5952 #endif 5953 return error; 5954 case MODULE_CMD_FINI: 5955 #ifdef _MODULE 5956 error = config_fini_component(cfdriver_ioconf_urtwn, 5957 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5958 #endif 5959 return error; 5960 default: 5961 return ENOTTY; 5962 } 5963 } 5964
Indexes created Fri Oct 03 02:09:57 GMT 2025