if_urtwn.c revision 1.59.2.2
1 /* $NetBSD: if_urtwn.c,v 1.59.2.2 2018/07/16 20:11:11 phil Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.2 2018/07/16 20:11:11 phil Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/kmem.h> 41 #include <sys/socket.h> 42 #include <sys/systm.h> 43 #include <sys/module.h> 44 #include <sys/conf.h> 45 #include <sys/device.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/usb/if_urtwnreg.h> 78 #include <dev/usb/if_urtwnvar.h> 79 #include <dev/usb/if_urtwn_data.h> 80 81 /* 82 * The sc_write_mtx locking is to prevent sequences of writes from 83 * being intermingled with each other. I don't know if this is really 84 * needed. I have added it just to be on the safe side. 85 */ 86 87 #ifdef URTWN_DEBUG 88 #define DBG_INIT __BIT(0) 89 #define DBG_FN __BIT(1) 90 #define DBG_TX __BIT(2) 91 #define DBG_RX __BIT(3) 92 #define DBG_STM __BIT(4) 93 #define DBG_RF __BIT(5) 94 #define DBG_REG __BIT(6) 95 #define DBG_ALL 0xffffffffU 96 /* NNN Reset urtwn_debug to 0 when done debugging. */ 97 u_int urtwn_debug = DBG_INIT|DBG_FN|DBG_STM; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 196 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 197 198 /* URTWN_RTL8192EU */ 199 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 200 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 201 }; 202 #undef URTWN_DEV 203 #undef URTWN_RTL8188E_DEV 204 #undef URTWN_RTL8192EU_DEV 205 206 static int urtwn_match(device_t, cfdata_t, void *); 207 static void urtwn_attach(device_t, device_t, void *); 208 static int urtwn_detach(device_t, int); 209 static int urtwn_activate(device_t, enum devact); 210 211 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 212 urtwn_attach, urtwn_detach, urtwn_activate); 213 214 static int urtwn_open_pipes(struct urtwn_softc *); 215 static void urtwn_close_pipes(struct urtwn_softc *); 216 static int urtwn_alloc_rx_list(struct urtwn_softc *); 217 static void urtwn_free_rx_list(struct urtwn_softc *); 218 static int urtwn_alloc_tx_list(struct urtwn_softc *); 219 static void urtwn_free_tx_list(struct urtwn_softc *); 220 static void urtwn_task(void *); 221 static void urtwn_do_async(struct urtwn_softc *, 222 void (*)(struct urtwn_softc *, void *), void *, int); 223 static void urtwn_wait_async(struct urtwn_softc *); 224 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 225 int); 226 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 227 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 228 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 229 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 230 int); 231 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 232 int); 233 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 234 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 235 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 236 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 237 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 238 uint32_t); 239 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 240 uint32_t); 241 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 242 uint32_t); 243 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 244 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 245 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 246 static void urtwn_efuse_read(struct urtwn_softc *); 247 static void urtwn_efuse_switch_power(struct urtwn_softc *); 248 static int urtwn_read_chipid(struct urtwn_softc *); 249 #ifdef URTWN_DEBUG 250 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 251 #endif 252 static void urtwn_read_rom(struct urtwn_softc *); 253 static void urtwn_r88e_read_rom(struct urtwn_softc *); 254 static int urtwn_media_change(struct ifnet *); 255 static int urtwn_ra_init(struct urtwn_softc *); 256 static int urtwn_get_nettype(struct urtwn_softc *); 257 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 258 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 259 static void urtwn_set_led(struct urtwn_softc *, int, int); 260 static void urtwn_calib_to(void *); 261 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 262 static void urtwn_next_scan(void *); 263 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 264 int); 265 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 266 static int urtwn_wme_update(struct ieee80211com *); 267 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 268 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 269 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 270 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 271 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 272 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 273 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 274 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 275 struct ieee80211_node *, struct urtwn_tx_data *); 276 static struct urtwn_tx_data * 277 urtwn_get_tx_data(struct urtwn_softc *, size_t); 278 static void urtwn_start(struct ifnet *); 279 static void urtwn_watchdog(struct ifnet *); 280 static int urtwn_r92c_power_on(struct urtwn_softc *); 281 static int urtwn_r92e_power_on(struct urtwn_softc *); 282 static int urtwn_r88e_power_on(struct urtwn_softc *); 283 static int urtwn_llt_init(struct urtwn_softc *); 284 static void urtwn_fw_reset(struct urtwn_softc *); 285 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 286 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 287 static int urtwn_load_firmware(struct urtwn_softc *); 288 static int urtwn_r92c_dma_init(struct urtwn_softc *); 289 static int urtwn_r88e_dma_init(struct urtwn_softc *); 290 static void urtwn_mac_init(struct urtwn_softc *); 291 static void urtwn_bb_init(struct urtwn_softc *); 292 static void urtwn_rf_init(struct urtwn_softc *); 293 static void urtwn_cam_init(struct urtwn_softc *); 294 static void urtwn_pa_bias_init(struct urtwn_softc *); 295 static void urtwn_rxfilter_init(struct urtwn_softc *); 296 static void urtwn_edca_init(struct urtwn_softc *); 297 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 298 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 299 uint16_t[]); 300 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 301 u_int, uint16_t[]); 302 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 303 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 304 u_int); 305 static void urtwn_iq_calib(struct urtwn_softc *, bool); 306 static void urtwn_lc_calib(struct urtwn_softc *); 307 static void urtwn_temp_calib(struct urtwn_softc *); 308 static int urtwn_init(struct ifnet *); 309 static void urtwn_stop(struct ifnet *, int); 310 static int urtwn_reset(struct ieee80211vap *, u_long); 311 static void urtwn_chip_stop(struct urtwn_softc *); 312 static void urtwn_newassoc(struct ieee80211_node *, int); 313 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 314 static struct ieee80211vap * 315 urtwn_vap_create(struct ieee80211com *, 316 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 317 const uint8_t [IEEE80211_ADDR_LEN], 318 const uint8_t [IEEE80211_ADDR_LEN]); 319 static void urtwn_vap_delete(struct ieee80211vap *); 320 static int urtwn_ioctl(struct ifnet *, u_long, void *); 321 322 /* Aliases. */ 323 #define urtwn_bb_write urtwn_write_4 324 #define urtwn_bb_read urtwn_read_4 325 326 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 327 328 static const uint16_t addaReg[] = { 329 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 330 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 331 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 332 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 333 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 334 }; 335 336 static int 337 urtwn_match(device_t parent, cfdata_t match, void *aux) 338 { 339 struct usb_attach_arg *uaa = aux; 340 341 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 342 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 343 } 344 345 static void 346 urtwn_attach(device_t parent, device_t self, void *aux) 347 { 348 struct urtwn_softc *sc = device_private(self); 349 struct ieee80211com *ic = &sc->sc_ic; 350 struct usb_attach_arg *uaa = aux; 351 char *devinfop; 352 const struct urtwn_dev *dev; 353 usb_device_request_t req; 354 size_t i; 355 int error; 356 357 sc->sc_dev = self; 358 sc->sc_udev = uaa->uaa_device; 359 360 sc->chip = 0; 361 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 362 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 363 SET(sc->chip, URTWN_CHIP_88E); 364 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 365 SET(sc->chip, URTWN_CHIP_92EU); 366 367 aprint_naive("\n"); 368 aprint_normal("\n"); 369 370 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 371 372 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 373 aprint_normal_dev(self, "%s\n", devinfop); 374 usbd_devinfo_free(devinfop); 375 376 req.bmRequestType = UT_WRITE_DEVICE; 377 req.bRequest = UR_SET_FEATURE; 378 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 379 USETW(req.wIndex, UHF_PORT_SUSPEND); 380 USETW(req.wLength, 0); 381 382 (void) usbd_do_request(sc->sc_udev, &req, 0); 383 384 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 385 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 386 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 387 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 388 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 389 390 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 391 392 /* NNN make these callouts use a vap ... in vap create??? */ 393 callout_init(&sc->sc_scan_to, 0); 394 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 395 callout_init(&sc->sc_calib_to, 0); 396 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 397 398 error = usbd_set_config_no(sc->sc_udev, 1, 0); 399 if (error != 0) { 400 aprint_error_dev(self, "failed to set configuration" 401 ", err=%s\n", usbd_errstr(error)); 402 goto fail; 403 } 404 405 /* Get the first interface handle. */ 406 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 407 if (error != 0) { 408 aprint_error_dev(self, "could not get interface handle\n"); 409 goto fail; 410 } 411 412 error = urtwn_read_chipid(sc); 413 if (error != 0) { 414 aprint_error_dev(self, "unsupported test chip\n"); 415 goto fail; 416 } 417 418 /* Determine number of Tx/Rx chains. */ 419 if (sc->chip & URTWN_CHIP_92C) { 420 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 421 sc->nrxchains = 2; 422 } else if (sc->chip & URTWN_CHIP_92EU) { 423 sc->ntxchains = 2; 424 sc->nrxchains = 2; 425 } else { 426 sc->ntxchains = 1; 427 sc->nrxchains = 1; 428 } 429 430 if (ISSET(sc->chip, URTWN_CHIP_88E) || 431 ISSET(sc->chip, URTWN_CHIP_92EU)) 432 urtwn_r88e_read_rom(sc); 433 else 434 urtwn_read_rom(sc); 435 436 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 437 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 438 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 439 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 440 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 441 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 442 "8188CUS", sc->ntxchains, sc->nrxchains, 443 ether_sprintf(ic->ic_macaddr)); 444 445 error = urtwn_open_pipes(sc); 446 if (error != 0) { 447 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 448 goto fail; 449 } 450 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 451 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 452 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 453 454 /* 455 * Setup the 802.11 device. 456 */ 457 ic->ic_softc = sc; 458 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 459 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 460 461 /* Set device capabilities. */ 462 ic->ic_caps = 463 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 464 IEEE80211_C_IBSS | /* IBSS mode supported */ 465 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 466 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 467 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 468 IEEE80211_C_WME | /* 802.11e */ 469 IEEE80211_C_WPA; /* 802.11i */ 470 471 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 472 473 /* Set supported .11b and .11g channels (1 through 14). */ 474 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 475 for (i = 0; i < 14; i++) { 476 ic->ic_channels[i].ic_freq = 477 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 478 ic->ic_channels[i].ic_flags = 479 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 480 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 481 } 482 483 printf ("eurtwn: Calling ieee80211_ifattach()\n"); 484 485 ieee80211_ifattach(ic); 486 487 printf ("urtwn: Returned from ieee80211_ifattach().\n"); 488 489 /* override default methods NNN Need a lot more here!!! */ 490 ic->ic_newassoc = urtwn_newassoc; 491 ic->ic_wme.wme_update = urtwn_wme_update; 492 ic->ic_vap_create = urtwn_vap_create; 493 ic->ic_vap_delete = urtwn_vap_delete; 494 495 /* Shouldn't do it, but call vap_create??? */ 496 uint8_t bssid[IEEE80211_ADDR_LEN] = {0}; 497 498 struct ieee80211vap *vap = 499 urtwn_vap_create(ic, device_xname(sc->sc_dev), 500 device_unit(sc->sc_dev), IEEE80211_M_IBSS, 501 IEEE80211_CLONE_MACADDR, bssid, ic->ic_macaddr); 502 503 if (vap == NULL) { 504 /* Didn't work ... now what! */ 505 printf ("vap_create didn't work ...\n"); 506 ieee80211_ifdetach(ic); 507 goto fail; 508 } 509 510 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 511 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 512 &sc->sc_drvbpf); 513 514 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 515 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 516 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 517 518 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 519 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 520 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 521 522 ieee80211_announce(ic); 523 524 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 525 526 if (!pmf_device_register(self, NULL, NULL)) 527 aprint_error_dev(self, "couldn't establish power handler\n"); 528 529 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 530 printf ("urtwn: Finished attach.\n"); 531 return; 532 533 fail: 534 sc->sc_dying = 1; 535 aprint_error_dev(self, "attach failed\n"); 536 } 537 538 static int 539 urtwn_detach(device_t self, int flags) 540 { 541 struct urtwn_softc *sc = device_private(self); 542 int s; 543 544 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 545 546 pmf_device_deregister(self); 547 548 s = splusb(); 549 550 sc->sc_dying = 1; 551 552 callout_stop(&sc->sc_scan_to); 553 callout_stop(&sc->sc_calib_to); 554 555 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 556 usb_rem_task(sc->sc_udev, &sc->sc_task); 557 558 ieee80211_ifdetach(&sc->sc_ic); 559 560 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 561 urtwn_close_pipes(sc); 562 } 563 564 splx(s); 565 566 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 567 568 callout_destroy(&sc->sc_scan_to); 569 callout_destroy(&sc->sc_calib_to); 570 571 mutex_destroy(&sc->sc_write_mtx); 572 mutex_destroy(&sc->sc_fwcmd_mtx); 573 mutex_destroy(&sc->sc_tx_mtx); 574 mutex_destroy(&sc->sc_rx_mtx); 575 mutex_destroy(&sc->sc_task_mtx); 576 577 return 0; 578 } 579 580 static int 581 urtwn_activate(device_t self, enum devact act) 582 { 583 struct urtwn_softc *sc = device_private(self); 584 585 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 586 587 switch (act) { 588 case DVACT_DEACTIVATE: 589 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 590 591 return 0; 592 default: 593 return EOPNOTSUPP; 594 } 595 } 596 597 static int 598 urtwn_open_pipes(struct urtwn_softc *sc) 599 { 600 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 601 static uint8_t epaddr[R92C_MAX_EPOUT]; 602 static uint8_t rxepaddr[R92C_MAX_EPIN]; 603 usb_interface_descriptor_t *id; 604 usb_endpoint_descriptor_t *ed; 605 size_t i, ntx = 0, nrx = 0; 606 int error; 607 608 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 609 610 /* Determine the number of bulk-out pipes. */ 611 id = usbd_get_interface_descriptor(sc->sc_iface); 612 for (i = 0; i < id->bNumEndpoints; i++) { 613 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 614 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 615 continue; 616 } 617 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 618 if (ntx < sizeof(epaddr)) 619 epaddr[ntx] = ed->bEndpointAddress; 620 ntx++; 621 } 622 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 623 if (nrx < sizeof(rxepaddr)) 624 rxepaddr[nrx] = ed->bEndpointAddress; 625 nrx++; 626 } 627 } 628 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 629 aprint_error_dev(sc->sc_dev, 630 "%zd: invalid number of Rx bulk pipes\n", nrx); 631 return EIO; 632 } 633 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 634 aprint_error_dev(sc->sc_dev, 635 "%zd: invalid number of Tx bulk pipes\n", ntx); 636 return EIO; 637 } 638 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 639 device_xname(sc->sc_dev), __func__, nrx, ntx)); 640 sc->rx_npipe = nrx; 641 sc->tx_npipe = ntx; 642 643 /* Open bulk-in pipe at address 0x81. */ 644 for (i = 0; i < nrx; i++) { 645 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 646 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 647 if (error != 0) { 648 aprint_error_dev(sc->sc_dev, 649 "could not open Rx bulk pipe 0x%02x: %d\n", 650 rxepaddr[i], error); 651 goto fail; 652 } 653 } 654 655 /* Open bulk-out pipes (up to 3). */ 656 for (i = 0; i < ntx; i++) { 657 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 658 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 659 if (error != 0) { 660 aprint_error_dev(sc->sc_dev, 661 "could not open Tx bulk pipe 0x%02x: %d\n", 662 epaddr[i], error); 663 goto fail; 664 } 665 } 666 667 /* Map 802.11 access categories to USB pipes. */ 668 sc->ac2idx[WME_AC_BK] = 669 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 670 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 671 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 672 673 fail: 674 if (error != 0) 675 urtwn_close_pipes(sc); 676 return error; 677 } 678 679 static void 680 urtwn_close_pipes(struct urtwn_softc *sc) 681 { 682 struct usbd_pipe *pipe; 683 size_t i; 684 685 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 686 687 /* Close Rx pipes. */ 688 CTASSERT(sizeof(pipe) == sizeof(void *)); 689 for (i = 0; i < sc->rx_npipe; i++) { 690 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 691 if (pipe != NULL) { 692 usbd_close_pipe(pipe); 693 } 694 } 695 696 /* Close Tx pipes. */ 697 for (i = 0; i < sc->tx_npipe; i++) { 698 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 699 if (pipe != NULL) { 700 usbd_close_pipe(pipe); 701 } 702 } 703 } 704 705 static int 706 urtwn_alloc_rx_list(struct urtwn_softc *sc) 707 { 708 struct urtwn_rx_data *data; 709 size_t i; 710 int error = 0; 711 712 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 713 714 for (size_t j = 0; j < sc->rx_npipe; j++) { 715 TAILQ_INIT(&sc->rx_free_list[j]); 716 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 717 data = &sc->rx_data[j][i]; 718 719 data->sc = sc; /* Backpointer for callbacks. */ 720 721 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 722 0, 0, &data->xfer); 723 if (error) { 724 aprint_error_dev(sc->sc_dev, 725 "could not allocate xfer\n"); 726 break; 727 } 728 729 data->buf = usbd_get_buffer(data->xfer); 730 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 731 } 732 } 733 if (error != 0) 734 urtwn_free_rx_list(sc); 735 return error; 736 } 737 738 static void 739 urtwn_free_rx_list(struct urtwn_softc *sc) 740 { 741 struct usbd_xfer *xfer; 742 size_t i; 743 744 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 745 746 /* NB: Caller must abort pipe first. */ 747 for (size_t j = 0; j < sc->rx_npipe; j++) { 748 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 749 CTASSERT(sizeof(xfer) == sizeof(void *)); 750 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 751 if (xfer != NULL) 752 usbd_destroy_xfer(xfer); 753 } 754 } 755 } 756 757 static int 758 urtwn_alloc_tx_list(struct urtwn_softc *sc) 759 { 760 struct urtwn_tx_data *data; 761 size_t i; 762 int error = 0; 763 764 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 765 766 mutex_enter(&sc->sc_tx_mtx); 767 for (size_t j = 0; j < sc->tx_npipe; j++) { 768 TAILQ_INIT(&sc->tx_free_list[j]); 769 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 770 data = &sc->tx_data[j][i]; 771 772 data->sc = sc; /* Backpointer for callbacks. */ 773 data->pidx = j; 774 775 error = usbd_create_xfer(sc->tx_pipe[j], 776 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 777 &data->xfer); 778 if (error) { 779 aprint_error_dev(sc->sc_dev, 780 "could not allocate xfer\n"); 781 goto fail; 782 } 783 784 data->buf = usbd_get_buffer(data->xfer); 785 786 /* Append this Tx buffer to our free list. */ 787 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 788 } 789 } 790 mutex_exit(&sc->sc_tx_mtx); 791 return 0; 792 793 fail: 794 urtwn_free_tx_list(sc); 795 mutex_exit(&sc->sc_tx_mtx); 796 return error; 797 } 798 799 static void 800 urtwn_free_tx_list(struct urtwn_softc *sc) 801 { 802 struct usbd_xfer *xfer; 803 size_t i; 804 805 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 806 807 /* NB: Caller must abort pipe first. */ 808 for (size_t j = 0; j < sc->tx_npipe; j++) { 809 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 810 CTASSERT(sizeof(xfer) == sizeof(void *)); 811 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 812 if (xfer != NULL) 813 usbd_destroy_xfer(xfer); 814 } 815 } 816 } 817 818 static void 819 urtwn_task(void *arg) 820 { 821 struct urtwn_softc *sc = arg; 822 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 823 struct urtwn_host_cmd *cmd; 824 int s; 825 826 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 827 828 /* Process host commands. */ 829 s = splusb(); 830 mutex_spin_enter(&sc->sc_task_mtx); 831 while (ring->next != ring->cur) { 832 cmd = &ring->cmd[ring->next]; 833 mutex_spin_exit(&sc->sc_task_mtx); 834 splx(s); 835 /* Invoke callback with kernel lock held. */ 836 cmd->cb(sc, cmd->data); 837 s = splusb(); 838 mutex_spin_enter(&sc->sc_task_mtx); 839 ring->queued--; 840 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 841 } 842 mutex_spin_exit(&sc->sc_task_mtx); 843 wakeup(&sc->cmdq); 844 splx(s); 845 } 846 847 static void 848 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 849 void *arg, int len) 850 { 851 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 852 struct urtwn_host_cmd *cmd; 853 int s; 854 855 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 856 device_xname(sc->sc_dev), __func__, cb, arg, len)); 857 858 s = splusb(); 859 mutex_spin_enter(&sc->sc_task_mtx); 860 cmd = &ring->cmd[ring->cur]; 861 cmd->cb = cb; 862 KASSERT(len <= sizeof(cmd->data)); 863 memcpy(cmd->data, arg, len); 864 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 865 866 /* If there is no pending command already, schedule a task. */ 867 if (!sc->sc_dying && ++ring->queued == 1) { 868 mutex_spin_exit(&sc->sc_task_mtx); 869 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 870 } else 871 mutex_spin_exit(&sc->sc_task_mtx); 872 splx(s); 873 } 874 875 static void 876 urtwn_wait_async(struct urtwn_softc *sc) 877 { 878 879 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 880 881 /* Wait for all queued asynchronous commands to complete. */ 882 while (sc->cmdq.queued > 0) 883 tsleep(&sc->cmdq, 0, "endtask", 0); 884 } 885 886 static int 887 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 888 int len) 889 { 890 usb_device_request_t req; 891 usbd_status error; 892 893 KASSERT(mutex_owned(&sc->sc_write_mtx)); 894 895 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 896 req.bRequest = R92C_REQ_REGS; 897 USETW(req.wValue, addr); 898 USETW(req.wIndex, 0); 899 USETW(req.wLength, len); 900 error = usbd_do_request(sc->sc_udev, &req, buf); 901 if (error != USBD_NORMAL_COMPLETION) { 902 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 903 device_xname(sc->sc_dev), __func__, error, addr, len)); 904 } 905 return error; 906 } 907 908 static void 909 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 910 { 911 912 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 913 device_xname(sc->sc_dev), __func__, addr, val)); 914 915 urtwn_write_region_1(sc, addr, &val, 1); 916 } 917 918 static void 919 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 920 { 921 uint8_t buf[2]; 922 923 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 924 device_xname(sc->sc_dev), __func__, addr, val)); 925 926 buf[0] = (uint8_t)val; 927 buf[1] = (uint8_t)(val >> 8); 928 urtwn_write_region_1(sc, addr, buf, 2); 929 } 930 931 static void 932 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 933 { 934 uint8_t buf[4]; 935 936 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 937 device_xname(sc->sc_dev), __func__, addr, val)); 938 939 buf[0] = (uint8_t)val; 940 buf[1] = (uint8_t)(val >> 8); 941 buf[2] = (uint8_t)(val >> 16); 942 buf[3] = (uint8_t)(val >> 24); 943 urtwn_write_region_1(sc, addr, buf, 4); 944 } 945 946 static int 947 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 948 { 949 950 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 951 device_xname(sc->sc_dev), __func__, addr, len)); 952 953 return urtwn_write_region_1(sc, addr, buf, len); 954 } 955 956 static int 957 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 958 int len) 959 { 960 usb_device_request_t req; 961 usbd_status error; 962 963 req.bmRequestType = UT_READ_VENDOR_DEVICE; 964 req.bRequest = R92C_REQ_REGS; 965 USETW(req.wValue, addr); 966 USETW(req.wIndex, 0); 967 USETW(req.wLength, len); 968 error = usbd_do_request(sc->sc_udev, &req, buf); 969 if (error != USBD_NORMAL_COMPLETION) { 970 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 971 device_xname(sc->sc_dev), __func__, error, addr, len)); 972 } 973 return error; 974 } 975 976 static uint8_t 977 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 978 { 979 uint8_t val; 980 981 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 982 return 0xff; 983 984 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 985 device_xname(sc->sc_dev), __func__, addr, val)); 986 return val; 987 } 988 989 static uint16_t 990 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 991 { 992 uint8_t buf[2]; 993 uint16_t val; 994 995 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 996 return 0xffff; 997 998 val = LE_READ_2(&buf[0]); 999 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1000 device_xname(sc->sc_dev), __func__, addr, val)); 1001 return val; 1002 } 1003 1004 static uint32_t 1005 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1006 { 1007 uint8_t buf[4]; 1008 uint32_t val; 1009 1010 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1011 return 0xffffffff; 1012 1013 val = LE_READ_4(&buf[0]); 1014 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1015 device_xname(sc->sc_dev), __func__, addr, val)); 1016 return val; 1017 } 1018 1019 static int 1020 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1021 { 1022 struct r92c_fw_cmd cmd; 1023 uint8_t *cp; 1024 int fwcur; 1025 int ntries; 1026 1027 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1028 device_xname(sc->sc_dev), __func__, id, buf, len)); 1029 1030 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1031 1032 mutex_enter(&sc->sc_fwcmd_mtx); 1033 fwcur = sc->fwcur; 1034 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1035 mutex_exit(&sc->sc_fwcmd_mtx); 1036 1037 /* Wait for current FW box to be empty. */ 1038 for (ntries = 0; ntries < 100; ntries++) { 1039 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1040 break; 1041 DELAY(10); 1042 } 1043 if (ntries == 100) { 1044 aprint_error_dev(sc->sc_dev, 1045 "could not send firmware command %d\n", id); 1046 return ETIMEDOUT; 1047 } 1048 1049 memset(&cmd, 0, sizeof(cmd)); 1050 KASSERT(len <= sizeof(cmd.msg)); 1051 memcpy(cmd.msg, buf, len); 1052 1053 /* Write the first word last since that will trigger the FW. */ 1054 cp = (uint8_t *)&cmd; 1055 cmd.id = id; 1056 if (len >= 4) { 1057 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1058 cmd.id |= R92C_CMD_FLAG_EXT; 1059 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1060 &cp[1], 2); 1061 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1062 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1063 (cp[5] << 24)); 1064 } else { 1065 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1066 &cp[4], 2); 1067 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1068 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1069 (cp[3] << 24)); 1070 } 1071 } else { 1072 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1073 } 1074 1075 return 0; 1076 } 1077 1078 static __inline void 1079 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1080 { 1081 1082 sc->sc_rf_write(sc, chain, addr, val); 1083 } 1084 1085 static void 1086 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1087 uint32_t val) 1088 { 1089 1090 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1091 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1092 } 1093 1094 static void 1095 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1096 uint32_t val) 1097 { 1098 1099 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1100 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1101 } 1102 1103 static void 1104 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1105 uint32_t val) 1106 { 1107 1108 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1109 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1110 } 1111 1112 static uint32_t 1113 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1114 { 1115 uint32_t reg[R92C_MAX_CHAINS], val; 1116 1117 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1118 if (chain != 0) { 1119 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1120 } 1121 1122 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1123 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1124 DELAY(1000); 1125 1126 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1127 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1128 R92C_HSSI_PARAM2_READ_EDGE); 1129 DELAY(1000); 1130 1131 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1132 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1133 DELAY(1000); 1134 1135 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1136 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1137 } else { 1138 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1139 } 1140 return MS(val, R92C_LSSI_READBACK_DATA); 1141 } 1142 1143 static int 1144 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1145 { 1146 int ntries; 1147 1148 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1149 1150 urtwn_write_4(sc, R92C_LLT_INIT, 1151 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1152 SM(R92C_LLT_INIT_ADDR, addr) | 1153 SM(R92C_LLT_INIT_DATA, data)); 1154 /* Wait for write operation to complete. */ 1155 for (ntries = 0; ntries < 20; ntries++) { 1156 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1157 R92C_LLT_INIT_OP_NO_ACTIVE) { 1158 /* Done */ 1159 return 0; 1160 } 1161 DELAY(5); 1162 } 1163 return ETIMEDOUT; 1164 } 1165 1166 static uint8_t 1167 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1168 { 1169 uint32_t reg; 1170 int ntries; 1171 1172 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1173 1174 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1175 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1176 reg &= ~R92C_EFUSE_CTRL_VALID; 1177 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1178 1179 /* Wait for read operation to complete. */ 1180 for (ntries = 0; ntries < 100; ntries++) { 1181 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1182 if (reg & R92C_EFUSE_CTRL_VALID) { 1183 /* Done */ 1184 return MS(reg, R92C_EFUSE_CTRL_DATA); 1185 } 1186 DELAY(5); 1187 } 1188 aprint_error_dev(sc->sc_dev, 1189 "could not read efuse byte at address 0x%04x\n", addr); 1190 return 0xff; 1191 } 1192 1193 static void 1194 urtwn_efuse_read(struct urtwn_softc *sc) 1195 { 1196 uint8_t *rom = (uint8_t *)&sc->rom; 1197 uint32_t reg; 1198 uint16_t addr = 0; 1199 uint8_t off, msk; 1200 size_t i; 1201 1202 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1203 1204 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1205 1206 urtwn_efuse_switch_power(sc); 1207 1208 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1209 while (addr < 512) { 1210 reg = urtwn_efuse_read_1(sc, addr); 1211 if (reg == 0xff) 1212 break; 1213 addr++; 1214 off = reg >> 4; 1215 msk = reg & 0xf; 1216 for (i = 0; i < 4; i++) { 1217 if (msk & (1U << i)) 1218 continue; 1219 1220 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1221 addr++; 1222 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1223 addr++; 1224 } 1225 } 1226 #ifdef URTWN_DEBUG 1227 if (urtwn_debug & DBG_INIT) { 1228 /* Dump ROM content. */ 1229 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1230 for (i = 0; i < (int)sizeof(sc->rom); i++) 1231 printf(":%02x", rom[i]); 1232 printf("\n"); 1233 } 1234 #endif 1235 } 1236 1237 static void 1238 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1239 { 1240 uint32_t reg; 1241 1242 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1243 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1244 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1245 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1246 } 1247 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1248 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1249 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1250 reg | R92C_SYS_FUNC_EN_ELDR); 1251 } 1252 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1253 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1254 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1255 urtwn_write_2(sc, R92C_SYS_CLKR, 1256 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1257 } 1258 } 1259 1260 static int 1261 urtwn_read_chipid(struct urtwn_softc *sc) 1262 { 1263 uint32_t reg; 1264 1265 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1266 1267 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1268 ISSET(sc->chip, URTWN_CHIP_92EU)) 1269 return 0; 1270 1271 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1272 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1273 /* test chip, not supported */ 1274 return EIO; 1275 } 1276 if (reg & R92C_SYS_CFG_TYPE_92C) { 1277 sc->chip |= URTWN_CHIP_92C; 1278 /* Check if it is a castrated 8192C. */ 1279 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1280 R92C_HPON_FSM_CHIP_BONDING_ID) == 1281 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1282 sc->chip |= URTWN_CHIP_92C_1T2R; 1283 } 1284 } 1285 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1286 sc->chip |= URTWN_CHIP_UMC; 1287 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1288 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1289 } 1290 } 1291 return 0; 1292 } 1293 1294 #ifdef URTWN_DEBUG 1295 static void 1296 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1297 { 1298 1299 aprint_normal_dev(sc->sc_dev, 1300 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1301 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1302 1303 aprint_normal_dev(sc->sc_dev, 1304 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1305 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1306 1307 aprint_normal_dev(sc->sc_dev, 1308 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1309 rp->macaddr[0], rp->macaddr[1], 1310 rp->macaddr[2], rp->macaddr[3], 1311 rp->macaddr[4], rp->macaddr[5]); 1312 1313 aprint_normal_dev(sc->sc_dev, 1314 "string %s, subcustomer_id 0x%x\n", 1315 rp->string, rp->subcustomer_id); 1316 1317 aprint_normal_dev(sc->sc_dev, 1318 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1319 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1320 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1321 1322 aprint_normal_dev(sc->sc_dev, 1323 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1324 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1325 rp->ht40_1s_tx_pwr[0][2], 1326 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1327 rp->ht40_1s_tx_pwr[1][2]); 1328 1329 aprint_normal_dev(sc->sc_dev, 1330 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1331 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1332 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1333 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1334 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1335 1336 aprint_normal_dev(sc->sc_dev, 1337 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1338 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1339 rp->ht20_tx_pwr_diff[2] & 0xf, 1340 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1341 rp->ht20_tx_pwr_diff[2] >> 4); 1342 1343 aprint_normal_dev(sc->sc_dev, 1344 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1345 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1346 rp->ofdm_tx_pwr_diff[2] & 0xf, 1347 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1348 rp->ofdm_tx_pwr_diff[2] >> 4); 1349 1350 aprint_normal_dev(sc->sc_dev, 1351 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1352 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1353 rp->ht40_max_pwr[2] & 0xf, 1354 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1355 rp->ht40_max_pwr[2] >> 4); 1356 1357 aprint_normal_dev(sc->sc_dev, 1358 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1359 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1360 rp->ht20_max_pwr[2] & 0xf, 1361 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1362 rp->ht20_max_pwr[2] >> 4); 1363 1364 aprint_normal_dev(sc->sc_dev, 1365 "xtal_calib %d, tssi %d %d, thermal %d\n", 1366 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1367 1368 aprint_normal_dev(sc->sc_dev, 1369 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1370 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1371 1372 aprint_normal_dev(sc->sc_dev, 1373 "channnel_plan %d, version %d customer_id 0x%x\n", 1374 rp->channel_plan, rp->version, rp->curstomer_id); 1375 } 1376 #endif 1377 1378 static void 1379 urtwn_read_rom(struct urtwn_softc *sc) 1380 { 1381 struct ieee80211com *ic = &sc->sc_ic; 1382 struct r92c_rom *rom = &sc->rom; 1383 1384 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1385 1386 mutex_enter(&sc->sc_write_mtx); 1387 1388 /* Read full ROM image. */ 1389 urtwn_efuse_read(sc); 1390 #ifdef URTWN_DEBUG 1391 if (urtwn_debug & DBG_REG) 1392 urtwn_dump_rom(sc, rom); 1393 #endif 1394 1395 /* XXX Weird but this is what the vendor driver does. */ 1396 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1397 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1398 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1399 1400 DPRINTFN(DBG_INIT, 1401 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1402 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1403 sc->board_type, sc->regulatory)); 1404 1405 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1406 1407 sc->sc_rf_write = urtwn_r92c_rf_write; 1408 sc->sc_power_on = urtwn_r92c_power_on; 1409 sc->sc_dma_init = urtwn_r92c_dma_init; 1410 1411 mutex_exit(&sc->sc_write_mtx); 1412 } 1413 1414 static void 1415 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1416 { 1417 struct ieee80211com *ic = &sc->sc_ic; 1418 uint8_t *rom = sc->r88e_rom; 1419 uint32_t reg; 1420 uint16_t addr = 0; 1421 uint8_t off, msk, tmp; 1422 int i; 1423 1424 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1425 1426 mutex_enter(&sc->sc_write_mtx); 1427 1428 off = 0; 1429 urtwn_efuse_switch_power(sc); 1430 1431 /* Read full ROM image. */ 1432 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1433 while (addr < 4096) { 1434 reg = urtwn_efuse_read_1(sc, addr); 1435 if (reg == 0xff) 1436 break; 1437 addr++; 1438 if ((reg & 0x1f) == 0x0f) { 1439 tmp = (reg & 0xe0) >> 5; 1440 reg = urtwn_efuse_read_1(sc, addr); 1441 if ((reg & 0x0f) != 0x0f) 1442 off = ((reg & 0xf0) >> 1) | tmp; 1443 addr++; 1444 } else 1445 off = reg >> 4; 1446 msk = reg & 0xf; 1447 for (i = 0; i < 4; i++) { 1448 if (msk & (1 << i)) 1449 continue; 1450 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1451 addr++; 1452 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1453 addr++; 1454 } 1455 } 1456 #ifdef URTWN_DEBUG 1457 if (urtwn_debug & DBG_REG) { 1458 } 1459 #endif 1460 1461 addr = 0x10; 1462 for (i = 0; i < 6; i++) 1463 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1464 for (i = 0; i < 5; i++) 1465 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1466 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1467 if (sc->bw20_tx_pwr_diff & 0x08) 1468 sc->bw20_tx_pwr_diff |= 0xf0; 1469 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1470 if (sc->ofdm_tx_pwr_diff & 0x08) 1471 sc->ofdm_tx_pwr_diff |= 0xf0; 1472 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1473 1474 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1475 1476 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1477 sc->sc_power_on = urtwn_r92e_power_on; 1478 sc->sc_rf_write = urtwn_r92e_rf_write; 1479 } else { 1480 sc->sc_power_on = urtwn_r88e_power_on; 1481 sc->sc_rf_write = urtwn_r88e_rf_write; 1482 } 1483 sc->sc_dma_init = urtwn_r88e_dma_init; 1484 1485 mutex_exit(&sc->sc_write_mtx); 1486 } 1487 1488 static __unused int 1489 urtwn_media_change(struct ifnet *ifp) 1490 { 1491 #ifdef URTWN_DEBUG 1492 struct urtwn_softc *sc = ifp->if_softc; 1493 #endif 1494 int error; 1495 1496 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1497 1498 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1499 return error; 1500 1501 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1502 (IFF_UP | IFF_RUNNING)) { 1503 urtwn_init(ifp); 1504 } 1505 return 0; 1506 } 1507 1508 /* 1509 * Initialize rate adaptation in firmware. 1510 */ 1511 static int 1512 urtwn_ra_init(struct urtwn_softc *sc) 1513 { 1514 static const uint8_t map[] = { 1515 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1516 }; 1517 struct ieee80211com *ic = &sc->sc_ic; 1518 #ifdef notyet 1519 struct ieee80211_node *ni = ic->ic_bss; */ 1520 struct ieee80211_rateset *rs = &ni->ni_rates; 1521 #else 1522 struct ieee80211_rateset *rs = ic->ic_sup_rates; 1523 #endif 1524 struct r92c_fw_cmd_macid_cfg cmd; 1525 uint32_t rates, basicrates; 1526 uint32_t mask, rrsr_mask, rrsr_rate; 1527 uint8_t mode; 1528 size_t maxrate, maxbasicrate, i, j; 1529 int error; 1530 1531 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1532 1533 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1534 1535 /* Get normal and basic rates mask. */ 1536 rates = basicrates = 1; 1537 maxrate = maxbasicrate = 0; 1538 for (i = 0; i < rs->rs_nrates; i++) { 1539 /* Convert 802.11 rate to HW rate index. */ 1540 for (j = 0; j < __arraycount(map); j++) { 1541 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1542 break; 1543 } 1544 } 1545 if (j == __arraycount(map)) { 1546 /* Unknown rate, skip. */ 1547 continue; 1548 } 1549 1550 rates |= 1U << j; 1551 if (j > maxrate) { 1552 maxrate = j; 1553 } 1554 1555 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1556 basicrates |= 1U << j; 1557 if (j > maxbasicrate) { 1558 maxbasicrate = j; 1559 } 1560 } 1561 } 1562 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1563 mode = R92C_RAID_11B; 1564 } else { 1565 mode = R92C_RAID_11BG; 1566 } 1567 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1568 "maxrate=%zx, maxbasicrate=%zx\n", 1569 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1570 maxrate, maxbasicrate)); 1571 1572 //NNN if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1573 maxbasicrate |= R92C_RATE_SHORTGI; 1574 maxrate |= R92C_RATE_SHORTGI; 1575 //NNN } 1576 1577 /* Set rates mask for group addressed frames. */ 1578 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1579 //NNN if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1580 cmd.macid |= URTWN_MACID_SHORTGI; 1581 1582 mask = (mode << 28) | basicrates; 1583 cmd.mask[0] = (uint8_t)mask; 1584 cmd.mask[1] = (uint8_t)(mask >> 8); 1585 cmd.mask[2] = (uint8_t)(mask >> 16); 1586 cmd.mask[3] = (uint8_t)(mask >> 24); 1587 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1588 if (error != 0) { 1589 aprint_error_dev(sc->sc_dev, 1590 "could not add broadcast station\n"); 1591 return error; 1592 } 1593 /* Set initial MRR rate. */ 1594 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1595 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1596 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1597 1598 /* Set rates mask for unicast frames. */ 1599 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1600 //NNN if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1601 cmd.macid |= URTWN_MACID_SHORTGI; 1602 1603 mask = (mode << 28) | rates; 1604 cmd.mask[0] = (uint8_t)mask; 1605 cmd.mask[1] = (uint8_t)(mask >> 8); 1606 cmd.mask[2] = (uint8_t)(mask >> 16); 1607 cmd.mask[3] = (uint8_t)(mask >> 24); 1608 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1609 if (error != 0) { 1610 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1611 return error; 1612 } 1613 /* Set initial MRR rate. */ 1614 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1615 __func__, maxrate)); 1616 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1617 1618 #if notyet 1619 /* NNN appears to have no fixed rate anywhere. */ 1620 rrsr_rate = ic->ic_fixed_rate; 1621 if (rrsr_rate == -1) 1622 #endif 1623 rrsr_rate = 11; 1624 1625 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1626 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1627 1628 #if notyet 1629 /* Indicate highest supported rate. */ 1630 ni->ni_txrate = rs->rs_nrates - 1; 1631 #endif 1632 return 0; 1633 } 1634 1635 static int 1636 urtwn_get_nettype(struct urtwn_softc *sc) 1637 { 1638 struct ieee80211com *ic = &sc->sc_ic; 1639 int type; 1640 1641 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1642 1643 switch (ic->ic_opmode) { 1644 case IEEE80211_M_STA: 1645 type = R92C_CR_NETTYPE_INFRA; 1646 break; 1647 1648 case IEEE80211_M_IBSS: 1649 type = R92C_CR_NETTYPE_ADHOC; 1650 break; 1651 1652 default: 1653 type = R92C_CR_NETTYPE_NOLINK; 1654 break; 1655 } 1656 1657 return type; 1658 } 1659 1660 static void 1661 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1662 { 1663 uint8_t reg; 1664 1665 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1666 __func__, type)); 1667 1668 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1669 1670 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1671 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1672 } 1673 1674 static void 1675 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1676 { 1677 #ifdef notyet 1678 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1679 uint64_t tsf; 1680 1681 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1682 1683 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1684 1685 /* Enable TSF synchronization. */ 1686 urtwn_write_1(sc, R92C_BCN_CTRL, 1687 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1688 1689 /* Correct TSF */ 1690 urtwn_write_1(sc, R92C_BCN_CTRL, 1691 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1692 1693 /* Set initial TSF. */ 1694 tsf = ni->ni_tstamp.tsf; 1695 tsf = le64toh(tsf); 1696 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1697 tsf -= IEEE80211_DUR_TU; 1698 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1699 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1700 1701 urtwn_write_1(sc, R92C_BCN_CTRL, 1702 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1703 #endif 1704 } 1705 1706 static void 1707 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1708 { 1709 uint8_t reg; 1710 1711 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1712 __func__, led, on)); 1713 1714 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1715 1716 if (led == URTWN_LED_LINK) { 1717 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1718 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1719 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1720 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1721 (R92C_LEDCFG0_DIS << 1)); 1722 if (on) { 1723 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1724 R92E_LEDSON; 1725 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1726 } 1727 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1728 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1729 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1730 if (!on) { 1731 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1732 urtwn_write_1(sc, R92C_LEDCFG2, 1733 reg | R92C_LEDCFG0_DIS); 1734 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1735 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1736 reg & 0xfe); 1737 } 1738 } else { 1739 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1740 if (!on) { 1741 reg |= R92C_LEDCFG0_DIS; 1742 } 1743 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1744 } 1745 sc->ledlink = on; /* Save LED state. */ 1746 } 1747 } 1748 1749 static void 1750 urtwn_calib_to(void *arg) 1751 { 1752 struct urtwn_softc *sc = arg; 1753 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1754 1755 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1756 1757 if (sc->sc_dying) 1758 return; 1759 1760 /* Do it in a process context. */ 1761 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1762 } 1763 1764 /* ARGSUSED */ 1765 static void 1766 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1767 { 1768 struct ieee80211vap *vap = arg; 1769 struct r92c_fw_cmd_rssi cmd; 1770 struct r92e_fw_cmd_rssi cmde; 1771 1772 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1773 1774 if (vap->iv_state != IEEE80211_S_RUN) 1775 goto restart_timer; 1776 1777 mutex_enter(&sc->sc_write_mtx); 1778 if (sc->avg_pwdb != -1) { 1779 /* Indicate Rx signal strength to FW for rate adaptation. */ 1780 memset(&cmd, 0, sizeof(cmd)); 1781 memset(&cmde, 0, sizeof(cmde)); 1782 cmd.macid = 0; /* BSS. */ 1783 cmde.macid = 0; /* BSS. */ 1784 cmd.pwdb = sc->avg_pwdb; 1785 cmde.pwdb = sc->avg_pwdb; 1786 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1787 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1788 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1789 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1790 sizeof(cmd)); 1791 } else { 1792 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1793 sizeof(cmde)); 1794 } 1795 } 1796 1797 /* Do temperature compensation. */ 1798 urtwn_temp_calib(sc); 1799 mutex_exit(&sc->sc_write_mtx); 1800 1801 restart_timer: 1802 if (!sc->sc_dying) { 1803 /* Restart calibration timer. */ 1804 callout_schedule(&sc->sc_calib_to, hz); 1805 } 1806 } 1807 1808 static void 1809 urtwn_next_scan(void *arg) 1810 { 1811 #ifdef notyet 1812 struct urtwn_softc *sc = arg; 1813 int s; 1814 1815 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1816 1817 if (sc->sc_dying) 1818 return; 1819 1820 s = splnet(); 1821 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1822 ieee80211_next_scan(&sc->sc_ic); 1823 splx(s); 1824 #endif 1825 } 1826 1827 static void 1828 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1829 { 1830 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1831 ether_sprintf(ni->ni_macaddr))); 1832 /* start with lowest Tx rate */ 1833 ni->ni_txrate = 0; 1834 } 1835 1836 static __unused int 1837 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1838 { 1839 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1840 struct urtwn_cmd_newstate cmd; 1841 1842 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1843 device_xname(sc->sc_dev), __func__, 1844 ieee80211_state_name[nstate], nstate, arg)); 1845 1846 callout_stop(&sc->sc_scan_to); 1847 callout_stop(&sc->sc_calib_to); 1848 1849 /* Do it in a process context. */ 1850 cmd.state = nstate; 1851 cmd.arg = arg; 1852 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1853 return 0; 1854 } 1855 1856 static void 1857 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1858 { 1859 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1860 struct urtwn_cmd_newstate *cmd = arg; 1861 struct ieee80211com *ic = &sc->sc_ic; 1862 struct ieee80211_node *ni; 1863 enum ieee80211_state ostate = vap->iv_state; 1864 enum ieee80211_state nstate = cmd->state; 1865 uint32_t reg; 1866 uint8_t sifs_time, msr; 1867 int s; 1868 1869 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1870 device_xname(sc->sc_dev), __func__, 1871 ieee80211_state_name[ostate], ostate, 1872 ieee80211_state_name[nstate], nstate)); 1873 1874 s = splnet(); 1875 mutex_enter(&sc->sc_write_mtx); 1876 1877 callout_stop(&sc->sc_scan_to); 1878 callout_stop(&sc->sc_calib_to); 1879 1880 switch (ostate) { 1881 case IEEE80211_S_INIT: 1882 break; 1883 1884 case IEEE80211_S_SCAN: 1885 if (nstate != IEEE80211_S_SCAN) { 1886 /* 1887 * End of scanning 1888 */ 1889 /* flush 4-AC Queue after site_survey */ 1890 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1891 1892 /* Allow Rx from our BSSID only. */ 1893 urtwn_write_4(sc, R92C_RCR, 1894 urtwn_read_4(sc, R92C_RCR) | 1895 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1896 } 1897 break; 1898 1899 case IEEE80211_S_AUTH: 1900 case IEEE80211_S_ASSOC: 1901 break; 1902 1903 case IEEE80211_S_RUN: 1904 /* Turn link LED off. */ 1905 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1906 1907 /* Set media status to 'No Link'. */ 1908 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1909 1910 /* Stop Rx of data frames. */ 1911 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1912 1913 /* Reset TSF. */ 1914 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1915 1916 /* Disable TSF synchronization. */ 1917 urtwn_write_1(sc, R92C_BCN_CTRL, 1918 urtwn_read_1(sc, R92C_BCN_CTRL) | 1919 R92C_BCN_CTRL_DIS_TSF_UDT0); 1920 1921 /* Back to 20MHz mode */ 1922 urtwn_set_chan(sc, ic->ic_curchan, 1923 IEEE80211_HTINFO_2NDCHAN_NONE); 1924 1925 if (ic->ic_opmode == IEEE80211_M_IBSS || 1926 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1927 /* Stop BCN */ 1928 urtwn_write_1(sc, R92C_BCN_CTRL, 1929 urtwn_read_1(sc, R92C_BCN_CTRL) & 1930 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1931 } 1932 1933 /* Reset EDCA parameters. */ 1934 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1935 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1936 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1937 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1938 1939 /* flush all cam entries */ 1940 urtwn_cam_init(sc); 1941 break; 1942 case IEEE80211_S_CAC: 1943 case IEEE80211_S_CSA: 1944 case IEEE80211_S_SLEEP: 1945 /* NNN what do we do in these states? XXX */ 1946 break; 1947 } 1948 1949 switch (nstate) { 1950 case IEEE80211_S_INIT: 1951 /* Turn link LED off. */ 1952 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1953 break; 1954 1955 case IEEE80211_S_SCAN: 1956 if (ostate != IEEE80211_S_SCAN) { 1957 /* 1958 * Begin of scanning 1959 */ 1960 1961 /* Set gain for scanning. */ 1962 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1963 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1964 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1965 1966 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1967 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1968 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1969 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1970 } 1971 1972 /* Set media status to 'No Link'. */ 1973 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1974 1975 /* Allow Rx from any BSSID. */ 1976 urtwn_write_4(sc, R92C_RCR, 1977 urtwn_read_4(sc, R92C_RCR) & 1978 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1979 1980 /* Stop Rx of data frames. */ 1981 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1982 1983 /* Disable update TSF */ 1984 urtwn_write_1(sc, R92C_BCN_CTRL, 1985 urtwn_read_1(sc, R92C_BCN_CTRL) | 1986 R92C_BCN_CTRL_DIS_TSF_UDT0); 1987 } 1988 1989 /* Make link LED blink during scan. */ 1990 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1991 1992 /* Pause AC Tx queues. */ 1993 urtwn_write_1(sc, R92C_TXPAUSE, 1994 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1995 1996 urtwn_set_chan(sc, ic->ic_curchan, 1997 IEEE80211_HTINFO_2NDCHAN_NONE); 1998 1999 /* Start periodic scan. */ 2000 if (!sc->sc_dying) 2001 callout_schedule(&sc->sc_scan_to, hz / 5); 2002 break; 2003 2004 case IEEE80211_S_AUTH: 2005 /* Set initial gain under link. */ 2006 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2007 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2008 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2009 2010 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2011 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2012 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2013 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2014 } 2015 2016 /* Set media status to 'No Link'. */ 2017 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2018 2019 /* Allow Rx from any BSSID. */ 2020 urtwn_write_4(sc, R92C_RCR, 2021 urtwn_read_4(sc, R92C_RCR) & 2022 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2023 2024 urtwn_set_chan(sc, ic->ic_curchan, 2025 IEEE80211_HTINFO_2NDCHAN_NONE); 2026 break; 2027 2028 case IEEE80211_S_ASSOC: 2029 break; 2030 2031 case IEEE80211_S_RUN: 2032 ni = vap->iv_bss; 2033 2034 /* XXX: Set 20MHz mode */ 2035 urtwn_set_chan(sc, ic->ic_curchan, 2036 IEEE80211_HTINFO_2NDCHAN_NONE); 2037 2038 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2039 /* Back to 20MHz mode */ 2040 urtwn_set_chan(sc, ic->ic_curchan, 2041 IEEE80211_HTINFO_2NDCHAN_NONE); 2042 2043 /* Set media status to 'No Link'. */ 2044 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2045 2046 /* Enable Rx of data frames. */ 2047 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2048 2049 /* Allow Rx from any BSSID. */ 2050 urtwn_write_4(sc, R92C_RCR, 2051 urtwn_read_4(sc, R92C_RCR) & 2052 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2053 2054 /* Accept Rx data/control/management frames */ 2055 urtwn_write_4(sc, R92C_RCR, 2056 urtwn_read_4(sc, R92C_RCR) | 2057 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2058 2059 /* Turn link LED on. */ 2060 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2061 break; 2062 } 2063 2064 /* Set media status to 'Associated'. */ 2065 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2066 2067 /* Set BSSID. */ 2068 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2069 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2070 2071 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2072 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2073 } else { 2074 /* 802.11b/g */ 2075 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2076 } 2077 2078 /* Enable Rx of data frames. */ 2079 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2080 2081 /* Set beacon interval. */ 2082 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2083 2084 msr = urtwn_read_1(sc, R92C_MSR); 2085 msr &= R92C_MSR_MASK; 2086 switch (ic->ic_opmode) { 2087 case IEEE80211_M_STA: 2088 /* Allow Rx from our BSSID only. */ 2089 urtwn_write_4(sc, R92C_RCR, 2090 urtwn_read_4(sc, R92C_RCR) | 2091 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2092 2093 /* Enable TSF synchronization. */ 2094 urtwn_tsf_sync_enable(sc); 2095 2096 msr |= R92C_MSR_INFRA; 2097 break; 2098 case IEEE80211_M_HOSTAP: 2099 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2100 2101 /* Allow Rx from any BSSID. */ 2102 urtwn_write_4(sc, R92C_RCR, 2103 urtwn_read_4(sc, R92C_RCR) & 2104 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2105 2106 /* Reset TSF timer to zero. */ 2107 reg = urtwn_read_4(sc, R92C_TCR); 2108 reg &= ~0x01; 2109 urtwn_write_4(sc, R92C_TCR, reg); 2110 reg |= 0x01; 2111 urtwn_write_4(sc, R92C_TCR, reg); 2112 2113 msr |= R92C_MSR_AP; 2114 break; 2115 default: 2116 msr |= R92C_MSR_ADHOC; 2117 break; 2118 } 2119 urtwn_write_1(sc, R92C_MSR, msr); 2120 2121 sifs_time = 10; 2122 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2123 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2124 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2125 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2126 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2127 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2128 2129 /* Initialize rate adaptation. */ 2130 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2131 ISSET(sc->chip, URTWN_CHIP_92EU)) 2132 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2133 else 2134 urtwn_ra_init(sc); 2135 2136 /* Turn link LED on. */ 2137 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2138 2139 /* Reset average RSSI. */ 2140 sc->avg_pwdb = -1; 2141 2142 /* Reset temperature calibration state machine. */ 2143 sc->thcal_state = 0; 2144 sc->thcal_lctemp = 0; 2145 2146 /* Start periodic calibration. */ 2147 if (!sc->sc_dying) 2148 callout_schedule(&sc->sc_calib_to, hz); 2149 break; 2150 case IEEE80211_S_CAC: 2151 case IEEE80211_S_CSA: 2152 case IEEE80211_S_SLEEP: 2153 /* NNN what do we do in these states? XXX */ 2154 break; 2155 } 2156 2157 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2158 2159 mutex_exit(&sc->sc_write_mtx); 2160 splx(s); 2161 } 2162 2163 static int 2164 urtwn_wme_update(struct ieee80211com *ic) 2165 { 2166 struct urtwn_softc *sc = ic->ic_softc; 2167 2168 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2169 2170 /* don't override default WME values if WME is not actually enabled */ 2171 if (!(ic->ic_flags & IEEE80211_F_WME)) 2172 return 0; 2173 2174 /* Do it in a process context. */ 2175 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2176 return 0; 2177 } 2178 2179 static void 2180 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2181 { 2182 static const uint16_t ac2reg[WME_NUM_AC] = { 2183 R92C_EDCA_BE_PARAM, 2184 R92C_EDCA_BK_PARAM, 2185 R92C_EDCA_VI_PARAM, 2186 R92C_EDCA_VO_PARAM 2187 }; 2188 struct ieee80211com *ic = &sc->sc_ic; 2189 const struct wmeParams *wmep; 2190 int ac, aifs, slottime; 2191 int s; 2192 2193 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2194 __func__)); 2195 2196 s = splnet(); 2197 mutex_enter(&sc->sc_write_mtx); 2198 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2199 for (ac = 0; ac < WME_NUM_AC; ac++) { 2200 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2201 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2202 aifs = wmep->wmep_aifsn * slottime + 10; 2203 urtwn_write_4(sc, ac2reg[ac], 2204 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2205 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2206 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2207 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2208 } 2209 mutex_exit(&sc->sc_write_mtx); 2210 splx(s); 2211 } 2212 2213 static void 2214 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2215 { 2216 int pwdb; 2217 2218 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2219 device_xname(sc->sc_dev), __func__, rate, rssi)); 2220 2221 /* Convert antenna signal to percentage. */ 2222 if (rssi <= -100 || rssi >= 20) 2223 pwdb = 0; 2224 else if (rssi >= 0) 2225 pwdb = 100; 2226 else 2227 pwdb = 100 + rssi; 2228 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2229 if (rate <= 3) { 2230 /* CCK gain is smaller than OFDM/MCS gain. */ 2231 pwdb += 6; 2232 if (pwdb > 100) 2233 pwdb = 100; 2234 if (pwdb <= 14) 2235 pwdb -= 4; 2236 else if (pwdb <= 26) 2237 pwdb -= 8; 2238 else if (pwdb <= 34) 2239 pwdb -= 6; 2240 else if (pwdb <= 42) 2241 pwdb -= 2; 2242 } 2243 } 2244 if (sc->avg_pwdb == -1) /* Init. */ 2245 sc->avg_pwdb = pwdb; 2246 else if (sc->avg_pwdb < pwdb) 2247 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2248 else 2249 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2250 2251 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2252 device_xname(sc->sc_dev), __func__, 2253 rate, rssi, pwdb, sc->avg_pwdb)); 2254 } 2255 2256 static int8_t 2257 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2258 { 2259 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2260 struct r92c_rx_phystat *phy; 2261 struct r92c_rx_cck *cck; 2262 uint8_t rpt; 2263 int8_t rssi; 2264 2265 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2266 __func__, rate)); 2267 2268 if (rate <= 3) { 2269 cck = (struct r92c_rx_cck *)physt; 2270 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2271 rpt = (cck->agc_rpt >> 5) & 0x3; 2272 rssi = (cck->agc_rpt & 0x1f) << 1; 2273 } else { 2274 rpt = (cck->agc_rpt >> 6) & 0x3; 2275 rssi = cck->agc_rpt & 0x3e; 2276 } 2277 rssi = cckoff[rpt] - rssi; 2278 } else { /* OFDM/HT. */ 2279 phy = (struct r92c_rx_phystat *)physt; 2280 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2281 } 2282 return rssi; 2283 } 2284 2285 static int8_t 2286 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2287 { 2288 struct r92c_rx_phystat *phy; 2289 struct r88e_rx_cck *cck; 2290 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2291 int8_t rssi; 2292 2293 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2294 __func__, rate)); 2295 2296 rssi = 0; 2297 if (rate <= 3) { 2298 cck = (struct r88e_rx_cck *)physt; 2299 cck_agc_rpt = cck->agc_rpt; 2300 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2301 vga_idx = cck_agc_rpt & 0x1f; 2302 switch (lna_idx) { 2303 case 7: 2304 if (vga_idx <= 27) 2305 rssi = -100 + 2* (27 - vga_idx); 2306 else 2307 rssi = -100; 2308 break; 2309 case 6: 2310 rssi = -48 + 2 * (2 - vga_idx); 2311 break; 2312 case 5: 2313 rssi = -42 + 2 * (7 - vga_idx); 2314 break; 2315 case 4: 2316 rssi = -36 + 2 * (7 - vga_idx); 2317 break; 2318 case 3: 2319 rssi = -24 + 2 * (7 - vga_idx); 2320 break; 2321 case 2: 2322 rssi = -12 + 2 * (5 - vga_idx); 2323 break; 2324 case 1: 2325 rssi = 8 - (2 * vga_idx); 2326 break; 2327 case 0: 2328 rssi = 14 - (2 * vga_idx); 2329 break; 2330 } 2331 rssi += 6; 2332 } else { /* OFDM/HT. */ 2333 phy = (struct r92c_rx_phystat *)physt; 2334 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2335 } 2336 return rssi; 2337 } 2338 2339 static void 2340 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2341 { 2342 struct ieee80211com *ic = &sc->sc_ic; 2343 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2344 struct ifnet *ifp = vap->iv_ifp; 2345 struct ieee80211_frame *wh; 2346 struct ieee80211_node *ni; 2347 struct r92c_rx_stat *stat; 2348 uint32_t rxdw0, rxdw3; 2349 struct mbuf *m; 2350 uint8_t rate; 2351 int8_t rssi = 0; 2352 int s, infosz; 2353 2354 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2355 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2356 2357 stat = (struct r92c_rx_stat *)buf; 2358 rxdw0 = le32toh(stat->rxdw0); 2359 rxdw3 = le32toh(stat->rxdw3); 2360 2361 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2362 /* 2363 * This should not happen since we setup our Rx filter 2364 * to not receive these frames. 2365 */ 2366 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2367 device_xname(sc->sc_dev), __func__)); 2368 ifp->if_ierrors++; 2369 return; 2370 } 2371 /* 2372 * XXX: This will drop most control packets. Do we really 2373 * want this in IEEE80211_M_MONITOR mode? 2374 */ 2375 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2376 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2377 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2378 device_xname(sc->sc_dev), __func__, pktlen)); 2379 vap->iv_stats.is_rx_tooshort++; 2380 ifp->if_ierrors++; 2381 return; 2382 } 2383 if (__predict_false(pktlen > MCLBYTES)) { 2384 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2385 device_xname(sc->sc_dev), __func__, pktlen)); 2386 ifp->if_ierrors++; 2387 return; 2388 } 2389 2390 rate = MS(rxdw3, R92C_RXDW3_RATE); 2391 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2392 2393 /* Get RSSI from PHY status descriptor if present. */ 2394 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2395 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2396 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2397 else 2398 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2399 /* Update our average RSSI. */ 2400 urtwn_update_avgrssi(sc, rate, rssi); 2401 } 2402 2403 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2404 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2405 2406 MGETHDR(m, M_DONTWAIT, MT_DATA); 2407 if (__predict_false(m == NULL)) { 2408 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2409 vap->iv_stats.is_rx_nobuf++; 2410 ifp->if_ierrors++; 2411 return; 2412 } 2413 if (pktlen > (int)MHLEN) { 2414 MCLGET(m, M_DONTWAIT); 2415 if (__predict_false(!(m->m_flags & M_EXT))) { 2416 aprint_error_dev(sc->sc_dev, 2417 "couldn't allocate rx mbuf cluster\n"); 2418 m_freem(m); 2419 vap->iv_stats.is_rx_nobuf++; 2420 ifp->if_ierrors++; 2421 return; 2422 } 2423 } 2424 2425 /* Finalize mbuf. */ 2426 m_set_rcvif(m, ifp); 2427 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2428 memcpy(mtod(m, uint8_t *), wh, pktlen); 2429 m->m_pkthdr.len = m->m_len = pktlen; 2430 2431 s = splnet(); 2432 if (__predict_false(sc->sc_drvbpf != NULL)) { 2433 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2434 2435 tap->wr_flags = 0; 2436 if (!(rxdw3 & R92C_RXDW3_HT)) { 2437 switch (rate) { 2438 /* CCK. */ 2439 case 0: tap->wr_rate = 2; break; 2440 case 1: tap->wr_rate = 4; break; 2441 case 2: tap->wr_rate = 11; break; 2442 case 3: tap->wr_rate = 22; break; 2443 /* OFDM. */ 2444 case 4: tap->wr_rate = 12; break; 2445 case 5: tap->wr_rate = 18; break; 2446 case 6: tap->wr_rate = 24; break; 2447 case 7: tap->wr_rate = 36; break; 2448 case 8: tap->wr_rate = 48; break; 2449 case 9: tap->wr_rate = 72; break; 2450 case 10: tap->wr_rate = 96; break; 2451 case 11: tap->wr_rate = 108; break; 2452 } 2453 } else if (rate >= 12) { /* MCS0~15. */ 2454 /* Bit 7 set means HT MCS instead of rate. */ 2455 tap->wr_rate = 0x80 | (rate - 12); 2456 } 2457 tap->wr_dbm_antsignal = rssi; 2458 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2459 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2460 2461 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2462 } 2463 2464 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2465 2466 /* push the frame up to the 802.11 stack */ 2467 ieee80211_input(ni, m, rssi, 0); 2468 2469 /* Node is no longer needed. */ 2470 ieee80211_free_node(ni); 2471 2472 splx(s); 2473 } 2474 2475 static void 2476 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2477 { 2478 struct urtwn_rx_data *data = priv; 2479 struct urtwn_softc *sc = data->sc; 2480 struct r92c_rx_stat *stat; 2481 size_t pidx = data->pidx; 2482 uint32_t rxdw0; 2483 uint8_t *buf; 2484 int len, totlen, pktlen, infosz, npkts; 2485 2486 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2487 device_xname(sc->sc_dev), __func__, status)); 2488 2489 mutex_enter(&sc->sc_rx_mtx); 2490 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2491 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2492 /* Put this Rx buffer back to our free list. */ 2493 mutex_exit(&sc->sc_rx_mtx); 2494 2495 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2496 if (status == USBD_STALLED) 2497 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2498 else if (status != USBD_CANCELLED) 2499 goto resubmit; 2500 return; 2501 } 2502 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2503 2504 if (__predict_false(len < (int)sizeof(*stat))) { 2505 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2506 device_xname(sc->sc_dev), __func__, len)); 2507 goto resubmit; 2508 } 2509 buf = data->buf; 2510 2511 /* Get the number of encapsulated frames. */ 2512 stat = (struct r92c_rx_stat *)buf; 2513 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2514 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2515 device_xname(sc->sc_dev), __func__, npkts)); 2516 2517 /* Process all of them. */ 2518 while (npkts-- > 0) { 2519 if (__predict_false(len < (int)sizeof(*stat))) { 2520 DPRINTFN(DBG_RX, 2521 ("%s: %s: len(%d) is short than header\n", 2522 device_xname(sc->sc_dev), __func__, len)); 2523 break; 2524 } 2525 stat = (struct r92c_rx_stat *)buf; 2526 rxdw0 = le32toh(stat->rxdw0); 2527 2528 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2529 if (__predict_false(pktlen == 0)) { 2530 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2531 device_xname(sc->sc_dev), __func__)); 2532 break; 2533 } 2534 2535 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2536 2537 /* Make sure everything fits in xfer. */ 2538 totlen = sizeof(*stat) + infosz + pktlen; 2539 if (__predict_false(totlen > len)) { 2540 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2541 device_xname(sc->sc_dev), __func__, totlen, 2542 (int)sizeof(*stat), infosz, pktlen, len)); 2543 break; 2544 } 2545 2546 /* Process 802.11 frame. */ 2547 urtwn_rx_frame(sc, buf, pktlen); 2548 2549 /* Next chunk is 128-byte aligned. */ 2550 totlen = roundup2(totlen, 128); 2551 buf += totlen; 2552 len -= totlen; 2553 } 2554 2555 resubmit: 2556 /* Setup a new transfer. */ 2557 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2558 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2559 (void)usbd_transfer(xfer); 2560 } 2561 2562 static void 2563 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2564 { 2565 struct urtwn_tx_data *data = priv; 2566 struct urtwn_softc *sc = data->sc; 2567 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 2568 size_t pidx = data->pidx; 2569 int s; 2570 2571 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2572 device_xname(sc->sc_dev), __func__, status)); 2573 2574 mutex_enter(&sc->sc_tx_mtx); 2575 /* Put this Tx buffer back to our free list. */ 2576 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2577 mutex_exit(&sc->sc_tx_mtx); 2578 2579 s = splnet(); 2580 sc->tx_timer = 0; 2581 ifp->if_flags &= ~IFF_OACTIVE; 2582 2583 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2584 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2585 if (status == USBD_STALLED) { 2586 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2587 usbd_clear_endpoint_stall_async(pipe); 2588 } 2589 printf("ERROR1\n"); 2590 ifp->if_oerrors++; 2591 } 2592 splx(s); 2593 return; 2594 } 2595 2596 ifp->if_opackets++; 2597 urtwn_start(ifp); 2598 splx(s); 2599 2600 } 2601 2602 static int 2603 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2604 struct urtwn_tx_data *data) 2605 { 2606 struct ieee80211com *ic = &sc->sc_ic; 2607 struct ieee80211_frame *wh; 2608 struct ieee80211_key *k = NULL; 2609 struct r92c_tx_desc *txd; 2610 size_t i, padsize, xferlen, txd_len; 2611 uint16_t seq, sum; 2612 uint8_t raid, type, tid; 2613 int s, hasqos, error; 2614 2615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2616 2617 wh = mtod(m, struct ieee80211_frame *); 2618 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2619 txd_len = sizeof(*txd); 2620 2621 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2622 txd_len = 32; 2623 2624 #define IEEE80211_FC1_WEP 1 /* NNN need to find where we know there is WEP */ 2625 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2626 k = ieee80211_crypto_encap(ni, m); 2627 if (k == NULL) 2628 return ENOBUFS; 2629 2630 /* packet header may have moved, reset our local pointer */ 2631 wh = mtod(m, struct ieee80211_frame *); 2632 } 2633 2634 2635 if (__predict_false(sc->sc_drvbpf != NULL)) { 2636 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2637 2638 tap->wt_flags = 0; 2639 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2640 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2641 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2642 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2643 2644 /* XXX: set tap->wt_rate? */ 2645 2646 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2647 } 2648 2649 /* non-qos data frames */ 2650 tid = R92C_TXDW1_QSEL_BE; 2651 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2652 /* data frames in 11n mode */ 2653 struct ieee80211_qosframe *qwh = (void *)wh; 2654 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2655 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2656 tid = R92C_TXDW1_QSEL_MGNT; 2657 } 2658 2659 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2660 padsize = 8; 2661 else 2662 padsize = 0; 2663 2664 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2665 padsize = 0; 2666 2667 /* Fill Tx descriptor. */ 2668 txd = (struct r92c_tx_desc *)data->buf; 2669 memset(txd, 0, txd_len + padsize); 2670 2671 txd->txdw0 |= htole32( 2672 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2673 SM(R92C_TXDW0_OFFSET, txd_len)); 2674 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2675 txd->txdw0 |= htole32( 2676 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2677 } 2678 2679 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2680 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2681 2682 /* fix pad field */ 2683 if (padsize > 0) { 2684 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2685 device_xname(sc->sc_dev), __func__, padsize)); 2686 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2687 } 2688 2689 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2690 type == IEEE80211_FC0_TYPE_DATA) { 2691 if (ic->ic_curmode == IEEE80211_MODE_11B) 2692 raid = R92C_RAID_11B; 2693 else 2694 raid = R92C_RAID_11BG; 2695 DPRINTFN(DBG_TX, 2696 ("%s: %s: data packet: tid=%d, raid=%d\n", 2697 device_xname(sc->sc_dev), __func__, tid, raid)); 2698 2699 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2700 txd->txdw1 |= htole32( 2701 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 2702 SM(R92C_TXDW1_QSEL, tid) | 2703 SM(R92C_TXDW1_RAID, raid) | 2704 R92C_TXDW1_AGGBK); 2705 } else 2706 txd->txdw1 |= htole32( 2707 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2708 SM(R92C_TXDW1_QSEL, tid) | 2709 SM(R92C_TXDW1_RAID, raid) | 2710 R92C_TXDW1_AGGBK); 2711 2712 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2713 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2714 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2715 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2716 2717 if (hasqos) { 2718 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2719 } 2720 2721 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2722 /* for 11g */ 2723 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2724 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2725 R92C_TXDW4_HWRTSEN); 2726 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2727 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2728 R92C_TXDW4_HWRTSEN); 2729 } 2730 } 2731 /* Send RTS at OFDM24. */ 2732 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2733 txd->txdw5 |= htole32(0x0001ff00); 2734 /* Send data at OFDM54. */ 2735 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2736 txd->txdw5 |= htole32(0x13 & 0x3f); 2737 else 2738 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2739 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2740 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2741 device_xname(sc->sc_dev), __func__)); 2742 txd->txdw1 |= htole32( 2743 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2744 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2745 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2746 2747 /* Force CCK1. */ 2748 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2749 /* Use 1Mbps */ 2750 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2751 } else { 2752 /* broadcast or multicast packets */ 2753 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2754 device_xname(sc->sc_dev), __func__)); 2755 txd->txdw1 |= htole32( 2756 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2757 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2758 2759 /* Force CCK1. */ 2760 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2761 /* Use 1Mbps */ 2762 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2763 } 2764 /* Set sequence number */ 2765 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2766 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2767 txd->txdseq |= htole16(seq); 2768 2769 if (!hasqos) { 2770 /* Use HW sequence numbering for non-QoS frames. */ 2771 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2772 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2773 } 2774 } else { 2775 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2776 R92E_HWSEQ_SHIFT); 2777 if (!hasqos) { 2778 /* Use HW sequence numbering for non-QoS frames. */ 2779 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2780 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2781 } 2782 } 2783 2784 /* Compute Tx descriptor checksum. */ 2785 sum = 0; 2786 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2787 sum ^= ((uint16_t *)txd)[i]; 2788 txd->txdsum = sum; /* NB: already little endian. */ 2789 2790 xferlen = txd_len + m->m_pkthdr.len + padsize; 2791 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2792 2793 s = splnet(); 2794 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2795 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2796 urtwn_txeof); 2797 error = usbd_transfer(data->xfer); 2798 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2799 error != USBD_IN_PROGRESS)) { 2800 splx(s); 2801 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2802 device_xname(sc->sc_dev), __func__, error)); 2803 return error; 2804 } 2805 splx(s); 2806 return 0; 2807 } 2808 2809 struct urtwn_tx_data * 2810 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2811 { 2812 struct urtwn_tx_data *data = NULL; 2813 2814 mutex_enter(&sc->sc_tx_mtx); 2815 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2816 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2817 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2818 } 2819 mutex_exit(&sc->sc_tx_mtx); 2820 2821 return data; 2822 } 2823 2824 static void 2825 urtwn_start(struct ifnet *ifp) 2826 { 2827 struct urtwn_softc *sc = ifp->if_softc; 2828 struct ieee80211com *ic = &sc->sc_ic; 2829 struct urtwn_tx_data *data; 2830 struct ether_header *eh; 2831 struct ieee80211_node *ni; 2832 struct ieee80211vap *vap; 2833 struct mbuf *m; 2834 2835 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2836 2837 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2838 return; 2839 2840 /* Find the associated vap. NEED A BETTER WAY! */ 2841 vap = TAILQ_FIRST(&ic->ic_vaps); 2842 while (vap != NULL) { 2843 if (vap->iv_ifp == ifp) 2844 break; 2845 vap = TAILQ_NEXT(vap, iv_next); 2846 } 2847 KASSERT(vap != NULL); 2848 2849 data = NULL; 2850 for (;;) { 2851 /* Send pending management frames first. */ 2852 IF_POLL(&ic->ic_mgtq, m); 2853 if (m != NULL) { 2854 /* Use AC_VO for management frames. */ 2855 2856 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2857 2858 if (data == NULL) { 2859 ifp->if_flags |= IFF_OACTIVE; 2860 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2861 device_xname(sc->sc_dev))); 2862 return; 2863 } 2864 IF_DEQUEUE(&ic->ic_mgtq, m); 2865 ni = M_GETCTX(m, struct ieee80211_node *); 2866 M_CLEARCTX(m); 2867 goto sendit; 2868 } 2869 2870 if (vap->iv_state != IEEE80211_S_RUN) 2871 break; 2872 2873 /* Encapsulate and send data frames. */ 2874 IFQ_POLL(&ifp->if_snd, m); 2875 if (m == NULL) 2876 break; 2877 2878 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2879 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2880 uint8_t qid = WME_AC_BE; 2881 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2882 /* data frames in 11n mode */ 2883 struct ieee80211_qosframe *qwh = (void *)wh; 2884 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2885 qid = TID_TO_WME_AC(tid); 2886 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2887 qid = WME_AC_VO; 2888 } 2889 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2890 2891 if (data == NULL) { 2892 ifp->if_flags |= IFF_OACTIVE; 2893 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2894 device_xname(sc->sc_dev))); 2895 return; 2896 } 2897 IFQ_DEQUEUE(&ifp->if_snd, m); 2898 2899 if (m->m_len < (int)sizeof(*eh) && 2900 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2901 printf("ERROR6\n"); 2902 ifp->if_oerrors++; 2903 continue; 2904 } 2905 eh = mtod(m, struct ether_header *); 2906 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 2907 if (ni == NULL) { 2908 m_freem(m); 2909 printf("ERROR5\n"); 2910 ifp->if_oerrors++; 2911 continue; 2912 } 2913 2914 bpf_mtap(ifp, m, BPF_D_OUT); 2915 2916 if ((m = ieee80211_encap(vap, ni, m)) == NULL) { 2917 ieee80211_free_node(ni); 2918 printf("ERROR4\n"); 2919 ifp->if_oerrors++; 2920 continue; 2921 } 2922 sendit: 2923 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 2924 2925 if (urtwn_tx(sc, m, ni, data) != 0) { 2926 m_freem(m); 2927 ieee80211_free_node(ni); 2928 printf("ERROR3\n"); 2929 ifp->if_oerrors++; 2930 continue; 2931 } 2932 m_freem(m); 2933 ieee80211_free_node(ni); 2934 sc->tx_timer = 5; 2935 ifp->if_timer = 1; 2936 } 2937 } 2938 2939 static void 2940 urtwn_watchdog(struct ifnet *ifp) 2941 { 2942 struct urtwn_softc *sc = ifp->if_softc; 2943 2944 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2945 2946 ifp->if_timer = 0; 2947 2948 if (sc->tx_timer > 0) { 2949 if (--sc->tx_timer == 0) { 2950 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2951 /* urtwn_init(ifp); XXX needs a process context! */ 2952 printf("ERROR2\n"); 2953 ifp->if_oerrors++; 2954 return; 2955 } 2956 ifp->if_timer = 1; 2957 } 2958 //NNN ieee80211_watchdog(&sc->sc_ic); Not sure what is happening! 2959 } 2960 2961 /* 2962 * Create a VAP node for use with the urtwn driver. 2963 */ 2964 2965 static struct ieee80211vap * 2966 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 2967 int unit, enum ieee80211_opmode opmode, int flags, 2968 const uint8_t bssid[IEEE80211_ADDR_LEN], 2969 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 2970 { 2971 printf ("in urtwn_vap_create ... \n"); 2972 2973 struct urtwn_softc *sc = ic->ic_softc; 2974 struct ifnet *ifp; 2975 struct ieee80211vap *vap; 2976 2977 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2978 2979 /* Allow only one VAP for the urtwn driver. */ 2980 if (!TAILQ_EMPTY(&ic->ic_vaps)) 2981 return NULL; 2982 2983 /* Allocate the vap and setup. */ 2984 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 2985 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 2986 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 2987 kmem_free(vap, sizeof(struct ieee80211vap)); 2988 return NULL; 2989 } 2990 2991 printf ("vap_create: after vap_setup\n"); 2992 2993 /* Local setup */ 2994 vap->iv_reset = urtwn_reset; 2995 2996 ifp = vap->iv_ifp; 2997 ifp->if_init = urtwn_init; 2998 ifp->if_ioctl = urtwn_ioctl; 2999 ifp->if_start = urtwn_start; 3000 ifp->if_watchdog = urtwn_watchdog; 3001 IFQ_SET_READY(&ifp->if_snd); 3002 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3003 3004 /* NNN needed ??? */ 3005 /* if_attach(ifp); */ 3006 3007 /* Override state transition machine. */ 3008 sc->sc_newstate = vap->iv_newstate; 3009 vap->iv_newstate = urtwn_newstate; 3010 3011 /* Finish setup */ 3012 ieee80211_vap_attach(vap, urtwn_media_change, 3013 ieee80211_media_status, macaddr); 3014 ic->ic_opmode = opmode; 3015 3016 return vap; 3017 } 3018 3019 static void 3020 urtwn_vap_delete(struct ieee80211vap *vap) 3021 { 3022 struct ifnet *ifp = vap->iv_ifp; 3023 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3024 3025 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3026 3027 urtwn_stop(ifp, 0); 3028 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3029 bpf_detach(ifp); 3030 if_detach(ifp); 3031 kmem_free(vap, sizeof(struct ieee80211vap)); 3032 } 3033 3034 static int 3035 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3036 { 3037 3038 struct ieee80211vap *vap = ifp->if_softc; 3039 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3040 int s, error = 0; 3041 3042 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3043 device_xname(sc->sc_dev), __func__, cmd, data)); 3044 3045 s = splnet(); 3046 3047 switch (cmd) { 3048 case SIOCSIFFLAGS: 3049 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3050 break; 3051 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3052 case IFF_UP | IFF_RUNNING: 3053 break; 3054 case IFF_UP: 3055 urtwn_init(ifp); 3056 break; 3057 case IFF_RUNNING: 3058 urtwn_stop(ifp, 1); 3059 break; 3060 case 0: 3061 break; 3062 } 3063 break; 3064 3065 case SIOCADDMULTI: 3066 case SIOCDELMULTI: 3067 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3068 /* setup multicast filter, etc */ 3069 error = 0; 3070 } 3071 break; 3072 3073 default: 3074 error = ieee80211_ioctl(ifp, cmd, data); 3075 break; 3076 } 3077 if (error == ENETRESET) { 3078 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3079 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3080 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3081 urtwn_init(ifp); 3082 } 3083 error = 0; 3084 } 3085 3086 splx(s); 3087 3088 return error; 3089 } 3090 3091 static __inline int 3092 urtwn_power_on(struct urtwn_softc *sc) 3093 { 3094 3095 return sc->sc_power_on(sc); 3096 } 3097 3098 static int 3099 urtwn_r92c_power_on(struct urtwn_softc *sc) 3100 { 3101 uint32_t reg; 3102 int ntries; 3103 3104 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3105 3106 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3107 3108 /* Wait for autoload done bit. */ 3109 for (ntries = 0; ntries < 1000; ntries++) { 3110 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3111 break; 3112 DELAY(5); 3113 } 3114 if (ntries == 1000) { 3115 aprint_error_dev(sc->sc_dev, 3116 "timeout waiting for chip autoload\n"); 3117 return ETIMEDOUT; 3118 } 3119 3120 /* Unlock ISO/CLK/Power control register. */ 3121 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3122 /* Move SPS into PWM mode. */ 3123 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3124 DELAY(5); 3125 3126 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3127 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3128 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3129 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3130 DELAY(100); 3131 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3132 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3133 ~R92C_SYS_ISO_CTRL_MD2PP); 3134 } 3135 3136 /* Auto enable WLAN. */ 3137 urtwn_write_2(sc, R92C_APS_FSMCO, 3138 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3139 for (ntries = 0; ntries < 1000; ntries++) { 3140 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3141 R92C_APS_FSMCO_APFM_ONMAC)) 3142 break; 3143 DELAY(100); 3144 } 3145 if (ntries == 1000) { 3146 aprint_error_dev(sc->sc_dev, 3147 "timeout waiting for MAC auto ON\n"); 3148 return ETIMEDOUT; 3149 } 3150 3151 /* Enable radio, GPIO and LED functions. */ 3152 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3153 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3154 urtwn_write_2(sc, R92C_APS_FSMCO, 3155 R92C_APS_FSMCO_AFSM_HSUS | 3156 R92C_APS_FSMCO_PDN_EN | 3157 R92C_APS_FSMCO_PFM_ALDN); 3158 3159 /* Release RF digital isolation. */ 3160 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3161 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3162 3163 /* Initialize MAC. */ 3164 urtwn_write_1(sc, R92C_APSD_CTRL, 3165 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3166 for (ntries = 0; ntries < 200; ntries++) { 3167 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3168 R92C_APSD_CTRL_OFF_STATUS)) 3169 break; 3170 DELAY(5); 3171 } 3172 if (ntries == 200) { 3173 aprint_error_dev(sc->sc_dev, 3174 "timeout waiting for MAC initialization\n"); 3175 return ETIMEDOUT; 3176 } 3177 3178 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3179 reg = urtwn_read_2(sc, R92C_CR); 3180 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3181 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3182 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3183 R92C_CR_ENSEC; 3184 urtwn_write_2(sc, R92C_CR, reg); 3185 3186 urtwn_write_1(sc, 0xfe10, 0x19); 3187 return 0; 3188 } 3189 3190 static int 3191 urtwn_r92e_power_on(struct urtwn_softc *sc) 3192 { 3193 uint32_t reg; 3194 uint32_t val; 3195 int ntries; 3196 3197 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3198 3199 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3200 3201 /* Enable radio, GPIO and LED functions. */ 3202 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3203 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3204 urtwn_write_2(sc, R92C_APS_FSMCO, 3205 R92C_APS_FSMCO_AFSM_HSUS | 3206 R92C_APS_FSMCO_PDN_EN | 3207 R92C_APS_FSMCO_PFM_ALDN); 3208 3209 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3210 /* LDO. */ 3211 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3212 } 3213 else { 3214 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3215 R92C_SYS_SWR_CTRL2) & 0xffff); 3216 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3217 } 3218 3219 for (ntries = 0; ntries < 2; ntries++) { 3220 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3221 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3222 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3223 R92C_AFE_CTRL4)); 3224 } 3225 3226 /* Reset BB. */ 3227 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3228 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3229 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3230 3231 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3232 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3233 3234 /* Disable HWPDN. */ 3235 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3236 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3237 3238 /* Disable WL suspend. */ 3239 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3240 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3241 R92C_APS_FSMCO_AFSM_HSUS)); 3242 3243 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3244 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3245 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3246 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3247 for (ntries = 0; ntries < 10000; ntries++) { 3248 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3249 R92C_APS_FSMCO_APFM_ONMAC; 3250 if (val == 0x0) 3251 break; 3252 DELAY(10); 3253 } 3254 if (ntries == 10000) { 3255 aprint_error_dev(sc->sc_dev, 3256 "timeout waiting for chip power up\n"); 3257 return ETIMEDOUT; 3258 } 3259 3260 urtwn_write_2(sc, R92C_CR, 0x00); 3261 reg = urtwn_read_2(sc, R92C_CR); 3262 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3263 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3264 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3265 urtwn_write_2(sc, R92C_CR, reg); 3266 3267 return 0; 3268 } 3269 3270 static int 3271 urtwn_r88e_power_on(struct urtwn_softc *sc) 3272 { 3273 uint32_t reg; 3274 uint8_t val; 3275 int ntries; 3276 3277 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3278 3279 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3280 3281 /* Wait for power ready bit. */ 3282 for (ntries = 0; ntries < 5000; ntries++) { 3283 val = urtwn_read_1(sc, 0x6) & 0x2; 3284 if (val == 0x2) 3285 break; 3286 DELAY(10); 3287 } 3288 if (ntries == 5000) { 3289 aprint_error_dev(sc->sc_dev, 3290 "timeout waiting for chip power up\n"); 3291 return ETIMEDOUT; 3292 } 3293 3294 /* Reset BB. */ 3295 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3296 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3297 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3298 3299 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3300 3301 /* Disable HWPDN. */ 3302 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3303 3304 /* Disable WL suspend. */ 3305 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3306 3307 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3308 for (ntries = 0; ntries < 5000; ntries++) { 3309 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3310 break; 3311 DELAY(10); 3312 } 3313 if (ntries == 5000) 3314 return ETIMEDOUT; 3315 3316 /* Enable LDO normal mode. */ 3317 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3318 3319 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3320 urtwn_write_2(sc, R92C_CR, 0); 3321 reg = urtwn_read_2(sc, R92C_CR); 3322 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3323 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3324 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3325 urtwn_write_2(sc, R92C_CR, reg); 3326 3327 return 0; 3328 } 3329 3330 static int 3331 urtwn_llt_init(struct urtwn_softc *sc) 3332 { 3333 size_t i, page_count, pktbuf_count; 3334 uint32_t val; 3335 int error; 3336 3337 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3338 3339 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3340 3341 if (sc->chip & URTWN_CHIP_88E) 3342 page_count = R88E_TX_PAGE_COUNT; 3343 else if (sc->chip & URTWN_CHIP_92EU) 3344 page_count = R92E_TX_PAGE_COUNT; 3345 else 3346 page_count = R92C_TX_PAGE_COUNT; 3347 if (sc->chip & URTWN_CHIP_88E) 3348 pktbuf_count = R88E_TXPKTBUF_COUNT; 3349 else if (sc->chip & URTWN_CHIP_92EU) 3350 pktbuf_count = R88E_TXPKTBUF_COUNT; 3351 else 3352 pktbuf_count = R92C_TXPKTBUF_COUNT; 3353 3354 if (sc->chip & URTWN_CHIP_92EU) { 3355 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3356 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3357 DELAY(100); 3358 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3359 if (val & R92E_AUTO_LLT_EN) 3360 return EIO; 3361 return 0; 3362 } 3363 3364 /* Reserve pages [0; page_count]. */ 3365 for (i = 0; i < page_count; i++) { 3366 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3367 return error; 3368 } 3369 /* NB: 0xff indicates end-of-list. */ 3370 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3371 return error; 3372 /* 3373 * Use pages [page_count + 1; pktbuf_count - 1] 3374 * as ring buffer. 3375 */ 3376 for (++i; i < pktbuf_count - 1; i++) { 3377 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3378 return error; 3379 } 3380 /* Make the last page point to the beginning of the ring buffer. */ 3381 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3382 return error; 3383 } 3384 3385 static __unused void 3386 urtwn_fw_reset(struct urtwn_softc *sc) 3387 { 3388 uint16_t reg; 3389 int ntries; 3390 3391 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3392 3393 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3394 3395 /* Tell 8051 to reset itself. */ 3396 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3397 3398 /* Wait until 8051 resets by itself. */ 3399 for (ntries = 0; ntries < 100; ntries++) { 3400 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3401 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3402 return; 3403 DELAY(50); 3404 } 3405 /* Force 8051 reset. */ 3406 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3407 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3408 } 3409 3410 static void 3411 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3412 { 3413 uint16_t reg; 3414 3415 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3416 3417 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3418 3419 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3420 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3421 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3422 } 3423 DELAY(50); 3424 3425 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3426 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3427 DELAY(50); 3428 3429 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3430 DELAY(50); 3431 3432 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3433 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3434 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3435 } 3436 DELAY(50); 3437 3438 } 3439 3440 static int 3441 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3442 { 3443 uint32_t reg; 3444 int off, mlen, error = 0; 3445 3446 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3447 device_xname(sc->sc_dev), __func__, page, buf, len)); 3448 3449 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3450 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3451 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3452 3453 off = R92C_FW_START_ADDR; 3454 while (len > 0) { 3455 if (len > 196) 3456 mlen = 196; 3457 else if (len > 4) 3458 mlen = 4; 3459 else 3460 mlen = 1; 3461 error = urtwn_write_region(sc, off, buf, mlen); 3462 if (error != 0) 3463 break; 3464 off += mlen; 3465 buf += mlen; 3466 len -= mlen; 3467 } 3468 return error; 3469 } 3470 3471 static int 3472 urtwn_load_firmware(struct urtwn_softc *sc) 3473 { 3474 firmware_handle_t fwh; 3475 const struct r92c_fw_hdr *hdr; 3476 const char *name; 3477 u_char *fw, *ptr; 3478 size_t len; 3479 uint32_t reg; 3480 int mlen, ntries, page, error; 3481 3482 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3483 3484 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3485 3486 /* Read firmware image from the filesystem. */ 3487 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3488 name = "rtl8188eufw.bin"; 3489 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3490 name = "rtl8192eefw.bin"; 3491 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3492 URTWN_CHIP_UMC_A_CUT) 3493 name = "rtl8192cfwU.bin"; 3494 else 3495 name = "rtl8192cfw.bin"; 3496 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3497 aprint_error_dev(sc->sc_dev, 3498 "failed load firmware of file %s (error %d)\n", name, 3499 error); 3500 return error; 3501 } 3502 const size_t fwlen = len = firmware_get_size(fwh); 3503 fw = firmware_malloc(len); 3504 if (fw == NULL) { 3505 aprint_error_dev(sc->sc_dev, 3506 "failed to allocate firmware memory\n"); 3507 firmware_close(fwh); 3508 return ENOMEM; 3509 } 3510 error = firmware_read(fwh, 0, fw, len); 3511 firmware_close(fwh); 3512 if (error != 0) { 3513 aprint_error_dev(sc->sc_dev, 3514 "failed to read firmware (error %d)\n", error); 3515 firmware_free(fw, fwlen); 3516 return error; 3517 } 3518 3519 len = fwlen; 3520 ptr = fw; 3521 hdr = (const struct r92c_fw_hdr *)ptr; 3522 /* Check if there is a valid FW header and skip it. */ 3523 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3524 (le16toh(hdr->signature) >> 4) == 0x88e || 3525 (le16toh(hdr->signature) >> 4) == 0x92e || 3526 (le16toh(hdr->signature) >> 4) == 0x92c) { 3527 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3528 device_xname(sc->sc_dev), __func__, 3529 le16toh(hdr->version), le16toh(hdr->subversion), 3530 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3531 ptr += sizeof(*hdr); 3532 len -= sizeof(*hdr); 3533 } 3534 3535 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3536 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3537 ISSET(sc->chip, URTWN_CHIP_92EU)) 3538 urtwn_r88e_fw_reset(sc); 3539 else 3540 urtwn_fw_reset(sc); 3541 } 3542 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3543 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3544 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3545 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3546 R92C_SYS_FUNC_EN_CPUEN); 3547 } 3548 3549 /* download enabled */ 3550 urtwn_write_1(sc, R92C_MCUFWDL, 3551 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3552 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3553 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3554 3555 /* Reset the FWDL checksum. */ 3556 urtwn_write_1(sc, R92C_MCUFWDL, 3557 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3558 3559 DELAY(50); 3560 /* download firmware */ 3561 for (page = 0; len > 0; page++) { 3562 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3563 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3564 if (error != 0) { 3565 aprint_error_dev(sc->sc_dev, 3566 "could not load firmware page %d\n", page); 3567 goto fail; 3568 } 3569 ptr += mlen; 3570 len -= mlen; 3571 } 3572 3573 /* download disable */ 3574 urtwn_write_1(sc, R92C_MCUFWDL, 3575 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3576 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3577 3578 /* Wait for checksum report. */ 3579 for (ntries = 0; ntries < 1000; ntries++) { 3580 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3581 break; 3582 DELAY(5); 3583 } 3584 if (ntries == 1000) { 3585 aprint_error_dev(sc->sc_dev, 3586 "timeout waiting for checksum report\n"); 3587 error = ETIMEDOUT; 3588 goto fail; 3589 } 3590 3591 /* Wait for firmware readiness. */ 3592 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3593 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3594 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3595 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3596 ISSET(sc->chip, URTWN_CHIP_92EU)) 3597 urtwn_r88e_fw_reset(sc); 3598 for (ntries = 0; ntries < 1000; ntries++) { 3599 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3600 break; 3601 DELAY(5); 3602 } 3603 if (ntries == 1000) { 3604 aprint_error_dev(sc->sc_dev, 3605 "timeout waiting for firmware readiness\n"); 3606 error = ETIMEDOUT; 3607 goto fail; 3608 } 3609 fail: 3610 firmware_free(fw, fwlen); 3611 return error; 3612 } 3613 3614 static __inline int 3615 urtwn_dma_init(struct urtwn_softc *sc) 3616 { 3617 3618 return sc->sc_dma_init(sc); 3619 } 3620 3621 static int 3622 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3623 { 3624 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3625 uint32_t reg; 3626 int error; 3627 3628 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3629 3630 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3631 3632 /* Initialize LLT table. */ 3633 error = urtwn_llt_init(sc); 3634 if (error != 0) 3635 return error; 3636 3637 /* Get Tx queues to USB endpoints mapping. */ 3638 hashq = hasnq = haslq = 0; 3639 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3640 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3641 device_xname(sc->sc_dev), __func__, reg)); 3642 if (MS(reg, R92C_USB_EP_HQ) != 0) 3643 hashq = 1; 3644 if (MS(reg, R92C_USB_EP_NQ) != 0) 3645 hasnq = 1; 3646 if (MS(reg, R92C_USB_EP_LQ) != 0) 3647 haslq = 1; 3648 nqueues = hashq + hasnq + haslq; 3649 if (nqueues == 0) 3650 return EIO; 3651 /* Get the number of pages for each queue. */ 3652 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3653 /* The remaining pages are assigned to the high priority queue. */ 3654 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3655 3656 /* Set number of pages for normal priority queue. */ 3657 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3658 urtwn_write_4(sc, R92C_RQPN, 3659 /* Set number of pages for public queue. */ 3660 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3661 /* Set number of pages for high priority queue. */ 3662 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3663 /* Set number of pages for low priority queue. */ 3664 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3665 /* Load values. */ 3666 R92C_RQPN_LD); 3667 3668 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3669 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3670 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3671 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3672 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3673 3674 /* Set queue to USB pipe mapping. */ 3675 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3676 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3677 if (nqueues == 1) { 3678 if (hashq) { 3679 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3680 } else if (hasnq) { 3681 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3682 } else { 3683 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3684 } 3685 } else if (nqueues == 2) { 3686 /* All 2-endpoints configs have a high priority queue. */ 3687 if (!hashq) { 3688 return EIO; 3689 } 3690 if (hasnq) { 3691 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3692 } else { 3693 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3694 } 3695 } else { 3696 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3697 } 3698 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3699 3700 /* Set Tx/Rx transfer page boundary. */ 3701 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3702 3703 /* Set Tx/Rx transfer page size. */ 3704 urtwn_write_1(sc, R92C_PBP, 3705 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3706 return 0; 3707 } 3708 3709 static int 3710 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3711 { 3712 usb_interface_descriptor_t *id; 3713 uint32_t reg; 3714 int nqueues; 3715 int error; 3716 3717 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3718 3719 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3720 3721 /* Initialize LLT table. */ 3722 error = urtwn_llt_init(sc); 3723 if (error != 0) 3724 return error; 3725 3726 /* Get Tx queues to USB endpoints mapping. */ 3727 id = usbd_get_interface_descriptor(sc->sc_iface); 3728 nqueues = id->bNumEndpoints - 1; 3729 if (nqueues == 0) 3730 return EIO; 3731 3732 /* Set number of pages for normal priority queue. */ 3733 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3734 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3735 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3736 3737 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3738 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3739 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3740 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3741 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3742 3743 /* Set queue to USB pipe mapping. */ 3744 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3745 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3746 if (nqueues == 1) 3747 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3748 else if (nqueues == 2) 3749 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3750 else 3751 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3752 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3753 3754 /* Set Tx/Rx transfer page boundary. */ 3755 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3756 3757 /* Set Tx/Rx transfer page size. */ 3758 urtwn_write_1(sc, R92C_PBP, 3759 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3760 3761 return 0; 3762 } 3763 3764 static void 3765 urtwn_mac_init(struct urtwn_softc *sc) 3766 { 3767 size_t i; 3768 3769 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3770 3771 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3772 3773 /* Write MAC initialization values. */ 3774 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3775 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3776 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3777 rtl8188eu_mac[i].val); 3778 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3779 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3780 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3781 rtl8192eu_mac[i].val); 3782 } else { 3783 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3784 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3785 rtl8192cu_mac[i].val); 3786 } 3787 } 3788 3789 static void 3790 urtwn_bb_init(struct urtwn_softc *sc) 3791 { 3792 const struct urtwn_bb_prog *prog; 3793 uint32_t reg; 3794 uint8_t crystalcap; 3795 size_t i; 3796 3797 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3798 3799 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3800 3801 /* Enable BB and RF. */ 3802 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3803 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3804 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3805 R92C_SYS_FUNC_EN_DIO_RF); 3806 3807 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3808 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3809 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3810 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3811 } 3812 3813 urtwn_write_1(sc, R92C_RF_CTRL, 3814 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3815 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3816 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3817 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3818 3819 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3820 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3821 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3822 urtwn_write_1(sc, 0x15, 0xe9); 3823 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3824 } 3825 3826 /* Select BB programming based on board type. */ 3827 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3828 prog = &rtl8188eu_bb_prog; 3829 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3830 prog = &rtl8192eu_bb_prog; 3831 else if (!(sc->chip & URTWN_CHIP_92C)) { 3832 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3833 prog = &rtl8188ce_bb_prog; 3834 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3835 prog = &rtl8188ru_bb_prog; 3836 } else { 3837 prog = &rtl8188cu_bb_prog; 3838 } 3839 } else { 3840 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3841 prog = &rtl8192ce_bb_prog; 3842 } else { 3843 prog = &rtl8192cu_bb_prog; 3844 } 3845 } 3846 /* Write BB initialization values. */ 3847 for (i = 0; i < prog->count; i++) { 3848 /* additional delay depend on registers */ 3849 switch (prog->regs[i]) { 3850 case 0xfe: 3851 urtwn_delay_ms(sc, 50); 3852 break; 3853 case 0xfd: 3854 urtwn_delay_ms(sc, 5); 3855 break; 3856 case 0xfc: 3857 urtwn_delay_ms(sc, 1); 3858 break; 3859 case 0xfb: 3860 DELAY(50); 3861 break; 3862 case 0xfa: 3863 DELAY(5); 3864 break; 3865 case 0xf9: 3866 DELAY(1); 3867 break; 3868 } 3869 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3870 DELAY(1); 3871 } 3872 3873 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3874 /* 8192C 1T only configuration. */ 3875 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3876 reg = (reg & ~0x00000003) | 0x2; 3877 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3878 3879 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3880 reg = (reg & ~0x00300033) | 0x00200022; 3881 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3882 3883 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3884 reg = (reg & ~0xff000000) | (0x45 << 24); 3885 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3886 3887 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3888 reg = (reg & ~0x000000ff) | 0x23; 3889 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3890 3891 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3892 reg = (reg & ~0x00000030) | (1 << 4); 3893 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3894 3895 reg = urtwn_bb_read(sc, 0xe74); 3896 reg = (reg & ~0x0c000000) | (2 << 26); 3897 urtwn_bb_write(sc, 0xe74, reg); 3898 reg = urtwn_bb_read(sc, 0xe78); 3899 reg = (reg & ~0x0c000000) | (2 << 26); 3900 urtwn_bb_write(sc, 0xe78, reg); 3901 reg = urtwn_bb_read(sc, 0xe7c); 3902 reg = (reg & ~0x0c000000) | (2 << 26); 3903 urtwn_bb_write(sc, 0xe7c, reg); 3904 reg = urtwn_bb_read(sc, 0xe80); 3905 reg = (reg & ~0x0c000000) | (2 << 26); 3906 urtwn_bb_write(sc, 0xe80, reg); 3907 reg = urtwn_bb_read(sc, 0xe88); 3908 reg = (reg & ~0x0c000000) | (2 << 26); 3909 urtwn_bb_write(sc, 0xe88, reg); 3910 } 3911 3912 /* Write AGC values. */ 3913 for (i = 0; i < prog->agccount; i++) { 3914 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3915 DELAY(1); 3916 } 3917 3918 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3919 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3920 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3921 DELAY(1); 3922 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3923 DELAY(1); 3924 } 3925 3926 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3927 crystalcap = sc->r88e_rom[0xb9]; 3928 if (crystalcap == 0x00) 3929 crystalcap = 0x20; 3930 crystalcap &= 0x3f; 3931 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3932 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3933 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3934 crystalcap | crystalcap << 6)); 3935 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3936 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3937 crystalcap = sc->r88e_rom[0xb9]; 3938 if (crystalcap == 0xff) 3939 crystalcap = 0x20; 3940 crystalcap &= 0x3f; 3941 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3942 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3943 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3944 crystalcap | crystalcap << 6)); 3945 } else { 3946 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3947 R92C_HSSI_PARAM2_CCK_HIPWR) { 3948 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3949 } 3950 } 3951 } 3952 3953 static void 3954 urtwn_rf_init(struct urtwn_softc *sc) 3955 { 3956 const struct urtwn_rf_prog *prog; 3957 uint32_t reg, mask, saved; 3958 size_t i, j, idx; 3959 3960 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3961 3962 /* Select RF programming based on board type. */ 3963 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3964 prog = rtl8188eu_rf_prog; 3965 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3966 prog = rtl8192eu_rf_prog; 3967 else if (!(sc->chip & URTWN_CHIP_92C)) { 3968 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3969 prog = rtl8188ce_rf_prog; 3970 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3971 prog = rtl8188ru_rf_prog; 3972 } else { 3973 prog = rtl8188cu_rf_prog; 3974 } 3975 } else { 3976 prog = rtl8192ce_rf_prog; 3977 } 3978 3979 for (i = 0; i < sc->nrxchains; i++) { 3980 /* Save RF_ENV control type. */ 3981 idx = i / 2; 3982 mask = 0xffffU << ((i % 2) * 16); 3983 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3984 3985 /* Set RF_ENV enable. */ 3986 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3987 reg |= 0x100000; 3988 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3989 DELAY(50); 3990 3991 /* Set RF_ENV output high. */ 3992 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3993 reg |= 0x10; 3994 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3995 DELAY(50); 3996 3997 /* Set address and data lengths of RF registers. */ 3998 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3999 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4000 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4001 DELAY(50); 4002 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4003 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4004 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4005 DELAY(50); 4006 4007 /* Write RF initialization values for this chain. */ 4008 for (j = 0; j < prog[i].count; j++) { 4009 if (prog[i].regs[j] >= 0xf9 && 4010 prog[i].regs[j] <= 0xfe) { 4011 /* 4012 * These are fake RF registers offsets that 4013 * indicate a delay is required. 4014 */ 4015 urtwn_delay_ms(sc, 50); 4016 continue; 4017 } 4018 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4019 DELAY(5); 4020 } 4021 4022 /* Restore RF_ENV control type. */ 4023 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4024 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4025 } 4026 4027 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4028 URTWN_CHIP_UMC_A_CUT) { 4029 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4030 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4031 } 4032 4033 /* Cache RF register CHNLBW. */ 4034 for (i = 0; i < 2; i++) { 4035 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4036 } 4037 } 4038 4039 static void 4040 urtwn_cam_init(struct urtwn_softc *sc) 4041 { 4042 uint32_t content, command; 4043 uint8_t idx; 4044 size_t i; 4045 4046 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4047 4048 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4049 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4050 return; 4051 4052 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4053 content = (idx & 3) 4054 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4055 | R92C_CAM_VALID; 4056 4057 command = R92C_CAMCMD_POLLING 4058 | R92C_CAMCMD_WRITE 4059 | R92C_CAM_CTL0(idx); 4060 4061 urtwn_write_4(sc, R92C_CAMWRITE, content); 4062 urtwn_write_4(sc, R92C_CAMCMD, command); 4063 } 4064 4065 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4066 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4067 if (i == 0) { 4068 content = (idx & 3) 4069 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4070 | R92C_CAM_VALID; 4071 } else { 4072 content = 0; 4073 } 4074 4075 command = R92C_CAMCMD_POLLING 4076 | R92C_CAMCMD_WRITE 4077 | R92C_CAM_CTL0(idx) 4078 | i; 4079 4080 urtwn_write_4(sc, R92C_CAMWRITE, content); 4081 urtwn_write_4(sc, R92C_CAMCMD, command); 4082 } 4083 } 4084 4085 /* Invalidate all CAM entries. */ 4086 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4087 } 4088 4089 static void 4090 urtwn_pa_bias_init(struct urtwn_softc *sc) 4091 { 4092 uint8_t reg; 4093 size_t i; 4094 4095 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4096 4097 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4098 4099 for (i = 0; i < sc->nrxchains; i++) { 4100 if (sc->pa_setting & (1U << i)) 4101 continue; 4102 4103 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4104 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4105 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4106 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4107 } 4108 if (!(sc->pa_setting & 0x10)) { 4109 reg = urtwn_read_1(sc, 0x16); 4110 reg = (reg & ~0xf0) | 0x90; 4111 urtwn_write_1(sc, 0x16, reg); 4112 } 4113 } 4114 4115 static void 4116 urtwn_rxfilter_init(struct urtwn_softc *sc) 4117 { 4118 4119 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4120 4121 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4122 4123 /* Initialize Rx filter. */ 4124 /* TODO: use better filter for monitor mode. */ 4125 urtwn_write_4(sc, R92C_RCR, 4126 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4127 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4128 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4129 /* Accept all multicast frames. */ 4130 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4131 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4132 /* Accept all management frames. */ 4133 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4134 /* Reject all control frames. */ 4135 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4136 /* Accept all data frames. */ 4137 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4138 } 4139 4140 static void 4141 urtwn_edca_init(struct urtwn_softc *sc) 4142 { 4143 4144 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4145 4146 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4147 4148 /* set spec SIFS (used in NAV) */ 4149 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4150 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4151 4152 /* set SIFS CCK/OFDM */ 4153 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4154 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4155 4156 /* TXOP */ 4157 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4158 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4159 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4160 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4161 } 4162 4163 static void 4164 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4165 uint16_t power[URTWN_RIDX_COUNT]) 4166 { 4167 uint32_t reg; 4168 4169 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4170 __func__, chain)); 4171 4172 /* Write per-CCK rate Tx power. */ 4173 if (chain == 0) { 4174 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4175 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4176 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4177 4178 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4179 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4180 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4181 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4182 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4183 } else { 4184 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4185 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4186 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4187 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4188 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4189 4190 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4191 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4192 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4193 } 4194 /* Write per-OFDM rate Tx power. */ 4195 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4196 SM(R92C_TXAGC_RATE06, power[ 4]) | 4197 SM(R92C_TXAGC_RATE09, power[ 5]) | 4198 SM(R92C_TXAGC_RATE12, power[ 6]) | 4199 SM(R92C_TXAGC_RATE18, power[ 7])); 4200 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4201 SM(R92C_TXAGC_RATE24, power[ 8]) | 4202 SM(R92C_TXAGC_RATE36, power[ 9]) | 4203 SM(R92C_TXAGC_RATE48, power[10]) | 4204 SM(R92C_TXAGC_RATE54, power[11])); 4205 /* Write per-MCS Tx power. */ 4206 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4207 SM(R92C_TXAGC_MCS00, power[12]) | 4208 SM(R92C_TXAGC_MCS01, power[13]) | 4209 SM(R92C_TXAGC_MCS02, power[14]) | 4210 SM(R92C_TXAGC_MCS03, power[15])); 4211 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4212 SM(R92C_TXAGC_MCS04, power[16]) | 4213 SM(R92C_TXAGC_MCS05, power[17]) | 4214 SM(R92C_TXAGC_MCS06, power[18]) | 4215 SM(R92C_TXAGC_MCS07, power[19])); 4216 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4217 SM(R92C_TXAGC_MCS08, power[20]) | 4218 SM(R92C_TXAGC_MCS09, power[21]) | 4219 SM(R92C_TXAGC_MCS10, power[22]) | 4220 SM(R92C_TXAGC_MCS11, power[23])); 4221 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4222 SM(R92C_TXAGC_MCS12, power[24]) | 4223 SM(R92C_TXAGC_MCS13, power[25]) | 4224 SM(R92C_TXAGC_MCS14, power[26]) | 4225 SM(R92C_TXAGC_MCS15, power[27])); 4226 } 4227 4228 static void 4229 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4230 uint16_t power[URTWN_RIDX_COUNT]) 4231 { 4232 struct r92c_rom *rom = &sc->rom; 4233 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4234 const struct urtwn_txpwr *base; 4235 int ridx, group; 4236 4237 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4238 device_xname(sc->sc_dev), __func__, chain, chan)); 4239 4240 /* Determine channel group. */ 4241 if (chan <= 3) { 4242 group = 0; 4243 } else if (chan <= 9) { 4244 group = 1; 4245 } else { 4246 group = 2; 4247 } 4248 4249 /* Get original Tx power based on board type and RF chain. */ 4250 if (!(sc->chip & URTWN_CHIP_92C)) { 4251 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4252 base = &rtl8188ru_txagc[chain]; 4253 } else { 4254 base = &rtl8192cu_txagc[chain]; 4255 } 4256 } else { 4257 base = &rtl8192cu_txagc[chain]; 4258 } 4259 4260 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4261 if (sc->regulatory == 0) { 4262 for (ridx = 0; ridx <= 3; ridx++) { 4263 power[ridx] = base->pwr[0][ridx]; 4264 } 4265 } 4266 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4267 if (sc->regulatory == 3) { 4268 power[ridx] = base->pwr[0][ridx]; 4269 /* Apply vendor limits. */ 4270 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4271 maxpow = rom->ht40_max_pwr[group]; 4272 } else { 4273 maxpow = rom->ht20_max_pwr[group]; 4274 } 4275 maxpow = (maxpow >> (chain * 4)) & 0xf; 4276 if (power[ridx] > maxpow) { 4277 power[ridx] = maxpow; 4278 } 4279 } else if (sc->regulatory == 1) { 4280 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4281 power[ridx] = base->pwr[group][ridx]; 4282 } 4283 } else if (sc->regulatory != 2) { 4284 power[ridx] = base->pwr[0][ridx]; 4285 } 4286 } 4287 4288 /* Compute per-CCK rate Tx power. */ 4289 cckpow = rom->cck_tx_pwr[chain][group]; 4290 for (ridx = 0; ridx <= 3; ridx++) { 4291 power[ridx] += cckpow; 4292 if (power[ridx] > R92C_MAX_TX_PWR) { 4293 power[ridx] = R92C_MAX_TX_PWR; 4294 } 4295 } 4296 4297 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4298 if (sc->ntxchains > 1) { 4299 /* Apply reduction for 2 spatial streams. */ 4300 diff = rom->ht40_2s_tx_pwr_diff[group]; 4301 diff = (diff >> (chain * 4)) & 0xf; 4302 htpow = (htpow > diff) ? htpow - diff : 0; 4303 } 4304 4305 /* Compute per-OFDM rate Tx power. */ 4306 diff = rom->ofdm_tx_pwr_diff[group]; 4307 diff = (diff >> (chain * 4)) & 0xf; 4308 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4309 for (ridx = 4; ridx <= 11; ridx++) { 4310 power[ridx] += ofdmpow; 4311 if (power[ridx] > R92C_MAX_TX_PWR) { 4312 power[ridx] = R92C_MAX_TX_PWR; 4313 } 4314 } 4315 4316 /* Compute per-MCS Tx power. */ 4317 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4318 diff = rom->ht20_tx_pwr_diff[group]; 4319 diff = (diff >> (chain * 4)) & 0xf; 4320 htpow += diff; /* HT40->HT20 correction. */ 4321 } 4322 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4323 power[ridx] += htpow; 4324 if (power[ridx] > R92C_MAX_TX_PWR) { 4325 power[ridx] = R92C_MAX_TX_PWR; 4326 } 4327 } 4328 #ifdef URTWN_DEBUG 4329 if (urtwn_debug & DBG_RF) { 4330 /* Dump per-rate Tx power values. */ 4331 printf("%s: %s: Tx power for chain %zd:\n", 4332 device_xname(sc->sc_dev), __func__, chain); 4333 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4334 printf("%s: %s: Rate %d = %u\n", 4335 device_xname(sc->sc_dev), __func__, ridx, 4336 power[ridx]); 4337 } 4338 } 4339 #endif 4340 } 4341 4342 void 4343 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4344 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4345 { 4346 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4347 const struct urtwn_r88e_txpwr *base; 4348 int ridx, group; 4349 4350 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4351 device_xname(sc->sc_dev), __func__, chain, chan)); 4352 4353 /* Determine channel group. */ 4354 if (chan <= 2) 4355 group = 0; 4356 else if (chan <= 5) 4357 group = 1; 4358 else if (chan <= 8) 4359 group = 2; 4360 else if (chan <= 11) 4361 group = 3; 4362 else if (chan <= 13) 4363 group = 4; 4364 else 4365 group = 5; 4366 4367 /* Get original Tx power based on board type and RF chain. */ 4368 base = &rtl8188eu_txagc[chain]; 4369 4370 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4371 if (sc->regulatory == 0) { 4372 for (ridx = 0; ridx <= 3; ridx++) 4373 power[ridx] = base->pwr[0][ridx]; 4374 } 4375 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4376 if (sc->regulatory == 3) 4377 power[ridx] = base->pwr[0][ridx]; 4378 else if (sc->regulatory == 1) { 4379 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4380 power[ridx] = base->pwr[group][ridx]; 4381 } else if (sc->regulatory != 2) 4382 power[ridx] = base->pwr[0][ridx]; 4383 } 4384 4385 /* Compute per-CCK rate Tx power. */ 4386 cckpow = sc->cck_tx_pwr[group]; 4387 for (ridx = 0; ridx <= 3; ridx++) { 4388 power[ridx] += cckpow; 4389 if (power[ridx] > R92C_MAX_TX_PWR) 4390 power[ridx] = R92C_MAX_TX_PWR; 4391 } 4392 4393 htpow = sc->ht40_tx_pwr[group]; 4394 4395 /* Compute per-OFDM rate Tx power. */ 4396 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4397 for (ridx = 4; ridx <= 11; ridx++) { 4398 power[ridx] += ofdmpow; 4399 if (power[ridx] > R92C_MAX_TX_PWR) 4400 power[ridx] = R92C_MAX_TX_PWR; 4401 } 4402 4403 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4404 for (ridx = 12; ridx <= 27; ridx++) { 4405 power[ridx] += bw20pow; 4406 if (power[ridx] > R92C_MAX_TX_PWR) 4407 power[ridx] = R92C_MAX_TX_PWR; 4408 } 4409 } 4410 4411 static void 4412 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4413 { 4414 uint16_t power[URTWN_RIDX_COUNT]; 4415 size_t i; 4416 4417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4418 4419 for (i = 0; i < sc->ntxchains; i++) { 4420 /* Compute per-rate Tx power values. */ 4421 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4422 ISSET(sc->chip, URTWN_CHIP_92EU)) 4423 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4424 else 4425 urtwn_get_txpower(sc, i, chan, ht40m, power); 4426 /* Write per-rate Tx power values to hardware. */ 4427 urtwn_write_txpower(sc, i, power); 4428 } 4429 } 4430 4431 static void 4432 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4433 { 4434 struct ieee80211com *ic = &sc->sc_ic; 4435 u_int chan; 4436 size_t i; 4437 4438 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4439 4440 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4441 __func__, chan)); 4442 4443 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4444 4445 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4446 chan += 2; 4447 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4448 chan -= 2; 4449 } 4450 4451 /* Set Tx power for this new channel. */ 4452 urtwn_set_txpower(sc, chan, ht40m); 4453 4454 for (i = 0; i < sc->nrxchains; i++) { 4455 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4456 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4457 } 4458 4459 if (ht40m) { 4460 /* Is secondary channel below or above primary? */ 4461 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4462 uint32_t reg; 4463 4464 urtwn_write_1(sc, R92C_BWOPMODE, 4465 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4466 4467 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4468 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4469 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4470 4471 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4472 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4473 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4474 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4475 4476 /* Set CCK side band. */ 4477 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4478 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4479 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4480 4481 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4482 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4483 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4484 4485 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4486 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4487 ~R92C_FPGA0_ANAPARAM2_CBW20); 4488 4489 reg = urtwn_bb_read(sc, 0x818); 4490 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4491 urtwn_bb_write(sc, 0x818, reg); 4492 4493 /* Select 40MHz bandwidth. */ 4494 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4495 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4496 } else { 4497 urtwn_write_1(sc, R92C_BWOPMODE, 4498 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4499 4500 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4501 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4502 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4503 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4504 4505 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4506 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4507 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4508 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4509 R92C_FPGA0_ANAPARAM2_CBW20); 4510 } 4511 4512 /* Select 20MHz bandwidth. */ 4513 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4514 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4515 (ISSET(sc->chip, URTWN_CHIP_88E) || 4516 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4517 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4518 } 4519 } 4520 4521 static void 4522 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4523 { 4524 4525 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4526 __func__, inited)); 4527 4528 uint32_t addaBackup[16], iqkBackup[4], piMode; 4529 4530 #ifdef notyet 4531 uint32_t odfm0_agccore_regs[3]; 4532 uint32_t ant_regs[3]; 4533 uint32_t rf_regs[8]; 4534 #endif 4535 uint32_t reg0, reg1, reg2; 4536 int i, attempt; 4537 4538 #ifdef notyet 4539 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4540 R92E_STBC_SETTING + 2)); 4541 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4542 /* Save AGCCORE regs. */ 4543 for (i = 0; i < sc->nrxchains; i++) { 4544 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4545 R92C_OFDM0_AGCCORE1(i)); 4546 } 4547 #endif 4548 /* Save BB regs. */ 4549 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4550 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4551 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4552 4553 /* Save adda regs to be restored when finished. */ 4554 for (i = 0; i < __arraycount(addaReg); i++) 4555 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4556 /* Save mac regs. */ 4557 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4558 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4559 iqkBackup[2] = urtwn_read_1(sc, R92C_USTIME_TSF); 4560 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4561 4562 #ifdef notyet 4563 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4564 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4565 4566 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4567 for (i = 0; i < sc->nrxchains; i++) 4568 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4569 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4570 #endif 4571 4572 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4573 R92C_HSSI_PARAM1_PI); 4574 if (piMode == 0) { 4575 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4576 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4577 R92C_HSSI_PARAM1_PI); 4578 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4579 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4580 R92C_HSSI_PARAM1_PI); 4581 } 4582 4583 attempt = 1; 4584 4585 next_attempt: 4586 4587 /* Set mac regs for calibration. */ 4588 for (i = 0; i < __arraycount(addaReg); i++) { 4589 urtwn_bb_write(sc, addaReg[i], 4590 addaReg[__arraycount(addaReg) - 1]); 4591 } 4592 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4593 R92C_CCK0_AFESETTING)); 4594 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4595 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4596 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4597 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4598 4599 if (sc->ntxchains > 1) 4600 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4601 4602 urtwn_write_1(sc, R92C_TXPAUSE, (~TP_STOPBECON) & TP_STOPALL); 4603 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4604 ~R92C_BCN_CTRL_EN_BCN)); 4605 urtwn_write_1(sc, R92C_USTIME_TSF, (iqkBackup[2] & ~0x8)); 4606 4607 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4608 ~R92C_GPIO_MUXCFG_ENBT)); 4609 4610 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4611 4612 if (sc->ntxchains > 1) 4613 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4614 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4615 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4616 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4617 4618 /* Restore BB regs. */ 4619 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4620 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4621 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4622 4623 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4624 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4625 if (sc->nrxchains > 1) 4626 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4627 4628 if (attempt-- > 0) 4629 goto next_attempt; 4630 4631 /* Restore mode. */ 4632 if (piMode == 0) { 4633 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4634 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4635 ~R92C_HSSI_PARAM1_PI); 4636 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4637 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4638 ~R92C_HSSI_PARAM1_PI); 4639 } 4640 4641 #ifdef notyet 4642 for (i = 0; i < sc->nrxchains; i++) { 4643 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4644 odfm0_agccore_regs[i]); 4645 } 4646 #endif 4647 4648 /* Restore adda regs. */ 4649 for (i = 0; i < __arraycount(addaReg); i++) 4650 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4651 /* Restore mac regs. */ 4652 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4653 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4654 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4655 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4656 4657 #ifdef notyet 4658 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4659 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4660 4661 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4662 for (i = 0; i < sc->nrxchains; i++) 4663 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4664 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4665 #endif 4666 } 4667 4668 static void 4669 urtwn_lc_calib(struct urtwn_softc *sc) 4670 { 4671 uint32_t rf_ac[2]; 4672 uint8_t txmode; 4673 size_t i; 4674 4675 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4676 4677 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4678 4679 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4680 if ((txmode & 0x70) != 0) { 4681 /* Disable all continuous Tx. */ 4682 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4683 4684 /* Set RF mode to standby mode. */ 4685 for (i = 0; i < sc->nrxchains; i++) { 4686 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4687 urtwn_rf_write(sc, i, R92C_RF_AC, 4688 RW(rf_ac[i], R92C_RF_AC_MODE, 4689 R92C_RF_AC_MODE_STANDBY)); 4690 } 4691 } else { 4692 /* Block all Tx queues. */ 4693 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4694 } 4695 /* Start calibration. */ 4696 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4697 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4698 4699 /* Give calibration the time to complete. */ 4700 urtwn_delay_ms(sc, 100); 4701 4702 /* Restore configuration. */ 4703 if ((txmode & 0x70) != 0) { 4704 /* Restore Tx mode. */ 4705 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4706 /* Restore RF mode. */ 4707 for (i = 0; i < sc->nrxchains; i++) { 4708 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4709 } 4710 } else { 4711 /* Unblock all Tx queues. */ 4712 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4713 } 4714 } 4715 4716 static void 4717 urtwn_temp_calib(struct urtwn_softc *sc) 4718 { 4719 int temp, t_meter_reg; 4720 4721 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4722 4723 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4724 4725 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4726 t_meter_reg = R92C_RF_T_METER; 4727 else 4728 t_meter_reg = R92E_RF_T_METER; 4729 4730 if (sc->thcal_state == 0) { 4731 /* Start measuring temperature. */ 4732 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4733 device_xname(sc->sc_dev), __func__)); 4734 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4735 sc->thcal_state = 1; 4736 return; 4737 } 4738 sc->thcal_state = 0; 4739 4740 /* Read measured temperature. */ 4741 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4742 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4743 __func__, temp)); 4744 if (temp == 0) /* Read failed, skip. */ 4745 return; 4746 4747 /* 4748 * Redo LC calibration if temperature changed significantly since 4749 * last calibration. 4750 */ 4751 if (sc->thcal_lctemp == 0) { 4752 /* First LC calibration is performed in urtwn_init(). */ 4753 sc->thcal_lctemp = temp; 4754 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4755 DPRINTFN(DBG_RF, 4756 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4757 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4758 temp)); 4759 urtwn_lc_calib(sc); 4760 /* Record temperature of last LC calibration. */ 4761 sc->thcal_lctemp = temp; 4762 } 4763 } 4764 4765 static int 4766 urtwn_init(struct ifnet *ifp) 4767 { 4768 struct urtwn_softc *sc = ifp->if_softc; 4769 struct ieee80211com *ic = &sc->sc_ic; 4770 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4771 struct urtwn_rx_data *data; 4772 uint32_t reg; 4773 size_t i; 4774 int error; 4775 4776 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4777 4778 urtwn_stop(ifp, 0); 4779 4780 mutex_enter(&sc->sc_write_mtx); 4781 4782 mutex_enter(&sc->sc_task_mtx); 4783 /* Init host async commands ring. */ 4784 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4785 mutex_exit(&sc->sc_task_mtx); 4786 4787 mutex_enter(&sc->sc_fwcmd_mtx); 4788 /* Init firmware commands ring. */ 4789 sc->fwcur = 0; 4790 mutex_exit(&sc->sc_fwcmd_mtx); 4791 4792 /* Allocate Tx/Rx buffers. */ 4793 error = urtwn_alloc_rx_list(sc); 4794 if (error != 0) { 4795 aprint_error_dev(sc->sc_dev, 4796 "could not allocate Rx buffers\n"); 4797 goto fail; 4798 } 4799 error = urtwn_alloc_tx_list(sc); 4800 if (error != 0) { 4801 aprint_error_dev(sc->sc_dev, 4802 "could not allocate Tx buffers\n"); 4803 goto fail; 4804 } 4805 4806 /* Power on adapter. */ 4807 error = urtwn_power_on(sc); 4808 if (error != 0) 4809 goto fail; 4810 4811 /* Initialize DMA. */ 4812 error = urtwn_dma_init(sc); 4813 if (error != 0) 4814 goto fail; 4815 4816 /* Set info size in Rx descriptors (in 64-bit words). */ 4817 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4818 4819 /* Init interrupts. */ 4820 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4821 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4822 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4823 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4824 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4825 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4826 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4827 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4828 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4829 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4830 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4831 } 4832 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4833 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4834 } else { 4835 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4836 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4837 } 4838 4839 /* Set MAC address. */ 4840 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 4841 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 4842 4843 /* Set initial network type. */ 4844 reg = urtwn_read_4(sc, R92C_CR); 4845 switch (ic->ic_opmode) { 4846 case IEEE80211_M_STA: 4847 default: 4848 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4849 break; 4850 4851 case IEEE80211_M_IBSS: 4852 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4853 break; 4854 } 4855 urtwn_write_4(sc, R92C_CR, reg); 4856 4857 /* Set response rate */ 4858 reg = urtwn_read_4(sc, R92C_RRSR); 4859 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4860 urtwn_write_4(sc, R92C_RRSR, reg); 4861 4862 /* SIFS (used in NAV) */ 4863 urtwn_write_2(sc, R92C_SPEC_SIFS, 4864 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4865 4866 /* Set short/long retry limits. */ 4867 urtwn_write_2(sc, R92C_RL, 4868 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4869 4870 /* Initialize EDCA parameters. */ 4871 urtwn_edca_init(sc); 4872 4873 /* Setup rate fallback. */ 4874 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4875 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4876 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4877 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4878 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4879 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4880 } 4881 4882 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4883 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4884 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4885 /* Set ACK timeout. */ 4886 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4887 4888 /* Setup USB aggregation. */ 4889 /* Tx */ 4890 reg = urtwn_read_4(sc, R92C_TDECTRL); 4891 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4892 urtwn_write_4(sc, R92C_TDECTRL, reg); 4893 /* Rx */ 4894 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4895 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4896 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4897 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4898 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4899 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4900 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4901 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4902 ISSET(sc->chip, URTWN_CHIP_92EU)) 4903 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4904 else 4905 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4906 4907 /* Initialize beacon parameters. */ 4908 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4909 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4910 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRIVER_EARLY_INT_TIME); 4911 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_DMA_ATIME_INT_TIME); 4912 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4913 4914 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4915 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4916 /* Setup AMPDU aggregation. */ 4917 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4918 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4919 urtwn_write_2(sc, 0x4ca, 0x0708); 4920 4921 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4922 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4923 } 4924 4925 /* Load 8051 microcode. */ 4926 error = urtwn_load_firmware(sc); 4927 if (error != 0) 4928 goto fail; 4929 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4930 4931 /* Initialize MAC/BB/RF blocks. */ 4932 /* 4933 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4934 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4935 * XXX: This setting should be removed from rtl8192cu_mac[]. 4936 */ 4937 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4938 urtwn_rxfilter_init(sc); // reset R92C_RCR 4939 urtwn_bb_init(sc); 4940 urtwn_rf_init(sc); 4941 4942 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4943 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4944 urtwn_write_2(sc, R92C_CR, 4945 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4946 R92C_CR_MACRXEN); 4947 } 4948 4949 /* Turn CCK and OFDM blocks on. */ 4950 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4951 reg |= R92C_RFMOD_CCK_EN; 4952 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4953 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4954 reg |= R92C_RFMOD_OFDM_EN; 4955 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4956 4957 /* Clear per-station keys table. */ 4958 urtwn_cam_init(sc); 4959 4960 /* Enable hardware sequence numbering. */ 4961 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4962 4963 /* Perform LO and IQ calibrations. */ 4964 urtwn_iq_calib(sc, sc->iqk_inited); 4965 sc->iqk_inited = true; 4966 4967 /* Perform LC calibration. */ 4968 urtwn_lc_calib(sc); 4969 4970 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4971 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4972 /* Fix USB interference issue. */ 4973 urtwn_write_1(sc, 0xfe40, 0xe0); 4974 urtwn_write_1(sc, 0xfe41, 0x8d); 4975 urtwn_write_1(sc, 0xfe42, 0x80); 4976 urtwn_write_4(sc, 0x20c, 0xfd0320); 4977 4978 urtwn_pa_bias_init(sc); 4979 } 4980 4981 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4982 !(sc->chip & URTWN_CHIP_92EU)) { 4983 /* 1T1R */ 4984 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4985 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4986 } 4987 4988 /* Initialize GPIO setting. */ 4989 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4990 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4991 4992 /* Fix for lower temperature. */ 4993 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4994 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4995 urtwn_write_1(sc, 0x15, 0xe9); 4996 4997 /* Set default channel. */ 4998 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4999 5000 /* Queue Rx xfers. */ 5001 for (size_t j = 0; j < sc->rx_npipe; j++) { 5002 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5003 data = &sc->rx_data[j][i]; 5004 usbd_setup_xfer(data->xfer, data, data->buf, 5005 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5006 urtwn_rxeof); 5007 error = usbd_transfer(data->xfer); 5008 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5009 error != USBD_IN_PROGRESS)) 5010 goto fail; 5011 } 5012 } 5013 5014 /* We're ready to go. */ 5015 ifp->if_flags &= ~IFF_OACTIVE; 5016 ifp->if_flags |= IFF_RUNNING; 5017 sc->sc_running = true; 5018 5019 mutex_exit(&sc->sc_write_mtx); 5020 5021 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5022 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5023 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5024 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5025 urtwn_wait_async(sc); 5026 5027 return 0; 5028 5029 fail: 5030 mutex_exit(&sc->sc_write_mtx); 5031 5032 urtwn_stop(ifp, 1); 5033 return error; 5034 } 5035 5036 static void 5037 urtwn_stop(struct ifnet *ifp, int disable) 5038 { 5039 struct urtwn_softc *sc = ifp->if_softc; 5040 struct ieee80211com *ic = &sc->sc_ic; 5041 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5042 size_t i; 5043 int s; 5044 5045 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5046 5047 s = splusb(); 5048 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5049 urtwn_wait_async(sc); 5050 splx(s); 5051 5052 sc->tx_timer = 0; 5053 ifp->if_timer = 0; 5054 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5055 5056 callout_stop(&sc->sc_scan_to); 5057 callout_stop(&sc->sc_calib_to); 5058 5059 /* Abort Tx. */ 5060 for (i = 0; i < sc->tx_npipe; i++) { 5061 if (sc->tx_pipe[i] != NULL) 5062 usbd_abort_pipe(sc->tx_pipe[i]); 5063 } 5064 5065 /* Stop Rx pipe. */ 5066 for (i = 0; i < sc->rx_npipe; i++) { 5067 if (sc->rx_pipe[i] != NULL) 5068 usbd_abort_pipe(sc->rx_pipe[i]); 5069 } 5070 5071 /* Free Tx/Rx buffers. */ 5072 urtwn_free_tx_list(sc); 5073 urtwn_free_rx_list(sc); 5074 5075 sc->sc_running = false; 5076 if (disable) 5077 urtwn_chip_stop(sc); 5078 } 5079 5080 static int 5081 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5082 { 5083 struct ifnet *ifp = vap->iv_ifp; 5084 struct urtwn_softc *sc = ifp->if_softc; 5085 struct ieee80211com *ic = &sc->sc_ic; 5086 5087 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5088 return ENETRESET; 5089 5090 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5091 5092 return 0; 5093 } 5094 5095 static void 5096 urtwn_chip_stop(struct urtwn_softc *sc) 5097 { 5098 uint32_t reg; 5099 bool disabled = true; 5100 5101 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5102 5103 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5104 return; 5105 5106 mutex_enter(&sc->sc_write_mtx); 5107 5108 /* 5109 * RF Off Sequence 5110 */ 5111 /* Pause MAC TX queue */ 5112 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5113 5114 /* Disable RF */ 5115 urtwn_rf_write(sc, 0, 0, 0); 5116 5117 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5118 5119 /* Reset BB state machine */ 5120 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5121 R92C_SYS_FUNC_EN_USBD | 5122 R92C_SYS_FUNC_EN_USBA | 5123 R92C_SYS_FUNC_EN_BB_GLB_RST); 5124 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5125 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5126 5127 /* 5128 * Reset digital sequence 5129 */ 5130 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5131 /* Reset MCU ready status */ 5132 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5133 /* If firmware in ram code, do reset */ 5134 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5135 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5136 ISSET(sc->chip, URTWN_CHIP_92EU)) 5137 urtwn_r88e_fw_reset(sc); 5138 else 5139 urtwn_fw_reset(sc); 5140 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5141 } 5142 } 5143 5144 /* Reset MAC and Enable 8051 */ 5145 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5146 5147 /* Reset MCU ready status */ 5148 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5149 5150 if (disabled) { 5151 /* Disable MAC clock */ 5152 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5153 /* Disable AFE PLL */ 5154 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5155 /* Gated AFE DIG_CLOCK */ 5156 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5157 /* Isolated digital to PON */ 5158 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5159 } 5160 5161 /* 5162 * Pull GPIO PIN to balance level and LED control 5163 */ 5164 /* 1. Disable GPIO[7:0] */ 5165 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5166 5167 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5168 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5169 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5170 5171 /* Disable GPIO[10:8] */ 5172 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5173 5174 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5175 reg |= (((reg & 0x000f) << 4) | 0x0780); 5176 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5177 5178 /* Disable LED0 & 1 */ 5179 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5180 5181 /* 5182 * Reset digital sequence 5183 */ 5184 if (disabled) { 5185 /* Disable ELDR clock */ 5186 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5187 /* Isolated ELDR to PON */ 5188 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5189 } 5190 5191 /* 5192 * Disable analog sequence 5193 */ 5194 if (disabled) { 5195 /* Disable A15 power */ 5196 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5197 /* Disable digital core power */ 5198 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5199 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5200 ~R92C_LDOV12D_CTRL_LDV12_EN); 5201 } 5202 5203 /* Enter PFM mode */ 5204 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5205 5206 /* Set USB suspend */ 5207 urtwn_write_2(sc, R92C_APS_FSMCO, 5208 R92C_APS_FSMCO_APDM_HOST | 5209 R92C_APS_FSMCO_AFSM_HSUS | 5210 R92C_APS_FSMCO_PFM_ALDN); 5211 5212 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5213 5214 mutex_exit(&sc->sc_write_mtx); 5215 } 5216 5217 static void 5218 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5219 { 5220 if (sc->sc_running == false) 5221 DELAY(ms * 1000); 5222 else 5223 usbd_delay_ms(sc->sc_udev, ms); 5224 } 5225 5226 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 5227 5228 #ifdef _MODULE 5229 #include "ioconf.c" 5230 #endif 5231 5232 static int 5233 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5234 { 5235 int error = 0; 5236 5237 switch (cmd) { 5238 case MODULE_CMD_INIT: 5239 #ifdef _MODULE 5240 error = config_init_component(cfdriver_ioconf_urtwn, 5241 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5242 #endif 5243 return error; 5244 case MODULE_CMD_FINI: 5245 #ifdef _MODULE 5246 error = config_fini_component(cfdriver_ioconf_urtwn, 5247 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5248 #endif 5249 return error; 5250 default: 5251 return ENOTTY; 5252 } 5253 } 5254
Indexes created Thu Oct 02 14:10:14 GMT 2025