if_urtwn.c revision 1.59.2.8
1 /* $NetBSD: if_urtwn.c,v 1.59.2.8 2019/06/26 16:51:29 phil Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.8 2019/06/26 16:51:29 phil Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 216 /* URTWN_RTL8192EU */ 217 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 218 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 219 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 220 }; 221 #undef URTWN_DEV 222 #undef URTWN_RTL8188E_DEV 223 #undef URTWN_RTL8192EU_DEV 224 225 /* urtwn data */ 226 static const uint8_t urtwn_chan_2ghz[] = 227 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 228 229 230 static int urtwn_match(device_t, cfdata_t, void *); 231 static void urtwn_attach(device_t, device_t, void *); 232 static int urtwn_detach(device_t, int); 233 static int urtwn_activate(device_t, enum devact); 234 235 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 236 urtwn_attach, urtwn_detach, urtwn_activate); 237 238 static int urtwn_open_pipes(struct urtwn_softc *); 239 static void urtwn_close_pipes(struct urtwn_softc *); 240 static int urtwn_alloc_rx_list(struct urtwn_softc *); 241 static void urtwn_free_rx_list(struct urtwn_softc *); 242 static int urtwn_alloc_tx_list(struct urtwn_softc *); 243 static void urtwn_free_tx_list(struct urtwn_softc *); 244 static void urtwn_task(void *); 245 static void urtwn_do_async(struct urtwn_softc *, 246 void (*)(struct urtwn_softc *, void *), void *, int); 247 static void urtwn_wait_async(struct urtwn_softc *); 248 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 249 int); 250 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 251 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 252 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 253 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 254 int); 255 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 256 int); 257 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 258 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 259 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 260 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 261 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 262 uint32_t); 263 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 264 uint32_t); 265 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 266 uint32_t); 267 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 268 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 269 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 270 static void urtwn_efuse_read(struct urtwn_softc *); 271 static void urtwn_efuse_switch_power(struct urtwn_softc *); 272 static int urtwn_read_chipid(struct urtwn_softc *); 273 #ifdef URTWN_DEBUG 274 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 275 #endif 276 static void urtwn_read_rom(struct urtwn_softc *); 277 static void urtwn_r88e_read_rom(struct urtwn_softc *); 278 static int urtwn_media_change(struct ifnet *); 279 static int urtwn_ra_init(struct ieee80211vap *); 280 static int urtwn_get_nettype(struct urtwn_softc *); 281 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 282 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 283 static void urtwn_set_led(struct urtwn_softc *, int, int); 284 static void urtwn_calib_to(void *); 285 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 286 static void urtwn_next_scan(void *); 287 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 288 int); 289 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 290 static int urtwn_wme_update(struct ieee80211com *); 291 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 292 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 293 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 294 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 295 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 296 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 297 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 298 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 299 struct ieee80211_node *, struct urtwn_tx_data *); 300 static struct urtwn_tx_data * 301 urtwn_get_tx_data(struct urtwn_softc *, size_t); 302 static void urtwn_start(struct ifnet *); 303 static void urtwn_watchdog(struct ifnet *); 304 static int urtwn_r92c_power_on(struct urtwn_softc *); 305 static int urtwn_r92e_power_on(struct urtwn_softc *); 306 static int urtwn_r88e_power_on(struct urtwn_softc *); 307 static int urtwn_llt_init(struct urtwn_softc *); 308 static void urtwn_fw_reset(struct urtwn_softc *); 309 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 310 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 311 static int urtwn_load_firmware(struct urtwn_softc *); 312 static int urtwn_r92c_dma_init(struct urtwn_softc *); 313 static int urtwn_r88e_dma_init(struct urtwn_softc *); 314 static void urtwn_mac_init(struct urtwn_softc *); 315 static void urtwn_bb_init(struct urtwn_softc *); 316 static void urtwn_rf_init(struct urtwn_softc *); 317 static void urtwn_cam_init(struct urtwn_softc *); 318 static void urtwn_pa_bias_init(struct urtwn_softc *); 319 static void urtwn_rxfilter_init(struct urtwn_softc *); 320 static void urtwn_edca_init(struct urtwn_softc *); 321 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 322 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 323 uint16_t[]); 324 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 325 u_int, uint16_t[]); 326 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 327 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 328 u_int); 329 static void urtwn_iq_calib(struct urtwn_softc *, bool); 330 static void urtwn_lc_calib(struct urtwn_softc *); 331 static void urtwn_temp_calib(struct urtwn_softc *); 332 static int urtwn_init(struct ifnet *); 333 static void urtwn_stop(struct ifnet *, int); 334 static int urtwn_reset(struct ieee80211vap *, u_long); 335 static void urtwn_chip_stop(struct urtwn_softc *); 336 static void urtwn_newassoc(struct ieee80211_node *, int); 337 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 338 /* Functions for wifi refresh */ 339 static struct ieee80211vap * 340 urtwn_vap_create(struct ieee80211com *, 341 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 342 const uint8_t [IEEE80211_ADDR_LEN], 343 const uint8_t [IEEE80211_ADDR_LEN]); 344 static void urtwn_vap_delete(struct ieee80211vap *); 345 static int urtwn_ioctl(struct ifnet *, u_long, void *); 346 static void urtwn_parent(struct ieee80211com *); 347 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 348 struct ieee80211_channel []); 349 static void urtwn_scan_start(struct ieee80211com *); 350 static void urtwn_scan_end(struct ieee80211com *); 351 static void urtwn_set_channel(struct ieee80211com *); 352 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 353 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 354 const struct ieee80211_bpf_params *); 355 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 356 357 /* Aliases. */ 358 #define urtwn_bb_write urtwn_write_4 359 #define urtwn_bb_read urtwn_read_4 360 361 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 362 363 static const uint16_t addaReg[] = { 364 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 365 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 366 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 367 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 368 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 369 }; 370 371 static int 372 urtwn_match(device_t parent, cfdata_t match, void *aux) 373 { 374 struct usb_attach_arg *uaa = aux; 375 376 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 377 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 378 } 379 380 static void 381 urtwn_attach(device_t parent, device_t self, void *aux) 382 { 383 struct urtwn_softc *sc = device_private(self); 384 struct ieee80211com *ic = &sc->sc_ic; 385 struct usb_attach_arg *uaa = aux; 386 char *devinfop; 387 const struct urtwn_dev *dev; 388 usb_device_request_t req; 389 // NNN loop below size_t i; 390 int error; 391 392 sc->sc_dev = self; 393 sc->sc_udev = uaa->uaa_device; 394 395 /* Name the ic. */ 396 ic->ic_name = "urtwn"; 397 398 /* Driver Send queue, separate from the if send queue*/ 399 sc->sc_sendq.ifq_maxlen = 32; 400 /* NNN how should this be initialized? */ 401 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 402 sc->sc_sendq.ifq_len = 0; 403 sc->sc_sendq.ifq_drops = 0; 404 IFQ_LOCK_INIT(&sc->sc_sendq); 405 406 sc->chip = 0; 407 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 408 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 409 SET(sc->chip, URTWN_CHIP_88E); 410 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 411 SET(sc->chip, URTWN_CHIP_92EU); 412 413 aprint_naive("\n"); 414 aprint_normal("\n"); 415 416 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 417 418 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 419 aprint_normal_dev(self, "%s\n", devinfop); 420 usbd_devinfo_free(devinfop); 421 422 req.bmRequestType = UT_WRITE_DEVICE; 423 req.bRequest = UR_SET_FEATURE; 424 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 425 USETW(req.wIndex, UHF_PORT_SUSPEND); 426 USETW(req.wLength, 0); 427 428 (void) usbd_do_request(sc->sc_udev, &req, 0); 429 430 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 431 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 432 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 434 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 435 436 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 437 438 /* NNN make these callouts use a vap ... in vap create??? */ 439 callout_init(&sc->sc_scan_to, 0); 440 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 441 callout_init(&sc->sc_calib_to, 0); 442 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 443 444 error = usbd_set_config_no(sc->sc_udev, 1, 0); 445 if (error != 0) { 446 aprint_error_dev(self, "failed to set configuration" 447 ", err=%s\n", usbd_errstr(error)); 448 goto fail; 449 } 450 451 /* Get the first interface handle. */ 452 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 453 if (error != 0) { 454 aprint_error_dev(self, "could not get interface handle\n"); 455 goto fail; 456 } 457 458 error = urtwn_read_chipid(sc); 459 if (error != 0) { 460 aprint_error_dev(self, "unsupported test chip\n"); 461 goto fail; 462 } 463 464 /* Determine number of Tx/Rx chains. */ 465 if (sc->chip & URTWN_CHIP_92C) { 466 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 467 sc->nrxchains = 2; 468 } else if (sc->chip & URTWN_CHIP_92EU) { 469 sc->ntxchains = 2; 470 sc->nrxchains = 2; 471 } else { 472 sc->ntxchains = 1; 473 sc->nrxchains = 1; 474 } 475 476 if (ISSET(sc->chip, URTWN_CHIP_88E) || 477 ISSET(sc->chip, URTWN_CHIP_92EU)) 478 urtwn_r88e_read_rom(sc); 479 else 480 urtwn_read_rom(sc); 481 482 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 483 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 484 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 485 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 486 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 487 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 488 "8188CUS", sc->ntxchains, sc->nrxchains, 489 ether_sprintf(ic->ic_macaddr)); 490 491 error = urtwn_open_pipes(sc); 492 if (error != 0) { 493 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 494 goto fail; 495 } 496 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 497 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 498 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 499 500 /* 501 * Setup the 802.11 device. 502 */ 503 ic->ic_softc = sc; 504 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 505 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 506 507 /* Set device capabilities. */ 508 ic->ic_caps = 509 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 510 IEEE80211_C_IBSS | /* IBSS mode supported */ 511 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 512 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 513 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 514 IEEE80211_C_WME | /* 802.11e */ 515 IEEE80211_C_WPA; /* 802.11i */ 516 517 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 518 519 #ifdef should_delete_NNN 520 /* Set supported .11b and .11g channels (1 through 14). */ 521 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 522 for (i = 0; i < 14; i++) { 523 ic->ic_channels[i].ic_freq = 524 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 525 ic->ic_channels[i].ic_flags = 526 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 527 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 528 } 529 #else 530 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 531 ic->ic_channels); 532 #endif 533 /* XXX issues here ... Figure out proper attach and vap creation */ 534 ieee80211_ifattach(ic); 535 536 /* override default methods NNN Need more here? */ 537 ic->ic_newassoc = urtwn_newassoc; 538 ic->ic_wme.wme_update = urtwn_wme_update; 539 ic->ic_vap_create = urtwn_vap_create; 540 ic->ic_vap_delete = urtwn_vap_delete; 541 ic->ic_parent = urtwn_parent; 542 ic->ic_scan_start = urtwn_scan_start; 543 ic->ic_scan_end = urtwn_scan_end; 544 ic->ic_set_channel = urtwn_set_channel; 545 ic->ic_transmit = urtwn_transmit; 546 // ic->ic_send_mgmt = urtwn_send_mgmt; 547 ic->ic_raw_xmit = urtwn_raw_xmit; 548 ic->ic_getradiocaps = urtwn_getradiocaps; 549 550 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 551 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 552 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 553 554 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 555 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 556 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 557 558 ieee80211_announce(ic); 559 560 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 561 562 if (!pmf_device_register(self, NULL, NULL)) 563 aprint_error_dev(self, "couldn't establish power handler\n"); 564 565 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 566 567 /* Should be called via an IOCTL. Temp call here for now. */ 568 569 struct ieee80211vap *vap = 570 urtwn_vap_create(ic, device_xname(sc->sc_dev), 571 device_unit(sc->sc_dev), IEEE80211_M_STA, 572 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 573 574 if (vap == NULL) { 575 /* Didn't work ... now what! */ 576 printf ("NNN vap_create didn't work ...\n"); 577 ieee80211_ifdetach(ic); 578 goto fail; 579 } 580 581 return; 582 583 fail: 584 sc->sc_dying = 1; 585 aprint_error_dev(self, "attach failed\n"); 586 } 587 588 static int 589 urtwn_detach(device_t self, int flags) 590 { 591 struct urtwn_softc *sc = device_private(self); 592 struct ieee80211com *ic = &sc->sc_ic; 593 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 594 struct ifnet *ifp = vap->iv_ifp; 595 int s; 596 597 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 598 599 pmf_device_deregister(self); 600 601 s = splusb(); 602 603 sc->sc_dying = 1; 604 605 callout_halt(&sc->sc_scan_to, NULL); 606 callout_halt(&sc->sc_calib_to, NULL); 607 608 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 609 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 610 NULL); 611 urtwn_stop(ifp, 0); 612 // vap_detach(...) ?? 613 614 ieee80211_ifdetach(&sc->sc_ic); 615 616 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 617 urtwn_close_pipes(sc); 618 } 619 620 /* sendq destroy */ 621 IFQ_PURGE(&sc->sc_sendq); 622 IFQ_LOCK_DESTROY(&sc->sc_sendq); 623 624 splx(s); 625 626 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 627 628 callout_destroy(&sc->sc_scan_to); 629 callout_destroy(&sc->sc_calib_to); 630 631 mutex_destroy(&sc->sc_write_mtx); 632 mutex_destroy(&sc->sc_fwcmd_mtx); 633 mutex_destroy(&sc->sc_tx_mtx); 634 mutex_destroy(&sc->sc_rx_mtx); 635 mutex_destroy(&sc->sc_task_mtx); 636 637 return 0; 638 } 639 640 static int 641 urtwn_activate(device_t self, enum devact act) 642 { 643 struct urtwn_softc *sc = device_private(self); 644 645 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 646 647 switch (act) { 648 case DVACT_DEACTIVATE: 649 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 650 651 return 0; 652 default: 653 return EOPNOTSUPP; 654 } 655 } 656 657 static int 658 urtwn_open_pipes(struct urtwn_softc *sc) 659 { 660 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 661 static uint8_t epaddr[R92C_MAX_EPOUT]; 662 static uint8_t rxepaddr[R92C_MAX_EPIN]; 663 usb_interface_descriptor_t *id; 664 usb_endpoint_descriptor_t *ed; 665 size_t i, ntx = 0, nrx = 0; 666 int error; 667 668 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 669 670 /* Determine the number of bulk-out pipes. */ 671 id = usbd_get_interface_descriptor(sc->sc_iface); 672 for (i = 0; i < id->bNumEndpoints; i++) { 673 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 674 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 675 continue; 676 } 677 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 678 if (ntx < sizeof(epaddr)) 679 epaddr[ntx] = ed->bEndpointAddress; 680 ntx++; 681 } 682 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 683 if (nrx < sizeof(rxepaddr)) 684 rxepaddr[nrx] = ed->bEndpointAddress; 685 nrx++; 686 } 687 } 688 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 689 aprint_error_dev(sc->sc_dev, 690 "%zd: invalid number of Rx bulk pipes\n", nrx); 691 return EIO; 692 } 693 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 694 aprint_error_dev(sc->sc_dev, 695 "%zd: invalid number of Tx bulk pipes\n", ntx); 696 return EIO; 697 } 698 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 699 device_xname(sc->sc_dev), __func__, nrx, ntx)); 700 sc->rx_npipe = nrx; 701 sc->tx_npipe = ntx; 702 703 /* Open bulk-in pipe at address 0x81. */ 704 for (i = 0; i < nrx; i++) { 705 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 706 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 707 if (error != 0) { 708 aprint_error_dev(sc->sc_dev, 709 "could not open Rx bulk pipe 0x%02x: %d\n", 710 rxepaddr[i], error); 711 goto fail; 712 } 713 } 714 715 /* Open bulk-out pipes (up to 3). */ 716 for (i = 0; i < ntx; i++) { 717 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 718 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 719 if (error != 0) { 720 aprint_error_dev(sc->sc_dev, 721 "could not open Tx bulk pipe 0x%02x: %d\n", 722 epaddr[i], error); 723 goto fail; 724 } 725 } 726 727 /* Map 802.11 access categories to USB pipes. */ 728 sc->ac2idx[WME_AC_BK] = 729 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 730 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 731 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 732 733 fail: 734 if (error != 0) 735 urtwn_close_pipes(sc); 736 return error; 737 } 738 739 static void 740 urtwn_close_pipes(struct urtwn_softc *sc) 741 { 742 struct usbd_pipe *pipe; 743 size_t i; 744 745 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 746 747 /* Close Rx pipes. */ 748 CTASSERT(sizeof(pipe) == sizeof(void *)); 749 for (i = 0; i < sc->rx_npipe; i++) { 750 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 751 if (pipe != NULL) { 752 usbd_close_pipe(pipe); 753 } 754 } 755 756 /* Close Tx pipes. */ 757 for (i = 0; i < sc->tx_npipe; i++) { 758 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 759 if (pipe != NULL) { 760 usbd_close_pipe(pipe); 761 } 762 } 763 } 764 765 static int 766 urtwn_alloc_rx_list(struct urtwn_softc *sc) 767 { 768 struct urtwn_rx_data *data; 769 size_t i; 770 int error = 0; 771 772 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 773 774 for (size_t j = 0; j < sc->rx_npipe; j++) { 775 TAILQ_INIT(&sc->rx_free_list[j]); 776 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 777 data = &sc->rx_data[j][i]; 778 779 data->sc = sc; /* Backpointer for callbacks. */ 780 781 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 782 0, 0, &data->xfer); 783 if (error) { 784 aprint_error_dev(sc->sc_dev, 785 "could not allocate xfer\n"); 786 break; 787 } 788 789 data->buf = usbd_get_buffer(data->xfer); 790 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 791 } 792 } 793 if (error != 0) 794 urtwn_free_rx_list(sc); 795 return error; 796 } 797 798 static void 799 urtwn_free_rx_list(struct urtwn_softc *sc) 800 { 801 struct usbd_xfer *xfer; 802 size_t i; 803 804 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 805 806 /* NB: Caller must abort pipe first. */ 807 for (size_t j = 0; j < sc->rx_npipe; j++) { 808 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 809 CTASSERT(sizeof(xfer) == sizeof(void *)); 810 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 811 if (xfer != NULL) 812 usbd_destroy_xfer(xfer); 813 } 814 } 815 } 816 817 static int 818 urtwn_alloc_tx_list(struct urtwn_softc *sc) 819 { 820 struct urtwn_tx_data *data; 821 size_t i; 822 int error = 0; 823 824 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 825 826 mutex_enter(&sc->sc_tx_mtx); 827 for (size_t j = 0; j < sc->tx_npipe; j++) { 828 TAILQ_INIT(&sc->tx_free_list[j]); 829 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 830 data = &sc->tx_data[j][i]; 831 832 data->sc = sc; /* Backpointer for callbacks. */ 833 data->pidx = j; 834 835 error = usbd_create_xfer(sc->tx_pipe[j], 836 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 837 &data->xfer); 838 if (error) { 839 aprint_error_dev(sc->sc_dev, 840 "could not allocate xfer\n"); 841 goto fail; 842 } 843 844 data->buf = usbd_get_buffer(data->xfer); 845 846 /* Append this Tx buffer to our free list. */ 847 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 848 } 849 } 850 mutex_exit(&sc->sc_tx_mtx); 851 return 0; 852 853 fail: 854 urtwn_free_tx_list(sc); 855 mutex_exit(&sc->sc_tx_mtx); 856 return error; 857 } 858 859 static void 860 urtwn_free_tx_list(struct urtwn_softc *sc) 861 { 862 struct usbd_xfer *xfer; 863 size_t i; 864 865 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 866 867 /* NB: Caller must abort pipe first. */ 868 for (size_t j = 0; j < sc->tx_npipe; j++) { 869 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 870 CTASSERT(sizeof(xfer) == sizeof(void *)); 871 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 872 if (xfer != NULL) 873 usbd_destroy_xfer(xfer); 874 } 875 } 876 } 877 878 static int 879 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 880 struct ieee80211_node *ni) 881 { 882 struct urtwn_tx_data *data = 883 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 884 return urtwn_tx(sc, m, ni, data); 885 } 886 887 static void 888 urtwn_task(void *arg) 889 { 890 struct urtwn_softc *sc = arg; 891 struct ieee80211com *ic = &sc->sc_ic; 892 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 893 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 894 struct urtwn_host_cmd *cmd; 895 int s; 896 897 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 898 if (vap->iv_state == IEEE80211_S_RUN && 899 (ic->ic_opmode == IEEE80211_M_HOSTAP || 900 ic->ic_opmode == IEEE80211_M_IBSS)) { 901 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 902 if (m == NULL) { 903 aprint_error_dev(sc->sc_dev, 904 "could not allocate beacon"); 905 } 906 907 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 908 m_freem(m); 909 aprint_error_dev(sc->sc_dev, "could not send beacon"); 910 } 911 912 /* beacon is no longer needed */ 913 m_freem(m); 914 } 915 916 /* Process host commands. */ 917 s = splusb(); 918 mutex_spin_enter(&sc->sc_task_mtx); 919 while (ring->next != ring->cur) { 920 cmd = &ring->cmd[ring->next]; 921 mutex_spin_exit(&sc->sc_task_mtx); 922 splx(s); 923 /* Invoke callback with kernel lock held. */ 924 cmd->cb(sc, cmd->data); 925 s = splusb(); 926 mutex_spin_enter(&sc->sc_task_mtx); 927 ring->queued--; 928 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 929 } 930 mutex_spin_exit(&sc->sc_task_mtx); 931 wakeup(&sc->cmdq); 932 splx(s); 933 } 934 935 static void 936 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 937 void *arg, int len) 938 { 939 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 940 struct urtwn_host_cmd *cmd; 941 int s; 942 943 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 944 device_xname(sc->sc_dev), __func__, cb, arg, len)); 945 946 s = splusb(); 947 mutex_spin_enter(&sc->sc_task_mtx); 948 cmd = &ring->cmd[ring->cur]; 949 cmd->cb = cb; 950 KASSERT(len <= sizeof(cmd->data)); 951 memcpy(cmd->data, arg, len); 952 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 953 954 /* If there is no pending command already, schedule a task. */ 955 if (!sc->sc_dying && ++ring->queued == 1) { 956 mutex_spin_exit(&sc->sc_task_mtx); 957 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 958 } else 959 mutex_spin_exit(&sc->sc_task_mtx); 960 splx(s); 961 } 962 963 static void 964 urtwn_wait_async(struct urtwn_softc *sc) 965 { 966 967 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 968 969 /* Wait for all queued asynchronous commands to complete. */ 970 while (sc->cmdq.queued > 0) 971 tsleep(&sc->cmdq, 0, "endtask", 0); 972 } 973 974 static int 975 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 976 int len) 977 { 978 usb_device_request_t req; 979 usbd_status error; 980 981 KASSERT(mutex_owned(&sc->sc_write_mtx)); 982 983 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 984 req.bRequest = R92C_REQ_REGS; 985 USETW(req.wValue, addr); 986 USETW(req.wIndex, 0); 987 USETW(req.wLength, len); 988 error = usbd_do_request(sc->sc_udev, &req, buf); 989 if (error != USBD_NORMAL_COMPLETION) { 990 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 991 device_xname(sc->sc_dev), __func__, error, addr, len)); 992 } 993 return error; 994 } 995 996 static void 997 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 998 { 999 1000 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1001 device_xname(sc->sc_dev), __func__, addr, val)); 1002 1003 urtwn_write_region_1(sc, addr, &val, 1); 1004 } 1005 1006 static void 1007 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1008 { 1009 uint8_t buf[2]; 1010 1011 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1012 device_xname(sc->sc_dev), __func__, addr, val)); 1013 1014 buf[0] = (uint8_t)val; 1015 buf[1] = (uint8_t)(val >> 8); 1016 urtwn_write_region_1(sc, addr, buf, 2); 1017 } 1018 1019 static void 1020 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1021 { 1022 uint8_t buf[4]; 1023 1024 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1025 device_xname(sc->sc_dev), __func__, addr, val)); 1026 1027 buf[0] = (uint8_t)val; 1028 buf[1] = (uint8_t)(val >> 8); 1029 buf[2] = (uint8_t)(val >> 16); 1030 buf[3] = (uint8_t)(val >> 24); 1031 urtwn_write_region_1(sc, addr, buf, 4); 1032 } 1033 1034 static int 1035 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1036 { 1037 1038 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 1039 device_xname(sc->sc_dev), __func__, addr, len)); 1040 1041 return urtwn_write_region_1(sc, addr, buf, len); 1042 } 1043 1044 static int 1045 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1046 int len) 1047 { 1048 usb_device_request_t req; 1049 usbd_status error; 1050 1051 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1052 req.bRequest = R92C_REQ_REGS; 1053 USETW(req.wValue, addr); 1054 USETW(req.wIndex, 0); 1055 USETW(req.wLength, len); 1056 error = usbd_do_request(sc->sc_udev, &req, buf); 1057 if (error != USBD_NORMAL_COMPLETION) { 1058 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1059 device_xname(sc->sc_dev), __func__, error, addr, len)); 1060 } 1061 return error; 1062 } 1063 1064 static uint8_t 1065 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1066 { 1067 uint8_t val; 1068 1069 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1070 return 0xff; 1071 1072 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1073 device_xname(sc->sc_dev), __func__, addr, val)); 1074 return val; 1075 } 1076 1077 static uint16_t 1078 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1079 { 1080 uint8_t buf[2]; 1081 uint16_t val; 1082 1083 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1084 return 0xffff; 1085 1086 val = LE_READ_2(&buf[0]); 1087 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1088 device_xname(sc->sc_dev), __func__, addr, val)); 1089 return val; 1090 } 1091 1092 static uint32_t 1093 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1094 { 1095 uint8_t buf[4]; 1096 uint32_t val; 1097 1098 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1099 return 0xffffffff; 1100 1101 val = LE_READ_4(&buf[0]); 1102 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1103 device_xname(sc->sc_dev), __func__, addr, val)); 1104 return val; 1105 } 1106 1107 static int 1108 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1109 { 1110 struct r92c_fw_cmd cmd; 1111 uint8_t *cp; 1112 int fwcur; 1113 int ntries; 1114 1115 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1116 device_xname(sc->sc_dev), __func__, id, buf, len)); 1117 1118 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1119 1120 mutex_enter(&sc->sc_fwcmd_mtx); 1121 fwcur = sc->fwcur; 1122 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1123 mutex_exit(&sc->sc_fwcmd_mtx); 1124 1125 /* Wait for current FW box to be empty. */ 1126 for (ntries = 0; ntries < 100; ntries++) { 1127 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1128 break; 1129 DELAY(2000); 1130 } 1131 if (ntries == 100) { 1132 aprint_error_dev(sc->sc_dev, 1133 "could not send firmware command %d\n", id); 1134 return ETIMEDOUT; 1135 } 1136 1137 memset(&cmd, 0, sizeof(cmd)); 1138 KASSERT(len <= sizeof(cmd.msg)); 1139 memcpy(cmd.msg, buf, len); 1140 1141 /* Write the first word last since that will trigger the FW. */ 1142 cp = (uint8_t *)&cmd; 1143 cmd.id = id; 1144 if (len >= 4) { 1145 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1146 cmd.id |= R92C_CMD_FLAG_EXT; 1147 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1148 &cp[1], 2); 1149 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1150 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1151 (cp[5] << 24)); 1152 } else { 1153 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1154 &cp[4], 2); 1155 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1156 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1157 (cp[3] << 24)); 1158 } 1159 } else { 1160 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1161 } 1162 1163 return 0; 1164 } 1165 1166 static __inline void 1167 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1168 { 1169 1170 sc->sc_rf_write(sc, chain, addr, val); 1171 } 1172 1173 static void 1174 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1175 uint32_t val) 1176 { 1177 1178 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1179 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1180 } 1181 1182 static void 1183 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1184 uint32_t val) 1185 { 1186 1187 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1188 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1189 } 1190 1191 static void 1192 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1193 uint32_t val) 1194 { 1195 1196 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1197 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1198 } 1199 1200 static uint32_t 1201 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1202 { 1203 uint32_t reg[R92C_MAX_CHAINS], val; 1204 1205 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1206 if (chain != 0) { 1207 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1208 } 1209 1210 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1211 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1212 DELAY(1000); 1213 1214 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1215 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1216 R92C_HSSI_PARAM2_READ_EDGE); 1217 DELAY(1000); 1218 1219 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1220 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1221 DELAY(1000); 1222 1223 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1224 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1225 } else { 1226 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1227 } 1228 return MS(val, R92C_LSSI_READBACK_DATA); 1229 } 1230 1231 static int 1232 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1233 { 1234 int ntries; 1235 1236 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1237 1238 urtwn_write_4(sc, R92C_LLT_INIT, 1239 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1240 SM(R92C_LLT_INIT_ADDR, addr) | 1241 SM(R92C_LLT_INIT_DATA, data)); 1242 /* Wait for write operation to complete. */ 1243 for (ntries = 0; ntries < 20; ntries++) { 1244 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1245 R92C_LLT_INIT_OP_NO_ACTIVE) { 1246 /* Done */ 1247 return 0; 1248 } 1249 DELAY(5); 1250 } 1251 return ETIMEDOUT; 1252 } 1253 1254 static uint8_t 1255 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1256 { 1257 uint32_t reg; 1258 int ntries; 1259 1260 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1261 1262 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1263 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1264 reg &= ~R92C_EFUSE_CTRL_VALID; 1265 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1266 1267 /* Wait for read operation to complete. */ 1268 for (ntries = 0; ntries < 100; ntries++) { 1269 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1270 if (reg & R92C_EFUSE_CTRL_VALID) { 1271 /* Done */ 1272 return MS(reg, R92C_EFUSE_CTRL_DATA); 1273 } 1274 DELAY(5); 1275 } 1276 aprint_error_dev(sc->sc_dev, 1277 "could not read efuse byte at address 0x%04x\n", addr); 1278 return 0xff; 1279 } 1280 1281 static void 1282 urtwn_efuse_read(struct urtwn_softc *sc) 1283 { 1284 uint8_t *rom = (uint8_t *)&sc->rom; 1285 uint32_t reg; 1286 uint16_t addr = 0; 1287 uint8_t off, msk; 1288 size_t i; 1289 1290 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1291 1292 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1293 1294 urtwn_efuse_switch_power(sc); 1295 1296 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1297 while (addr < 512) { 1298 reg = urtwn_efuse_read_1(sc, addr); 1299 if (reg == 0xff) 1300 break; 1301 addr++; 1302 off = reg >> 4; 1303 msk = reg & 0xf; 1304 for (i = 0; i < 4; i++) { 1305 if (msk & (1U << i)) 1306 continue; 1307 1308 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1309 addr++; 1310 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1311 addr++; 1312 } 1313 } 1314 #ifdef URTWN_DEBUG 1315 if (urtwn_debug & DBG_INIT) { 1316 /* Dump ROM content. */ 1317 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1318 for (i = 0; i < (int)sizeof(sc->rom); i++) 1319 printf(":%02x", rom[i]); 1320 printf("\n"); 1321 } 1322 #endif 1323 } 1324 1325 static void 1326 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1327 { 1328 uint32_t reg; 1329 1330 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1331 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1332 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1333 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1334 } 1335 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1336 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1337 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1338 reg | R92C_SYS_FUNC_EN_ELDR); 1339 } 1340 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1341 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1342 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1343 urtwn_write_2(sc, R92C_SYS_CLKR, 1344 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1345 } 1346 } 1347 1348 static int 1349 urtwn_read_chipid(struct urtwn_softc *sc) 1350 { 1351 uint32_t reg; 1352 1353 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1354 1355 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1356 ISSET(sc->chip, URTWN_CHIP_92EU)) 1357 return 0; 1358 1359 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1360 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1361 /* test chip, not supported */ 1362 return EIO; 1363 } 1364 if (reg & R92C_SYS_CFG_TYPE_92C) { 1365 sc->chip |= URTWN_CHIP_92C; 1366 /* Check if it is a castrated 8192C. */ 1367 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1368 R92C_HPON_FSM_CHIP_BONDING_ID) == 1369 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1370 sc->chip |= URTWN_CHIP_92C_1T2R; 1371 } 1372 } 1373 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1374 sc->chip |= URTWN_CHIP_UMC; 1375 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1376 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1377 } 1378 } 1379 return 0; 1380 } 1381 1382 #ifdef URTWN_DEBUG 1383 static void 1384 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1385 { 1386 1387 aprint_normal_dev(sc->sc_dev, 1388 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1389 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1390 1391 aprint_normal_dev(sc->sc_dev, 1392 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1393 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1394 1395 aprint_normal_dev(sc->sc_dev, 1396 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1397 rp->macaddr[0], rp->macaddr[1], 1398 rp->macaddr[2], rp->macaddr[3], 1399 rp->macaddr[4], rp->macaddr[5]); 1400 1401 aprint_normal_dev(sc->sc_dev, 1402 "string %s, subcustomer_id 0x%x\n", 1403 rp->string, rp->subcustomer_id); 1404 1405 aprint_normal_dev(sc->sc_dev, 1406 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1407 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1408 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1409 1410 aprint_normal_dev(sc->sc_dev, 1411 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1412 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1413 rp->ht40_1s_tx_pwr[0][2], 1414 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1415 rp->ht40_1s_tx_pwr[1][2]); 1416 1417 aprint_normal_dev(sc->sc_dev, 1418 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1419 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1420 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1421 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1422 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1423 1424 aprint_normal_dev(sc->sc_dev, 1425 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1426 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1427 rp->ht20_tx_pwr_diff[2] & 0xf, 1428 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1429 rp->ht20_tx_pwr_diff[2] >> 4); 1430 1431 aprint_normal_dev(sc->sc_dev, 1432 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1433 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1434 rp->ofdm_tx_pwr_diff[2] & 0xf, 1435 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1436 rp->ofdm_tx_pwr_diff[2] >> 4); 1437 1438 aprint_normal_dev(sc->sc_dev, 1439 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1440 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1441 rp->ht40_max_pwr[2] & 0xf, 1442 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1443 rp->ht40_max_pwr[2] >> 4); 1444 1445 aprint_normal_dev(sc->sc_dev, 1446 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1447 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1448 rp->ht20_max_pwr[2] & 0xf, 1449 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1450 rp->ht20_max_pwr[2] >> 4); 1451 1452 aprint_normal_dev(sc->sc_dev, 1453 "xtal_calib %d, tssi %d %d, thermal %d\n", 1454 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1455 1456 aprint_normal_dev(sc->sc_dev, 1457 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1458 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1459 1460 aprint_normal_dev(sc->sc_dev, 1461 "channnel_plan %d, version %d customer_id 0x%x\n", 1462 rp->channel_plan, rp->version, rp->curstomer_id); 1463 } 1464 #endif 1465 1466 static void 1467 urtwn_read_rom(struct urtwn_softc *sc) 1468 { 1469 struct ieee80211com *ic = &sc->sc_ic; 1470 struct r92c_rom *rom = &sc->rom; 1471 1472 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1473 1474 mutex_enter(&sc->sc_write_mtx); 1475 1476 /* Read full ROM image. */ 1477 urtwn_efuse_read(sc); 1478 #ifdef URTWN_DEBUG 1479 if (urtwn_debug & DBG_REG) 1480 urtwn_dump_rom(sc, rom); 1481 #endif 1482 1483 /* XXX Weird but this is what the vendor driver does. */ 1484 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1485 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1486 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1487 1488 DPRINTFN(DBG_INIT, 1489 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1490 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1491 sc->board_type, sc->regulatory)); 1492 1493 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1494 1495 sc->sc_rf_write = urtwn_r92c_rf_write; 1496 sc->sc_power_on = urtwn_r92c_power_on; 1497 sc->sc_dma_init = urtwn_r92c_dma_init; 1498 1499 mutex_exit(&sc->sc_write_mtx); 1500 } 1501 1502 static void 1503 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1504 { 1505 struct ieee80211com *ic = &sc->sc_ic; 1506 uint8_t *rom = sc->r88e_rom; 1507 uint32_t reg; 1508 uint16_t addr = 0; 1509 uint8_t off, msk, tmp; 1510 int i; 1511 1512 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1513 1514 mutex_enter(&sc->sc_write_mtx); 1515 1516 off = 0; 1517 urtwn_efuse_switch_power(sc); 1518 1519 /* Read full ROM image. */ 1520 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1521 while (addr < 4096) { 1522 reg = urtwn_efuse_read_1(sc, addr); 1523 if (reg == 0xff) 1524 break; 1525 addr++; 1526 if ((reg & 0x1f) == 0x0f) { 1527 tmp = (reg & 0xe0) >> 5; 1528 reg = urtwn_efuse_read_1(sc, addr); 1529 if ((reg & 0x0f) != 0x0f) 1530 off = ((reg & 0xf0) >> 1) | tmp; 1531 addr++; 1532 } else 1533 off = reg >> 4; 1534 msk = reg & 0xf; 1535 for (i = 0; i < 4; i++) { 1536 if (msk & (1 << i)) 1537 continue; 1538 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1539 addr++; 1540 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1541 addr++; 1542 } 1543 } 1544 #ifdef URTWN_DEBUG 1545 if (urtwn_debug & DBG_REG) { 1546 } 1547 #endif 1548 1549 addr = 0x10; 1550 for (i = 0; i < 6; i++) 1551 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1552 for (i = 0; i < 5; i++) 1553 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1554 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1555 if (sc->bw20_tx_pwr_diff & 0x08) 1556 sc->bw20_tx_pwr_diff |= 0xf0; 1557 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1558 if (sc->ofdm_tx_pwr_diff & 0x08) 1559 sc->ofdm_tx_pwr_diff |= 0xf0; 1560 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1561 1562 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1563 1564 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1565 sc->sc_power_on = urtwn_r92e_power_on; 1566 sc->sc_rf_write = urtwn_r92e_rf_write; 1567 } else { 1568 sc->sc_power_on = urtwn_r88e_power_on; 1569 sc->sc_rf_write = urtwn_r88e_rf_write; 1570 } 1571 sc->sc_dma_init = urtwn_r88e_dma_init; 1572 1573 mutex_exit(&sc->sc_write_mtx); 1574 } 1575 1576 /* NNN Do we need to do something with this? */ 1577 1578 static __unused int 1579 urtwn_media_change(struct ifnet *ifp) 1580 { 1581 #ifdef URTWN_DEBUG 1582 struct ieee80211vap *vap = ifp->if_softc; 1583 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1584 #endif 1585 int error; 1586 1587 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1588 1589 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1590 return error; 1591 1592 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1593 (IFF_UP | IFF_RUNNING)) { 1594 urtwn_init(ifp); 1595 } 1596 return 0; 1597 } 1598 1599 /* 1600 * Initialize rate adaptation in firmware. 1601 */ 1602 static int 1603 urtwn_ra_init(struct ieee80211vap *vap) 1604 { 1605 static const uint8_t map[] = { 1606 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1607 }; 1608 struct ieee80211com *ic = vap->iv_ic; 1609 struct urtwn_softc *sc = ic->ic_softc; 1610 struct ieee80211_node *ni = vap->iv_bss; 1611 struct ieee80211_rateset *rs = &ni->ni_rates; 1612 1613 struct r92c_fw_cmd_macid_cfg cmd; 1614 uint32_t rates, basicrates; 1615 uint32_t rrsr_mask, rrsr_rate; 1616 uint8_t mode; 1617 size_t maxrate, maxbasicrate, i, j; 1618 int error; 1619 1620 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1621 1622 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1623 1624 /* Get normal and basic rates mask. */ 1625 rates = basicrates = 1; 1626 maxrate = maxbasicrate = 0; 1627 for (i = 0; i < rs->rs_nrates; i++) { 1628 /* Convert 802.11 rate to HW rate index. */ 1629 for (j = 0; j < __arraycount(map); j++) { 1630 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1631 break; 1632 } 1633 } 1634 if (j == __arraycount(map)) { 1635 /* Unknown rate, skip. */ 1636 continue; 1637 } 1638 1639 rates |= 1U << j; 1640 if (j > maxrate) { 1641 maxrate = j; 1642 } 1643 1644 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1645 basicrates |= 1U << j; 1646 if (j > maxbasicrate) { 1647 maxbasicrate = j; 1648 } 1649 } 1650 } 1651 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1652 mode = R92C_RAID_11B; 1653 } else { 1654 mode = R92C_RAID_11BG; 1655 } 1656 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1657 "maxrate=%zx, maxbasicrate=%zx\n", 1658 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1659 maxrate, maxbasicrate)); 1660 1661 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1662 maxbasicrate |= R92C_RATE_SHORTGI; 1663 maxrate |= R92C_RATE_SHORTGI; 1664 } 1665 1666 /* Set rates mask for group addressed frames. */ 1667 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1668 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1669 cmd.macid |= RTWN_MACID_SHORTGI; 1670 cmd.mask = htole32((mode << 28) | basicrates); 1671 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1672 if (error != 0) { 1673 aprint_error_dev(sc->sc_dev, 1674 "could not add broadcast station\n"); 1675 return error; 1676 } 1677 /* Set initial MRR rate. */ 1678 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1679 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1680 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1681 1682 /* Set rates mask for unicast frames. */ 1683 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1684 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1685 cmd.macid |= RTWN_MACID_SHORTGI; 1686 cmd.mask = htole32((mode << 28) | rates); 1687 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1688 if (error != 0) { 1689 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1690 return error; 1691 } 1692 /* Set initial MRR rate. */ 1693 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1694 __func__, maxrate)); 1695 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1696 1697 #if notyet 1698 /* NNN appears to have no fixed rate anywhere. */ 1699 rrsr_rate = ic->ic_fixed_rate; 1700 if (rrsr_rate == -1) 1701 #endif 1702 rrsr_rate = 11; 1703 1704 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1705 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1706 1707 #if notyet 1708 /* Indicate highest supported rate. */ 1709 ni->ni_txrate = rs->rs_nrates - 1; 1710 #endif 1711 return 0; 1712 } 1713 1714 static int 1715 urtwn_get_nettype(struct urtwn_softc *sc) 1716 { 1717 struct ieee80211com *ic = &sc->sc_ic; 1718 int type; 1719 1720 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1721 1722 switch (ic->ic_opmode) { 1723 case IEEE80211_M_STA: 1724 type = R92C_CR_NETTYPE_INFRA; 1725 break; 1726 1727 case IEEE80211_M_IBSS: 1728 type = R92C_CR_NETTYPE_ADHOC; 1729 break; 1730 1731 default: 1732 type = R92C_CR_NETTYPE_NOLINK; 1733 break; 1734 } 1735 1736 return type; 1737 } 1738 1739 static void 1740 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1741 { 1742 uint8_t reg; 1743 1744 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1745 __func__, type)); 1746 1747 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1748 1749 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1750 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1751 } 1752 1753 static void 1754 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1755 { 1756 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1757 struct ieee80211_node *ni = vap->iv_bss; 1758 uint64_t tsf; 1759 1760 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1761 1762 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1763 1764 /* Enable TSF synchronization. */ 1765 urtwn_write_1(sc, R92C_BCN_CTRL, 1766 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1767 1768 /* Correct TSF */ 1769 urtwn_write_1(sc, R92C_BCN_CTRL, 1770 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1771 1772 /* Set initial TSF. */ 1773 tsf = ni->ni_tstamp.tsf; 1774 tsf = le64toh(tsf); 1775 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1776 tsf -= IEEE80211_DUR_TU; 1777 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1778 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1779 1780 urtwn_write_1(sc, R92C_BCN_CTRL, 1781 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1782 } 1783 1784 static void 1785 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1786 { 1787 uint8_t reg; 1788 1789 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1790 __func__, led, on)); 1791 1792 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1793 1794 if (led == URTWN_LED_LINK) { 1795 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1796 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1797 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1798 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1799 (R92C_LEDCFG0_DIS << 1)); 1800 if (on) { 1801 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1802 R92E_LEDSON; 1803 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1804 } 1805 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1806 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1807 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1808 if (!on) { 1809 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1810 urtwn_write_1(sc, R92C_LEDCFG2, 1811 reg | R92C_LEDCFG0_DIS); 1812 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1813 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1814 reg & 0xfe); 1815 } 1816 } else { 1817 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1818 if (!on) { 1819 reg |= R92C_LEDCFG0_DIS; 1820 } 1821 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1822 } 1823 sc->ledlink = on; /* Save LED state. */ 1824 } 1825 } 1826 1827 static void 1828 urtwn_calib_to(void *arg) 1829 { 1830 struct urtwn_softc *sc = arg; 1831 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1832 1833 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1834 1835 if (sc->sc_dying) 1836 return; 1837 1838 /* Do it in a process context. */ 1839 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1840 } 1841 1842 /* ARGSUSED */ 1843 static void 1844 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1845 { 1846 struct ieee80211vap *vap = arg; 1847 struct r92c_fw_cmd_rssi cmd; 1848 struct r92e_fw_cmd_rssi cmde; 1849 1850 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1851 1852 if (vap->iv_state != IEEE80211_S_RUN) 1853 goto restart_timer; 1854 1855 mutex_enter(&sc->sc_write_mtx); 1856 if (sc->avg_pwdb != -1) { 1857 /* Indicate Rx signal strength to FW for rate adaptation. */ 1858 memset(&cmd, 0, sizeof(cmd)); 1859 memset(&cmde, 0, sizeof(cmde)); 1860 cmd.macid = 0; /* BSS. */ 1861 cmde.macid = 0; /* BSS. */ 1862 cmd.pwdb = sc->avg_pwdb; 1863 cmde.pwdb = sc->avg_pwdb; 1864 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1865 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1866 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1867 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1868 sizeof(cmd)); 1869 } else { 1870 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1871 sizeof(cmde)); 1872 } 1873 } 1874 1875 /* Do temperature compensation. */ 1876 urtwn_temp_calib(sc); 1877 mutex_exit(&sc->sc_write_mtx); 1878 1879 restart_timer: 1880 if (!sc->sc_dying) { 1881 /* Restart calibration timer. */ 1882 callout_schedule(&sc->sc_calib_to, hz); 1883 } 1884 } 1885 1886 static void 1887 urtwn_next_scan(void *arg) 1888 { 1889 printf ("NNN urtwn_next_scan called....\n"); 1890 #ifdef notyet 1891 struct urtwn_softc *sc = arg; 1892 int s; 1893 1894 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1895 1896 if (sc->sc_dying) 1897 return; 1898 1899 s = splnet(); 1900 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1901 ieee80211_next_scan(&sc->sc_ic); 1902 splx(s); 1903 #endif 1904 } 1905 1906 static void 1907 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1908 { 1909 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1910 ether_sprintf(ni->ni_macaddr))); 1911 1912 /* start with lowest Tx rate */ 1913 ni->ni_txrate = 0; 1914 } 1915 1916 #if OLDSTUFF 1917 static int 1918 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1919 { 1920 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1921 struct urtwn_cmd_newstate cmd; 1922 1923 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1924 device_xname(sc->sc_dev), __func__, 1925 ieee80211_state_name[nstate], nstate, arg)); 1926 1927 callout_stop(&sc->sc_scan_to); 1928 callout_stop(&sc->sc_calib_to); 1929 1930 /* Do it in a process context. */ 1931 cmd.state = nstate; 1932 cmd.arg = arg; 1933 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1934 return 0; 1935 } 1936 1937 static void 1938 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1939 { 1940 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1941 struct urtwn_cmd_newstate *cmd = arg; 1942 struct ieee80211com *ic = &sc->sc_ic; 1943 struct ieee80211_node *ni; 1944 enum ieee80211_state ostate = vap->iv_state; 1945 enum ieee80211_state nstate = cmd->state; 1946 uint32_t reg; 1947 uint8_t sifs_time, msr; 1948 int s; 1949 1950 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1951 device_xname(sc->sc_dev), __func__, 1952 ieee80211_state_name[ostate], ostate, 1953 ieee80211_state_name[nstate], nstate)); 1954 1955 s = splnet(); 1956 mutex_enter(&sc->sc_write_mtx); 1957 1958 callout_stop(&sc->sc_scan_to); 1959 callout_stop(&sc->sc_calib_to); 1960 1961 switch (ostate) { 1962 case IEEE80211_S_INIT: 1963 break; 1964 1965 case IEEE80211_S_SCAN: 1966 if (nstate != IEEE80211_S_SCAN) { 1967 /* 1968 * End of scanning 1969 */ 1970 /* flush 4-AC Queue after site_survey */ 1971 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1972 1973 /* Allow Rx from our BSSID only. */ 1974 urtwn_write_4(sc, R92C_RCR, 1975 urtwn_read_4(sc, R92C_RCR) | 1976 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1977 } 1978 break; 1979 1980 case IEEE80211_S_AUTH: 1981 case IEEE80211_S_ASSOC: 1982 break; 1983 1984 case IEEE80211_S_RUN: 1985 /* Turn link LED off. */ 1986 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1987 1988 /* Set media status to 'No Link'. */ 1989 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1990 1991 /* Stop Rx of data frames. */ 1992 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1993 1994 /* Reset TSF. */ 1995 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1996 1997 /* Disable TSF synchronization. */ 1998 urtwn_write_1(sc, R92C_BCN_CTRL, 1999 urtwn_read_1(sc, R92C_BCN_CTRL) | 2000 R92C_BCN_CTRL_DIS_TSF_UDT0); 2001 2002 /* Back to 20MHz mode */ 2003 urtwn_set_chan(sc, ic->ic_curchan, 2004 IEEE80211_HTINFO_2NDCHAN_NONE); 2005 2006 if (ic->ic_opmode == IEEE80211_M_IBSS || 2007 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2008 /* Stop BCN */ 2009 urtwn_write_1(sc, R92C_BCN_CTRL, 2010 urtwn_read_1(sc, R92C_BCN_CTRL) & 2011 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2012 } 2013 2014 /* Reset EDCA parameters. */ 2015 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2016 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2017 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2018 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2019 2020 /* flush all cam entries */ 2021 urtwn_cam_init(sc); 2022 break; 2023 case IEEE80211_S_CAC: 2024 case IEEE80211_S_CSA: 2025 case IEEE80211_S_SLEEP: 2026 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2027 /* NNN what do we do in these states? XXX */ 2028 break; 2029 } 2030 2031 switch (nstate) { 2032 case IEEE80211_S_INIT: 2033 /* Turn link LED off. */ 2034 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2035 break; 2036 2037 case IEEE80211_S_SCAN: 2038 if (ostate != IEEE80211_S_SCAN) { 2039 /* 2040 * Begin of scanning 2041 */ 2042 2043 /* Set gain for scanning. */ 2044 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2045 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2046 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2047 2048 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2049 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2050 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2051 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2052 } 2053 2054 /* Set media status to 'No Link'. */ 2055 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2056 2057 /* Allow Rx from any BSSID. */ 2058 urtwn_write_4(sc, R92C_RCR, 2059 urtwn_read_4(sc, R92C_RCR) & 2060 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2061 2062 /* Stop Rx of data frames. */ 2063 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2064 2065 /* Disable update TSF */ 2066 urtwn_write_1(sc, R92C_BCN_CTRL, 2067 urtwn_read_1(sc, R92C_BCN_CTRL) | 2068 R92C_BCN_CTRL_DIS_TSF_UDT0); 2069 } 2070 2071 /* Make link LED blink during scan. */ 2072 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2073 2074 /* Pause AC Tx queues. */ 2075 urtwn_write_1(sc, R92C_TXPAUSE, 2076 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2077 2078 urtwn_set_chan(sc, ic->ic_curchan, 2079 IEEE80211_HTINFO_2NDCHAN_NONE); 2080 2081 /* Start periodic scan. */ 2082 if (!sc->sc_dying) 2083 callout_schedule(&sc->sc_scan_to, hz / 5); 2084 break; 2085 2086 case IEEE80211_S_AUTH: 2087 /* Set initial gain under link. */ 2088 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2089 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2090 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2091 2092 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2093 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2094 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2095 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2096 } 2097 2098 /* Set media status to 'No Link'. */ 2099 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2100 2101 /* Allow Rx from any BSSID. */ 2102 urtwn_write_4(sc, R92C_RCR, 2103 urtwn_read_4(sc, R92C_RCR) & 2104 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2105 2106 urtwn_set_chan(sc, ic->ic_curchan, 2107 IEEE80211_HTINFO_2NDCHAN_NONE); 2108 break; 2109 2110 case IEEE80211_S_ASSOC: 2111 break; 2112 2113 case IEEE80211_S_RUN: 2114 ni = vap->iv_bss; 2115 2116 /* XXX: Set 20MHz mode */ 2117 urtwn_set_chan(sc, ic->ic_curchan, 2118 IEEE80211_HTINFO_2NDCHAN_NONE); 2119 2120 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2121 /* Back to 20MHz mode */ 2122 urtwn_set_chan(sc, ic->ic_curchan, 2123 IEEE80211_HTINFO_2NDCHAN_NONE); 2124 2125 /* Set media status to 'No Link'. */ 2126 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2127 2128 /* Enable Rx of data frames. */ 2129 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2130 2131 /* Allow Rx from any BSSID. */ 2132 urtwn_write_4(sc, R92C_RCR, 2133 urtwn_read_4(sc, R92C_RCR) & 2134 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2135 2136 /* Accept Rx data/control/management frames */ 2137 urtwn_write_4(sc, R92C_RCR, 2138 urtwn_read_4(sc, R92C_RCR) | 2139 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2140 2141 /* Turn link LED on. */ 2142 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2143 break; 2144 } 2145 2146 /* Set media status to 'Associated'. */ 2147 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2148 2149 /* Set BSSID. */ 2150 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2151 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2152 2153 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2154 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2155 } else { 2156 /* 802.11b/g */ 2157 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2158 } 2159 2160 /* Enable Rx of data frames. */ 2161 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2162 2163 /* Set beacon interval. */ 2164 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2165 2166 msr = urtwn_read_1(sc, R92C_MSR); 2167 msr &= R92C_MSR_MASK; 2168 switch (ic->ic_opmode) { 2169 case IEEE80211_M_STA: 2170 /* Allow Rx from our BSSID only. */ 2171 urtwn_write_4(sc, R92C_RCR, 2172 urtwn_read_4(sc, R92C_RCR) | 2173 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2174 2175 /* Enable TSF synchronization. */ 2176 urtwn_tsf_sync_enable(sc); 2177 2178 msr |= R92C_MSR_INFRA; 2179 break; 2180 case IEEE80211_M_HOSTAP: 2181 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2182 2183 /* Allow Rx from any BSSID. */ 2184 urtwn_write_4(sc, R92C_RCR, 2185 urtwn_read_4(sc, R92C_RCR) & 2186 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2187 2188 /* Reset TSF timer to zero. */ 2189 reg = urtwn_read_4(sc, R92C_TCR); 2190 reg &= ~0x01; 2191 urtwn_write_4(sc, R92C_TCR, reg); 2192 reg |= 0x01; 2193 urtwn_write_4(sc, R92C_TCR, reg); 2194 2195 msr |= R92C_MSR_AP; 2196 break; 2197 default: 2198 msr |= R92C_MSR_ADHOC; 2199 break; 2200 } 2201 urtwn_write_1(sc, R92C_MSR, msr); 2202 2203 sifs_time = 10; 2204 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2205 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2206 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2207 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2208 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2209 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2210 2211 /* Initialize rate adaptation. */ 2212 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2213 ISSET(sc->chip, URTWN_CHIP_92EU)) 2214 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2215 else 2216 urtwn_ra_init(vap); 2217 2218 /* Turn link LED on. */ 2219 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2220 2221 /* Reset average RSSI. */ 2222 sc->avg_pwdb = -1; 2223 2224 /* Reset temperature calibration state machine. */ 2225 sc->thcal_state = 0; 2226 sc->thcal_lctemp = 0; 2227 2228 /* Start periodic calibration. */ 2229 if (!sc->sc_dying) 2230 callout_schedule(&sc->sc_calib_to, hz); 2231 break; 2232 case IEEE80211_S_CAC: 2233 case IEEE80211_S_CSA: 2234 case IEEE80211_S_SLEEP: 2235 /* NNN what do we do in these states? XXX */ 2236 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2237 break; 2238 } 2239 /* newstate functions expect the ic to be locked. */ 2240 IEEE80211_LOCK(ic); 2241 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2242 IEEE80211_UNLOCK(ic); 2243 2244 mutex_exit(&sc->sc_write_mtx); 2245 splx(s); 2246 } 2247 #endif 2248 2249 static int 2250 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2251 { 2252 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2253 struct ieee80211com *ic = &sc->sc_ic; 2254 struct ieee80211_node *ni; 2255 enum ieee80211_state ostate = vap->iv_state; 2256 uint32_t reg; 2257 uint8_t sifs_time, msr; 2258 int s; 2259 int error; 2260 2261 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2262 device_xname(sc->sc_dev), __func__, 2263 ieee80211_state_name[ostate], ostate, 2264 ieee80211_state_name[nstate], nstate)); 2265 2266 s = splnet(); 2267 mutex_enter(&sc->sc_write_mtx); 2268 2269 callout_stop(&sc->sc_scan_to); 2270 callout_stop(&sc->sc_calib_to); 2271 2272 switch (ostate) { 2273 case IEEE80211_S_INIT: 2274 break; 2275 2276 case IEEE80211_S_SCAN: 2277 if (nstate != IEEE80211_S_SCAN) { 2278 /* 2279 * End of scanning 2280 */ 2281 /* flush 4-AC Queue after site_survey */ 2282 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2283 2284 /* Allow Rx from our BSSID only. */ 2285 urtwn_write_4(sc, R92C_RCR, 2286 urtwn_read_4(sc, R92C_RCR) | 2287 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2288 } 2289 break; 2290 2291 case IEEE80211_S_AUTH: 2292 case IEEE80211_S_ASSOC: 2293 break; 2294 2295 case IEEE80211_S_RUN: 2296 /* Turn link LED off. */ 2297 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2298 2299 /* Set media status to 'No Link'. */ 2300 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2301 2302 /* Stop Rx of data frames. */ 2303 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2304 2305 /* Reset TSF. */ 2306 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2307 2308 /* Disable TSF synchronization. */ 2309 urtwn_write_1(sc, R92C_BCN_CTRL, 2310 urtwn_read_1(sc, R92C_BCN_CTRL) | 2311 R92C_BCN_CTRL_DIS_TSF_UDT0); 2312 2313 /* Back to 20MHz mode */ 2314 urtwn_set_chan(sc, ic->ic_curchan, 2315 IEEE80211_HTINFO_2NDCHAN_NONE); 2316 2317 if (ic->ic_opmode == IEEE80211_M_IBSS || 2318 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2319 /* Stop BCN */ 2320 urtwn_write_1(sc, R92C_BCN_CTRL, 2321 urtwn_read_1(sc, R92C_BCN_CTRL) & 2322 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2323 } 2324 2325 /* Reset EDCA parameters. */ 2326 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2327 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2328 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2329 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2330 2331 /* flush all cam entries */ 2332 urtwn_cam_init(sc); 2333 break; 2334 case IEEE80211_S_CAC: 2335 case IEEE80211_S_CSA: 2336 case IEEE80211_S_SLEEP: 2337 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2338 /* NNN what do we do in these states? XXX */ 2339 break; 2340 } 2341 2342 switch (nstate) { 2343 case IEEE80211_S_INIT: 2344 /* Turn link LED off. */ 2345 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2346 break; 2347 2348 case IEEE80211_S_SCAN: 2349 if (ostate != IEEE80211_S_SCAN) { 2350 /* 2351 * Begin of scanning 2352 */ 2353 2354 /* Set gain for scanning. */ 2355 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2356 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2357 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2358 2359 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2360 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2361 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2362 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2363 } 2364 2365 /* Set media status to 'No Link'. */ 2366 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2367 2368 /* Allow Rx from any BSSID. */ 2369 urtwn_write_4(sc, R92C_RCR, 2370 urtwn_read_4(sc, R92C_RCR) & 2371 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2372 2373 /* Stop Rx of data frames. */ 2374 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2375 2376 /* Disable update TSF */ 2377 urtwn_write_1(sc, R92C_BCN_CTRL, 2378 urtwn_read_1(sc, R92C_BCN_CTRL) | 2379 R92C_BCN_CTRL_DIS_TSF_UDT0); 2380 } 2381 2382 /* Make link LED blink during scan. */ 2383 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2384 2385 /* Pause AC Tx queues. */ 2386 urtwn_write_1(sc, R92C_TXPAUSE, 2387 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2388 2389 urtwn_set_chan(sc, ic->ic_curchan, 2390 IEEE80211_HTINFO_2NDCHAN_NONE); 2391 2392 /* Start periodic scan. */ 2393 if (!sc->sc_dying) 2394 callout_schedule(&sc->sc_scan_to, hz / 5); 2395 break; 2396 2397 case IEEE80211_S_AUTH: 2398 /* Set initial gain under link. */ 2399 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2400 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2401 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2402 2403 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2404 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2405 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2406 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2407 } 2408 2409 /* Set media status to 'No Link'. */ 2410 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2411 2412 /* Allow Rx from any BSSID. */ 2413 urtwn_write_4(sc, R92C_RCR, 2414 urtwn_read_4(sc, R92C_RCR) & 2415 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2416 2417 urtwn_set_chan(sc, ic->ic_curchan, 2418 IEEE80211_HTINFO_2NDCHAN_NONE); 2419 break; 2420 2421 case IEEE80211_S_ASSOC: 2422 break; 2423 2424 case IEEE80211_S_RUN: 2425 ni = vap->iv_bss; 2426 2427 /* XXX: Set 20MHz mode */ 2428 urtwn_set_chan(sc, ic->ic_curchan, 2429 IEEE80211_HTINFO_2NDCHAN_NONE); 2430 2431 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2432 /* Back to 20MHz mode */ 2433 urtwn_set_chan(sc, ic->ic_curchan, 2434 IEEE80211_HTINFO_2NDCHAN_NONE); 2435 2436 /* Set media status to 'No Link'. */ 2437 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2438 2439 /* Enable Rx of data frames. */ 2440 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2441 2442 /* Allow Rx from any BSSID. */ 2443 urtwn_write_4(sc, R92C_RCR, 2444 urtwn_read_4(sc, R92C_RCR) & 2445 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2446 2447 /* Accept Rx data/control/management frames */ 2448 urtwn_write_4(sc, R92C_RCR, 2449 urtwn_read_4(sc, R92C_RCR) | 2450 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2451 2452 /* Turn link LED on. */ 2453 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2454 break; 2455 } 2456 2457 /* Set media status to 'Associated'. */ 2458 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2459 2460 /* Set BSSID. */ 2461 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2462 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2463 2464 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2465 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2466 } else { 2467 /* 802.11b/g */ 2468 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2469 } 2470 2471 /* Enable Rx of data frames. */ 2472 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2473 2474 /* Set beacon interval. */ 2475 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2476 2477 msr = urtwn_read_1(sc, R92C_MSR); 2478 msr &= R92C_MSR_MASK; 2479 switch (ic->ic_opmode) { 2480 case IEEE80211_M_STA: 2481 /* Allow Rx from our BSSID only. */ 2482 urtwn_write_4(sc, R92C_RCR, 2483 urtwn_read_4(sc, R92C_RCR) | 2484 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2485 2486 /* Enable TSF synchronization. */ 2487 urtwn_tsf_sync_enable(sc); 2488 2489 msr |= R92C_MSR_INFRA; 2490 break; 2491 case IEEE80211_M_HOSTAP: 2492 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2493 2494 /* Allow Rx from any BSSID. */ 2495 urtwn_write_4(sc, R92C_RCR, 2496 urtwn_read_4(sc, R92C_RCR) & 2497 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2498 2499 /* Reset TSF timer to zero. */ 2500 reg = urtwn_read_4(sc, R92C_TCR); 2501 reg &= ~0x01; 2502 urtwn_write_4(sc, R92C_TCR, reg); 2503 reg |= 0x01; 2504 urtwn_write_4(sc, R92C_TCR, reg); 2505 2506 msr |= R92C_MSR_AP; 2507 break; 2508 default: 2509 msr |= R92C_MSR_ADHOC; 2510 break; 2511 } 2512 urtwn_write_1(sc, R92C_MSR, msr); 2513 2514 sifs_time = 10; 2515 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2516 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2517 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2518 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2519 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2520 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2521 2522 /* Initialize rate adaptation. */ 2523 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2524 ISSET(sc->chip, URTWN_CHIP_92EU)) 2525 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2526 else 2527 urtwn_ra_init(vap); 2528 2529 /* Turn link LED on. */ 2530 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2531 2532 /* Reset average RSSI. */ 2533 sc->avg_pwdb = -1; 2534 2535 /* Reset temperature calibration state machine. */ 2536 sc->thcal_state = 0; 2537 sc->thcal_lctemp = 0; 2538 2539 /* Start periodic calibration. */ 2540 if (!sc->sc_dying) 2541 callout_schedule(&sc->sc_calib_to, hz); 2542 break; 2543 case IEEE80211_S_CAC: 2544 case IEEE80211_S_CSA: 2545 case IEEE80211_S_SLEEP: 2546 /* NNN what do we do in these states? XXX */ 2547 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2548 break; 2549 } 2550 mutex_exit(&sc->sc_write_mtx); 2551 2552 /* newstate functions expect the ic to be locked. */ 2553 error = (*sc->sc_newstate)(vap, nstate, arg); 2554 2555 splx(s); 2556 return error; 2557 } 2558 2559 static int 2560 urtwn_wme_update(struct ieee80211com *ic) 2561 { 2562 struct urtwn_softc *sc = ic->ic_softc; 2563 2564 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2565 2566 /* don't override default WME values if WME is not actually enabled */ 2567 if (!(ic->ic_flags & IEEE80211_F_WME)) 2568 return 0; 2569 2570 /* Do it in a process context. */ 2571 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2572 return 0; 2573 } 2574 2575 static void 2576 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2577 { 2578 static const uint16_t ac2reg[WME_NUM_AC] = { 2579 R92C_EDCA_BE_PARAM, 2580 R92C_EDCA_BK_PARAM, 2581 R92C_EDCA_VI_PARAM, 2582 R92C_EDCA_VO_PARAM 2583 }; 2584 struct ieee80211com *ic = &sc->sc_ic; 2585 const struct wmeParams *wmep; 2586 int ac, aifs, slottime; 2587 int s; 2588 2589 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2590 __func__)); 2591 2592 s = splnet(); 2593 mutex_enter(&sc->sc_write_mtx); 2594 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2595 for (ac = 0; ac < WME_NUM_AC; ac++) { 2596 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2597 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2598 aifs = wmep->wmep_aifsn * slottime + 10; 2599 urtwn_write_4(sc, ac2reg[ac], 2600 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2601 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2602 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2603 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2604 } 2605 mutex_exit(&sc->sc_write_mtx); 2606 splx(s); 2607 } 2608 2609 static void 2610 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2611 { 2612 int pwdb; 2613 2614 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2615 device_xname(sc->sc_dev), __func__, rate, rssi)); 2616 2617 /* Convert antenna signal to percentage. */ 2618 if (rssi <= -100 || rssi >= 20) 2619 pwdb = 0; 2620 else if (rssi >= 0) 2621 pwdb = 100; 2622 else 2623 pwdb = 100 + rssi; 2624 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2625 if (rate <= 3) { 2626 /* CCK gain is smaller than OFDM/MCS gain. */ 2627 pwdb += 6; 2628 if (pwdb > 100) 2629 pwdb = 100; 2630 if (pwdb <= 14) 2631 pwdb -= 4; 2632 else if (pwdb <= 26) 2633 pwdb -= 8; 2634 else if (pwdb <= 34) 2635 pwdb -= 6; 2636 else if (pwdb <= 42) 2637 pwdb -= 2; 2638 } 2639 } 2640 if (sc->avg_pwdb == -1) /* Init. */ 2641 sc->avg_pwdb = pwdb; 2642 else if (sc->avg_pwdb < pwdb) 2643 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2644 else 2645 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2646 2647 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2648 device_xname(sc->sc_dev), __func__, 2649 rate, rssi, pwdb, sc->avg_pwdb)); 2650 } 2651 2652 static int8_t 2653 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2654 { 2655 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2656 struct r92c_rx_phystat *phy; 2657 struct r92c_rx_cck *cck; 2658 uint8_t rpt; 2659 int8_t rssi; 2660 2661 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2662 __func__, rate)); 2663 2664 if (rate <= 3) { 2665 cck = (struct r92c_rx_cck *)physt; 2666 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2667 rpt = (cck->agc_rpt >> 5) & 0x3; 2668 rssi = (cck->agc_rpt & 0x1f) << 1; 2669 } else { 2670 rpt = (cck->agc_rpt >> 6) & 0x3; 2671 rssi = cck->agc_rpt & 0x3e; 2672 } 2673 rssi = cckoff[rpt] - rssi; 2674 } else { /* OFDM/HT. */ 2675 phy = (struct r92c_rx_phystat *)physt; 2676 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2677 } 2678 return rssi; 2679 } 2680 2681 static int8_t 2682 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2683 { 2684 struct r92c_rx_phystat *phy; 2685 struct r88e_rx_cck *cck; 2686 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2687 int8_t rssi; 2688 2689 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2690 __func__, rate)); 2691 2692 rssi = 0; 2693 if (rate <= 3) { 2694 cck = (struct r88e_rx_cck *)physt; 2695 cck_agc_rpt = cck->agc_rpt; 2696 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2697 vga_idx = cck_agc_rpt & 0x1f; 2698 switch (lna_idx) { 2699 case 7: 2700 if (vga_idx <= 27) 2701 rssi = -100 + 2* (27 - vga_idx); 2702 else 2703 rssi = -100; 2704 break; 2705 case 6: 2706 rssi = -48 + 2 * (2 - vga_idx); 2707 break; 2708 case 5: 2709 rssi = -42 + 2 * (7 - vga_idx); 2710 break; 2711 case 4: 2712 rssi = -36 + 2 * (7 - vga_idx); 2713 break; 2714 case 3: 2715 rssi = -24 + 2 * (7 - vga_idx); 2716 break; 2717 case 2: 2718 rssi = -12 + 2 * (5 - vga_idx); 2719 break; 2720 case 1: 2721 rssi = 8 - (2 * vga_idx); 2722 break; 2723 case 0: 2724 rssi = 14 - (2 * vga_idx); 2725 break; 2726 } 2727 rssi += 6; 2728 } else { /* OFDM/HT. */ 2729 phy = (struct r92c_rx_phystat *)physt; 2730 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2731 } 2732 return rssi; 2733 } 2734 2735 static void 2736 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2737 { 2738 struct ieee80211com *ic = &sc->sc_ic; 2739 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2740 struct ifnet *ifp = vap->iv_ifp; 2741 struct ieee80211_frame *wh; 2742 struct ieee80211_node *ni; 2743 struct r92c_rx_desc_usb *stat; 2744 uint32_t rxdw0, rxdw3; 2745 struct mbuf *m; 2746 uint8_t rate; 2747 int8_t rssi = 0; 2748 int s, infosz; 2749 2750 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2751 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2752 2753 stat = (struct r92c_rx_desc_usb *)buf; 2754 rxdw0 = le32toh(stat->rxdw0); 2755 rxdw3 = le32toh(stat->rxdw3); 2756 2757 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2758 /* 2759 * This should not happen since we setup our Rx filter 2760 * to not receive these frames. 2761 */ 2762 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2763 device_xname(sc->sc_dev), __func__)); 2764 ifp->if_ierrors++; 2765 return; 2766 } 2767 2768 /* 2769 * XXX: This will drop most control packets. Do we really 2770 * want this in IEEE80211_M_MONITOR mode? 2771 */ 2772 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2773 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2774 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2775 device_xname(sc->sc_dev), __func__, pktlen)); 2776 vap->iv_stats.is_rx_tooshort++; 2777 ifp->if_ierrors++; 2778 return; 2779 } 2780 if (__predict_false(pktlen > MCLBYTES)) { 2781 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2782 device_xname(sc->sc_dev), __func__, pktlen)); 2783 ifp->if_ierrors++; 2784 return; 2785 } 2786 2787 rate = MS(rxdw3, R92C_RXDW3_RATE); 2788 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2789 2790 /* Get RSSI from PHY status descriptor if present. */ 2791 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2792 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2793 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2794 else 2795 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2796 /* Update our average RSSI. */ 2797 urtwn_update_avgrssi(sc, rate, rssi); 2798 } 2799 2800 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2801 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2802 2803 MGETHDR(m, M_DONTWAIT, MT_DATA); 2804 if (__predict_false(m == NULL)) { 2805 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2806 vap->iv_stats.is_rx_nobuf++; 2807 ifp->if_ierrors++; 2808 return; 2809 } 2810 if (pktlen > (int)MHLEN) { 2811 MCLGET(m, M_DONTWAIT); 2812 if (__predict_false(!(m->m_flags & M_EXT))) { 2813 aprint_error_dev(sc->sc_dev, 2814 "couldn't allocate rx mbuf cluster\n"); 2815 m_freem(m); 2816 vap->iv_stats.is_rx_nobuf++; 2817 ifp->if_ierrors++; 2818 return; 2819 } 2820 } 2821 2822 /* Finalize mbuf. */ 2823 m_set_rcvif(m, ifp); 2824 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2825 2826 memcpy(mtod(m, uint8_t *), wh, pktlen); 2827 m->m_pkthdr.len = m->m_len = pktlen; 2828 2829 s = splnet(); 2830 if (__predict_false(sc->sc_drvbpf != NULL)) { 2831 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2832 2833 tap->wr_flags = 0; 2834 if (!(rxdw3 & R92C_RXDW3_HT)) { 2835 switch (rate) { 2836 /* CCK. */ 2837 case 0: tap->wr_rate = 2; break; 2838 case 1: tap->wr_rate = 4; break; 2839 case 2: tap->wr_rate = 11; break; 2840 case 3: tap->wr_rate = 22; break; 2841 /* OFDM. */ 2842 case 4: tap->wr_rate = 12; break; 2843 case 5: tap->wr_rate = 18; break; 2844 case 6: tap->wr_rate = 24; break; 2845 case 7: tap->wr_rate = 36; break; 2846 case 8: tap->wr_rate = 48; break; 2847 case 9: tap->wr_rate = 72; break; 2848 case 10: tap->wr_rate = 96; break; 2849 case 11: tap->wr_rate = 108; break; 2850 } 2851 } else if (rate >= 12) { /* MCS0~15. */ 2852 /* Bit 7 set means HT MCS instead of rate. */ 2853 tap->wr_rate = 0x80 | (rate - 12); 2854 } 2855 tap->wr_dbm_antsignal = rssi; 2856 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2857 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2858 2859 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2860 } 2861 2862 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2863 2864 if (ni != NULL) { 2865 if (ni->ni_vap != NULL) { 2866 2867 } else { 2868 splx(s); 2869 return; 2870 } 2871 /* push the frame up to the 802.11 stack */ 2872 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2873 ieee80211_input(ni, m, rssi+90, 0); 2874 2875 /* Node is no longer needed. */ 2876 ieee80211_free_node(ni); 2877 2878 } else { 2879 2880 /* No node found ... process differently. */ 2881 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2882 } 2883 2884 splx(s); 2885 } 2886 2887 static void 2888 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2889 { 2890 struct urtwn_rx_data *data = priv; 2891 struct urtwn_softc *sc = data->sc; 2892 struct r92c_rx_desc_usb *stat; 2893 size_t pidx = data->pidx; 2894 uint32_t rxdw0; 2895 uint8_t *buf; 2896 int len, totlen, pktlen, infosz, npkts; 2897 2898 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2899 device_xname(sc->sc_dev), __func__, status)); 2900 2901 mutex_enter(&sc->sc_rx_mtx); 2902 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2903 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2904 /* Put this Rx buffer back to our free list. */ 2905 mutex_exit(&sc->sc_rx_mtx); 2906 2907 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2908 if (status == USBD_STALLED) 2909 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2910 else if (status != USBD_CANCELLED) 2911 goto resubmit; 2912 return; 2913 } 2914 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2915 2916 if (__predict_false(len < (int)sizeof(*stat))) { 2917 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2918 device_xname(sc->sc_dev), __func__, len)); 2919 goto resubmit; 2920 } 2921 buf = data->buf; 2922 2923 /* Get the number of encapsulated frames. */ 2924 stat = (struct r92c_rx_desc_usb *)buf; 2925 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2926 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2927 device_xname(sc->sc_dev), __func__, npkts)); 2928 2929 /* Process all of them. */ 2930 while (npkts-- > 0) { 2931 if (__predict_false(len < (int)sizeof(*stat))) { 2932 DPRINTFN(DBG_RX, 2933 ("%s: %s: len(%d) is short than header\n", 2934 device_xname(sc->sc_dev), __func__, len)); 2935 break; 2936 } 2937 stat = (struct r92c_rx_desc_usb *)buf; 2938 rxdw0 = le32toh(stat->rxdw0); 2939 2940 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2941 if (__predict_false(pktlen == 0)) { 2942 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2943 device_xname(sc->sc_dev), __func__)); 2944 break; 2945 } 2946 2947 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2948 2949 /* Make sure everything fits in xfer. */ 2950 totlen = sizeof(*stat) + infosz + pktlen; 2951 if (__predict_false(totlen > len)) { 2952 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2953 device_xname(sc->sc_dev), __func__, totlen, 2954 (int)sizeof(*stat), infosz, pktlen, len)); 2955 break; 2956 } 2957 2958 /* Process 802.11 frame. */ 2959 urtwn_rx_frame(sc, buf, pktlen); 2960 2961 /* Next chunk is 128-byte aligned. */ 2962 totlen = roundup2(totlen, 128); 2963 buf += totlen; 2964 len -= totlen; 2965 } 2966 2967 resubmit: 2968 /* Setup a new transfer. */ 2969 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2970 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2971 (void)usbd_transfer(xfer); 2972 } 2973 2974 static void 2975 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2976 { 2977 struct urtwn_tx_data *data = priv; 2978 struct urtwn_softc *sc = data->sc; 2979 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 2980 size_t pidx = data->pidx; 2981 int s; 2982 2983 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2984 device_xname(sc->sc_dev), __func__, status)); 2985 2986 mutex_enter(&sc->sc_tx_mtx); 2987 /* Put this Tx buffer back to our free list. */ 2988 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2989 mutex_exit(&sc->sc_tx_mtx); 2990 2991 s = splnet(); 2992 sc->tx_timer = 0; 2993 ifp->if_flags &= ~IFF_OACTIVE; 2994 2995 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2996 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2997 if (status == USBD_STALLED) { 2998 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2999 usbd_clear_endpoint_stall_async(pipe); 3000 } 3001 printf("ERROR1\n"); 3002 ifp->if_oerrors++; 3003 } 3004 splx(s); 3005 return; 3006 } 3007 3008 ifp->if_opackets++; 3009 urtwn_start(ifp); 3010 splx(s); 3011 3012 } 3013 3014 static int 3015 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3016 struct urtwn_tx_data *data) 3017 { 3018 struct ieee80211com *ic = &sc->sc_ic; 3019 struct ieee80211_frame *wh; 3020 struct ieee80211_key *k = NULL; 3021 struct r92c_tx_desc_usb *txd; 3022 size_t i, padsize, xferlen, txd_len; 3023 uint16_t seq, sum; 3024 uint8_t raid, type, tid; 3025 int s, hasqos, error; 3026 3027 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3028 3029 wh = mtod(m, struct ieee80211_frame *); 3030 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3031 txd_len = sizeof(*txd); 3032 3033 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3034 txd_len = 32; 3035 3036 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3037 k = ieee80211_crypto_encap(ni, m); 3038 if (k == NULL) 3039 return ENOBUFS; 3040 3041 /* packet header may have moved, reset our local pointer */ 3042 wh = mtod(m, struct ieee80211_frame *); 3043 } 3044 3045 if (__predict_false(sc->sc_drvbpf != NULL)) { 3046 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3047 3048 tap->wt_flags = 0; 3049 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3050 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3051 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3052 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3053 3054 /* XXX: set tap->wt_rate? */ 3055 3056 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3057 } 3058 3059 /* non-qos data frames */ 3060 tid = R92C_TXDW1_QSEL_BE; 3061 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3062 /* data frames in 11n mode */ 3063 struct ieee80211_qosframe *qwh = (void *)wh; 3064 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3065 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3066 tid = R92C_TXDW1_QSEL_MGNT; 3067 } 3068 3069 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3070 padsize = 8; 3071 else 3072 padsize = 0; 3073 3074 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3075 padsize = 0; 3076 3077 /* Fill Tx descriptor. */ 3078 txd = (struct r92c_tx_desc_usb *)data->buf; 3079 memset(txd, 0, txd_len + padsize); 3080 3081 txd->txdw0 |= htole32( 3082 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3083 SM(R92C_TXDW0_OFFSET, txd_len)); 3084 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3085 txd->txdw0 |= htole32( 3086 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3087 } 3088 3089 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3090 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3091 3092 /* fix pad field */ 3093 if (padsize > 0) { 3094 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3095 device_xname(sc->sc_dev), __func__, padsize)); 3096 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3097 } 3098 3099 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3100 type == IEEE80211_FC0_TYPE_DATA) { 3101 if (ic->ic_curmode == IEEE80211_MODE_11B) 3102 raid = R92C_RAID_11B; 3103 else 3104 raid = R92C_RAID_11BG; 3105 DPRINTFN(DBG_TX, 3106 ("%s: %s: data packet: tid=%d, raid=%d\n", 3107 device_xname(sc->sc_dev), __func__, tid, raid)); 3108 3109 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3110 txd->txdw1 |= htole32( 3111 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3112 SM(R92C_TXDW1_QSEL, tid) | 3113 SM(R92C_TXDW1_RAID, raid) | 3114 R92C_TXDW1_AGGBK); 3115 } else 3116 txd->txdw1 |= htole32( 3117 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3118 SM(R92C_TXDW1_QSEL, tid) | 3119 SM(R92C_TXDW1_RAID, raid) | 3120 R92C_TXDW1_AGGBK); 3121 3122 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3123 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3124 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3125 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3126 3127 if (hasqos) { 3128 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3129 } 3130 3131 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3132 /* for 11g */ 3133 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3134 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3135 R92C_TXDW4_HWRTSEN); 3136 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3137 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3138 R92C_TXDW4_HWRTSEN); 3139 } 3140 } 3141 /* Send RTS at OFDM24. */ 3142 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3143 txd->txdw5 |= htole32(0x0001ff00); 3144 /* Send data at OFDM54. */ 3145 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3146 txd->txdw5 |= htole32(0x13 & 0x3f); 3147 else 3148 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3149 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3150 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3151 device_xname(sc->sc_dev), __func__)); 3152 txd->txdw1 |= htole32( 3153 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3154 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3155 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3156 3157 /* Force CCK1. */ 3158 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3159 /* Use 1Mbps */ 3160 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3161 } else { 3162 /* broadcast or multicast packets */ 3163 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3164 device_xname(sc->sc_dev), __func__)); 3165 txd->txdw1 |= htole32( 3166 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3167 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3168 3169 /* Force CCK1. */ 3170 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3171 /* Use 1Mbps */ 3172 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3173 } 3174 /* Set sequence number */ 3175 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3176 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3177 txd->txdseq |= htole16(seq); 3178 3179 if (!hasqos) { 3180 /* Use HW sequence numbering for non-QoS frames. */ 3181 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3182 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3183 } 3184 } else { 3185 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3186 R92E_HWSEQ_SHIFT); 3187 if (!hasqos) { 3188 /* Use HW sequence numbering for non-QoS frames. */ 3189 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3190 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3191 } 3192 } 3193 3194 /* Compute Tx descriptor checksum. */ 3195 sum = 0; 3196 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3197 sum ^= ((uint16_t *)txd)[i]; 3198 txd->txdsum = sum; /* NB: already little endian. */ 3199 3200 xferlen = txd_len + m->m_pkthdr.len + padsize; 3201 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3202 3203 if (data->xfer == NULL) { 3204 /* NNN Don't crash ... but what is going on! */ 3205 printf ("urtwn_tx: data->xfer is NULL\n"); 3206 m_print(m,"", printf); 3207 return -1; 3208 } 3209 3210 s = splnet(); 3211 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3212 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3213 urtwn_txeof); 3214 error = usbd_transfer(data->xfer); 3215 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3216 error != USBD_IN_PROGRESS)) { 3217 splx(s); 3218 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3219 device_xname(sc->sc_dev), __func__, error)); 3220 return error; 3221 } 3222 splx(s); 3223 return 0; 3224 } 3225 3226 struct urtwn_tx_data * 3227 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3228 { 3229 struct urtwn_tx_data *data = NULL; 3230 3231 mutex_enter(&sc->sc_tx_mtx); 3232 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3233 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3234 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3235 } 3236 mutex_exit(&sc->sc_tx_mtx); 3237 3238 return data; 3239 } 3240 3241 static void 3242 urtwn_start(struct ifnet *ifp) 3243 { 3244 struct ieee80211vap *vap = ifp->if_softc; 3245 struct ieee80211com *ic = vap->iv_ic; 3246 struct urtwn_softc *sc = ic->ic_softc; 3247 struct urtwn_tx_data *data; 3248 struct ether_header *eh; 3249 struct ieee80211_node *ni; 3250 struct mbuf *m; 3251 3252 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3253 3254 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3255 return; 3256 3257 data = NULL; 3258 for (;;) { 3259 /* Send pending management frames first. */ 3260 IF_POLL(&ic->ic_mgtq, m); 3261 if (m != NULL) { 3262 /* Use AC_VO for management frames. */ 3263 3264 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3265 3266 if (data == NULL) { 3267 ifp->if_flags |= IFF_OACTIVE; 3268 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3269 device_xname(sc->sc_dev))); 3270 return; 3271 } 3272 IF_DEQUEUE(&ic->ic_mgtq, m); 3273 ni = M_GETCTX(m, struct ieee80211_node *); 3274 M_CLEARCTX(m); 3275 goto sendit; 3276 } 3277 3278 if (vap->iv_state != IEEE80211_S_RUN) 3279 break; 3280 3281 /* Encapsulate and send data frames. */ 3282 IFQ_POLL(&sc->sc_sendq, m); 3283 if (m == NULL) 3284 break; 3285 3286 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3287 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3288 uint8_t qid = WME_AC_BE; 3289 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3290 /* data frames in 11n mode */ 3291 struct ieee80211_qosframe *qwh = (void *)wh; 3292 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3293 qid = TID_TO_WME_AC(tid); 3294 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3295 qid = WME_AC_VO; 3296 } 3297 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3298 3299 if (data == NULL) { 3300 ifp->if_flags |= IFF_OACTIVE; 3301 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3302 device_xname(sc->sc_dev))); 3303 return; 3304 } 3305 IFQ_DEQUEUE(&sc->sc_sendq, m); 3306 3307 if (m->m_len < (int)sizeof(*eh) && 3308 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3309 printf("ERROR6\n"); 3310 ifp->if_oerrors++; 3311 continue; 3312 } 3313 eh = mtod(m, struct ether_header *); 3314 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3315 if (ni == NULL) { 3316 m_freem(m); 3317 printf("ERROR5\n"); 3318 ifp->if_oerrors++; 3319 continue; 3320 } 3321 3322 //bpf_mtap(ifp, m, BPF_D_OUT); 3323 3324 sendit: 3325 if (urtwn_tx(sc, m, ni, data) != 0) { 3326 m_freem(m); 3327 ieee80211_free_node(ni); 3328 printf("ERROR3\n"); 3329 ifp->if_oerrors++; 3330 continue; 3331 } 3332 m_freem(m); 3333 ieee80211_free_node(ni); 3334 sc->tx_timer = 5; 3335 ifp->if_timer = 1; 3336 } 3337 } 3338 3339 static __unused void 3340 urtwn_watchdog(struct ifnet *ifp) 3341 { 3342 struct ieee80211vap *vap = ifp->if_softc; 3343 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3344 3345 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3346 3347 ifp->if_timer = 0; 3348 3349 if (sc->tx_timer > 0) { 3350 if (--sc->tx_timer == 0) { 3351 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3352 /* urtwn_init(ifp); XXX needs a process context! */ 3353 printf("ERROR2\n"); 3354 ifp->if_oerrors++; 3355 return; 3356 } 3357 ifp->if_timer = 1; 3358 } 3359 // ieee80211_watchdog(&sc->sc_ic); 3360 } 3361 3362 /* 3363 * Create a VAP node for use with the urtwn driver. 3364 */ 3365 3366 static struct ieee80211vap * 3367 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3368 int unit, enum ieee80211_opmode opmode, int flags, 3369 const uint8_t bssid[IEEE80211_ADDR_LEN], 3370 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3371 { 3372 struct urtwn_softc *sc = ic->ic_softc; 3373 struct ifnet *ifp; 3374 struct ieee80211vap *vap; 3375 3376 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3377 3378 /* Allow only one VAP for the urtwn driver. */ 3379 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3380 return NULL; 3381 3382 /* Allocate the vap and setup. */ 3383 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3384 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3385 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3386 kmem_free(vap, sizeof(struct ieee80211vap)); 3387 return NULL; 3388 } 3389 3390 /* Local setup */ 3391 vap->iv_reset = urtwn_reset; 3392 3393 ifp = vap->iv_ifp; 3394 if_initialize(ifp); 3395 ifp->if_init = urtwn_init; 3396 ifp->if_ioctl = urtwn_ioctl; 3397 ifp->if_start = urtwn_start; 3398 // ifp->if_watchdog = urtwn_watchdog; NNN 3399 ifp->if_extflags |= IFEF_MPSAFE; 3400 // IFQ_SET_READY(&ifp->if_snd); 3401 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3402 3403 ifp->if_percpuq = if_percpuq_create(ifp); 3404 3405 /* Override state transition machine. */ 3406 /* NNN --- many possible newstate machines ... issue! */ 3407 sc->sc_newstate = vap->iv_newstate; 3408 vap->iv_newstate = urtwn_newstate; 3409 3410 /* Finish setup */ 3411 ieee80211_vap_attach(vap, urtwn_media_change, 3412 ieee80211_media_status, macaddr); 3413 ic->ic_opmode = opmode; 3414 3415 /* Attach the packet filter */ 3416 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3417 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3418 &sc->sc_drvbpf); 3419 3420 return vap; 3421 } 3422 3423 static void 3424 urtwn_vap_delete(struct ieee80211vap *vap) 3425 { 3426 struct ifnet *ifp = vap->iv_ifp; 3427 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3428 3429 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3430 3431 urtwn_stop(ifp, 0); 3432 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3433 bpf_detach(ifp); 3434 if_detach(ifp); 3435 kmem_free(vap, sizeof(struct ieee80211vap)); 3436 } 3437 3438 static void 3439 urtwn_parent(struct ieee80211com *ic) 3440 { 3441 struct urtwn_softc *sc __unused = ic->ic_softc; 3442 3443 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3444 3445 /* Not sure what to do here yet. */ 3446 } 3447 3448 static void 3449 urtwn_scan_start(struct ieee80211com *ic) 3450 { 3451 struct urtwn_softc *sc = ic->ic_softc; 3452 //uint32_t reg; 3453 //int s; 3454 3455 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3456 3457 /* 3458 * Not sure what to do here yet. Try #1: do what was in the 3459 * state machine. NNN 3460 */ 3461 #if NOTWITHSTATEMACHINEOVERRIDE 3462 /* 3463 * Begin of scanning 3464 */ 3465 3466 s = splnet(); 3467 mutex_enter(&sc->sc_write_mtx); 3468 3469 /* Set gain for scanning. */ 3470 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3471 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3472 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3473 3474 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3475 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3476 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3477 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3478 } 3479 3480 /* Set media status to 'No Link'. */ 3481 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3482 3483 /* Allow Rx from any BSSID. */ 3484 urtwn_write_4(sc, R92C_RCR, 3485 urtwn_read_4(sc, R92C_RCR) & 3486 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3487 3488 /* Stop Rx of data frames. */ 3489 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3490 3491 /* Disable update TSF */ 3492 urtwn_write_1(sc, R92C_BCN_CTRL, 3493 urtwn_read_1(sc, R92C_BCN_CTRL) | 3494 R92C_BCN_CTRL_DIS_TSF_UDT0); 3495 3496 /* Make link LED blink during scan. */ 3497 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3498 3499 /* Pause AC Tx queues. */ 3500 urtwn_write_1(sc, R92C_TXPAUSE, 3501 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3502 3503 urtwn_set_chan(sc, ic->ic_curchan, 3504 IEEE80211_HTINFO_2NDCHAN_NONE); 3505 3506 mutex_exit(&sc->sc_write_mtx); 3507 splx(s); 3508 #endif 3509 } 3510 3511 static void 3512 urtwn_scan_end(struct ieee80211com *ic) 3513 { 3514 struct urtwn_softc *sc = ic->ic_softc; 3515 3516 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3517 3518 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3519 /* 3520 * End of scanning 3521 */ 3522 3523 mutex_enter(&sc->sc_write_mtx); 3524 3525 /* flush 4-AC Queue after site_survey */ 3526 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3527 3528 /* Allow Rx from our BSSID only. */ 3529 urtwn_write_4(sc, R92C_RCR, 3530 urtwn_read_4(sc, R92C_RCR) | 3531 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3532 3533 /* Turn link LED off. */ 3534 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3535 3536 mutex_exit(&sc->sc_write_mtx); 3537 #endif 3538 } 3539 3540 static void 3541 urtwn_set_channel(struct ieee80211com *ic) 3542 { 3543 struct urtwn_softc *sc = ic->ic_softc; 3544 3545 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3546 3547 mutex_enter(&sc->sc_write_mtx); 3548 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3549 mutex_exit(&sc->sc_write_mtx); 3550 } 3551 3552 static int 3553 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3554 { 3555 struct urtwn_softc *sc = ic->ic_softc; 3556 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3557 int s; 3558 size_t pktlen = m->m_pkthdr.len; 3559 bool mcast = (m->m_flags & M_MCAST) != 0; 3560 3561 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3562 3563 s = splnet(); 3564 3565 IF_ENQUEUE(&sc->sc_sendq, m); 3566 3567 vap->iv_ifp->if_obytes += pktlen; 3568 if (mcast) 3569 vap->iv_ifp->if_omcasts++; 3570 3571 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3572 if_start_lock(vap->iv_ifp); 3573 splx(s); 3574 3575 urtwn_start(vap->iv_ifp); 3576 3577 return 0; 3578 } 3579 3580 #if 0 3581 static int 3582 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3583 #ifdef URTWN_DEBUG 3584 // struct ieee80211vap *vap = ni->ni_vap; 3585 struct ieee80211com *ic = ni->ni_ic; 3586 struct urtwn_softc *sc = ic->ic_softc; 3587 #endif 3588 3589 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3590 3591 /* Don't know what to do right now. */ 3592 return ENOTTY; 3593 } 3594 #endif 3595 3596 3597 static int 3598 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3599 const struct ieee80211_bpf_params *bpfp) 3600 { 3601 struct ieee80211vap *vap = ni->ni_vap; 3602 struct ieee80211com *ic = ni->ni_ic; 3603 struct urtwn_softc *sc = ic->ic_softc; 3604 struct urtwn_tx_data *data; 3605 int error; 3606 3607 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3608 3609 KASSERT(vap != NULL); /* NNN need these? */ 3610 KASSERT(ic != NULL); 3611 KASSERT(sc != NULL); 3612 KASSERT(m != NULL); 3613 3614 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3615 3616 if (data == NULL) { 3617 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3618 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3619 device_xname(sc->sc_dev))); 3620 return ENOBUFS; 3621 } 3622 3623 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3624 3625 error = urtwn_tx(sc, m, ni, data); 3626 if (error != 0) { 3627 printf("ERROR3\n"); 3628 vap->iv_ifp->if_oerrors++; 3629 } else { 3630 sc->tx_timer = 5; 3631 vap->iv_ifp->if_timer = 1; 3632 } 3633 m_freem(m); 3634 ieee80211_free_node(ni); 3635 return error; 3636 } 3637 3638 static void 3639 urtwn_getradiocaps(struct ieee80211com *ic, 3640 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3641 { 3642 uint8_t bands[IEEE80211_MODE_BYTES]; 3643 3644 /* 3645 * NNN Should be able to do something based on chip if 3646 * a chip has more bands .... eg. N ... but for the future. 3647 */ 3648 3649 memset(bands, 0, sizeof(bands)); 3650 setbit(bands, IEEE80211_MODE_11B); 3651 setbit(bands, IEEE80211_MODE_11G); 3652 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3653 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 3654 } 3655 3656 3657 static int 3658 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3659 { 3660 3661 struct ieee80211vap *vap = ifp->if_softc; 3662 struct ieee80211com *ic = vap->iv_ic; 3663 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3664 int s, error = 0; 3665 3666 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3667 device_xname(sc->sc_dev), __func__, cmd, data)); 3668 3669 s = splnet(); 3670 3671 switch (cmd) { 3672 case SIOCSIFFLAGS: 3673 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3674 break; 3675 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3676 case IFF_UP | IFF_RUNNING: 3677 break; 3678 case IFF_UP: 3679 urtwn_init(ifp); 3680 break; 3681 case IFF_RUNNING: 3682 urtwn_stop(ifp, 1); 3683 break; 3684 case 0: 3685 break; 3686 } 3687 break; 3688 3689 case SIOCADDMULTI: 3690 case SIOCDELMULTI: 3691 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3692 /* setup multicast filter, etc */ 3693 error = 0; 3694 } 3695 break; 3696 3697 case SIOCS80211CHANNEL: 3698 /* 3699 * This allows for fast channel switching in monitor mode 3700 * (used by kismet). In IBSS mode, we must explicitly reset 3701 * the interface to generate a new beacon frame. 3702 */ 3703 error = ieee80211_ioctl(ifp, cmd, data); 3704 if (error == ENETRESET && 3705 ic->ic_opmode == IEEE80211_M_MONITOR) { 3706 urtwn_set_chan(sc, ic->ic_curchan, 3707 IEEE80211_HTINFO_2NDCHAN_NONE); 3708 error = 0; 3709 } 3710 break; 3711 3712 default: 3713 error = ieee80211_ioctl(ifp, cmd, data); 3714 break; 3715 } 3716 if (error == ENETRESET) { 3717 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3718 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3719 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3720 urtwn_init(ifp); 3721 } 3722 error = 0; 3723 } 3724 3725 splx(s); 3726 3727 return error; 3728 } 3729 3730 static __inline int 3731 urtwn_power_on(struct urtwn_softc *sc) 3732 { 3733 3734 return sc->sc_power_on(sc); 3735 } 3736 3737 static int 3738 urtwn_r92c_power_on(struct urtwn_softc *sc) 3739 { 3740 uint32_t reg; 3741 int ntries; 3742 3743 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3744 3745 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3746 3747 /* Wait for autoload done bit. */ 3748 for (ntries = 0; ntries < 1000; ntries++) { 3749 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3750 break; 3751 DELAY(5); 3752 } 3753 if (ntries == 1000) { 3754 aprint_error_dev(sc->sc_dev, 3755 "timeout waiting for chip autoload\n"); 3756 return ETIMEDOUT; 3757 } 3758 3759 /* Unlock ISO/CLK/Power control register. */ 3760 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3761 /* Move SPS into PWM mode. */ 3762 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3763 DELAY(5); 3764 3765 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3766 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3767 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3768 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3769 DELAY(100); 3770 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3771 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3772 ~R92C_SYS_ISO_CTRL_MD2PP); 3773 } 3774 3775 /* Auto enable WLAN. */ 3776 urtwn_write_2(sc, R92C_APS_FSMCO, 3777 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3778 for (ntries = 0; ntries < 1000; ntries++) { 3779 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3780 R92C_APS_FSMCO_APFM_ONMAC)) 3781 break; 3782 DELAY(100); 3783 } 3784 if (ntries == 1000) { 3785 aprint_error_dev(sc->sc_dev, 3786 "timeout waiting for MAC auto ON\n"); 3787 return ETIMEDOUT; 3788 } 3789 3790 /* Enable radio, GPIO and LED functions. */ 3791 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3792 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3793 urtwn_write_2(sc, R92C_APS_FSMCO, 3794 R92C_APS_FSMCO_AFSM_HSUS | 3795 R92C_APS_FSMCO_PDN_EN | 3796 R92C_APS_FSMCO_PFM_ALDN); 3797 3798 /* Release RF digital isolation. */ 3799 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3800 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3801 3802 /* Initialize MAC. */ 3803 urtwn_write_1(sc, R92C_APSD_CTRL, 3804 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3805 for (ntries = 0; ntries < 200; ntries++) { 3806 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3807 R92C_APSD_CTRL_OFF_STATUS)) 3808 break; 3809 DELAY(5); 3810 } 3811 if (ntries == 200) { 3812 aprint_error_dev(sc->sc_dev, 3813 "timeout waiting for MAC initialization\n"); 3814 return ETIMEDOUT; 3815 } 3816 3817 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3818 reg = urtwn_read_2(sc, R92C_CR); 3819 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3820 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3821 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3822 R92C_CR_ENSEC; 3823 urtwn_write_2(sc, R92C_CR, reg); 3824 3825 urtwn_write_1(sc, 0xfe10, 0x19); 3826 return 0; 3827 } 3828 3829 static int 3830 urtwn_r92e_power_on(struct urtwn_softc *sc) 3831 { 3832 uint32_t reg; 3833 uint32_t val; 3834 int ntries; 3835 3836 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3837 3838 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3839 3840 /* Enable radio, GPIO and LED functions. */ 3841 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3842 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3843 urtwn_write_2(sc, R92C_APS_FSMCO, 3844 R92C_APS_FSMCO_AFSM_HSUS | 3845 R92C_APS_FSMCO_PDN_EN | 3846 R92C_APS_FSMCO_PFM_ALDN); 3847 3848 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3849 /* LDO. */ 3850 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3851 } 3852 else { 3853 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3854 R92C_SYS_SWR_CTRL2) & 0xffff); 3855 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3856 } 3857 3858 for (ntries = 0; ntries < 2; ntries++) { 3859 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3860 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3861 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3862 R92C_AFE_CTRL4)); 3863 } 3864 3865 /* Reset BB. */ 3866 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3867 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3868 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3869 3870 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3871 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3872 3873 /* Disable HWPDN. */ 3874 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3875 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3876 3877 /* Disable WL suspend. */ 3878 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3879 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3880 R92C_APS_FSMCO_AFSM_HSUS)); 3881 3882 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3883 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3884 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3885 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3886 for (ntries = 0; ntries < 10000; ntries++) { 3887 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3888 R92C_APS_FSMCO_APFM_ONMAC; 3889 if (val == 0x0) 3890 break; 3891 DELAY(10); 3892 } 3893 if (ntries == 10000) { 3894 aprint_error_dev(sc->sc_dev, 3895 "timeout waiting for chip power up\n"); 3896 return ETIMEDOUT; 3897 } 3898 3899 urtwn_write_2(sc, R92C_CR, 0x00); 3900 reg = urtwn_read_2(sc, R92C_CR); 3901 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3902 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3903 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3904 urtwn_write_2(sc, R92C_CR, reg); 3905 3906 return 0; 3907 } 3908 3909 static int 3910 urtwn_r88e_power_on(struct urtwn_softc *sc) 3911 { 3912 uint32_t reg; 3913 uint8_t val; 3914 int ntries; 3915 3916 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3917 3918 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3919 3920 /* Wait for power ready bit. */ 3921 for (ntries = 0; ntries < 5000; ntries++) { 3922 val = urtwn_read_1(sc, 0x6) & 0x2; 3923 if (val == 0x2) 3924 break; 3925 DELAY(10); 3926 } 3927 if (ntries == 5000) { 3928 aprint_error_dev(sc->sc_dev, 3929 "timeout waiting for chip power up\n"); 3930 return ETIMEDOUT; 3931 } 3932 3933 /* Reset BB. */ 3934 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3935 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3936 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3937 3938 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3939 3940 /* Disable HWPDN. */ 3941 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3942 3943 /* Disable WL suspend. */ 3944 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3945 3946 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3947 for (ntries = 0; ntries < 5000; ntries++) { 3948 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3949 break; 3950 DELAY(10); 3951 } 3952 if (ntries == 5000) 3953 return ETIMEDOUT; 3954 3955 /* Enable LDO normal mode. */ 3956 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3957 3958 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3959 urtwn_write_2(sc, R92C_CR, 0); 3960 reg = urtwn_read_2(sc, R92C_CR); 3961 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3962 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3963 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3964 urtwn_write_2(sc, R92C_CR, reg); 3965 3966 return 0; 3967 } 3968 3969 static int 3970 urtwn_llt_init(struct urtwn_softc *sc) 3971 { 3972 size_t i, page_count, pktbuf_count; 3973 uint32_t val; 3974 int error; 3975 3976 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3977 3978 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3979 3980 if (sc->chip & URTWN_CHIP_88E) 3981 page_count = R88E_TX_PAGE_COUNT; 3982 else if (sc->chip & URTWN_CHIP_92EU) 3983 page_count = R92E_TX_PAGE_COUNT; 3984 else 3985 page_count = R92C_TX_PAGE_COUNT; 3986 if (sc->chip & URTWN_CHIP_88E) 3987 pktbuf_count = R88E_TXPKTBUF_COUNT; 3988 else if (sc->chip & URTWN_CHIP_92EU) 3989 pktbuf_count = R88E_TXPKTBUF_COUNT; 3990 else 3991 pktbuf_count = R92C_TXPKTBUF_COUNT; 3992 3993 if (sc->chip & URTWN_CHIP_92EU) { 3994 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3995 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3996 DELAY(100); 3997 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3998 if (val & R92E_AUTO_LLT_EN) 3999 return EIO; 4000 return 0; 4001 } 4002 4003 /* Reserve pages [0; page_count]. */ 4004 for (i = 0; i < page_count; i++) { 4005 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4006 return error; 4007 } 4008 /* NB: 0xff indicates end-of-list. */ 4009 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4010 return error; 4011 /* 4012 * Use pages [page_count + 1; pktbuf_count - 1] 4013 * as ring buffer. 4014 */ 4015 for (++i; i < pktbuf_count - 1; i++) { 4016 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4017 return error; 4018 } 4019 /* Make the last page point to the beginning of the ring buffer. */ 4020 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4021 return error; 4022 } 4023 4024 static __unused void 4025 urtwn_fw_reset(struct urtwn_softc *sc) 4026 { 4027 uint16_t reg; 4028 int ntries; 4029 4030 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4031 4032 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4033 4034 /* Tell 8051 to reset itself. */ 4035 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4036 4037 /* Wait until 8051 resets by itself. */ 4038 for (ntries = 0; ntries < 100; ntries++) { 4039 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4040 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4041 return; 4042 DELAY(50); 4043 } 4044 /* Force 8051 reset. */ 4045 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4046 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4047 } 4048 4049 static void 4050 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4051 { 4052 uint16_t reg; 4053 4054 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4055 4056 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4057 4058 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4059 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4060 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4061 } 4062 DELAY(50); 4063 4064 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4065 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4066 DELAY(50); 4067 4068 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4069 DELAY(50); 4070 4071 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4072 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4073 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4074 } 4075 DELAY(50); 4076 4077 } 4078 4079 static int 4080 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4081 { 4082 uint32_t reg; 4083 int off, mlen, error = 0; 4084 4085 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4086 device_xname(sc->sc_dev), __func__, page, buf, len)); 4087 4088 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4089 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4090 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4091 4092 off = R92C_FW_START_ADDR; 4093 while (len > 0) { 4094 if (len > 196) 4095 mlen = 196; 4096 else if (len > 4) 4097 mlen = 4; 4098 else 4099 mlen = 1; 4100 error = urtwn_write_region(sc, off, buf, mlen); 4101 if (error != 0) 4102 break; 4103 off += mlen; 4104 buf += mlen; 4105 len -= mlen; 4106 } 4107 return error; 4108 } 4109 4110 static int 4111 urtwn_load_firmware(struct urtwn_softc *sc) 4112 { 4113 firmware_handle_t fwh; 4114 const struct r92c_fw_hdr *hdr; 4115 const char *name; 4116 u_char *fw, *ptr; 4117 size_t len; 4118 uint32_t reg; 4119 int mlen, ntries, page, error; 4120 4121 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4122 4123 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4124 4125 /* Read firmware image from the filesystem. */ 4126 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4127 name = "rtl8188eufw.bin"; 4128 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4129 name = "rtl8192eefw.bin"; 4130 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4131 URTWN_CHIP_UMC_A_CUT) 4132 name = "rtl8192cfwU.bin"; 4133 else 4134 name = "rtl8192cfw.bin"; 4135 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4136 aprint_error_dev(sc->sc_dev, 4137 "failed load firmware of file %s (error %d)\n", name, 4138 error); 4139 return error; 4140 } 4141 const size_t fwlen = len = firmware_get_size(fwh); 4142 fw = firmware_malloc(len); 4143 if (fw == NULL) { 4144 aprint_error_dev(sc->sc_dev, 4145 "failed to allocate firmware memory\n"); 4146 firmware_close(fwh); 4147 return ENOMEM; 4148 } 4149 error = firmware_read(fwh, 0, fw, len); 4150 firmware_close(fwh); 4151 if (error != 0) { 4152 aprint_error_dev(sc->sc_dev, 4153 "failed to read firmware (error %d)\n", error); 4154 firmware_free(fw, fwlen); 4155 return error; 4156 } 4157 4158 len = fwlen; 4159 ptr = fw; 4160 hdr = (const struct r92c_fw_hdr *)ptr; 4161 /* Check if there is a valid FW header and skip it. */ 4162 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4163 (le16toh(hdr->signature) >> 4) == 0x88e || 4164 (le16toh(hdr->signature) >> 4) == 0x92e || 4165 (le16toh(hdr->signature) >> 4) == 0x92c) { 4166 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4167 device_xname(sc->sc_dev), __func__, 4168 le16toh(hdr->version), le16toh(hdr->subversion), 4169 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4170 ptr += sizeof(*hdr); 4171 len -= sizeof(*hdr); 4172 } 4173 4174 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4175 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4176 ISSET(sc->chip, URTWN_CHIP_92EU)) 4177 urtwn_r88e_fw_reset(sc); 4178 else 4179 urtwn_fw_reset(sc); 4180 } 4181 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4182 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4183 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4184 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4185 R92C_SYS_FUNC_EN_CPUEN); 4186 } 4187 4188 /* download enabled */ 4189 urtwn_write_1(sc, R92C_MCUFWDL, 4190 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4191 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4192 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4193 4194 /* Reset the FWDL checksum. */ 4195 urtwn_write_1(sc, R92C_MCUFWDL, 4196 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4197 4198 DELAY(50); 4199 /* download firmware */ 4200 for (page = 0; len > 0; page++) { 4201 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4202 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4203 if (error != 0) { 4204 aprint_error_dev(sc->sc_dev, 4205 "could not load firmware page %d\n", page); 4206 goto fail; 4207 } 4208 ptr += mlen; 4209 len -= mlen; 4210 } 4211 4212 /* download disable */ 4213 urtwn_write_1(sc, R92C_MCUFWDL, 4214 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4215 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4216 4217 /* Wait for checksum report. */ 4218 for (ntries = 0; ntries < 1000; ntries++) { 4219 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4220 break; 4221 DELAY(5); 4222 } 4223 if (ntries == 1000) { 4224 aprint_error_dev(sc->sc_dev, 4225 "timeout waiting for checksum report\n"); 4226 error = ETIMEDOUT; 4227 goto fail; 4228 } 4229 4230 /* Wait for firmware readiness. */ 4231 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4232 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4233 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4234 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4235 ISSET(sc->chip, URTWN_CHIP_92EU)) 4236 urtwn_r88e_fw_reset(sc); 4237 for (ntries = 0; ntries < 6000; ntries++) { 4238 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4239 break; 4240 DELAY(5); 4241 } 4242 if (ntries == 6000) { 4243 aprint_error_dev(sc->sc_dev, 4244 "timeout waiting for firmware readiness\n"); 4245 error = ETIMEDOUT; 4246 goto fail; 4247 } 4248 fail: 4249 firmware_free(fw, fwlen); 4250 return error; 4251 } 4252 4253 static __inline int 4254 urtwn_dma_init(struct urtwn_softc *sc) 4255 { 4256 4257 return sc->sc_dma_init(sc); 4258 } 4259 4260 static int 4261 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4262 { 4263 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4264 uint32_t reg; 4265 int error; 4266 4267 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4268 4269 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4270 4271 /* Initialize LLT table. */ 4272 error = urtwn_llt_init(sc); 4273 if (error != 0) 4274 return error; 4275 4276 /* Get Tx queues to USB endpoints mapping. */ 4277 hashq = hasnq = haslq = 0; 4278 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4279 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 4280 device_xname(sc->sc_dev), __func__, reg)); 4281 if (MS(reg, R92C_USB_EP_HQ) != 0) 4282 hashq = 1; 4283 if (MS(reg, R92C_USB_EP_NQ) != 0) 4284 hasnq = 1; 4285 if (MS(reg, R92C_USB_EP_LQ) != 0) 4286 haslq = 1; 4287 nqueues = hashq + hasnq + haslq; 4288 if (nqueues == 0) 4289 return EIO; 4290 /* Get the number of pages for each queue. */ 4291 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4292 /* The remaining pages are assigned to the high priority queue. */ 4293 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4294 4295 /* Set number of pages for normal priority queue. */ 4296 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4297 urtwn_write_4(sc, R92C_RQPN, 4298 /* Set number of pages for public queue. */ 4299 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4300 /* Set number of pages for high priority queue. */ 4301 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4302 /* Set number of pages for low priority queue. */ 4303 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4304 /* Load values. */ 4305 R92C_RQPN_LD); 4306 4307 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4308 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4309 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4310 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4311 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4312 4313 /* Set queue to USB pipe mapping. */ 4314 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4315 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4316 if (nqueues == 1) { 4317 if (hashq) { 4318 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4319 } else if (hasnq) { 4320 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4321 } else { 4322 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4323 } 4324 } else if (nqueues == 2) { 4325 /* All 2-endpoints configs have a high priority queue. */ 4326 if (!hashq) { 4327 return EIO; 4328 } 4329 if (hasnq) { 4330 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4331 } else { 4332 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4333 } 4334 } else { 4335 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4336 } 4337 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4338 4339 /* Set Tx/Rx transfer page boundary. */ 4340 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4341 4342 /* Set Tx/Rx transfer page size. */ 4343 urtwn_write_1(sc, R92C_PBP, 4344 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4345 return 0; 4346 } 4347 4348 static int 4349 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4350 { 4351 usb_interface_descriptor_t *id; 4352 uint32_t reg; 4353 int nqueues; 4354 int error; 4355 4356 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4357 4358 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4359 4360 /* Initialize LLT table. */ 4361 error = urtwn_llt_init(sc); 4362 if (error != 0) 4363 return error; 4364 4365 /* Get Tx queues to USB endpoints mapping. */ 4366 id = usbd_get_interface_descriptor(sc->sc_iface); 4367 nqueues = id->bNumEndpoints - 1; 4368 if (nqueues == 0) 4369 return EIO; 4370 4371 /* Set number of pages for normal priority queue. */ 4372 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4373 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4374 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4375 4376 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4377 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4378 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4379 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4380 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4381 4382 /* Set queue to USB pipe mapping. */ 4383 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4384 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4385 if (nqueues == 1) 4386 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4387 else if (nqueues == 2) 4388 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4389 else 4390 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4391 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4392 4393 /* Set Tx/Rx transfer page boundary. */ 4394 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4395 4396 /* Set Tx/Rx transfer page size. */ 4397 urtwn_write_1(sc, R92C_PBP, 4398 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4399 4400 return 0; 4401 } 4402 4403 static void 4404 urtwn_mac_init(struct urtwn_softc *sc) 4405 { 4406 size_t i; 4407 4408 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4409 4410 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4411 4412 /* Write MAC initialization values. */ 4413 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4414 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4415 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4416 rtl8188eu_mac[i].val); 4417 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4418 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4419 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4420 rtl8192eu_mac[i].val); 4421 } else { 4422 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4423 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4424 rtl8192cu_mac[i].val); 4425 } 4426 } 4427 4428 static void 4429 urtwn_bb_init(struct urtwn_softc *sc) 4430 { 4431 const struct rtwn_bb_prog *prog; 4432 uint32_t reg; 4433 uint8_t crystalcap; 4434 size_t i; 4435 4436 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4437 4438 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4439 4440 /* Enable BB and RF. */ 4441 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4442 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4443 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4444 R92C_SYS_FUNC_EN_DIO_RF); 4445 4446 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4447 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4448 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4449 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4450 } 4451 4452 urtwn_write_1(sc, R92C_RF_CTRL, 4453 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4454 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4455 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4456 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4457 4458 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4459 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4460 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4461 urtwn_write_1(sc, 0x15, 0xe9); 4462 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4463 } 4464 4465 /* Select BB programming based on board type. */ 4466 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4467 prog = &rtl8188eu_bb_prog; 4468 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4469 prog = &rtl8192eu_bb_prog; 4470 else if (!(sc->chip & URTWN_CHIP_92C)) { 4471 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4472 prog = &rtl8188ce_bb_prog; 4473 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4474 prog = &rtl8188ru_bb_prog; 4475 } else { 4476 prog = &rtl8188cu_bb_prog; 4477 } 4478 } else { 4479 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4480 prog = &rtl8192ce_bb_prog; 4481 } else { 4482 prog = &rtl8192cu_bb_prog; 4483 } 4484 } 4485 /* Write BB initialization values. */ 4486 for (i = 0; i < prog->count; i++) { 4487 /* additional delay depend on registers */ 4488 switch (prog->regs[i]) { 4489 case 0xfe: 4490 urtwn_delay_ms(sc, 50); 4491 break; 4492 case 0xfd: 4493 urtwn_delay_ms(sc, 5); 4494 break; 4495 case 0xfc: 4496 urtwn_delay_ms(sc, 1); 4497 break; 4498 case 0xfb: 4499 DELAY(50); 4500 break; 4501 case 0xfa: 4502 DELAY(5); 4503 break; 4504 case 0xf9: 4505 DELAY(1); 4506 break; 4507 } 4508 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4509 DELAY(1); 4510 } 4511 4512 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4513 /* 8192C 1T only configuration. */ 4514 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4515 reg = (reg & ~0x00000003) | 0x2; 4516 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4517 4518 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4519 reg = (reg & ~0x00300033) | 0x00200022; 4520 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4521 4522 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4523 reg = (reg & ~0xff000000) | (0x45 << 24); 4524 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4525 4526 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4527 reg = (reg & ~0x000000ff) | 0x23; 4528 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4529 4530 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4531 reg = (reg & ~0x00000030) | (1 << 4); 4532 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4533 4534 reg = urtwn_bb_read(sc, 0xe74); 4535 reg = (reg & ~0x0c000000) | (2 << 26); 4536 urtwn_bb_write(sc, 0xe74, reg); 4537 reg = urtwn_bb_read(sc, 0xe78); 4538 reg = (reg & ~0x0c000000) | (2 << 26); 4539 urtwn_bb_write(sc, 0xe78, reg); 4540 reg = urtwn_bb_read(sc, 0xe7c); 4541 reg = (reg & ~0x0c000000) | (2 << 26); 4542 urtwn_bb_write(sc, 0xe7c, reg); 4543 reg = urtwn_bb_read(sc, 0xe80); 4544 reg = (reg & ~0x0c000000) | (2 << 26); 4545 urtwn_bb_write(sc, 0xe80, reg); 4546 reg = urtwn_bb_read(sc, 0xe88); 4547 reg = (reg & ~0x0c000000) | (2 << 26); 4548 urtwn_bb_write(sc, 0xe88, reg); 4549 } 4550 4551 /* Write AGC values. */ 4552 for (i = 0; i < prog->agccount; i++) { 4553 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4554 DELAY(1); 4555 } 4556 4557 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4558 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4559 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4560 DELAY(1); 4561 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4562 DELAY(1); 4563 } 4564 4565 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4566 crystalcap = sc->r88e_rom[0xb9]; 4567 if (crystalcap == 0x00) 4568 crystalcap = 0x20; 4569 crystalcap &= 0x3f; 4570 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4571 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4572 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4573 crystalcap | crystalcap << 6)); 4574 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4575 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4576 crystalcap = sc->r88e_rom[0xb9]; 4577 if (crystalcap == 0xff) 4578 crystalcap = 0x20; 4579 crystalcap &= 0x3f; 4580 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4581 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4582 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4583 crystalcap | crystalcap << 6)); 4584 } else { 4585 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4586 R92C_HSSI_PARAM2_CCK_HIPWR) { 4587 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4588 } 4589 } 4590 } 4591 4592 static void 4593 urtwn_rf_init(struct urtwn_softc *sc) 4594 { 4595 const struct rtwn_rf_prog *prog; 4596 uint32_t reg, mask, saved; 4597 size_t i, j, idx; 4598 4599 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4600 4601 /* Select RF programming based on board type. */ 4602 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4603 prog = rtl8188eu_rf_prog; 4604 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4605 prog = rtl8192eu_rf_prog; 4606 else if (!(sc->chip & URTWN_CHIP_92C)) { 4607 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4608 prog = rtl8188ce_rf_prog; 4609 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4610 prog = rtl8188ru_rf_prog; 4611 } else { 4612 prog = rtl8188cu_rf_prog; 4613 } 4614 } else { 4615 prog = rtl8192ce_rf_prog; 4616 } 4617 4618 for (i = 0; i < sc->nrxchains; i++) { 4619 /* Save RF_ENV control type. */ 4620 idx = i / 2; 4621 mask = 0xffffU << ((i % 2) * 16); 4622 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4623 4624 /* Set RF_ENV enable. */ 4625 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4626 reg |= 0x100000; 4627 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4628 DELAY(50); 4629 4630 /* Set RF_ENV output high. */ 4631 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4632 reg |= 0x10; 4633 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4634 DELAY(50); 4635 4636 /* Set address and data lengths of RF registers. */ 4637 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4638 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4639 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4640 DELAY(50); 4641 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4642 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4643 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4644 DELAY(50); 4645 4646 /* Write RF initialization values for this chain. */ 4647 for (j = 0; j < prog[i].count; j++) { 4648 if (prog[i].regs[j] >= 0xf9 && 4649 prog[i].regs[j] <= 0xfe) { 4650 /* 4651 * These are fake RF registers offsets that 4652 * indicate a delay is required. 4653 */ 4654 urtwn_delay_ms(sc, 50); 4655 continue; 4656 } 4657 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4658 DELAY(5); 4659 } 4660 4661 /* Restore RF_ENV control type. */ 4662 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4663 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4664 } 4665 4666 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4667 URTWN_CHIP_UMC_A_CUT) { 4668 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4669 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4670 } 4671 4672 /* Cache RF register CHNLBW. */ 4673 for (i = 0; i < 2; i++) { 4674 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4675 } 4676 } 4677 4678 static void 4679 urtwn_cam_init(struct urtwn_softc *sc) 4680 { 4681 uint32_t content, command; 4682 uint8_t idx; 4683 size_t i; 4684 4685 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4686 4687 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4688 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4689 return; 4690 4691 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4692 content = (idx & 3) 4693 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4694 | R92C_CAM_VALID; 4695 4696 command = R92C_CAMCMD_POLLING 4697 | R92C_CAMCMD_WRITE 4698 | R92C_CAM_CTL0(idx); 4699 4700 urtwn_write_4(sc, R92C_CAMWRITE, content); 4701 urtwn_write_4(sc, R92C_CAMCMD, command); 4702 } 4703 4704 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4705 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4706 if (i == 0) { 4707 content = (idx & 3) 4708 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4709 | R92C_CAM_VALID; 4710 } else { 4711 content = 0; 4712 } 4713 4714 command = R92C_CAMCMD_POLLING 4715 | R92C_CAMCMD_WRITE 4716 | R92C_CAM_CTL0(idx) 4717 | i; 4718 4719 urtwn_write_4(sc, R92C_CAMWRITE, content); 4720 urtwn_write_4(sc, R92C_CAMCMD, command); 4721 } 4722 } 4723 4724 /* Invalidate all CAM entries. */ 4725 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4726 } 4727 4728 static void 4729 urtwn_pa_bias_init(struct urtwn_softc *sc) 4730 { 4731 uint8_t reg; 4732 size_t i; 4733 4734 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4735 4736 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4737 4738 for (i = 0; i < sc->nrxchains; i++) { 4739 if (sc->pa_setting & (1U << i)) 4740 continue; 4741 4742 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4743 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4744 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4745 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4746 } 4747 if (!(sc->pa_setting & 0x10)) { 4748 reg = urtwn_read_1(sc, 0x16); 4749 reg = (reg & ~0xf0) | 0x90; 4750 urtwn_write_1(sc, 0x16, reg); 4751 } 4752 } 4753 4754 static void 4755 urtwn_rxfilter_init(struct urtwn_softc *sc) 4756 { 4757 4758 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4759 4760 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4761 4762 /* Initialize Rx filter. */ 4763 /* TODO: use better filter for monitor mode. */ 4764 urtwn_write_4(sc, R92C_RCR, 4765 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4766 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4767 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4768 /* Accept all multicast frames. */ 4769 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4770 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4771 /* Accept all management frames. */ 4772 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4773 /* Reject all control frames. */ 4774 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4775 /* Accept all data frames. */ 4776 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4777 } 4778 4779 static void 4780 urtwn_edca_init(struct urtwn_softc *sc) 4781 { 4782 4783 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4784 4785 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4786 4787 /* set spec SIFS (used in NAV) */ 4788 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4789 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4790 4791 /* set SIFS CCK/OFDM */ 4792 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4793 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4794 4795 /* TXOP */ 4796 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4797 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4798 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4799 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4800 } 4801 4802 static void 4803 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4804 uint16_t power[URTWN_RIDX_COUNT]) 4805 { 4806 uint32_t reg; 4807 4808 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4809 __func__, chain)); 4810 4811 /* Write per-CCK rate Tx power. */ 4812 if (chain == 0) { 4813 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4814 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4815 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4816 4817 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4818 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4819 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4820 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4821 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4822 } else { 4823 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4824 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4825 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4826 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4827 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4828 4829 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4830 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4831 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4832 } 4833 /* Write per-OFDM rate Tx power. */ 4834 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4835 SM(R92C_TXAGC_RATE06, power[ 4]) | 4836 SM(R92C_TXAGC_RATE09, power[ 5]) | 4837 SM(R92C_TXAGC_RATE12, power[ 6]) | 4838 SM(R92C_TXAGC_RATE18, power[ 7])); 4839 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4840 SM(R92C_TXAGC_RATE24, power[ 8]) | 4841 SM(R92C_TXAGC_RATE36, power[ 9]) | 4842 SM(R92C_TXAGC_RATE48, power[10]) | 4843 SM(R92C_TXAGC_RATE54, power[11])); 4844 /* Write per-MCS Tx power. */ 4845 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4846 SM(R92C_TXAGC_MCS00, power[12]) | 4847 SM(R92C_TXAGC_MCS01, power[13]) | 4848 SM(R92C_TXAGC_MCS02, power[14]) | 4849 SM(R92C_TXAGC_MCS03, power[15])); 4850 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4851 SM(R92C_TXAGC_MCS04, power[16]) | 4852 SM(R92C_TXAGC_MCS05, power[17]) | 4853 SM(R92C_TXAGC_MCS06, power[18]) | 4854 SM(R92C_TXAGC_MCS07, power[19])); 4855 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4856 SM(R92C_TXAGC_MCS08, power[20]) | 4857 SM(R92C_TXAGC_MCS09, power[21]) | 4858 SM(R92C_TXAGC_MCS10, power[22]) | 4859 SM(R92C_TXAGC_MCS11, power[23])); 4860 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4861 SM(R92C_TXAGC_MCS12, power[24]) | 4862 SM(R92C_TXAGC_MCS13, power[25]) | 4863 SM(R92C_TXAGC_MCS14, power[26]) | 4864 SM(R92C_TXAGC_MCS15, power[27])); 4865 } 4866 4867 static void 4868 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4869 uint16_t power[URTWN_RIDX_COUNT]) 4870 { 4871 struct r92c_rom *rom = &sc->rom; 4872 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4873 const struct rtwn_txpwr *base; 4874 int ridx, group; 4875 4876 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4877 device_xname(sc->sc_dev), __func__, chain, chan)); 4878 4879 /* Determine channel group. */ 4880 if (chan <= 3) { 4881 group = 0; 4882 } else if (chan <= 9) { 4883 group = 1; 4884 } else { 4885 group = 2; 4886 } 4887 4888 /* Get original Tx power based on board type and RF chain. */ 4889 if (!(sc->chip & URTWN_CHIP_92C)) { 4890 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4891 base = &rtl8188ru_txagc[chain]; 4892 } else { 4893 base = &rtl8192cu_txagc[chain]; 4894 } 4895 } else { 4896 base = &rtl8192cu_txagc[chain]; 4897 } 4898 4899 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4900 if (sc->regulatory == 0) { 4901 for (ridx = 0; ridx <= 3; ridx++) { 4902 power[ridx] = base->pwr[0][ridx]; 4903 } 4904 } 4905 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4906 if (sc->regulatory == 3) { 4907 power[ridx] = base->pwr[0][ridx]; 4908 /* Apply vendor limits. */ 4909 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4910 maxpow = rom->ht40_max_pwr[group]; 4911 } else { 4912 maxpow = rom->ht20_max_pwr[group]; 4913 } 4914 maxpow = (maxpow >> (chain * 4)) & 0xf; 4915 if (power[ridx] > maxpow) { 4916 power[ridx] = maxpow; 4917 } 4918 } else if (sc->regulatory == 1) { 4919 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4920 power[ridx] = base->pwr[group][ridx]; 4921 } 4922 } else if (sc->regulatory != 2) { 4923 power[ridx] = base->pwr[0][ridx]; 4924 } 4925 } 4926 4927 /* Compute per-CCK rate Tx power. */ 4928 cckpow = rom->cck_tx_pwr[chain][group]; 4929 for (ridx = 0; ridx <= 3; ridx++) { 4930 power[ridx] += cckpow; 4931 if (power[ridx] > R92C_MAX_TX_PWR) { 4932 power[ridx] = R92C_MAX_TX_PWR; 4933 } 4934 } 4935 4936 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4937 if (sc->ntxchains > 1) { 4938 /* Apply reduction for 2 spatial streams. */ 4939 diff = rom->ht40_2s_tx_pwr_diff[group]; 4940 diff = (diff >> (chain * 4)) & 0xf; 4941 htpow = (htpow > diff) ? htpow - diff : 0; 4942 } 4943 4944 /* Compute per-OFDM rate Tx power. */ 4945 diff = rom->ofdm_tx_pwr_diff[group]; 4946 diff = (diff >> (chain * 4)) & 0xf; 4947 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4948 for (ridx = 4; ridx <= 11; ridx++) { 4949 power[ridx] += ofdmpow; 4950 if (power[ridx] > R92C_MAX_TX_PWR) { 4951 power[ridx] = R92C_MAX_TX_PWR; 4952 } 4953 } 4954 4955 /* Compute per-MCS Tx power. */ 4956 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4957 diff = rom->ht20_tx_pwr_diff[group]; 4958 diff = (diff >> (chain * 4)) & 0xf; 4959 htpow += diff; /* HT40->HT20 correction. */ 4960 } 4961 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4962 power[ridx] += htpow; 4963 if (power[ridx] > R92C_MAX_TX_PWR) { 4964 power[ridx] = R92C_MAX_TX_PWR; 4965 } 4966 } 4967 #ifdef URTWN_DEBUG 4968 if (urtwn_debug & DBG_RF) { 4969 /* Dump per-rate Tx power values. */ 4970 printf("%s: %s: Tx power for chain %zd:\n", 4971 device_xname(sc->sc_dev), __func__, chain); 4972 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4973 printf("%s: %s: Rate %d = %u\n", 4974 device_xname(sc->sc_dev), __func__, ridx, 4975 power[ridx]); 4976 } 4977 } 4978 #endif 4979 } 4980 4981 void 4982 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4983 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4984 { 4985 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4986 const struct rtwn_r88e_txpwr *base; 4987 int ridx, group; 4988 4989 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4990 device_xname(sc->sc_dev), __func__, chain, chan)); 4991 4992 /* Determine channel group. */ 4993 if (chan <= 2) 4994 group = 0; 4995 else if (chan <= 5) 4996 group = 1; 4997 else if (chan <= 8) 4998 group = 2; 4999 else if (chan <= 11) 5000 group = 3; 5001 else if (chan <= 13) 5002 group = 4; 5003 else 5004 group = 5; 5005 5006 /* Get original Tx power based on board type and RF chain. */ 5007 base = &rtl8188eu_txagc[chain]; 5008 5009 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5010 if (sc->regulatory == 0) { 5011 for (ridx = 0; ridx <= 3; ridx++) 5012 power[ridx] = base->pwr[0][ridx]; 5013 } 5014 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5015 if (sc->regulatory == 3) 5016 power[ridx] = base->pwr[0][ridx]; 5017 else if (sc->regulatory == 1) { 5018 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5019 power[ridx] = base->pwr[group][ridx]; 5020 } else if (sc->regulatory != 2) 5021 power[ridx] = base->pwr[0][ridx]; 5022 } 5023 5024 /* Compute per-CCK rate Tx power. */ 5025 cckpow = sc->cck_tx_pwr[group]; 5026 for (ridx = 0; ridx <= 3; ridx++) { 5027 power[ridx] += cckpow; 5028 if (power[ridx] > R92C_MAX_TX_PWR) 5029 power[ridx] = R92C_MAX_TX_PWR; 5030 } 5031 5032 htpow = sc->ht40_tx_pwr[group]; 5033 5034 /* Compute per-OFDM rate Tx power. */ 5035 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5036 for (ridx = 4; ridx <= 11; ridx++) { 5037 power[ridx] += ofdmpow; 5038 if (power[ridx] > R92C_MAX_TX_PWR) 5039 power[ridx] = R92C_MAX_TX_PWR; 5040 } 5041 5042 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5043 for (ridx = 12; ridx <= 27; ridx++) { 5044 power[ridx] += bw20pow; 5045 if (power[ridx] > R92C_MAX_TX_PWR) 5046 power[ridx] = R92C_MAX_TX_PWR; 5047 } 5048 } 5049 5050 static void 5051 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5052 { 5053 uint16_t power[URTWN_RIDX_COUNT]; 5054 size_t i; 5055 5056 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5057 5058 for (i = 0; i < sc->ntxchains; i++) { 5059 /* Compute per-rate Tx power values. */ 5060 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5061 ISSET(sc->chip, URTWN_CHIP_92EU)) 5062 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5063 else 5064 urtwn_get_txpower(sc, i, chan, ht40m, power); 5065 /* Write per-rate Tx power values to hardware. */ 5066 urtwn_write_txpower(sc, i, power); 5067 } 5068 } 5069 5070 static void 5071 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5072 { 5073 struct ieee80211com *ic = &sc->sc_ic; 5074 u_int chan; 5075 size_t i; 5076 5077 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5078 5079 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5080 __func__, chan)); 5081 5082 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5083 5084 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5085 chan += 2; 5086 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5087 chan -= 2; 5088 } 5089 5090 /* Set Tx power for this new channel. */ 5091 urtwn_set_txpower(sc, chan, ht40m); 5092 5093 for (i = 0; i < sc->nrxchains; i++) { 5094 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5095 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5096 } 5097 5098 if (ht40m) { 5099 /* Is secondary channel below or above primary? */ 5100 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5101 uint32_t reg; 5102 5103 urtwn_write_1(sc, R92C_BWOPMODE, 5104 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5105 5106 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5107 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5108 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5109 5110 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5111 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5112 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5113 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5114 5115 /* Set CCK side band. */ 5116 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5117 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5118 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5119 5120 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5121 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5122 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5123 5124 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5125 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5126 ~R92C_FPGA0_ANAPARAM2_CBW20); 5127 5128 reg = urtwn_bb_read(sc, 0x818); 5129 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5130 urtwn_bb_write(sc, 0x818, reg); 5131 5132 /* Select 40MHz bandwidth. */ 5133 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5134 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5135 } else { 5136 urtwn_write_1(sc, R92C_BWOPMODE, 5137 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5138 5139 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5140 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5141 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5142 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5143 5144 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5145 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5146 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5147 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5148 R92C_FPGA0_ANAPARAM2_CBW20); 5149 } 5150 5151 /* Select 20MHz bandwidth. */ 5152 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5153 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5154 (ISSET(sc->chip, URTWN_CHIP_88E) || 5155 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5156 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5157 } 5158 } 5159 5160 static void 5161 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5162 { 5163 5164 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5165 __func__, inited)); 5166 5167 uint32_t addaBackup[16], iqkBackup[4], piMode; 5168 5169 #ifdef notyet 5170 uint32_t odfm0_agccore_regs[3]; 5171 uint32_t ant_regs[3]; 5172 uint32_t rf_regs[8]; 5173 #endif 5174 uint32_t reg0, reg1, reg2; 5175 int i, attempt; 5176 5177 #ifdef notyet 5178 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5179 R92E_STBC_SETTING + 2)); 5180 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5181 /* Save AGCCORE regs. */ 5182 for (i = 0; i < sc->nrxchains; i++) { 5183 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5184 R92C_OFDM0_AGCCORE1(i)); 5185 } 5186 #endif 5187 /* Save BB regs. */ 5188 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5189 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5190 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5191 5192 /* Save adda regs to be restored when finished. */ 5193 for (i = 0; i < __arraycount(addaReg); i++) 5194 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5195 /* Save mac regs. */ 5196 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5197 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5198 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5199 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5200 5201 #ifdef notyet 5202 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5203 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5204 5205 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5206 for (i = 0; i < sc->nrxchains; i++) 5207 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5208 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5209 #endif 5210 5211 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5212 R92C_HSSI_PARAM1_PI); 5213 if (piMode == 0) { 5214 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5215 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5216 R92C_HSSI_PARAM1_PI); 5217 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5218 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5219 R92C_HSSI_PARAM1_PI); 5220 } 5221 5222 attempt = 1; 5223 5224 next_attempt: 5225 5226 /* Set mac regs for calibration. */ 5227 for (i = 0; i < __arraycount(addaReg); i++) { 5228 urtwn_bb_write(sc, addaReg[i], 5229 addaReg[__arraycount(addaReg) - 1]); 5230 } 5231 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5232 R92C_CCK0_AFESETTING)); 5233 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5234 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5235 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5236 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5237 5238 if (sc->ntxchains > 1) 5239 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5240 5241 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5242 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5243 ~R92C_BCN_CTRL_EN_BCN)); 5244 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5245 ~R92C_BCN_CTRL_EN_BCN)); 5246 5247 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5248 ~R92C_GPIO_MUXCFG_ENBT)); 5249 5250 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5251 5252 if (sc->ntxchains > 1) 5253 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5254 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5255 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5256 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5257 5258 /* Restore BB regs. */ 5259 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5260 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5261 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5262 5263 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5264 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5265 if (sc->nrxchains > 1) 5266 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5267 5268 if (attempt-- > 0) 5269 goto next_attempt; 5270 5271 /* Restore mode. */ 5272 if (piMode == 0) { 5273 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5274 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5275 ~R92C_HSSI_PARAM1_PI); 5276 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5277 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5278 ~R92C_HSSI_PARAM1_PI); 5279 } 5280 5281 #ifdef notyet 5282 for (i = 0; i < sc->nrxchains; i++) { 5283 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5284 odfm0_agccore_regs[i]); 5285 } 5286 #endif 5287 5288 /* Restore adda regs. */ 5289 for (i = 0; i < __arraycount(addaReg); i++) 5290 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5291 /* Restore mac regs. */ 5292 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5293 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5294 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5295 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5296 5297 #ifdef notyet 5298 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5299 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5300 5301 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5302 for (i = 0; i < sc->nrxchains; i++) 5303 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5304 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5305 #endif 5306 } 5307 5308 static void 5309 urtwn_lc_calib(struct urtwn_softc *sc) 5310 { 5311 uint32_t rf_ac[2]; 5312 uint8_t txmode; 5313 size_t i; 5314 5315 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5316 5317 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5318 5319 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5320 if ((txmode & 0x70) != 0) { 5321 /* Disable all continuous Tx. */ 5322 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5323 5324 /* Set RF mode to standby mode. */ 5325 for (i = 0; i < sc->nrxchains; i++) { 5326 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5327 urtwn_rf_write(sc, i, R92C_RF_AC, 5328 RW(rf_ac[i], R92C_RF_AC_MODE, 5329 R92C_RF_AC_MODE_STANDBY)); 5330 } 5331 } else { 5332 /* Block all Tx queues. */ 5333 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5334 } 5335 /* Start calibration. */ 5336 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5337 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5338 5339 /* Give calibration the time to complete. */ 5340 urtwn_delay_ms(sc, 100); 5341 5342 /* Restore configuration. */ 5343 if ((txmode & 0x70) != 0) { 5344 /* Restore Tx mode. */ 5345 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5346 /* Restore RF mode. */ 5347 for (i = 0; i < sc->nrxchains; i++) { 5348 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5349 } 5350 } else { 5351 /* Unblock all Tx queues. */ 5352 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5353 } 5354 } 5355 5356 static void 5357 urtwn_temp_calib(struct urtwn_softc *sc) 5358 { 5359 int temp, t_meter_reg; 5360 5361 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5362 5363 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5364 5365 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5366 t_meter_reg = R92C_RF_T_METER; 5367 else 5368 t_meter_reg = R92E_RF_T_METER; 5369 5370 if (sc->thcal_state == 0) { 5371 /* Start measuring temperature. */ 5372 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5373 device_xname(sc->sc_dev), __func__)); 5374 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5375 sc->thcal_state = 1; 5376 return; 5377 } 5378 sc->thcal_state = 0; 5379 5380 /* Read measured temperature. */ 5381 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5382 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5383 __func__, temp)); 5384 if (temp == 0) /* Read failed, skip. */ 5385 return; 5386 5387 /* 5388 * Redo LC calibration if temperature changed significantly since 5389 * last calibration. 5390 */ 5391 if (sc->thcal_lctemp == 0) { 5392 /* First LC calibration is performed in urtwn_init(). */ 5393 sc->thcal_lctemp = temp; 5394 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5395 DPRINTFN(DBG_RF, 5396 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5397 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5398 temp)); 5399 urtwn_lc_calib(sc); 5400 /* Record temperature of last LC calibration. */ 5401 sc->thcal_lctemp = temp; 5402 } 5403 } 5404 5405 static int 5406 urtwn_init(struct ifnet *ifp) 5407 { 5408 struct ieee80211vap *vap = ifp->if_softc; 5409 struct ieee80211com *ic = vap->iv_ic; 5410 struct urtwn_softc *sc = ic->ic_softc; 5411 struct urtwn_rx_data *data; 5412 uint32_t reg; 5413 size_t i; 5414 int error; 5415 5416 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5417 5418 urtwn_stop(ifp, 0); 5419 5420 mutex_enter(&sc->sc_write_mtx); 5421 5422 mutex_enter(&sc->sc_task_mtx); 5423 /* Init host async commands ring. */ 5424 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5425 mutex_exit(&sc->sc_task_mtx); 5426 5427 mutex_enter(&sc->sc_fwcmd_mtx); 5428 /* Init firmware commands ring. */ 5429 sc->fwcur = 0; 5430 mutex_exit(&sc->sc_fwcmd_mtx); 5431 5432 /* Allocate Tx/Rx buffers. */ 5433 error = urtwn_alloc_rx_list(sc); 5434 if (error != 0) { 5435 aprint_error_dev(sc->sc_dev, 5436 "could not allocate Rx buffers\n"); 5437 goto fail; 5438 } 5439 error = urtwn_alloc_tx_list(sc); 5440 if (error != 0) { 5441 aprint_error_dev(sc->sc_dev, 5442 "could not allocate Tx buffers\n"); 5443 goto fail; 5444 } 5445 5446 /* Power on adapter. */ 5447 error = urtwn_power_on(sc); 5448 if (error != 0) 5449 goto fail; 5450 5451 /* Initialize DMA. */ 5452 error = urtwn_dma_init(sc); 5453 if (error != 0) 5454 goto fail; 5455 5456 /* Set info size in Rx descriptors (in 64-bit words). */ 5457 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5458 5459 /* Init interrupts. */ 5460 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5461 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5462 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5463 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5464 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5465 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5466 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5467 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5468 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5469 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5470 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5471 } 5472 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5473 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5474 } else { 5475 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5476 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5477 } 5478 5479 /* Set MAC address. */ 5480 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5481 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5482 5483 /* Set initial network type. */ 5484 reg = urtwn_read_4(sc, R92C_CR); 5485 switch (ic->ic_opmode) { 5486 case IEEE80211_M_STA: 5487 default: 5488 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5489 break; 5490 5491 case IEEE80211_M_IBSS: 5492 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5493 break; 5494 } 5495 urtwn_write_4(sc, R92C_CR, reg); 5496 5497 /* Set response rate */ 5498 reg = urtwn_read_4(sc, R92C_RRSR); 5499 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5500 urtwn_write_4(sc, R92C_RRSR, reg); 5501 5502 /* SIFS (used in NAV) */ 5503 urtwn_write_2(sc, R92C_SPEC_SIFS, 5504 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5505 5506 /* Set short/long retry limits. */ 5507 urtwn_write_2(sc, R92C_RL, 5508 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5509 5510 /* Initialize EDCA parameters. */ 5511 urtwn_edca_init(sc); 5512 5513 /* Setup rate fallback. */ 5514 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5515 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5516 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5517 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5518 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5519 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5520 } 5521 5522 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5523 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5524 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5525 /* Set ACK timeout. */ 5526 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5527 5528 /* Setup USB aggregation. */ 5529 /* Tx */ 5530 reg = urtwn_read_4(sc, R92C_TDECTRL); 5531 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5532 urtwn_write_4(sc, R92C_TDECTRL, reg); 5533 /* Rx */ 5534 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5535 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5536 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5537 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5538 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5539 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5540 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5541 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5542 ISSET(sc->chip, URTWN_CHIP_92EU)) 5543 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5544 else 5545 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5546 5547 /* Initialize beacon parameters. */ 5548 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5549 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5550 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5551 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5552 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5553 5554 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5555 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5556 /* Setup AMPDU aggregation. */ 5557 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5558 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5559 urtwn_write_2(sc, 0x4ca, 0x0708); 5560 5561 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5562 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5563 } 5564 5565 /* Load 8051 microcode. */ 5566 error = urtwn_load_firmware(sc); 5567 if (error != 0) 5568 goto fail; 5569 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5570 5571 /* Initialize MAC/BB/RF blocks. */ 5572 /* 5573 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5574 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5575 * XXX: This setting should be removed from rtl8192cu_mac[]. 5576 */ 5577 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5578 urtwn_rxfilter_init(sc); // reset R92C_RCR 5579 urtwn_bb_init(sc); 5580 urtwn_rf_init(sc); 5581 5582 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5583 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5584 urtwn_write_2(sc, R92C_CR, 5585 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5586 R92C_CR_MACRXEN); 5587 } 5588 5589 /* Turn CCK and OFDM blocks on. */ 5590 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5591 reg |= R92C_RFMOD_CCK_EN; 5592 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5593 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5594 reg |= R92C_RFMOD_OFDM_EN; 5595 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5596 5597 /* Clear per-station keys table. */ 5598 urtwn_cam_init(sc); 5599 5600 /* Enable hardware sequence numbering. */ 5601 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5602 5603 /* Perform LO and IQ calibrations. */ 5604 urtwn_iq_calib(sc, sc->iqk_inited); 5605 sc->iqk_inited = true; 5606 5607 /* Perform LC calibration. */ 5608 urtwn_lc_calib(sc); 5609 5610 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5611 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5612 /* Fix USB interference issue. */ 5613 urtwn_write_1(sc, 0xfe40, 0xe0); 5614 urtwn_write_1(sc, 0xfe41, 0x8d); 5615 urtwn_write_1(sc, 0xfe42, 0x80); 5616 urtwn_write_4(sc, 0x20c, 0xfd0320); 5617 5618 urtwn_pa_bias_init(sc); 5619 } 5620 5621 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5622 !(sc->chip & URTWN_CHIP_92EU)) { 5623 /* 1T1R */ 5624 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5625 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5626 } 5627 5628 /* Initialize GPIO setting. */ 5629 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5630 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5631 5632 /* Fix for lower temperature. */ 5633 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5634 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5635 urtwn_write_1(sc, 0x15, 0xe9); 5636 5637 /* Set default channel. */ 5638 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5639 5640 /* Queue Rx xfers. */ 5641 for (size_t j = 0; j < sc->rx_npipe; j++) { 5642 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5643 data = &sc->rx_data[j][i]; 5644 usbd_setup_xfer(data->xfer, data, data->buf, 5645 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5646 urtwn_rxeof); 5647 error = usbd_transfer(data->xfer); 5648 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5649 error != USBD_IN_PROGRESS)) 5650 goto fail; 5651 } 5652 } 5653 5654 /* We're ready to go. */ 5655 ifp->if_flags &= ~IFF_OACTIVE; 5656 ifp->if_flags |= IFF_RUNNING; 5657 sc->sc_running = true; 5658 5659 mutex_exit(&sc->sc_write_mtx); 5660 5661 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5662 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5663 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5664 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5665 urtwn_wait_async(sc); 5666 5667 /* Init the rest of the 802.11 stuff */ 5668 ieee80211_init(ifp); 5669 5670 return 0; 5671 5672 fail: 5673 mutex_exit(&sc->sc_write_mtx); 5674 5675 urtwn_stop(ifp, 1); 5676 return error; 5677 } 5678 5679 static void 5680 urtwn_stop(struct ifnet *ifp, int disable) 5681 { 5682 struct ieee80211vap *vap = ifp->if_softc; 5683 struct ieee80211com *ic = vap->iv_ic; 5684 struct urtwn_softc *sc = ic->ic_softc; 5685 size_t i; 5686 int s; 5687 5688 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5689 5690 s = splusb(); 5691 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5692 urtwn_wait_async(sc); 5693 splx(s); 5694 5695 sc->tx_timer = 0; 5696 ifp->if_timer = 0; 5697 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5698 5699 callout_stop(&sc->sc_scan_to); 5700 callout_stop(&sc->sc_calib_to); 5701 5702 /* Abort Tx. */ 5703 for (i = 0; i < sc->tx_npipe; i++) { 5704 if (sc->tx_pipe[i] != NULL) 5705 usbd_abort_pipe(sc->tx_pipe[i]); 5706 } 5707 5708 /* Stop Rx pipe. */ 5709 for (i = 0; i < sc->rx_npipe; i++) { 5710 if (sc->rx_pipe[i] != NULL) 5711 usbd_abort_pipe(sc->rx_pipe[i]); 5712 } 5713 5714 /* Free Tx/Rx buffers. */ 5715 urtwn_free_tx_list(sc); 5716 urtwn_free_rx_list(sc); 5717 5718 sc->sc_running = false; 5719 if (disable) 5720 urtwn_chip_stop(sc); 5721 } 5722 5723 static int 5724 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5725 { 5726 struct ifnet *ifp = vap->iv_ifp; 5727 struct urtwn_softc *sc = ifp->if_softc; 5728 struct ieee80211com *ic = &sc->sc_ic; 5729 5730 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5731 return ENETRESET; 5732 5733 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5734 5735 return 0; 5736 } 5737 5738 static void 5739 urtwn_chip_stop(struct urtwn_softc *sc) 5740 { 5741 uint32_t reg; 5742 bool disabled = true; 5743 5744 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5745 5746 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5747 ISSET(sc->chip, URTWN_CHIP_92EU)) 5748 return; 5749 5750 mutex_enter(&sc->sc_write_mtx); 5751 5752 /* 5753 * RF Off Sequence 5754 */ 5755 /* Pause MAC TX queue */ 5756 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5757 5758 /* Disable RF */ 5759 urtwn_rf_write(sc, 0, 0, 0); 5760 5761 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5762 5763 /* Reset BB state machine */ 5764 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5765 R92C_SYS_FUNC_EN_USBD | 5766 R92C_SYS_FUNC_EN_USBA | 5767 R92C_SYS_FUNC_EN_BB_GLB_RST); 5768 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5769 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5770 5771 /* 5772 * Reset digital sequence 5773 */ 5774 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5775 /* Reset MCU ready status */ 5776 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5777 /* If firmware in ram code, do reset */ 5778 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5779 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5780 ISSET(sc->chip, URTWN_CHIP_92EU)) 5781 urtwn_r88e_fw_reset(sc); 5782 else 5783 urtwn_fw_reset(sc); 5784 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5785 } 5786 } 5787 5788 /* Reset MAC and Enable 8051 */ 5789 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5790 5791 /* Reset MCU ready status */ 5792 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5793 5794 if (disabled) { 5795 /* Disable MAC clock */ 5796 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5797 /* Disable AFE PLL */ 5798 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5799 /* Gated AFE DIG_CLOCK */ 5800 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5801 /* Isolated digital to PON */ 5802 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5803 } 5804 5805 /* 5806 * Pull GPIO PIN to balance level and LED control 5807 */ 5808 /* 1. Disable GPIO[7:0] */ 5809 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5810 5811 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5812 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5813 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5814 5815 /* Disable GPIO[10:8] */ 5816 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5817 5818 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5819 reg |= (((reg & 0x000f) << 4) | 0x0780); 5820 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5821 5822 /* Disable LED0 & 1 */ 5823 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5824 5825 /* 5826 * Reset digital sequence 5827 */ 5828 if (disabled) { 5829 /* Disable ELDR clock */ 5830 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5831 /* Isolated ELDR to PON */ 5832 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5833 } 5834 5835 /* 5836 * Disable analog sequence 5837 */ 5838 if (disabled) { 5839 /* Disable A15 power */ 5840 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5841 /* Disable digital core power */ 5842 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5843 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5844 ~R92C_LDOV12D_CTRL_LDV12_EN); 5845 } 5846 5847 /* Enter PFM mode */ 5848 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5849 5850 /* Set USB suspend */ 5851 urtwn_write_2(sc, R92C_APS_FSMCO, 5852 R92C_APS_FSMCO_APDM_HOST | 5853 R92C_APS_FSMCO_AFSM_HSUS | 5854 R92C_APS_FSMCO_PFM_ALDN); 5855 5856 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5857 5858 mutex_exit(&sc->sc_write_mtx); 5859 } 5860 5861 static void 5862 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5863 { 5864 if (sc->sc_running == false) 5865 DELAY(ms * 1000); 5866 else 5867 usbd_delay_ms(sc->sc_udev, ms); 5868 } 5869 5870 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5871 5872 #ifdef _MODULE 5873 #include "ioconf.c" 5874 #endif 5875 5876 static int 5877 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5878 { 5879 int error = 0; 5880 5881 switch (cmd) { 5882 case MODULE_CMD_INIT: 5883 #ifdef _MODULE 5884 error = config_init_component(cfdriver_ioconf_urtwn, 5885 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5886 #endif 5887 return error; 5888 case MODULE_CMD_FINI: 5889 #ifdef _MODULE 5890 error = config_fini_component(cfdriver_ioconf_urtwn, 5891 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5892 #endif 5893 return error; 5894 default: 5895 return ENOTTY; 5896 } 5897 } 5898
Indexes created Thu Oct 02 14:10:14 GMT 2025