if_urtwn.c revision 1.59.2.9
1 /* $NetBSD: if_urtwn.c,v 1.59.2.9 2020/04/13 08:04:49 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* Some code taken from FreeBSD dev/usb/wlan/if_urtw.c with copyright */ 23 /*- 24 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 25 * 26 * Permission to use, copy, modify, and distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 /*- 40 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 41 * RTL8192EU. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.59.2.9 2020/04/13 08:04:49 martin Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_inet.h" 49 #include "opt_usb.h" 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/socket.h> 59 #include <sys/systm.h> 60 #include <sys/module.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 64 #include <sys/bus.h> 65 #include <machine/endian.h> 66 #include <sys/intr.h> 67 68 #include <net/bpf.h> 69 #include <net/if.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_ether.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 #include <netinet/if_inarp.h> 81 82 #include <net80211/ieee80211_netbsd.h> 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_radiotap.h> 85 86 #include <dev/firmload.h> 87 88 #include <dev/usb/usb.h> 89 #include <dev/usb/usbdi.h> 90 #include <dev/usb/usbdivar.h> 91 #include <dev/usb/usbdi_util.h> 92 #include <dev/usb/usbdevs.h> 93 94 #include <dev/ic/rtwnreg.h> 95 #include <dev/ic/rtwn_data.h> 96 #include <dev/usb/if_urtwnreg.h> 97 #include <dev/usb/if_urtwnvar.h> 98 99 /* 100 * The sc_write_mtx locking is to prevent sequences of writes from 101 * being intermingled with each other. I don't know if this is really 102 * needed. I have added it just to be on the safe side. 103 */ 104 105 #ifdef URTWN_DEBUG 106 #define DBG_INIT __BIT(0) 107 #define DBG_FN __BIT(1) 108 #define DBG_TX __BIT(2) 109 #define DBG_RX __BIT(3) 110 #define DBG_STM __BIT(4) 111 #define DBG_RF __BIT(5) 112 #define DBG_REG __BIT(6) 113 #define DBG_ALL 0xffffffffU 114 /* NNN Reset urtwn_debug to 0 when done debugging. */ 115 u_int urtwn_debug = 0; 116 #define DPRINTFN(n, s) \ 117 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 118 #else 119 #define DPRINTFN(n, s) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 /* urtwn data */ 227 static const uint8_t urtwn_chan_2ghz[] = 228 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 229 230 231 static int urtwn_match(device_t, cfdata_t, void *); 232 static void urtwn_attach(device_t, device_t, void *); 233 static int urtwn_detach(device_t, int); 234 static int urtwn_activate(device_t, enum devact); 235 236 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 237 urtwn_attach, urtwn_detach, urtwn_activate); 238 239 static int urtwn_open_pipes(struct urtwn_softc *); 240 static void urtwn_close_pipes(struct urtwn_softc *); 241 static int urtwn_alloc_rx_list(struct urtwn_softc *); 242 static void urtwn_free_rx_list(struct urtwn_softc *); 243 static int urtwn_alloc_tx_list(struct urtwn_softc *); 244 static void urtwn_free_tx_list(struct urtwn_softc *); 245 static void urtwn_task(void *); 246 static void urtwn_do_async(struct urtwn_softc *, 247 void (*)(struct urtwn_softc *, void *), void *, int); 248 static void urtwn_wait_async(struct urtwn_softc *); 249 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 252 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 253 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 254 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 255 int); 256 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 257 int); 258 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 259 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 260 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 261 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 262 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 263 uint32_t); 264 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 265 uint32_t); 266 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 267 uint32_t); 268 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 269 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 270 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 271 static void urtwn_efuse_read(struct urtwn_softc *); 272 static void urtwn_efuse_switch_power(struct urtwn_softc *); 273 static int urtwn_read_chipid(struct urtwn_softc *); 274 #ifdef URTWN_DEBUG 275 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 276 #endif 277 static void urtwn_read_rom(struct urtwn_softc *); 278 static void urtwn_r88e_read_rom(struct urtwn_softc *); 279 static int urtwn_media_change(struct ifnet *); 280 static int urtwn_ra_init(struct ieee80211vap *); 281 static int urtwn_get_nettype(struct urtwn_softc *); 282 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 283 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 284 static void urtwn_set_led(struct urtwn_softc *, int, int); 285 static void urtwn_calib_to(void *); 286 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 287 static void urtwn_next_scan(void *); 288 static int urtwn_newstate(struct ieee80211vap *, enum ieee80211_state, 289 int); 290 //static void urtwn_newstate_cb(struct urtwn_softc *, void *); 291 static int urtwn_wme_update(struct ieee80211com *); 292 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 293 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 294 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 295 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 296 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 297 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 298 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 299 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 300 struct ieee80211_node *, struct urtwn_tx_data *); 301 static struct urtwn_tx_data * 302 urtwn_get_tx_data(struct urtwn_softc *, size_t); 303 static void urtwn_start(struct ifnet *); 304 static void urtwn_watchdog(struct ifnet *); 305 static int urtwn_r92c_power_on(struct urtwn_softc *); 306 static int urtwn_r92e_power_on(struct urtwn_softc *); 307 static int urtwn_r88e_power_on(struct urtwn_softc *); 308 static int urtwn_llt_init(struct urtwn_softc *); 309 static void urtwn_fw_reset(struct urtwn_softc *); 310 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 311 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 312 static int urtwn_load_firmware(struct urtwn_softc *); 313 static int urtwn_r92c_dma_init(struct urtwn_softc *); 314 static int urtwn_r88e_dma_init(struct urtwn_softc *); 315 static void urtwn_mac_init(struct urtwn_softc *); 316 static void urtwn_bb_init(struct urtwn_softc *); 317 static void urtwn_rf_init(struct urtwn_softc *); 318 static void urtwn_cam_init(struct urtwn_softc *); 319 static void urtwn_pa_bias_init(struct urtwn_softc *); 320 static void urtwn_rxfilter_init(struct urtwn_softc *); 321 static void urtwn_edca_init(struct urtwn_softc *); 322 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 323 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 324 uint16_t[]); 325 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 326 u_int, uint16_t[]); 327 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 328 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 329 u_int); 330 static void urtwn_iq_calib(struct urtwn_softc *, bool); 331 static void urtwn_lc_calib(struct urtwn_softc *); 332 static void urtwn_temp_calib(struct urtwn_softc *); 333 static int urtwn_init(struct ifnet *); 334 static void urtwn_stop(struct ifnet *, int); 335 static int urtwn_reset(struct ieee80211vap *, u_long); 336 static void urtwn_chip_stop(struct urtwn_softc *); 337 static void urtwn_newassoc(struct ieee80211_node *, int); 338 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 339 /* Functions for wifi refresh */ 340 static struct ieee80211vap * 341 urtwn_vap_create(struct ieee80211com *, 342 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 343 const uint8_t [IEEE80211_ADDR_LEN], 344 const uint8_t [IEEE80211_ADDR_LEN]); 345 static void urtwn_vap_delete(struct ieee80211vap *); 346 static int urtwn_ioctl(struct ifnet *, u_long, void *); 347 static void urtwn_parent(struct ieee80211com *); 348 static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 349 struct ieee80211_channel []); 350 static void urtwn_scan_start(struct ieee80211com *); 351 static void urtwn_scan_end(struct ieee80211com *); 352 static void urtwn_set_channel(struct ieee80211com *); 353 static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 354 static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 355 const struct ieee80211_bpf_params *); 356 //static int urtwn_send_mgmt(struct ieee80211_node *, int, int); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 363 364 static const uint16_t addaReg[] = { 365 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 366 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 367 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 368 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 369 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 370 }; 371 372 static int 373 urtwn_match(device_t parent, cfdata_t match, void *aux) 374 { 375 struct usb_attach_arg *uaa = aux; 376 377 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 378 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 379 } 380 381 static void 382 urtwn_attach(device_t parent, device_t self, void *aux) 383 { 384 struct urtwn_softc *sc = device_private(self); 385 struct ieee80211com *ic = &sc->sc_ic; 386 struct usb_attach_arg *uaa = aux; 387 char *devinfop; 388 const struct urtwn_dev *dev; 389 usb_device_request_t req; 390 // NNN loop below size_t i; 391 int error; 392 393 sc->sc_dev = self; 394 sc->sc_udev = uaa->uaa_device; 395 396 /* Name the ic. */ 397 ic->ic_name = "urtwn"; 398 399 /* Driver Send queue, separate from the if send queue*/ 400 sc->sc_sendq.ifq_maxlen = 32; 401 /* NNN how should this be initialized? */ 402 sc->sc_sendq.ifq_head = sc->sc_sendq.ifq_tail = NULL; 403 sc->sc_sendq.ifq_len = 0; 404 sc->sc_sendq.ifq_drops = 0; 405 IFQ_LOCK_INIT(&sc->sc_sendq); 406 407 sc->chip = 0; 408 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 409 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 410 SET(sc->chip, URTWN_CHIP_88E); 411 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 412 SET(sc->chip, URTWN_CHIP_92EU); 413 414 aprint_naive("\n"); 415 aprint_normal("\n"); 416 417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 418 419 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 420 aprint_normal_dev(self, "%s\n", devinfop); 421 usbd_devinfo_free(devinfop); 422 423 req.bmRequestType = UT_WRITE_DEVICE; 424 req.bRequest = UR_SET_FEATURE; 425 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 426 USETW(req.wIndex, UHF_PORT_SUSPEND); 427 USETW(req.wLength, 0); 428 429 (void) usbd_do_request(sc->sc_udev, &req, 0); 430 431 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 432 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 433 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_SOFTNET); 434 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 435 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 436 437 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 438 439 /* NNN make these callouts use a vap ... in vap create??? */ 440 callout_init(&sc->sc_scan_to, 0); 441 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 442 callout_init(&sc->sc_calib_to, 0); 443 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 444 445 error = usbd_set_config_no(sc->sc_udev, 1, 0); 446 if (error != 0) { 447 aprint_error_dev(self, "failed to set configuration" 448 ", err=%s\n", usbd_errstr(error)); 449 goto fail; 450 } 451 452 /* Get the first interface handle. */ 453 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 454 if (error != 0) { 455 aprint_error_dev(self, "could not get interface handle\n"); 456 goto fail; 457 } 458 459 error = urtwn_read_chipid(sc); 460 if (error != 0) { 461 aprint_error_dev(self, "unsupported test chip\n"); 462 goto fail; 463 } 464 465 /* Determine number of Tx/Rx chains. */ 466 if (sc->chip & URTWN_CHIP_92C) { 467 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 468 sc->nrxchains = 2; 469 } else if (sc->chip & URTWN_CHIP_92EU) { 470 sc->ntxchains = 2; 471 sc->nrxchains = 2; 472 } else { 473 sc->ntxchains = 1; 474 sc->nrxchains = 1; 475 } 476 477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 478 ISSET(sc->chip, URTWN_CHIP_92EU)) 479 urtwn_r88e_read_rom(sc); 480 else 481 urtwn_read_rom(sc); 482 483 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 484 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 485 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 486 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 487 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 488 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 489 "8188CUS", sc->ntxchains, sc->nrxchains, 490 ether_sprintf(ic->ic_macaddr)); 491 492 error = urtwn_open_pipes(sc); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 495 goto fail; 496 } 497 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 498 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 499 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 500 501 /* 502 * Setup the 802.11 device. 503 */ 504 ic->ic_softc = sc; 505 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 506 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 507 508 /* Set device capabilities. */ 509 ic->ic_caps = 510 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 511 IEEE80211_C_IBSS | /* IBSS mode supported */ 512 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 513 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 514 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 515 IEEE80211_C_WME | /* 802.11e */ 516 IEEE80211_C_WPA; /* 802.11i */ 517 518 ic->ic_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 519 520 #ifdef should_delete_NNN 521 /* Set supported .11b and .11g channels (1 through 14). */ 522 ic->ic_nchans = 14; /* NNN ? get this from somewhere? */ 523 for (i = 0; i < 14; i++) { 524 ic->ic_channels[i].ic_freq = 525 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 526 ic->ic_channels[i].ic_flags = 527 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 528 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 529 } 530 #else 531 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 532 ic->ic_channels); 533 #endif 534 /* XXX issues here ... Figure out proper attach and vap creation */ 535 ieee80211_ifattach(ic); 536 537 /* override default methods NNN Need more here? */ 538 ic->ic_newassoc = urtwn_newassoc; 539 ic->ic_wme.wme_update = urtwn_wme_update; 540 ic->ic_vap_create = urtwn_vap_create; 541 ic->ic_vap_delete = urtwn_vap_delete; 542 ic->ic_parent = urtwn_parent; 543 ic->ic_scan_start = urtwn_scan_start; 544 ic->ic_scan_end = urtwn_scan_end; 545 ic->ic_set_channel = urtwn_set_channel; 546 ic->ic_transmit = urtwn_transmit; 547 // ic->ic_send_mgmt = urtwn_send_mgmt; 548 ic->ic_raw_xmit = urtwn_raw_xmit; 549 ic->ic_getradiocaps = urtwn_getradiocaps; 550 551 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 552 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 553 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 554 555 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 556 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 557 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 558 559 ieee80211_announce(ic); 560 561 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 562 563 if (!pmf_device_register(self, NULL, NULL)) 564 aprint_error_dev(self, "couldn't establish power handler\n"); 565 566 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 567 568 /* Should be called via an IOCTL. Temp call here for now. */ 569 570 struct ieee80211vap *vap = 571 urtwn_vap_create(ic, device_xname(sc->sc_dev), 572 device_unit(sc->sc_dev), IEEE80211_M_STA, 573 IEEE80211_CLONE_MACADDR, ic->ic_macaddr, ic->ic_macaddr); 574 575 if (vap == NULL) { 576 /* Didn't work ... now what! */ 577 printf ("NNN vap_create didn't work ...\n"); 578 ieee80211_ifdetach(ic); 579 goto fail; 580 } 581 582 return; 583 584 fail: 585 sc->sc_dying = 1; 586 aprint_error_dev(self, "attach failed\n"); 587 } 588 589 static int 590 urtwn_detach(device_t self, int flags) 591 { 592 struct urtwn_softc *sc = device_private(self); 593 struct ieee80211com *ic = &sc->sc_ic; 594 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 595 struct ifnet *ifp = vap->iv_ifp; 596 int s; 597 598 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 599 600 pmf_device_deregister(self); 601 602 s = splusb(); 603 604 sc->sc_dying = 1; 605 606 callout_halt(&sc->sc_scan_to, NULL); 607 callout_halt(&sc->sc_calib_to, NULL); 608 609 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 610 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 611 NULL); 612 urtwn_stop(ifp, 0); 613 // vap_detach(...) ?? 614 615 ieee80211_ifdetach(&sc->sc_ic); 616 617 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 618 urtwn_close_pipes(sc); 619 } 620 621 /* sendq destroy */ 622 IFQ_PURGE(&sc->sc_sendq); 623 IFQ_LOCK_DESTROY(&sc->sc_sendq); 624 625 splx(s); 626 627 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 628 629 callout_destroy(&sc->sc_scan_to); 630 callout_destroy(&sc->sc_calib_to); 631 632 mutex_destroy(&sc->sc_write_mtx); 633 mutex_destroy(&sc->sc_fwcmd_mtx); 634 mutex_destroy(&sc->sc_tx_mtx); 635 mutex_destroy(&sc->sc_rx_mtx); 636 mutex_destroy(&sc->sc_task_mtx); 637 638 return 0; 639 } 640 641 static int 642 urtwn_activate(device_t self, enum devact act) 643 { 644 struct urtwn_softc *sc = device_private(self); 645 646 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 647 648 switch (act) { 649 case DVACT_DEACTIVATE: 650 if_deactivate(TAILQ_FIRST(&(sc->sc_ic.ic_vaps))->iv_ifp); 651 652 return 0; 653 default: 654 return EOPNOTSUPP; 655 } 656 } 657 658 static int 659 urtwn_open_pipes(struct urtwn_softc *sc) 660 { 661 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 662 static uint8_t epaddr[R92C_MAX_EPOUT]; 663 static uint8_t rxepaddr[R92C_MAX_EPIN]; 664 usb_interface_descriptor_t *id; 665 usb_endpoint_descriptor_t *ed; 666 size_t i, ntx = 0, nrx = 0; 667 int error; 668 669 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 670 671 /* Determine the number of bulk-out pipes. */ 672 id = usbd_get_interface_descriptor(sc->sc_iface); 673 for (i = 0; i < id->bNumEndpoints; i++) { 674 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 675 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 676 continue; 677 } 678 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 679 if (ntx < sizeof(epaddr)) 680 epaddr[ntx] = ed->bEndpointAddress; 681 ntx++; 682 } 683 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 684 if (nrx < sizeof(rxepaddr)) 685 rxepaddr[nrx] = ed->bEndpointAddress; 686 nrx++; 687 } 688 } 689 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 690 aprint_error_dev(sc->sc_dev, 691 "%zd: invalid number of Rx bulk pipes\n", nrx); 692 return EIO; 693 } 694 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 695 aprint_error_dev(sc->sc_dev, 696 "%zd: invalid number of Tx bulk pipes\n", ntx); 697 return EIO; 698 } 699 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 700 device_xname(sc->sc_dev), __func__, nrx, ntx)); 701 sc->rx_npipe = nrx; 702 sc->tx_npipe = ntx; 703 704 /* Open bulk-in pipe at address 0x81. */ 705 for (i = 0; i < nrx; i++) { 706 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 707 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 708 if (error != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "could not open Rx bulk pipe 0x%02x: %d\n", 711 rxepaddr[i], error); 712 goto fail; 713 } 714 } 715 716 /* Open bulk-out pipes (up to 3). */ 717 for (i = 0; i < ntx; i++) { 718 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 719 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 720 if (error != 0) { 721 aprint_error_dev(sc->sc_dev, 722 "could not open Tx bulk pipe 0x%02x: %d\n", 723 epaddr[i], error); 724 goto fail; 725 } 726 } 727 728 /* Map 802.11 access categories to USB pipes. */ 729 sc->ac2idx[WME_AC_BK] = 730 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 731 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 732 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 733 734 fail: 735 if (error != 0) 736 urtwn_close_pipes(sc); 737 return error; 738 } 739 740 static void 741 urtwn_close_pipes(struct urtwn_softc *sc) 742 { 743 struct usbd_pipe *pipe; 744 size_t i; 745 746 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 747 748 /* Close Rx pipes. */ 749 CTASSERT(sizeof(pipe) == sizeof(void *)); 750 for (i = 0; i < sc->rx_npipe; i++) { 751 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 752 if (pipe != NULL) { 753 usbd_close_pipe(pipe); 754 } 755 } 756 757 /* Close Tx pipes. */ 758 for (i = 0; i < sc->tx_npipe; i++) { 759 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 760 if (pipe != NULL) { 761 usbd_close_pipe(pipe); 762 } 763 } 764 } 765 766 static int 767 urtwn_alloc_rx_list(struct urtwn_softc *sc) 768 { 769 struct urtwn_rx_data *data; 770 size_t i; 771 int error = 0; 772 773 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 774 775 for (size_t j = 0; j < sc->rx_npipe; j++) { 776 TAILQ_INIT(&sc->rx_free_list[j]); 777 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 778 data = &sc->rx_data[j][i]; 779 780 data->sc = sc; /* Backpointer for callbacks. */ 781 782 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 783 0, 0, &data->xfer); 784 if (error) { 785 aprint_error_dev(sc->sc_dev, 786 "could not allocate xfer\n"); 787 break; 788 } 789 790 data->buf = usbd_get_buffer(data->xfer); 791 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 792 } 793 } 794 if (error != 0) 795 urtwn_free_rx_list(sc); 796 return error; 797 } 798 799 static void 800 urtwn_free_rx_list(struct urtwn_softc *sc) 801 { 802 struct usbd_xfer *xfer; 803 size_t i; 804 805 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 806 807 /* NB: Caller must abort pipe first. */ 808 for (size_t j = 0; j < sc->rx_npipe; j++) { 809 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 810 CTASSERT(sizeof(xfer) == sizeof(void *)); 811 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 812 if (xfer != NULL) 813 usbd_destroy_xfer(xfer); 814 } 815 } 816 } 817 818 static int 819 urtwn_alloc_tx_list(struct urtwn_softc *sc) 820 { 821 struct urtwn_tx_data *data; 822 size_t i; 823 int error = 0; 824 825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 826 827 mutex_enter(&sc->sc_tx_mtx); 828 for (size_t j = 0; j < sc->tx_npipe; j++) { 829 TAILQ_INIT(&sc->tx_free_list[j]); 830 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 831 data = &sc->tx_data[j][i]; 832 833 data->sc = sc; /* Backpointer for callbacks. */ 834 data->pidx = j; 835 836 error = usbd_create_xfer(sc->tx_pipe[j], 837 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 838 &data->xfer); 839 if (error) { 840 aprint_error_dev(sc->sc_dev, 841 "could not allocate xfer\n"); 842 goto fail; 843 } 844 845 data->buf = usbd_get_buffer(data->xfer); 846 847 /* Append this Tx buffer to our free list. */ 848 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 849 } 850 } 851 mutex_exit(&sc->sc_tx_mtx); 852 return 0; 853 854 fail: 855 urtwn_free_tx_list(sc); 856 mutex_exit(&sc->sc_tx_mtx); 857 return error; 858 } 859 860 static void 861 urtwn_free_tx_list(struct urtwn_softc *sc) 862 { 863 struct usbd_xfer *xfer; 864 size_t i; 865 866 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 867 868 /* NB: Caller must abort pipe first. */ 869 for (size_t j = 0; j < sc->tx_npipe; j++) { 870 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 871 CTASSERT(sizeof(xfer) == sizeof(void *)); 872 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 873 if (xfer != NULL) 874 usbd_destroy_xfer(xfer); 875 } 876 } 877 } 878 879 static int 880 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 881 struct ieee80211_node *ni) 882 { 883 struct urtwn_tx_data *data = 884 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 885 return urtwn_tx(sc, m, ni, data); 886 } 887 888 static void 889 urtwn_task(void *arg) 890 { 891 struct urtwn_softc *sc = arg; 892 struct ieee80211com *ic = &sc->sc_ic; 893 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 894 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 895 struct urtwn_host_cmd *cmd; 896 int s; 897 898 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 899 if (vap->iv_state == IEEE80211_S_RUN && 900 (ic->ic_opmode == IEEE80211_M_HOSTAP || 901 ic->ic_opmode == IEEE80211_M_IBSS)) { 902 struct mbuf *m = ieee80211_beacon_alloc(vap->iv_bss); 903 if (m == NULL) { 904 aprint_error_dev(sc->sc_dev, 905 "could not allocate beacon"); 906 } 907 908 if (urtwn_tx_beacon(sc, m, vap->iv_bss) != 0) { 909 m_freem(m); 910 aprint_error_dev(sc->sc_dev, "could not send beacon"); 911 } 912 913 /* beacon is no longer needed */ 914 m_freem(m); 915 } 916 917 /* Process host commands. */ 918 s = splusb(); 919 mutex_spin_enter(&sc->sc_task_mtx); 920 while (ring->next != ring->cur) { 921 cmd = &ring->cmd[ring->next]; 922 mutex_spin_exit(&sc->sc_task_mtx); 923 splx(s); 924 /* Invoke callback with kernel lock held. */ 925 cmd->cb(sc, cmd->data); 926 s = splusb(); 927 mutex_spin_enter(&sc->sc_task_mtx); 928 ring->queued--; 929 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 930 } 931 mutex_spin_exit(&sc->sc_task_mtx); 932 wakeup(&sc->cmdq); 933 splx(s); 934 } 935 936 static void 937 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc*, void *), 938 void *arg, int len) 939 { 940 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 941 struct urtwn_host_cmd *cmd; 942 int s; 943 944 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 945 device_xname(sc->sc_dev), __func__, cb, arg, len)); 946 947 s = splusb(); 948 mutex_spin_enter(&sc->sc_task_mtx); 949 cmd = &ring->cmd[ring->cur]; 950 cmd->cb = cb; 951 KASSERT(len <= sizeof(cmd->data)); 952 memcpy(cmd->data, arg, len); 953 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 954 955 /* If there is no pending command already, schedule a task. */ 956 if (!sc->sc_dying && ++ring->queued == 1) { 957 mutex_spin_exit(&sc->sc_task_mtx); 958 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 959 } else 960 mutex_spin_exit(&sc->sc_task_mtx); 961 splx(s); 962 } 963 964 static void 965 urtwn_wait_async(struct urtwn_softc *sc) 966 { 967 968 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 969 970 /* Wait for all queued asynchronous commands to complete. */ 971 while (sc->cmdq.queued > 0) 972 tsleep(&sc->cmdq, 0, "endtask", 0); 973 } 974 975 static int 976 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 977 int len) 978 { 979 usb_device_request_t req; 980 usbd_status error; 981 982 KASSERT(mutex_owned(&sc->sc_write_mtx)); 983 984 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 985 req.bRequest = R92C_REQ_REGS; 986 USETW(req.wValue, addr); 987 USETW(req.wIndex, 0); 988 USETW(req.wLength, len); 989 error = usbd_do_request(sc->sc_udev, &req, buf); 990 if (error != USBD_NORMAL_COMPLETION) { 991 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 992 device_xname(sc->sc_dev), __func__, error, addr, len)); 993 } 994 return error; 995 } 996 997 static void 998 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 999 { 1000 1001 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1002 device_xname(sc->sc_dev), __func__, addr, val)); 1003 1004 urtwn_write_region_1(sc, addr, &val, 1); 1005 } 1006 1007 static void 1008 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1009 { 1010 uint8_t buf[2]; 1011 1012 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1013 device_xname(sc->sc_dev), __func__, addr, val)); 1014 1015 buf[0] = (uint8_t)val; 1016 buf[1] = (uint8_t)(val >> 8); 1017 urtwn_write_region_1(sc, addr, buf, 2); 1018 } 1019 1020 static void 1021 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1022 { 1023 uint8_t buf[4]; 1024 1025 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1026 device_xname(sc->sc_dev), __func__, addr, val)); 1027 1028 buf[0] = (uint8_t)val; 1029 buf[1] = (uint8_t)(val >> 8); 1030 buf[2] = (uint8_t)(val >> 16); 1031 buf[3] = (uint8_t)(val >> 24); 1032 urtwn_write_region_1(sc, addr, buf, 4); 1033 } 1034 1035 static int 1036 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1037 { 1038 1039 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, len=%#x\n", 1040 device_xname(sc->sc_dev), __func__, addr, len)); 1041 1042 return urtwn_write_region_1(sc, addr, buf, len); 1043 } 1044 1045 static int 1046 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1047 int len) 1048 { 1049 usb_device_request_t req; 1050 usbd_status error; 1051 1052 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1053 req.bRequest = R92C_REQ_REGS; 1054 USETW(req.wValue, addr); 1055 USETW(req.wIndex, 0); 1056 USETW(req.wLength, len); 1057 error = usbd_do_request(sc->sc_udev, &req, buf); 1058 if (error != USBD_NORMAL_COMPLETION) { 1059 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=%#x, len=%d\n", 1060 device_xname(sc->sc_dev), __func__, error, addr, len)); 1061 } 1062 return error; 1063 } 1064 1065 static uint8_t 1066 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1067 { 1068 uint8_t val; 1069 1070 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1071 return 0xff; 1072 1073 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1074 device_xname(sc->sc_dev), __func__, addr, val)); 1075 return val; 1076 } 1077 1078 static uint16_t 1079 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1080 { 1081 uint8_t buf[2]; 1082 uint16_t val; 1083 1084 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1085 return 0xffff; 1086 1087 val = LE_READ_2(&buf[0]); 1088 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1089 device_xname(sc->sc_dev), __func__, addr, val)); 1090 return val; 1091 } 1092 1093 static uint32_t 1094 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1095 { 1096 uint8_t buf[4]; 1097 uint32_t val; 1098 1099 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1100 return 0xffffffff; 1101 1102 val = LE_READ_4(&buf[0]); 1103 DPRINTFN(DBG_REG, ("%s: %s: addr=%#x, val=%#x\n", 1104 device_xname(sc->sc_dev), __func__, addr, val)); 1105 return val; 1106 } 1107 1108 static int 1109 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1110 { 1111 struct r92c_fw_cmd cmd; 1112 uint8_t *cp; 1113 int fwcur; 1114 int ntries; 1115 1116 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1117 device_xname(sc->sc_dev), __func__, id, buf, len)); 1118 1119 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1120 1121 mutex_enter(&sc->sc_fwcmd_mtx); 1122 fwcur = sc->fwcur; 1123 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1124 mutex_exit(&sc->sc_fwcmd_mtx); 1125 1126 /* Wait for current FW box to be empty. */ 1127 for (ntries = 0; ntries < 100; ntries++) { 1128 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1129 break; 1130 DELAY(2000); 1131 } 1132 if (ntries == 100) { 1133 aprint_error_dev(sc->sc_dev, 1134 "could not send firmware command %d\n", id); 1135 return ETIMEDOUT; 1136 } 1137 1138 memset(&cmd, 0, sizeof(cmd)); 1139 KASSERT(len <= sizeof(cmd.msg)); 1140 memcpy(cmd.msg, buf, len); 1141 1142 /* Write the first word last since that will trigger the FW. */ 1143 cp = (uint8_t *)&cmd; 1144 cmd.id = id; 1145 if (len >= 4) { 1146 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1147 cmd.id |= R92C_CMD_FLAG_EXT; 1148 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1149 &cp[1], 2); 1150 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1151 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1152 (cp[5] << 24)); 1153 } else { 1154 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1155 &cp[4], 2); 1156 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1157 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1158 (cp[3] << 24)); 1159 } 1160 } else { 1161 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1162 } 1163 1164 return 0; 1165 } 1166 1167 static __inline void 1168 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1169 { 1170 1171 sc->sc_rf_write(sc, chain, addr, val); 1172 } 1173 1174 static void 1175 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1176 uint32_t val) 1177 { 1178 1179 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1180 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1181 } 1182 1183 static void 1184 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1185 uint32_t val) 1186 { 1187 1188 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1189 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1190 } 1191 1192 static void 1193 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1194 uint32_t val) 1195 { 1196 1197 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1198 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1199 } 1200 1201 static uint32_t 1202 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1203 { 1204 uint32_t reg[R92C_MAX_CHAINS], val; 1205 1206 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1207 if (chain != 0) { 1208 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1209 } 1210 1211 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1212 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1213 DELAY(1000); 1214 1215 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1216 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1217 R92C_HSSI_PARAM2_READ_EDGE); 1218 DELAY(1000); 1219 1220 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1221 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1222 DELAY(1000); 1223 1224 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1225 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1226 } else { 1227 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1228 } 1229 return MS(val, R92C_LSSI_READBACK_DATA); 1230 } 1231 1232 static int 1233 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1234 { 1235 int ntries; 1236 1237 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1238 1239 urtwn_write_4(sc, R92C_LLT_INIT, 1240 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1241 SM(R92C_LLT_INIT_ADDR, addr) | 1242 SM(R92C_LLT_INIT_DATA, data)); 1243 /* Wait for write operation to complete. */ 1244 for (ntries = 0; ntries < 20; ntries++) { 1245 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1246 R92C_LLT_INIT_OP_NO_ACTIVE) { 1247 /* Done */ 1248 return 0; 1249 } 1250 DELAY(5); 1251 } 1252 return ETIMEDOUT; 1253 } 1254 1255 static uint8_t 1256 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1257 { 1258 uint32_t reg; 1259 int ntries; 1260 1261 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1262 1263 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1264 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1265 reg &= ~R92C_EFUSE_CTRL_VALID; 1266 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1267 1268 /* Wait for read operation to complete. */ 1269 for (ntries = 0; ntries < 100; ntries++) { 1270 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1271 if (reg & R92C_EFUSE_CTRL_VALID) { 1272 /* Done */ 1273 return MS(reg, R92C_EFUSE_CTRL_DATA); 1274 } 1275 DELAY(5); 1276 } 1277 aprint_error_dev(sc->sc_dev, 1278 "could not read efuse byte at address 0x%04x\n", addr); 1279 return 0xff; 1280 } 1281 1282 static void 1283 urtwn_efuse_read(struct urtwn_softc *sc) 1284 { 1285 uint8_t *rom = (uint8_t *)&sc->rom; 1286 uint32_t reg; 1287 uint16_t addr = 0; 1288 uint8_t off, msk; 1289 size_t i; 1290 1291 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1292 1293 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1294 1295 urtwn_efuse_switch_power(sc); 1296 1297 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1298 while (addr < 512) { 1299 reg = urtwn_efuse_read_1(sc, addr); 1300 if (reg == 0xff) 1301 break; 1302 addr++; 1303 off = reg >> 4; 1304 msk = reg & 0xf; 1305 for (i = 0; i < 4; i++) { 1306 if (msk & (1U << i)) 1307 continue; 1308 1309 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1310 addr++; 1311 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1312 addr++; 1313 } 1314 } 1315 #ifdef URTWN_DEBUG 1316 if (urtwn_debug & DBG_INIT) { 1317 /* Dump ROM content. */ 1318 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1319 for (i = 0; i < (int)sizeof(sc->rom); i++) 1320 printf(":%02x", rom[i]); 1321 printf("\n"); 1322 } 1323 #endif 1324 } 1325 1326 static void 1327 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1328 { 1329 uint32_t reg; 1330 1331 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1332 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1333 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1334 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1335 } 1336 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1337 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1338 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1339 reg | R92C_SYS_FUNC_EN_ELDR); 1340 } 1341 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1342 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1343 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1344 urtwn_write_2(sc, R92C_SYS_CLKR, 1345 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1346 } 1347 } 1348 1349 static int 1350 urtwn_read_chipid(struct urtwn_softc *sc) 1351 { 1352 uint32_t reg; 1353 1354 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1355 1356 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1357 ISSET(sc->chip, URTWN_CHIP_92EU)) 1358 return 0; 1359 1360 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1361 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1362 /* test chip, not supported */ 1363 return EIO; 1364 } 1365 if (reg & R92C_SYS_CFG_TYPE_92C) { 1366 sc->chip |= URTWN_CHIP_92C; 1367 /* Check if it is a castrated 8192C. */ 1368 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1369 R92C_HPON_FSM_CHIP_BONDING_ID) == 1370 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1371 sc->chip |= URTWN_CHIP_92C_1T2R; 1372 } 1373 } 1374 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1375 sc->chip |= URTWN_CHIP_UMC; 1376 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1377 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1378 } 1379 } 1380 return 0; 1381 } 1382 1383 #ifdef URTWN_DEBUG 1384 static void 1385 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1386 { 1387 1388 aprint_normal_dev(sc->sc_dev, 1389 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1390 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1391 1392 aprint_normal_dev(sc->sc_dev, 1393 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1394 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1395 1396 aprint_normal_dev(sc->sc_dev, 1397 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1398 rp->macaddr[0], rp->macaddr[1], 1399 rp->macaddr[2], rp->macaddr[3], 1400 rp->macaddr[4], rp->macaddr[5]); 1401 1402 aprint_normal_dev(sc->sc_dev, 1403 "string %s, subcustomer_id %#x\n", 1404 rp->string, rp->subcustomer_id); 1405 1406 aprint_normal_dev(sc->sc_dev, 1407 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1408 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1409 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1410 1411 aprint_normal_dev(sc->sc_dev, 1412 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1413 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1414 rp->ht40_1s_tx_pwr[0][2], 1415 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1416 rp->ht40_1s_tx_pwr[1][2]); 1417 1418 aprint_normal_dev(sc->sc_dev, 1419 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1420 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1421 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1422 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1423 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1424 1425 aprint_normal_dev(sc->sc_dev, 1426 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1427 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1428 rp->ht20_tx_pwr_diff[2] & 0xf, 1429 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1430 rp->ht20_tx_pwr_diff[2] >> 4); 1431 1432 aprint_normal_dev(sc->sc_dev, 1433 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1434 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1435 rp->ofdm_tx_pwr_diff[2] & 0xf, 1436 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1437 rp->ofdm_tx_pwr_diff[2] >> 4); 1438 1439 aprint_normal_dev(sc->sc_dev, 1440 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1441 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1442 rp->ht40_max_pwr[2] & 0xf, 1443 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1444 rp->ht40_max_pwr[2] >> 4); 1445 1446 aprint_normal_dev(sc->sc_dev, 1447 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1448 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1449 rp->ht20_max_pwr[2] & 0xf, 1450 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1451 rp->ht20_max_pwr[2] >> 4); 1452 1453 aprint_normal_dev(sc->sc_dev, 1454 "xtal_calib %d, tssi %d %d, thermal %d\n", 1455 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1456 1457 aprint_normal_dev(sc->sc_dev, 1458 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1459 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1460 1461 aprint_normal_dev(sc->sc_dev, 1462 "channnel_plan %d, version %d customer_id %#x\n", 1463 rp->channel_plan, rp->version, rp->curstomer_id); 1464 } 1465 #endif 1466 1467 static void 1468 urtwn_read_rom(struct urtwn_softc *sc) 1469 { 1470 struct ieee80211com *ic = &sc->sc_ic; 1471 struct r92c_rom *rom = &sc->rom; 1472 1473 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1474 1475 mutex_enter(&sc->sc_write_mtx); 1476 1477 /* Read full ROM image. */ 1478 urtwn_efuse_read(sc); 1479 #ifdef URTWN_DEBUG 1480 if (urtwn_debug & DBG_REG) 1481 urtwn_dump_rom(sc, rom); 1482 #endif 1483 1484 /* XXX Weird but this is what the vendor driver does. */ 1485 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1486 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1487 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1488 1489 DPRINTFN(DBG_INIT, 1490 ("%s: %s: PA setting=%#x, board=%#x, regulatory=%d\n", 1491 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1492 sc->board_type, sc->regulatory)); 1493 1494 IEEE80211_ADDR_COPY(ic->ic_macaddr, rom->macaddr); 1495 1496 sc->sc_rf_write = urtwn_r92c_rf_write; 1497 sc->sc_power_on = urtwn_r92c_power_on; 1498 sc->sc_dma_init = urtwn_r92c_dma_init; 1499 1500 mutex_exit(&sc->sc_write_mtx); 1501 } 1502 1503 static void 1504 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1505 { 1506 struct ieee80211com *ic = &sc->sc_ic; 1507 uint8_t *rom = sc->r88e_rom; 1508 uint32_t reg; 1509 uint16_t addr = 0; 1510 uint8_t off, msk, tmp; 1511 int i; 1512 1513 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1514 1515 mutex_enter(&sc->sc_write_mtx); 1516 1517 off = 0; 1518 urtwn_efuse_switch_power(sc); 1519 1520 /* Read full ROM image. */ 1521 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1522 while (addr < 4096) { 1523 reg = urtwn_efuse_read_1(sc, addr); 1524 if (reg == 0xff) 1525 break; 1526 addr++; 1527 if ((reg & 0x1f) == 0x0f) { 1528 tmp = (reg & 0xe0) >> 5; 1529 reg = urtwn_efuse_read_1(sc, addr); 1530 if ((reg & 0x0f) != 0x0f) 1531 off = ((reg & 0xf0) >> 1) | tmp; 1532 addr++; 1533 } else 1534 off = reg >> 4; 1535 msk = reg & 0xf; 1536 for (i = 0; i < 4; i++) { 1537 if (msk & (1 << i)) 1538 continue; 1539 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1540 addr++; 1541 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1542 addr++; 1543 } 1544 } 1545 #ifdef URTWN_DEBUG 1546 if (urtwn_debug & DBG_REG) { 1547 } 1548 #endif 1549 1550 addr = 0x10; 1551 for (i = 0; i < 6; i++) 1552 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1553 for (i = 0; i < 5; i++) 1554 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1555 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1556 if (sc->bw20_tx_pwr_diff & 0x08) 1557 sc->bw20_tx_pwr_diff |= 0xf0; 1558 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1559 if (sc->ofdm_tx_pwr_diff & 0x08) 1560 sc->ofdm_tx_pwr_diff |= 0xf0; 1561 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1562 1563 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->r88e_rom[0xd7]); 1564 1565 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1566 sc->sc_power_on = urtwn_r92e_power_on; 1567 sc->sc_rf_write = urtwn_r92e_rf_write; 1568 } else { 1569 sc->sc_power_on = urtwn_r88e_power_on; 1570 sc->sc_rf_write = urtwn_r88e_rf_write; 1571 } 1572 sc->sc_dma_init = urtwn_r88e_dma_init; 1573 1574 mutex_exit(&sc->sc_write_mtx); 1575 } 1576 1577 /* NNN Do we need to do something with this? */ 1578 1579 static __unused int 1580 urtwn_media_change(struct ifnet *ifp) 1581 { 1582 #ifdef URTWN_DEBUG 1583 struct ieee80211vap *vap = ifp->if_softc; 1584 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1585 #endif 1586 int error; 1587 1588 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1589 1590 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1591 return error; 1592 1593 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1594 (IFF_UP | IFF_RUNNING)) { 1595 urtwn_init(ifp); 1596 } 1597 return 0; 1598 } 1599 1600 /* 1601 * Initialize rate adaptation in firmware. 1602 */ 1603 static int 1604 urtwn_ra_init(struct ieee80211vap *vap) 1605 { 1606 static const uint8_t map[] = { 1607 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1608 }; 1609 struct ieee80211com *ic = vap->iv_ic; 1610 struct urtwn_softc *sc = ic->ic_softc; 1611 struct ieee80211_node *ni = vap->iv_bss; 1612 struct ieee80211_rateset *rs = &ni->ni_rates; 1613 1614 struct r92c_fw_cmd_macid_cfg cmd; 1615 uint32_t rates, basicrates; 1616 uint32_t rrsr_mask, rrsr_rate; 1617 uint8_t mode; 1618 size_t maxrate, maxbasicrate, i, j; 1619 int error; 1620 1621 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1622 1623 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1624 1625 /* Get normal and basic rates mask. */ 1626 rates = basicrates = 1; 1627 maxrate = maxbasicrate = 0; 1628 for (i = 0; i < rs->rs_nrates; i++) { 1629 /* Convert 802.11 rate to HW rate index. */ 1630 for (j = 0; j < __arraycount(map); j++) { 1631 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1632 break; 1633 } 1634 } 1635 if (j == __arraycount(map)) { 1636 /* Unknown rate, skip. */ 1637 continue; 1638 } 1639 1640 rates |= 1U << j; 1641 if (j > maxrate) { 1642 maxrate = j; 1643 } 1644 1645 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1646 basicrates |= 1U << j; 1647 if (j > maxbasicrate) { 1648 maxbasicrate = j; 1649 } 1650 } 1651 } 1652 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1653 mode = R92C_RAID_11B; 1654 } else { 1655 mode = R92C_RAID_11BG; 1656 } 1657 DPRINTFN(DBG_INIT, ("%s: %s: mode=%#x rates=%#x, basicrates=%#x, " 1658 "maxrate=%zx, maxbasicrate=%zx\n", 1659 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1660 maxrate, maxbasicrate)); 1661 1662 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1663 maxbasicrate |= R92C_RATE_SHORTGI; 1664 maxrate |= R92C_RATE_SHORTGI; 1665 } 1666 1667 /* Set rates mask for group addressed frames. */ 1668 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1669 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1670 cmd.macid |= RTWN_MACID_SHORTGI; 1671 cmd.mask = htole32((mode << 28) | basicrates); 1672 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1673 if (error != 0) { 1674 aprint_error_dev(sc->sc_dev, 1675 "could not add broadcast station\n"); 1676 return error; 1677 } 1678 /* Set initial MRR rate. */ 1679 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1680 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1681 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1682 1683 /* Set rates mask for unicast frames. */ 1684 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1685 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1686 cmd.macid |= RTWN_MACID_SHORTGI; 1687 cmd.mask = htole32((mode << 28) | rates); 1688 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1689 if (error != 0) { 1690 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1691 return error; 1692 } 1693 /* Set initial MRR rate. */ 1694 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1695 __func__, maxrate)); 1696 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1697 1698 #if notyet 1699 /* NNN appears to have no fixed rate anywhere. */ 1700 rrsr_rate = ic->ic_fixed_rate; 1701 if (rrsr_rate == -1) 1702 #endif 1703 rrsr_rate = 11; 1704 1705 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1706 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1707 1708 #if notyet 1709 /* Indicate highest supported rate. */ 1710 ni->ni_txrate = rs->rs_nrates - 1; 1711 #endif 1712 return 0; 1713 } 1714 1715 static int 1716 urtwn_get_nettype(struct urtwn_softc *sc) 1717 { 1718 struct ieee80211com *ic = &sc->sc_ic; 1719 int type; 1720 1721 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1722 1723 switch (ic->ic_opmode) { 1724 case IEEE80211_M_STA: 1725 type = R92C_CR_NETTYPE_INFRA; 1726 break; 1727 1728 case IEEE80211_M_IBSS: 1729 type = R92C_CR_NETTYPE_ADHOC; 1730 break; 1731 1732 default: 1733 type = R92C_CR_NETTYPE_NOLINK; 1734 break; 1735 } 1736 1737 return type; 1738 } 1739 1740 static void 1741 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1742 { 1743 uint8_t reg; 1744 1745 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1746 __func__, type)); 1747 1748 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1749 1750 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1751 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1752 } 1753 1754 static void 1755 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1756 { 1757 struct ieee80211vap *vap = TAILQ_FIRST(&sc->sc_ic.ic_vaps); 1758 struct ieee80211_node *ni = vap->iv_bss; 1759 uint64_t tsf; 1760 1761 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1762 1763 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1764 1765 /* Enable TSF synchronization. */ 1766 urtwn_write_1(sc, R92C_BCN_CTRL, 1767 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1768 1769 /* Correct TSF */ 1770 urtwn_write_1(sc, R92C_BCN_CTRL, 1771 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1772 1773 /* Set initial TSF. */ 1774 tsf = ni->ni_tstamp.tsf; 1775 tsf = le64toh(tsf); 1776 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1777 tsf -= IEEE80211_DUR_TU; 1778 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1779 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1780 1781 urtwn_write_1(sc, R92C_BCN_CTRL, 1782 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1783 } 1784 1785 static void 1786 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1787 { 1788 uint8_t reg; 1789 1790 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1791 __func__, led, on)); 1792 1793 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1794 1795 if (led == URTWN_LED_LINK) { 1796 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1797 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1798 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1799 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1800 (R92C_LEDCFG0_DIS << 1)); 1801 if (on) { 1802 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1803 R92E_LEDSON; 1804 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1805 } 1806 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1807 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1808 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1809 if (!on) { 1810 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1811 urtwn_write_1(sc, R92C_LEDCFG2, 1812 reg | R92C_LEDCFG0_DIS); 1813 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1814 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1815 reg & 0xfe); 1816 } 1817 } else { 1818 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1819 if (!on) { 1820 reg |= R92C_LEDCFG0_DIS; 1821 } 1822 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1823 } 1824 sc->ledlink = on; /* Save LED state. */ 1825 } 1826 } 1827 1828 static void 1829 urtwn_calib_to(void *arg) 1830 { 1831 struct urtwn_softc *sc = arg; 1832 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1833 1834 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1835 1836 if (sc->sc_dying) 1837 return; 1838 1839 /* Do it in a process context. */ 1840 urtwn_do_async(sc, urtwn_calib_to_cb, vap, sizeof(struct ieee80211vap *)); 1841 } 1842 1843 /* ARGSUSED */ 1844 static void 1845 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1846 { 1847 struct ieee80211vap *vap = arg; 1848 struct r92c_fw_cmd_rssi cmd; 1849 struct r92e_fw_cmd_rssi cmde; 1850 1851 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1852 1853 if (vap->iv_state != IEEE80211_S_RUN) 1854 goto restart_timer; 1855 1856 mutex_enter(&sc->sc_write_mtx); 1857 if (sc->avg_pwdb != -1) { 1858 /* Indicate Rx signal strength to FW for rate adaptation. */ 1859 memset(&cmd, 0, sizeof(cmd)); 1860 memset(&cmde, 0, sizeof(cmde)); 1861 cmd.macid = 0; /* BSS. */ 1862 cmde.macid = 0; /* BSS. */ 1863 cmd.pwdb = sc->avg_pwdb; 1864 cmde.pwdb = sc->avg_pwdb; 1865 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1866 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1867 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1868 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1869 sizeof(cmd)); 1870 } else { 1871 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1872 sizeof(cmde)); 1873 } 1874 } 1875 1876 /* Do temperature compensation. */ 1877 urtwn_temp_calib(sc); 1878 mutex_exit(&sc->sc_write_mtx); 1879 1880 restart_timer: 1881 if (!sc->sc_dying) { 1882 /* Restart calibration timer. */ 1883 callout_schedule(&sc->sc_calib_to, hz); 1884 } 1885 } 1886 1887 static void 1888 urtwn_next_scan(void *arg) 1889 { 1890 printf ("NNN urtwn_next_scan called....\n"); 1891 #ifdef notyet 1892 struct urtwn_softc *sc = arg; 1893 int s; 1894 1895 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1896 1897 if (sc->sc_dying) 1898 return; 1899 1900 s = splnet(); 1901 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1902 ieee80211_next_scan(&sc->sc_ic); 1903 splx(s); 1904 #endif 1905 } 1906 1907 static void 1908 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1909 { 1910 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1911 ether_sprintf(ni->ni_macaddr))); 1912 1913 /* start with lowest Tx rate */ 1914 ni->ni_txrate = 0; 1915 } 1916 1917 #if OLDSTUFF 1918 static int 1919 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1920 { 1921 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1922 struct urtwn_cmd_newstate cmd; 1923 1924 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1925 device_xname(sc->sc_dev), __func__, 1926 ieee80211_state_name[nstate], nstate, arg)); 1927 1928 callout_stop(&sc->sc_scan_to); 1929 callout_stop(&sc->sc_calib_to); 1930 1931 /* Do it in a process context. */ 1932 cmd.state = nstate; 1933 cmd.arg = arg; 1934 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1935 return 0; 1936 } 1937 1938 static void 1939 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1940 { 1941 struct ieee80211vap *vap = TAILQ_FIRST(&(sc->sc_ic.ic_vaps)); 1942 struct urtwn_cmd_newstate *cmd = arg; 1943 struct ieee80211com *ic = &sc->sc_ic; 1944 struct ieee80211_node *ni; 1945 enum ieee80211_state ostate = vap->iv_state; 1946 enum ieee80211_state nstate = cmd->state; 1947 uint32_t reg; 1948 uint8_t sifs_time, msr; 1949 int s; 1950 1951 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1952 device_xname(sc->sc_dev), __func__, 1953 ieee80211_state_name[ostate], ostate, 1954 ieee80211_state_name[nstate], nstate)); 1955 1956 s = splnet(); 1957 mutex_enter(&sc->sc_write_mtx); 1958 1959 callout_stop(&sc->sc_scan_to); 1960 callout_stop(&sc->sc_calib_to); 1961 1962 switch (ostate) { 1963 case IEEE80211_S_INIT: 1964 break; 1965 1966 case IEEE80211_S_SCAN: 1967 if (nstate != IEEE80211_S_SCAN) { 1968 /* 1969 * End of scanning 1970 */ 1971 /* flush 4-AC Queue after site_survey */ 1972 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1973 1974 /* Allow Rx from our BSSID only. */ 1975 urtwn_write_4(sc, R92C_RCR, 1976 urtwn_read_4(sc, R92C_RCR) | 1977 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1978 } 1979 break; 1980 1981 case IEEE80211_S_AUTH: 1982 case IEEE80211_S_ASSOC: 1983 break; 1984 1985 case IEEE80211_S_RUN: 1986 /* Turn link LED off. */ 1987 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1988 1989 /* Set media status to 'No Link'. */ 1990 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1991 1992 /* Stop Rx of data frames. */ 1993 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1994 1995 /* Reset TSF. */ 1996 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1997 1998 /* Disable TSF synchronization. */ 1999 urtwn_write_1(sc, R92C_BCN_CTRL, 2000 urtwn_read_1(sc, R92C_BCN_CTRL) | 2001 R92C_BCN_CTRL_DIS_TSF_UDT0); 2002 2003 /* Back to 20MHz mode */ 2004 urtwn_set_chan(sc, ic->ic_curchan, 2005 IEEE80211_HTINFO_2NDCHAN_NONE); 2006 2007 if (ic->ic_opmode == IEEE80211_M_IBSS || 2008 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2009 /* Stop BCN */ 2010 urtwn_write_1(sc, R92C_BCN_CTRL, 2011 urtwn_read_1(sc, R92C_BCN_CTRL) & 2012 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2013 } 2014 2015 /* Reset EDCA parameters. */ 2016 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2017 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2018 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2019 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2020 2021 /* flush all cam entries */ 2022 urtwn_cam_init(sc); 2023 break; 2024 case IEEE80211_S_CAC: 2025 case IEEE80211_S_CSA: 2026 case IEEE80211_S_SLEEP: 2027 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2028 /* NNN what do we do in these states? XXX */ 2029 break; 2030 } 2031 2032 switch (nstate) { 2033 case IEEE80211_S_INIT: 2034 /* Turn link LED off. */ 2035 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2036 break; 2037 2038 case IEEE80211_S_SCAN: 2039 if (ostate != IEEE80211_S_SCAN) { 2040 /* 2041 * Begin of scanning 2042 */ 2043 2044 /* Set gain for scanning. */ 2045 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2046 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2047 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2048 2049 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2050 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2051 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2052 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2053 } 2054 2055 /* Set media status to 'No Link'. */ 2056 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2057 2058 /* Allow Rx from any BSSID. */ 2059 urtwn_write_4(sc, R92C_RCR, 2060 urtwn_read_4(sc, R92C_RCR) & 2061 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2062 2063 /* Stop Rx of data frames. */ 2064 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2065 2066 /* Disable update TSF */ 2067 urtwn_write_1(sc, R92C_BCN_CTRL, 2068 urtwn_read_1(sc, R92C_BCN_CTRL) | 2069 R92C_BCN_CTRL_DIS_TSF_UDT0); 2070 } 2071 2072 /* Make link LED blink during scan. */ 2073 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2074 2075 /* Pause AC Tx queues. */ 2076 urtwn_write_1(sc, R92C_TXPAUSE, 2077 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2078 2079 urtwn_set_chan(sc, ic->ic_curchan, 2080 IEEE80211_HTINFO_2NDCHAN_NONE); 2081 2082 /* Start periodic scan. */ 2083 if (!sc->sc_dying) 2084 callout_schedule(&sc->sc_scan_to, hz / 5); 2085 break; 2086 2087 case IEEE80211_S_AUTH: 2088 /* Set initial gain under link. */ 2089 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2090 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2091 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2092 2093 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2094 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2095 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2096 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2097 } 2098 2099 /* Set media status to 'No Link'. */ 2100 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2101 2102 /* Allow Rx from any BSSID. */ 2103 urtwn_write_4(sc, R92C_RCR, 2104 urtwn_read_4(sc, R92C_RCR) & 2105 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2106 2107 urtwn_set_chan(sc, ic->ic_curchan, 2108 IEEE80211_HTINFO_2NDCHAN_NONE); 2109 break; 2110 2111 case IEEE80211_S_ASSOC: 2112 break; 2113 2114 case IEEE80211_S_RUN: 2115 ni = vap->iv_bss; 2116 2117 /* XXX: Set 20MHz mode */ 2118 urtwn_set_chan(sc, ic->ic_curchan, 2119 IEEE80211_HTINFO_2NDCHAN_NONE); 2120 2121 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2122 /* Back to 20MHz mode */ 2123 urtwn_set_chan(sc, ic->ic_curchan, 2124 IEEE80211_HTINFO_2NDCHAN_NONE); 2125 2126 /* Set media status to 'No Link'. */ 2127 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2128 2129 /* Enable Rx of data frames. */ 2130 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2131 2132 /* Allow Rx from any BSSID. */ 2133 urtwn_write_4(sc, R92C_RCR, 2134 urtwn_read_4(sc, R92C_RCR) & 2135 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2136 2137 /* Accept Rx data/control/management frames */ 2138 urtwn_write_4(sc, R92C_RCR, 2139 urtwn_read_4(sc, R92C_RCR) | 2140 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2141 2142 /* Turn link LED on. */ 2143 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2144 break; 2145 } 2146 2147 /* Set media status to 'Associated'. */ 2148 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2149 2150 /* Set BSSID. */ 2151 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2152 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2153 2154 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2155 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2156 } else { 2157 /* 802.11b/g */ 2158 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2159 } 2160 2161 /* Enable Rx of data frames. */ 2162 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2163 2164 /* Set beacon interval. */ 2165 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2166 2167 msr = urtwn_read_1(sc, R92C_MSR); 2168 msr &= R92C_MSR_MASK; 2169 switch (ic->ic_opmode) { 2170 case IEEE80211_M_STA: 2171 /* Allow Rx from our BSSID only. */ 2172 urtwn_write_4(sc, R92C_RCR, 2173 urtwn_read_4(sc, R92C_RCR) | 2174 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2175 2176 /* Enable TSF synchronization. */ 2177 urtwn_tsf_sync_enable(sc); 2178 2179 msr |= R92C_MSR_INFRA; 2180 break; 2181 case IEEE80211_M_HOSTAP: 2182 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2183 2184 /* Allow Rx from any BSSID. */ 2185 urtwn_write_4(sc, R92C_RCR, 2186 urtwn_read_4(sc, R92C_RCR) & 2187 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2188 2189 /* Reset TSF timer to zero. */ 2190 reg = urtwn_read_4(sc, R92C_TCR); 2191 reg &= ~0x01; 2192 urtwn_write_4(sc, R92C_TCR, reg); 2193 reg |= 0x01; 2194 urtwn_write_4(sc, R92C_TCR, reg); 2195 2196 msr |= R92C_MSR_AP; 2197 break; 2198 default: 2199 msr |= R92C_MSR_ADHOC; 2200 break; 2201 } 2202 urtwn_write_1(sc, R92C_MSR, msr); 2203 2204 sifs_time = 10; 2205 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2206 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2207 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2208 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2209 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2210 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2211 2212 /* Initialize rate adaptation. */ 2213 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2214 ISSET(sc->chip, URTWN_CHIP_92EU)) 2215 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2216 else 2217 urtwn_ra_init(vap); 2218 2219 /* Turn link LED on. */ 2220 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2221 2222 /* Reset average RSSI. */ 2223 sc->avg_pwdb = -1; 2224 2225 /* Reset temperature calibration state machine. */ 2226 sc->thcal_state = 0; 2227 sc->thcal_lctemp = 0; 2228 2229 /* Start periodic calibration. */ 2230 if (!sc->sc_dying) 2231 callout_schedule(&sc->sc_calib_to, hz); 2232 break; 2233 case IEEE80211_S_CAC: 2234 case IEEE80211_S_CSA: 2235 case IEEE80211_S_SLEEP: 2236 /* NNN what do we do in these states? XXX */ 2237 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2238 break; 2239 } 2240 /* newstate functions expect the ic to be locked. */ 2241 IEEE80211_LOCK(ic); 2242 (*sc->sc_newstate)(vap, nstate, cmd->arg); 2243 IEEE80211_UNLOCK(ic); 2244 2245 mutex_exit(&sc->sc_write_mtx); 2246 splx(s); 2247 } 2248 #endif 2249 2250 static int 2251 urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2252 { 2253 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2254 struct ieee80211com *ic = &sc->sc_ic; 2255 struct ieee80211_node *ni; 2256 enum ieee80211_state ostate = vap->iv_state; 2257 uint32_t reg; 2258 uint8_t sifs_time, msr; 2259 int s; 2260 int error; 2261 2262 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 2263 device_xname(sc->sc_dev), __func__, 2264 ieee80211_state_name[ostate], ostate, 2265 ieee80211_state_name[nstate], nstate)); 2266 2267 s = splnet(); 2268 mutex_enter(&sc->sc_write_mtx); 2269 2270 callout_stop(&sc->sc_scan_to); 2271 callout_stop(&sc->sc_calib_to); 2272 2273 switch (ostate) { 2274 case IEEE80211_S_INIT: 2275 break; 2276 2277 case IEEE80211_S_SCAN: 2278 if (nstate != IEEE80211_S_SCAN) { 2279 /* 2280 * End of scanning 2281 */ 2282 /* flush 4-AC Queue after site_survey */ 2283 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 2284 2285 /* Allow Rx from our BSSID only. */ 2286 urtwn_write_4(sc, R92C_RCR, 2287 urtwn_read_4(sc, R92C_RCR) | 2288 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2289 } 2290 break; 2291 2292 case IEEE80211_S_AUTH: 2293 case IEEE80211_S_ASSOC: 2294 break; 2295 2296 case IEEE80211_S_RUN: 2297 /* Turn link LED off. */ 2298 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2299 2300 /* Set media status to 'No Link'. */ 2301 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2302 2303 /* Stop Rx of data frames. */ 2304 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2305 2306 /* Reset TSF. */ 2307 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2308 2309 /* Disable TSF synchronization. */ 2310 urtwn_write_1(sc, R92C_BCN_CTRL, 2311 urtwn_read_1(sc, R92C_BCN_CTRL) | 2312 R92C_BCN_CTRL_DIS_TSF_UDT0); 2313 2314 /* Back to 20MHz mode */ 2315 urtwn_set_chan(sc, ic->ic_curchan, 2316 IEEE80211_HTINFO_2NDCHAN_NONE); 2317 2318 if (ic->ic_opmode == IEEE80211_M_IBSS || 2319 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2320 /* Stop BCN */ 2321 urtwn_write_1(sc, R92C_BCN_CTRL, 2322 urtwn_read_1(sc, R92C_BCN_CTRL) & 2323 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2324 } 2325 2326 /* Reset EDCA parameters. */ 2327 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2328 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2329 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2330 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2331 2332 /* flush all cam entries */ 2333 urtwn_cam_init(sc); 2334 break; 2335 case IEEE80211_S_CAC: 2336 case IEEE80211_S_CSA: 2337 case IEEE80211_S_SLEEP: 2338 printf ("URTWN UNKNOWN oSTATE: %d\n", ostate); 2339 /* NNN what do we do in these states? XXX */ 2340 break; 2341 } 2342 2343 switch (nstate) { 2344 case IEEE80211_S_INIT: 2345 /* Turn link LED off. */ 2346 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2347 break; 2348 2349 case IEEE80211_S_SCAN: 2350 if (ostate != IEEE80211_S_SCAN) { 2351 /* 2352 * Begin of scanning 2353 */ 2354 2355 /* Set gain for scanning. */ 2356 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2357 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2358 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2359 2360 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2361 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2362 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2363 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2364 } 2365 2366 /* Set media status to 'No Link'. */ 2367 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2368 2369 /* Allow Rx from any BSSID. */ 2370 urtwn_write_4(sc, R92C_RCR, 2371 urtwn_read_4(sc, R92C_RCR) & 2372 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2373 2374 /* Stop Rx of data frames. */ 2375 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2376 2377 /* Disable update TSF */ 2378 urtwn_write_1(sc, R92C_BCN_CTRL, 2379 urtwn_read_1(sc, R92C_BCN_CTRL) | 2380 R92C_BCN_CTRL_DIS_TSF_UDT0); 2381 } 2382 2383 /* Make link LED blink during scan. */ 2384 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2385 2386 /* Pause AC Tx queues. */ 2387 urtwn_write_1(sc, R92C_TXPAUSE, 2388 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2389 2390 urtwn_set_chan(sc, ic->ic_curchan, 2391 IEEE80211_HTINFO_2NDCHAN_NONE); 2392 2393 /* Start periodic scan. */ 2394 if (!sc->sc_dying) 2395 callout_schedule(&sc->sc_scan_to, hz / 5); 2396 break; 2397 2398 case IEEE80211_S_AUTH: 2399 /* Set initial gain under link. */ 2400 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2401 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2402 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2403 2404 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2405 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2406 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2407 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2408 } 2409 2410 /* Set media status to 'No Link'. */ 2411 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2412 2413 /* Allow Rx from any BSSID. */ 2414 urtwn_write_4(sc, R92C_RCR, 2415 urtwn_read_4(sc, R92C_RCR) & 2416 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2417 2418 urtwn_set_chan(sc, ic->ic_curchan, 2419 IEEE80211_HTINFO_2NDCHAN_NONE); 2420 break; 2421 2422 case IEEE80211_S_ASSOC: 2423 break; 2424 2425 case IEEE80211_S_RUN: 2426 ni = vap->iv_bss; 2427 2428 /* XXX: Set 20MHz mode */ 2429 urtwn_set_chan(sc, ic->ic_curchan, 2430 IEEE80211_HTINFO_2NDCHAN_NONE); 2431 2432 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2433 /* Back to 20MHz mode */ 2434 urtwn_set_chan(sc, ic->ic_curchan, 2435 IEEE80211_HTINFO_2NDCHAN_NONE); 2436 2437 /* Set media status to 'No Link'. */ 2438 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2439 2440 /* Enable Rx of data frames. */ 2441 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2442 2443 /* Allow Rx from any BSSID. */ 2444 urtwn_write_4(sc, R92C_RCR, 2445 urtwn_read_4(sc, R92C_RCR) & 2446 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2447 2448 /* Accept Rx data/control/management frames */ 2449 urtwn_write_4(sc, R92C_RCR, 2450 urtwn_read_4(sc, R92C_RCR) | 2451 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2452 2453 /* Turn link LED on. */ 2454 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2455 break; 2456 } 2457 2458 /* Set media status to 'Associated'. */ 2459 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2460 2461 /* Set BSSID. */ 2462 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2463 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2464 2465 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2466 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2467 } else { 2468 /* 802.11b/g */ 2469 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2470 } 2471 2472 /* Enable Rx of data frames. */ 2473 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2474 2475 /* Set beacon interval. */ 2476 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2477 2478 msr = urtwn_read_1(sc, R92C_MSR); 2479 msr &= R92C_MSR_MASK; 2480 switch (ic->ic_opmode) { 2481 case IEEE80211_M_STA: 2482 /* Allow Rx from our BSSID only. */ 2483 urtwn_write_4(sc, R92C_RCR, 2484 urtwn_read_4(sc, R92C_RCR) | 2485 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2486 2487 /* Enable TSF synchronization. */ 2488 urtwn_tsf_sync_enable(sc); 2489 2490 msr |= R92C_MSR_INFRA; 2491 break; 2492 case IEEE80211_M_HOSTAP: 2493 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2494 2495 /* Allow Rx from any BSSID. */ 2496 urtwn_write_4(sc, R92C_RCR, 2497 urtwn_read_4(sc, R92C_RCR) & 2498 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2499 2500 /* Reset TSF timer to zero. */ 2501 reg = urtwn_read_4(sc, R92C_TCR); 2502 reg &= ~0x01; 2503 urtwn_write_4(sc, R92C_TCR, reg); 2504 reg |= 0x01; 2505 urtwn_write_4(sc, R92C_TCR, reg); 2506 2507 msr |= R92C_MSR_AP; 2508 break; 2509 default: 2510 msr |= R92C_MSR_ADHOC; 2511 break; 2512 } 2513 urtwn_write_1(sc, R92C_MSR, msr); 2514 2515 sifs_time = 10; 2516 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2517 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2518 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2519 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2520 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2521 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2522 2523 /* Initialize rate adaptation. */ 2524 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2525 ISSET(sc->chip, URTWN_CHIP_92EU)) 2526 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2527 else 2528 urtwn_ra_init(vap); 2529 2530 /* Turn link LED on. */ 2531 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2532 2533 /* Reset average RSSI. */ 2534 sc->avg_pwdb = -1; 2535 2536 /* Reset temperature calibration state machine. */ 2537 sc->thcal_state = 0; 2538 sc->thcal_lctemp = 0; 2539 2540 /* Start periodic calibration. */ 2541 if (!sc->sc_dying) 2542 callout_schedule(&sc->sc_calib_to, hz); 2543 break; 2544 case IEEE80211_S_CAC: 2545 case IEEE80211_S_CSA: 2546 case IEEE80211_S_SLEEP: 2547 /* NNN what do we do in these states? XXX */ 2548 printf ("URTWN UNKNOWN nSTATE: %d\n", nstate); 2549 break; 2550 } 2551 mutex_exit(&sc->sc_write_mtx); 2552 2553 /* newstate functions expect the ic to be locked. */ 2554 error = (*sc->sc_newstate)(vap, nstate, arg); 2555 2556 splx(s); 2557 return error; 2558 } 2559 2560 static int 2561 urtwn_wme_update(struct ieee80211com *ic) 2562 { 2563 struct urtwn_softc *sc = ic->ic_softc; 2564 2565 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2566 2567 /* don't override default WME values if WME is not actually enabled */ 2568 if (!(ic->ic_flags & IEEE80211_F_WME)) 2569 return 0; 2570 2571 /* Do it in a process context. */ 2572 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2573 return 0; 2574 } 2575 2576 static void 2577 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2578 { 2579 static const uint16_t ac2reg[WME_NUM_AC] = { 2580 R92C_EDCA_BE_PARAM, 2581 R92C_EDCA_BK_PARAM, 2582 R92C_EDCA_VI_PARAM, 2583 R92C_EDCA_VO_PARAM 2584 }; 2585 struct ieee80211com *ic = &sc->sc_ic; 2586 const struct wmeParams *wmep; 2587 int ac, aifs, slottime; 2588 int s; 2589 2590 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2591 __func__)); 2592 2593 s = splnet(); 2594 mutex_enter(&sc->sc_write_mtx); 2595 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2596 for (ac = 0; ac < WME_NUM_AC; ac++) { 2597 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2598 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2599 aifs = wmep->wmep_aifsn * slottime + 10; 2600 urtwn_write_4(sc, ac2reg[ac], 2601 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2602 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2603 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2604 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2605 } 2606 mutex_exit(&sc->sc_write_mtx); 2607 splx(s); 2608 } 2609 2610 static void 2611 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2612 { 2613 int pwdb; 2614 2615 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2616 device_xname(sc->sc_dev), __func__, rate, rssi)); 2617 2618 /* Convert antenna signal to percentage. */ 2619 if (rssi <= -100 || rssi >= 20) 2620 pwdb = 0; 2621 else if (rssi >= 0) 2622 pwdb = 100; 2623 else 2624 pwdb = 100 + rssi; 2625 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2626 if (rate <= 3) { 2627 /* CCK gain is smaller than OFDM/MCS gain. */ 2628 pwdb += 6; 2629 if (pwdb > 100) 2630 pwdb = 100; 2631 if (pwdb <= 14) 2632 pwdb -= 4; 2633 else if (pwdb <= 26) 2634 pwdb -= 8; 2635 else if (pwdb <= 34) 2636 pwdb -= 6; 2637 else if (pwdb <= 42) 2638 pwdb -= 2; 2639 } 2640 } 2641 if (sc->avg_pwdb == -1) /* Init. */ 2642 sc->avg_pwdb = pwdb; 2643 else if (sc->avg_pwdb < pwdb) 2644 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2645 else 2646 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2647 2648 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2649 device_xname(sc->sc_dev), __func__, 2650 rate, rssi, pwdb, sc->avg_pwdb)); 2651 } 2652 2653 static int8_t 2654 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2655 { 2656 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2657 struct r92c_rx_phystat *phy; 2658 struct r92c_rx_cck *cck; 2659 uint8_t rpt; 2660 int8_t rssi; 2661 2662 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2663 __func__, rate)); 2664 2665 if (rate <= 3) { 2666 cck = (struct r92c_rx_cck *)physt; 2667 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2668 rpt = (cck->agc_rpt >> 5) & 0x3; 2669 rssi = (cck->agc_rpt & 0x1f) << 1; 2670 } else { 2671 rpt = (cck->agc_rpt >> 6) & 0x3; 2672 rssi = cck->agc_rpt & 0x3e; 2673 } 2674 rssi = cckoff[rpt] - rssi; 2675 } else { /* OFDM/HT. */ 2676 phy = (struct r92c_rx_phystat *)physt; 2677 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2678 } 2679 return rssi; 2680 } 2681 2682 static int8_t 2683 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2684 { 2685 struct r92c_rx_phystat *phy; 2686 struct r88e_rx_cck *cck; 2687 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2688 int8_t rssi; 2689 2690 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2691 __func__, rate)); 2692 2693 rssi = 0; 2694 if (rate <= 3) { 2695 cck = (struct r88e_rx_cck *)physt; 2696 cck_agc_rpt = cck->agc_rpt; 2697 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2698 vga_idx = cck_agc_rpt & 0x1f; 2699 switch (lna_idx) { 2700 case 7: 2701 if (vga_idx <= 27) 2702 rssi = -100 + 2* (27 - vga_idx); 2703 else 2704 rssi = -100; 2705 break; 2706 case 6: 2707 rssi = -48 + 2 * (2 - vga_idx); 2708 break; 2709 case 5: 2710 rssi = -42 + 2 * (7 - vga_idx); 2711 break; 2712 case 4: 2713 rssi = -36 + 2 * (7 - vga_idx); 2714 break; 2715 case 3: 2716 rssi = -24 + 2 * (7 - vga_idx); 2717 break; 2718 case 2: 2719 rssi = -12 + 2 * (5 - vga_idx); 2720 break; 2721 case 1: 2722 rssi = 8 - (2 * vga_idx); 2723 break; 2724 case 0: 2725 rssi = 14 - (2 * vga_idx); 2726 break; 2727 } 2728 rssi += 6; 2729 } else { /* OFDM/HT. */ 2730 phy = (struct r92c_rx_phystat *)physt; 2731 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2732 } 2733 return rssi; 2734 } 2735 2736 static void 2737 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2738 { 2739 struct ieee80211com *ic = &sc->sc_ic; 2740 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2741 struct ifnet *ifp = vap->iv_ifp; 2742 struct ieee80211_frame *wh; 2743 struct ieee80211_node *ni; 2744 struct r92c_rx_desc_usb *stat; 2745 uint32_t rxdw0, rxdw3; 2746 struct mbuf *m; 2747 uint8_t rate; 2748 int8_t rssi = 0; 2749 int s, infosz; 2750 2751 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2752 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2753 2754 stat = (struct r92c_rx_desc_usb *)buf; 2755 rxdw0 = le32toh(stat->rxdw0); 2756 rxdw3 = le32toh(stat->rxdw3); 2757 2758 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2759 /* 2760 * This should not happen since we setup our Rx filter 2761 * to not receive these frames. 2762 */ 2763 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2764 device_xname(sc->sc_dev), __func__)); 2765 ifp->if_ierrors++; 2766 return; 2767 } 2768 2769 /* 2770 * XXX: This will drop most control packets. Do we really 2771 * want this in IEEE80211_M_MONITOR mode? 2772 */ 2773 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2774 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2775 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2776 device_xname(sc->sc_dev), __func__, pktlen)); 2777 vap->iv_stats.is_rx_tooshort++; 2778 ifp->if_ierrors++; 2779 return; 2780 } 2781 if (__predict_false(pktlen > MCLBYTES)) { 2782 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2783 device_xname(sc->sc_dev), __func__, pktlen)); 2784 ifp->if_ierrors++; 2785 return; 2786 } 2787 2788 rate = MS(rxdw3, R92C_RXDW3_RATE); 2789 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2790 2791 /* Get RSSI from PHY status descriptor if present. */ 2792 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2793 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2794 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2795 else 2796 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2797 /* Update our average RSSI. */ 2798 urtwn_update_avgrssi(sc, rate, rssi); 2799 } 2800 2801 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2802 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2803 2804 MGETHDR(m, M_DONTWAIT, MT_DATA); 2805 if (__predict_false(m == NULL)) { 2806 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2807 vap->iv_stats.is_rx_nobuf++; 2808 ifp->if_ierrors++; 2809 return; 2810 } 2811 if (pktlen > (int)MHLEN) { 2812 MCLGET(m, M_DONTWAIT); 2813 if (__predict_false(!(m->m_flags & M_EXT))) { 2814 aprint_error_dev(sc->sc_dev, 2815 "couldn't allocate rx mbuf cluster\n"); 2816 m_freem(m); 2817 vap->iv_stats.is_rx_nobuf++; 2818 ifp->if_ierrors++; 2819 return; 2820 } 2821 } 2822 2823 /* Finalize mbuf. */ 2824 m_set_rcvif(m, ifp); 2825 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2826 2827 memcpy(mtod(m, uint8_t *), wh, pktlen); 2828 m->m_pkthdr.len = m->m_len = pktlen; 2829 2830 s = splnet(); 2831 if (__predict_false(sc->sc_drvbpf != NULL)) { 2832 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2833 2834 tap->wr_flags = 0; 2835 if (!(rxdw3 & R92C_RXDW3_HT)) { 2836 switch (rate) { 2837 /* CCK. */ 2838 case 0: tap->wr_rate = 2; break; 2839 case 1: tap->wr_rate = 4; break; 2840 case 2: tap->wr_rate = 11; break; 2841 case 3: tap->wr_rate = 22; break; 2842 /* OFDM. */ 2843 case 4: tap->wr_rate = 12; break; 2844 case 5: tap->wr_rate = 18; break; 2845 case 6: tap->wr_rate = 24; break; 2846 case 7: tap->wr_rate = 36; break; 2847 case 8: tap->wr_rate = 48; break; 2848 case 9: tap->wr_rate = 72; break; 2849 case 10: tap->wr_rate = 96; break; 2850 case 11: tap->wr_rate = 108; break; 2851 } 2852 } else if (rate >= 12) { /* MCS0~15. */ 2853 /* Bit 7 set means HT MCS instead of rate. */ 2854 tap->wr_rate = 0x80 | (rate - 12); 2855 } 2856 tap->wr_dbm_antsignal = rssi; 2857 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2858 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2859 2860 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2861 } 2862 2863 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2864 2865 if (ni != NULL) { 2866 if (ni->ni_vap != NULL) { 2867 2868 } else { 2869 splx(s); 2870 return; 2871 } 2872 /* push the frame up to the 802.11 stack */ 2873 /* NNN Convert rssi to -10 to 110 ? for 802.11 layer */ 2874 ieee80211_input(ni, m, rssi+90, 0); 2875 2876 /* Node is no longer needed. */ 2877 ieee80211_free_node(ni); 2878 2879 } else { 2880 2881 /* No node found ... process differently. */ 2882 (void) ieee80211_input_all(ic, m, rssi+90, 0); 2883 } 2884 2885 splx(s); 2886 } 2887 2888 static void 2889 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2890 { 2891 struct urtwn_rx_data *data = priv; 2892 struct urtwn_softc *sc = data->sc; 2893 struct r92c_rx_desc_usb *stat; 2894 size_t pidx = data->pidx; 2895 uint32_t rxdw0; 2896 uint8_t *buf; 2897 int len, totlen, pktlen, infosz, npkts; 2898 2899 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2900 device_xname(sc->sc_dev), __func__, status)); 2901 2902 mutex_enter(&sc->sc_rx_mtx); 2903 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2904 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2905 /* Put this Rx buffer back to our free list. */ 2906 mutex_exit(&sc->sc_rx_mtx); 2907 2908 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2909 if (status == USBD_STALLED) 2910 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2911 else if (status != USBD_CANCELLED) 2912 goto resubmit; 2913 return; 2914 } 2915 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2916 2917 if (__predict_false(len < (int)sizeof(*stat))) { 2918 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2919 device_xname(sc->sc_dev), __func__, len)); 2920 goto resubmit; 2921 } 2922 buf = data->buf; 2923 2924 /* Get the number of encapsulated frames. */ 2925 stat = (struct r92c_rx_desc_usb *)buf; 2926 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2927 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2928 device_xname(sc->sc_dev), __func__, npkts)); 2929 2930 /* Process all of them. */ 2931 while (npkts-- > 0) { 2932 if (__predict_false(len < (int)sizeof(*stat))) { 2933 DPRINTFN(DBG_RX, 2934 ("%s: %s: len(%d) is short than header\n", 2935 device_xname(sc->sc_dev), __func__, len)); 2936 break; 2937 } 2938 stat = (struct r92c_rx_desc_usb *)buf; 2939 rxdw0 = le32toh(stat->rxdw0); 2940 2941 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2942 if (__predict_false(pktlen == 0)) { 2943 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2944 device_xname(sc->sc_dev), __func__)); 2945 break; 2946 } 2947 2948 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2949 2950 /* Make sure everything fits in xfer. */ 2951 totlen = sizeof(*stat) + infosz + pktlen; 2952 if (__predict_false(totlen > len)) { 2953 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2954 device_xname(sc->sc_dev), __func__, totlen, 2955 (int)sizeof(*stat), infosz, pktlen, len)); 2956 break; 2957 } 2958 2959 /* Process 802.11 frame. */ 2960 urtwn_rx_frame(sc, buf, pktlen); 2961 2962 /* Next chunk is 128-byte aligned. */ 2963 totlen = roundup2(totlen, 128); 2964 buf += totlen; 2965 len -= totlen; 2966 } 2967 2968 resubmit: 2969 /* Setup a new transfer. */ 2970 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2971 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2972 (void)usbd_transfer(xfer); 2973 } 2974 2975 static void 2976 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2977 { 2978 struct urtwn_tx_data *data = priv; 2979 struct urtwn_softc *sc = data->sc; 2980 struct ifnet *ifp = TAILQ_FIRST(&sc->sc_ic.ic_vaps)->iv_ifp; 2981 size_t pidx = data->pidx; 2982 int s; 2983 2984 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2985 device_xname(sc->sc_dev), __func__, status)); 2986 2987 mutex_enter(&sc->sc_tx_mtx); 2988 /* Put this Tx buffer back to our free list. */ 2989 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2990 mutex_exit(&sc->sc_tx_mtx); 2991 2992 s = splnet(); 2993 sc->tx_timer = 0; 2994 ifp->if_flags &= ~IFF_OACTIVE; 2995 2996 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2997 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2998 if (status == USBD_STALLED) { 2999 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 3000 usbd_clear_endpoint_stall_async(pipe); 3001 } 3002 printf("ERROR1\n"); 3003 ifp->if_oerrors++; 3004 } 3005 splx(s); 3006 return; 3007 } 3008 3009 ifp->if_opackets++; 3010 urtwn_start(ifp); 3011 splx(s); 3012 3013 } 3014 3015 static int 3016 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 3017 struct urtwn_tx_data *data) 3018 { 3019 struct ieee80211com *ic = &sc->sc_ic; 3020 struct ieee80211_frame *wh; 3021 struct ieee80211_key *k = NULL; 3022 struct r92c_tx_desc_usb *txd; 3023 size_t i, padsize, xferlen, txd_len; 3024 uint16_t seq, sum; 3025 uint8_t raid, type, tid; 3026 int s, hasqos, error; 3027 3028 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3029 3030 wh = mtod(m, struct ieee80211_frame *); 3031 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3032 txd_len = sizeof(*txd); 3033 3034 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 3035 txd_len = 32; 3036 3037 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3038 k = ieee80211_crypto_encap(ni, m); 3039 if (k == NULL) 3040 return ENOBUFS; 3041 3042 /* packet header may have moved, reset our local pointer */ 3043 wh = mtod(m, struct ieee80211_frame *); 3044 } 3045 3046 if (__predict_false(sc->sc_drvbpf != NULL)) { 3047 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3048 3049 tap->wt_flags = 0; 3050 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 3051 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 3052 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3053 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3054 3055 /* XXX: set tap->wt_rate? */ 3056 3057 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 3058 } 3059 3060 /* non-qos data frames */ 3061 tid = R92C_TXDW1_QSEL_BE; 3062 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 3063 /* data frames in 11n mode */ 3064 struct ieee80211_qosframe *qwh = (void *)wh; 3065 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3066 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3067 tid = R92C_TXDW1_QSEL_MGNT; 3068 } 3069 3070 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 3071 padsize = 8; 3072 else 3073 padsize = 0; 3074 3075 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3076 padsize = 0; 3077 3078 /* Fill Tx descriptor. */ 3079 txd = (struct r92c_tx_desc_usb *)data->buf; 3080 memset(txd, 0, txd_len + padsize); 3081 3082 txd->txdw0 |= htole32( 3083 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 3084 SM(R92C_TXDW0_OFFSET, txd_len)); 3085 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3086 txd->txdw0 |= htole32( 3087 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3088 } 3089 3090 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3091 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3092 3093 /* fix pad field */ 3094 if (padsize > 0) { 3095 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 3096 device_xname(sc->sc_dev), __func__, padsize)); 3097 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 3098 } 3099 3100 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3101 type == IEEE80211_FC0_TYPE_DATA) { 3102 if (ic->ic_curmode == IEEE80211_MODE_11B) 3103 raid = R92C_RAID_11B; 3104 else 3105 raid = R92C_RAID_11BG; 3106 DPRINTFN(DBG_TX, 3107 ("%s: %s: data packet: tid=%d, raid=%d\n", 3108 device_xname(sc->sc_dev), __func__, tid, raid)); 3109 3110 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 3111 txd->txdw1 |= htole32( 3112 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 3113 SM(R92C_TXDW1_QSEL, tid) | 3114 SM(R92C_TXDW1_RAID, raid) | 3115 R92C_TXDW1_AGGBK); 3116 } else 3117 txd->txdw1 |= htole32( 3118 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3119 SM(R92C_TXDW1_QSEL, tid) | 3120 SM(R92C_TXDW1_RAID, raid) | 3121 R92C_TXDW1_AGGBK); 3122 3123 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3124 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 3125 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3126 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 3127 3128 if (hasqos) { 3129 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 3130 } 3131 3132 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3133 /* for 11g */ 3134 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 3135 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 3136 R92C_TXDW4_HWRTSEN); 3137 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 3138 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 3139 R92C_TXDW4_HWRTSEN); 3140 } 3141 } 3142 /* Send RTS at OFDM24. */ 3143 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 3144 txd->txdw5 |= htole32(0x0001ff00); 3145 /* Send data at OFDM54. */ 3146 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3147 txd->txdw5 |= htole32(0x13 & 0x3f); 3148 else 3149 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 3150 } else if (type == IEEE80211_FC0_TYPE_MGT) { 3151 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 3152 device_xname(sc->sc_dev), __func__)); 3153 txd->txdw1 |= htole32( 3154 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 3155 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 3156 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3157 3158 /* Force CCK1. */ 3159 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3160 /* Use 1Mbps */ 3161 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3162 } else { 3163 /* broadcast or multicast packets */ 3164 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 3165 device_xname(sc->sc_dev), __func__)); 3166 txd->txdw1 |= htole32( 3167 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 3168 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 3169 3170 /* Force CCK1. */ 3171 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3172 /* Use 1Mbps */ 3173 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 3174 } 3175 /* Set sequence number */ 3176 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 3177 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 3178 txd->txdseq |= htole16(seq); 3179 3180 if (!hasqos) { 3181 /* Use HW sequence numbering for non-QoS frames. */ 3182 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3183 txd->txdseq |= htole16(R92C_HWSEQ_EN); 3184 } 3185 } else { 3186 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 3187 R92E_HWSEQ_SHIFT); 3188 if (!hasqos) { 3189 /* Use HW sequence numbering for non-QoS frames. */ 3190 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 3191 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 3192 } 3193 } 3194 3195 /* Compute Tx descriptor checksum. */ 3196 sum = 0; 3197 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 3198 sum ^= ((uint16_t *)txd)[i]; 3199 txd->txdsum = sum; /* NB: already little endian. */ 3200 3201 xferlen = txd_len + m->m_pkthdr.len + padsize; 3202 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 3203 3204 if (data->xfer == NULL) { 3205 /* NNN Don't crash ... but what is going on! */ 3206 printf ("urtwn_tx: data->xfer is NULL\n"); 3207 m_print(m,"", printf); 3208 return -1; 3209 } 3210 3211 s = splnet(); 3212 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 3213 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 3214 urtwn_txeof); 3215 error = usbd_transfer(data->xfer); 3216 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3217 error != USBD_IN_PROGRESS)) { 3218 splx(s); 3219 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 3220 device_xname(sc->sc_dev), __func__, error)); 3221 return error; 3222 } 3223 splx(s); 3224 return 0; 3225 } 3226 3227 struct urtwn_tx_data * 3228 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 3229 { 3230 struct urtwn_tx_data *data = NULL; 3231 3232 mutex_enter(&sc->sc_tx_mtx); 3233 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 3234 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 3235 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 3236 } 3237 mutex_exit(&sc->sc_tx_mtx); 3238 3239 return data; 3240 } 3241 3242 static void 3243 urtwn_start(struct ifnet *ifp) 3244 { 3245 struct ieee80211vap *vap = ifp->if_softc; 3246 struct ieee80211com *ic = vap->iv_ic; 3247 struct urtwn_softc *sc = ic->ic_softc; 3248 struct urtwn_tx_data *data; 3249 struct ether_header *eh; 3250 struct ieee80211_node *ni; 3251 struct mbuf *m; 3252 3253 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3254 3255 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3256 return; 3257 3258 data = NULL; 3259 for (;;) { 3260 /* Send pending management frames first. */ 3261 IF_POLL(&ic->ic_mgtq, m); 3262 if (m != NULL) { 3263 /* Use AC_VO for management frames. */ 3264 3265 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3266 3267 if (data == NULL) { 3268 ifp->if_flags |= IFF_OACTIVE; 3269 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3270 device_xname(sc->sc_dev))); 3271 return; 3272 } 3273 IF_DEQUEUE(&ic->ic_mgtq, m); 3274 ni = M_GETCTX(m, struct ieee80211_node *); 3275 M_CLEARCTX(m); 3276 goto sendit; 3277 } 3278 3279 if (vap->iv_state != IEEE80211_S_RUN) 3280 break; 3281 3282 /* Encapsulate and send data frames. */ 3283 IFQ_POLL(&sc->sc_sendq, m); 3284 if (m == NULL) 3285 break; 3286 3287 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 3288 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3289 uint8_t qid = WME_AC_BE; 3290 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3291 /* data frames in 11n mode */ 3292 struct ieee80211_qosframe *qwh = (void *)wh; 3293 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 3294 qid = TID_TO_WME_AC(tid); 3295 } else if (type != IEEE80211_FC0_TYPE_DATA) { 3296 qid = WME_AC_VO; 3297 } 3298 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 3299 3300 if (data == NULL) { 3301 ifp->if_flags |= IFF_OACTIVE; 3302 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3303 device_xname(sc->sc_dev))); 3304 return; 3305 } 3306 IFQ_DEQUEUE(&sc->sc_sendq, m); 3307 3308 if (m->m_len < (int)sizeof(*eh) && 3309 (m = m_pullup(m, sizeof(*eh))) == NULL) { 3310 printf("ERROR6\n"); 3311 ifp->if_oerrors++; 3312 continue; 3313 } 3314 eh = mtod(m, struct ether_header *); 3315 ni = ieee80211_find_txnode(vap, eh->ether_dhost); 3316 if (ni == NULL) { 3317 m_freem(m); 3318 printf("ERROR5\n"); 3319 ifp->if_oerrors++; 3320 continue; 3321 } 3322 3323 //bpf_mtap(ifp, m, BPF_D_OUT); 3324 3325 sendit: 3326 if (urtwn_tx(sc, m, ni, data) != 0) { 3327 m_freem(m); 3328 ieee80211_free_node(ni); 3329 printf("ERROR3\n"); 3330 ifp->if_oerrors++; 3331 continue; 3332 } 3333 m_freem(m); 3334 ieee80211_free_node(ni); 3335 sc->tx_timer = 5; 3336 ifp->if_timer = 1; 3337 } 3338 } 3339 3340 static __unused void 3341 urtwn_watchdog(struct ifnet *ifp) 3342 { 3343 struct ieee80211vap *vap = ifp->if_softc; 3344 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 3345 3346 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3347 3348 ifp->if_timer = 0; 3349 3350 if (sc->tx_timer > 0) { 3351 if (--sc->tx_timer == 0) { 3352 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3353 /* urtwn_init(ifp); XXX needs a process context! */ 3354 printf("ERROR2\n"); 3355 ifp->if_oerrors++; 3356 return; 3357 } 3358 ifp->if_timer = 1; 3359 } 3360 // ieee80211_watchdog(&sc->sc_ic); 3361 } 3362 3363 /* 3364 * Create a VAP node for use with the urtwn driver. 3365 */ 3366 3367 static struct ieee80211vap * 3368 urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], 3369 int unit, enum ieee80211_opmode opmode, int flags, 3370 const uint8_t bssid[IEEE80211_ADDR_LEN], 3371 const uint8_t macaddr[IEEE80211_ADDR_LEN]) 3372 { 3373 struct urtwn_softc *sc = ic->ic_softc; 3374 struct ifnet *ifp; 3375 struct ieee80211vap *vap; 3376 3377 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3378 3379 /* Allow only one VAP for the urtwn driver. */ 3380 if (!TAILQ_EMPTY(&ic->ic_vaps)) 3381 return NULL; 3382 3383 /* Allocate the vap and setup. */ 3384 vap = kmem_zalloc(sizeof(struct ieee80211vap), KM_SLEEP); 3385 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 3386 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 3387 kmem_free(vap, sizeof(struct ieee80211vap)); 3388 return NULL; 3389 } 3390 3391 /* Local setup */ 3392 vap->iv_reset = urtwn_reset; 3393 3394 ifp = vap->iv_ifp; 3395 if_initialize(ifp); 3396 ifp->if_init = urtwn_init; 3397 ifp->if_ioctl = urtwn_ioctl; 3398 ifp->if_start = urtwn_start; 3399 // ifp->if_watchdog = urtwn_watchdog; NNN 3400 ifp->if_extflags |= IFEF_MPSAFE; 3401 // IFQ_SET_READY(&ifp->if_snd); 3402 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 3403 3404 ifp->if_percpuq = if_percpuq_create(ifp); 3405 3406 /* Override state transition machine. */ 3407 /* NNN --- many possible newstate machines ... issue! */ 3408 sc->sc_newstate = vap->iv_newstate; 3409 vap->iv_newstate = urtwn_newstate; 3410 3411 /* Finish setup */ 3412 ieee80211_vap_attach(vap, urtwn_media_change, 3413 ieee80211_media_status, macaddr); 3414 ic->ic_opmode = opmode; 3415 3416 /* Attach the packet filter */ 3417 bpf_attach2(vap->iv_ifp, DLT_IEEE802_11_RADIO, 3418 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 3419 &sc->sc_drvbpf); 3420 3421 return vap; 3422 } 3423 3424 static void 3425 urtwn_vap_delete(struct ieee80211vap *vap) 3426 { 3427 struct ifnet *ifp = vap->iv_ifp; 3428 struct urtwn_softc *sc __unused =vap->iv_ic->ic_softc; 3429 3430 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3431 3432 urtwn_stop(ifp, 0); 3433 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3434 bpf_detach(ifp); 3435 if_detach(ifp); 3436 kmem_free(vap, sizeof(struct ieee80211vap)); 3437 } 3438 3439 static void 3440 urtwn_parent(struct ieee80211com *ic) 3441 { 3442 struct urtwn_softc *sc __unused = ic->ic_softc; 3443 3444 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3445 3446 /* Not sure what to do here yet. */ 3447 } 3448 3449 static void 3450 urtwn_scan_start(struct ieee80211com *ic) 3451 { 3452 struct urtwn_softc *sc = ic->ic_softc; 3453 //uint32_t reg; 3454 //int s; 3455 3456 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3457 3458 /* 3459 * Not sure what to do here yet. Try #1: do what was in the 3460 * state machine. NNN 3461 */ 3462 #if NOTWITHSTATEMACHINEOVERRIDE 3463 /* 3464 * Begin of scanning 3465 */ 3466 3467 s = splnet(); 3468 mutex_enter(&sc->sc_write_mtx); 3469 3470 /* Set gain for scanning. */ 3471 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3472 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3473 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3474 3475 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 3476 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3477 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 3478 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3479 } 3480 3481 /* Set media status to 'No Link'. */ 3482 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 3483 3484 /* Allow Rx from any BSSID. */ 3485 urtwn_write_4(sc, R92C_RCR, 3486 urtwn_read_4(sc, R92C_RCR) & 3487 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 3488 3489 /* Stop Rx of data frames. */ 3490 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 3491 3492 /* Disable update TSF */ 3493 urtwn_write_1(sc, R92C_BCN_CTRL, 3494 urtwn_read_1(sc, R92C_BCN_CTRL) | 3495 R92C_BCN_CTRL_DIS_TSF_UDT0); 3496 3497 /* Make link LED blink during scan. */ 3498 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3499 3500 /* Pause AC Tx queues. */ 3501 urtwn_write_1(sc, R92C_TXPAUSE, 3502 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 3503 3504 urtwn_set_chan(sc, ic->ic_curchan, 3505 IEEE80211_HTINFO_2NDCHAN_NONE); 3506 3507 mutex_exit(&sc->sc_write_mtx); 3508 splx(s); 3509 #endif 3510 } 3511 3512 static void 3513 urtwn_scan_end(struct ieee80211com *ic) 3514 { 3515 struct urtwn_softc *sc = ic->ic_softc; 3516 3517 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3518 3519 #ifdef NOTWITHSTATEMACHINEOVERRIDE 3520 /* 3521 * End of scanning 3522 */ 3523 3524 mutex_enter(&sc->sc_write_mtx); 3525 3526 /* flush 4-AC Queue after site_survey */ 3527 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 3528 3529 /* Allow Rx from our BSSID only. */ 3530 urtwn_write_4(sc, R92C_RCR, 3531 urtwn_read_4(sc, R92C_RCR) | 3532 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 3533 3534 /* Turn link LED off. */ 3535 urtwn_set_led(sc, URTWN_LED_LINK, 0); 3536 3537 mutex_exit(&sc->sc_write_mtx); 3538 #endif 3539 } 3540 3541 static void 3542 urtwn_set_channel(struct ieee80211com *ic) 3543 { 3544 struct urtwn_softc *sc = ic->ic_softc; 3545 3546 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3547 3548 mutex_enter(&sc->sc_write_mtx); 3549 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 3550 mutex_exit(&sc->sc_write_mtx); 3551 } 3552 3553 static int 3554 urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3555 { 3556 struct urtwn_softc *sc = ic->ic_softc; 3557 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3558 int s; 3559 size_t pktlen = m->m_pkthdr.len; 3560 bool mcast = (m->m_flags & M_MCAST) != 0; 3561 3562 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3563 3564 s = splnet(); 3565 3566 IF_ENQUEUE(&sc->sc_sendq, m); 3567 3568 vap->iv_ifp->if_obytes += pktlen; 3569 if (mcast) 3570 vap->iv_ifp->if_omcasts++; 3571 3572 if ((vap->iv_ifp->if_flags & IFF_OACTIVE) == 0) 3573 if_start_lock(vap->iv_ifp); 3574 splx(s); 3575 3576 urtwn_start(vap->iv_ifp); 3577 3578 return 0; 3579 } 3580 3581 #if 0 3582 static int 3583 urtwn_send_mgmt(struct ieee80211_node *ni, int arg1, int arg2) { 3584 #ifdef URTWN_DEBUG 3585 // struct ieee80211vap *vap = ni->ni_vap; 3586 struct ieee80211com *ic = ni->ni_ic; 3587 struct urtwn_softc *sc = ic->ic_softc; 3588 #endif 3589 3590 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3591 3592 /* Don't know what to do right now. */ 3593 return ENOTTY; 3594 } 3595 #endif 3596 3597 3598 static int 3599 urtwn_raw_xmit(struct ieee80211_node *ni , struct mbuf *m, 3600 const struct ieee80211_bpf_params *bpfp) 3601 { 3602 struct ieee80211vap *vap = ni->ni_vap; 3603 struct ieee80211com *ic = ni->ni_ic; 3604 struct urtwn_softc *sc = ic->ic_softc; 3605 struct urtwn_tx_data *data; 3606 int error; 3607 3608 DPRINTFN(DBG_FN, ("%s: %s\n",device_xname(sc->sc_dev), __func__)); 3609 3610 KASSERT(vap != NULL); /* NNN need these? */ 3611 KASSERT(ic != NULL); 3612 KASSERT(sc != NULL); 3613 KASSERT(m != NULL); 3614 3615 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 3616 3617 if (data == NULL) { 3618 vap->iv_ifp->if_flags |= IFF_OACTIVE; 3619 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 3620 device_xname(sc->sc_dev))); 3621 return ENOBUFS; 3622 } 3623 3624 bpf_mtap3(vap->iv_rawbpf, m, BPF_D_OUT); 3625 3626 error = urtwn_tx(sc, m, ni, data); 3627 if (error != 0) { 3628 printf("ERROR3\n"); 3629 vap->iv_ifp->if_oerrors++; 3630 } else { 3631 sc->tx_timer = 5; 3632 vap->iv_ifp->if_timer = 1; 3633 } 3634 m_freem(m); 3635 ieee80211_free_node(ni); 3636 return error; 3637 } 3638 3639 static void 3640 urtwn_getradiocaps(struct ieee80211com *ic, 3641 int maxchans, int *nchans, struct ieee80211_channel chans[]) 3642 { 3643 uint8_t bands[IEEE80211_MODE_BYTES]; 3644 3645 /* 3646 * NNN Should be able to do something based on chip if 3647 * a chip has more bands .... eg. N ... but for the future. 3648 */ 3649 3650 memset(bands, 0, sizeof(bands)); 3651 setbit(bands, IEEE80211_MODE_11B); 3652 setbit(bands, IEEE80211_MODE_11G); 3653 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 3654 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 3655 } 3656 3657 3658 static int 3659 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3660 { 3661 3662 struct ieee80211vap *vap = ifp->if_softc; 3663 struct ieee80211com *ic = vap->iv_ic; 3664 struct urtwn_softc *sc __unused = vap->iv_ic->ic_softc; 3665 int s, error = 0; 3666 3667 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3668 device_xname(sc->sc_dev), __func__, cmd, data)); 3669 3670 s = splnet(); 3671 3672 switch (cmd) { 3673 case SIOCSIFFLAGS: 3674 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3675 break; 3676 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3677 case IFF_UP | IFF_RUNNING: 3678 break; 3679 case IFF_UP: 3680 urtwn_init(ifp); 3681 break; 3682 case IFF_RUNNING: 3683 urtwn_stop(ifp, 1); 3684 break; 3685 case 0: 3686 break; 3687 } 3688 break; 3689 3690 case SIOCADDMULTI: 3691 case SIOCDELMULTI: 3692 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3693 /* setup multicast filter, etc */ 3694 error = 0; 3695 } 3696 break; 3697 3698 case SIOCS80211CHANNEL: 3699 /* 3700 * This allows for fast channel switching in monitor mode 3701 * (used by kismet). In IBSS mode, we must explicitly reset 3702 * the interface to generate a new beacon frame. 3703 */ 3704 error = ieee80211_ioctl(ifp, cmd, data); 3705 if (error == ENETRESET && 3706 ic->ic_opmode == IEEE80211_M_MONITOR) { 3707 urtwn_set_chan(sc, ic->ic_curchan, 3708 IEEE80211_HTINFO_2NDCHAN_NONE); 3709 error = 0; 3710 } 3711 break; 3712 3713 default: 3714 error = ieee80211_ioctl(ifp, cmd, data); 3715 break; 3716 } 3717 if (error == ENETRESET) { 3718 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3719 (IFF_UP | IFF_RUNNING) /* && NNN need a vap for next line 3720 ic->ic_roaming != IEEE80211_ROAMING_MANUAL*/) { 3721 urtwn_init(ifp); 3722 } 3723 error = 0; 3724 } 3725 3726 splx(s); 3727 3728 return error; 3729 } 3730 3731 static __inline int 3732 urtwn_power_on(struct urtwn_softc *sc) 3733 { 3734 3735 return sc->sc_power_on(sc); 3736 } 3737 3738 static int 3739 urtwn_r92c_power_on(struct urtwn_softc *sc) 3740 { 3741 uint32_t reg; 3742 int ntries; 3743 3744 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3745 3746 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3747 3748 /* Wait for autoload done bit. */ 3749 for (ntries = 0; ntries < 1000; ntries++) { 3750 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3751 break; 3752 DELAY(5); 3753 } 3754 if (ntries == 1000) { 3755 aprint_error_dev(sc->sc_dev, 3756 "timeout waiting for chip autoload\n"); 3757 return ETIMEDOUT; 3758 } 3759 3760 /* Unlock ISO/CLK/Power control register. */ 3761 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3762 /* Move SPS into PWM mode. */ 3763 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3764 DELAY(5); 3765 3766 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3767 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3768 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3769 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3770 DELAY(100); 3771 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3772 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3773 ~R92C_SYS_ISO_CTRL_MD2PP); 3774 } 3775 3776 /* Auto enable WLAN. */ 3777 urtwn_write_2(sc, R92C_APS_FSMCO, 3778 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3779 for (ntries = 0; ntries < 1000; ntries++) { 3780 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3781 R92C_APS_FSMCO_APFM_ONMAC)) 3782 break; 3783 DELAY(100); 3784 } 3785 if (ntries == 1000) { 3786 aprint_error_dev(sc->sc_dev, 3787 "timeout waiting for MAC auto ON\n"); 3788 return ETIMEDOUT; 3789 } 3790 3791 /* Enable radio, GPIO and LED functions. */ 3792 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3793 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3794 urtwn_write_2(sc, R92C_APS_FSMCO, 3795 R92C_APS_FSMCO_AFSM_HSUS | 3796 R92C_APS_FSMCO_PDN_EN | 3797 R92C_APS_FSMCO_PFM_ALDN); 3798 3799 /* Release RF digital isolation. */ 3800 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3801 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3802 3803 /* Initialize MAC. */ 3804 urtwn_write_1(sc, R92C_APSD_CTRL, 3805 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3806 for (ntries = 0; ntries < 200; ntries++) { 3807 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3808 R92C_APSD_CTRL_OFF_STATUS)) 3809 break; 3810 DELAY(5); 3811 } 3812 if (ntries == 200) { 3813 aprint_error_dev(sc->sc_dev, 3814 "timeout waiting for MAC initialization\n"); 3815 return ETIMEDOUT; 3816 } 3817 3818 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3819 reg = urtwn_read_2(sc, R92C_CR); 3820 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3821 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3822 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3823 R92C_CR_ENSEC; 3824 urtwn_write_2(sc, R92C_CR, reg); 3825 3826 urtwn_write_1(sc, 0xfe10, 0x19); 3827 return 0; 3828 } 3829 3830 static int 3831 urtwn_r92e_power_on(struct urtwn_softc *sc) 3832 { 3833 uint32_t reg; 3834 uint32_t val; 3835 int ntries; 3836 3837 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3838 3839 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3840 3841 /* Enable radio, GPIO and LED functions. */ 3842 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3843 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3844 urtwn_write_2(sc, R92C_APS_FSMCO, 3845 R92C_APS_FSMCO_AFSM_HSUS | 3846 R92C_APS_FSMCO_PDN_EN | 3847 R92C_APS_FSMCO_PFM_ALDN); 3848 3849 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3850 /* LDO. */ 3851 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3852 } 3853 else { 3854 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3855 R92C_SYS_SWR_CTRL2) & 0xffff); 3856 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3857 } 3858 3859 for (ntries = 0; ntries < 2; ntries++) { 3860 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3861 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3862 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3863 R92C_AFE_CTRL4)); 3864 } 3865 3866 /* Reset BB. */ 3867 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3868 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3869 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3870 3871 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3872 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3873 3874 /* Disable HWPDN. */ 3875 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3876 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3877 3878 /* Disable WL suspend. */ 3879 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3880 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3881 R92C_APS_FSMCO_AFSM_HSUS)); 3882 3883 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3884 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3885 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3886 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3887 for (ntries = 0; ntries < 10000; ntries++) { 3888 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3889 R92C_APS_FSMCO_APFM_ONMAC; 3890 if (val == 0x0) 3891 break; 3892 DELAY(10); 3893 } 3894 if (ntries == 10000) { 3895 aprint_error_dev(sc->sc_dev, 3896 "timeout waiting for chip power up\n"); 3897 return ETIMEDOUT; 3898 } 3899 3900 urtwn_write_2(sc, R92C_CR, 0x00); 3901 reg = urtwn_read_2(sc, R92C_CR); 3902 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3903 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3904 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3905 urtwn_write_2(sc, R92C_CR, reg); 3906 3907 return 0; 3908 } 3909 3910 static int 3911 urtwn_r88e_power_on(struct urtwn_softc *sc) 3912 { 3913 uint32_t reg; 3914 uint8_t val; 3915 int ntries; 3916 3917 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3918 3919 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3920 3921 /* Wait for power ready bit. */ 3922 for (ntries = 0; ntries < 5000; ntries++) { 3923 val = urtwn_read_1(sc, 0x6) & 0x2; 3924 if (val == 0x2) 3925 break; 3926 DELAY(10); 3927 } 3928 if (ntries == 5000) { 3929 aprint_error_dev(sc->sc_dev, 3930 "timeout waiting for chip power up\n"); 3931 return ETIMEDOUT; 3932 } 3933 3934 /* Reset BB. */ 3935 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3936 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3937 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3938 3939 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3940 3941 /* Disable HWPDN. */ 3942 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3943 3944 /* Disable WL suspend. */ 3945 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3946 3947 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3948 for (ntries = 0; ntries < 5000; ntries++) { 3949 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3950 break; 3951 DELAY(10); 3952 } 3953 if (ntries == 5000) 3954 return ETIMEDOUT; 3955 3956 /* Enable LDO normal mode. */ 3957 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3958 3959 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3960 urtwn_write_2(sc, R92C_CR, 0); 3961 reg = urtwn_read_2(sc, R92C_CR); 3962 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3963 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3964 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3965 urtwn_write_2(sc, R92C_CR, reg); 3966 3967 return 0; 3968 } 3969 3970 static int 3971 urtwn_llt_init(struct urtwn_softc *sc) 3972 { 3973 size_t i, page_count, pktbuf_count; 3974 uint32_t val; 3975 int error; 3976 3977 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3978 3979 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3980 3981 if (sc->chip & URTWN_CHIP_88E) 3982 page_count = R88E_TX_PAGE_COUNT; 3983 else if (sc->chip & URTWN_CHIP_92EU) 3984 page_count = R92E_TX_PAGE_COUNT; 3985 else 3986 page_count = R92C_TX_PAGE_COUNT; 3987 if (sc->chip & URTWN_CHIP_88E) 3988 pktbuf_count = R88E_TXPKTBUF_COUNT; 3989 else if (sc->chip & URTWN_CHIP_92EU) 3990 pktbuf_count = R88E_TXPKTBUF_COUNT; 3991 else 3992 pktbuf_count = R92C_TXPKTBUF_COUNT; 3993 3994 if (sc->chip & URTWN_CHIP_92EU) { 3995 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3996 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3997 DELAY(100); 3998 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3999 if (val & R92E_AUTO_LLT_EN) 4000 return EIO; 4001 return 0; 4002 } 4003 4004 /* Reserve pages [0; page_count]. */ 4005 for (i = 0; i < page_count; i++) { 4006 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4007 return error; 4008 } 4009 /* NB: 0xff indicates end-of-list. */ 4010 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 4011 return error; 4012 /* 4013 * Use pages [page_count + 1; pktbuf_count - 1] 4014 * as ring buffer. 4015 */ 4016 for (++i; i < pktbuf_count - 1; i++) { 4017 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 4018 return error; 4019 } 4020 /* Make the last page point to the beginning of the ring buffer. */ 4021 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 4022 return error; 4023 } 4024 4025 static __unused void 4026 urtwn_fw_reset(struct urtwn_softc *sc) 4027 { 4028 uint16_t reg; 4029 int ntries; 4030 4031 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4032 4033 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4034 4035 /* Tell 8051 to reset itself. */ 4036 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 4037 4038 /* Wait until 8051 resets by itself. */ 4039 for (ntries = 0; ntries < 100; ntries++) { 4040 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4041 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 4042 return; 4043 DELAY(50); 4044 } 4045 /* Force 8051 reset. */ 4046 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4047 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 4048 } 4049 4050 static void 4051 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 4052 { 4053 uint16_t reg; 4054 4055 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4056 4057 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4058 4059 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4060 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 4061 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4062 } 4063 DELAY(50); 4064 4065 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 4066 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 4067 DELAY(50); 4068 4069 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 4070 DELAY(50); 4071 4072 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4073 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 4074 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 4075 } 4076 DELAY(50); 4077 4078 } 4079 4080 static int 4081 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 4082 { 4083 uint32_t reg; 4084 int off, mlen, error = 0; 4085 4086 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 4087 device_xname(sc->sc_dev), __func__, page, buf, len)); 4088 4089 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4090 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 4091 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4092 4093 off = R92C_FW_START_ADDR; 4094 while (len > 0) { 4095 if (len > 196) 4096 mlen = 196; 4097 else if (len > 4) 4098 mlen = 4; 4099 else 4100 mlen = 1; 4101 error = urtwn_write_region(sc, off, buf, mlen); 4102 if (error != 0) 4103 break; 4104 off += mlen; 4105 buf += mlen; 4106 len -= mlen; 4107 } 4108 return error; 4109 } 4110 4111 static int 4112 urtwn_load_firmware(struct urtwn_softc *sc) 4113 { 4114 firmware_handle_t fwh; 4115 const struct r92c_fw_hdr *hdr; 4116 const char *name; 4117 u_char *fw, *ptr; 4118 size_t len; 4119 uint32_t reg; 4120 int mlen, ntries, page, error; 4121 4122 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4123 4124 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4125 4126 /* Read firmware image from the filesystem. */ 4127 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4128 name = "rtl8188eufw.bin"; 4129 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4130 name = "rtl8192eefw.bin"; 4131 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4132 URTWN_CHIP_UMC_A_CUT) 4133 name = "rtl8192cfwU.bin"; 4134 else 4135 name = "rtl8192cfw.bin"; 4136 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 4137 aprint_error_dev(sc->sc_dev, 4138 "failed load firmware of file %s (error %d)\n", name, 4139 error); 4140 return error; 4141 } 4142 const size_t fwlen = len = firmware_get_size(fwh); 4143 fw = firmware_malloc(len); 4144 if (fw == NULL) { 4145 aprint_error_dev(sc->sc_dev, 4146 "failed to allocate firmware memory\n"); 4147 firmware_close(fwh); 4148 return ENOMEM; 4149 } 4150 error = firmware_read(fwh, 0, fw, len); 4151 firmware_close(fwh); 4152 if (error != 0) { 4153 aprint_error_dev(sc->sc_dev, 4154 "failed to read firmware (error %d)\n", error); 4155 firmware_free(fw, fwlen); 4156 return error; 4157 } 4158 4159 len = fwlen; 4160 ptr = fw; 4161 hdr = (const struct r92c_fw_hdr *)ptr; 4162 /* Check if there is a valid FW header and skip it. */ 4163 if ((le16toh(hdr->signature) >> 4) == 0x88c || 4164 (le16toh(hdr->signature) >> 4) == 0x88e || 4165 (le16toh(hdr->signature) >> 4) == 0x92e || 4166 (le16toh(hdr->signature) >> 4) == 0x92c) { 4167 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 4168 device_xname(sc->sc_dev), __func__, 4169 le16toh(hdr->version), le16toh(hdr->subversion), 4170 hdr->month, hdr->date, hdr->hour, hdr->minute)); 4171 ptr += sizeof(*hdr); 4172 len -= sizeof(*hdr); 4173 } 4174 4175 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 4176 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4177 ISSET(sc->chip, URTWN_CHIP_92EU)) 4178 urtwn_r88e_fw_reset(sc); 4179 else 4180 urtwn_fw_reset(sc); 4181 } 4182 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4183 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4184 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4185 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4186 R92C_SYS_FUNC_EN_CPUEN); 4187 } 4188 4189 /* download enabled */ 4190 urtwn_write_1(sc, R92C_MCUFWDL, 4191 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 4192 urtwn_write_1(sc, R92C_MCUFWDL + 2, 4193 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 4194 4195 /* Reset the FWDL checksum. */ 4196 urtwn_write_1(sc, R92C_MCUFWDL, 4197 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 4198 4199 DELAY(50); 4200 /* download firmware */ 4201 for (page = 0; len > 0; page++) { 4202 mlen = MIN(len, R92C_FW_PAGE_SIZE); 4203 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 4204 if (error != 0) { 4205 aprint_error_dev(sc->sc_dev, 4206 "could not load firmware page %d\n", page); 4207 goto fail; 4208 } 4209 ptr += mlen; 4210 len -= mlen; 4211 } 4212 4213 /* download disable */ 4214 urtwn_write_1(sc, R92C_MCUFWDL, 4215 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4216 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4217 4218 /* Wait for checksum report. */ 4219 for (ntries = 0; ntries < 1000; ntries++) { 4220 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4221 break; 4222 DELAY(5); 4223 } 4224 if (ntries == 1000) { 4225 aprint_error_dev(sc->sc_dev, 4226 "timeout waiting for checksum report\n"); 4227 error = ETIMEDOUT; 4228 goto fail; 4229 } 4230 4231 /* Wait for firmware readiness. */ 4232 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4233 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4234 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4235 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4236 ISSET(sc->chip, URTWN_CHIP_92EU)) 4237 urtwn_r88e_fw_reset(sc); 4238 for (ntries = 0; ntries < 6000; ntries++) { 4239 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4240 break; 4241 DELAY(5); 4242 } 4243 if (ntries == 6000) { 4244 aprint_error_dev(sc->sc_dev, 4245 "timeout waiting for firmware readiness\n"); 4246 error = ETIMEDOUT; 4247 goto fail; 4248 } 4249 fail: 4250 firmware_free(fw, fwlen); 4251 return error; 4252 } 4253 4254 static __inline int 4255 urtwn_dma_init(struct urtwn_softc *sc) 4256 { 4257 4258 return sc->sc_dma_init(sc); 4259 } 4260 4261 static int 4262 urtwn_r92c_dma_init(struct urtwn_softc *sc) 4263 { 4264 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 4265 uint32_t reg; 4266 int error; 4267 4268 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4269 4270 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4271 4272 /* Initialize LLT table. */ 4273 error = urtwn_llt_init(sc); 4274 if (error != 0) 4275 return error; 4276 4277 /* Get Tx queues to USB endpoints mapping. */ 4278 hashq = hasnq = haslq = 0; 4279 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 4280 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping %#x\n", 4281 device_xname(sc->sc_dev), __func__, reg)); 4282 if (MS(reg, R92C_USB_EP_HQ) != 0) 4283 hashq = 1; 4284 if (MS(reg, R92C_USB_EP_NQ) != 0) 4285 hasnq = 1; 4286 if (MS(reg, R92C_USB_EP_LQ) != 0) 4287 haslq = 1; 4288 nqueues = hashq + hasnq + haslq; 4289 if (nqueues == 0) 4290 return EIO; 4291 /* Get the number of pages for each queue. */ 4292 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 4293 /* The remaining pages are assigned to the high priority queue. */ 4294 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 4295 4296 /* Set number of pages for normal priority queue. */ 4297 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4298 urtwn_write_4(sc, R92C_RQPN, 4299 /* Set number of pages for public queue. */ 4300 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 4301 /* Set number of pages for high priority queue. */ 4302 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4303 /* Set number of pages for low priority queue. */ 4304 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4305 /* Load values. */ 4306 R92C_RQPN_LD); 4307 4308 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4309 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 4310 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 4311 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 4312 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 4313 4314 /* Set queue to USB pipe mapping. */ 4315 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4316 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4317 if (nqueues == 1) { 4318 if (hashq) { 4319 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4320 } else if (hasnq) { 4321 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4322 } else { 4323 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4324 } 4325 } else if (nqueues == 2) { 4326 /* All 2-endpoints configs have a high priority queue. */ 4327 if (!hashq) { 4328 return EIO; 4329 } 4330 if (hasnq) { 4331 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4332 } else { 4333 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 4334 } 4335 } else { 4336 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4337 } 4338 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4339 4340 /* Set Tx/Rx transfer page boundary. */ 4341 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 4342 4343 /* Set Tx/Rx transfer page size. */ 4344 urtwn_write_1(sc, R92C_PBP, 4345 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4346 return 0; 4347 } 4348 4349 static int 4350 urtwn_r88e_dma_init(struct urtwn_softc *sc) 4351 { 4352 usb_interface_descriptor_t *id; 4353 uint32_t reg; 4354 int nqueues; 4355 int error; 4356 4357 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4358 4359 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4360 4361 /* Initialize LLT table. */ 4362 error = urtwn_llt_init(sc); 4363 if (error != 0) 4364 return error; 4365 4366 /* Get Tx queues to USB endpoints mapping. */ 4367 id = usbd_get_interface_descriptor(sc->sc_iface); 4368 nqueues = id->bNumEndpoints - 1; 4369 if (nqueues == 0) 4370 return EIO; 4371 4372 /* Set number of pages for normal priority queue. */ 4373 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 4374 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 4375 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4376 4377 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4378 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 4379 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 4380 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 4381 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 4382 4383 /* Set queue to USB pipe mapping. */ 4384 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4385 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4386 if (nqueues == 1) 4387 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4388 else if (nqueues == 2) 4389 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4390 else 4391 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4392 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4393 4394 /* Set Tx/Rx transfer page boundary. */ 4395 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 4396 4397 /* Set Tx/Rx transfer page size. */ 4398 urtwn_write_1(sc, R92C_PBP, 4399 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 4400 4401 return 0; 4402 } 4403 4404 static void 4405 urtwn_mac_init(struct urtwn_softc *sc) 4406 { 4407 size_t i; 4408 4409 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4410 4411 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4412 4413 /* Write MAC initialization values. */ 4414 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4415 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 4416 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4417 rtl8188eu_mac[i].val); 4418 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4419 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 4420 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 4421 rtl8192eu_mac[i].val); 4422 } else { 4423 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 4424 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4425 rtl8192cu_mac[i].val); 4426 } 4427 } 4428 4429 static void 4430 urtwn_bb_init(struct urtwn_softc *sc) 4431 { 4432 const struct rtwn_bb_prog *prog; 4433 uint32_t reg; 4434 uint8_t crystalcap; 4435 size_t i; 4436 4437 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4438 4439 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4440 4441 /* Enable BB and RF. */ 4442 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4443 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4444 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4445 R92C_SYS_FUNC_EN_DIO_RF); 4446 4447 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4448 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4449 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 4450 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 4451 } 4452 4453 urtwn_write_1(sc, R92C_RF_CTRL, 4454 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4455 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4456 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4457 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4458 4459 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4460 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4461 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4462 urtwn_write_1(sc, 0x15, 0xe9); 4463 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4464 } 4465 4466 /* Select BB programming based on board type. */ 4467 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4468 prog = &rtl8188eu_bb_prog; 4469 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4470 prog = &rtl8192eu_bb_prog; 4471 else if (!(sc->chip & URTWN_CHIP_92C)) { 4472 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4473 prog = &rtl8188ce_bb_prog; 4474 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4475 prog = &rtl8188ru_bb_prog; 4476 } else { 4477 prog = &rtl8188cu_bb_prog; 4478 } 4479 } else { 4480 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4481 prog = &rtl8192ce_bb_prog; 4482 } else { 4483 prog = &rtl8192cu_bb_prog; 4484 } 4485 } 4486 /* Write BB initialization values. */ 4487 for (i = 0; i < prog->count; i++) { 4488 /* additional delay depend on registers */ 4489 switch (prog->regs[i]) { 4490 case 0xfe: 4491 urtwn_delay_ms(sc, 50); 4492 break; 4493 case 0xfd: 4494 urtwn_delay_ms(sc, 5); 4495 break; 4496 case 0xfc: 4497 urtwn_delay_ms(sc, 1); 4498 break; 4499 case 0xfb: 4500 DELAY(50); 4501 break; 4502 case 0xfa: 4503 DELAY(5); 4504 break; 4505 case 0xf9: 4506 DELAY(1); 4507 break; 4508 } 4509 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4510 DELAY(1); 4511 } 4512 4513 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4514 /* 8192C 1T only configuration. */ 4515 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4516 reg = (reg & ~0x00000003) | 0x2; 4517 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4518 4519 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4520 reg = (reg & ~0x00300033) | 0x00200022; 4521 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4522 4523 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4524 reg = (reg & ~0xff000000) | (0x45 << 24); 4525 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4526 4527 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4528 reg = (reg & ~0x000000ff) | 0x23; 4529 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4530 4531 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4532 reg = (reg & ~0x00000030) | (1 << 4); 4533 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4534 4535 reg = urtwn_bb_read(sc, 0xe74); 4536 reg = (reg & ~0x0c000000) | (2 << 26); 4537 urtwn_bb_write(sc, 0xe74, reg); 4538 reg = urtwn_bb_read(sc, 0xe78); 4539 reg = (reg & ~0x0c000000) | (2 << 26); 4540 urtwn_bb_write(sc, 0xe78, reg); 4541 reg = urtwn_bb_read(sc, 0xe7c); 4542 reg = (reg & ~0x0c000000) | (2 << 26); 4543 urtwn_bb_write(sc, 0xe7c, reg); 4544 reg = urtwn_bb_read(sc, 0xe80); 4545 reg = (reg & ~0x0c000000) | (2 << 26); 4546 urtwn_bb_write(sc, 0xe80, reg); 4547 reg = urtwn_bb_read(sc, 0xe88); 4548 reg = (reg & ~0x0c000000) | (2 << 26); 4549 urtwn_bb_write(sc, 0xe88, reg); 4550 } 4551 4552 /* Write AGC values. */ 4553 for (i = 0; i < prog->agccount; i++) { 4554 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 4555 DELAY(1); 4556 } 4557 4558 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4559 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4560 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4561 DELAY(1); 4562 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4563 DELAY(1); 4564 } 4565 4566 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 4567 crystalcap = sc->r88e_rom[0xb9]; 4568 if (crystalcap == 0x00) 4569 crystalcap = 0x20; 4570 crystalcap &= 0x3f; 4571 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 4572 urtwn_bb_write(sc, R92C_AFE_CTRL3, 4573 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4574 crystalcap | crystalcap << 6)); 4575 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 4576 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4577 crystalcap = sc->r88e_rom[0xb9]; 4578 if (crystalcap == 0xff) 4579 crystalcap = 0x20; 4580 crystalcap &= 0x3f; 4581 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4582 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4583 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4584 crystalcap | crystalcap << 6)); 4585 } else { 4586 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4587 R92C_HSSI_PARAM2_CCK_HIPWR) { 4588 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 4589 } 4590 } 4591 } 4592 4593 static void 4594 urtwn_rf_init(struct urtwn_softc *sc) 4595 { 4596 const struct rtwn_rf_prog *prog; 4597 uint32_t reg, mask, saved; 4598 size_t i, j, idx; 4599 4600 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4601 4602 /* Select RF programming based on board type. */ 4603 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4604 prog = rtl8188eu_rf_prog; 4605 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4606 prog = rtl8192eu_rf_prog; 4607 else if (!(sc->chip & URTWN_CHIP_92C)) { 4608 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4609 prog = rtl8188ce_rf_prog; 4610 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4611 prog = rtl8188ru_rf_prog; 4612 } else { 4613 prog = rtl8188cu_rf_prog; 4614 } 4615 } else { 4616 prog = rtl8192ce_rf_prog; 4617 } 4618 4619 for (i = 0; i < sc->nrxchains; i++) { 4620 /* Save RF_ENV control type. */ 4621 idx = i / 2; 4622 mask = 0xffffU << ((i % 2) * 16); 4623 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4624 4625 /* Set RF_ENV enable. */ 4626 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4627 reg |= 0x100000; 4628 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4629 DELAY(50); 4630 4631 /* Set RF_ENV output high. */ 4632 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4633 reg |= 0x10; 4634 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4635 DELAY(50); 4636 4637 /* Set address and data lengths of RF registers. */ 4638 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4639 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4640 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4641 DELAY(50); 4642 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4643 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4644 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4645 DELAY(50); 4646 4647 /* Write RF initialization values for this chain. */ 4648 for (j = 0; j < prog[i].count; j++) { 4649 if (prog[i].regs[j] >= 0xf9 && 4650 prog[i].regs[j] <= 0xfe) { 4651 /* 4652 * These are fake RF registers offsets that 4653 * indicate a delay is required. 4654 */ 4655 urtwn_delay_ms(sc, 50); 4656 continue; 4657 } 4658 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4659 DELAY(5); 4660 } 4661 4662 /* Restore RF_ENV control type. */ 4663 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4664 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4665 } 4666 4667 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4668 URTWN_CHIP_UMC_A_CUT) { 4669 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4670 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4671 } 4672 4673 /* Cache RF register CHNLBW. */ 4674 for (i = 0; i < 2; i++) { 4675 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4676 } 4677 } 4678 4679 static void 4680 urtwn_cam_init(struct urtwn_softc *sc) 4681 { 4682 uint32_t content, command; 4683 uint8_t idx; 4684 size_t i; 4685 4686 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4687 4688 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4689 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4690 return; 4691 4692 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4693 content = (idx & 3) 4694 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4695 | R92C_CAM_VALID; 4696 4697 command = R92C_CAMCMD_POLLING 4698 | R92C_CAMCMD_WRITE 4699 | R92C_CAM_CTL0(idx); 4700 4701 urtwn_write_4(sc, R92C_CAMWRITE, content); 4702 urtwn_write_4(sc, R92C_CAMCMD, command); 4703 } 4704 4705 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4706 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4707 if (i == 0) { 4708 content = (idx & 3) 4709 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4710 | R92C_CAM_VALID; 4711 } else { 4712 content = 0; 4713 } 4714 4715 command = R92C_CAMCMD_POLLING 4716 | R92C_CAMCMD_WRITE 4717 | R92C_CAM_CTL0(idx) 4718 | i; 4719 4720 urtwn_write_4(sc, R92C_CAMWRITE, content); 4721 urtwn_write_4(sc, R92C_CAMCMD, command); 4722 } 4723 } 4724 4725 /* Invalidate all CAM entries. */ 4726 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4727 } 4728 4729 static void 4730 urtwn_pa_bias_init(struct urtwn_softc *sc) 4731 { 4732 uint8_t reg; 4733 size_t i; 4734 4735 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4736 4737 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4738 4739 for (i = 0; i < sc->nrxchains; i++) { 4740 if (sc->pa_setting & (1U << i)) 4741 continue; 4742 4743 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4744 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4745 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4746 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4747 } 4748 if (!(sc->pa_setting & 0x10)) { 4749 reg = urtwn_read_1(sc, 0x16); 4750 reg = (reg & ~0xf0) | 0x90; 4751 urtwn_write_1(sc, 0x16, reg); 4752 } 4753 } 4754 4755 static void 4756 urtwn_rxfilter_init(struct urtwn_softc *sc) 4757 { 4758 4759 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4760 4761 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4762 4763 /* Initialize Rx filter. */ 4764 /* TODO: use better filter for monitor mode. */ 4765 urtwn_write_4(sc, R92C_RCR, 4766 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4767 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4768 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4769 /* Accept all multicast frames. */ 4770 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4771 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4772 /* Accept all management frames. */ 4773 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4774 /* Reject all control frames. */ 4775 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4776 /* Accept all data frames. */ 4777 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4778 } 4779 4780 static void 4781 urtwn_edca_init(struct urtwn_softc *sc) 4782 { 4783 4784 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4785 4786 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4787 4788 /* set spec SIFS (used in NAV) */ 4789 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4790 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4791 4792 /* set SIFS CCK/OFDM */ 4793 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4794 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4795 4796 /* TXOP */ 4797 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4798 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4799 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4800 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4801 } 4802 4803 static void 4804 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4805 uint16_t power[URTWN_RIDX_COUNT]) 4806 { 4807 uint32_t reg; 4808 4809 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4810 __func__, chain)); 4811 4812 /* Write per-CCK rate Tx power. */ 4813 if (chain == 0) { 4814 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4815 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4816 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4817 4818 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4819 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4820 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4821 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4822 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4823 } else { 4824 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4825 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4826 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4827 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4828 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4829 4830 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4831 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4832 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4833 } 4834 /* Write per-OFDM rate Tx power. */ 4835 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4836 SM(R92C_TXAGC_RATE06, power[ 4]) | 4837 SM(R92C_TXAGC_RATE09, power[ 5]) | 4838 SM(R92C_TXAGC_RATE12, power[ 6]) | 4839 SM(R92C_TXAGC_RATE18, power[ 7])); 4840 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4841 SM(R92C_TXAGC_RATE24, power[ 8]) | 4842 SM(R92C_TXAGC_RATE36, power[ 9]) | 4843 SM(R92C_TXAGC_RATE48, power[10]) | 4844 SM(R92C_TXAGC_RATE54, power[11])); 4845 /* Write per-MCS Tx power. */ 4846 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4847 SM(R92C_TXAGC_MCS00, power[12]) | 4848 SM(R92C_TXAGC_MCS01, power[13]) | 4849 SM(R92C_TXAGC_MCS02, power[14]) | 4850 SM(R92C_TXAGC_MCS03, power[15])); 4851 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4852 SM(R92C_TXAGC_MCS04, power[16]) | 4853 SM(R92C_TXAGC_MCS05, power[17]) | 4854 SM(R92C_TXAGC_MCS06, power[18]) | 4855 SM(R92C_TXAGC_MCS07, power[19])); 4856 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4857 SM(R92C_TXAGC_MCS08, power[20]) | 4858 SM(R92C_TXAGC_MCS09, power[21]) | 4859 SM(R92C_TXAGC_MCS10, power[22]) | 4860 SM(R92C_TXAGC_MCS11, power[23])); 4861 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4862 SM(R92C_TXAGC_MCS12, power[24]) | 4863 SM(R92C_TXAGC_MCS13, power[25]) | 4864 SM(R92C_TXAGC_MCS14, power[26]) | 4865 SM(R92C_TXAGC_MCS15, power[27])); 4866 } 4867 4868 static void 4869 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4870 uint16_t power[URTWN_RIDX_COUNT]) 4871 { 4872 struct r92c_rom *rom = &sc->rom; 4873 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4874 const struct rtwn_txpwr *base; 4875 int ridx, group; 4876 4877 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4878 device_xname(sc->sc_dev), __func__, chain, chan)); 4879 4880 /* Determine channel group. */ 4881 if (chan <= 3) { 4882 group = 0; 4883 } else if (chan <= 9) { 4884 group = 1; 4885 } else { 4886 group = 2; 4887 } 4888 4889 /* Get original Tx power based on board type and RF chain. */ 4890 if (!(sc->chip & URTWN_CHIP_92C)) { 4891 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4892 base = &rtl8188ru_txagc[chain]; 4893 } else { 4894 base = &rtl8192cu_txagc[chain]; 4895 } 4896 } else { 4897 base = &rtl8192cu_txagc[chain]; 4898 } 4899 4900 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4901 if (sc->regulatory == 0) { 4902 for (ridx = 0; ridx <= 3; ridx++) { 4903 power[ridx] = base->pwr[0][ridx]; 4904 } 4905 } 4906 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4907 if (sc->regulatory == 3) { 4908 power[ridx] = base->pwr[0][ridx]; 4909 /* Apply vendor limits. */ 4910 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4911 maxpow = rom->ht40_max_pwr[group]; 4912 } else { 4913 maxpow = rom->ht20_max_pwr[group]; 4914 } 4915 maxpow = (maxpow >> (chain * 4)) & 0xf; 4916 if (power[ridx] > maxpow) { 4917 power[ridx] = maxpow; 4918 } 4919 } else if (sc->regulatory == 1) { 4920 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4921 power[ridx] = base->pwr[group][ridx]; 4922 } 4923 } else if (sc->regulatory != 2) { 4924 power[ridx] = base->pwr[0][ridx]; 4925 } 4926 } 4927 4928 /* Compute per-CCK rate Tx power. */ 4929 cckpow = rom->cck_tx_pwr[chain][group]; 4930 for (ridx = 0; ridx <= 3; ridx++) { 4931 power[ridx] += cckpow; 4932 if (power[ridx] > R92C_MAX_TX_PWR) { 4933 power[ridx] = R92C_MAX_TX_PWR; 4934 } 4935 } 4936 4937 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4938 if (sc->ntxchains > 1) { 4939 /* Apply reduction for 2 spatial streams. */ 4940 diff = rom->ht40_2s_tx_pwr_diff[group]; 4941 diff = (diff >> (chain * 4)) & 0xf; 4942 htpow = (htpow > diff) ? htpow - diff : 0; 4943 } 4944 4945 /* Compute per-OFDM rate Tx power. */ 4946 diff = rom->ofdm_tx_pwr_diff[group]; 4947 diff = (diff >> (chain * 4)) & 0xf; 4948 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4949 for (ridx = 4; ridx <= 11; ridx++) { 4950 power[ridx] += ofdmpow; 4951 if (power[ridx] > R92C_MAX_TX_PWR) { 4952 power[ridx] = R92C_MAX_TX_PWR; 4953 } 4954 } 4955 4956 /* Compute per-MCS Tx power. */ 4957 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4958 diff = rom->ht20_tx_pwr_diff[group]; 4959 diff = (diff >> (chain * 4)) & 0xf; 4960 htpow += diff; /* HT40->HT20 correction. */ 4961 } 4962 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4963 power[ridx] += htpow; 4964 if (power[ridx] > R92C_MAX_TX_PWR) { 4965 power[ridx] = R92C_MAX_TX_PWR; 4966 } 4967 } 4968 #ifdef URTWN_DEBUG 4969 if (urtwn_debug & DBG_RF) { 4970 /* Dump per-rate Tx power values. */ 4971 printf("%s: %s: Tx power for chain %zd:\n", 4972 device_xname(sc->sc_dev), __func__, chain); 4973 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4974 printf("%s: %s: Rate %d = %u\n", 4975 device_xname(sc->sc_dev), __func__, ridx, 4976 power[ridx]); 4977 } 4978 } 4979 #endif 4980 } 4981 4982 void 4983 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4984 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4985 { 4986 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4987 const struct rtwn_r88e_txpwr *base; 4988 int ridx, group; 4989 4990 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4991 device_xname(sc->sc_dev), __func__, chain, chan)); 4992 4993 /* Determine channel group. */ 4994 if (chan <= 2) 4995 group = 0; 4996 else if (chan <= 5) 4997 group = 1; 4998 else if (chan <= 8) 4999 group = 2; 5000 else if (chan <= 11) 5001 group = 3; 5002 else if (chan <= 13) 5003 group = 4; 5004 else 5005 group = 5; 5006 5007 /* Get original Tx power based on board type and RF chain. */ 5008 base = &rtl8188eu_txagc[chain]; 5009 5010 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 5011 if (sc->regulatory == 0) { 5012 for (ridx = 0; ridx <= 3; ridx++) 5013 power[ridx] = base->pwr[0][ridx]; 5014 } 5015 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 5016 if (sc->regulatory == 3) 5017 power[ridx] = base->pwr[0][ridx]; 5018 else if (sc->regulatory == 1) { 5019 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 5020 power[ridx] = base->pwr[group][ridx]; 5021 } else if (sc->regulatory != 2) 5022 power[ridx] = base->pwr[0][ridx]; 5023 } 5024 5025 /* Compute per-CCK rate Tx power. */ 5026 cckpow = sc->cck_tx_pwr[group]; 5027 for (ridx = 0; ridx <= 3; ridx++) { 5028 power[ridx] += cckpow; 5029 if (power[ridx] > R92C_MAX_TX_PWR) 5030 power[ridx] = R92C_MAX_TX_PWR; 5031 } 5032 5033 htpow = sc->ht40_tx_pwr[group]; 5034 5035 /* Compute per-OFDM rate Tx power. */ 5036 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 5037 for (ridx = 4; ridx <= 11; ridx++) { 5038 power[ridx] += ofdmpow; 5039 if (power[ridx] > R92C_MAX_TX_PWR) 5040 power[ridx] = R92C_MAX_TX_PWR; 5041 } 5042 5043 bw20pow = htpow + sc->bw20_tx_pwr_diff; 5044 for (ridx = 12; ridx <= 27; ridx++) { 5045 power[ridx] += bw20pow; 5046 if (power[ridx] > R92C_MAX_TX_PWR) 5047 power[ridx] = R92C_MAX_TX_PWR; 5048 } 5049 } 5050 5051 static void 5052 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 5053 { 5054 uint16_t power[URTWN_RIDX_COUNT]; 5055 size_t i; 5056 5057 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5058 5059 for (i = 0; i < sc->ntxchains; i++) { 5060 /* Compute per-rate Tx power values. */ 5061 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5062 ISSET(sc->chip, URTWN_CHIP_92EU)) 5063 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 5064 else 5065 urtwn_get_txpower(sc, i, chan, ht40m, power); 5066 /* Write per-rate Tx power values to hardware. */ 5067 urtwn_write_txpower(sc, i, power); 5068 } 5069 } 5070 5071 static void 5072 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 5073 { 5074 struct ieee80211com *ic = &sc->sc_ic; 5075 u_int chan; 5076 size_t i; 5077 5078 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5079 5080 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 5081 __func__, chan)); 5082 5083 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5084 5085 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 5086 chan += 2; 5087 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 5088 chan -= 2; 5089 } 5090 5091 /* Set Tx power for this new channel. */ 5092 urtwn_set_txpower(sc, chan, ht40m); 5093 5094 for (i = 0; i < sc->nrxchains; i++) { 5095 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5096 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5097 } 5098 5099 if (ht40m) { 5100 /* Is secondary channel below or above primary? */ 5101 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 5102 uint32_t reg; 5103 5104 urtwn_write_1(sc, R92C_BWOPMODE, 5105 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5106 5107 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5108 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5109 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 5110 5111 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5112 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5113 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5114 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5115 5116 /* Set CCK side band. */ 5117 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5118 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5119 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5120 5121 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5122 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5123 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5124 5125 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5126 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5127 ~R92C_FPGA0_ANAPARAM2_CBW20); 5128 5129 reg = urtwn_bb_read(sc, 0x818); 5130 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5131 urtwn_bb_write(sc, 0x818, reg); 5132 5133 /* Select 40MHz bandwidth. */ 5134 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5135 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5136 } else { 5137 urtwn_write_1(sc, R92C_BWOPMODE, 5138 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5139 5140 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5141 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5142 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5143 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5144 5145 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5146 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5147 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5148 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5149 R92C_FPGA0_ANAPARAM2_CBW20); 5150 } 5151 5152 /* Select 20MHz bandwidth. */ 5153 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5154 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5155 (ISSET(sc->chip, URTWN_CHIP_88E) || 5156 ISSET(sc->chip, URTWN_CHIP_92EU) ? 5157 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 5158 } 5159 } 5160 5161 static void 5162 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 5163 { 5164 5165 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 5166 __func__, inited)); 5167 5168 uint32_t addaBackup[16], iqkBackup[4], piMode; 5169 5170 #ifdef notyet 5171 uint32_t odfm0_agccore_regs[3]; 5172 uint32_t ant_regs[3]; 5173 uint32_t rf_regs[8]; 5174 #endif 5175 uint32_t reg0, reg1, reg2; 5176 int i, attempt; 5177 5178 #ifdef notyet 5179 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 5180 R92E_STBC_SETTING + 2)); 5181 urtwn_write_1(sc, R92C_ACLK_MON, 0); 5182 /* Save AGCCORE regs. */ 5183 for (i = 0; i < sc->nrxchains; i++) { 5184 odfm0_agccore_regs[i] = urtwn_read_4(sc, 5185 R92C_OFDM0_AGCCORE1(i)); 5186 } 5187 #endif 5188 /* Save BB regs. */ 5189 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 5190 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 5191 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 5192 5193 /* Save adda regs to be restored when finished. */ 5194 for (i = 0; i < __arraycount(addaReg); i++) 5195 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 5196 /* Save mac regs. */ 5197 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 5198 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 5199 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 5200 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 5201 5202 #ifdef notyet 5203 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 5204 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 5205 5206 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 5207 for (i = 0; i < sc->nrxchains; i++) 5208 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 5209 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 5210 #endif 5211 5212 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5213 R92C_HSSI_PARAM1_PI); 5214 if (piMode == 0) { 5215 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5216 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 5217 R92C_HSSI_PARAM1_PI); 5218 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5219 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 5220 R92C_HSSI_PARAM1_PI); 5221 } 5222 5223 attempt = 1; 5224 5225 next_attempt: 5226 5227 /* Set mac regs for calibration. */ 5228 for (i = 0; i < __arraycount(addaReg); i++) { 5229 urtwn_bb_write(sc, addaReg[i], 5230 addaReg[__arraycount(addaReg) - 1]); 5231 } 5232 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 5233 R92C_CCK0_AFESETTING)); 5234 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 5235 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 5236 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 5237 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 5238 5239 if (sc->ntxchains > 1) 5240 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 5241 5242 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 5243 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 5244 ~R92C_BCN_CTRL_EN_BCN)); 5245 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 5246 ~R92C_BCN_CTRL_EN_BCN)); 5247 5248 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 5249 ~R92C_GPIO_MUXCFG_ENBT)); 5250 5251 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 5252 5253 if (sc->ntxchains > 1) 5254 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 5255 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 5256 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 5257 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 5258 5259 /* Restore BB regs. */ 5260 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 5261 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 5262 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 5263 5264 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 5265 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 5266 if (sc->nrxchains > 1) 5267 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 5268 5269 if (attempt-- > 0) 5270 goto next_attempt; 5271 5272 /* Restore mode. */ 5273 if (piMode == 0) { 5274 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 5275 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 5276 ~R92C_HSSI_PARAM1_PI); 5277 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 5278 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 5279 ~R92C_HSSI_PARAM1_PI); 5280 } 5281 5282 #ifdef notyet 5283 for (i = 0; i < sc->nrxchains; i++) { 5284 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 5285 odfm0_agccore_regs[i]); 5286 } 5287 #endif 5288 5289 /* Restore adda regs. */ 5290 for (i = 0; i < __arraycount(addaReg); i++) 5291 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 5292 /* Restore mac regs. */ 5293 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 5294 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 5295 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 5296 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 5297 5298 #ifdef notyet 5299 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 5300 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 5301 5302 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 5303 for (i = 0; i < sc->nrxchains; i++) 5304 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 5305 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 5306 #endif 5307 } 5308 5309 static void 5310 urtwn_lc_calib(struct urtwn_softc *sc) 5311 { 5312 uint32_t rf_ac[2]; 5313 uint8_t txmode; 5314 size_t i; 5315 5316 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5317 5318 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5319 5320 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5321 if ((txmode & 0x70) != 0) { 5322 /* Disable all continuous Tx. */ 5323 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5324 5325 /* Set RF mode to standby mode. */ 5326 for (i = 0; i < sc->nrxchains; i++) { 5327 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5328 urtwn_rf_write(sc, i, R92C_RF_AC, 5329 RW(rf_ac[i], R92C_RF_AC_MODE, 5330 R92C_RF_AC_MODE_STANDBY)); 5331 } 5332 } else { 5333 /* Block all Tx queues. */ 5334 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 5335 } 5336 /* Start calibration. */ 5337 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5338 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5339 5340 /* Give calibration the time to complete. */ 5341 urtwn_delay_ms(sc, 100); 5342 5343 /* Restore configuration. */ 5344 if ((txmode & 0x70) != 0) { 5345 /* Restore Tx mode. */ 5346 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5347 /* Restore RF mode. */ 5348 for (i = 0; i < sc->nrxchains; i++) { 5349 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5350 } 5351 } else { 5352 /* Unblock all Tx queues. */ 5353 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5354 } 5355 } 5356 5357 static void 5358 urtwn_temp_calib(struct urtwn_softc *sc) 5359 { 5360 int temp, t_meter_reg; 5361 5362 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5363 5364 KASSERT(mutex_owned(&sc->sc_write_mtx)); 5365 5366 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 5367 t_meter_reg = R92C_RF_T_METER; 5368 else 5369 t_meter_reg = R92E_RF_T_METER; 5370 5371 if (sc->thcal_state == 0) { 5372 /* Start measuring temperature. */ 5373 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 5374 device_xname(sc->sc_dev), __func__)); 5375 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 5376 sc->thcal_state = 1; 5377 return; 5378 } 5379 sc->thcal_state = 0; 5380 5381 /* Read measured temperature. */ 5382 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 5383 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 5384 __func__, temp)); 5385 if (temp == 0) /* Read failed, skip. */ 5386 return; 5387 5388 /* 5389 * Redo LC calibration if temperature changed significantly since 5390 * last calibration. 5391 */ 5392 if (sc->thcal_lctemp == 0) { 5393 /* First LC calibration is performed in urtwn_init(). */ 5394 sc->thcal_lctemp = temp; 5395 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5396 DPRINTFN(DBG_RF, 5397 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 5398 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 5399 temp)); 5400 urtwn_lc_calib(sc); 5401 /* Record temperature of last LC calibration. */ 5402 sc->thcal_lctemp = temp; 5403 } 5404 } 5405 5406 static int 5407 urtwn_init(struct ifnet *ifp) 5408 { 5409 struct ieee80211vap *vap = ifp->if_softc; 5410 struct ieee80211com *ic = vap->iv_ic; 5411 struct urtwn_softc *sc = ic->ic_softc; 5412 struct urtwn_rx_data *data; 5413 uint32_t reg; 5414 size_t i; 5415 int error; 5416 5417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5418 5419 urtwn_stop(ifp, 0); 5420 5421 mutex_enter(&sc->sc_write_mtx); 5422 5423 mutex_enter(&sc->sc_task_mtx); 5424 /* Init host async commands ring. */ 5425 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 5426 mutex_exit(&sc->sc_task_mtx); 5427 5428 mutex_enter(&sc->sc_fwcmd_mtx); 5429 /* Init firmware commands ring. */ 5430 sc->fwcur = 0; 5431 mutex_exit(&sc->sc_fwcmd_mtx); 5432 5433 /* Allocate Tx/Rx buffers. */ 5434 error = urtwn_alloc_rx_list(sc); 5435 if (error != 0) { 5436 aprint_error_dev(sc->sc_dev, 5437 "could not allocate Rx buffers\n"); 5438 goto fail; 5439 } 5440 error = urtwn_alloc_tx_list(sc); 5441 if (error != 0) { 5442 aprint_error_dev(sc->sc_dev, 5443 "could not allocate Tx buffers\n"); 5444 goto fail; 5445 } 5446 5447 /* Power on adapter. */ 5448 error = urtwn_power_on(sc); 5449 if (error != 0) 5450 goto fail; 5451 5452 /* Initialize DMA. */ 5453 error = urtwn_dma_init(sc); 5454 if (error != 0) 5455 goto fail; 5456 5457 /* Set info size in Rx descriptors (in 64-bit words). */ 5458 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5459 5460 /* Init interrupts. */ 5461 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5462 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5463 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5464 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5465 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5466 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5467 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5468 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 5469 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5470 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5471 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5472 } 5473 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 5474 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 5475 } else { 5476 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5477 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5478 } 5479 5480 /* Set MAC address. */ 5481 IEEE80211_ADDR_COPY(ic->ic_macaddr, CLLADDR(ifp->if_sadl)); 5482 urtwn_write_region(sc, R92C_MACID, ic->ic_macaddr, IEEE80211_ADDR_LEN); 5483 5484 /* Set initial network type. */ 5485 reg = urtwn_read_4(sc, R92C_CR); 5486 switch (ic->ic_opmode) { 5487 case IEEE80211_M_STA: 5488 default: 5489 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 5490 break; 5491 5492 case IEEE80211_M_IBSS: 5493 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 5494 break; 5495 } 5496 urtwn_write_4(sc, R92C_CR, reg); 5497 5498 /* Set response rate */ 5499 reg = urtwn_read_4(sc, R92C_RRSR); 5500 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5501 urtwn_write_4(sc, R92C_RRSR, reg); 5502 5503 /* SIFS (used in NAV) */ 5504 urtwn_write_2(sc, R92C_SPEC_SIFS, 5505 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 5506 5507 /* Set short/long retry limits. */ 5508 urtwn_write_2(sc, R92C_RL, 5509 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5510 5511 /* Initialize EDCA parameters. */ 5512 urtwn_edca_init(sc); 5513 5514 /* Setup rate fallback. */ 5515 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5516 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5517 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5518 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5519 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5520 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5521 } 5522 5523 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5524 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5525 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5526 /* Set ACK timeout. */ 5527 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5528 5529 /* Setup USB aggregation. */ 5530 /* Tx */ 5531 reg = urtwn_read_4(sc, R92C_TDECTRL); 5532 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5533 urtwn_write_4(sc, R92C_TDECTRL, reg); 5534 /* Rx */ 5535 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5536 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5537 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5538 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5539 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 5540 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 5541 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5542 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5543 ISSET(sc->chip, URTWN_CHIP_92EU)) 5544 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5545 else 5546 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5547 5548 /* Initialize beacon parameters. */ 5549 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5550 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5551 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 5552 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 5553 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5554 5555 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5556 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5557 /* Setup AMPDU aggregation. */ 5558 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5559 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5560 urtwn_write_2(sc, 0x4ca, 0x0708); 5561 5562 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5563 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 5564 } 5565 5566 /* Load 8051 microcode. */ 5567 error = urtwn_load_firmware(sc); 5568 if (error != 0) 5569 goto fail; 5570 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 5571 5572 /* Initialize MAC/BB/RF blocks. */ 5573 /* 5574 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 5575 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 5576 * XXX: This setting should be removed from rtl8192cu_mac[]. 5577 */ 5578 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 5579 urtwn_rxfilter_init(sc); // reset R92C_RCR 5580 urtwn_bb_init(sc); 5581 urtwn_rf_init(sc); 5582 5583 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5584 ISSET(sc->chip, URTWN_CHIP_92EU)) { 5585 urtwn_write_2(sc, R92C_CR, 5586 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5587 R92C_CR_MACRXEN); 5588 } 5589 5590 /* Turn CCK and OFDM blocks on. */ 5591 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5592 reg |= R92C_RFMOD_CCK_EN; 5593 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5594 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5595 reg |= R92C_RFMOD_OFDM_EN; 5596 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5597 5598 /* Clear per-station keys table. */ 5599 urtwn_cam_init(sc); 5600 5601 /* Enable hardware sequence numbering. */ 5602 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 5603 5604 /* Perform LO and IQ calibrations. */ 5605 urtwn_iq_calib(sc, sc->iqk_inited); 5606 sc->iqk_inited = true; 5607 5608 /* Perform LC calibration. */ 5609 urtwn_lc_calib(sc); 5610 5611 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5612 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5613 /* Fix USB interference issue. */ 5614 urtwn_write_1(sc, 0xfe40, 0xe0); 5615 urtwn_write_1(sc, 0xfe41, 0x8d); 5616 urtwn_write_1(sc, 0xfe42, 0x80); 5617 urtwn_write_4(sc, 0x20c, 0xfd0320); 5618 5619 urtwn_pa_bias_init(sc); 5620 } 5621 5622 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5623 !(sc->chip & URTWN_CHIP_92EU)) { 5624 /* 1T1R */ 5625 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5626 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5627 } 5628 5629 /* Initialize GPIO setting. */ 5630 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5631 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5632 5633 /* Fix for lower temperature. */ 5634 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5635 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5636 urtwn_write_1(sc, 0x15, 0xe9); 5637 5638 /* Set default channel. */ 5639 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5640 5641 /* Queue Rx xfers. */ 5642 for (size_t j = 0; j < sc->rx_npipe; j++) { 5643 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5644 data = &sc->rx_data[j][i]; 5645 usbd_setup_xfer(data->xfer, data, data->buf, 5646 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5647 urtwn_rxeof); 5648 error = usbd_transfer(data->xfer); 5649 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5650 error != USBD_IN_PROGRESS)) 5651 goto fail; 5652 } 5653 } 5654 5655 /* We're ready to go. */ 5656 ifp->if_flags &= ~IFF_OACTIVE; 5657 ifp->if_flags |= IFF_RUNNING; 5658 sc->sc_running = true; 5659 5660 mutex_exit(&sc->sc_write_mtx); 5661 5662 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5663 ieee80211_new_state(vap, IEEE80211_S_RUN, -1); 5664 else if (vap->iv_roaming != IEEE80211_ROAMING_MANUAL) 5665 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 5666 urtwn_wait_async(sc); 5667 5668 /* Init the rest of the 802.11 stuff */ 5669 ieee80211_init(ifp); 5670 5671 return 0; 5672 5673 fail: 5674 mutex_exit(&sc->sc_write_mtx); 5675 5676 urtwn_stop(ifp, 1); 5677 return error; 5678 } 5679 5680 static void 5681 urtwn_stop(struct ifnet *ifp, int disable) 5682 { 5683 struct ieee80211vap *vap = ifp->if_softc; 5684 struct ieee80211com *ic = vap->iv_ic; 5685 struct urtwn_softc *sc = ic->ic_softc; 5686 size_t i; 5687 int s; 5688 5689 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5690 5691 s = splusb(); 5692 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 5693 urtwn_wait_async(sc); 5694 splx(s); 5695 5696 sc->tx_timer = 0; 5697 ifp->if_timer = 0; 5698 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5699 5700 callout_stop(&sc->sc_scan_to); 5701 callout_stop(&sc->sc_calib_to); 5702 5703 /* Abort Tx. */ 5704 for (i = 0; i < sc->tx_npipe; i++) { 5705 if (sc->tx_pipe[i] != NULL) 5706 usbd_abort_pipe(sc->tx_pipe[i]); 5707 } 5708 5709 /* Stop Rx pipe. */ 5710 for (i = 0; i < sc->rx_npipe; i++) { 5711 if (sc->rx_pipe[i] != NULL) 5712 usbd_abort_pipe(sc->rx_pipe[i]); 5713 } 5714 5715 /* Free Tx/Rx buffers. */ 5716 urtwn_free_tx_list(sc); 5717 urtwn_free_rx_list(sc); 5718 5719 sc->sc_running = false; 5720 if (disable) 5721 urtwn_chip_stop(sc); 5722 } 5723 5724 static int 5725 urtwn_reset(struct ieee80211vap *vap, u_long arg) 5726 { 5727 struct ifnet *ifp = vap->iv_ifp; 5728 struct urtwn_softc *sc = ifp->if_softc; 5729 struct ieee80211com *ic = &sc->sc_ic; 5730 5731 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5732 return ENETRESET; 5733 5734 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5735 5736 return 0; 5737 } 5738 5739 static void 5740 urtwn_chip_stop(struct urtwn_softc *sc) 5741 { 5742 uint32_t reg; 5743 bool disabled = true; 5744 5745 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5746 5747 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5748 ISSET(sc->chip, URTWN_CHIP_92EU)) 5749 return; 5750 5751 mutex_enter(&sc->sc_write_mtx); 5752 5753 /* 5754 * RF Off Sequence 5755 */ 5756 /* Pause MAC TX queue */ 5757 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5758 5759 /* Disable RF */ 5760 urtwn_rf_write(sc, 0, 0, 0); 5761 5762 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5763 5764 /* Reset BB state machine */ 5765 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5766 R92C_SYS_FUNC_EN_USBD | 5767 R92C_SYS_FUNC_EN_USBA | 5768 R92C_SYS_FUNC_EN_BB_GLB_RST); 5769 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5770 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5771 5772 /* 5773 * Reset digital sequence 5774 */ 5775 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5776 /* Reset MCU ready status */ 5777 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5778 /* If firmware in ram code, do reset */ 5779 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5780 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5781 ISSET(sc->chip, URTWN_CHIP_92EU)) 5782 urtwn_r88e_fw_reset(sc); 5783 else 5784 urtwn_fw_reset(sc); 5785 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5786 } 5787 } 5788 5789 /* Reset MAC and Enable 8051 */ 5790 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5791 5792 /* Reset MCU ready status */ 5793 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5794 5795 if (disabled) { 5796 /* Disable MAC clock */ 5797 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5798 /* Disable AFE PLL */ 5799 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5800 /* Gated AFE DIG_CLOCK */ 5801 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5802 /* Isolated digital to PON */ 5803 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5804 } 5805 5806 /* 5807 * Pull GPIO PIN to balance level and LED control 5808 */ 5809 /* 1. Disable GPIO[7:0] */ 5810 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5811 5812 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5813 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5814 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5815 5816 /* Disable GPIO[10:8] */ 5817 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5818 5819 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5820 reg |= (((reg & 0x000f) << 4) | 0x0780); 5821 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5822 5823 /* Disable LED0 & 1 */ 5824 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5825 5826 /* 5827 * Reset digital sequence 5828 */ 5829 if (disabled) { 5830 /* Disable ELDR clock */ 5831 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5832 /* Isolated ELDR to PON */ 5833 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5834 } 5835 5836 /* 5837 * Disable analog sequence 5838 */ 5839 if (disabled) { 5840 /* Disable A15 power */ 5841 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5842 /* Disable digital core power */ 5843 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5844 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5845 ~R92C_LDOV12D_CTRL_LDV12_EN); 5846 } 5847 5848 /* Enter PFM mode */ 5849 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5850 5851 /* Set USB suspend */ 5852 urtwn_write_2(sc, R92C_APS_FSMCO, 5853 R92C_APS_FSMCO_APDM_HOST | 5854 R92C_APS_FSMCO_AFSM_HSUS | 5855 R92C_APS_FSMCO_PFM_ALDN); 5856 5857 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5858 5859 mutex_exit(&sc->sc_write_mtx); 5860 } 5861 5862 static void 5863 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5864 { 5865 if (sc->sc_running == false) 5866 DELAY(ms * 1000); 5867 else 5868 usbd_delay_ms(sc->sc_udev, ms); 5869 } 5870 5871 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5872 5873 #ifdef _MODULE 5874 #include "ioconf.c" 5875 #endif 5876 5877 static int 5878 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5879 { 5880 int error = 0; 5881 5882 switch (cmd) { 5883 case MODULE_CMD_INIT: 5884 #ifdef _MODULE 5885 error = config_init_component(cfdriver_ioconf_urtwn, 5886 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5887 #endif 5888 return error; 5889 case MODULE_CMD_FINI: 5890 #ifdef _MODULE 5891 error = config_fini_component(cfdriver_ioconf_urtwn, 5892 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5893 #endif 5894 return error; 5895 default: 5896 return ENOTTY; 5897 } 5898 } 5899
Indexes created Thu Oct 02 14:10:14 GMT 2025