if_urtwn.c revision 1.70
1 /* $NetBSD: if_urtwn.c,v 1.70 2019/06/15 04:00:17 msaitoh Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.70 2019/06/15 04:00:17 msaitoh Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/ic/rtwnreg.h> 78 #include <dev/ic/rtwn_data.h> 79 #include <dev/usb/if_urtwnreg.h> 80 #include <dev/usb/if_urtwnvar.h> 81 82 /* 83 * The sc_write_mtx locking is to prevent sequences of writes from 84 * being intermingled with each other. I don't know if this is really 85 * needed. I have added it just to be on the safe side. 86 */ 87 88 #ifdef URTWN_DEBUG 89 #define DBG_INIT __BIT(0) 90 #define DBG_FN __BIT(1) 91 #define DBG_TX __BIT(2) 92 #define DBG_RX __BIT(3) 93 #define DBG_STM __BIT(4) 94 #define DBG_RF __BIT(5) 95 #define DBG_REG __BIT(6) 96 #define DBG_ALL 0xffffffffU 97 u_int urtwn_debug = 0; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 196 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 197 198 /* URTWN_RTL8192EU */ 199 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 200 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 201 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 202 }; 203 #undef URTWN_DEV 204 #undef URTWN_RTL8188E_DEV 205 #undef URTWN_RTL8192EU_DEV 206 207 static int urtwn_match(device_t, cfdata_t, void *); 208 static void urtwn_attach(device_t, device_t, void *); 209 static int urtwn_detach(device_t, int); 210 static int urtwn_activate(device_t, enum devact); 211 212 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 213 urtwn_attach, urtwn_detach, urtwn_activate); 214 215 static int urtwn_open_pipes(struct urtwn_softc *); 216 static void urtwn_close_pipes(struct urtwn_softc *); 217 static int urtwn_alloc_rx_list(struct urtwn_softc *); 218 static void urtwn_free_rx_list(struct urtwn_softc *); 219 static int urtwn_alloc_tx_list(struct urtwn_softc *); 220 static void urtwn_free_tx_list(struct urtwn_softc *); 221 static void urtwn_task(void *); 222 static void urtwn_do_async(struct urtwn_softc *, 223 void (*)(struct urtwn_softc *, void *), void *, int); 224 static void urtwn_wait_async(struct urtwn_softc *); 225 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 226 int); 227 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 228 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 229 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 230 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 231 int); 232 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 233 int); 234 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 235 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 236 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 237 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 238 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 239 uint32_t); 240 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 241 uint32_t); 242 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 243 uint32_t); 244 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 245 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 246 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 247 static void urtwn_efuse_read(struct urtwn_softc *); 248 static void urtwn_efuse_switch_power(struct urtwn_softc *); 249 static int urtwn_read_chipid(struct urtwn_softc *); 250 #ifdef URTWN_DEBUG 251 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 252 #endif 253 static void urtwn_read_rom(struct urtwn_softc *); 254 static void urtwn_r88e_read_rom(struct urtwn_softc *); 255 static int urtwn_media_change(struct ifnet *); 256 static int urtwn_ra_init(struct urtwn_softc *); 257 static int urtwn_get_nettype(struct urtwn_softc *); 258 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 259 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 260 static void urtwn_set_led(struct urtwn_softc *, int, int); 261 static void urtwn_calib_to(void *); 262 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 263 static void urtwn_next_scan(void *); 264 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 265 int); 266 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 267 static int urtwn_wme_update(struct ieee80211com *); 268 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 269 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 270 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 271 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 272 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 273 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 274 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 275 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 276 struct ieee80211_node *, struct urtwn_tx_data *); 277 static struct urtwn_tx_data * 278 urtwn_get_tx_data(struct urtwn_softc *, size_t); 279 static void urtwn_start(struct ifnet *); 280 static void urtwn_watchdog(struct ifnet *); 281 static int urtwn_ioctl(struct ifnet *, u_long, void *); 282 static int urtwn_r92c_power_on(struct urtwn_softc *); 283 static int urtwn_r92e_power_on(struct urtwn_softc *); 284 static int urtwn_r88e_power_on(struct urtwn_softc *); 285 static int urtwn_llt_init(struct urtwn_softc *); 286 static void urtwn_fw_reset(struct urtwn_softc *); 287 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 288 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 289 static int urtwn_load_firmware(struct urtwn_softc *); 290 static int urtwn_r92c_dma_init(struct urtwn_softc *); 291 static int urtwn_r88e_dma_init(struct urtwn_softc *); 292 static void urtwn_mac_init(struct urtwn_softc *); 293 static void urtwn_bb_init(struct urtwn_softc *); 294 static void urtwn_rf_init(struct urtwn_softc *); 295 static void urtwn_cam_init(struct urtwn_softc *); 296 static void urtwn_pa_bias_init(struct urtwn_softc *); 297 static void urtwn_rxfilter_init(struct urtwn_softc *); 298 static void urtwn_edca_init(struct urtwn_softc *); 299 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 300 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 301 uint16_t[]); 302 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 303 u_int, uint16_t[]); 304 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 305 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 306 u_int); 307 static void urtwn_iq_calib(struct urtwn_softc *, bool); 308 static void urtwn_lc_calib(struct urtwn_softc *); 309 static void urtwn_temp_calib(struct urtwn_softc *); 310 static int urtwn_init(struct ifnet *); 311 static void urtwn_stop(struct ifnet *, int); 312 static int urtwn_reset(struct ifnet *); 313 static void urtwn_chip_stop(struct urtwn_softc *); 314 static void urtwn_newassoc(struct ieee80211_node *, int); 315 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 316 317 /* Aliases. */ 318 #define urtwn_bb_write urtwn_write_4 319 #define urtwn_bb_read urtwn_read_4 320 321 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 322 323 static const uint16_t addaReg[] = { 324 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 325 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 326 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 327 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 328 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 329 }; 330 331 static int 332 urtwn_match(device_t parent, cfdata_t match, void *aux) 333 { 334 struct usb_attach_arg *uaa = aux; 335 336 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 337 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 338 } 339 340 static void 341 urtwn_attach(device_t parent, device_t self, void *aux) 342 { 343 struct urtwn_softc *sc = device_private(self); 344 struct ieee80211com *ic = &sc->sc_ic; 345 struct ifnet *ifp = &sc->sc_if; 346 struct usb_attach_arg *uaa = aux; 347 char *devinfop; 348 const struct urtwn_dev *dev; 349 usb_device_request_t req; 350 size_t i; 351 int error; 352 353 sc->sc_dev = self; 354 sc->sc_udev = uaa->uaa_device; 355 356 sc->chip = 0; 357 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 358 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 359 SET(sc->chip, URTWN_CHIP_88E); 360 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 361 SET(sc->chip, URTWN_CHIP_92EU); 362 363 aprint_naive("\n"); 364 aprint_normal("\n"); 365 366 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 367 368 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 369 aprint_normal_dev(self, "%s\n", devinfop); 370 usbd_devinfo_free(devinfop); 371 372 req.bmRequestType = UT_WRITE_DEVICE; 373 req.bRequest = UR_SET_FEATURE; 374 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 375 USETW(req.wIndex, UHF_PORT_SUSPEND); 376 USETW(req.wLength, 0); 377 378 (void) usbd_do_request(sc->sc_udev, &req, 0); 379 380 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 381 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 382 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 383 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 384 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 385 386 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 387 388 callout_init(&sc->sc_scan_to, 0); 389 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 390 callout_init(&sc->sc_calib_to, 0); 391 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 392 393 error = usbd_set_config_no(sc->sc_udev, 1, 0); 394 if (error != 0) { 395 aprint_error_dev(self, "failed to set configuration" 396 ", err=%s\n", usbd_errstr(error)); 397 goto fail; 398 } 399 400 /* Get the first interface handle. */ 401 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 402 if (error != 0) { 403 aprint_error_dev(self, "could not get interface handle\n"); 404 goto fail; 405 } 406 407 error = urtwn_read_chipid(sc); 408 if (error != 0) { 409 aprint_error_dev(self, "unsupported test chip\n"); 410 goto fail; 411 } 412 413 /* Determine number of Tx/Rx chains. */ 414 if (sc->chip & URTWN_CHIP_92C) { 415 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 416 sc->nrxchains = 2; 417 } else if (sc->chip & URTWN_CHIP_92EU) { 418 sc->ntxchains = 2; 419 sc->nrxchains = 2; 420 } else { 421 sc->ntxchains = 1; 422 sc->nrxchains = 1; 423 } 424 425 if (ISSET(sc->chip, URTWN_CHIP_88E) || 426 ISSET(sc->chip, URTWN_CHIP_92EU)) 427 urtwn_r88e_read_rom(sc); 428 else 429 urtwn_read_rom(sc); 430 431 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 432 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 433 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 434 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 435 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 436 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 437 "8188CUS", sc->ntxchains, sc->nrxchains, 438 ether_sprintf(ic->ic_myaddr)); 439 440 error = urtwn_open_pipes(sc); 441 if (error != 0) { 442 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 443 goto fail; 444 } 445 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 446 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 447 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 448 449 /* 450 * Setup the 802.11 device. 451 */ 452 ic->ic_ifp = ifp; 453 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 454 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 455 ic->ic_state = IEEE80211_S_INIT; 456 457 /* Set device capabilities. */ 458 ic->ic_caps = 459 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 460 IEEE80211_C_IBSS | /* IBSS mode supported */ 461 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 462 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 463 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 464 IEEE80211_C_WME | /* 802.11e */ 465 IEEE80211_C_WPA; /* 802.11i */ 466 467 /* Set supported .11b and .11g rates. */ 468 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 469 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 470 471 /* Set supported .11b and .11g channels (1 through 14). */ 472 for (i = 1; i <= 14; i++) { 473 ic->ic_channels[i].ic_freq = 474 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 475 ic->ic_channels[i].ic_flags = 476 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 477 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 478 } 479 480 ifp->if_softc = sc; 481 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 482 ifp->if_init = urtwn_init; 483 ifp->if_ioctl = urtwn_ioctl; 484 ifp->if_start = urtwn_start; 485 ifp->if_watchdog = urtwn_watchdog; 486 IFQ_SET_READY(&ifp->if_snd); 487 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 488 489 if_initialize(ifp); 490 ieee80211_ifattach(ic); 491 492 /* override default methods */ 493 ic->ic_newassoc = urtwn_newassoc; 494 ic->ic_reset = urtwn_reset; 495 ic->ic_wme.wme_update = urtwn_wme_update; 496 497 /* Override state transition machine. */ 498 sc->sc_newstate = ic->ic_newstate; 499 ic->ic_newstate = urtwn_newstate; 500 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 501 502 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 503 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 504 &sc->sc_drvbpf); 505 506 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 507 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 508 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 509 510 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 511 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 512 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 513 514 ifp->if_percpuq = if_percpuq_create(ifp); 515 if_register(ifp); 516 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 517 RND_TYPE_NET, RND_FLAG_DEFAULT); 518 519 ieee80211_announce(ic); 520 521 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 522 523 if (!pmf_device_register(self, NULL, NULL)) 524 aprint_error_dev(self, "couldn't establish power handler\n"); 525 526 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 527 return; 528 529 fail: 530 sc->sc_dying = 1; 531 aprint_error_dev(self, "attach failed\n"); 532 } 533 534 static int 535 urtwn_detach(device_t self, int flags) 536 { 537 struct urtwn_softc *sc = device_private(self); 538 struct ifnet *ifp = &sc->sc_if; 539 int s; 540 541 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 542 543 pmf_device_deregister(self); 544 545 s = splusb(); 546 547 sc->sc_dying = 1; 548 549 callout_halt(&sc->sc_scan_to, NULL); 550 callout_halt(&sc->sc_calib_to, NULL); 551 552 pmf_device_deregister(self); 553 554 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 555 urtwn_stop(ifp, 0); 556 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 557 NULL); 558 559 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 560 bpf_detach(ifp); 561 ieee80211_ifdetach(&sc->sc_ic); 562 if_detach(ifp); 563 564 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 565 urtwn_close_pipes(sc); 566 } 567 568 splx(s); 569 570 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 571 572 callout_destroy(&sc->sc_scan_to); 573 callout_destroy(&sc->sc_calib_to); 574 575 mutex_destroy(&sc->sc_write_mtx); 576 mutex_destroy(&sc->sc_fwcmd_mtx); 577 mutex_destroy(&sc->sc_tx_mtx); 578 mutex_destroy(&sc->sc_rx_mtx); 579 mutex_destroy(&sc->sc_task_mtx); 580 581 return 0; 582 } 583 584 static int 585 urtwn_activate(device_t self, enum devact act) 586 { 587 struct urtwn_softc *sc = device_private(self); 588 589 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 590 591 switch (act) { 592 case DVACT_DEACTIVATE: 593 if_deactivate(sc->sc_ic.ic_ifp); 594 return 0; 595 default: 596 return EOPNOTSUPP; 597 } 598 } 599 600 static int 601 urtwn_open_pipes(struct urtwn_softc *sc) 602 { 603 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 604 static uint8_t epaddr[R92C_MAX_EPOUT]; 605 static uint8_t rxepaddr[R92C_MAX_EPIN]; 606 usb_interface_descriptor_t *id; 607 usb_endpoint_descriptor_t *ed; 608 size_t i, ntx = 0, nrx = 0; 609 int error; 610 611 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 612 613 /* Determine the number of bulk-out pipes. */ 614 id = usbd_get_interface_descriptor(sc->sc_iface); 615 for (i = 0; i < id->bNumEndpoints; i++) { 616 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 617 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 618 continue; 619 } 620 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 621 if (ntx < sizeof(epaddr)) 622 epaddr[ntx] = ed->bEndpointAddress; 623 ntx++; 624 } 625 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 626 if (nrx < sizeof(rxepaddr)) 627 rxepaddr[nrx] = ed->bEndpointAddress; 628 nrx++; 629 } 630 } 631 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 632 aprint_error_dev(sc->sc_dev, 633 "%zd: invalid number of Rx bulk pipes\n", nrx); 634 return EIO; 635 } 636 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 637 aprint_error_dev(sc->sc_dev, 638 "%zd: invalid number of Tx bulk pipes\n", ntx); 639 return EIO; 640 } 641 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 642 device_xname(sc->sc_dev), __func__, nrx, ntx)); 643 sc->rx_npipe = nrx; 644 sc->tx_npipe = ntx; 645 646 /* Open bulk-in pipe at address 0x81. */ 647 for (i = 0; i < nrx; i++) { 648 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 649 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 650 if (error != 0) { 651 aprint_error_dev(sc->sc_dev, 652 "could not open Rx bulk pipe 0x%02x: %d\n", 653 rxepaddr[i], error); 654 goto fail; 655 } 656 } 657 658 /* Open bulk-out pipes (up to 3). */ 659 for (i = 0; i < ntx; i++) { 660 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 661 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 662 if (error != 0) { 663 aprint_error_dev(sc->sc_dev, 664 "could not open Tx bulk pipe 0x%02x: %d\n", 665 epaddr[i], error); 666 goto fail; 667 } 668 } 669 670 /* Map 802.11 access categories to USB pipes. */ 671 sc->ac2idx[WME_AC_BK] = 672 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 673 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 674 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 675 676 fail: 677 if (error != 0) 678 urtwn_close_pipes(sc); 679 return error; 680 } 681 682 static void 683 urtwn_close_pipes(struct urtwn_softc *sc) 684 { 685 struct usbd_pipe *pipe; 686 size_t i; 687 688 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 689 690 /* Close Rx pipes. */ 691 CTASSERT(sizeof(pipe) == sizeof(void *)); 692 for (i = 0; i < sc->rx_npipe; i++) { 693 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 694 if (pipe != NULL) { 695 usbd_close_pipe(pipe); 696 } 697 } 698 699 /* Close Tx pipes. */ 700 for (i = 0; i < sc->tx_npipe; i++) { 701 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 702 if (pipe != NULL) { 703 usbd_close_pipe(pipe); 704 } 705 } 706 } 707 708 static int 709 urtwn_alloc_rx_list(struct urtwn_softc *sc) 710 { 711 struct urtwn_rx_data *data; 712 size_t i; 713 int error = 0; 714 715 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 716 717 for (size_t j = 0; j < sc->rx_npipe; j++) { 718 TAILQ_INIT(&sc->rx_free_list[j]); 719 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 720 data = &sc->rx_data[j][i]; 721 722 data->sc = sc; /* Backpointer for callbacks. */ 723 724 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 725 0, 0, &data->xfer); 726 if (error) { 727 aprint_error_dev(sc->sc_dev, 728 "could not allocate xfer\n"); 729 break; 730 } 731 732 data->buf = usbd_get_buffer(data->xfer); 733 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 734 } 735 } 736 if (error != 0) 737 urtwn_free_rx_list(sc); 738 return error; 739 } 740 741 static void 742 urtwn_free_rx_list(struct urtwn_softc *sc) 743 { 744 struct usbd_xfer *xfer; 745 size_t i; 746 747 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 748 749 /* NB: Caller must abort pipe first. */ 750 for (size_t j = 0; j < sc->rx_npipe; j++) { 751 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 752 CTASSERT(sizeof(xfer) == sizeof(void *)); 753 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 754 if (xfer != NULL) 755 usbd_destroy_xfer(xfer); 756 } 757 } 758 } 759 760 static int 761 urtwn_alloc_tx_list(struct urtwn_softc *sc) 762 { 763 struct urtwn_tx_data *data; 764 size_t i; 765 int error = 0; 766 767 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 768 769 mutex_enter(&sc->sc_tx_mtx); 770 for (size_t j = 0; j < sc->tx_npipe; j++) { 771 TAILQ_INIT(&sc->tx_free_list[j]); 772 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 773 data = &sc->tx_data[j][i]; 774 775 data->sc = sc; /* Backpointer for callbacks. */ 776 data->pidx = j; 777 778 error = usbd_create_xfer(sc->tx_pipe[j], 779 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 780 &data->xfer); 781 if (error) { 782 aprint_error_dev(sc->sc_dev, 783 "could not allocate xfer\n"); 784 goto fail; 785 } 786 787 data->buf = usbd_get_buffer(data->xfer); 788 789 /* Append this Tx buffer to our free list. */ 790 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 791 } 792 } 793 mutex_exit(&sc->sc_tx_mtx); 794 return 0; 795 796 fail: 797 urtwn_free_tx_list(sc); 798 mutex_exit(&sc->sc_tx_mtx); 799 return error; 800 } 801 802 static void 803 urtwn_free_tx_list(struct urtwn_softc *sc) 804 { 805 struct usbd_xfer *xfer; 806 size_t i; 807 808 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 809 810 /* NB: Caller must abort pipe first. */ 811 for (size_t j = 0; j < sc->tx_npipe; j++) { 812 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 813 CTASSERT(sizeof(xfer) == sizeof(void *)); 814 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 815 if (xfer != NULL) 816 usbd_destroy_xfer(xfer); 817 } 818 } 819 } 820 821 static int 822 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 823 struct ieee80211_node *ni) 824 { 825 struct urtwn_tx_data *data = 826 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 827 return urtwn_tx(sc, m, ni, data); 828 } 829 830 static void 831 urtwn_task(void *arg) 832 { 833 struct urtwn_softc *sc = arg; 834 struct ieee80211com *ic = &sc->sc_ic; 835 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 836 struct urtwn_host_cmd *cmd; 837 int s; 838 839 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 840 if (ic->ic_state == IEEE80211_S_RUN && 841 (ic->ic_opmode == IEEE80211_M_HOSTAP || 842 ic->ic_opmode == IEEE80211_M_IBSS)) { 843 844 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 845 &sc->sc_bo); 846 if (m == NULL) { 847 aprint_error_dev(sc->sc_dev, 848 "could not allocate beacon"); 849 } 850 851 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 852 m_freem(m); 853 aprint_error_dev(sc->sc_dev, "could not send beacon"); 854 } 855 856 /* beacon is no longer needed */ 857 m_freem(m); 858 } 859 860 /* Process host commands. */ 861 s = splusb(); 862 mutex_spin_enter(&sc->sc_task_mtx); 863 while (ring->next != ring->cur) { 864 cmd = &ring->cmd[ring->next]; 865 mutex_spin_exit(&sc->sc_task_mtx); 866 splx(s); 867 /* Invoke callback with kernel lock held. */ 868 cmd->cb(sc, cmd->data); 869 s = splusb(); 870 mutex_spin_enter(&sc->sc_task_mtx); 871 ring->queued--; 872 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 873 } 874 mutex_spin_exit(&sc->sc_task_mtx); 875 wakeup(&sc->cmdq); 876 splx(s); 877 } 878 879 static void 880 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 881 void *arg, int len) 882 { 883 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 884 struct urtwn_host_cmd *cmd; 885 int s; 886 887 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 888 device_xname(sc->sc_dev), __func__, cb, arg, len)); 889 890 s = splusb(); 891 mutex_spin_enter(&sc->sc_task_mtx); 892 cmd = &ring->cmd[ring->cur]; 893 cmd->cb = cb; 894 KASSERT(len <= sizeof(cmd->data)); 895 memcpy(cmd->data, arg, len); 896 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 897 898 /* If there is no pending command already, schedule a task. */ 899 if (!sc->sc_dying && ++ring->queued == 1) { 900 mutex_spin_exit(&sc->sc_task_mtx); 901 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 902 } else 903 mutex_spin_exit(&sc->sc_task_mtx); 904 splx(s); 905 } 906 907 static void 908 urtwn_wait_async(struct urtwn_softc *sc) 909 { 910 911 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 912 913 /* Wait for all queued asynchronous commands to complete. */ 914 while (sc->cmdq.queued > 0) 915 tsleep(&sc->cmdq, 0, "endtask", 0); 916 } 917 918 static int 919 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 920 int len) 921 { 922 usb_device_request_t req; 923 usbd_status error; 924 925 KASSERT(mutex_owned(&sc->sc_write_mtx)); 926 927 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 928 req.bRequest = R92C_REQ_REGS; 929 USETW(req.wValue, addr); 930 USETW(req.wIndex, 0); 931 USETW(req.wLength, len); 932 error = usbd_do_request(sc->sc_udev, &req, buf); 933 if (error != USBD_NORMAL_COMPLETION) { 934 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 935 device_xname(sc->sc_dev), __func__, error, addr, len)); 936 } 937 return error; 938 } 939 940 static void 941 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 942 { 943 944 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 945 device_xname(sc->sc_dev), __func__, addr, val)); 946 947 urtwn_write_region_1(sc, addr, &val, 1); 948 } 949 950 static void 951 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 952 { 953 uint8_t buf[2]; 954 955 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 956 device_xname(sc->sc_dev), __func__, addr, val)); 957 958 buf[0] = (uint8_t)val; 959 buf[1] = (uint8_t)(val >> 8); 960 urtwn_write_region_1(sc, addr, buf, 2); 961 } 962 963 static void 964 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 965 { 966 uint8_t buf[4]; 967 968 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 969 device_xname(sc->sc_dev), __func__, addr, val)); 970 971 buf[0] = (uint8_t)val; 972 buf[1] = (uint8_t)(val >> 8); 973 buf[2] = (uint8_t)(val >> 16); 974 buf[3] = (uint8_t)(val >> 24); 975 urtwn_write_region_1(sc, addr, buf, 4); 976 } 977 978 static int 979 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 980 { 981 982 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 983 device_xname(sc->sc_dev), __func__, addr, len)); 984 985 return urtwn_write_region_1(sc, addr, buf, len); 986 } 987 988 static int 989 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 990 int len) 991 { 992 usb_device_request_t req; 993 usbd_status error; 994 995 req.bmRequestType = UT_READ_VENDOR_DEVICE; 996 req.bRequest = R92C_REQ_REGS; 997 USETW(req.wValue, addr); 998 USETW(req.wIndex, 0); 999 USETW(req.wLength, len); 1000 error = usbd_do_request(sc->sc_udev, &req, buf); 1001 if (error != USBD_NORMAL_COMPLETION) { 1002 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1003 device_xname(sc->sc_dev), __func__, error, addr, len)); 1004 } 1005 return error; 1006 } 1007 1008 static uint8_t 1009 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1010 { 1011 uint8_t val; 1012 1013 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1014 return 0xff; 1015 1016 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1017 device_xname(sc->sc_dev), __func__, addr, val)); 1018 return val; 1019 } 1020 1021 static uint16_t 1022 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1023 { 1024 uint8_t buf[2]; 1025 uint16_t val; 1026 1027 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1028 return 0xffff; 1029 1030 val = LE_READ_2(&buf[0]); 1031 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1032 device_xname(sc->sc_dev), __func__, addr, val)); 1033 return val; 1034 } 1035 1036 static uint32_t 1037 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1038 { 1039 uint8_t buf[4]; 1040 uint32_t val; 1041 1042 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1043 return 0xffffffff; 1044 1045 val = LE_READ_4(&buf[0]); 1046 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1047 device_xname(sc->sc_dev), __func__, addr, val)); 1048 return val; 1049 } 1050 1051 static int 1052 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1053 { 1054 struct r92c_fw_cmd cmd; 1055 uint8_t *cp; 1056 int fwcur; 1057 int ntries; 1058 1059 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1060 device_xname(sc->sc_dev), __func__, id, buf, len)); 1061 1062 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1063 1064 mutex_enter(&sc->sc_fwcmd_mtx); 1065 fwcur = sc->fwcur; 1066 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1067 mutex_exit(&sc->sc_fwcmd_mtx); 1068 1069 /* Wait for current FW box to be empty. */ 1070 for (ntries = 0; ntries < 100; ntries++) { 1071 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1072 break; 1073 DELAY(2000); 1074 } 1075 if (ntries == 100) { 1076 aprint_error_dev(sc->sc_dev, 1077 "could not send firmware command %d\n", id); 1078 return ETIMEDOUT; 1079 } 1080 1081 memset(&cmd, 0, sizeof(cmd)); 1082 KASSERT(len <= sizeof(cmd.msg)); 1083 memcpy(cmd.msg, buf, len); 1084 1085 /* Write the first word last since that will trigger the FW. */ 1086 cp = (uint8_t *)&cmd; 1087 cmd.id = id; 1088 if (len >= 4) { 1089 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1090 cmd.id |= R92C_CMD_FLAG_EXT; 1091 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1092 &cp[1], 2); 1093 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1094 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1095 (cp[5] << 24)); 1096 } else { 1097 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1098 &cp[4], 2); 1099 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1100 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1101 (cp[3] << 24)); 1102 } 1103 } else { 1104 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1105 } 1106 1107 return 0; 1108 } 1109 1110 static __inline void 1111 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1112 { 1113 1114 sc->sc_rf_write(sc, chain, addr, val); 1115 } 1116 1117 static void 1118 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1119 uint32_t val) 1120 { 1121 1122 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1123 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1124 } 1125 1126 static void 1127 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1128 uint32_t val) 1129 { 1130 1131 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1132 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1133 } 1134 1135 static void 1136 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1137 uint32_t val) 1138 { 1139 1140 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1141 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1142 } 1143 1144 static uint32_t 1145 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1146 { 1147 uint32_t reg[R92C_MAX_CHAINS], val; 1148 1149 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1150 if (chain != 0) { 1151 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1152 } 1153 1154 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1155 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1156 DELAY(1000); 1157 1158 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1159 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1160 R92C_HSSI_PARAM2_READ_EDGE); 1161 DELAY(1000); 1162 1163 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1164 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1165 DELAY(1000); 1166 1167 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1168 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1169 } else { 1170 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1171 } 1172 return MS(val, R92C_LSSI_READBACK_DATA); 1173 } 1174 1175 static int 1176 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1177 { 1178 int ntries; 1179 1180 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1181 1182 urtwn_write_4(sc, R92C_LLT_INIT, 1183 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1184 SM(R92C_LLT_INIT_ADDR, addr) | 1185 SM(R92C_LLT_INIT_DATA, data)); 1186 /* Wait for write operation to complete. */ 1187 for (ntries = 0; ntries < 20; ntries++) { 1188 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1189 R92C_LLT_INIT_OP_NO_ACTIVE) { 1190 /* Done */ 1191 return 0; 1192 } 1193 DELAY(5); 1194 } 1195 return ETIMEDOUT; 1196 } 1197 1198 static uint8_t 1199 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1200 { 1201 uint32_t reg; 1202 int ntries; 1203 1204 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1205 1206 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1207 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1208 reg &= ~R92C_EFUSE_CTRL_VALID; 1209 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1210 1211 /* Wait for read operation to complete. */ 1212 for (ntries = 0; ntries < 100; ntries++) { 1213 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1214 if (reg & R92C_EFUSE_CTRL_VALID) { 1215 /* Done */ 1216 return MS(reg, R92C_EFUSE_CTRL_DATA); 1217 } 1218 DELAY(5); 1219 } 1220 aprint_error_dev(sc->sc_dev, 1221 "could not read efuse byte at address 0x%04x\n", addr); 1222 return 0xff; 1223 } 1224 1225 static void 1226 urtwn_efuse_read(struct urtwn_softc *sc) 1227 { 1228 uint8_t *rom = (uint8_t *)&sc->rom; 1229 uint32_t reg; 1230 uint16_t addr = 0; 1231 uint8_t off, msk; 1232 size_t i; 1233 1234 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1235 1236 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1237 1238 urtwn_efuse_switch_power(sc); 1239 1240 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1241 while (addr < 512) { 1242 reg = urtwn_efuse_read_1(sc, addr); 1243 if (reg == 0xff) 1244 break; 1245 addr++; 1246 off = reg >> 4; 1247 msk = reg & 0xf; 1248 for (i = 0; i < 4; i++) { 1249 if (msk & (1U << i)) 1250 continue; 1251 1252 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1253 addr++; 1254 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1255 addr++; 1256 } 1257 } 1258 #ifdef URTWN_DEBUG 1259 if (urtwn_debug & DBG_INIT) { 1260 /* Dump ROM content. */ 1261 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1262 for (i = 0; i < (int)sizeof(sc->rom); i++) 1263 printf(":%02x", rom[i]); 1264 printf("\n"); 1265 } 1266 #endif 1267 } 1268 1269 static void 1270 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1271 { 1272 uint32_t reg; 1273 1274 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1275 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1276 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1277 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1278 } 1279 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1280 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1281 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1282 reg | R92C_SYS_FUNC_EN_ELDR); 1283 } 1284 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1285 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1286 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1287 urtwn_write_2(sc, R92C_SYS_CLKR, 1288 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1289 } 1290 } 1291 1292 static int 1293 urtwn_read_chipid(struct urtwn_softc *sc) 1294 { 1295 uint32_t reg; 1296 1297 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1298 1299 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1300 ISSET(sc->chip, URTWN_CHIP_92EU)) 1301 return 0; 1302 1303 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1304 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1305 /* test chip, not supported */ 1306 return EIO; 1307 } 1308 if (reg & R92C_SYS_CFG_TYPE_92C) { 1309 sc->chip |= URTWN_CHIP_92C; 1310 /* Check if it is a castrated 8192C. */ 1311 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1312 R92C_HPON_FSM_CHIP_BONDING_ID) == 1313 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1314 sc->chip |= URTWN_CHIP_92C_1T2R; 1315 } 1316 } 1317 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1318 sc->chip |= URTWN_CHIP_UMC; 1319 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1320 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1321 } 1322 } 1323 return 0; 1324 } 1325 1326 #ifdef URTWN_DEBUG 1327 static void 1328 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1329 { 1330 1331 aprint_normal_dev(sc->sc_dev, 1332 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1333 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1334 1335 aprint_normal_dev(sc->sc_dev, 1336 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1337 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1338 1339 aprint_normal_dev(sc->sc_dev, 1340 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1341 rp->macaddr[0], rp->macaddr[1], 1342 rp->macaddr[2], rp->macaddr[3], 1343 rp->macaddr[4], rp->macaddr[5]); 1344 1345 aprint_normal_dev(sc->sc_dev, 1346 "string %s, subcustomer_id 0x%x\n", 1347 rp->string, rp->subcustomer_id); 1348 1349 aprint_normal_dev(sc->sc_dev, 1350 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1351 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1352 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1353 1354 aprint_normal_dev(sc->sc_dev, 1355 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1356 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1357 rp->ht40_1s_tx_pwr[0][2], 1358 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1359 rp->ht40_1s_tx_pwr[1][2]); 1360 1361 aprint_normal_dev(sc->sc_dev, 1362 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1363 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1364 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1365 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1366 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1367 1368 aprint_normal_dev(sc->sc_dev, 1369 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1370 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1371 rp->ht20_tx_pwr_diff[2] & 0xf, 1372 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1373 rp->ht20_tx_pwr_diff[2] >> 4); 1374 1375 aprint_normal_dev(sc->sc_dev, 1376 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1377 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1378 rp->ofdm_tx_pwr_diff[2] & 0xf, 1379 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1380 rp->ofdm_tx_pwr_diff[2] >> 4); 1381 1382 aprint_normal_dev(sc->sc_dev, 1383 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1384 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1385 rp->ht40_max_pwr[2] & 0xf, 1386 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1387 rp->ht40_max_pwr[2] >> 4); 1388 1389 aprint_normal_dev(sc->sc_dev, 1390 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1391 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1392 rp->ht20_max_pwr[2] & 0xf, 1393 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1394 rp->ht20_max_pwr[2] >> 4); 1395 1396 aprint_normal_dev(sc->sc_dev, 1397 "xtal_calib %d, tssi %d %d, thermal %d\n", 1398 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1399 1400 aprint_normal_dev(sc->sc_dev, 1401 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1402 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1403 1404 aprint_normal_dev(sc->sc_dev, 1405 "channnel_plan %d, version %d customer_id 0x%x\n", 1406 rp->channel_plan, rp->version, rp->curstomer_id); 1407 } 1408 #endif 1409 1410 static void 1411 urtwn_read_rom(struct urtwn_softc *sc) 1412 { 1413 struct ieee80211com *ic = &sc->sc_ic; 1414 struct r92c_rom *rom = &sc->rom; 1415 1416 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1417 1418 mutex_enter(&sc->sc_write_mtx); 1419 1420 /* Read full ROM image. */ 1421 urtwn_efuse_read(sc); 1422 #ifdef URTWN_DEBUG 1423 if (urtwn_debug & DBG_REG) 1424 urtwn_dump_rom(sc, rom); 1425 #endif 1426 1427 /* XXX Weird but this is what the vendor driver does. */ 1428 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1429 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1430 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1431 1432 DPRINTFN(DBG_INIT, 1433 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1434 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1435 sc->board_type, sc->regulatory)); 1436 1437 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1438 1439 sc->sc_rf_write = urtwn_r92c_rf_write; 1440 sc->sc_power_on = urtwn_r92c_power_on; 1441 sc->sc_dma_init = urtwn_r92c_dma_init; 1442 1443 mutex_exit(&sc->sc_write_mtx); 1444 } 1445 1446 static void 1447 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1448 { 1449 struct ieee80211com *ic = &sc->sc_ic; 1450 uint8_t *rom = sc->r88e_rom; 1451 uint32_t reg; 1452 uint16_t addr = 0; 1453 uint8_t off, msk, tmp; 1454 int i; 1455 1456 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1457 1458 mutex_enter(&sc->sc_write_mtx); 1459 1460 off = 0; 1461 urtwn_efuse_switch_power(sc); 1462 1463 /* Read full ROM image. */ 1464 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1465 while (addr < 4096) { 1466 reg = urtwn_efuse_read_1(sc, addr); 1467 if (reg == 0xff) 1468 break; 1469 addr++; 1470 if ((reg & 0x1f) == 0x0f) { 1471 tmp = (reg & 0xe0) >> 5; 1472 reg = urtwn_efuse_read_1(sc, addr); 1473 if ((reg & 0x0f) != 0x0f) 1474 off = ((reg & 0xf0) >> 1) | tmp; 1475 addr++; 1476 } else 1477 off = reg >> 4; 1478 msk = reg & 0xf; 1479 for (i = 0; i < 4; i++) { 1480 if (msk & (1 << i)) 1481 continue; 1482 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1483 addr++; 1484 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1485 addr++; 1486 } 1487 } 1488 #ifdef URTWN_DEBUG 1489 if (urtwn_debug & DBG_REG) { 1490 } 1491 #endif 1492 1493 addr = 0x10; 1494 for (i = 0; i < 6; i++) 1495 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1496 for (i = 0; i < 5; i++) 1497 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1498 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1499 if (sc->bw20_tx_pwr_diff & 0x08) 1500 sc->bw20_tx_pwr_diff |= 0xf0; 1501 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1502 if (sc->ofdm_tx_pwr_diff & 0x08) 1503 sc->ofdm_tx_pwr_diff |= 0xf0; 1504 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1505 1506 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1507 1508 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1509 sc->sc_power_on = urtwn_r92e_power_on; 1510 sc->sc_rf_write = urtwn_r92e_rf_write; 1511 } else { 1512 sc->sc_power_on = urtwn_r88e_power_on; 1513 sc->sc_rf_write = urtwn_r88e_rf_write; 1514 } 1515 sc->sc_dma_init = urtwn_r88e_dma_init; 1516 1517 mutex_exit(&sc->sc_write_mtx); 1518 } 1519 1520 static int 1521 urtwn_media_change(struct ifnet *ifp) 1522 { 1523 #ifdef URTWN_DEBUG 1524 struct urtwn_softc *sc = ifp->if_softc; 1525 #endif 1526 int error; 1527 1528 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1529 1530 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1531 return error; 1532 1533 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1534 (IFF_UP | IFF_RUNNING)) { 1535 urtwn_init(ifp); 1536 } 1537 return 0; 1538 } 1539 1540 /* 1541 * Initialize rate adaptation in firmware. 1542 */ 1543 static int 1544 urtwn_ra_init(struct urtwn_softc *sc) 1545 { 1546 static const uint8_t map[] = { 1547 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1548 }; 1549 struct ieee80211com *ic = &sc->sc_ic; 1550 struct ieee80211_node *ni = ic->ic_bss; 1551 struct ieee80211_rateset *rs = &ni->ni_rates; 1552 struct r92c_fw_cmd_macid_cfg cmd; 1553 uint32_t rates, basicrates; 1554 uint32_t rrsr_mask, rrsr_rate; 1555 uint8_t mode; 1556 size_t maxrate, maxbasicrate, i, j; 1557 int error; 1558 1559 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1560 1561 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1562 1563 /* Get normal and basic rates mask. */ 1564 rates = basicrates = 1; 1565 maxrate = maxbasicrate = 0; 1566 for (i = 0; i < rs->rs_nrates; i++) { 1567 /* Convert 802.11 rate to HW rate index. */ 1568 for (j = 0; j < __arraycount(map); j++) { 1569 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1570 break; 1571 } 1572 } 1573 if (j == __arraycount(map)) { 1574 /* Unknown rate, skip. */ 1575 continue; 1576 } 1577 1578 rates |= 1U << j; 1579 if (j > maxrate) { 1580 maxrate = j; 1581 } 1582 1583 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1584 basicrates |= 1U << j; 1585 if (j > maxbasicrate) { 1586 maxbasicrate = j; 1587 } 1588 } 1589 } 1590 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1591 mode = R92C_RAID_11B; 1592 } else { 1593 mode = R92C_RAID_11BG; 1594 } 1595 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1596 "maxrate=%zx, maxbasicrate=%zx\n", 1597 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1598 maxrate, maxbasicrate)); 1599 1600 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1601 maxbasicrate |= R92C_RATE_SHORTGI; 1602 maxrate |= R92C_RATE_SHORTGI; 1603 } 1604 1605 /* Set rates mask for group addressed frames. */ 1606 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1607 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1608 cmd.macid |= RTWN_MACID_SHORTGI; 1609 cmd.mask = htole32((mode << 28) | basicrates); 1610 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1611 if (error != 0) { 1612 aprint_error_dev(sc->sc_dev, 1613 "could not add broadcast station\n"); 1614 return error; 1615 } 1616 /* Set initial MRR rate. */ 1617 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1618 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1619 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1620 1621 /* Set rates mask for unicast frames. */ 1622 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1623 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1624 cmd.macid |= RTWN_MACID_SHORTGI; 1625 cmd.mask = htole32((mode << 28) | rates); 1626 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1627 if (error != 0) { 1628 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1629 return error; 1630 } 1631 /* Set initial MRR rate. */ 1632 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1633 __func__, maxrate)); 1634 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1635 1636 rrsr_rate = ic->ic_fixed_rate; 1637 if (rrsr_rate == -1) 1638 rrsr_rate = 11; 1639 1640 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1641 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1642 1643 /* Indicate highest supported rate. */ 1644 ni->ni_txrate = rs->rs_nrates - 1; 1645 1646 return 0; 1647 } 1648 1649 static int 1650 urtwn_get_nettype(struct urtwn_softc *sc) 1651 { 1652 struct ieee80211com *ic = &sc->sc_ic; 1653 int type; 1654 1655 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1656 1657 switch (ic->ic_opmode) { 1658 case IEEE80211_M_STA: 1659 type = R92C_CR_NETTYPE_INFRA; 1660 break; 1661 1662 case IEEE80211_M_IBSS: 1663 type = R92C_CR_NETTYPE_ADHOC; 1664 break; 1665 1666 default: 1667 type = R92C_CR_NETTYPE_NOLINK; 1668 break; 1669 } 1670 1671 return type; 1672 } 1673 1674 static void 1675 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1676 { 1677 uint8_t reg; 1678 1679 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1680 __func__, type)); 1681 1682 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1683 1684 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1685 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1686 } 1687 1688 static void 1689 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1690 { 1691 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1692 uint64_t tsf; 1693 1694 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1695 1696 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1697 1698 /* Enable TSF synchronization. */ 1699 urtwn_write_1(sc, R92C_BCN_CTRL, 1700 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1701 1702 /* Correct TSF */ 1703 urtwn_write_1(sc, R92C_BCN_CTRL, 1704 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1705 1706 /* Set initial TSF. */ 1707 tsf = ni->ni_tstamp.tsf; 1708 tsf = le64toh(tsf); 1709 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1710 tsf -= IEEE80211_DUR_TU; 1711 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1712 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1713 1714 urtwn_write_1(sc, R92C_BCN_CTRL, 1715 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1716 } 1717 1718 static void 1719 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1720 { 1721 uint8_t reg; 1722 1723 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1724 __func__, led, on)); 1725 1726 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1727 1728 if (led == URTWN_LED_LINK) { 1729 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1730 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1731 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1732 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1733 (R92C_LEDCFG0_DIS << 1)); 1734 if (on) { 1735 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1736 R92E_LEDSON; 1737 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1738 } 1739 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1740 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1741 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1742 if (!on) { 1743 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1744 urtwn_write_1(sc, R92C_LEDCFG2, 1745 reg | R92C_LEDCFG0_DIS); 1746 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1747 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1748 reg & 0xfe); 1749 } 1750 } else { 1751 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1752 if (!on) { 1753 reg |= R92C_LEDCFG0_DIS; 1754 } 1755 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1756 } 1757 sc->ledlink = on; /* Save LED state. */ 1758 } 1759 } 1760 1761 static void 1762 urtwn_calib_to(void *arg) 1763 { 1764 struct urtwn_softc *sc = arg; 1765 1766 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1767 1768 if (sc->sc_dying) 1769 return; 1770 1771 /* Do it in a process context. */ 1772 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1773 } 1774 1775 /* ARGSUSED */ 1776 static void 1777 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1778 { 1779 struct r92c_fw_cmd_rssi cmd; 1780 struct r92e_fw_cmd_rssi cmde; 1781 1782 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1783 1784 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1785 goto restart_timer; 1786 1787 mutex_enter(&sc->sc_write_mtx); 1788 if (sc->avg_pwdb != -1) { 1789 /* Indicate Rx signal strength to FW for rate adaptation. */ 1790 memset(&cmd, 0, sizeof(cmd)); 1791 memset(&cmde, 0, sizeof(cmde)); 1792 cmd.macid = 0; /* BSS. */ 1793 cmde.macid = 0; /* BSS. */ 1794 cmd.pwdb = sc->avg_pwdb; 1795 cmde.pwdb = sc->avg_pwdb; 1796 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1797 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1798 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1799 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1800 sizeof(cmd)); 1801 } else { 1802 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1803 sizeof(cmde)); 1804 } 1805 } 1806 1807 /* Do temperature compensation. */ 1808 urtwn_temp_calib(sc); 1809 mutex_exit(&sc->sc_write_mtx); 1810 1811 restart_timer: 1812 if (!sc->sc_dying) { 1813 /* Restart calibration timer. */ 1814 callout_schedule(&sc->sc_calib_to, hz); 1815 } 1816 } 1817 1818 static void 1819 urtwn_next_scan(void *arg) 1820 { 1821 struct urtwn_softc *sc = arg; 1822 int s; 1823 1824 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1825 1826 if (sc->sc_dying) 1827 return; 1828 1829 s = splnet(); 1830 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1831 ieee80211_next_scan(&sc->sc_ic); 1832 splx(s); 1833 } 1834 1835 static void 1836 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1837 { 1838 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1839 ether_sprintf(ni->ni_macaddr))); 1840 /* start with lowest Tx rate */ 1841 ni->ni_txrate = 0; 1842 } 1843 1844 static int 1845 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1846 { 1847 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1848 struct urtwn_cmd_newstate cmd; 1849 1850 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1851 device_xname(sc->sc_dev), __func__, 1852 ieee80211_state_name[nstate], nstate, arg)); 1853 1854 callout_stop(&sc->sc_scan_to); 1855 callout_stop(&sc->sc_calib_to); 1856 1857 /* Do it in a process context. */ 1858 cmd.state = nstate; 1859 cmd.arg = arg; 1860 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1861 return 0; 1862 } 1863 1864 static void 1865 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1866 { 1867 struct urtwn_cmd_newstate *cmd = arg; 1868 struct ieee80211com *ic = &sc->sc_ic; 1869 struct ieee80211_node *ni; 1870 enum ieee80211_state ostate = ic->ic_state; 1871 enum ieee80211_state nstate = cmd->state; 1872 uint32_t reg; 1873 uint8_t sifs_time, msr; 1874 int s; 1875 1876 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1877 device_xname(sc->sc_dev), __func__, 1878 ieee80211_state_name[ostate], ostate, 1879 ieee80211_state_name[nstate], nstate)); 1880 1881 s = splnet(); 1882 mutex_enter(&sc->sc_write_mtx); 1883 1884 callout_stop(&sc->sc_scan_to); 1885 callout_stop(&sc->sc_calib_to); 1886 1887 switch (ostate) { 1888 case IEEE80211_S_INIT: 1889 break; 1890 1891 case IEEE80211_S_SCAN: 1892 if (nstate != IEEE80211_S_SCAN) { 1893 /* 1894 * End of scanning 1895 */ 1896 /* flush 4-AC Queue after site_survey */ 1897 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1898 1899 /* Allow Rx from our BSSID only. */ 1900 urtwn_write_4(sc, R92C_RCR, 1901 urtwn_read_4(sc, R92C_RCR) | 1902 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1903 } 1904 break; 1905 1906 case IEEE80211_S_AUTH: 1907 case IEEE80211_S_ASSOC: 1908 break; 1909 1910 case IEEE80211_S_RUN: 1911 /* Turn link LED off. */ 1912 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1913 1914 /* Set media status to 'No Link'. */ 1915 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1916 1917 /* Stop Rx of data frames. */ 1918 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1919 1920 /* Reset TSF. */ 1921 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1922 1923 /* Disable TSF synchronization. */ 1924 urtwn_write_1(sc, R92C_BCN_CTRL, 1925 urtwn_read_1(sc, R92C_BCN_CTRL) | 1926 R92C_BCN_CTRL_DIS_TSF_UDT0); 1927 1928 /* Back to 20MHz mode */ 1929 urtwn_set_chan(sc, ic->ic_curchan, 1930 IEEE80211_HTINFO_2NDCHAN_NONE); 1931 1932 if (ic->ic_opmode == IEEE80211_M_IBSS || 1933 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1934 /* Stop BCN */ 1935 urtwn_write_1(sc, R92C_BCN_CTRL, 1936 urtwn_read_1(sc, R92C_BCN_CTRL) & 1937 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1938 } 1939 1940 /* Reset EDCA parameters. */ 1941 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1942 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1943 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1944 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1945 1946 /* flush all cam entries */ 1947 urtwn_cam_init(sc); 1948 break; 1949 } 1950 1951 switch (nstate) { 1952 case IEEE80211_S_INIT: 1953 /* Turn link LED off. */ 1954 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1955 break; 1956 1957 case IEEE80211_S_SCAN: 1958 if (ostate != IEEE80211_S_SCAN) { 1959 /* 1960 * Begin of scanning 1961 */ 1962 1963 /* Set gain for scanning. */ 1964 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1965 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1966 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1967 1968 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1969 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1970 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1971 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1972 } 1973 1974 /* Set media status to 'No Link'. */ 1975 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1976 1977 /* Allow Rx from any BSSID. */ 1978 urtwn_write_4(sc, R92C_RCR, 1979 urtwn_read_4(sc, R92C_RCR) & 1980 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1981 1982 /* Stop Rx of data frames. */ 1983 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1984 1985 /* Disable update TSF */ 1986 urtwn_write_1(sc, R92C_BCN_CTRL, 1987 urtwn_read_1(sc, R92C_BCN_CTRL) | 1988 R92C_BCN_CTRL_DIS_TSF_UDT0); 1989 } 1990 1991 /* Make link LED blink during scan. */ 1992 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1993 1994 /* Pause AC Tx queues. */ 1995 urtwn_write_1(sc, R92C_TXPAUSE, 1996 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1997 1998 urtwn_set_chan(sc, ic->ic_curchan, 1999 IEEE80211_HTINFO_2NDCHAN_NONE); 2000 2001 /* Start periodic scan. */ 2002 if (!sc->sc_dying) 2003 callout_schedule(&sc->sc_scan_to, hz / 5); 2004 break; 2005 2006 case IEEE80211_S_AUTH: 2007 /* Set initial gain under link. */ 2008 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2009 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2010 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2011 2012 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2013 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2014 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2015 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2016 } 2017 2018 /* Set media status to 'No Link'. */ 2019 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2020 2021 /* Allow Rx from any BSSID. */ 2022 urtwn_write_4(sc, R92C_RCR, 2023 urtwn_read_4(sc, R92C_RCR) & 2024 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2025 2026 urtwn_set_chan(sc, ic->ic_curchan, 2027 IEEE80211_HTINFO_2NDCHAN_NONE); 2028 break; 2029 2030 case IEEE80211_S_ASSOC: 2031 break; 2032 2033 case IEEE80211_S_RUN: 2034 ni = ic->ic_bss; 2035 2036 /* XXX: Set 20MHz mode */ 2037 urtwn_set_chan(sc, ic->ic_curchan, 2038 IEEE80211_HTINFO_2NDCHAN_NONE); 2039 2040 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2041 /* Back to 20MHz mode */ 2042 urtwn_set_chan(sc, ic->ic_curchan, 2043 IEEE80211_HTINFO_2NDCHAN_NONE); 2044 2045 /* Set media status to 'No Link'. */ 2046 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2047 2048 /* Enable Rx of data frames. */ 2049 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2050 2051 /* Allow Rx from any BSSID. */ 2052 urtwn_write_4(sc, R92C_RCR, 2053 urtwn_read_4(sc, R92C_RCR) & 2054 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2055 2056 /* Accept Rx data/control/management frames */ 2057 urtwn_write_4(sc, R92C_RCR, 2058 urtwn_read_4(sc, R92C_RCR) | 2059 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2060 2061 /* Turn link LED on. */ 2062 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2063 break; 2064 } 2065 2066 /* Set media status to 'Associated'. */ 2067 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2068 2069 /* Set BSSID. */ 2070 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2071 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2072 2073 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2074 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2075 } else { 2076 /* 802.11b/g */ 2077 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2078 } 2079 2080 /* Enable Rx of data frames. */ 2081 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2082 2083 /* Set beacon interval. */ 2084 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2085 2086 msr = urtwn_read_1(sc, R92C_MSR); 2087 msr &= R92C_MSR_MASK; 2088 switch (ic->ic_opmode) { 2089 case IEEE80211_M_STA: 2090 /* Allow Rx from our BSSID only. */ 2091 urtwn_write_4(sc, R92C_RCR, 2092 urtwn_read_4(sc, R92C_RCR) | 2093 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2094 2095 /* Enable TSF synchronization. */ 2096 urtwn_tsf_sync_enable(sc); 2097 2098 msr |= R92C_MSR_INFRA; 2099 break; 2100 case IEEE80211_M_HOSTAP: 2101 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2102 2103 /* Allow Rx from any BSSID. */ 2104 urtwn_write_4(sc, R92C_RCR, 2105 urtwn_read_4(sc, R92C_RCR) & 2106 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2107 2108 /* Reset TSF timer to zero. */ 2109 reg = urtwn_read_4(sc, R92C_TCR); 2110 reg &= ~0x01; 2111 urtwn_write_4(sc, R92C_TCR, reg); 2112 reg |= 0x01; 2113 urtwn_write_4(sc, R92C_TCR, reg); 2114 2115 msr |= R92C_MSR_AP; 2116 break; 2117 default: 2118 msr |= R92C_MSR_ADHOC; 2119 break; 2120 } 2121 urtwn_write_1(sc, R92C_MSR, msr); 2122 2123 sifs_time = 10; 2124 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2125 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2126 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2127 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2128 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2129 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2130 2131 /* Initialize rate adaptation. */ 2132 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2133 ISSET(sc->chip, URTWN_CHIP_92EU)) 2134 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2135 else 2136 urtwn_ra_init(sc); 2137 2138 /* Turn link LED on. */ 2139 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2140 2141 /* Reset average RSSI. */ 2142 sc->avg_pwdb = -1; 2143 2144 /* Reset temperature calibration state machine. */ 2145 sc->thcal_state = 0; 2146 sc->thcal_lctemp = 0; 2147 2148 /* Start periodic calibration. */ 2149 if (!sc->sc_dying) 2150 callout_schedule(&sc->sc_calib_to, hz); 2151 break; 2152 } 2153 2154 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2155 2156 mutex_exit(&sc->sc_write_mtx); 2157 splx(s); 2158 } 2159 2160 static int 2161 urtwn_wme_update(struct ieee80211com *ic) 2162 { 2163 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2164 2165 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2166 2167 /* don't override default WME values if WME is not actually enabled */ 2168 if (!(ic->ic_flags & IEEE80211_F_WME)) 2169 return 0; 2170 2171 /* Do it in a process context. */ 2172 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2173 return 0; 2174 } 2175 2176 static void 2177 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2178 { 2179 static const uint16_t ac2reg[WME_NUM_AC] = { 2180 R92C_EDCA_BE_PARAM, 2181 R92C_EDCA_BK_PARAM, 2182 R92C_EDCA_VI_PARAM, 2183 R92C_EDCA_VO_PARAM 2184 }; 2185 struct ieee80211com *ic = &sc->sc_ic; 2186 const struct wmeParams *wmep; 2187 int ac, aifs, slottime; 2188 int s; 2189 2190 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2191 __func__)); 2192 2193 s = splnet(); 2194 mutex_enter(&sc->sc_write_mtx); 2195 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2196 for (ac = 0; ac < WME_NUM_AC; ac++) { 2197 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2198 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2199 aifs = wmep->wmep_aifsn * slottime + 10; 2200 urtwn_write_4(sc, ac2reg[ac], 2201 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2202 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2203 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2204 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2205 } 2206 mutex_exit(&sc->sc_write_mtx); 2207 splx(s); 2208 } 2209 2210 static void 2211 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2212 { 2213 int pwdb; 2214 2215 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2216 device_xname(sc->sc_dev), __func__, rate, rssi)); 2217 2218 /* Convert antenna signal to percentage. */ 2219 if (rssi <= -100 || rssi >= 20) 2220 pwdb = 0; 2221 else if (rssi >= 0) 2222 pwdb = 100; 2223 else 2224 pwdb = 100 + rssi; 2225 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2226 if (rate <= 3) { 2227 /* CCK gain is smaller than OFDM/MCS gain. */ 2228 pwdb += 6; 2229 if (pwdb > 100) 2230 pwdb = 100; 2231 if (pwdb <= 14) 2232 pwdb -= 4; 2233 else if (pwdb <= 26) 2234 pwdb -= 8; 2235 else if (pwdb <= 34) 2236 pwdb -= 6; 2237 else if (pwdb <= 42) 2238 pwdb -= 2; 2239 } 2240 } 2241 if (sc->avg_pwdb == -1) /* Init. */ 2242 sc->avg_pwdb = pwdb; 2243 else if (sc->avg_pwdb < pwdb) 2244 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2245 else 2246 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2247 2248 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2249 device_xname(sc->sc_dev), __func__, 2250 rate, rssi, pwdb, sc->avg_pwdb)); 2251 } 2252 2253 static int8_t 2254 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2255 { 2256 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2257 struct r92c_rx_phystat *phy; 2258 struct r92c_rx_cck *cck; 2259 uint8_t rpt; 2260 int8_t rssi; 2261 2262 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2263 __func__, rate)); 2264 2265 if (rate <= 3) { 2266 cck = (struct r92c_rx_cck *)physt; 2267 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2268 rpt = (cck->agc_rpt >> 5) & 0x3; 2269 rssi = (cck->agc_rpt & 0x1f) << 1; 2270 } else { 2271 rpt = (cck->agc_rpt >> 6) & 0x3; 2272 rssi = cck->agc_rpt & 0x3e; 2273 } 2274 rssi = cckoff[rpt] - rssi; 2275 } else { /* OFDM/HT. */ 2276 phy = (struct r92c_rx_phystat *)physt; 2277 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2278 } 2279 return rssi; 2280 } 2281 2282 static int8_t 2283 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2284 { 2285 struct r92c_rx_phystat *phy; 2286 struct r88e_rx_cck *cck; 2287 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2288 int8_t rssi; 2289 2290 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2291 __func__, rate)); 2292 2293 rssi = 0; 2294 if (rate <= 3) { 2295 cck = (struct r88e_rx_cck *)physt; 2296 cck_agc_rpt = cck->agc_rpt; 2297 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2298 vga_idx = cck_agc_rpt & 0x1f; 2299 switch (lna_idx) { 2300 case 7: 2301 if (vga_idx <= 27) 2302 rssi = -100 + 2* (27 - vga_idx); 2303 else 2304 rssi = -100; 2305 break; 2306 case 6: 2307 rssi = -48 + 2 * (2 - vga_idx); 2308 break; 2309 case 5: 2310 rssi = -42 + 2 * (7 - vga_idx); 2311 break; 2312 case 4: 2313 rssi = -36 + 2 * (7 - vga_idx); 2314 break; 2315 case 3: 2316 rssi = -24 + 2 * (7 - vga_idx); 2317 break; 2318 case 2: 2319 rssi = -12 + 2 * (5 - vga_idx); 2320 break; 2321 case 1: 2322 rssi = 8 - (2 * vga_idx); 2323 break; 2324 case 0: 2325 rssi = 14 - (2 * vga_idx); 2326 break; 2327 } 2328 rssi += 6; 2329 } else { /* OFDM/HT. */ 2330 phy = (struct r92c_rx_phystat *)physt; 2331 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2332 } 2333 return rssi; 2334 } 2335 2336 static void 2337 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2338 { 2339 struct ieee80211com *ic = &sc->sc_ic; 2340 struct ifnet *ifp = ic->ic_ifp; 2341 struct ieee80211_frame *wh; 2342 struct ieee80211_node *ni; 2343 struct r92c_rx_desc_usb *stat; 2344 uint32_t rxdw0, rxdw3; 2345 struct mbuf *m; 2346 uint8_t rate; 2347 int8_t rssi = 0; 2348 int s, infosz; 2349 2350 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2351 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2352 2353 stat = (struct r92c_rx_desc_usb *)buf; 2354 rxdw0 = le32toh(stat->rxdw0); 2355 rxdw3 = le32toh(stat->rxdw3); 2356 2357 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2358 /* 2359 * This should not happen since we setup our Rx filter 2360 * to not receive these frames. 2361 */ 2362 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2363 device_xname(sc->sc_dev), __func__)); 2364 ifp->if_ierrors++; 2365 return; 2366 } 2367 /* 2368 * XXX: This will drop most control packets. Do we really 2369 * want this in IEEE80211_M_MONITOR mode? 2370 */ 2371 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2372 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2373 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2374 device_xname(sc->sc_dev), __func__, pktlen)); 2375 ic->ic_stats.is_rx_tooshort++; 2376 ifp->if_ierrors++; 2377 return; 2378 } 2379 if (__predict_false(pktlen > MCLBYTES)) { 2380 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2381 device_xname(sc->sc_dev), __func__, pktlen)); 2382 ifp->if_ierrors++; 2383 return; 2384 } 2385 2386 rate = MS(rxdw3, R92C_RXDW3_RATE); 2387 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2388 2389 /* Get RSSI from PHY status descriptor if present. */ 2390 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2391 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2392 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2393 else 2394 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2395 /* Update our average RSSI. */ 2396 urtwn_update_avgrssi(sc, rate, rssi); 2397 } 2398 2399 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2400 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2401 2402 MGETHDR(m, M_DONTWAIT, MT_DATA); 2403 if (__predict_false(m == NULL)) { 2404 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2405 ic->ic_stats.is_rx_nobuf++; 2406 ifp->if_ierrors++; 2407 return; 2408 } 2409 if (pktlen > (int)MHLEN) { 2410 MCLGET(m, M_DONTWAIT); 2411 if (__predict_false(!(m->m_flags & M_EXT))) { 2412 aprint_error_dev(sc->sc_dev, 2413 "couldn't allocate rx mbuf cluster\n"); 2414 m_freem(m); 2415 ic->ic_stats.is_rx_nobuf++; 2416 ifp->if_ierrors++; 2417 return; 2418 } 2419 } 2420 2421 /* Finalize mbuf. */ 2422 m_set_rcvif(m, ifp); 2423 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2424 memcpy(mtod(m, uint8_t *), wh, pktlen); 2425 m->m_pkthdr.len = m->m_len = pktlen; 2426 2427 s = splnet(); 2428 if (__predict_false(sc->sc_drvbpf != NULL)) { 2429 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2430 2431 tap->wr_flags = 0; 2432 if (!(rxdw3 & R92C_RXDW3_HT)) { 2433 switch (rate) { 2434 /* CCK. */ 2435 case 0: tap->wr_rate = 2; break; 2436 case 1: tap->wr_rate = 4; break; 2437 case 2: tap->wr_rate = 11; break; 2438 case 3: tap->wr_rate = 22; break; 2439 /* OFDM. */ 2440 case 4: tap->wr_rate = 12; break; 2441 case 5: tap->wr_rate = 18; break; 2442 case 6: tap->wr_rate = 24; break; 2443 case 7: tap->wr_rate = 36; break; 2444 case 8: tap->wr_rate = 48; break; 2445 case 9: tap->wr_rate = 72; break; 2446 case 10: tap->wr_rate = 96; break; 2447 case 11: tap->wr_rate = 108; break; 2448 } 2449 } else if (rate >= 12) { /* MCS0~15. */ 2450 /* Bit 7 set means HT MCS instead of rate. */ 2451 tap->wr_rate = 0x80 | (rate - 12); 2452 } 2453 tap->wr_dbm_antsignal = rssi; 2454 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2455 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2456 2457 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2458 } 2459 2460 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2461 2462 /* push the frame up to the 802.11 stack */ 2463 ieee80211_input(ic, m, ni, rssi, 0); 2464 2465 /* Node is no longer needed. */ 2466 ieee80211_free_node(ni); 2467 2468 splx(s); 2469 } 2470 2471 static void 2472 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2473 { 2474 struct urtwn_rx_data *data = priv; 2475 struct urtwn_softc *sc = data->sc; 2476 struct r92c_rx_desc_usb *stat; 2477 size_t pidx = data->pidx; 2478 uint32_t rxdw0; 2479 uint8_t *buf; 2480 int len, totlen, pktlen, infosz, npkts; 2481 2482 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2483 device_xname(sc->sc_dev), __func__, status)); 2484 2485 mutex_enter(&sc->sc_rx_mtx); 2486 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2487 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2488 /* Put this Rx buffer back to our free list. */ 2489 mutex_exit(&sc->sc_rx_mtx); 2490 2491 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2492 if (status == USBD_STALLED) 2493 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2494 else if (status != USBD_CANCELLED) 2495 goto resubmit; 2496 return; 2497 } 2498 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2499 2500 if (__predict_false(len < (int)sizeof(*stat))) { 2501 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2502 device_xname(sc->sc_dev), __func__, len)); 2503 goto resubmit; 2504 } 2505 buf = data->buf; 2506 2507 /* Get the number of encapsulated frames. */ 2508 stat = (struct r92c_rx_desc_usb *)buf; 2509 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2510 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2511 device_xname(sc->sc_dev), __func__, npkts)); 2512 2513 if (npkts != 0) 2514 rnd_add_uint32(&sc->rnd_source, npkts); 2515 2516 /* Process all of them. */ 2517 while (npkts-- > 0) { 2518 if (__predict_false(len < (int)sizeof(*stat))) { 2519 DPRINTFN(DBG_RX, 2520 ("%s: %s: len(%d) is short than header\n", 2521 device_xname(sc->sc_dev), __func__, len)); 2522 break; 2523 } 2524 stat = (struct r92c_rx_desc_usb *)buf; 2525 rxdw0 = le32toh(stat->rxdw0); 2526 2527 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2528 if (__predict_false(pktlen == 0)) { 2529 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2530 device_xname(sc->sc_dev), __func__)); 2531 break; 2532 } 2533 2534 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2535 2536 /* Make sure everything fits in xfer. */ 2537 totlen = sizeof(*stat) + infosz + pktlen; 2538 if (__predict_false(totlen > len)) { 2539 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2540 device_xname(sc->sc_dev), __func__, totlen, 2541 (int)sizeof(*stat), infosz, pktlen, len)); 2542 break; 2543 } 2544 2545 /* Process 802.11 frame. */ 2546 urtwn_rx_frame(sc, buf, pktlen); 2547 2548 /* Next chunk is 128-byte aligned. */ 2549 totlen = roundup2(totlen, 128); 2550 buf += totlen; 2551 len -= totlen; 2552 } 2553 2554 resubmit: 2555 /* Setup a new transfer. */ 2556 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2557 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2558 (void)usbd_transfer(xfer); 2559 } 2560 2561 static void 2562 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2563 { 2564 struct urtwn_tx_data *data = priv; 2565 struct urtwn_softc *sc = data->sc; 2566 struct ifnet *ifp = &sc->sc_if; 2567 size_t pidx = data->pidx; 2568 int s; 2569 2570 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2571 device_xname(sc->sc_dev), __func__, status)); 2572 2573 mutex_enter(&sc->sc_tx_mtx); 2574 /* Put this Tx buffer back to our free list. */ 2575 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2576 mutex_exit(&sc->sc_tx_mtx); 2577 2578 s = splnet(); 2579 sc->tx_timer = 0; 2580 ifp->if_flags &= ~IFF_OACTIVE; 2581 2582 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2583 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2584 if (status == USBD_STALLED) { 2585 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2586 usbd_clear_endpoint_stall_async(pipe); 2587 } 2588 printf("ERROR1\n"); 2589 ifp->if_oerrors++; 2590 } 2591 splx(s); 2592 return; 2593 } 2594 2595 ifp->if_opackets++; 2596 urtwn_start(ifp); 2597 splx(s); 2598 2599 } 2600 2601 static int 2602 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2603 struct urtwn_tx_data *data) 2604 { 2605 struct ieee80211com *ic = &sc->sc_ic; 2606 struct ieee80211_frame *wh; 2607 struct ieee80211_key *k = NULL; 2608 struct r92c_tx_desc_usb *txd; 2609 size_t i, padsize, xferlen, txd_len; 2610 uint16_t seq, sum; 2611 uint8_t raid, type, tid; 2612 int s, hasqos, error; 2613 2614 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2615 2616 wh = mtod(m, struct ieee80211_frame *); 2617 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2618 txd_len = sizeof(*txd); 2619 2620 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2621 txd_len = 32; 2622 2623 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2624 k = ieee80211_crypto_encap(ic, ni, m); 2625 if (k == NULL) 2626 return ENOBUFS; 2627 2628 /* packet header may have moved, reset our local pointer */ 2629 wh = mtod(m, struct ieee80211_frame *); 2630 } 2631 2632 if (__predict_false(sc->sc_drvbpf != NULL)) { 2633 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2634 2635 tap->wt_flags = 0; 2636 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2637 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2638 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2639 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2640 2641 /* XXX: set tap->wt_rate? */ 2642 2643 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2644 } 2645 2646 /* non-qos data frames */ 2647 tid = R92C_TXDW1_QSEL_BE; 2648 if ((hasqos = ieee80211_has_qos(wh))) { 2649 /* data frames in 11n mode */ 2650 struct ieee80211_qosframe *qwh = (void *)wh; 2651 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2652 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2653 tid = R92C_TXDW1_QSEL_MGNT; 2654 } 2655 2656 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2657 padsize = 8; 2658 else 2659 padsize = 0; 2660 2661 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2662 padsize = 0; 2663 2664 /* Fill Tx descriptor. */ 2665 txd = (struct r92c_tx_desc_usb *)data->buf; 2666 memset(txd, 0, txd_len + padsize); 2667 2668 txd->txdw0 |= htole32( 2669 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2670 SM(R92C_TXDW0_OFFSET, txd_len)); 2671 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2672 txd->txdw0 |= htole32( 2673 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2674 } 2675 2676 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2677 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2678 2679 /* fix pad field */ 2680 if (padsize > 0) { 2681 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2682 device_xname(sc->sc_dev), __func__, padsize)); 2683 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2684 } 2685 2686 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2687 type == IEEE80211_FC0_TYPE_DATA) { 2688 if (ic->ic_curmode == IEEE80211_MODE_11B) 2689 raid = R92C_RAID_11B; 2690 else 2691 raid = R92C_RAID_11BG; 2692 DPRINTFN(DBG_TX, 2693 ("%s: %s: data packet: tid=%d, raid=%d\n", 2694 device_xname(sc->sc_dev), __func__, tid, raid)); 2695 2696 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2697 txd->txdw1 |= htole32( 2698 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2699 SM(R92C_TXDW1_QSEL, tid) | 2700 SM(R92C_TXDW1_RAID, raid) | 2701 R92C_TXDW1_AGGBK); 2702 } else 2703 txd->txdw1 |= htole32( 2704 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2705 SM(R92C_TXDW1_QSEL, tid) | 2706 SM(R92C_TXDW1_RAID, raid) | 2707 R92C_TXDW1_AGGBK); 2708 2709 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2710 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2711 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2712 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2713 2714 if (hasqos) { 2715 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2716 } 2717 2718 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2719 /* for 11g */ 2720 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2721 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2722 R92C_TXDW4_HWRTSEN); 2723 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2724 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2725 R92C_TXDW4_HWRTSEN); 2726 } 2727 } 2728 /* Send RTS at OFDM24. */ 2729 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2730 txd->txdw5 |= htole32(0x0001ff00); 2731 /* Send data at OFDM54. */ 2732 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2733 txd->txdw5 |= htole32(0x13 & 0x3f); 2734 else 2735 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2736 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2737 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2738 device_xname(sc->sc_dev), __func__)); 2739 txd->txdw1 |= htole32( 2740 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2741 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2742 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2743 2744 /* Force CCK1. */ 2745 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2746 /* Use 1Mbps */ 2747 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2748 } else { 2749 /* broadcast or multicast packets */ 2750 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2751 device_xname(sc->sc_dev), __func__)); 2752 txd->txdw1 |= htole32( 2753 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2754 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2755 2756 /* Force CCK1. */ 2757 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2758 /* Use 1Mbps */ 2759 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2760 } 2761 /* Set sequence number */ 2762 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2763 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2764 txd->txdseq |= htole16(seq); 2765 2766 if (!hasqos) { 2767 /* Use HW sequence numbering for non-QoS frames. */ 2768 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2769 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2770 } 2771 } else { 2772 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2773 R92E_HWSEQ_SHIFT); 2774 if (!hasqos) { 2775 /* Use HW sequence numbering for non-QoS frames. */ 2776 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2777 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2778 } 2779 } 2780 2781 /* Compute Tx descriptor checksum. */ 2782 sum = 0; 2783 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2784 sum ^= ((uint16_t *)txd)[i]; 2785 txd->txdsum = sum; /* NB: already little endian. */ 2786 2787 xferlen = txd_len + m->m_pkthdr.len + padsize; 2788 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2789 2790 s = splnet(); 2791 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2792 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2793 urtwn_txeof); 2794 error = usbd_transfer(data->xfer); 2795 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2796 error != USBD_IN_PROGRESS)) { 2797 splx(s); 2798 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2799 device_xname(sc->sc_dev), __func__, error)); 2800 return error; 2801 } 2802 splx(s); 2803 return 0; 2804 } 2805 2806 struct urtwn_tx_data * 2807 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2808 { 2809 struct urtwn_tx_data *data = NULL; 2810 2811 mutex_enter(&sc->sc_tx_mtx); 2812 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2813 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2814 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2815 } 2816 mutex_exit(&sc->sc_tx_mtx); 2817 2818 return data; 2819 } 2820 2821 static void 2822 urtwn_start(struct ifnet *ifp) 2823 { 2824 struct urtwn_softc *sc = ifp->if_softc; 2825 struct ieee80211com *ic = &sc->sc_ic; 2826 struct urtwn_tx_data *data; 2827 struct ether_header *eh; 2828 struct ieee80211_node *ni; 2829 struct mbuf *m; 2830 2831 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2832 2833 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2834 return; 2835 2836 data = NULL; 2837 for (;;) { 2838 /* Send pending management frames first. */ 2839 IF_POLL(&ic->ic_mgtq, m); 2840 if (m != NULL) { 2841 /* Use AC_VO for management frames. */ 2842 2843 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2844 2845 if (data == NULL) { 2846 ifp->if_flags |= IFF_OACTIVE; 2847 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2848 device_xname(sc->sc_dev))); 2849 return; 2850 } 2851 IF_DEQUEUE(&ic->ic_mgtq, m); 2852 ni = M_GETCTX(m, struct ieee80211_node *); 2853 M_CLEARCTX(m); 2854 goto sendit; 2855 } 2856 if (ic->ic_state != IEEE80211_S_RUN) 2857 break; 2858 2859 /* Encapsulate and send data frames. */ 2860 IFQ_POLL(&ifp->if_snd, m); 2861 if (m == NULL) 2862 break; 2863 2864 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2865 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2866 uint8_t qid = WME_AC_BE; 2867 if (ieee80211_has_qos(wh)) { 2868 /* data frames in 11n mode */ 2869 struct ieee80211_qosframe *qwh = (void *)wh; 2870 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2871 qid = TID_TO_WME_AC(tid); 2872 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2873 qid = WME_AC_VO; 2874 } 2875 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2876 2877 if (data == NULL) { 2878 ifp->if_flags |= IFF_OACTIVE; 2879 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2880 device_xname(sc->sc_dev))); 2881 return; 2882 } 2883 IFQ_DEQUEUE(&ifp->if_snd, m); 2884 2885 if (m->m_len < (int)sizeof(*eh) && 2886 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2887 printf("ERROR6\n"); 2888 ifp->if_oerrors++; 2889 continue; 2890 } 2891 eh = mtod(m, struct ether_header *); 2892 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2893 if (ni == NULL) { 2894 m_freem(m); 2895 printf("ERROR5\n"); 2896 ifp->if_oerrors++; 2897 continue; 2898 } 2899 2900 bpf_mtap(ifp, m, BPF_D_OUT); 2901 2902 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2903 ieee80211_free_node(ni); 2904 printf("ERROR4\n"); 2905 ifp->if_oerrors++; 2906 continue; 2907 } 2908 sendit: 2909 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2910 2911 if (urtwn_tx(sc, m, ni, data) != 0) { 2912 m_freem(m); 2913 ieee80211_free_node(ni); 2914 printf("ERROR3\n"); 2915 ifp->if_oerrors++; 2916 continue; 2917 } 2918 m_freem(m); 2919 ieee80211_free_node(ni); 2920 sc->tx_timer = 5; 2921 ifp->if_timer = 1; 2922 } 2923 } 2924 2925 static void 2926 urtwn_watchdog(struct ifnet *ifp) 2927 { 2928 struct urtwn_softc *sc = ifp->if_softc; 2929 2930 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2931 2932 ifp->if_timer = 0; 2933 2934 if (sc->tx_timer > 0) { 2935 if (--sc->tx_timer == 0) { 2936 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2937 /* urtwn_init(ifp); XXX needs a process context! */ 2938 printf("ERROR2\n"); 2939 ifp->if_oerrors++; 2940 return; 2941 } 2942 ifp->if_timer = 1; 2943 } 2944 ieee80211_watchdog(&sc->sc_ic); 2945 } 2946 2947 static int 2948 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2949 { 2950 struct urtwn_softc *sc = ifp->if_softc; 2951 struct ieee80211com *ic = &sc->sc_ic; 2952 int s, error = 0; 2953 2954 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2955 device_xname(sc->sc_dev), __func__, cmd, data)); 2956 2957 s = splnet(); 2958 2959 switch (cmd) { 2960 case SIOCSIFFLAGS: 2961 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2962 break; 2963 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2964 case IFF_UP | IFF_RUNNING: 2965 break; 2966 case IFF_UP: 2967 urtwn_init(ifp); 2968 break; 2969 case IFF_RUNNING: 2970 urtwn_stop(ifp, 1); 2971 break; 2972 case 0: 2973 break; 2974 } 2975 break; 2976 2977 case SIOCADDMULTI: 2978 case SIOCDELMULTI: 2979 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2980 /* setup multicast filter, etc */ 2981 error = 0; 2982 } 2983 break; 2984 2985 case SIOCS80211CHANNEL: 2986 /* 2987 * This allows for fast channel switching in monitor mode 2988 * (used by kismet). In IBSS mode, we must explicitly reset 2989 * the interface to generate a new beacon frame. 2990 */ 2991 error = ieee80211_ioctl(ic, cmd, data); 2992 if (error == ENETRESET && 2993 ic->ic_opmode == IEEE80211_M_MONITOR) { 2994 urtwn_set_chan(sc, ic->ic_curchan, 2995 IEEE80211_HTINFO_2NDCHAN_NONE); 2996 error = 0; 2997 } 2998 break; 2999 3000 default: 3001 error = ieee80211_ioctl(ic, cmd, data); 3002 break; 3003 } 3004 if (error == ENETRESET) { 3005 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3006 (IFF_UP | IFF_RUNNING) && 3007 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3008 urtwn_init(ifp); 3009 } 3010 error = 0; 3011 } 3012 3013 splx(s); 3014 3015 return error; 3016 } 3017 3018 static __inline int 3019 urtwn_power_on(struct urtwn_softc *sc) 3020 { 3021 3022 return sc->sc_power_on(sc); 3023 } 3024 3025 static int 3026 urtwn_r92c_power_on(struct urtwn_softc *sc) 3027 { 3028 uint32_t reg; 3029 int ntries; 3030 3031 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3032 3033 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3034 3035 /* Wait for autoload done bit. */ 3036 for (ntries = 0; ntries < 1000; ntries++) { 3037 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3038 break; 3039 DELAY(5); 3040 } 3041 if (ntries == 1000) { 3042 aprint_error_dev(sc->sc_dev, 3043 "timeout waiting for chip autoload\n"); 3044 return ETIMEDOUT; 3045 } 3046 3047 /* Unlock ISO/CLK/Power control register. */ 3048 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3049 /* Move SPS into PWM mode. */ 3050 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3051 DELAY(5); 3052 3053 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3054 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3055 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3056 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3057 DELAY(100); 3058 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3059 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3060 ~R92C_SYS_ISO_CTRL_MD2PP); 3061 } 3062 3063 /* Auto enable WLAN. */ 3064 urtwn_write_2(sc, R92C_APS_FSMCO, 3065 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3066 for (ntries = 0; ntries < 1000; ntries++) { 3067 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3068 R92C_APS_FSMCO_APFM_ONMAC)) 3069 break; 3070 DELAY(100); 3071 } 3072 if (ntries == 1000) { 3073 aprint_error_dev(sc->sc_dev, 3074 "timeout waiting for MAC auto ON\n"); 3075 return ETIMEDOUT; 3076 } 3077 3078 /* Enable radio, GPIO and LED functions. */ 3079 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3080 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3081 urtwn_write_2(sc, R92C_APS_FSMCO, 3082 R92C_APS_FSMCO_AFSM_HSUS | 3083 R92C_APS_FSMCO_PDN_EN | 3084 R92C_APS_FSMCO_PFM_ALDN); 3085 3086 /* Release RF digital isolation. */ 3087 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3088 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3089 3090 /* Initialize MAC. */ 3091 urtwn_write_1(sc, R92C_APSD_CTRL, 3092 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3093 for (ntries = 0; ntries < 200; ntries++) { 3094 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3095 R92C_APSD_CTRL_OFF_STATUS)) 3096 break; 3097 DELAY(5); 3098 } 3099 if (ntries == 200) { 3100 aprint_error_dev(sc->sc_dev, 3101 "timeout waiting for MAC initialization\n"); 3102 return ETIMEDOUT; 3103 } 3104 3105 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3106 reg = urtwn_read_2(sc, R92C_CR); 3107 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3108 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3109 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3110 R92C_CR_ENSEC; 3111 urtwn_write_2(sc, R92C_CR, reg); 3112 3113 urtwn_write_1(sc, 0xfe10, 0x19); 3114 return 0; 3115 } 3116 3117 static int 3118 urtwn_r92e_power_on(struct urtwn_softc *sc) 3119 { 3120 uint32_t reg; 3121 uint32_t val; 3122 int ntries; 3123 3124 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3125 3126 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3127 3128 /* Enable radio, GPIO and LED functions. */ 3129 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3130 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3131 urtwn_write_2(sc, R92C_APS_FSMCO, 3132 R92C_APS_FSMCO_AFSM_HSUS | 3133 R92C_APS_FSMCO_PDN_EN | 3134 R92C_APS_FSMCO_PFM_ALDN); 3135 3136 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3137 /* LDO. */ 3138 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3139 } 3140 else { 3141 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3142 R92C_SYS_SWR_CTRL2) & 0xffff); 3143 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3144 } 3145 3146 for (ntries = 0; ntries < 2; ntries++) { 3147 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3148 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3149 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3150 R92C_AFE_CTRL4)); 3151 } 3152 3153 /* Reset BB. */ 3154 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3155 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3156 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3157 3158 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3159 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3160 3161 /* Disable HWPDN. */ 3162 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3163 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3164 3165 /* Disable WL suspend. */ 3166 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3167 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3168 R92C_APS_FSMCO_AFSM_HSUS)); 3169 3170 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3171 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3172 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3173 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3174 for (ntries = 0; ntries < 10000; ntries++) { 3175 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3176 R92C_APS_FSMCO_APFM_ONMAC; 3177 if (val == 0x0) 3178 break; 3179 DELAY(10); 3180 } 3181 if (ntries == 10000) { 3182 aprint_error_dev(sc->sc_dev, 3183 "timeout waiting for chip power up\n"); 3184 return ETIMEDOUT; 3185 } 3186 3187 urtwn_write_2(sc, R92C_CR, 0x00); 3188 reg = urtwn_read_2(sc, R92C_CR); 3189 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3190 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3191 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3192 urtwn_write_2(sc, R92C_CR, reg); 3193 3194 return 0; 3195 } 3196 3197 static int 3198 urtwn_r88e_power_on(struct urtwn_softc *sc) 3199 { 3200 uint32_t reg; 3201 uint8_t val; 3202 int ntries; 3203 3204 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3205 3206 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3207 3208 /* Wait for power ready bit. */ 3209 for (ntries = 0; ntries < 5000; ntries++) { 3210 val = urtwn_read_1(sc, 0x6) & 0x2; 3211 if (val == 0x2) 3212 break; 3213 DELAY(10); 3214 } 3215 if (ntries == 5000) { 3216 aprint_error_dev(sc->sc_dev, 3217 "timeout waiting for chip power up\n"); 3218 return ETIMEDOUT; 3219 } 3220 3221 /* Reset BB. */ 3222 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3223 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3224 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3225 3226 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3227 3228 /* Disable HWPDN. */ 3229 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3230 3231 /* Disable WL suspend. */ 3232 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3233 3234 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3235 for (ntries = 0; ntries < 5000; ntries++) { 3236 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3237 break; 3238 DELAY(10); 3239 } 3240 if (ntries == 5000) 3241 return ETIMEDOUT; 3242 3243 /* Enable LDO normal mode. */ 3244 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3245 3246 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3247 urtwn_write_2(sc, R92C_CR, 0); 3248 reg = urtwn_read_2(sc, R92C_CR); 3249 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3250 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3251 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3252 urtwn_write_2(sc, R92C_CR, reg); 3253 3254 return 0; 3255 } 3256 3257 static int 3258 urtwn_llt_init(struct urtwn_softc *sc) 3259 { 3260 size_t i, page_count, pktbuf_count; 3261 uint32_t val; 3262 int error; 3263 3264 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3265 3266 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3267 3268 if (sc->chip & URTWN_CHIP_88E) 3269 page_count = R88E_TX_PAGE_COUNT; 3270 else if (sc->chip & URTWN_CHIP_92EU) 3271 page_count = R92E_TX_PAGE_COUNT; 3272 else 3273 page_count = R92C_TX_PAGE_COUNT; 3274 if (sc->chip & URTWN_CHIP_88E) 3275 pktbuf_count = R88E_TXPKTBUF_COUNT; 3276 else if (sc->chip & URTWN_CHIP_92EU) 3277 pktbuf_count = R88E_TXPKTBUF_COUNT; 3278 else 3279 pktbuf_count = R92C_TXPKTBUF_COUNT; 3280 3281 if (sc->chip & URTWN_CHIP_92EU) { 3282 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3283 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3284 DELAY(100); 3285 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3286 if (val & R92E_AUTO_LLT_EN) 3287 return EIO; 3288 return 0; 3289 } 3290 3291 /* Reserve pages [0; page_count]. */ 3292 for (i = 0; i < page_count; i++) { 3293 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3294 return error; 3295 } 3296 /* NB: 0xff indicates end-of-list. */ 3297 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3298 return error; 3299 /* 3300 * Use pages [page_count + 1; pktbuf_count - 1] 3301 * as ring buffer. 3302 */ 3303 for (++i; i < pktbuf_count - 1; i++) { 3304 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3305 return error; 3306 } 3307 /* Make the last page point to the beginning of the ring buffer. */ 3308 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3309 return error; 3310 } 3311 3312 static void 3313 urtwn_fw_reset(struct urtwn_softc *sc) 3314 { 3315 uint16_t reg; 3316 int ntries; 3317 3318 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3319 3320 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3321 3322 /* Tell 8051 to reset itself. */ 3323 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3324 3325 /* Wait until 8051 resets by itself. */ 3326 for (ntries = 0; ntries < 100; ntries++) { 3327 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3328 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3329 return; 3330 DELAY(50); 3331 } 3332 /* Force 8051 reset. */ 3333 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3334 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3335 } 3336 3337 static void 3338 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3339 { 3340 uint16_t reg; 3341 3342 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3343 3344 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3345 3346 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3347 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3348 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3349 } 3350 DELAY(50); 3351 3352 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3353 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3354 DELAY(50); 3355 3356 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3357 DELAY(50); 3358 3359 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3360 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3361 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3362 } 3363 DELAY(50); 3364 3365 } 3366 3367 static int 3368 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3369 { 3370 uint32_t reg; 3371 int off, mlen, error = 0; 3372 3373 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3374 device_xname(sc->sc_dev), __func__, page, buf, len)); 3375 3376 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3377 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3378 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3379 3380 off = R92C_FW_START_ADDR; 3381 while (len > 0) { 3382 if (len > 196) 3383 mlen = 196; 3384 else if (len > 4) 3385 mlen = 4; 3386 else 3387 mlen = 1; 3388 error = urtwn_write_region(sc, off, buf, mlen); 3389 if (error != 0) 3390 break; 3391 off += mlen; 3392 buf += mlen; 3393 len -= mlen; 3394 } 3395 return error; 3396 } 3397 3398 static int 3399 urtwn_load_firmware(struct urtwn_softc *sc) 3400 { 3401 firmware_handle_t fwh; 3402 const struct r92c_fw_hdr *hdr; 3403 const char *name; 3404 u_char *fw, *ptr; 3405 size_t len; 3406 uint32_t reg; 3407 int mlen, ntries, page, error; 3408 3409 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3410 3411 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3412 3413 /* Read firmware image from the filesystem. */ 3414 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3415 name = "rtl8188eufw.bin"; 3416 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3417 name = "rtl8192eefw.bin"; 3418 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3419 URTWN_CHIP_UMC_A_CUT) 3420 name = "rtl8192cfwU.bin"; 3421 else 3422 name = "rtl8192cfw.bin"; 3423 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3424 aprint_error_dev(sc->sc_dev, 3425 "failed load firmware of file %s (error %d)\n", name, 3426 error); 3427 return error; 3428 } 3429 const size_t fwlen = len = firmware_get_size(fwh); 3430 fw = firmware_malloc(len); 3431 if (fw == NULL) { 3432 aprint_error_dev(sc->sc_dev, 3433 "failed to allocate firmware memory\n"); 3434 firmware_close(fwh); 3435 return ENOMEM; 3436 } 3437 error = firmware_read(fwh, 0, fw, len); 3438 firmware_close(fwh); 3439 if (error != 0) { 3440 aprint_error_dev(sc->sc_dev, 3441 "failed to read firmware (error %d)\n", error); 3442 firmware_free(fw, fwlen); 3443 return error; 3444 } 3445 3446 len = fwlen; 3447 ptr = fw; 3448 hdr = (const struct r92c_fw_hdr *)ptr; 3449 /* Check if there is a valid FW header and skip it. */ 3450 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3451 (le16toh(hdr->signature) >> 4) == 0x88e || 3452 (le16toh(hdr->signature) >> 4) == 0x92e || 3453 (le16toh(hdr->signature) >> 4) == 0x92c) { 3454 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3455 device_xname(sc->sc_dev), __func__, 3456 le16toh(hdr->version), le16toh(hdr->subversion), 3457 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3458 ptr += sizeof(*hdr); 3459 len -= sizeof(*hdr); 3460 } 3461 3462 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3463 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3464 ISSET(sc->chip, URTWN_CHIP_92EU)) 3465 urtwn_r88e_fw_reset(sc); 3466 else 3467 urtwn_fw_reset(sc); 3468 } 3469 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3470 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3471 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3472 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3473 R92C_SYS_FUNC_EN_CPUEN); 3474 } 3475 3476 /* download enabled */ 3477 urtwn_write_1(sc, R92C_MCUFWDL, 3478 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3479 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3480 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3481 3482 /* Reset the FWDL checksum. */ 3483 urtwn_write_1(sc, R92C_MCUFWDL, 3484 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3485 3486 DELAY(50); 3487 /* download firmware */ 3488 for (page = 0; len > 0; page++) { 3489 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3490 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3491 if (error != 0) { 3492 aprint_error_dev(sc->sc_dev, 3493 "could not load firmware page %d\n", page); 3494 goto fail; 3495 } 3496 ptr += mlen; 3497 len -= mlen; 3498 } 3499 3500 /* download disable */ 3501 urtwn_write_1(sc, R92C_MCUFWDL, 3502 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3503 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3504 3505 /* Wait for checksum report. */ 3506 for (ntries = 0; ntries < 1000; ntries++) { 3507 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3508 break; 3509 DELAY(5); 3510 } 3511 if (ntries == 1000) { 3512 aprint_error_dev(sc->sc_dev, 3513 "timeout waiting for checksum report\n"); 3514 error = ETIMEDOUT; 3515 goto fail; 3516 } 3517 3518 /* Wait for firmware readiness. */ 3519 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3520 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3521 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3522 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3523 ISSET(sc->chip, URTWN_CHIP_92EU)) 3524 urtwn_r88e_fw_reset(sc); 3525 for (ntries = 0; ntries < 6000; ntries++) { 3526 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3527 break; 3528 DELAY(5); 3529 } 3530 if (ntries == 6000) { 3531 aprint_error_dev(sc->sc_dev, 3532 "timeout waiting for firmware readiness\n"); 3533 error = ETIMEDOUT; 3534 goto fail; 3535 } 3536 fail: 3537 firmware_free(fw, fwlen); 3538 return error; 3539 } 3540 3541 static __inline int 3542 urtwn_dma_init(struct urtwn_softc *sc) 3543 { 3544 3545 return sc->sc_dma_init(sc); 3546 } 3547 3548 static int 3549 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3550 { 3551 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3552 uint32_t reg; 3553 int error; 3554 3555 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3556 3557 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3558 3559 /* Initialize LLT table. */ 3560 error = urtwn_llt_init(sc); 3561 if (error != 0) 3562 return error; 3563 3564 /* Get Tx queues to USB endpoints mapping. */ 3565 hashq = hasnq = haslq = 0; 3566 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3567 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3568 device_xname(sc->sc_dev), __func__, reg)); 3569 if (MS(reg, R92C_USB_EP_HQ) != 0) 3570 hashq = 1; 3571 if (MS(reg, R92C_USB_EP_NQ) != 0) 3572 hasnq = 1; 3573 if (MS(reg, R92C_USB_EP_LQ) != 0) 3574 haslq = 1; 3575 nqueues = hashq + hasnq + haslq; 3576 if (nqueues == 0) 3577 return EIO; 3578 /* Get the number of pages for each queue. */ 3579 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3580 /* The remaining pages are assigned to the high priority queue. */ 3581 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3582 3583 /* Set number of pages for normal priority queue. */ 3584 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3585 urtwn_write_4(sc, R92C_RQPN, 3586 /* Set number of pages for public queue. */ 3587 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3588 /* Set number of pages for high priority queue. */ 3589 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3590 /* Set number of pages for low priority queue. */ 3591 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3592 /* Load values. */ 3593 R92C_RQPN_LD); 3594 3595 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3596 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3597 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3598 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3599 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3600 3601 /* Set queue to USB pipe mapping. */ 3602 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3603 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3604 if (nqueues == 1) { 3605 if (hashq) { 3606 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3607 } else if (hasnq) { 3608 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3609 } else { 3610 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3611 } 3612 } else if (nqueues == 2) { 3613 /* All 2-endpoints configs have a high priority queue. */ 3614 if (!hashq) { 3615 return EIO; 3616 } 3617 if (hasnq) { 3618 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3619 } else { 3620 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3621 } 3622 } else { 3623 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3624 } 3625 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3626 3627 /* Set Tx/Rx transfer page boundary. */ 3628 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3629 3630 /* Set Tx/Rx transfer page size. */ 3631 urtwn_write_1(sc, R92C_PBP, 3632 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3633 return 0; 3634 } 3635 3636 static int 3637 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3638 { 3639 usb_interface_descriptor_t *id; 3640 uint32_t reg; 3641 int nqueues; 3642 int error; 3643 3644 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3645 3646 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3647 3648 /* Initialize LLT table. */ 3649 error = urtwn_llt_init(sc); 3650 if (error != 0) 3651 return error; 3652 3653 /* Get Tx queues to USB endpoints mapping. */ 3654 id = usbd_get_interface_descriptor(sc->sc_iface); 3655 nqueues = id->bNumEndpoints - 1; 3656 if (nqueues == 0) 3657 return EIO; 3658 3659 /* Set number of pages for normal priority queue. */ 3660 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3661 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3662 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3663 3664 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3665 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3666 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3667 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3668 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3669 3670 /* Set queue to USB pipe mapping. */ 3671 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3672 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3673 if (nqueues == 1) 3674 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3675 else if (nqueues == 2) 3676 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3677 else 3678 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3679 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3680 3681 /* Set Tx/Rx transfer page boundary. */ 3682 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3683 3684 /* Set Tx/Rx transfer page size. */ 3685 urtwn_write_1(sc, R92C_PBP, 3686 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3687 3688 return 0; 3689 } 3690 3691 static void 3692 urtwn_mac_init(struct urtwn_softc *sc) 3693 { 3694 size_t i; 3695 3696 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3697 3698 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3699 3700 /* Write MAC initialization values. */ 3701 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3702 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3703 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3704 rtl8188eu_mac[i].val); 3705 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3706 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3707 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3708 rtl8192eu_mac[i].val); 3709 } else { 3710 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3711 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3712 rtl8192cu_mac[i].val); 3713 } 3714 } 3715 3716 static void 3717 urtwn_bb_init(struct urtwn_softc *sc) 3718 { 3719 const struct rtwn_bb_prog *prog; 3720 uint32_t reg; 3721 uint8_t crystalcap; 3722 size_t i; 3723 3724 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3725 3726 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3727 3728 /* Enable BB and RF. */ 3729 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3730 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3731 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3732 R92C_SYS_FUNC_EN_DIO_RF); 3733 3734 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3735 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3736 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3737 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3738 } 3739 3740 urtwn_write_1(sc, R92C_RF_CTRL, 3741 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3742 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3743 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3744 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3745 3746 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3747 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3748 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3749 urtwn_write_1(sc, 0x15, 0xe9); 3750 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3751 } 3752 3753 /* Select BB programming based on board type. */ 3754 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3755 prog = &rtl8188eu_bb_prog; 3756 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3757 prog = &rtl8192eu_bb_prog; 3758 else if (!(sc->chip & URTWN_CHIP_92C)) { 3759 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3760 prog = &rtl8188ce_bb_prog; 3761 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3762 prog = &rtl8188ru_bb_prog; 3763 } else { 3764 prog = &rtl8188cu_bb_prog; 3765 } 3766 } else { 3767 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3768 prog = &rtl8192ce_bb_prog; 3769 } else { 3770 prog = &rtl8192cu_bb_prog; 3771 } 3772 } 3773 /* Write BB initialization values. */ 3774 for (i = 0; i < prog->count; i++) { 3775 /* additional delay depend on registers */ 3776 switch (prog->regs[i]) { 3777 case 0xfe: 3778 urtwn_delay_ms(sc, 50); 3779 break; 3780 case 0xfd: 3781 urtwn_delay_ms(sc, 5); 3782 break; 3783 case 0xfc: 3784 urtwn_delay_ms(sc, 1); 3785 break; 3786 case 0xfb: 3787 DELAY(50); 3788 break; 3789 case 0xfa: 3790 DELAY(5); 3791 break; 3792 case 0xf9: 3793 DELAY(1); 3794 break; 3795 } 3796 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3797 DELAY(1); 3798 } 3799 3800 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3801 /* 8192C 1T only configuration. */ 3802 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3803 reg = (reg & ~0x00000003) | 0x2; 3804 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3805 3806 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3807 reg = (reg & ~0x00300033) | 0x00200022; 3808 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3809 3810 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3811 reg = (reg & ~0xff000000) | (0x45 << 24); 3812 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3813 3814 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3815 reg = (reg & ~0x000000ff) | 0x23; 3816 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3817 3818 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3819 reg = (reg & ~0x00000030) | (1 << 4); 3820 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3821 3822 reg = urtwn_bb_read(sc, 0xe74); 3823 reg = (reg & ~0x0c000000) | (2 << 26); 3824 urtwn_bb_write(sc, 0xe74, reg); 3825 reg = urtwn_bb_read(sc, 0xe78); 3826 reg = (reg & ~0x0c000000) | (2 << 26); 3827 urtwn_bb_write(sc, 0xe78, reg); 3828 reg = urtwn_bb_read(sc, 0xe7c); 3829 reg = (reg & ~0x0c000000) | (2 << 26); 3830 urtwn_bb_write(sc, 0xe7c, reg); 3831 reg = urtwn_bb_read(sc, 0xe80); 3832 reg = (reg & ~0x0c000000) | (2 << 26); 3833 urtwn_bb_write(sc, 0xe80, reg); 3834 reg = urtwn_bb_read(sc, 0xe88); 3835 reg = (reg & ~0x0c000000) | (2 << 26); 3836 urtwn_bb_write(sc, 0xe88, reg); 3837 } 3838 3839 /* Write AGC values. */ 3840 for (i = 0; i < prog->agccount; i++) { 3841 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3842 DELAY(1); 3843 } 3844 3845 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3846 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3847 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3848 DELAY(1); 3849 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3850 DELAY(1); 3851 } 3852 3853 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3854 crystalcap = sc->r88e_rom[0xb9]; 3855 if (crystalcap == 0x00) 3856 crystalcap = 0x20; 3857 crystalcap &= 0x3f; 3858 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3859 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3860 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3861 crystalcap | crystalcap << 6)); 3862 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3863 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3864 crystalcap = sc->r88e_rom[0xb9]; 3865 if (crystalcap == 0xff) 3866 crystalcap = 0x20; 3867 crystalcap &= 0x3f; 3868 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3869 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3870 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3871 crystalcap | crystalcap << 6)); 3872 } else { 3873 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3874 R92C_HSSI_PARAM2_CCK_HIPWR) { 3875 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3876 } 3877 } 3878 } 3879 3880 static void 3881 urtwn_rf_init(struct urtwn_softc *sc) 3882 { 3883 const struct rtwn_rf_prog *prog; 3884 uint32_t reg, mask, saved; 3885 size_t i, j, idx; 3886 3887 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3888 3889 /* Select RF programming based on board type. */ 3890 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3891 prog = rtl8188eu_rf_prog; 3892 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3893 prog = rtl8192eu_rf_prog; 3894 else if (!(sc->chip & URTWN_CHIP_92C)) { 3895 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3896 prog = rtl8188ce_rf_prog; 3897 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3898 prog = rtl8188ru_rf_prog; 3899 } else { 3900 prog = rtl8188cu_rf_prog; 3901 } 3902 } else { 3903 prog = rtl8192ce_rf_prog; 3904 } 3905 3906 for (i = 0; i < sc->nrxchains; i++) { 3907 /* Save RF_ENV control type. */ 3908 idx = i / 2; 3909 mask = 0xffffU << ((i % 2) * 16); 3910 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3911 3912 /* Set RF_ENV enable. */ 3913 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3914 reg |= 0x100000; 3915 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3916 DELAY(50); 3917 3918 /* Set RF_ENV output high. */ 3919 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3920 reg |= 0x10; 3921 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3922 DELAY(50); 3923 3924 /* Set address and data lengths of RF registers. */ 3925 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3926 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3927 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3928 DELAY(50); 3929 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3930 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3931 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3932 DELAY(50); 3933 3934 /* Write RF initialization values for this chain. */ 3935 for (j = 0; j < prog[i].count; j++) { 3936 if (prog[i].regs[j] >= 0xf9 && 3937 prog[i].regs[j] <= 0xfe) { 3938 /* 3939 * These are fake RF registers offsets that 3940 * indicate a delay is required. 3941 */ 3942 urtwn_delay_ms(sc, 50); 3943 continue; 3944 } 3945 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3946 DELAY(5); 3947 } 3948 3949 /* Restore RF_ENV control type. */ 3950 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3951 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3952 } 3953 3954 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3955 URTWN_CHIP_UMC_A_CUT) { 3956 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3957 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3958 } 3959 3960 /* Cache RF register CHNLBW. */ 3961 for (i = 0; i < 2; i++) { 3962 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3963 } 3964 } 3965 3966 static void 3967 urtwn_cam_init(struct urtwn_softc *sc) 3968 { 3969 uint32_t content, command; 3970 uint8_t idx; 3971 size_t i; 3972 3973 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3974 3975 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3976 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3977 return; 3978 3979 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3980 content = (idx & 3) 3981 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3982 | R92C_CAM_VALID; 3983 3984 command = R92C_CAMCMD_POLLING 3985 | R92C_CAMCMD_WRITE 3986 | R92C_CAM_CTL0(idx); 3987 3988 urtwn_write_4(sc, R92C_CAMWRITE, content); 3989 urtwn_write_4(sc, R92C_CAMCMD, command); 3990 } 3991 3992 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3993 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3994 if (i == 0) { 3995 content = (idx & 3) 3996 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3997 | R92C_CAM_VALID; 3998 } else { 3999 content = 0; 4000 } 4001 4002 command = R92C_CAMCMD_POLLING 4003 | R92C_CAMCMD_WRITE 4004 | R92C_CAM_CTL0(idx) 4005 | i; 4006 4007 urtwn_write_4(sc, R92C_CAMWRITE, content); 4008 urtwn_write_4(sc, R92C_CAMCMD, command); 4009 } 4010 } 4011 4012 /* Invalidate all CAM entries. */ 4013 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4014 } 4015 4016 static void 4017 urtwn_pa_bias_init(struct urtwn_softc *sc) 4018 { 4019 uint8_t reg; 4020 size_t i; 4021 4022 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4023 4024 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4025 4026 for (i = 0; i < sc->nrxchains; i++) { 4027 if (sc->pa_setting & (1U << i)) 4028 continue; 4029 4030 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4031 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4032 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4033 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4034 } 4035 if (!(sc->pa_setting & 0x10)) { 4036 reg = urtwn_read_1(sc, 0x16); 4037 reg = (reg & ~0xf0) | 0x90; 4038 urtwn_write_1(sc, 0x16, reg); 4039 } 4040 } 4041 4042 static void 4043 urtwn_rxfilter_init(struct urtwn_softc *sc) 4044 { 4045 4046 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4047 4048 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4049 4050 /* Initialize Rx filter. */ 4051 /* TODO: use better filter for monitor mode. */ 4052 urtwn_write_4(sc, R92C_RCR, 4053 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4054 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4055 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4056 /* Accept all multicast frames. */ 4057 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4058 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4059 /* Accept all management frames. */ 4060 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4061 /* Reject all control frames. */ 4062 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4063 /* Accept all data frames. */ 4064 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4065 } 4066 4067 static void 4068 urtwn_edca_init(struct urtwn_softc *sc) 4069 { 4070 4071 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4072 4073 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4074 4075 /* set spec SIFS (used in NAV) */ 4076 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4077 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4078 4079 /* set SIFS CCK/OFDM */ 4080 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4081 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4082 4083 /* TXOP */ 4084 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4085 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4086 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4087 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4088 } 4089 4090 static void 4091 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4092 uint16_t power[URTWN_RIDX_COUNT]) 4093 { 4094 uint32_t reg; 4095 4096 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4097 __func__, chain)); 4098 4099 /* Write per-CCK rate Tx power. */ 4100 if (chain == 0) { 4101 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4102 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4103 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4104 4105 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4106 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4107 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4108 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4109 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4110 } else { 4111 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4112 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4113 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4114 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4115 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4116 4117 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4118 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4119 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4120 } 4121 /* Write per-OFDM rate Tx power. */ 4122 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4123 SM(R92C_TXAGC_RATE06, power[ 4]) | 4124 SM(R92C_TXAGC_RATE09, power[ 5]) | 4125 SM(R92C_TXAGC_RATE12, power[ 6]) | 4126 SM(R92C_TXAGC_RATE18, power[ 7])); 4127 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4128 SM(R92C_TXAGC_RATE24, power[ 8]) | 4129 SM(R92C_TXAGC_RATE36, power[ 9]) | 4130 SM(R92C_TXAGC_RATE48, power[10]) | 4131 SM(R92C_TXAGC_RATE54, power[11])); 4132 /* Write per-MCS Tx power. */ 4133 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4134 SM(R92C_TXAGC_MCS00, power[12]) | 4135 SM(R92C_TXAGC_MCS01, power[13]) | 4136 SM(R92C_TXAGC_MCS02, power[14]) | 4137 SM(R92C_TXAGC_MCS03, power[15])); 4138 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4139 SM(R92C_TXAGC_MCS04, power[16]) | 4140 SM(R92C_TXAGC_MCS05, power[17]) | 4141 SM(R92C_TXAGC_MCS06, power[18]) | 4142 SM(R92C_TXAGC_MCS07, power[19])); 4143 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4144 SM(R92C_TXAGC_MCS08, power[20]) | 4145 SM(R92C_TXAGC_MCS09, power[21]) | 4146 SM(R92C_TXAGC_MCS10, power[22]) | 4147 SM(R92C_TXAGC_MCS11, power[23])); 4148 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4149 SM(R92C_TXAGC_MCS12, power[24]) | 4150 SM(R92C_TXAGC_MCS13, power[25]) | 4151 SM(R92C_TXAGC_MCS14, power[26]) | 4152 SM(R92C_TXAGC_MCS15, power[27])); 4153 } 4154 4155 static void 4156 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4157 uint16_t power[URTWN_RIDX_COUNT]) 4158 { 4159 struct r92c_rom *rom = &sc->rom; 4160 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4161 const struct rtwn_txpwr *base; 4162 int ridx, group; 4163 4164 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4165 device_xname(sc->sc_dev), __func__, chain, chan)); 4166 4167 /* Determine channel group. */ 4168 if (chan <= 3) { 4169 group = 0; 4170 } else if (chan <= 9) { 4171 group = 1; 4172 } else { 4173 group = 2; 4174 } 4175 4176 /* Get original Tx power based on board type and RF chain. */ 4177 if (!(sc->chip & URTWN_CHIP_92C)) { 4178 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4179 base = &rtl8188ru_txagc[chain]; 4180 } else { 4181 base = &rtl8192cu_txagc[chain]; 4182 } 4183 } else { 4184 base = &rtl8192cu_txagc[chain]; 4185 } 4186 4187 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4188 if (sc->regulatory == 0) { 4189 for (ridx = 0; ridx <= 3; ridx++) { 4190 power[ridx] = base->pwr[0][ridx]; 4191 } 4192 } 4193 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4194 if (sc->regulatory == 3) { 4195 power[ridx] = base->pwr[0][ridx]; 4196 /* Apply vendor limits. */ 4197 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4198 maxpow = rom->ht40_max_pwr[group]; 4199 } else { 4200 maxpow = rom->ht20_max_pwr[group]; 4201 } 4202 maxpow = (maxpow >> (chain * 4)) & 0xf; 4203 if (power[ridx] > maxpow) { 4204 power[ridx] = maxpow; 4205 } 4206 } else if (sc->regulatory == 1) { 4207 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4208 power[ridx] = base->pwr[group][ridx]; 4209 } 4210 } else if (sc->regulatory != 2) { 4211 power[ridx] = base->pwr[0][ridx]; 4212 } 4213 } 4214 4215 /* Compute per-CCK rate Tx power. */ 4216 cckpow = rom->cck_tx_pwr[chain][group]; 4217 for (ridx = 0; ridx <= 3; ridx++) { 4218 power[ridx] += cckpow; 4219 if (power[ridx] > R92C_MAX_TX_PWR) { 4220 power[ridx] = R92C_MAX_TX_PWR; 4221 } 4222 } 4223 4224 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4225 if (sc->ntxchains > 1) { 4226 /* Apply reduction for 2 spatial streams. */ 4227 diff = rom->ht40_2s_tx_pwr_diff[group]; 4228 diff = (diff >> (chain * 4)) & 0xf; 4229 htpow = (htpow > diff) ? htpow - diff : 0; 4230 } 4231 4232 /* Compute per-OFDM rate Tx power. */ 4233 diff = rom->ofdm_tx_pwr_diff[group]; 4234 diff = (diff >> (chain * 4)) & 0xf; 4235 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4236 for (ridx = 4; ridx <= 11; ridx++) { 4237 power[ridx] += ofdmpow; 4238 if (power[ridx] > R92C_MAX_TX_PWR) { 4239 power[ridx] = R92C_MAX_TX_PWR; 4240 } 4241 } 4242 4243 /* Compute per-MCS Tx power. */ 4244 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4245 diff = rom->ht20_tx_pwr_diff[group]; 4246 diff = (diff >> (chain * 4)) & 0xf; 4247 htpow += diff; /* HT40->HT20 correction. */ 4248 } 4249 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4250 power[ridx] += htpow; 4251 if (power[ridx] > R92C_MAX_TX_PWR) { 4252 power[ridx] = R92C_MAX_TX_PWR; 4253 } 4254 } 4255 #ifdef URTWN_DEBUG 4256 if (urtwn_debug & DBG_RF) { 4257 /* Dump per-rate Tx power values. */ 4258 printf("%s: %s: Tx power for chain %zd:\n", 4259 device_xname(sc->sc_dev), __func__, chain); 4260 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4261 printf("%s: %s: Rate %d = %u\n", 4262 device_xname(sc->sc_dev), __func__, ridx, 4263 power[ridx]); 4264 } 4265 } 4266 #endif 4267 } 4268 4269 void 4270 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4271 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4272 { 4273 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4274 const struct rtwn_r88e_txpwr *base; 4275 int ridx, group; 4276 4277 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4278 device_xname(sc->sc_dev), __func__, chain, chan)); 4279 4280 /* Determine channel group. */ 4281 if (chan <= 2) 4282 group = 0; 4283 else if (chan <= 5) 4284 group = 1; 4285 else if (chan <= 8) 4286 group = 2; 4287 else if (chan <= 11) 4288 group = 3; 4289 else if (chan <= 13) 4290 group = 4; 4291 else 4292 group = 5; 4293 4294 /* Get original Tx power based on board type and RF chain. */ 4295 base = &rtl8188eu_txagc[chain]; 4296 4297 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4298 if (sc->regulatory == 0) { 4299 for (ridx = 0; ridx <= 3; ridx++) 4300 power[ridx] = base->pwr[0][ridx]; 4301 } 4302 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4303 if (sc->regulatory == 3) 4304 power[ridx] = base->pwr[0][ridx]; 4305 else if (sc->regulatory == 1) { 4306 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4307 power[ridx] = base->pwr[group][ridx]; 4308 } else if (sc->regulatory != 2) 4309 power[ridx] = base->pwr[0][ridx]; 4310 } 4311 4312 /* Compute per-CCK rate Tx power. */ 4313 cckpow = sc->cck_tx_pwr[group]; 4314 for (ridx = 0; ridx <= 3; ridx++) { 4315 power[ridx] += cckpow; 4316 if (power[ridx] > R92C_MAX_TX_PWR) 4317 power[ridx] = R92C_MAX_TX_PWR; 4318 } 4319 4320 htpow = sc->ht40_tx_pwr[group]; 4321 4322 /* Compute per-OFDM rate Tx power. */ 4323 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4324 for (ridx = 4; ridx <= 11; ridx++) { 4325 power[ridx] += ofdmpow; 4326 if (power[ridx] > R92C_MAX_TX_PWR) 4327 power[ridx] = R92C_MAX_TX_PWR; 4328 } 4329 4330 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4331 for (ridx = 12; ridx <= 27; ridx++) { 4332 power[ridx] += bw20pow; 4333 if (power[ridx] > R92C_MAX_TX_PWR) 4334 power[ridx] = R92C_MAX_TX_PWR; 4335 } 4336 } 4337 4338 static void 4339 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4340 { 4341 uint16_t power[URTWN_RIDX_COUNT]; 4342 size_t i; 4343 4344 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4345 4346 for (i = 0; i < sc->ntxchains; i++) { 4347 /* Compute per-rate Tx power values. */ 4348 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4349 ISSET(sc->chip, URTWN_CHIP_92EU)) 4350 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4351 else 4352 urtwn_get_txpower(sc, i, chan, ht40m, power); 4353 /* Write per-rate Tx power values to hardware. */ 4354 urtwn_write_txpower(sc, i, power); 4355 } 4356 } 4357 4358 static void 4359 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4360 { 4361 struct ieee80211com *ic = &sc->sc_ic; 4362 u_int chan; 4363 size_t i; 4364 4365 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4366 4367 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4368 __func__, chan)); 4369 4370 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4371 4372 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4373 chan += 2; 4374 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4375 chan -= 2; 4376 } 4377 4378 /* Set Tx power for this new channel. */ 4379 urtwn_set_txpower(sc, chan, ht40m); 4380 4381 for (i = 0; i < sc->nrxchains; i++) { 4382 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4383 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4384 } 4385 4386 if (ht40m) { 4387 /* Is secondary channel below or above primary? */ 4388 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4389 uint32_t reg; 4390 4391 urtwn_write_1(sc, R92C_BWOPMODE, 4392 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4393 4394 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4395 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4396 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4397 4398 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4399 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4400 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4401 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4402 4403 /* Set CCK side band. */ 4404 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4405 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4406 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4407 4408 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4409 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4410 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4411 4412 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4413 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4414 ~R92C_FPGA0_ANAPARAM2_CBW20); 4415 4416 reg = urtwn_bb_read(sc, 0x818); 4417 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4418 urtwn_bb_write(sc, 0x818, reg); 4419 4420 /* Select 40MHz bandwidth. */ 4421 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4422 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4423 } else { 4424 urtwn_write_1(sc, R92C_BWOPMODE, 4425 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4426 4427 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4428 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4429 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4430 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4431 4432 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4433 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4434 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4435 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4436 R92C_FPGA0_ANAPARAM2_CBW20); 4437 } 4438 4439 /* Select 20MHz bandwidth. */ 4440 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4441 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4442 (ISSET(sc->chip, URTWN_CHIP_88E) || 4443 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4444 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4445 } 4446 } 4447 4448 static void 4449 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4450 { 4451 4452 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4453 __func__, inited)); 4454 4455 uint32_t addaBackup[16], iqkBackup[4], piMode; 4456 4457 #ifdef notyet 4458 uint32_t odfm0_agccore_regs[3]; 4459 uint32_t ant_regs[3]; 4460 uint32_t rf_regs[8]; 4461 #endif 4462 uint32_t reg0, reg1, reg2; 4463 int i, attempt; 4464 4465 #ifdef notyet 4466 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4467 R92E_STBC_SETTING + 2)); 4468 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4469 /* Save AGCCORE regs. */ 4470 for (i = 0; i < sc->nrxchains; i++) { 4471 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4472 R92C_OFDM0_AGCCORE1(i)); 4473 } 4474 #endif 4475 /* Save BB regs. */ 4476 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4477 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4478 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4479 4480 /* Save adda regs to be restored when finished. */ 4481 for (i = 0; i < __arraycount(addaReg); i++) 4482 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4483 /* Save mac regs. */ 4484 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4485 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4486 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4487 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4488 4489 #ifdef notyet 4490 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4491 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4492 4493 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4494 for (i = 0; i < sc->nrxchains; i++) 4495 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4496 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4497 #endif 4498 4499 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4500 R92C_HSSI_PARAM1_PI); 4501 if (piMode == 0) { 4502 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4503 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4504 R92C_HSSI_PARAM1_PI); 4505 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4506 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4507 R92C_HSSI_PARAM1_PI); 4508 } 4509 4510 attempt = 1; 4511 4512 next_attempt: 4513 4514 /* Set mac regs for calibration. */ 4515 for (i = 0; i < __arraycount(addaReg); i++) { 4516 urtwn_bb_write(sc, addaReg[i], 4517 addaReg[__arraycount(addaReg) - 1]); 4518 } 4519 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4520 R92C_CCK0_AFESETTING)); 4521 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4522 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4523 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4524 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4525 4526 if (sc->ntxchains > 1) 4527 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4528 4529 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4530 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4531 ~R92C_BCN_CTRL_EN_BCN)); 4532 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4533 ~R92C_BCN_CTRL_EN_BCN)); 4534 4535 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4536 ~R92C_GPIO_MUXCFG_ENBT)); 4537 4538 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4539 4540 if (sc->ntxchains > 1) 4541 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4542 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4543 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4544 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4545 4546 /* Restore BB regs. */ 4547 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4548 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4549 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4550 4551 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4552 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4553 if (sc->nrxchains > 1) 4554 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4555 4556 if (attempt-- > 0) 4557 goto next_attempt; 4558 4559 /* Restore mode. */ 4560 if (piMode == 0) { 4561 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4562 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4563 ~R92C_HSSI_PARAM1_PI); 4564 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4565 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4566 ~R92C_HSSI_PARAM1_PI); 4567 } 4568 4569 #ifdef notyet 4570 for (i = 0; i < sc->nrxchains; i++) { 4571 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4572 odfm0_agccore_regs[i]); 4573 } 4574 #endif 4575 4576 /* Restore adda regs. */ 4577 for (i = 0; i < __arraycount(addaReg); i++) 4578 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4579 /* Restore mac regs. */ 4580 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4581 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4582 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4583 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4584 4585 #ifdef notyet 4586 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4587 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4588 4589 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4590 for (i = 0; i < sc->nrxchains; i++) 4591 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4592 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4593 #endif 4594 } 4595 4596 static void 4597 urtwn_lc_calib(struct urtwn_softc *sc) 4598 { 4599 uint32_t rf_ac[2]; 4600 uint8_t txmode; 4601 size_t i; 4602 4603 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4604 4605 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4606 4607 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4608 if ((txmode & 0x70) != 0) { 4609 /* Disable all continuous Tx. */ 4610 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4611 4612 /* Set RF mode to standby mode. */ 4613 for (i = 0; i < sc->nrxchains; i++) { 4614 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4615 urtwn_rf_write(sc, i, R92C_RF_AC, 4616 RW(rf_ac[i], R92C_RF_AC_MODE, 4617 R92C_RF_AC_MODE_STANDBY)); 4618 } 4619 } else { 4620 /* Block all Tx queues. */ 4621 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4622 } 4623 /* Start calibration. */ 4624 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4625 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4626 4627 /* Give calibration the time to complete. */ 4628 urtwn_delay_ms(sc, 100); 4629 4630 /* Restore configuration. */ 4631 if ((txmode & 0x70) != 0) { 4632 /* Restore Tx mode. */ 4633 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4634 /* Restore RF mode. */ 4635 for (i = 0; i < sc->nrxchains; i++) { 4636 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4637 } 4638 } else { 4639 /* Unblock all Tx queues. */ 4640 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4641 } 4642 } 4643 4644 static void 4645 urtwn_temp_calib(struct urtwn_softc *sc) 4646 { 4647 int temp, t_meter_reg; 4648 4649 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4650 4651 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4652 4653 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4654 t_meter_reg = R92C_RF_T_METER; 4655 else 4656 t_meter_reg = R92E_RF_T_METER; 4657 4658 if (sc->thcal_state == 0) { 4659 /* Start measuring temperature. */ 4660 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4661 device_xname(sc->sc_dev), __func__)); 4662 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4663 sc->thcal_state = 1; 4664 return; 4665 } 4666 sc->thcal_state = 0; 4667 4668 /* Read measured temperature. */ 4669 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4670 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4671 __func__, temp)); 4672 if (temp == 0) /* Read failed, skip. */ 4673 return; 4674 4675 /* 4676 * Redo LC calibration if temperature changed significantly since 4677 * last calibration. 4678 */ 4679 if (sc->thcal_lctemp == 0) { 4680 /* First LC calibration is performed in urtwn_init(). */ 4681 sc->thcal_lctemp = temp; 4682 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4683 DPRINTFN(DBG_RF, 4684 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4685 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4686 temp)); 4687 urtwn_lc_calib(sc); 4688 /* Record temperature of last LC calibration. */ 4689 sc->thcal_lctemp = temp; 4690 } 4691 } 4692 4693 static int 4694 urtwn_init(struct ifnet *ifp) 4695 { 4696 struct urtwn_softc *sc = ifp->if_softc; 4697 struct ieee80211com *ic = &sc->sc_ic; 4698 struct urtwn_rx_data *data; 4699 uint32_t reg; 4700 size_t i; 4701 int error; 4702 4703 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4704 4705 urtwn_stop(ifp, 0); 4706 4707 mutex_enter(&sc->sc_write_mtx); 4708 4709 mutex_enter(&sc->sc_task_mtx); 4710 /* Init host async commands ring. */ 4711 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4712 mutex_exit(&sc->sc_task_mtx); 4713 4714 mutex_enter(&sc->sc_fwcmd_mtx); 4715 /* Init firmware commands ring. */ 4716 sc->fwcur = 0; 4717 mutex_exit(&sc->sc_fwcmd_mtx); 4718 4719 /* Allocate Tx/Rx buffers. */ 4720 error = urtwn_alloc_rx_list(sc); 4721 if (error != 0) { 4722 aprint_error_dev(sc->sc_dev, 4723 "could not allocate Rx buffers\n"); 4724 goto fail; 4725 } 4726 error = urtwn_alloc_tx_list(sc); 4727 if (error != 0) { 4728 aprint_error_dev(sc->sc_dev, 4729 "could not allocate Tx buffers\n"); 4730 goto fail; 4731 } 4732 4733 /* Power on adapter. */ 4734 error = urtwn_power_on(sc); 4735 if (error != 0) 4736 goto fail; 4737 4738 /* Initialize DMA. */ 4739 error = urtwn_dma_init(sc); 4740 if (error != 0) 4741 goto fail; 4742 4743 /* Set info size in Rx descriptors (in 64-bit words). */ 4744 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4745 4746 /* Init interrupts. */ 4747 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4748 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4749 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4750 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4751 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4752 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4753 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4754 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4755 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4756 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4757 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4758 } 4759 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4760 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4761 } else { 4762 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4763 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4764 } 4765 4766 /* Set MAC address. */ 4767 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4768 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4769 4770 /* Set initial network type. */ 4771 reg = urtwn_read_4(sc, R92C_CR); 4772 switch (ic->ic_opmode) { 4773 case IEEE80211_M_STA: 4774 default: 4775 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4776 break; 4777 4778 case IEEE80211_M_IBSS: 4779 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4780 break; 4781 } 4782 urtwn_write_4(sc, R92C_CR, reg); 4783 4784 /* Set response rate */ 4785 reg = urtwn_read_4(sc, R92C_RRSR); 4786 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4787 urtwn_write_4(sc, R92C_RRSR, reg); 4788 4789 /* SIFS (used in NAV) */ 4790 urtwn_write_2(sc, R92C_SPEC_SIFS, 4791 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4792 4793 /* Set short/long retry limits. */ 4794 urtwn_write_2(sc, R92C_RL, 4795 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4796 4797 /* Initialize EDCA parameters. */ 4798 urtwn_edca_init(sc); 4799 4800 /* Setup rate fallback. */ 4801 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4802 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4803 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4804 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4805 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4806 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4807 } 4808 4809 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4810 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4811 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4812 /* Set ACK timeout. */ 4813 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4814 4815 /* Setup USB aggregation. */ 4816 /* Tx */ 4817 reg = urtwn_read_4(sc, R92C_TDECTRL); 4818 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4819 urtwn_write_4(sc, R92C_TDECTRL, reg); 4820 /* Rx */ 4821 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4822 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4823 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4824 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4825 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4826 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4827 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4828 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4829 ISSET(sc->chip, URTWN_CHIP_92EU)) 4830 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4831 else 4832 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4833 4834 /* Initialize beacon parameters. */ 4835 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4836 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4837 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4838 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4839 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4840 4841 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4842 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4843 /* Setup AMPDU aggregation. */ 4844 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4845 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4846 urtwn_write_2(sc, 0x4ca, 0x0708); 4847 4848 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4849 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4850 } 4851 4852 /* Load 8051 microcode. */ 4853 error = urtwn_load_firmware(sc); 4854 if (error != 0) 4855 goto fail; 4856 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4857 4858 /* Initialize MAC/BB/RF blocks. */ 4859 /* 4860 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4861 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4862 * XXX: This setting should be removed from rtl8192cu_mac[]. 4863 */ 4864 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4865 urtwn_rxfilter_init(sc); // reset R92C_RCR 4866 urtwn_bb_init(sc); 4867 urtwn_rf_init(sc); 4868 4869 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4870 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4871 urtwn_write_2(sc, R92C_CR, 4872 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4873 R92C_CR_MACRXEN); 4874 } 4875 4876 /* Turn CCK and OFDM blocks on. */ 4877 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4878 reg |= R92C_RFMOD_CCK_EN; 4879 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4880 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4881 reg |= R92C_RFMOD_OFDM_EN; 4882 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4883 4884 /* Clear per-station keys table. */ 4885 urtwn_cam_init(sc); 4886 4887 /* Enable hardware sequence numbering. */ 4888 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4889 4890 /* Perform LO and IQ calibrations. */ 4891 urtwn_iq_calib(sc, sc->iqk_inited); 4892 sc->iqk_inited = true; 4893 4894 /* Perform LC calibration. */ 4895 urtwn_lc_calib(sc); 4896 4897 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4898 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4899 /* Fix USB interference issue. */ 4900 urtwn_write_1(sc, 0xfe40, 0xe0); 4901 urtwn_write_1(sc, 0xfe41, 0x8d); 4902 urtwn_write_1(sc, 0xfe42, 0x80); 4903 urtwn_write_4(sc, 0x20c, 0xfd0320); 4904 4905 urtwn_pa_bias_init(sc); 4906 } 4907 4908 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4909 !(sc->chip & URTWN_CHIP_92EU)) { 4910 /* 1T1R */ 4911 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4912 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4913 } 4914 4915 /* Initialize GPIO setting. */ 4916 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4917 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4918 4919 /* Fix for lower temperature. */ 4920 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4921 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4922 urtwn_write_1(sc, 0x15, 0xe9); 4923 4924 /* Set default channel. */ 4925 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4926 4927 /* Queue Rx xfers. */ 4928 for (size_t j = 0; j < sc->rx_npipe; j++) { 4929 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4930 data = &sc->rx_data[j][i]; 4931 usbd_setup_xfer(data->xfer, data, data->buf, 4932 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4933 urtwn_rxeof); 4934 error = usbd_transfer(data->xfer); 4935 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4936 error != USBD_IN_PROGRESS)) 4937 goto fail; 4938 } 4939 } 4940 4941 /* We're ready to go. */ 4942 ifp->if_flags &= ~IFF_OACTIVE; 4943 ifp->if_flags |= IFF_RUNNING; 4944 sc->sc_running = true; 4945 4946 mutex_exit(&sc->sc_write_mtx); 4947 4948 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4949 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4950 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4951 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4952 urtwn_wait_async(sc); 4953 4954 return 0; 4955 4956 fail: 4957 mutex_exit(&sc->sc_write_mtx); 4958 4959 urtwn_stop(ifp, 1); 4960 return error; 4961 } 4962 4963 static void 4964 urtwn_stop(struct ifnet *ifp, int disable) 4965 { 4966 struct urtwn_softc *sc = ifp->if_softc; 4967 struct ieee80211com *ic = &sc->sc_ic; 4968 size_t i; 4969 int s; 4970 4971 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4972 4973 s = splusb(); 4974 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4975 urtwn_wait_async(sc); 4976 splx(s); 4977 4978 sc->tx_timer = 0; 4979 ifp->if_timer = 0; 4980 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4981 4982 callout_stop(&sc->sc_scan_to); 4983 callout_stop(&sc->sc_calib_to); 4984 4985 /* Abort Tx. */ 4986 for (i = 0; i < sc->tx_npipe; i++) { 4987 if (sc->tx_pipe[i] != NULL) 4988 usbd_abort_pipe(sc->tx_pipe[i]); 4989 } 4990 4991 /* Stop Rx pipe. */ 4992 for (i = 0; i < sc->rx_npipe; i++) { 4993 if (sc->rx_pipe[i] != NULL) 4994 usbd_abort_pipe(sc->rx_pipe[i]); 4995 } 4996 4997 /* Free Tx/Rx buffers. */ 4998 urtwn_free_tx_list(sc); 4999 urtwn_free_rx_list(sc); 5000 5001 sc->sc_running = false; 5002 if (disable) 5003 urtwn_chip_stop(sc); 5004 } 5005 5006 static int 5007 urtwn_reset(struct ifnet *ifp) 5008 { 5009 struct urtwn_softc *sc = ifp->if_softc; 5010 struct ieee80211com *ic = &sc->sc_ic; 5011 5012 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5013 return ENETRESET; 5014 5015 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5016 5017 return 0; 5018 } 5019 5020 static void 5021 urtwn_chip_stop(struct urtwn_softc *sc) 5022 { 5023 uint32_t reg; 5024 bool disabled = true; 5025 5026 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5027 5028 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5029 ISSET(sc->chip, URTWN_CHIP_92EU)) 5030 return; 5031 5032 mutex_enter(&sc->sc_write_mtx); 5033 5034 /* 5035 * RF Off Sequence 5036 */ 5037 /* Pause MAC TX queue */ 5038 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5039 5040 /* Disable RF */ 5041 urtwn_rf_write(sc, 0, 0, 0); 5042 5043 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5044 5045 /* Reset BB state machine */ 5046 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5047 R92C_SYS_FUNC_EN_USBD | 5048 R92C_SYS_FUNC_EN_USBA | 5049 R92C_SYS_FUNC_EN_BB_GLB_RST); 5050 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5051 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5052 5053 /* 5054 * Reset digital sequence 5055 */ 5056 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5057 /* Reset MCU ready status */ 5058 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5059 /* If firmware in ram code, do reset */ 5060 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5061 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5062 ISSET(sc->chip, URTWN_CHIP_92EU)) 5063 urtwn_r88e_fw_reset(sc); 5064 else 5065 urtwn_fw_reset(sc); 5066 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5067 } 5068 } 5069 5070 /* Reset MAC and Enable 8051 */ 5071 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5072 5073 /* Reset MCU ready status */ 5074 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5075 5076 if (disabled) { 5077 /* Disable MAC clock */ 5078 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5079 /* Disable AFE PLL */ 5080 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5081 /* Gated AFE DIG_CLOCK */ 5082 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5083 /* Isolated digital to PON */ 5084 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5085 } 5086 5087 /* 5088 * Pull GPIO PIN to balance level and LED control 5089 */ 5090 /* 1. Disable GPIO[7:0] */ 5091 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5092 5093 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5094 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5095 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5096 5097 /* Disable GPIO[10:8] */ 5098 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5099 5100 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5101 reg |= (((reg & 0x000f) << 4) | 0x0780); 5102 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5103 5104 /* Disable LED0 & 1 */ 5105 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5106 5107 /* 5108 * Reset digital sequence 5109 */ 5110 if (disabled) { 5111 /* Disable ELDR clock */ 5112 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5113 /* Isolated ELDR to PON */ 5114 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5115 } 5116 5117 /* 5118 * Disable analog sequence 5119 */ 5120 if (disabled) { 5121 /* Disable A15 power */ 5122 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5123 /* Disable digital core power */ 5124 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5125 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5126 ~R92C_LDOV12D_CTRL_LDV12_EN); 5127 } 5128 5129 /* Enter PFM mode */ 5130 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5131 5132 /* Set USB suspend */ 5133 urtwn_write_2(sc, R92C_APS_FSMCO, 5134 R92C_APS_FSMCO_APDM_HOST | 5135 R92C_APS_FSMCO_AFSM_HSUS | 5136 R92C_APS_FSMCO_PFM_ALDN); 5137 5138 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5139 5140 mutex_exit(&sc->sc_write_mtx); 5141 } 5142 5143 static void 5144 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5145 { 5146 if (sc->sc_running == false) 5147 DELAY(ms * 1000); 5148 else 5149 usbd_delay_ms(sc->sc_udev, ms); 5150 } 5151 5152 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5153 5154 #ifdef _MODULE 5155 #include "ioconf.c" 5156 #endif 5157 5158 static int 5159 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5160 { 5161 int error = 0; 5162 5163 switch (cmd) { 5164 case MODULE_CMD_INIT: 5165 #ifdef _MODULE 5166 error = config_init_component(cfdriver_ioconf_urtwn, 5167 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5168 #endif 5169 return error; 5170 case MODULE_CMD_FINI: 5171 #ifdef _MODULE 5172 error = config_fini_component(cfdriver_ioconf_urtwn, 5173 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5174 #endif 5175 return error; 5176 default: 5177 return ENOTTY; 5178 } 5179 } 5180
Indexes created Tue Sep 30 11:09:46 GMT 2025