if_urtwn.c revision 1.71.2.3
1 /* $NetBSD: if_urtwn.c,v 1.71.2.3 2020/04/24 17:28:21 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.71.2.3 2020/04/24 17:28:21 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/ic/rtwnreg.h> 78 #include <dev/ic/rtwn_data.h> 79 #include <dev/usb/if_urtwnreg.h> 80 #include <dev/usb/if_urtwnvar.h> 81 82 /* 83 * The sc_write_mtx locking is to prevent sequences of writes from 84 * being intermingled with each other. I don't know if this is really 85 * needed. I have added it just to be on the safe side. 86 */ 87 88 #ifdef URTWN_DEBUG 89 #define DBG_INIT __BIT(0) 90 #define DBG_FN __BIT(1) 91 #define DBG_TX __BIT(2) 92 #define DBG_RX __BIT(3) 93 #define DBG_STM __BIT(4) 94 #define DBG_RF __BIT(5) 95 #define DBG_REG __BIT(6) 96 #define DBG_ALL 0xffffffffU 97 u_int urtwn_debug = 0; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 196 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 197 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 198 199 /* URTWN_RTL8192EU */ 200 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 201 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 202 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 203 }; 204 #undef URTWN_DEV 205 #undef URTWN_RTL8188E_DEV 206 #undef URTWN_RTL8192EU_DEV 207 208 static int urtwn_match(device_t, cfdata_t, void *); 209 static void urtwn_attach(device_t, device_t, void *); 210 static int urtwn_detach(device_t, int); 211 static int urtwn_activate(device_t, enum devact); 212 213 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 214 urtwn_attach, urtwn_detach, urtwn_activate); 215 216 static int urtwn_open_pipes(struct urtwn_softc *); 217 static void urtwn_close_pipes(struct urtwn_softc *); 218 static int urtwn_alloc_rx_list(struct urtwn_softc *); 219 static void urtwn_free_rx_list(struct urtwn_softc *); 220 static int urtwn_alloc_tx_list(struct urtwn_softc *); 221 static void urtwn_free_tx_list(struct urtwn_softc *); 222 static void urtwn_task(void *); 223 static void urtwn_do_async(struct urtwn_softc *, 224 void (*)(struct urtwn_softc *, void *), void *, int); 225 static void urtwn_wait_async(struct urtwn_softc *); 226 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 227 int); 228 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 229 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 230 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 231 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 232 int); 233 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 234 int); 235 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 236 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 237 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 238 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 239 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 240 uint32_t); 241 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 242 uint32_t); 243 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 244 uint32_t); 245 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 246 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 247 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 248 static void urtwn_efuse_read(struct urtwn_softc *); 249 static void urtwn_efuse_switch_power(struct urtwn_softc *); 250 static int urtwn_read_chipid(struct urtwn_softc *); 251 #ifdef URTWN_DEBUG 252 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 253 #endif 254 static void urtwn_read_rom(struct urtwn_softc *); 255 static void urtwn_r88e_read_rom(struct urtwn_softc *); 256 static int urtwn_media_change(struct ifnet *); 257 static int urtwn_ra_init(struct urtwn_softc *); 258 static int urtwn_get_nettype(struct urtwn_softc *); 259 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 260 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 261 static void urtwn_set_led(struct urtwn_softc *, int, int); 262 static void urtwn_calib_to(void *); 263 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 264 static void urtwn_next_scan(void *); 265 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 266 int); 267 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 268 static int urtwn_wme_update(struct ieee80211com *); 269 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 270 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 271 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 272 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 273 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 274 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 275 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 276 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 277 struct ieee80211_node *, struct urtwn_tx_data *); 278 static struct urtwn_tx_data * 279 urtwn_get_tx_data(struct urtwn_softc *, size_t); 280 static void urtwn_start(struct ifnet *); 281 static void urtwn_watchdog(struct ifnet *); 282 static int urtwn_ioctl(struct ifnet *, u_long, void *); 283 static int urtwn_r92c_power_on(struct urtwn_softc *); 284 static int urtwn_r92e_power_on(struct urtwn_softc *); 285 static int urtwn_r88e_power_on(struct urtwn_softc *); 286 static int urtwn_llt_init(struct urtwn_softc *); 287 static void urtwn_fw_reset(struct urtwn_softc *); 288 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 289 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 290 static int urtwn_load_firmware(struct urtwn_softc *); 291 static int urtwn_r92c_dma_init(struct urtwn_softc *); 292 static int urtwn_r88e_dma_init(struct urtwn_softc *); 293 static void urtwn_mac_init(struct urtwn_softc *); 294 static void urtwn_bb_init(struct urtwn_softc *); 295 static void urtwn_rf_init(struct urtwn_softc *); 296 static void urtwn_cam_init(struct urtwn_softc *); 297 static void urtwn_pa_bias_init(struct urtwn_softc *); 298 static void urtwn_rxfilter_init(struct urtwn_softc *); 299 static void urtwn_edca_init(struct urtwn_softc *); 300 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 301 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 302 uint16_t[]); 303 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 304 u_int, uint16_t[]); 305 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 306 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 307 u_int); 308 static void urtwn_iq_calib(struct urtwn_softc *, bool); 309 static void urtwn_lc_calib(struct urtwn_softc *); 310 static void urtwn_temp_calib(struct urtwn_softc *); 311 static int urtwn_init(struct ifnet *); 312 static void urtwn_stop(struct ifnet *, int); 313 static int urtwn_reset(struct ifnet *); 314 static void urtwn_chip_stop(struct urtwn_softc *); 315 static void urtwn_newassoc(struct ieee80211_node *, int); 316 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 317 318 /* Aliases. */ 319 #define urtwn_bb_write urtwn_write_4 320 #define urtwn_bb_read urtwn_read_4 321 322 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 323 324 static const uint16_t addaReg[] = { 325 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 326 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 327 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 328 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 329 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 330 }; 331 332 static int 333 urtwn_match(device_t parent, cfdata_t match, void *aux) 334 { 335 struct usb_attach_arg *uaa = aux; 336 337 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 338 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 339 } 340 341 static void 342 urtwn_attach(device_t parent, device_t self, void *aux) 343 { 344 struct urtwn_softc *sc = device_private(self); 345 struct ieee80211com *ic = &sc->sc_ic; 346 struct ifnet *ifp = &sc->sc_if; 347 struct usb_attach_arg *uaa = aux; 348 char *devinfop; 349 const struct urtwn_dev *dev; 350 usb_device_request_t req; 351 size_t i; 352 int error; 353 354 sc->sc_dev = self; 355 sc->sc_udev = uaa->uaa_device; 356 357 sc->chip = 0; 358 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 359 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 360 SET(sc->chip, URTWN_CHIP_88E); 361 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 362 SET(sc->chip, URTWN_CHIP_92EU); 363 364 aprint_naive("\n"); 365 aprint_normal("\n"); 366 367 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 368 369 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 370 aprint_normal_dev(self, "%s\n", devinfop); 371 usbd_devinfo_free(devinfop); 372 373 req.bmRequestType = UT_WRITE_DEVICE; 374 req.bRequest = UR_SET_FEATURE; 375 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 376 USETW(req.wIndex, UHF_PORT_SUSPEND); 377 USETW(req.wLength, 0); 378 379 (void) usbd_do_request(sc->sc_udev, &req, 0); 380 381 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 382 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 383 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 384 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 385 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 386 387 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 388 389 callout_init(&sc->sc_scan_to, 0); 390 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 391 callout_init(&sc->sc_calib_to, 0); 392 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 393 394 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 395 RND_TYPE_NET, RND_FLAG_DEFAULT); 396 397 error = usbd_set_config_no(sc->sc_udev, 1, 0); 398 if (error != 0) { 399 aprint_error_dev(self, "failed to set configuration" 400 ", err=%s\n", usbd_errstr(error)); 401 goto fail; 402 } 403 404 /* Get the first interface handle. */ 405 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 406 if (error != 0) { 407 aprint_error_dev(self, "could not get interface handle\n"); 408 goto fail; 409 } 410 411 error = urtwn_read_chipid(sc); 412 if (error != 0) { 413 aprint_error_dev(self, "unsupported test chip\n"); 414 goto fail; 415 } 416 417 /* Determine number of Tx/Rx chains. */ 418 if (sc->chip & URTWN_CHIP_92C) { 419 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 420 sc->nrxchains = 2; 421 } else if (sc->chip & URTWN_CHIP_92EU) { 422 sc->ntxchains = 2; 423 sc->nrxchains = 2; 424 } else { 425 sc->ntxchains = 1; 426 sc->nrxchains = 1; 427 } 428 429 if (ISSET(sc->chip, URTWN_CHIP_88E) || 430 ISSET(sc->chip, URTWN_CHIP_92EU)) 431 urtwn_r88e_read_rom(sc); 432 else 433 urtwn_read_rom(sc); 434 435 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 436 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 437 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 438 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 439 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 440 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 441 "8188CUS", sc->ntxchains, sc->nrxchains, 442 ether_sprintf(ic->ic_myaddr)); 443 444 error = urtwn_open_pipes(sc); 445 if (error != 0) { 446 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 447 goto fail; 448 } 449 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 450 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 451 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 452 453 /* 454 * Setup the 802.11 device. 455 */ 456 ic->ic_ifp = ifp; 457 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 458 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 459 ic->ic_state = IEEE80211_S_INIT; 460 461 /* Set device capabilities. */ 462 ic->ic_caps = 463 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 464 IEEE80211_C_IBSS | /* IBSS mode supported */ 465 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 466 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 467 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 468 IEEE80211_C_WME | /* 802.11e */ 469 IEEE80211_C_WPA; /* 802.11i */ 470 471 /* Set supported .11b and .11g rates. */ 472 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 473 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 474 475 /* Set supported .11b and .11g channels (1 through 14). */ 476 for (i = 1; i <= 14; i++) { 477 ic->ic_channels[i].ic_freq = 478 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 479 ic->ic_channels[i].ic_flags = 480 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 481 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 482 } 483 484 ifp->if_softc = sc; 485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 486 ifp->if_init = urtwn_init; 487 ifp->if_ioctl = urtwn_ioctl; 488 ifp->if_start = urtwn_start; 489 ifp->if_watchdog = urtwn_watchdog; 490 IFQ_SET_READY(&ifp->if_snd); 491 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 492 493 if_initialize(ifp); 494 ieee80211_ifattach(ic); 495 496 /* override default methods */ 497 ic->ic_newassoc = urtwn_newassoc; 498 ic->ic_reset = urtwn_reset; 499 ic->ic_wme.wme_update = urtwn_wme_update; 500 501 /* Override state transition machine. */ 502 sc->sc_newstate = ic->ic_newstate; 503 ic->ic_newstate = urtwn_newstate; 504 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 505 506 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 507 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 508 &sc->sc_drvbpf); 509 510 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 511 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 512 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 513 514 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 515 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 516 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 517 518 ifp->if_percpuq = if_percpuq_create(ifp); 519 if_register(ifp); 520 521 ieee80211_announce(ic); 522 523 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 524 525 if (!pmf_device_register(self, NULL, NULL)) 526 aprint_error_dev(self, "couldn't establish power handler\n"); 527 528 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 529 return; 530 531 fail: 532 sc->sc_dying = 1; 533 aprint_error_dev(self, "attach failed\n"); 534 } 535 536 static int 537 urtwn_detach(device_t self, int flags) 538 { 539 struct urtwn_softc *sc = device_private(self); 540 struct ifnet *ifp = &sc->sc_if; 541 int s; 542 543 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 544 545 pmf_device_deregister(self); 546 547 s = splusb(); 548 549 sc->sc_dying = 1; 550 551 callout_halt(&sc->sc_scan_to, NULL); 552 callout_halt(&sc->sc_calib_to, NULL); 553 554 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 555 urtwn_stop(ifp, 0); 556 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 557 NULL); 558 559 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 560 bpf_detach(ifp); 561 ieee80211_ifdetach(&sc->sc_ic); 562 if_detach(ifp); 563 564 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 565 urtwn_close_pipes(sc); 566 } 567 568 splx(s); 569 570 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 571 572 rnd_detach_source(&sc->rnd_source); 573 574 callout_destroy(&sc->sc_scan_to); 575 callout_destroy(&sc->sc_calib_to); 576 577 mutex_destroy(&sc->sc_write_mtx); 578 mutex_destroy(&sc->sc_fwcmd_mtx); 579 mutex_destroy(&sc->sc_tx_mtx); 580 mutex_destroy(&sc->sc_rx_mtx); 581 mutex_destroy(&sc->sc_task_mtx); 582 583 return 0; 584 } 585 586 static int 587 urtwn_activate(device_t self, enum devact act) 588 { 589 struct urtwn_softc *sc = device_private(self); 590 591 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 592 593 switch (act) { 594 case DVACT_DEACTIVATE: 595 if_deactivate(sc->sc_ic.ic_ifp); 596 return 0; 597 default: 598 return EOPNOTSUPP; 599 } 600 } 601 602 static int 603 urtwn_open_pipes(struct urtwn_softc *sc) 604 { 605 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 606 static uint8_t epaddr[R92C_MAX_EPOUT]; 607 static uint8_t rxepaddr[R92C_MAX_EPIN]; 608 usb_interface_descriptor_t *id; 609 usb_endpoint_descriptor_t *ed; 610 size_t i, ntx = 0, nrx = 0; 611 int error; 612 613 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 614 615 /* Determine the number of bulk-out pipes. */ 616 id = usbd_get_interface_descriptor(sc->sc_iface); 617 for (i = 0; i < id->bNumEndpoints; i++) { 618 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 619 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 620 continue; 621 } 622 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 623 if (ntx < sizeof(epaddr)) 624 epaddr[ntx] = ed->bEndpointAddress; 625 ntx++; 626 } 627 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 628 if (nrx < sizeof(rxepaddr)) 629 rxepaddr[nrx] = ed->bEndpointAddress; 630 nrx++; 631 } 632 } 633 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 634 aprint_error_dev(sc->sc_dev, 635 "%zd: invalid number of Rx bulk pipes\n", nrx); 636 return EIO; 637 } 638 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 639 aprint_error_dev(sc->sc_dev, 640 "%zd: invalid number of Tx bulk pipes\n", ntx); 641 return EIO; 642 } 643 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 644 device_xname(sc->sc_dev), __func__, nrx, ntx)); 645 sc->rx_npipe = nrx; 646 sc->tx_npipe = ntx; 647 648 /* Open bulk-in pipe at address 0x81. */ 649 for (i = 0; i < nrx; i++) { 650 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 651 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 652 if (error != 0) { 653 aprint_error_dev(sc->sc_dev, 654 "could not open Rx bulk pipe 0x%02x: %d\n", 655 rxepaddr[i], error); 656 goto fail; 657 } 658 } 659 660 /* Open bulk-out pipes (up to 3). */ 661 for (i = 0; i < ntx; i++) { 662 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 663 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 664 if (error != 0) { 665 aprint_error_dev(sc->sc_dev, 666 "could not open Tx bulk pipe 0x%02x: %d\n", 667 epaddr[i], error); 668 goto fail; 669 } 670 } 671 672 /* Map 802.11 access categories to USB pipes. */ 673 sc->ac2idx[WME_AC_BK] = 674 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 675 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 676 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 677 678 fail: 679 if (error != 0) 680 urtwn_close_pipes(sc); 681 return error; 682 } 683 684 static void 685 urtwn_close_pipes(struct urtwn_softc *sc) 686 { 687 struct usbd_pipe *pipe; 688 size_t i; 689 690 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 691 692 /* Close Rx pipes. */ 693 CTASSERT(sizeof(pipe) == sizeof(void *)); 694 for (i = 0; i < sc->rx_npipe; i++) { 695 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 696 if (pipe != NULL) { 697 usbd_close_pipe(pipe); 698 } 699 } 700 701 /* Close Tx pipes. */ 702 for (i = 0; i < sc->tx_npipe; i++) { 703 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 704 if (pipe != NULL) { 705 usbd_close_pipe(pipe); 706 } 707 } 708 } 709 710 static int 711 urtwn_alloc_rx_list(struct urtwn_softc *sc) 712 { 713 struct urtwn_rx_data *data; 714 size_t i; 715 int error = 0; 716 717 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 718 719 for (size_t j = 0; j < sc->rx_npipe; j++) { 720 TAILQ_INIT(&sc->rx_free_list[j]); 721 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 722 data = &sc->rx_data[j][i]; 723 724 data->sc = sc; /* Backpointer for callbacks. */ 725 726 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 727 0, 0, &data->xfer); 728 if (error) { 729 aprint_error_dev(sc->sc_dev, 730 "could not allocate xfer\n"); 731 break; 732 } 733 734 data->buf = usbd_get_buffer(data->xfer); 735 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 736 } 737 } 738 if (error != 0) 739 urtwn_free_rx_list(sc); 740 return error; 741 } 742 743 static void 744 urtwn_free_rx_list(struct urtwn_softc *sc) 745 { 746 struct usbd_xfer *xfer; 747 size_t i; 748 749 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 750 751 /* NB: Caller must abort pipe first. */ 752 for (size_t j = 0; j < sc->rx_npipe; j++) { 753 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 754 CTASSERT(sizeof(xfer) == sizeof(void *)); 755 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 756 if (xfer != NULL) 757 usbd_destroy_xfer(xfer); 758 } 759 } 760 } 761 762 static int 763 urtwn_alloc_tx_list(struct urtwn_softc *sc) 764 { 765 struct urtwn_tx_data *data; 766 size_t i; 767 int error = 0; 768 769 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 770 771 mutex_enter(&sc->sc_tx_mtx); 772 for (size_t j = 0; j < sc->tx_npipe; j++) { 773 TAILQ_INIT(&sc->tx_free_list[j]); 774 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 775 data = &sc->tx_data[j][i]; 776 777 data->sc = sc; /* Backpointer for callbacks. */ 778 data->pidx = j; 779 780 error = usbd_create_xfer(sc->tx_pipe[j], 781 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 782 &data->xfer); 783 if (error) { 784 aprint_error_dev(sc->sc_dev, 785 "could not allocate xfer\n"); 786 goto fail; 787 } 788 789 data->buf = usbd_get_buffer(data->xfer); 790 791 /* Append this Tx buffer to our free list. */ 792 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 793 } 794 } 795 mutex_exit(&sc->sc_tx_mtx); 796 return 0; 797 798 fail: 799 urtwn_free_tx_list(sc); 800 mutex_exit(&sc->sc_tx_mtx); 801 return error; 802 } 803 804 static void 805 urtwn_free_tx_list(struct urtwn_softc *sc) 806 { 807 struct usbd_xfer *xfer; 808 size_t i; 809 810 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 811 812 /* NB: Caller must abort pipe first. */ 813 for (size_t j = 0; j < sc->tx_npipe; j++) { 814 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 815 CTASSERT(sizeof(xfer) == sizeof(void *)); 816 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 817 if (xfer != NULL) 818 usbd_destroy_xfer(xfer); 819 } 820 } 821 } 822 823 static int 824 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 825 struct ieee80211_node *ni) 826 { 827 struct urtwn_tx_data *data = 828 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 829 return urtwn_tx(sc, m, ni, data); 830 } 831 832 static void 833 urtwn_task(void *arg) 834 { 835 struct urtwn_softc *sc = arg; 836 struct ieee80211com *ic = &sc->sc_ic; 837 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 838 struct urtwn_host_cmd *cmd; 839 int s; 840 841 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 842 if (ic->ic_state == IEEE80211_S_RUN && 843 (ic->ic_opmode == IEEE80211_M_HOSTAP || 844 ic->ic_opmode == IEEE80211_M_IBSS)) { 845 846 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 847 &sc->sc_bo); 848 if (m == NULL) { 849 aprint_error_dev(sc->sc_dev, 850 "could not allocate beacon"); 851 } 852 853 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 854 m_freem(m); 855 aprint_error_dev(sc->sc_dev, "could not send beacon"); 856 } 857 858 /* beacon is no longer needed */ 859 m_freem(m); 860 } 861 862 /* Process host commands. */ 863 s = splusb(); 864 mutex_spin_enter(&sc->sc_task_mtx); 865 while (ring->next != ring->cur) { 866 cmd = &ring->cmd[ring->next]; 867 mutex_spin_exit(&sc->sc_task_mtx); 868 splx(s); 869 /* Invoke callback with kernel lock held. */ 870 cmd->cb(sc, cmd->data); 871 s = splusb(); 872 mutex_spin_enter(&sc->sc_task_mtx); 873 ring->queued--; 874 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 875 } 876 mutex_spin_exit(&sc->sc_task_mtx); 877 wakeup(&sc->cmdq); 878 splx(s); 879 } 880 881 static void 882 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 883 void *arg, int len) 884 { 885 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 886 struct urtwn_host_cmd *cmd; 887 int s; 888 889 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 890 device_xname(sc->sc_dev), __func__, cb, arg, len)); 891 892 s = splusb(); 893 mutex_spin_enter(&sc->sc_task_mtx); 894 cmd = &ring->cmd[ring->cur]; 895 cmd->cb = cb; 896 KASSERT(len <= sizeof(cmd->data)); 897 memcpy(cmd->data, arg, len); 898 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 899 900 /* If there is no pending command already, schedule a task. */ 901 if (!sc->sc_dying && ++ring->queued == 1) { 902 mutex_spin_exit(&sc->sc_task_mtx); 903 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 904 } else 905 mutex_spin_exit(&sc->sc_task_mtx); 906 splx(s); 907 } 908 909 static void 910 urtwn_wait_async(struct urtwn_softc *sc) 911 { 912 913 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 914 915 /* Wait for all queued asynchronous commands to complete. */ 916 while (sc->cmdq.queued > 0) 917 tsleep(&sc->cmdq, 0, "endtask", 0); 918 } 919 920 static int 921 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 922 int len) 923 { 924 usb_device_request_t req; 925 usbd_status error; 926 927 KASSERT(mutex_owned(&sc->sc_write_mtx)); 928 929 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 930 req.bRequest = R92C_REQ_REGS; 931 USETW(req.wValue, addr); 932 USETW(req.wIndex, 0); 933 USETW(req.wLength, len); 934 error = usbd_do_request(sc->sc_udev, &req, buf); 935 if (error != USBD_NORMAL_COMPLETION) { 936 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 937 device_xname(sc->sc_dev), __func__, error, addr, len)); 938 } 939 return error; 940 } 941 942 static void 943 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 944 { 945 946 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 947 device_xname(sc->sc_dev), __func__, addr, val)); 948 949 urtwn_write_region_1(sc, addr, &val, 1); 950 } 951 952 static void 953 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 954 { 955 uint8_t buf[2]; 956 957 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 958 device_xname(sc->sc_dev), __func__, addr, val)); 959 960 buf[0] = (uint8_t)val; 961 buf[1] = (uint8_t)(val >> 8); 962 urtwn_write_region_1(sc, addr, buf, 2); 963 } 964 965 static void 966 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 967 { 968 uint8_t buf[4]; 969 970 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 971 device_xname(sc->sc_dev), __func__, addr, val)); 972 973 buf[0] = (uint8_t)val; 974 buf[1] = (uint8_t)(val >> 8); 975 buf[2] = (uint8_t)(val >> 16); 976 buf[3] = (uint8_t)(val >> 24); 977 urtwn_write_region_1(sc, addr, buf, 4); 978 } 979 980 static int 981 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 982 { 983 984 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 985 device_xname(sc->sc_dev), __func__, addr, len)); 986 987 return urtwn_write_region_1(sc, addr, buf, len); 988 } 989 990 static int 991 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 992 int len) 993 { 994 usb_device_request_t req; 995 usbd_status error; 996 997 req.bmRequestType = UT_READ_VENDOR_DEVICE; 998 req.bRequest = R92C_REQ_REGS; 999 USETW(req.wValue, addr); 1000 USETW(req.wIndex, 0); 1001 USETW(req.wLength, len); 1002 error = usbd_do_request(sc->sc_udev, &req, buf); 1003 if (error != USBD_NORMAL_COMPLETION) { 1004 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1005 device_xname(sc->sc_dev), __func__, error, addr, len)); 1006 } 1007 return error; 1008 } 1009 1010 static uint8_t 1011 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1012 { 1013 uint8_t val; 1014 1015 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1016 return 0xff; 1017 1018 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1019 device_xname(sc->sc_dev), __func__, addr, val)); 1020 return val; 1021 } 1022 1023 static uint16_t 1024 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1025 { 1026 uint8_t buf[2]; 1027 uint16_t val; 1028 1029 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1030 return 0xffff; 1031 1032 val = LE_READ_2(&buf[0]); 1033 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1034 device_xname(sc->sc_dev), __func__, addr, val)); 1035 return val; 1036 } 1037 1038 static uint32_t 1039 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1040 { 1041 uint8_t buf[4]; 1042 uint32_t val; 1043 1044 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1045 return 0xffffffff; 1046 1047 val = LE_READ_4(&buf[0]); 1048 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1049 device_xname(sc->sc_dev), __func__, addr, val)); 1050 return val; 1051 } 1052 1053 static int 1054 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1055 { 1056 struct r92c_fw_cmd cmd; 1057 uint8_t *cp; 1058 int fwcur; 1059 int ntries; 1060 1061 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1062 device_xname(sc->sc_dev), __func__, id, buf, len)); 1063 1064 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1065 1066 mutex_enter(&sc->sc_fwcmd_mtx); 1067 fwcur = sc->fwcur; 1068 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1069 mutex_exit(&sc->sc_fwcmd_mtx); 1070 1071 /* Wait for current FW box to be empty. */ 1072 for (ntries = 0; ntries < 100; ntries++) { 1073 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1074 break; 1075 DELAY(2000); 1076 } 1077 if (ntries == 100) { 1078 aprint_error_dev(sc->sc_dev, 1079 "could not send firmware command %d\n", id); 1080 return ETIMEDOUT; 1081 } 1082 1083 memset(&cmd, 0, sizeof(cmd)); 1084 KASSERT(len <= sizeof(cmd.msg)); 1085 memcpy(cmd.msg, buf, len); 1086 1087 /* Write the first word last since that will trigger the FW. */ 1088 cp = (uint8_t *)&cmd; 1089 cmd.id = id; 1090 if (len >= 4) { 1091 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1092 cmd.id |= R92C_CMD_FLAG_EXT; 1093 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1094 &cp[1], 2); 1095 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1096 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1097 ((uint32_t)cp[5] << 24)); 1098 } else { 1099 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1100 &cp[4], 2); 1101 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1102 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1103 ((uint32_t)cp[3] << 24)); 1104 } 1105 } else { 1106 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1107 } 1108 1109 return 0; 1110 } 1111 1112 static __inline void 1113 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1114 { 1115 1116 sc->sc_rf_write(sc, chain, addr, val); 1117 } 1118 1119 static void 1120 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1121 uint32_t val) 1122 { 1123 1124 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1125 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1126 } 1127 1128 static void 1129 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1130 uint32_t val) 1131 { 1132 1133 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1134 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1135 } 1136 1137 static void 1138 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1139 uint32_t val) 1140 { 1141 1142 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1143 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1144 } 1145 1146 static uint32_t 1147 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1148 { 1149 uint32_t reg[R92C_MAX_CHAINS], val; 1150 1151 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1152 if (chain != 0) { 1153 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1154 } 1155 1156 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1157 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1158 DELAY(1000); 1159 1160 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1161 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1162 R92C_HSSI_PARAM2_READ_EDGE); 1163 DELAY(1000); 1164 1165 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1166 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1167 DELAY(1000); 1168 1169 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1170 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1171 } else { 1172 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1173 } 1174 return MS(val, R92C_LSSI_READBACK_DATA); 1175 } 1176 1177 static int 1178 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1179 { 1180 int ntries; 1181 1182 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1183 1184 urtwn_write_4(sc, R92C_LLT_INIT, 1185 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1186 SM(R92C_LLT_INIT_ADDR, addr) | 1187 SM(R92C_LLT_INIT_DATA, data)); 1188 /* Wait for write operation to complete. */ 1189 for (ntries = 0; ntries < 20; ntries++) { 1190 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1191 R92C_LLT_INIT_OP_NO_ACTIVE) { 1192 /* Done */ 1193 return 0; 1194 } 1195 DELAY(5); 1196 } 1197 return ETIMEDOUT; 1198 } 1199 1200 static uint8_t 1201 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1202 { 1203 uint32_t reg; 1204 int ntries; 1205 1206 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1207 1208 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1209 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1210 reg &= ~R92C_EFUSE_CTRL_VALID; 1211 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1212 1213 /* Wait for read operation to complete. */ 1214 for (ntries = 0; ntries < 100; ntries++) { 1215 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1216 if (reg & R92C_EFUSE_CTRL_VALID) { 1217 /* Done */ 1218 return MS(reg, R92C_EFUSE_CTRL_DATA); 1219 } 1220 DELAY(5); 1221 } 1222 aprint_error_dev(sc->sc_dev, 1223 "could not read efuse byte at address 0x%04x\n", addr); 1224 return 0xff; 1225 } 1226 1227 static void 1228 urtwn_efuse_read(struct urtwn_softc *sc) 1229 { 1230 uint8_t *rom = (uint8_t *)&sc->rom; 1231 uint32_t reg; 1232 uint16_t addr = 0; 1233 uint8_t off, msk; 1234 size_t i; 1235 1236 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1237 1238 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1239 1240 urtwn_efuse_switch_power(sc); 1241 1242 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1243 while (addr < 512) { 1244 reg = urtwn_efuse_read_1(sc, addr); 1245 if (reg == 0xff) 1246 break; 1247 addr++; 1248 off = reg >> 4; 1249 msk = reg & 0xf; 1250 for (i = 0; i < 4; i++) { 1251 if (msk & (1U << i)) 1252 continue; 1253 1254 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1255 addr++; 1256 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1257 addr++; 1258 } 1259 } 1260 #ifdef URTWN_DEBUG 1261 if (urtwn_debug & DBG_INIT) { 1262 /* Dump ROM content. */ 1263 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1264 for (i = 0; i < (int)sizeof(sc->rom); i++) 1265 printf(":%02x", rom[i]); 1266 printf("\n"); 1267 } 1268 #endif 1269 } 1270 1271 static void 1272 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1273 { 1274 uint32_t reg; 1275 1276 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1277 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1278 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1279 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1280 } 1281 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1282 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1283 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1284 reg | R92C_SYS_FUNC_EN_ELDR); 1285 } 1286 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1287 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1288 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1289 urtwn_write_2(sc, R92C_SYS_CLKR, 1290 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1291 } 1292 } 1293 1294 static int 1295 urtwn_read_chipid(struct urtwn_softc *sc) 1296 { 1297 uint32_t reg; 1298 1299 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1300 1301 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1302 ISSET(sc->chip, URTWN_CHIP_92EU)) 1303 return 0; 1304 1305 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1306 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1307 /* test chip, not supported */ 1308 return EIO; 1309 } 1310 if (reg & R92C_SYS_CFG_TYPE_92C) { 1311 sc->chip |= URTWN_CHIP_92C; 1312 /* Check if it is a castrated 8192C. */ 1313 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1314 R92C_HPON_FSM_CHIP_BONDING_ID) == 1315 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1316 sc->chip |= URTWN_CHIP_92C_1T2R; 1317 } 1318 } 1319 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1320 sc->chip |= URTWN_CHIP_UMC; 1321 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1322 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1323 } 1324 } 1325 return 0; 1326 } 1327 1328 #ifdef URTWN_DEBUG 1329 static void 1330 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1331 { 1332 1333 aprint_normal_dev(sc->sc_dev, 1334 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1335 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1336 1337 aprint_normal_dev(sc->sc_dev, 1338 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1339 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1340 1341 aprint_normal_dev(sc->sc_dev, 1342 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1343 rp->macaddr[0], rp->macaddr[1], 1344 rp->macaddr[2], rp->macaddr[3], 1345 rp->macaddr[4], rp->macaddr[5]); 1346 1347 aprint_normal_dev(sc->sc_dev, 1348 "string %s, subcustomer_id 0x%x\n", 1349 rp->string, rp->subcustomer_id); 1350 1351 aprint_normal_dev(sc->sc_dev, 1352 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1353 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1354 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1355 1356 aprint_normal_dev(sc->sc_dev, 1357 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1358 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1359 rp->ht40_1s_tx_pwr[0][2], 1360 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1361 rp->ht40_1s_tx_pwr[1][2]); 1362 1363 aprint_normal_dev(sc->sc_dev, 1364 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1365 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1366 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1367 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1368 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1369 1370 aprint_normal_dev(sc->sc_dev, 1371 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1372 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1373 rp->ht20_tx_pwr_diff[2] & 0xf, 1374 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1375 rp->ht20_tx_pwr_diff[2] >> 4); 1376 1377 aprint_normal_dev(sc->sc_dev, 1378 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1379 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1380 rp->ofdm_tx_pwr_diff[2] & 0xf, 1381 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1382 rp->ofdm_tx_pwr_diff[2] >> 4); 1383 1384 aprint_normal_dev(sc->sc_dev, 1385 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1386 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1387 rp->ht40_max_pwr[2] & 0xf, 1388 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1389 rp->ht40_max_pwr[2] >> 4); 1390 1391 aprint_normal_dev(sc->sc_dev, 1392 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1393 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1394 rp->ht20_max_pwr[2] & 0xf, 1395 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1396 rp->ht20_max_pwr[2] >> 4); 1397 1398 aprint_normal_dev(sc->sc_dev, 1399 "xtal_calib %d, tssi %d %d, thermal %d\n", 1400 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1401 1402 aprint_normal_dev(sc->sc_dev, 1403 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1404 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1405 1406 aprint_normal_dev(sc->sc_dev, 1407 "channnel_plan %d, version %d customer_id 0x%x\n", 1408 rp->channel_plan, rp->version, rp->curstomer_id); 1409 } 1410 #endif 1411 1412 static void 1413 urtwn_read_rom(struct urtwn_softc *sc) 1414 { 1415 struct ieee80211com *ic = &sc->sc_ic; 1416 struct r92c_rom *rom = &sc->rom; 1417 1418 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1419 1420 mutex_enter(&sc->sc_write_mtx); 1421 1422 /* Read full ROM image. */ 1423 urtwn_efuse_read(sc); 1424 #ifdef URTWN_DEBUG 1425 if (urtwn_debug & DBG_REG) 1426 urtwn_dump_rom(sc, rom); 1427 #endif 1428 1429 /* XXX Weird but this is what the vendor driver does. */ 1430 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1431 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1432 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1433 1434 DPRINTFN(DBG_INIT, 1435 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1436 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1437 sc->board_type, sc->regulatory)); 1438 1439 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1440 1441 sc->sc_rf_write = urtwn_r92c_rf_write; 1442 sc->sc_power_on = urtwn_r92c_power_on; 1443 sc->sc_dma_init = urtwn_r92c_dma_init; 1444 1445 mutex_exit(&sc->sc_write_mtx); 1446 } 1447 1448 static void 1449 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1450 { 1451 struct ieee80211com *ic = &sc->sc_ic; 1452 uint8_t *rom = sc->r88e_rom; 1453 uint32_t reg; 1454 uint16_t addr = 0; 1455 uint8_t off, msk, tmp; 1456 int i; 1457 1458 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1459 1460 mutex_enter(&sc->sc_write_mtx); 1461 1462 off = 0; 1463 urtwn_efuse_switch_power(sc); 1464 1465 /* Read full ROM image. */ 1466 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1467 while (addr < 4096) { 1468 reg = urtwn_efuse_read_1(sc, addr); 1469 if (reg == 0xff) 1470 break; 1471 addr++; 1472 if ((reg & 0x1f) == 0x0f) { 1473 tmp = (reg & 0xe0) >> 5; 1474 reg = urtwn_efuse_read_1(sc, addr); 1475 if ((reg & 0x0f) != 0x0f) 1476 off = ((reg & 0xf0) >> 1) | tmp; 1477 addr++; 1478 } else 1479 off = reg >> 4; 1480 msk = reg & 0xf; 1481 for (i = 0; i < 4; i++) { 1482 if (msk & (1 << i)) 1483 continue; 1484 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1485 addr++; 1486 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1487 addr++; 1488 } 1489 } 1490 #ifdef URTWN_DEBUG 1491 if (urtwn_debug & DBG_REG) { 1492 } 1493 #endif 1494 1495 addr = 0x10; 1496 for (i = 0; i < 6; i++) 1497 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1498 for (i = 0; i < 5; i++) 1499 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1500 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1501 if (sc->bw20_tx_pwr_diff & 0x08) 1502 sc->bw20_tx_pwr_diff |= 0xf0; 1503 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1504 if (sc->ofdm_tx_pwr_diff & 0x08) 1505 sc->ofdm_tx_pwr_diff |= 0xf0; 1506 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1507 1508 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1509 1510 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1511 sc->sc_power_on = urtwn_r92e_power_on; 1512 sc->sc_rf_write = urtwn_r92e_rf_write; 1513 } else { 1514 sc->sc_power_on = urtwn_r88e_power_on; 1515 sc->sc_rf_write = urtwn_r88e_rf_write; 1516 } 1517 sc->sc_dma_init = urtwn_r88e_dma_init; 1518 1519 mutex_exit(&sc->sc_write_mtx); 1520 } 1521 1522 static int 1523 urtwn_media_change(struct ifnet *ifp) 1524 { 1525 #ifdef URTWN_DEBUG 1526 struct urtwn_softc *sc = ifp->if_softc; 1527 #endif 1528 int error; 1529 1530 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1531 1532 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1533 return error; 1534 1535 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1536 (IFF_UP | IFF_RUNNING)) { 1537 urtwn_init(ifp); 1538 } 1539 return 0; 1540 } 1541 1542 /* 1543 * Initialize rate adaptation in firmware. 1544 */ 1545 static int 1546 urtwn_ra_init(struct urtwn_softc *sc) 1547 { 1548 static const uint8_t map[] = { 1549 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1550 }; 1551 struct ieee80211com *ic = &sc->sc_ic; 1552 struct ieee80211_node *ni = ic->ic_bss; 1553 struct ieee80211_rateset *rs = &ni->ni_rates; 1554 struct r92c_fw_cmd_macid_cfg cmd; 1555 uint32_t rates, basicrates; 1556 uint32_t rrsr_mask, rrsr_rate; 1557 uint8_t mode; 1558 size_t maxrate, maxbasicrate, i, j; 1559 int error; 1560 1561 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1562 1563 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1564 1565 /* Get normal and basic rates mask. */ 1566 rates = basicrates = 1; 1567 maxrate = maxbasicrate = 0; 1568 for (i = 0; i < rs->rs_nrates; i++) { 1569 /* Convert 802.11 rate to HW rate index. */ 1570 for (j = 0; j < __arraycount(map); j++) { 1571 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1572 break; 1573 } 1574 } 1575 if (j == __arraycount(map)) { 1576 /* Unknown rate, skip. */ 1577 continue; 1578 } 1579 1580 rates |= 1U << j; 1581 if (j > maxrate) { 1582 maxrate = j; 1583 } 1584 1585 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1586 basicrates |= 1U << j; 1587 if (j > maxbasicrate) { 1588 maxbasicrate = j; 1589 } 1590 } 1591 } 1592 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1593 mode = R92C_RAID_11B; 1594 } else { 1595 mode = R92C_RAID_11BG; 1596 } 1597 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1598 "maxrate=%zx, maxbasicrate=%zx\n", 1599 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1600 maxrate, maxbasicrate)); 1601 1602 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1603 maxbasicrate |= R92C_RATE_SHORTGI; 1604 maxrate |= R92C_RATE_SHORTGI; 1605 } 1606 1607 /* Set rates mask for group addressed frames. */ 1608 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1609 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1610 cmd.macid |= RTWN_MACID_SHORTGI; 1611 cmd.mask = htole32((mode << 28) | basicrates); 1612 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1613 if (error != 0) { 1614 aprint_error_dev(sc->sc_dev, 1615 "could not add broadcast station\n"); 1616 return error; 1617 } 1618 /* Set initial MRR rate. */ 1619 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1620 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1621 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1622 1623 /* Set rates mask for unicast frames. */ 1624 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1625 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1626 cmd.macid |= RTWN_MACID_SHORTGI; 1627 cmd.mask = htole32((mode << 28) | rates); 1628 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1629 if (error != 0) { 1630 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1631 return error; 1632 } 1633 /* Set initial MRR rate. */ 1634 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1635 __func__, maxrate)); 1636 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1637 1638 rrsr_rate = ic->ic_fixed_rate; 1639 if (rrsr_rate == -1) 1640 rrsr_rate = 11; 1641 1642 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1643 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1644 1645 /* Indicate highest supported rate. */ 1646 ni->ni_txrate = rs->rs_nrates - 1; 1647 1648 return 0; 1649 } 1650 1651 static int 1652 urtwn_get_nettype(struct urtwn_softc *sc) 1653 { 1654 struct ieee80211com *ic = &sc->sc_ic; 1655 int type; 1656 1657 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1658 1659 switch (ic->ic_opmode) { 1660 case IEEE80211_M_STA: 1661 type = R92C_CR_NETTYPE_INFRA; 1662 break; 1663 1664 case IEEE80211_M_IBSS: 1665 type = R92C_CR_NETTYPE_ADHOC; 1666 break; 1667 1668 default: 1669 type = R92C_CR_NETTYPE_NOLINK; 1670 break; 1671 } 1672 1673 return type; 1674 } 1675 1676 static void 1677 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1678 { 1679 uint8_t reg; 1680 1681 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1682 __func__, type)); 1683 1684 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1685 1686 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1687 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1688 } 1689 1690 static void 1691 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1692 { 1693 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1694 uint64_t tsf; 1695 1696 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1697 1698 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1699 1700 /* Enable TSF synchronization. */ 1701 urtwn_write_1(sc, R92C_BCN_CTRL, 1702 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1703 1704 /* Correct TSF */ 1705 urtwn_write_1(sc, R92C_BCN_CTRL, 1706 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1707 1708 /* Set initial TSF. */ 1709 tsf = ni->ni_tstamp.tsf; 1710 tsf = le64toh(tsf); 1711 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1712 tsf -= IEEE80211_DUR_TU; 1713 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1714 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1715 1716 urtwn_write_1(sc, R92C_BCN_CTRL, 1717 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1718 } 1719 1720 static void 1721 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1722 { 1723 uint8_t reg; 1724 1725 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1726 __func__, led, on)); 1727 1728 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1729 1730 if (led == URTWN_LED_LINK) { 1731 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1732 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1733 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1734 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1735 (R92C_LEDCFG0_DIS << 1)); 1736 if (on) { 1737 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1738 R92E_LEDSON; 1739 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1740 } 1741 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1742 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1743 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1744 if (!on) { 1745 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1746 urtwn_write_1(sc, R92C_LEDCFG2, 1747 reg | R92C_LEDCFG0_DIS); 1748 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1749 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1750 reg & 0xfe); 1751 } 1752 } else { 1753 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1754 if (!on) { 1755 reg |= R92C_LEDCFG0_DIS; 1756 } 1757 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1758 } 1759 sc->ledlink = on; /* Save LED state. */ 1760 } 1761 } 1762 1763 static void 1764 urtwn_calib_to(void *arg) 1765 { 1766 struct urtwn_softc *sc = arg; 1767 1768 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1769 1770 if (sc->sc_dying) 1771 return; 1772 1773 /* Do it in a process context. */ 1774 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1775 } 1776 1777 /* ARGSUSED */ 1778 static void 1779 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1780 { 1781 struct r92c_fw_cmd_rssi cmd; 1782 struct r92e_fw_cmd_rssi cmde; 1783 1784 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1785 1786 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1787 goto restart_timer; 1788 1789 mutex_enter(&sc->sc_write_mtx); 1790 if (sc->avg_pwdb != -1) { 1791 /* Indicate Rx signal strength to FW for rate adaptation. */ 1792 memset(&cmd, 0, sizeof(cmd)); 1793 memset(&cmde, 0, sizeof(cmde)); 1794 cmd.macid = 0; /* BSS. */ 1795 cmde.macid = 0; /* BSS. */ 1796 cmd.pwdb = sc->avg_pwdb; 1797 cmde.pwdb = sc->avg_pwdb; 1798 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1799 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1800 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1801 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1802 sizeof(cmd)); 1803 } else { 1804 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1805 sizeof(cmde)); 1806 } 1807 } 1808 1809 /* Do temperature compensation. */ 1810 urtwn_temp_calib(sc); 1811 mutex_exit(&sc->sc_write_mtx); 1812 1813 restart_timer: 1814 if (!sc->sc_dying) { 1815 /* Restart calibration timer. */ 1816 callout_schedule(&sc->sc_calib_to, hz); 1817 } 1818 } 1819 1820 static void 1821 urtwn_next_scan(void *arg) 1822 { 1823 struct urtwn_softc *sc = arg; 1824 int s; 1825 1826 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1827 1828 if (sc->sc_dying) 1829 return; 1830 1831 s = splnet(); 1832 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1833 ieee80211_next_scan(&sc->sc_ic); 1834 splx(s); 1835 } 1836 1837 static void 1838 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1839 { 1840 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1841 ether_sprintf(ni->ni_macaddr))); 1842 /* start with lowest Tx rate */ 1843 ni->ni_txrate = 0; 1844 } 1845 1846 static int 1847 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1848 { 1849 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1850 struct urtwn_cmd_newstate cmd; 1851 1852 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1853 device_xname(sc->sc_dev), __func__, 1854 ieee80211_state_name[nstate], nstate, arg)); 1855 1856 callout_stop(&sc->sc_scan_to); 1857 callout_stop(&sc->sc_calib_to); 1858 1859 /* Do it in a process context. */ 1860 cmd.state = nstate; 1861 cmd.arg = arg; 1862 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1863 return 0; 1864 } 1865 1866 static void 1867 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1868 { 1869 struct urtwn_cmd_newstate *cmd = arg; 1870 struct ieee80211com *ic = &sc->sc_ic; 1871 struct ieee80211_node *ni; 1872 enum ieee80211_state ostate = ic->ic_state; 1873 enum ieee80211_state nstate = cmd->state; 1874 uint32_t reg; 1875 uint8_t sifs_time, msr; 1876 int s; 1877 1878 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1879 device_xname(sc->sc_dev), __func__, 1880 ieee80211_state_name[ostate], ostate, 1881 ieee80211_state_name[nstate], nstate)); 1882 1883 s = splnet(); 1884 mutex_enter(&sc->sc_write_mtx); 1885 1886 callout_stop(&sc->sc_scan_to); 1887 callout_stop(&sc->sc_calib_to); 1888 1889 switch (ostate) { 1890 case IEEE80211_S_INIT: 1891 break; 1892 1893 case IEEE80211_S_SCAN: 1894 if (nstate != IEEE80211_S_SCAN) { 1895 /* 1896 * End of scanning 1897 */ 1898 /* flush 4-AC Queue after site_survey */ 1899 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1900 1901 /* Allow Rx from our BSSID only. */ 1902 urtwn_write_4(sc, R92C_RCR, 1903 urtwn_read_4(sc, R92C_RCR) | 1904 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1905 } 1906 break; 1907 1908 case IEEE80211_S_AUTH: 1909 case IEEE80211_S_ASSOC: 1910 break; 1911 1912 case IEEE80211_S_RUN: 1913 /* Turn link LED off. */ 1914 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1915 1916 /* Set media status to 'No Link'. */ 1917 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1918 1919 /* Stop Rx of data frames. */ 1920 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1921 1922 /* Reset TSF. */ 1923 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1924 1925 /* Disable TSF synchronization. */ 1926 urtwn_write_1(sc, R92C_BCN_CTRL, 1927 urtwn_read_1(sc, R92C_BCN_CTRL) | 1928 R92C_BCN_CTRL_DIS_TSF_UDT0); 1929 1930 /* Back to 20MHz mode */ 1931 urtwn_set_chan(sc, ic->ic_curchan, 1932 IEEE80211_HTINFO_2NDCHAN_NONE); 1933 1934 if (ic->ic_opmode == IEEE80211_M_IBSS || 1935 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1936 /* Stop BCN */ 1937 urtwn_write_1(sc, R92C_BCN_CTRL, 1938 urtwn_read_1(sc, R92C_BCN_CTRL) & 1939 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1940 } 1941 1942 /* Reset EDCA parameters. */ 1943 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1944 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1945 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1946 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1947 1948 /* flush all cam entries */ 1949 urtwn_cam_init(sc); 1950 break; 1951 } 1952 1953 switch (nstate) { 1954 case IEEE80211_S_INIT: 1955 /* Turn link LED off. */ 1956 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1957 break; 1958 1959 case IEEE80211_S_SCAN: 1960 if (ostate != IEEE80211_S_SCAN) { 1961 /* 1962 * Begin of scanning 1963 */ 1964 1965 /* Set gain for scanning. */ 1966 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1967 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1968 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1969 1970 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1971 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1972 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1973 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1974 } 1975 1976 /* Set media status to 'No Link'. */ 1977 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1978 1979 /* Allow Rx from any BSSID. */ 1980 urtwn_write_4(sc, R92C_RCR, 1981 urtwn_read_4(sc, R92C_RCR) & 1982 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1983 1984 /* Stop Rx of data frames. */ 1985 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1986 1987 /* Disable update TSF */ 1988 urtwn_write_1(sc, R92C_BCN_CTRL, 1989 urtwn_read_1(sc, R92C_BCN_CTRL) | 1990 R92C_BCN_CTRL_DIS_TSF_UDT0); 1991 } 1992 1993 /* Make link LED blink during scan. */ 1994 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1995 1996 /* Pause AC Tx queues. */ 1997 urtwn_write_1(sc, R92C_TXPAUSE, 1998 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1999 2000 urtwn_set_chan(sc, ic->ic_curchan, 2001 IEEE80211_HTINFO_2NDCHAN_NONE); 2002 2003 /* Start periodic scan. */ 2004 if (!sc->sc_dying) 2005 callout_schedule(&sc->sc_scan_to, hz / 5); 2006 break; 2007 2008 case IEEE80211_S_AUTH: 2009 /* Set initial gain under link. */ 2010 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2011 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2012 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2013 2014 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2015 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2016 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2017 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2018 } 2019 2020 /* Set media status to 'No Link'. */ 2021 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2022 2023 /* Allow Rx from any BSSID. */ 2024 urtwn_write_4(sc, R92C_RCR, 2025 urtwn_read_4(sc, R92C_RCR) & 2026 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2027 2028 urtwn_set_chan(sc, ic->ic_curchan, 2029 IEEE80211_HTINFO_2NDCHAN_NONE); 2030 break; 2031 2032 case IEEE80211_S_ASSOC: 2033 break; 2034 2035 case IEEE80211_S_RUN: 2036 ni = ic->ic_bss; 2037 2038 /* XXX: Set 20MHz mode */ 2039 urtwn_set_chan(sc, ic->ic_curchan, 2040 IEEE80211_HTINFO_2NDCHAN_NONE); 2041 2042 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2043 /* Back to 20MHz mode */ 2044 urtwn_set_chan(sc, ic->ic_curchan, 2045 IEEE80211_HTINFO_2NDCHAN_NONE); 2046 2047 /* Set media status to 'No Link'. */ 2048 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2049 2050 /* Enable Rx of data frames. */ 2051 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2052 2053 /* Allow Rx from any BSSID. */ 2054 urtwn_write_4(sc, R92C_RCR, 2055 urtwn_read_4(sc, R92C_RCR) & 2056 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2057 2058 /* Accept Rx data/control/management frames */ 2059 urtwn_write_4(sc, R92C_RCR, 2060 urtwn_read_4(sc, R92C_RCR) | 2061 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2062 2063 /* Turn link LED on. */ 2064 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2065 break; 2066 } 2067 2068 /* Set media status to 'Associated'. */ 2069 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2070 2071 /* Set BSSID. */ 2072 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2073 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2074 2075 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2076 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2077 } else { 2078 /* 802.11b/g */ 2079 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2080 } 2081 2082 /* Enable Rx of data frames. */ 2083 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2084 2085 /* Set beacon interval. */ 2086 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2087 2088 msr = urtwn_read_1(sc, R92C_MSR); 2089 msr &= R92C_MSR_MASK; 2090 switch (ic->ic_opmode) { 2091 case IEEE80211_M_STA: 2092 /* Allow Rx from our BSSID only. */ 2093 urtwn_write_4(sc, R92C_RCR, 2094 urtwn_read_4(sc, R92C_RCR) | 2095 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2096 2097 /* Enable TSF synchronization. */ 2098 urtwn_tsf_sync_enable(sc); 2099 2100 msr |= R92C_MSR_INFRA; 2101 break; 2102 case IEEE80211_M_HOSTAP: 2103 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2104 2105 /* Allow Rx from any BSSID. */ 2106 urtwn_write_4(sc, R92C_RCR, 2107 urtwn_read_4(sc, R92C_RCR) & 2108 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2109 2110 /* Reset TSF timer to zero. */ 2111 reg = urtwn_read_4(sc, R92C_TCR); 2112 reg &= ~0x01; 2113 urtwn_write_4(sc, R92C_TCR, reg); 2114 reg |= 0x01; 2115 urtwn_write_4(sc, R92C_TCR, reg); 2116 2117 msr |= R92C_MSR_AP; 2118 break; 2119 default: 2120 msr |= R92C_MSR_ADHOC; 2121 break; 2122 } 2123 urtwn_write_1(sc, R92C_MSR, msr); 2124 2125 sifs_time = 10; 2126 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2127 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2128 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2129 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2130 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2131 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2132 2133 /* Initialize rate adaptation. */ 2134 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2135 ISSET(sc->chip, URTWN_CHIP_92EU)) 2136 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2137 else 2138 urtwn_ra_init(sc); 2139 2140 /* Turn link LED on. */ 2141 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2142 2143 /* Reset average RSSI. */ 2144 sc->avg_pwdb = -1; 2145 2146 /* Reset temperature calibration state machine. */ 2147 sc->thcal_state = 0; 2148 sc->thcal_lctemp = 0; 2149 2150 /* Start periodic calibration. */ 2151 if (!sc->sc_dying) 2152 callout_schedule(&sc->sc_calib_to, hz); 2153 break; 2154 } 2155 2156 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2157 2158 mutex_exit(&sc->sc_write_mtx); 2159 splx(s); 2160 } 2161 2162 static int 2163 urtwn_wme_update(struct ieee80211com *ic) 2164 { 2165 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2166 2167 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2168 2169 /* don't override default WME values if WME is not actually enabled */ 2170 if (!(ic->ic_flags & IEEE80211_F_WME)) 2171 return 0; 2172 2173 /* Do it in a process context. */ 2174 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2175 return 0; 2176 } 2177 2178 static void 2179 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2180 { 2181 static const uint16_t ac2reg[WME_NUM_AC] = { 2182 R92C_EDCA_BE_PARAM, 2183 R92C_EDCA_BK_PARAM, 2184 R92C_EDCA_VI_PARAM, 2185 R92C_EDCA_VO_PARAM 2186 }; 2187 struct ieee80211com *ic = &sc->sc_ic; 2188 const struct wmeParams *wmep; 2189 int ac, aifs, slottime; 2190 int s; 2191 2192 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2193 __func__)); 2194 2195 s = splnet(); 2196 mutex_enter(&sc->sc_write_mtx); 2197 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2198 for (ac = 0; ac < WME_NUM_AC; ac++) { 2199 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2200 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2201 aifs = wmep->wmep_aifsn * slottime + 10; 2202 urtwn_write_4(sc, ac2reg[ac], 2203 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2204 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2205 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2206 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2207 } 2208 mutex_exit(&sc->sc_write_mtx); 2209 splx(s); 2210 } 2211 2212 static void 2213 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2214 { 2215 int pwdb; 2216 2217 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2218 device_xname(sc->sc_dev), __func__, rate, rssi)); 2219 2220 /* Convert antenna signal to percentage. */ 2221 if (rssi <= -100 || rssi >= 20) 2222 pwdb = 0; 2223 else if (rssi >= 0) 2224 pwdb = 100; 2225 else 2226 pwdb = 100 + rssi; 2227 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2228 if (rate <= 3) { 2229 /* CCK gain is smaller than OFDM/MCS gain. */ 2230 pwdb += 6; 2231 if (pwdb > 100) 2232 pwdb = 100; 2233 if (pwdb <= 14) 2234 pwdb -= 4; 2235 else if (pwdb <= 26) 2236 pwdb -= 8; 2237 else if (pwdb <= 34) 2238 pwdb -= 6; 2239 else if (pwdb <= 42) 2240 pwdb -= 2; 2241 } 2242 } 2243 if (sc->avg_pwdb == -1) /* Init. */ 2244 sc->avg_pwdb = pwdb; 2245 else if (sc->avg_pwdb < pwdb) 2246 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2247 else 2248 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2249 2250 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2251 device_xname(sc->sc_dev), __func__, 2252 rate, rssi, pwdb, sc->avg_pwdb)); 2253 } 2254 2255 static int8_t 2256 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2257 { 2258 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2259 struct r92c_rx_phystat *phy; 2260 struct r92c_rx_cck *cck; 2261 uint8_t rpt; 2262 int8_t rssi; 2263 2264 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2265 __func__, rate)); 2266 2267 if (rate <= 3) { 2268 cck = (struct r92c_rx_cck *)physt; 2269 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2270 rpt = (cck->agc_rpt >> 5) & 0x3; 2271 rssi = (cck->agc_rpt & 0x1f) << 1; 2272 } else { 2273 rpt = (cck->agc_rpt >> 6) & 0x3; 2274 rssi = cck->agc_rpt & 0x3e; 2275 } 2276 rssi = cckoff[rpt] - rssi; 2277 } else { /* OFDM/HT. */ 2278 phy = (struct r92c_rx_phystat *)physt; 2279 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2280 } 2281 return rssi; 2282 } 2283 2284 static int8_t 2285 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2286 { 2287 struct r92c_rx_phystat *phy; 2288 struct r88e_rx_cck *cck; 2289 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2290 int8_t rssi; 2291 2292 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2293 __func__, rate)); 2294 2295 rssi = 0; 2296 if (rate <= 3) { 2297 cck = (struct r88e_rx_cck *)physt; 2298 cck_agc_rpt = cck->agc_rpt; 2299 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2300 vga_idx = cck_agc_rpt & 0x1f; 2301 switch (lna_idx) { 2302 case 7: 2303 if (vga_idx <= 27) 2304 rssi = -100 + 2* (27 - vga_idx); 2305 else 2306 rssi = -100; 2307 break; 2308 case 6: 2309 rssi = -48 + 2 * (2 - vga_idx); 2310 break; 2311 case 5: 2312 rssi = -42 + 2 * (7 - vga_idx); 2313 break; 2314 case 4: 2315 rssi = -36 + 2 * (7 - vga_idx); 2316 break; 2317 case 3: 2318 rssi = -24 + 2 * (7 - vga_idx); 2319 break; 2320 case 2: 2321 rssi = -12 + 2 * (5 - vga_idx); 2322 break; 2323 case 1: 2324 rssi = 8 - (2 * vga_idx); 2325 break; 2326 case 0: 2327 rssi = 14 - (2 * vga_idx); 2328 break; 2329 } 2330 rssi += 6; 2331 } else { /* OFDM/HT. */ 2332 phy = (struct r92c_rx_phystat *)physt; 2333 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2334 } 2335 return rssi; 2336 } 2337 2338 static void 2339 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2340 { 2341 struct ieee80211com *ic = &sc->sc_ic; 2342 struct ifnet *ifp = ic->ic_ifp; 2343 struct ieee80211_frame *wh; 2344 struct ieee80211_node *ni; 2345 struct r92c_rx_desc_usb *stat; 2346 uint32_t rxdw0, rxdw3; 2347 struct mbuf *m; 2348 uint8_t rate; 2349 int8_t rssi = 0; 2350 int s, infosz; 2351 2352 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2353 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2354 2355 stat = (struct r92c_rx_desc_usb *)buf; 2356 rxdw0 = le32toh(stat->rxdw0); 2357 rxdw3 = le32toh(stat->rxdw3); 2358 2359 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2360 /* 2361 * This should not happen since we setup our Rx filter 2362 * to not receive these frames. 2363 */ 2364 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2365 device_xname(sc->sc_dev), __func__)); 2366 ifp->if_ierrors++; 2367 return; 2368 } 2369 /* 2370 * XXX: This will drop most control packets. Do we really 2371 * want this in IEEE80211_M_MONITOR mode? 2372 */ 2373 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2374 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2375 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2376 device_xname(sc->sc_dev), __func__, pktlen)); 2377 ic->ic_stats.is_rx_tooshort++; 2378 ifp->if_ierrors++; 2379 return; 2380 } 2381 if (__predict_false(pktlen > MCLBYTES)) { 2382 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2383 device_xname(sc->sc_dev), __func__, pktlen)); 2384 ifp->if_ierrors++; 2385 return; 2386 } 2387 2388 rate = MS(rxdw3, R92C_RXDW3_RATE); 2389 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2390 2391 /* Get RSSI from PHY status descriptor if present. */ 2392 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2393 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2394 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2395 else 2396 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2397 /* Update our average RSSI. */ 2398 urtwn_update_avgrssi(sc, rate, rssi); 2399 } 2400 2401 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2402 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2403 2404 MGETHDR(m, M_DONTWAIT, MT_DATA); 2405 if (__predict_false(m == NULL)) { 2406 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2407 ic->ic_stats.is_rx_nobuf++; 2408 ifp->if_ierrors++; 2409 return; 2410 } 2411 if (pktlen > (int)MHLEN) { 2412 MCLGET(m, M_DONTWAIT); 2413 if (__predict_false(!(m->m_flags & M_EXT))) { 2414 aprint_error_dev(sc->sc_dev, 2415 "couldn't allocate rx mbuf cluster\n"); 2416 m_freem(m); 2417 ic->ic_stats.is_rx_nobuf++; 2418 ifp->if_ierrors++; 2419 return; 2420 } 2421 } 2422 2423 /* Finalize mbuf. */ 2424 m_set_rcvif(m, ifp); 2425 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2426 memcpy(mtod(m, uint8_t *), wh, pktlen); 2427 m->m_pkthdr.len = m->m_len = pktlen; 2428 2429 s = splnet(); 2430 if (__predict_false(sc->sc_drvbpf != NULL)) { 2431 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2432 2433 tap->wr_flags = 0; 2434 if (!(rxdw3 & R92C_RXDW3_HT)) { 2435 switch (rate) { 2436 /* CCK. */ 2437 case 0: tap->wr_rate = 2; break; 2438 case 1: tap->wr_rate = 4; break; 2439 case 2: tap->wr_rate = 11; break; 2440 case 3: tap->wr_rate = 22; break; 2441 /* OFDM. */ 2442 case 4: tap->wr_rate = 12; break; 2443 case 5: tap->wr_rate = 18; break; 2444 case 6: tap->wr_rate = 24; break; 2445 case 7: tap->wr_rate = 36; break; 2446 case 8: tap->wr_rate = 48; break; 2447 case 9: tap->wr_rate = 72; break; 2448 case 10: tap->wr_rate = 96; break; 2449 case 11: tap->wr_rate = 108; break; 2450 } 2451 } else if (rate >= 12) { /* MCS0~15. */ 2452 /* Bit 7 set means HT MCS instead of rate. */ 2453 tap->wr_rate = 0x80 | (rate - 12); 2454 } 2455 tap->wr_dbm_antsignal = rssi; 2456 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2457 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2458 2459 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2460 } 2461 2462 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2463 2464 /* push the frame up to the 802.11 stack */ 2465 ieee80211_input(ic, m, ni, rssi, 0); 2466 2467 /* Node is no longer needed. */ 2468 ieee80211_free_node(ni); 2469 2470 splx(s); 2471 } 2472 2473 static void 2474 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2475 { 2476 struct urtwn_rx_data *data = priv; 2477 struct urtwn_softc *sc = data->sc; 2478 struct r92c_rx_desc_usb *stat; 2479 size_t pidx = data->pidx; 2480 uint32_t rxdw0; 2481 uint8_t *buf; 2482 int len, totlen, pktlen, infosz, npkts; 2483 2484 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2485 device_xname(sc->sc_dev), __func__, status)); 2486 2487 mutex_enter(&sc->sc_rx_mtx); 2488 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2489 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2490 /* Put this Rx buffer back to our free list. */ 2491 mutex_exit(&sc->sc_rx_mtx); 2492 2493 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2494 if (status == USBD_STALLED) 2495 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2496 else if (status != USBD_CANCELLED) 2497 goto resubmit; 2498 return; 2499 } 2500 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2501 2502 if (__predict_false(len < (int)sizeof(*stat))) { 2503 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2504 device_xname(sc->sc_dev), __func__, len)); 2505 goto resubmit; 2506 } 2507 buf = data->buf; 2508 2509 /* Get the number of encapsulated frames. */ 2510 stat = (struct r92c_rx_desc_usb *)buf; 2511 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2512 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2513 device_xname(sc->sc_dev), __func__, npkts)); 2514 2515 if (npkts != 0) 2516 rnd_add_uint32(&sc->rnd_source, npkts); 2517 2518 /* Process all of them. */ 2519 while (npkts-- > 0) { 2520 if (__predict_false(len < (int)sizeof(*stat))) { 2521 DPRINTFN(DBG_RX, 2522 ("%s: %s: len(%d) is short than header\n", 2523 device_xname(sc->sc_dev), __func__, len)); 2524 break; 2525 } 2526 stat = (struct r92c_rx_desc_usb *)buf; 2527 rxdw0 = le32toh(stat->rxdw0); 2528 2529 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2530 if (__predict_false(pktlen == 0)) { 2531 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2532 device_xname(sc->sc_dev), __func__)); 2533 break; 2534 } 2535 2536 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2537 2538 /* Make sure everything fits in xfer. */ 2539 totlen = sizeof(*stat) + infosz + pktlen; 2540 if (__predict_false(totlen > len)) { 2541 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2542 device_xname(sc->sc_dev), __func__, totlen, 2543 (int)sizeof(*stat), infosz, pktlen, len)); 2544 break; 2545 } 2546 2547 /* Process 802.11 frame. */ 2548 urtwn_rx_frame(sc, buf, pktlen); 2549 2550 /* Next chunk is 128-byte aligned. */ 2551 totlen = roundup2(totlen, 128); 2552 buf += totlen; 2553 len -= totlen; 2554 } 2555 2556 resubmit: 2557 /* Setup a new transfer. */ 2558 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2559 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2560 (void)usbd_transfer(xfer); 2561 } 2562 2563 static void 2564 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2565 { 2566 struct urtwn_tx_data *data = priv; 2567 struct urtwn_softc *sc = data->sc; 2568 struct ifnet *ifp = &sc->sc_if; 2569 size_t pidx = data->pidx; 2570 int s; 2571 2572 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2573 device_xname(sc->sc_dev), __func__, status)); 2574 2575 mutex_enter(&sc->sc_tx_mtx); 2576 /* Put this Tx buffer back to our free list. */ 2577 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2578 mutex_exit(&sc->sc_tx_mtx); 2579 2580 s = splnet(); 2581 sc->tx_timer = 0; 2582 ifp->if_flags &= ~IFF_OACTIVE; 2583 2584 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2585 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2586 if (status == USBD_STALLED) { 2587 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2588 usbd_clear_endpoint_stall_async(pipe); 2589 } 2590 printf("ERROR1\n"); 2591 ifp->if_oerrors++; 2592 } 2593 splx(s); 2594 return; 2595 } 2596 2597 ifp->if_opackets++; 2598 urtwn_start(ifp); 2599 splx(s); 2600 2601 } 2602 2603 static int 2604 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2605 struct urtwn_tx_data *data) 2606 { 2607 struct ieee80211com *ic = &sc->sc_ic; 2608 struct ieee80211_frame *wh; 2609 struct ieee80211_key *k = NULL; 2610 struct r92c_tx_desc_usb *txd; 2611 size_t i, padsize, xferlen, txd_len; 2612 uint16_t seq, sum; 2613 uint8_t raid, type, tid; 2614 int s, hasqos, error; 2615 2616 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2617 2618 wh = mtod(m, struct ieee80211_frame *); 2619 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2620 txd_len = sizeof(*txd); 2621 2622 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2623 txd_len = 32; 2624 2625 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2626 k = ieee80211_crypto_encap(ic, ni, m); 2627 if (k == NULL) 2628 return ENOBUFS; 2629 2630 /* packet header may have moved, reset our local pointer */ 2631 wh = mtod(m, struct ieee80211_frame *); 2632 } 2633 2634 if (__predict_false(sc->sc_drvbpf != NULL)) { 2635 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2636 2637 tap->wt_flags = 0; 2638 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2639 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2640 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2641 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2642 2643 /* XXX: set tap->wt_rate? */ 2644 2645 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2646 } 2647 2648 /* non-qos data frames */ 2649 tid = R92C_TXDW1_QSEL_BE; 2650 if ((hasqos = ieee80211_has_qos(wh))) { 2651 /* data frames in 11n mode */ 2652 struct ieee80211_qosframe *qwh = (void *)wh; 2653 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2654 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2655 tid = R92C_TXDW1_QSEL_MGNT; 2656 } 2657 2658 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2659 padsize = 8; 2660 else 2661 padsize = 0; 2662 2663 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2664 padsize = 0; 2665 2666 /* Fill Tx descriptor. */ 2667 txd = (struct r92c_tx_desc_usb *)data->buf; 2668 memset(txd, 0, txd_len + padsize); 2669 2670 txd->txdw0 |= htole32( 2671 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2672 SM(R92C_TXDW0_OFFSET, txd_len)); 2673 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2674 txd->txdw0 |= htole32( 2675 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2676 } 2677 2678 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2679 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2680 2681 /* fix pad field */ 2682 if (padsize > 0) { 2683 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2684 device_xname(sc->sc_dev), __func__, padsize)); 2685 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2686 } 2687 2688 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2689 type == IEEE80211_FC0_TYPE_DATA) { 2690 if (ic->ic_curmode == IEEE80211_MODE_11B) 2691 raid = R92C_RAID_11B; 2692 else 2693 raid = R92C_RAID_11BG; 2694 DPRINTFN(DBG_TX, 2695 ("%s: %s: data packet: tid=%d, raid=%d\n", 2696 device_xname(sc->sc_dev), __func__, tid, raid)); 2697 2698 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2699 txd->txdw1 |= htole32( 2700 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2701 SM(R92C_TXDW1_QSEL, tid) | 2702 SM(R92C_TXDW1_RAID, raid) | 2703 R92C_TXDW1_AGGBK); 2704 } else 2705 txd->txdw1 |= htole32( 2706 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2707 SM(R92C_TXDW1_QSEL, tid) | 2708 SM(R92C_TXDW1_RAID, raid) | 2709 R92C_TXDW1_AGGBK); 2710 2711 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2712 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2713 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2714 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2715 2716 if (hasqos) { 2717 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2718 } 2719 2720 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2721 /* for 11g */ 2722 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2723 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2724 R92C_TXDW4_HWRTSEN); 2725 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2726 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2727 R92C_TXDW4_HWRTSEN); 2728 } 2729 } 2730 /* Send RTS at OFDM24. */ 2731 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2732 txd->txdw5 |= htole32(0x0001ff00); 2733 /* Send data at OFDM54. */ 2734 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2735 txd->txdw5 |= htole32(0x13 & 0x3f); 2736 else 2737 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2738 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2739 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2740 device_xname(sc->sc_dev), __func__)); 2741 txd->txdw1 |= htole32( 2742 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2743 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2744 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2745 2746 /* Force CCK1. */ 2747 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2748 /* Use 1Mbps */ 2749 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2750 } else { 2751 /* broadcast or multicast packets */ 2752 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2753 device_xname(sc->sc_dev), __func__)); 2754 txd->txdw1 |= htole32( 2755 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2756 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2757 2758 /* Force CCK1. */ 2759 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2760 /* Use 1Mbps */ 2761 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2762 } 2763 /* Set sequence number */ 2764 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2765 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2766 txd->txdseq |= htole16(seq); 2767 2768 if (!hasqos) { 2769 /* Use HW sequence numbering for non-QoS frames. */ 2770 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2771 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2772 } 2773 } else { 2774 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2775 R92E_HWSEQ_SHIFT); 2776 if (!hasqos) { 2777 /* Use HW sequence numbering for non-QoS frames. */ 2778 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2779 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2780 } 2781 } 2782 2783 /* Compute Tx descriptor checksum. */ 2784 sum = 0; 2785 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2786 sum ^= ((uint16_t *)txd)[i]; 2787 txd->txdsum = sum; /* NB: already little endian. */ 2788 2789 xferlen = txd_len + m->m_pkthdr.len + padsize; 2790 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2791 2792 s = splnet(); 2793 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2794 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2795 urtwn_txeof); 2796 error = usbd_transfer(data->xfer); 2797 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2798 error != USBD_IN_PROGRESS)) { 2799 splx(s); 2800 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2801 device_xname(sc->sc_dev), __func__, error)); 2802 return error; 2803 } 2804 splx(s); 2805 return 0; 2806 } 2807 2808 struct urtwn_tx_data * 2809 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2810 { 2811 struct urtwn_tx_data *data = NULL; 2812 2813 mutex_enter(&sc->sc_tx_mtx); 2814 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2815 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2816 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2817 } 2818 mutex_exit(&sc->sc_tx_mtx); 2819 2820 return data; 2821 } 2822 2823 static void 2824 urtwn_start(struct ifnet *ifp) 2825 { 2826 struct urtwn_softc *sc = ifp->if_softc; 2827 struct ieee80211com *ic = &sc->sc_ic; 2828 struct urtwn_tx_data *data; 2829 struct ether_header *eh; 2830 struct ieee80211_node *ni; 2831 struct mbuf *m; 2832 2833 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2834 2835 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2836 return; 2837 2838 data = NULL; 2839 for (;;) { 2840 /* Send pending management frames first. */ 2841 IF_POLL(&ic->ic_mgtq, m); 2842 if (m != NULL) { 2843 /* Use AC_VO for management frames. */ 2844 2845 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2846 2847 if (data == NULL) { 2848 ifp->if_flags |= IFF_OACTIVE; 2849 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2850 device_xname(sc->sc_dev))); 2851 return; 2852 } 2853 IF_DEQUEUE(&ic->ic_mgtq, m); 2854 ni = M_GETCTX(m, struct ieee80211_node *); 2855 M_CLEARCTX(m); 2856 goto sendit; 2857 } 2858 if (ic->ic_state != IEEE80211_S_RUN) 2859 break; 2860 2861 /* Encapsulate and send data frames. */ 2862 IFQ_POLL(&ifp->if_snd, m); 2863 if (m == NULL) 2864 break; 2865 2866 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2867 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2868 uint8_t qid = WME_AC_BE; 2869 if (ieee80211_has_qos(wh)) { 2870 /* data frames in 11n mode */ 2871 struct ieee80211_qosframe *qwh = (void *)wh; 2872 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2873 qid = TID_TO_WME_AC(tid); 2874 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2875 qid = WME_AC_VO; 2876 } 2877 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2878 2879 if (data == NULL) { 2880 ifp->if_flags |= IFF_OACTIVE; 2881 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2882 device_xname(sc->sc_dev))); 2883 return; 2884 } 2885 IFQ_DEQUEUE(&ifp->if_snd, m); 2886 2887 if (m->m_len < (int)sizeof(*eh) && 2888 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2889 printf("ERROR6\n"); 2890 ifp->if_oerrors++; 2891 continue; 2892 } 2893 eh = mtod(m, struct ether_header *); 2894 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2895 if (ni == NULL) { 2896 m_freem(m); 2897 printf("ERROR5\n"); 2898 ifp->if_oerrors++; 2899 continue; 2900 } 2901 2902 bpf_mtap(ifp, m, BPF_D_OUT); 2903 2904 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2905 ieee80211_free_node(ni); 2906 printf("ERROR4\n"); 2907 ifp->if_oerrors++; 2908 continue; 2909 } 2910 sendit: 2911 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2912 2913 if (urtwn_tx(sc, m, ni, data) != 0) { 2914 m_freem(m); 2915 ieee80211_free_node(ni); 2916 printf("ERROR3\n"); 2917 ifp->if_oerrors++; 2918 continue; 2919 } 2920 m_freem(m); 2921 ieee80211_free_node(ni); 2922 sc->tx_timer = 5; 2923 ifp->if_timer = 1; 2924 } 2925 } 2926 2927 static void 2928 urtwn_watchdog(struct ifnet *ifp) 2929 { 2930 struct urtwn_softc *sc = ifp->if_softc; 2931 2932 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2933 2934 ifp->if_timer = 0; 2935 2936 if (sc->tx_timer > 0) { 2937 if (--sc->tx_timer == 0) { 2938 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2939 /* urtwn_init(ifp); XXX needs a process context! */ 2940 printf("ERROR2\n"); 2941 ifp->if_oerrors++; 2942 return; 2943 } 2944 ifp->if_timer = 1; 2945 } 2946 ieee80211_watchdog(&sc->sc_ic); 2947 } 2948 2949 static int 2950 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2951 { 2952 struct urtwn_softc *sc = ifp->if_softc; 2953 struct ieee80211com *ic = &sc->sc_ic; 2954 int s, error = 0; 2955 2956 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2957 device_xname(sc->sc_dev), __func__, cmd, data)); 2958 2959 s = splnet(); 2960 2961 switch (cmd) { 2962 case SIOCSIFFLAGS: 2963 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2964 break; 2965 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2966 case IFF_UP | IFF_RUNNING: 2967 break; 2968 case IFF_UP: 2969 urtwn_init(ifp); 2970 break; 2971 case IFF_RUNNING: 2972 urtwn_stop(ifp, 1); 2973 break; 2974 case 0: 2975 break; 2976 } 2977 break; 2978 2979 case SIOCADDMULTI: 2980 case SIOCDELMULTI: 2981 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2982 /* setup multicast filter, etc */ 2983 error = 0; 2984 } 2985 break; 2986 2987 case SIOCS80211CHANNEL: 2988 /* 2989 * This allows for fast channel switching in monitor mode 2990 * (used by kismet). In IBSS mode, we must explicitly reset 2991 * the interface to generate a new beacon frame. 2992 */ 2993 error = ieee80211_ioctl(ic, cmd, data); 2994 if (error == ENETRESET && 2995 ic->ic_opmode == IEEE80211_M_MONITOR) { 2996 urtwn_set_chan(sc, ic->ic_curchan, 2997 IEEE80211_HTINFO_2NDCHAN_NONE); 2998 error = 0; 2999 } 3000 break; 3001 3002 default: 3003 error = ieee80211_ioctl(ic, cmd, data); 3004 break; 3005 } 3006 if (error == ENETRESET) { 3007 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3008 (IFF_UP | IFF_RUNNING) && 3009 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3010 urtwn_init(ifp); 3011 } 3012 error = 0; 3013 } 3014 3015 splx(s); 3016 3017 return error; 3018 } 3019 3020 static __inline int 3021 urtwn_power_on(struct urtwn_softc *sc) 3022 { 3023 3024 return sc->sc_power_on(sc); 3025 } 3026 3027 static int 3028 urtwn_r92c_power_on(struct urtwn_softc *sc) 3029 { 3030 uint32_t reg; 3031 int ntries; 3032 3033 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3034 3035 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3036 3037 /* Wait for autoload done bit. */ 3038 for (ntries = 0; ntries < 1000; ntries++) { 3039 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3040 break; 3041 DELAY(5); 3042 } 3043 if (ntries == 1000) { 3044 aprint_error_dev(sc->sc_dev, 3045 "timeout waiting for chip autoload\n"); 3046 return ETIMEDOUT; 3047 } 3048 3049 /* Unlock ISO/CLK/Power control register. */ 3050 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3051 /* Move SPS into PWM mode. */ 3052 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3053 DELAY(5); 3054 3055 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3056 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3057 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3058 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3059 DELAY(100); 3060 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3061 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3062 ~R92C_SYS_ISO_CTRL_MD2PP); 3063 } 3064 3065 /* Auto enable WLAN. */ 3066 urtwn_write_2(sc, R92C_APS_FSMCO, 3067 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3068 for (ntries = 0; ntries < 1000; ntries++) { 3069 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3070 R92C_APS_FSMCO_APFM_ONMAC)) 3071 break; 3072 DELAY(100); 3073 } 3074 if (ntries == 1000) { 3075 aprint_error_dev(sc->sc_dev, 3076 "timeout waiting for MAC auto ON\n"); 3077 return ETIMEDOUT; 3078 } 3079 3080 /* Enable radio, GPIO and LED functions. */ 3081 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3082 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3083 urtwn_write_2(sc, R92C_APS_FSMCO, 3084 R92C_APS_FSMCO_AFSM_HSUS | 3085 R92C_APS_FSMCO_PDN_EN | 3086 R92C_APS_FSMCO_PFM_ALDN); 3087 3088 /* Release RF digital isolation. */ 3089 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3090 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3091 3092 /* Initialize MAC. */ 3093 urtwn_write_1(sc, R92C_APSD_CTRL, 3094 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3095 for (ntries = 0; ntries < 200; ntries++) { 3096 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3097 R92C_APSD_CTRL_OFF_STATUS)) 3098 break; 3099 DELAY(5); 3100 } 3101 if (ntries == 200) { 3102 aprint_error_dev(sc->sc_dev, 3103 "timeout waiting for MAC initialization\n"); 3104 return ETIMEDOUT; 3105 } 3106 3107 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3108 reg = urtwn_read_2(sc, R92C_CR); 3109 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3110 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3111 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3112 R92C_CR_ENSEC; 3113 urtwn_write_2(sc, R92C_CR, reg); 3114 3115 urtwn_write_1(sc, 0xfe10, 0x19); 3116 return 0; 3117 } 3118 3119 static int 3120 urtwn_r92e_power_on(struct urtwn_softc *sc) 3121 { 3122 uint32_t reg; 3123 uint32_t val; 3124 int ntries; 3125 3126 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3127 3128 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3129 3130 /* Enable radio, GPIO and LED functions. */ 3131 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3132 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3133 urtwn_write_2(sc, R92C_APS_FSMCO, 3134 R92C_APS_FSMCO_AFSM_HSUS | 3135 R92C_APS_FSMCO_PDN_EN | 3136 R92C_APS_FSMCO_PFM_ALDN); 3137 3138 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3139 /* LDO. */ 3140 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3141 } 3142 else { 3143 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3144 R92C_SYS_SWR_CTRL2) & 0xffff); 3145 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3146 } 3147 3148 for (ntries = 0; ntries < 2; ntries++) { 3149 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3150 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3151 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3152 R92C_AFE_CTRL4)); 3153 } 3154 3155 /* Reset BB. */ 3156 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3157 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3158 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3159 3160 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3161 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3162 3163 /* Disable HWPDN. */ 3164 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3165 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3166 3167 /* Disable WL suspend. */ 3168 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3169 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3170 R92C_APS_FSMCO_AFSM_HSUS)); 3171 3172 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3173 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3174 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3175 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3176 for (ntries = 0; ntries < 10000; ntries++) { 3177 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3178 R92C_APS_FSMCO_APFM_ONMAC; 3179 if (val == 0x0) 3180 break; 3181 DELAY(10); 3182 } 3183 if (ntries == 10000) { 3184 aprint_error_dev(sc->sc_dev, 3185 "timeout waiting for chip power up\n"); 3186 return ETIMEDOUT; 3187 } 3188 3189 urtwn_write_2(sc, R92C_CR, 0x00); 3190 reg = urtwn_read_2(sc, R92C_CR); 3191 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3192 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3193 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3194 urtwn_write_2(sc, R92C_CR, reg); 3195 3196 return 0; 3197 } 3198 3199 static int 3200 urtwn_r88e_power_on(struct urtwn_softc *sc) 3201 { 3202 uint32_t reg; 3203 uint8_t val; 3204 int ntries; 3205 3206 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3207 3208 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3209 3210 /* Wait for power ready bit. */ 3211 for (ntries = 0; ntries < 5000; ntries++) { 3212 val = urtwn_read_1(sc, 0x6) & 0x2; 3213 if (val == 0x2) 3214 break; 3215 DELAY(10); 3216 } 3217 if (ntries == 5000) { 3218 aprint_error_dev(sc->sc_dev, 3219 "timeout waiting for chip power up\n"); 3220 return ETIMEDOUT; 3221 } 3222 3223 /* Reset BB. */ 3224 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3225 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3226 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3227 3228 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3229 3230 /* Disable HWPDN. */ 3231 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3232 3233 /* Disable WL suspend. */ 3234 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3235 3236 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3237 for (ntries = 0; ntries < 5000; ntries++) { 3238 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3239 break; 3240 DELAY(10); 3241 } 3242 if (ntries == 5000) 3243 return ETIMEDOUT; 3244 3245 /* Enable LDO normal mode. */ 3246 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3247 3248 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3249 urtwn_write_2(sc, R92C_CR, 0); 3250 reg = urtwn_read_2(sc, R92C_CR); 3251 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3252 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3253 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3254 urtwn_write_2(sc, R92C_CR, reg); 3255 3256 return 0; 3257 } 3258 3259 static int 3260 urtwn_llt_init(struct urtwn_softc *sc) 3261 { 3262 size_t i, page_count, pktbuf_count; 3263 uint32_t val; 3264 int error; 3265 3266 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3267 3268 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3269 3270 if (sc->chip & URTWN_CHIP_88E) 3271 page_count = R88E_TX_PAGE_COUNT; 3272 else if (sc->chip & URTWN_CHIP_92EU) 3273 page_count = R92E_TX_PAGE_COUNT; 3274 else 3275 page_count = R92C_TX_PAGE_COUNT; 3276 if (sc->chip & URTWN_CHIP_88E) 3277 pktbuf_count = R88E_TXPKTBUF_COUNT; 3278 else if (sc->chip & URTWN_CHIP_92EU) 3279 pktbuf_count = R88E_TXPKTBUF_COUNT; 3280 else 3281 pktbuf_count = R92C_TXPKTBUF_COUNT; 3282 3283 if (sc->chip & URTWN_CHIP_92EU) { 3284 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3285 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3286 DELAY(100); 3287 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3288 if (val & R92E_AUTO_LLT_EN) 3289 return EIO; 3290 return 0; 3291 } 3292 3293 /* Reserve pages [0; page_count]. */ 3294 for (i = 0; i < page_count; i++) { 3295 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3296 return error; 3297 } 3298 /* NB: 0xff indicates end-of-list. */ 3299 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3300 return error; 3301 /* 3302 * Use pages [page_count + 1; pktbuf_count - 1] 3303 * as ring buffer. 3304 */ 3305 for (++i; i < pktbuf_count - 1; i++) { 3306 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3307 return error; 3308 } 3309 /* Make the last page point to the beginning of the ring buffer. */ 3310 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3311 return error; 3312 } 3313 3314 static void 3315 urtwn_fw_reset(struct urtwn_softc *sc) 3316 { 3317 uint16_t reg; 3318 int ntries; 3319 3320 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3321 3322 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3323 3324 /* Tell 8051 to reset itself. */ 3325 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3326 3327 /* Wait until 8051 resets by itself. */ 3328 for (ntries = 0; ntries < 100; ntries++) { 3329 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3330 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3331 return; 3332 DELAY(50); 3333 } 3334 /* Force 8051 reset. */ 3335 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3336 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3337 } 3338 3339 static void 3340 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3341 { 3342 uint16_t reg; 3343 3344 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3345 3346 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3347 3348 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3349 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3350 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3351 } 3352 DELAY(50); 3353 3354 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3355 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3356 DELAY(50); 3357 3358 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3359 DELAY(50); 3360 3361 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3362 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3363 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3364 } 3365 DELAY(50); 3366 3367 } 3368 3369 static int 3370 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3371 { 3372 uint32_t reg; 3373 int off, mlen, error = 0; 3374 3375 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3376 device_xname(sc->sc_dev), __func__, page, buf, len)); 3377 3378 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3379 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3380 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3381 3382 off = R92C_FW_START_ADDR; 3383 while (len > 0) { 3384 if (len > 196) 3385 mlen = 196; 3386 else if (len > 4) 3387 mlen = 4; 3388 else 3389 mlen = 1; 3390 error = urtwn_write_region(sc, off, buf, mlen); 3391 if (error != 0) 3392 break; 3393 off += mlen; 3394 buf += mlen; 3395 len -= mlen; 3396 } 3397 return error; 3398 } 3399 3400 static int 3401 urtwn_load_firmware(struct urtwn_softc *sc) 3402 { 3403 firmware_handle_t fwh; 3404 const struct r92c_fw_hdr *hdr; 3405 const char *name; 3406 u_char *fw, *ptr; 3407 size_t len; 3408 uint32_t reg; 3409 int mlen, ntries, page, error; 3410 3411 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3412 3413 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3414 3415 /* Read firmware image from the filesystem. */ 3416 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3417 name = "rtl8188eufw.bin"; 3418 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3419 name = "rtl8192eefw.bin"; 3420 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3421 URTWN_CHIP_UMC_A_CUT) 3422 name = "rtl8192cfwU.bin"; 3423 else 3424 name = "rtl8192cfw.bin"; 3425 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3426 aprint_error_dev(sc->sc_dev, 3427 "failed load firmware of file %s (error %d)\n", name, 3428 error); 3429 return error; 3430 } 3431 const size_t fwlen = len = firmware_get_size(fwh); 3432 fw = firmware_malloc(len); 3433 if (fw == NULL) { 3434 aprint_error_dev(sc->sc_dev, 3435 "failed to allocate firmware memory\n"); 3436 firmware_close(fwh); 3437 return ENOMEM; 3438 } 3439 error = firmware_read(fwh, 0, fw, len); 3440 firmware_close(fwh); 3441 if (error != 0) { 3442 aprint_error_dev(sc->sc_dev, 3443 "failed to read firmware (error %d)\n", error); 3444 firmware_free(fw, fwlen); 3445 return error; 3446 } 3447 3448 len = fwlen; 3449 ptr = fw; 3450 hdr = (const struct r92c_fw_hdr *)ptr; 3451 /* Check if there is a valid FW header and skip it. */ 3452 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3453 (le16toh(hdr->signature) >> 4) == 0x88e || 3454 (le16toh(hdr->signature) >> 4) == 0x92e || 3455 (le16toh(hdr->signature) >> 4) == 0x92c) { 3456 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3457 device_xname(sc->sc_dev), __func__, 3458 le16toh(hdr->version), le16toh(hdr->subversion), 3459 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3460 ptr += sizeof(*hdr); 3461 len -= sizeof(*hdr); 3462 } 3463 3464 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3465 /* Reset MCU ready status */ 3466 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3467 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3468 ISSET(sc->chip, URTWN_CHIP_92EU)) 3469 urtwn_r88e_fw_reset(sc); 3470 else 3471 urtwn_fw_reset(sc); 3472 } 3473 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3474 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3475 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3476 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3477 R92C_SYS_FUNC_EN_CPUEN); 3478 } 3479 3480 /* download enabled */ 3481 urtwn_write_1(sc, R92C_MCUFWDL, 3482 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3483 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3484 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3485 3486 /* Reset the FWDL checksum. */ 3487 urtwn_write_1(sc, R92C_MCUFWDL, 3488 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3489 3490 DELAY(50); 3491 /* download firmware */ 3492 for (page = 0; len > 0; page++) { 3493 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3494 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3495 if (error != 0) { 3496 aprint_error_dev(sc->sc_dev, 3497 "could not load firmware page %d\n", page); 3498 goto fail; 3499 } 3500 ptr += mlen; 3501 len -= mlen; 3502 } 3503 3504 /* download disable */ 3505 urtwn_write_1(sc, R92C_MCUFWDL, 3506 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3507 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3508 3509 /* Wait for checksum report. */ 3510 for (ntries = 0; ntries < 1000; ntries++) { 3511 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3512 break; 3513 DELAY(5); 3514 } 3515 if (ntries == 1000) { 3516 aprint_error_dev(sc->sc_dev, 3517 "timeout waiting for checksum report\n"); 3518 error = ETIMEDOUT; 3519 goto fail; 3520 } 3521 3522 /* Wait for firmware readiness. */ 3523 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3524 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3525 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3526 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3527 ISSET(sc->chip, URTWN_CHIP_92EU)) 3528 urtwn_r88e_fw_reset(sc); 3529 for (ntries = 0; ntries < 6000; ntries++) { 3530 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3531 break; 3532 DELAY(5); 3533 } 3534 if (ntries == 6000) { 3535 aprint_error_dev(sc->sc_dev, 3536 "timeout waiting for firmware readiness\n"); 3537 error = ETIMEDOUT; 3538 goto fail; 3539 } 3540 fail: 3541 firmware_free(fw, fwlen); 3542 return error; 3543 } 3544 3545 static __inline int 3546 urtwn_dma_init(struct urtwn_softc *sc) 3547 { 3548 3549 return sc->sc_dma_init(sc); 3550 } 3551 3552 static int 3553 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3554 { 3555 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3556 uint32_t reg; 3557 int error; 3558 3559 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3560 3561 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3562 3563 /* Initialize LLT table. */ 3564 error = urtwn_llt_init(sc); 3565 if (error != 0) 3566 return error; 3567 3568 /* Get Tx queues to USB endpoints mapping. */ 3569 hashq = hasnq = haslq = 0; 3570 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3571 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3572 device_xname(sc->sc_dev), __func__, reg)); 3573 if (MS(reg, R92C_USB_EP_HQ) != 0) 3574 hashq = 1; 3575 if (MS(reg, R92C_USB_EP_NQ) != 0) 3576 hasnq = 1; 3577 if (MS(reg, R92C_USB_EP_LQ) != 0) 3578 haslq = 1; 3579 nqueues = hashq + hasnq + haslq; 3580 if (nqueues == 0) 3581 return EIO; 3582 /* Get the number of pages for each queue. */ 3583 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3584 /* The remaining pages are assigned to the high priority queue. */ 3585 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3586 3587 /* Set number of pages for normal priority queue. */ 3588 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3589 urtwn_write_4(sc, R92C_RQPN, 3590 /* Set number of pages for public queue. */ 3591 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3592 /* Set number of pages for high priority queue. */ 3593 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3594 /* Set number of pages for low priority queue. */ 3595 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3596 /* Load values. */ 3597 R92C_RQPN_LD); 3598 3599 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3600 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3601 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3602 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3603 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3604 3605 /* Set queue to USB pipe mapping. */ 3606 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3607 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3608 if (nqueues == 1) { 3609 if (hashq) { 3610 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3611 } else if (hasnq) { 3612 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3613 } else { 3614 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3615 } 3616 } else if (nqueues == 2) { 3617 /* All 2-endpoints configs have a high priority queue. */ 3618 if (!hashq) { 3619 return EIO; 3620 } 3621 if (hasnq) { 3622 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3623 } else { 3624 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3625 } 3626 } else { 3627 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3628 } 3629 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3630 3631 /* Set Tx/Rx transfer page boundary. */ 3632 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3633 3634 /* Set Tx/Rx transfer page size. */ 3635 urtwn_write_1(sc, R92C_PBP, 3636 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3637 return 0; 3638 } 3639 3640 static int 3641 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3642 { 3643 usb_interface_descriptor_t *id; 3644 uint32_t reg; 3645 int nqueues; 3646 int error; 3647 3648 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3649 3650 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3651 3652 /* Initialize LLT table. */ 3653 error = urtwn_llt_init(sc); 3654 if (error != 0) 3655 return error; 3656 3657 /* Get Tx queues to USB endpoints mapping. */ 3658 id = usbd_get_interface_descriptor(sc->sc_iface); 3659 nqueues = id->bNumEndpoints - 1; 3660 if (nqueues == 0) 3661 return EIO; 3662 3663 /* Set number of pages for normal priority queue. */ 3664 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3665 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3666 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3667 3668 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3669 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3670 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3671 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3672 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3673 3674 /* Set queue to USB pipe mapping. */ 3675 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3676 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3677 if (nqueues == 1) 3678 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3679 else if (nqueues == 2) 3680 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3681 else 3682 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3683 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3684 3685 /* Set Tx/Rx transfer page boundary. */ 3686 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3687 3688 /* Set Tx/Rx transfer page size. */ 3689 urtwn_write_1(sc, R92C_PBP, 3690 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3691 3692 return 0; 3693 } 3694 3695 static void 3696 urtwn_mac_init(struct urtwn_softc *sc) 3697 { 3698 size_t i; 3699 3700 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3701 3702 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3703 3704 /* Write MAC initialization values. */ 3705 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3706 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3707 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3708 rtl8188eu_mac[i].val); 3709 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3710 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3711 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3712 rtl8192eu_mac[i].val); 3713 } else { 3714 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3715 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3716 rtl8192cu_mac[i].val); 3717 } 3718 } 3719 3720 static void 3721 urtwn_bb_init(struct urtwn_softc *sc) 3722 { 3723 const struct rtwn_bb_prog *prog; 3724 uint32_t reg; 3725 uint8_t crystalcap; 3726 size_t i; 3727 3728 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3729 3730 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3731 3732 /* Enable BB and RF. */ 3733 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3734 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3735 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3736 R92C_SYS_FUNC_EN_DIO_RF); 3737 3738 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3739 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3740 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3741 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3742 } 3743 3744 urtwn_write_1(sc, R92C_RF_CTRL, 3745 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3746 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3747 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3748 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3749 3750 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3751 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3752 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3753 urtwn_write_1(sc, 0x15, 0xe9); 3754 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3755 } 3756 3757 /* Select BB programming based on board type. */ 3758 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3759 prog = &rtl8188eu_bb_prog; 3760 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3761 prog = &rtl8192eu_bb_prog; 3762 else if (!(sc->chip & URTWN_CHIP_92C)) { 3763 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3764 prog = &rtl8188ce_bb_prog; 3765 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3766 prog = &rtl8188ru_bb_prog; 3767 } else { 3768 prog = &rtl8188cu_bb_prog; 3769 } 3770 } else { 3771 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3772 prog = &rtl8192ce_bb_prog; 3773 } else { 3774 prog = &rtl8192cu_bb_prog; 3775 } 3776 } 3777 /* Write BB initialization values. */ 3778 for (i = 0; i < prog->count; i++) { 3779 /* additional delay depend on registers */ 3780 switch (prog->regs[i]) { 3781 case 0xfe: 3782 urtwn_delay_ms(sc, 50); 3783 break; 3784 case 0xfd: 3785 urtwn_delay_ms(sc, 5); 3786 break; 3787 case 0xfc: 3788 urtwn_delay_ms(sc, 1); 3789 break; 3790 case 0xfb: 3791 DELAY(50); 3792 break; 3793 case 0xfa: 3794 DELAY(5); 3795 break; 3796 case 0xf9: 3797 DELAY(1); 3798 break; 3799 } 3800 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3801 DELAY(1); 3802 } 3803 3804 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3805 /* 8192C 1T only configuration. */ 3806 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3807 reg = (reg & ~0x00000003) | 0x2; 3808 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3809 3810 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3811 reg = (reg & ~0x00300033) | 0x00200022; 3812 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3813 3814 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3815 reg = (reg & ~0xff000000) | (0x45 << 24); 3816 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3817 3818 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3819 reg = (reg & ~0x000000ff) | 0x23; 3820 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3821 3822 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3823 reg = (reg & ~0x00000030) | (1 << 4); 3824 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3825 3826 reg = urtwn_bb_read(sc, 0xe74); 3827 reg = (reg & ~0x0c000000) | (2 << 26); 3828 urtwn_bb_write(sc, 0xe74, reg); 3829 reg = urtwn_bb_read(sc, 0xe78); 3830 reg = (reg & ~0x0c000000) | (2 << 26); 3831 urtwn_bb_write(sc, 0xe78, reg); 3832 reg = urtwn_bb_read(sc, 0xe7c); 3833 reg = (reg & ~0x0c000000) | (2 << 26); 3834 urtwn_bb_write(sc, 0xe7c, reg); 3835 reg = urtwn_bb_read(sc, 0xe80); 3836 reg = (reg & ~0x0c000000) | (2 << 26); 3837 urtwn_bb_write(sc, 0xe80, reg); 3838 reg = urtwn_bb_read(sc, 0xe88); 3839 reg = (reg & ~0x0c000000) | (2 << 26); 3840 urtwn_bb_write(sc, 0xe88, reg); 3841 } 3842 3843 /* Write AGC values. */ 3844 for (i = 0; i < prog->agccount; i++) { 3845 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3846 DELAY(1); 3847 } 3848 3849 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3850 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3851 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3852 DELAY(1); 3853 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3854 DELAY(1); 3855 } 3856 3857 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3858 crystalcap = sc->r88e_rom[0xb9]; 3859 if (crystalcap == 0x00) 3860 crystalcap = 0x20; 3861 crystalcap &= 0x3f; 3862 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3863 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3864 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3865 crystalcap | crystalcap << 6)); 3866 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3867 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3868 crystalcap = sc->r88e_rom[0xb9]; 3869 if (crystalcap == 0xff) 3870 crystalcap = 0x20; 3871 crystalcap &= 0x3f; 3872 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3873 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3874 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3875 crystalcap | crystalcap << 6)); 3876 } else { 3877 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3878 R92C_HSSI_PARAM2_CCK_HIPWR) { 3879 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3880 } 3881 } 3882 } 3883 3884 static void 3885 urtwn_rf_init(struct urtwn_softc *sc) 3886 { 3887 const struct rtwn_rf_prog *prog; 3888 uint32_t reg, mask, saved; 3889 size_t i, j, idx; 3890 3891 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3892 3893 /* Select RF programming based on board type. */ 3894 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3895 prog = rtl8188eu_rf_prog; 3896 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3897 prog = rtl8192eu_rf_prog; 3898 else if (!(sc->chip & URTWN_CHIP_92C)) { 3899 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3900 prog = rtl8188ce_rf_prog; 3901 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3902 prog = rtl8188ru_rf_prog; 3903 } else { 3904 prog = rtl8188cu_rf_prog; 3905 } 3906 } else { 3907 prog = rtl8192ce_rf_prog; 3908 } 3909 3910 for (i = 0; i < sc->nrxchains; i++) { 3911 /* Save RF_ENV control type. */ 3912 idx = i / 2; 3913 mask = 0xffffU << ((i % 2) * 16); 3914 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3915 3916 /* Set RF_ENV enable. */ 3917 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3918 reg |= 0x100000; 3919 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3920 DELAY(50); 3921 3922 /* Set RF_ENV output high. */ 3923 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3924 reg |= 0x10; 3925 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3926 DELAY(50); 3927 3928 /* Set address and data lengths of RF registers. */ 3929 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3930 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3931 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3932 DELAY(50); 3933 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3934 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3935 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3936 DELAY(50); 3937 3938 /* Write RF initialization values for this chain. */ 3939 for (j = 0; j < prog[i].count; j++) { 3940 if (prog[i].regs[j] >= 0xf9 && 3941 prog[i].regs[j] <= 0xfe) { 3942 /* 3943 * These are fake RF registers offsets that 3944 * indicate a delay is required. 3945 */ 3946 urtwn_delay_ms(sc, 50); 3947 continue; 3948 } 3949 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3950 DELAY(5); 3951 } 3952 3953 /* Restore RF_ENV control type. */ 3954 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3955 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3956 } 3957 3958 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3959 URTWN_CHIP_UMC_A_CUT) { 3960 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3961 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3962 } 3963 3964 /* Cache RF register CHNLBW. */ 3965 for (i = 0; i < 2; i++) { 3966 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3967 } 3968 } 3969 3970 static void 3971 urtwn_cam_init(struct urtwn_softc *sc) 3972 { 3973 uint32_t content, command; 3974 uint8_t idx; 3975 size_t i; 3976 3977 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3978 3979 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3980 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3981 return; 3982 3983 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3984 content = (idx & 3) 3985 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3986 | R92C_CAM_VALID; 3987 3988 command = R92C_CAMCMD_POLLING 3989 | R92C_CAMCMD_WRITE 3990 | R92C_CAM_CTL0(idx); 3991 3992 urtwn_write_4(sc, R92C_CAMWRITE, content); 3993 urtwn_write_4(sc, R92C_CAMCMD, command); 3994 } 3995 3996 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3997 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3998 if (i == 0) { 3999 content = (idx & 3) 4000 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4001 | R92C_CAM_VALID; 4002 } else { 4003 content = 0; 4004 } 4005 4006 command = R92C_CAMCMD_POLLING 4007 | R92C_CAMCMD_WRITE 4008 | R92C_CAM_CTL0(idx) 4009 | i; 4010 4011 urtwn_write_4(sc, R92C_CAMWRITE, content); 4012 urtwn_write_4(sc, R92C_CAMCMD, command); 4013 } 4014 } 4015 4016 /* Invalidate all CAM entries. */ 4017 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4018 } 4019 4020 static void 4021 urtwn_pa_bias_init(struct urtwn_softc *sc) 4022 { 4023 uint8_t reg; 4024 size_t i; 4025 4026 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4027 4028 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4029 4030 for (i = 0; i < sc->nrxchains; i++) { 4031 if (sc->pa_setting & (1U << i)) 4032 continue; 4033 4034 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4035 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4036 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4037 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4038 } 4039 if (!(sc->pa_setting & 0x10)) { 4040 reg = urtwn_read_1(sc, 0x16); 4041 reg = (reg & ~0xf0) | 0x90; 4042 urtwn_write_1(sc, 0x16, reg); 4043 } 4044 } 4045 4046 static void 4047 urtwn_rxfilter_init(struct urtwn_softc *sc) 4048 { 4049 4050 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4051 4052 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4053 4054 /* Initialize Rx filter. */ 4055 /* TODO: use better filter for monitor mode. */ 4056 urtwn_write_4(sc, R92C_RCR, 4057 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4058 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4059 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4060 /* Accept all multicast frames. */ 4061 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4062 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4063 /* Accept all management frames. */ 4064 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4065 /* Reject all control frames. */ 4066 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4067 /* Accept all data frames. */ 4068 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4069 } 4070 4071 static void 4072 urtwn_edca_init(struct urtwn_softc *sc) 4073 { 4074 4075 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4076 4077 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4078 4079 /* set spec SIFS (used in NAV) */ 4080 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4081 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4082 4083 /* set SIFS CCK/OFDM */ 4084 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4085 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4086 4087 /* TXOP */ 4088 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4089 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4090 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4091 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4092 } 4093 4094 static void 4095 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4096 uint16_t power[URTWN_RIDX_COUNT]) 4097 { 4098 uint32_t reg; 4099 4100 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4101 __func__, chain)); 4102 4103 /* Write per-CCK rate Tx power. */ 4104 if (chain == 0) { 4105 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4106 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4107 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4108 4109 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4110 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4111 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4112 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4113 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4114 } else { 4115 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4116 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4117 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4118 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4119 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4120 4121 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4122 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4123 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4124 } 4125 /* Write per-OFDM rate Tx power. */ 4126 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4127 SM(R92C_TXAGC_RATE06, power[ 4]) | 4128 SM(R92C_TXAGC_RATE09, power[ 5]) | 4129 SM(R92C_TXAGC_RATE12, power[ 6]) | 4130 SM(R92C_TXAGC_RATE18, power[ 7])); 4131 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4132 SM(R92C_TXAGC_RATE24, power[ 8]) | 4133 SM(R92C_TXAGC_RATE36, power[ 9]) | 4134 SM(R92C_TXAGC_RATE48, power[10]) | 4135 SM(R92C_TXAGC_RATE54, power[11])); 4136 /* Write per-MCS Tx power. */ 4137 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4138 SM(R92C_TXAGC_MCS00, power[12]) | 4139 SM(R92C_TXAGC_MCS01, power[13]) | 4140 SM(R92C_TXAGC_MCS02, power[14]) | 4141 SM(R92C_TXAGC_MCS03, power[15])); 4142 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4143 SM(R92C_TXAGC_MCS04, power[16]) | 4144 SM(R92C_TXAGC_MCS05, power[17]) | 4145 SM(R92C_TXAGC_MCS06, power[18]) | 4146 SM(R92C_TXAGC_MCS07, power[19])); 4147 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4148 SM(R92C_TXAGC_MCS08, power[20]) | 4149 SM(R92C_TXAGC_MCS09, power[21]) | 4150 SM(R92C_TXAGC_MCS10, power[22]) | 4151 SM(R92C_TXAGC_MCS11, power[23])); 4152 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4153 SM(R92C_TXAGC_MCS12, power[24]) | 4154 SM(R92C_TXAGC_MCS13, power[25]) | 4155 SM(R92C_TXAGC_MCS14, power[26]) | 4156 SM(R92C_TXAGC_MCS15, power[27])); 4157 } 4158 4159 static void 4160 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4161 uint16_t power[URTWN_RIDX_COUNT]) 4162 { 4163 struct r92c_rom *rom = &sc->rom; 4164 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4165 const struct rtwn_txpwr *base; 4166 int ridx, group; 4167 4168 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4169 device_xname(sc->sc_dev), __func__, chain, chan)); 4170 4171 /* Determine channel group. */ 4172 if (chan <= 3) { 4173 group = 0; 4174 } else if (chan <= 9) { 4175 group = 1; 4176 } else { 4177 group = 2; 4178 } 4179 4180 /* Get original Tx power based on board type and RF chain. */ 4181 if (!(sc->chip & URTWN_CHIP_92C)) { 4182 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4183 base = &rtl8188ru_txagc[chain]; 4184 } else { 4185 base = &rtl8192cu_txagc[chain]; 4186 } 4187 } else { 4188 base = &rtl8192cu_txagc[chain]; 4189 } 4190 4191 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4192 if (sc->regulatory == 0) { 4193 for (ridx = 0; ridx <= 3; ridx++) { 4194 power[ridx] = base->pwr[0][ridx]; 4195 } 4196 } 4197 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4198 if (sc->regulatory == 3) { 4199 power[ridx] = base->pwr[0][ridx]; 4200 /* Apply vendor limits. */ 4201 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4202 maxpow = rom->ht40_max_pwr[group]; 4203 } else { 4204 maxpow = rom->ht20_max_pwr[group]; 4205 } 4206 maxpow = (maxpow >> (chain * 4)) & 0xf; 4207 if (power[ridx] > maxpow) { 4208 power[ridx] = maxpow; 4209 } 4210 } else if (sc->regulatory == 1) { 4211 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4212 power[ridx] = base->pwr[group][ridx]; 4213 } 4214 } else if (sc->regulatory != 2) { 4215 power[ridx] = base->pwr[0][ridx]; 4216 } 4217 } 4218 4219 /* Compute per-CCK rate Tx power. */ 4220 cckpow = rom->cck_tx_pwr[chain][group]; 4221 for (ridx = 0; ridx <= 3; ridx++) { 4222 power[ridx] += cckpow; 4223 if (power[ridx] > R92C_MAX_TX_PWR) { 4224 power[ridx] = R92C_MAX_TX_PWR; 4225 } 4226 } 4227 4228 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4229 if (sc->ntxchains > 1) { 4230 /* Apply reduction for 2 spatial streams. */ 4231 diff = rom->ht40_2s_tx_pwr_diff[group]; 4232 diff = (diff >> (chain * 4)) & 0xf; 4233 htpow = (htpow > diff) ? htpow - diff : 0; 4234 } 4235 4236 /* Compute per-OFDM rate Tx power. */ 4237 diff = rom->ofdm_tx_pwr_diff[group]; 4238 diff = (diff >> (chain * 4)) & 0xf; 4239 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4240 for (ridx = 4; ridx <= 11; ridx++) { 4241 power[ridx] += ofdmpow; 4242 if (power[ridx] > R92C_MAX_TX_PWR) { 4243 power[ridx] = R92C_MAX_TX_PWR; 4244 } 4245 } 4246 4247 /* Compute per-MCS Tx power. */ 4248 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4249 diff = rom->ht20_tx_pwr_diff[group]; 4250 diff = (diff >> (chain * 4)) & 0xf; 4251 htpow += diff; /* HT40->HT20 correction. */ 4252 } 4253 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4254 power[ridx] += htpow; 4255 if (power[ridx] > R92C_MAX_TX_PWR) { 4256 power[ridx] = R92C_MAX_TX_PWR; 4257 } 4258 } 4259 #ifdef URTWN_DEBUG 4260 if (urtwn_debug & DBG_RF) { 4261 /* Dump per-rate Tx power values. */ 4262 printf("%s: %s: Tx power for chain %zd:\n", 4263 device_xname(sc->sc_dev), __func__, chain); 4264 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4265 printf("%s: %s: Rate %d = %u\n", 4266 device_xname(sc->sc_dev), __func__, ridx, 4267 power[ridx]); 4268 } 4269 } 4270 #endif 4271 } 4272 4273 void 4274 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4275 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4276 { 4277 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4278 const struct rtwn_r88e_txpwr *base; 4279 int ridx, group; 4280 4281 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4282 device_xname(sc->sc_dev), __func__, chain, chan)); 4283 4284 /* Determine channel group. */ 4285 if (chan <= 2) 4286 group = 0; 4287 else if (chan <= 5) 4288 group = 1; 4289 else if (chan <= 8) 4290 group = 2; 4291 else if (chan <= 11) 4292 group = 3; 4293 else if (chan <= 13) 4294 group = 4; 4295 else 4296 group = 5; 4297 4298 /* Get original Tx power based on board type and RF chain. */ 4299 base = &rtl8188eu_txagc[chain]; 4300 4301 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4302 if (sc->regulatory == 0) { 4303 for (ridx = 0; ridx <= 3; ridx++) 4304 power[ridx] = base->pwr[0][ridx]; 4305 } 4306 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4307 if (sc->regulatory == 3) 4308 power[ridx] = base->pwr[0][ridx]; 4309 else if (sc->regulatory == 1) { 4310 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4311 power[ridx] = base->pwr[group][ridx]; 4312 } else if (sc->regulatory != 2) 4313 power[ridx] = base->pwr[0][ridx]; 4314 } 4315 4316 /* Compute per-CCK rate Tx power. */ 4317 cckpow = sc->cck_tx_pwr[group]; 4318 for (ridx = 0; ridx <= 3; ridx++) { 4319 power[ridx] += cckpow; 4320 if (power[ridx] > R92C_MAX_TX_PWR) 4321 power[ridx] = R92C_MAX_TX_PWR; 4322 } 4323 4324 htpow = sc->ht40_tx_pwr[group]; 4325 4326 /* Compute per-OFDM rate Tx power. */ 4327 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4328 for (ridx = 4; ridx <= 11; ridx++) { 4329 power[ridx] += ofdmpow; 4330 if (power[ridx] > R92C_MAX_TX_PWR) 4331 power[ridx] = R92C_MAX_TX_PWR; 4332 } 4333 4334 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4335 for (ridx = 12; ridx <= 27; ridx++) { 4336 power[ridx] += bw20pow; 4337 if (power[ridx] > R92C_MAX_TX_PWR) 4338 power[ridx] = R92C_MAX_TX_PWR; 4339 } 4340 } 4341 4342 static void 4343 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4344 { 4345 uint16_t power[URTWN_RIDX_COUNT]; 4346 size_t i; 4347 4348 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4349 4350 for (i = 0; i < sc->ntxchains; i++) { 4351 /* Compute per-rate Tx power values. */ 4352 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4353 ISSET(sc->chip, URTWN_CHIP_92EU)) 4354 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4355 else 4356 urtwn_get_txpower(sc, i, chan, ht40m, power); 4357 /* Write per-rate Tx power values to hardware. */ 4358 urtwn_write_txpower(sc, i, power); 4359 } 4360 } 4361 4362 static void 4363 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4364 { 4365 struct ieee80211com *ic = &sc->sc_ic; 4366 u_int chan; 4367 size_t i; 4368 4369 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4370 4371 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4372 __func__, chan)); 4373 4374 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4375 4376 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4377 chan += 2; 4378 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4379 chan -= 2; 4380 } 4381 4382 /* Set Tx power for this new channel. */ 4383 urtwn_set_txpower(sc, chan, ht40m); 4384 4385 for (i = 0; i < sc->nrxchains; i++) { 4386 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4387 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4388 } 4389 4390 if (ht40m) { 4391 /* Is secondary channel below or above primary? */ 4392 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4393 uint32_t reg; 4394 4395 urtwn_write_1(sc, R92C_BWOPMODE, 4396 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4397 4398 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4399 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4400 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4401 4402 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4403 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4404 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4405 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4406 4407 /* Set CCK side band. */ 4408 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4409 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4410 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4411 4412 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4413 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4414 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4415 4416 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4417 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4418 ~R92C_FPGA0_ANAPARAM2_CBW20); 4419 4420 reg = urtwn_bb_read(sc, 0x818); 4421 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4422 urtwn_bb_write(sc, 0x818, reg); 4423 4424 /* Select 40MHz bandwidth. */ 4425 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4426 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4427 } else { 4428 urtwn_write_1(sc, R92C_BWOPMODE, 4429 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4430 4431 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4432 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4433 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4434 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4435 4436 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4437 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4438 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4439 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4440 R92C_FPGA0_ANAPARAM2_CBW20); 4441 } 4442 4443 /* Select 20MHz bandwidth. */ 4444 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4445 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4446 (ISSET(sc->chip, URTWN_CHIP_88E) || 4447 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4448 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4449 } 4450 } 4451 4452 static void 4453 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4454 { 4455 4456 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4457 __func__, inited)); 4458 4459 uint32_t addaBackup[16], iqkBackup[4], piMode; 4460 4461 #ifdef notyet 4462 uint32_t odfm0_agccore_regs[3]; 4463 uint32_t ant_regs[3]; 4464 uint32_t rf_regs[8]; 4465 #endif 4466 uint32_t reg0, reg1, reg2; 4467 int i, attempt; 4468 4469 #ifdef notyet 4470 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4471 R92E_STBC_SETTING + 2)); 4472 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4473 /* Save AGCCORE regs. */ 4474 for (i = 0; i < sc->nrxchains; i++) { 4475 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4476 R92C_OFDM0_AGCCORE1(i)); 4477 } 4478 #endif 4479 /* Save BB regs. */ 4480 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4481 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4482 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4483 4484 /* Save adda regs to be restored when finished. */ 4485 for (i = 0; i < __arraycount(addaReg); i++) 4486 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4487 /* Save mac regs. */ 4488 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4489 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4490 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4491 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4492 4493 #ifdef notyet 4494 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4495 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4496 4497 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4498 for (i = 0; i < sc->nrxchains; i++) 4499 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4500 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4501 #endif 4502 4503 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4504 R92C_HSSI_PARAM1_PI); 4505 if (piMode == 0) { 4506 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4507 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4508 R92C_HSSI_PARAM1_PI); 4509 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4510 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4511 R92C_HSSI_PARAM1_PI); 4512 } 4513 4514 attempt = 1; 4515 4516 next_attempt: 4517 4518 /* Set mac regs for calibration. */ 4519 for (i = 0; i < __arraycount(addaReg); i++) { 4520 urtwn_bb_write(sc, addaReg[i], 4521 addaReg[__arraycount(addaReg) - 1]); 4522 } 4523 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4524 R92C_CCK0_AFESETTING)); 4525 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4526 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4527 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4528 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4529 4530 if (sc->ntxchains > 1) 4531 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4532 4533 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4534 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4535 ~R92C_BCN_CTRL_EN_BCN)); 4536 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4537 ~R92C_BCN_CTRL_EN_BCN)); 4538 4539 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4540 ~R92C_GPIO_MUXCFG_ENBT)); 4541 4542 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4543 4544 if (sc->ntxchains > 1) 4545 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4546 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4547 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4548 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4549 4550 /* Restore BB regs. */ 4551 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4552 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4553 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4554 4555 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4556 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4557 if (sc->nrxchains > 1) 4558 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4559 4560 if (attempt-- > 0) 4561 goto next_attempt; 4562 4563 /* Restore mode. */ 4564 if (piMode == 0) { 4565 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4566 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4567 ~R92C_HSSI_PARAM1_PI); 4568 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4569 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4570 ~R92C_HSSI_PARAM1_PI); 4571 } 4572 4573 #ifdef notyet 4574 for (i = 0; i < sc->nrxchains; i++) { 4575 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4576 odfm0_agccore_regs[i]); 4577 } 4578 #endif 4579 4580 /* Restore adda regs. */ 4581 for (i = 0; i < __arraycount(addaReg); i++) 4582 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4583 /* Restore mac regs. */ 4584 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4585 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4586 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4587 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4588 4589 #ifdef notyet 4590 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4591 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4592 4593 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4594 for (i = 0; i < sc->nrxchains; i++) 4595 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4596 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4597 #endif 4598 } 4599 4600 static void 4601 urtwn_lc_calib(struct urtwn_softc *sc) 4602 { 4603 uint32_t rf_ac[2]; 4604 uint8_t txmode; 4605 size_t i; 4606 4607 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4608 4609 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4610 4611 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4612 if ((txmode & 0x70) != 0) { 4613 /* Disable all continuous Tx. */ 4614 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4615 4616 /* Set RF mode to standby mode. */ 4617 for (i = 0; i < sc->nrxchains; i++) { 4618 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4619 urtwn_rf_write(sc, i, R92C_RF_AC, 4620 RW(rf_ac[i], R92C_RF_AC_MODE, 4621 R92C_RF_AC_MODE_STANDBY)); 4622 } 4623 } else { 4624 /* Block all Tx queues. */ 4625 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4626 } 4627 /* Start calibration. */ 4628 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4629 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4630 4631 /* Give calibration the time to complete. */ 4632 urtwn_delay_ms(sc, 100); 4633 4634 /* Restore configuration. */ 4635 if ((txmode & 0x70) != 0) { 4636 /* Restore Tx mode. */ 4637 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4638 /* Restore RF mode. */ 4639 for (i = 0; i < sc->nrxchains; i++) { 4640 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4641 } 4642 } else { 4643 /* Unblock all Tx queues. */ 4644 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4645 } 4646 } 4647 4648 static void 4649 urtwn_temp_calib(struct urtwn_softc *sc) 4650 { 4651 int temp, t_meter_reg; 4652 4653 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4654 4655 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4656 4657 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4658 t_meter_reg = R92C_RF_T_METER; 4659 else 4660 t_meter_reg = R92E_RF_T_METER; 4661 4662 if (sc->thcal_state == 0) { 4663 /* Start measuring temperature. */ 4664 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4665 device_xname(sc->sc_dev), __func__)); 4666 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4667 sc->thcal_state = 1; 4668 return; 4669 } 4670 sc->thcal_state = 0; 4671 4672 /* Read measured temperature. */ 4673 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4674 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4675 __func__, temp)); 4676 if (temp == 0) /* Read failed, skip. */ 4677 return; 4678 4679 /* 4680 * Redo LC calibration if temperature changed significantly since 4681 * last calibration. 4682 */ 4683 if (sc->thcal_lctemp == 0) { 4684 /* First LC calibration is performed in urtwn_init(). */ 4685 sc->thcal_lctemp = temp; 4686 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4687 DPRINTFN(DBG_RF, 4688 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4689 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4690 temp)); 4691 urtwn_lc_calib(sc); 4692 /* Record temperature of last LC calibration. */ 4693 sc->thcal_lctemp = temp; 4694 } 4695 } 4696 4697 static int 4698 urtwn_init(struct ifnet *ifp) 4699 { 4700 struct urtwn_softc *sc = ifp->if_softc; 4701 struct ieee80211com *ic = &sc->sc_ic; 4702 struct urtwn_rx_data *data; 4703 uint32_t reg; 4704 size_t i; 4705 int error; 4706 4707 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4708 4709 urtwn_stop(ifp, 0); 4710 4711 mutex_enter(&sc->sc_write_mtx); 4712 4713 mutex_enter(&sc->sc_task_mtx); 4714 /* Init host async commands ring. */ 4715 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4716 mutex_exit(&sc->sc_task_mtx); 4717 4718 mutex_enter(&sc->sc_fwcmd_mtx); 4719 /* Init firmware commands ring. */ 4720 sc->fwcur = 0; 4721 mutex_exit(&sc->sc_fwcmd_mtx); 4722 4723 /* Allocate Tx/Rx buffers. */ 4724 error = urtwn_alloc_rx_list(sc); 4725 if (error != 0) { 4726 aprint_error_dev(sc->sc_dev, 4727 "could not allocate Rx buffers\n"); 4728 goto fail; 4729 } 4730 error = urtwn_alloc_tx_list(sc); 4731 if (error != 0) { 4732 aprint_error_dev(sc->sc_dev, 4733 "could not allocate Tx buffers\n"); 4734 goto fail; 4735 } 4736 4737 /* Power on adapter. */ 4738 error = urtwn_power_on(sc); 4739 if (error != 0) 4740 goto fail; 4741 4742 /* Initialize DMA. */ 4743 error = urtwn_dma_init(sc); 4744 if (error != 0) 4745 goto fail; 4746 4747 /* Set info size in Rx descriptors (in 64-bit words). */ 4748 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4749 4750 /* Init interrupts. */ 4751 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4752 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4753 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4754 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4755 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4756 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4757 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4758 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4759 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4760 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4761 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4762 } 4763 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4764 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4765 } else { 4766 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4767 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4768 } 4769 4770 /* Set MAC address. */ 4771 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4772 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4773 4774 /* Set initial network type. */ 4775 reg = urtwn_read_4(sc, R92C_CR); 4776 switch (ic->ic_opmode) { 4777 case IEEE80211_M_STA: 4778 default: 4779 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4780 break; 4781 4782 case IEEE80211_M_IBSS: 4783 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4784 break; 4785 } 4786 urtwn_write_4(sc, R92C_CR, reg); 4787 4788 /* Set response rate */ 4789 reg = urtwn_read_4(sc, R92C_RRSR); 4790 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4791 urtwn_write_4(sc, R92C_RRSR, reg); 4792 4793 /* SIFS (used in NAV) */ 4794 urtwn_write_2(sc, R92C_SPEC_SIFS, 4795 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4796 4797 /* Set short/long retry limits. */ 4798 urtwn_write_2(sc, R92C_RL, 4799 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4800 4801 /* Initialize EDCA parameters. */ 4802 urtwn_edca_init(sc); 4803 4804 /* Setup rate fallback. */ 4805 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4806 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4807 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4808 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4809 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4810 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4811 } 4812 4813 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4814 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4815 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4816 /* Set ACK timeout. */ 4817 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4818 4819 /* Setup USB aggregation. */ 4820 /* Tx */ 4821 reg = urtwn_read_4(sc, R92C_TDECTRL); 4822 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4823 urtwn_write_4(sc, R92C_TDECTRL, reg); 4824 /* Rx */ 4825 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4826 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4827 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4828 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4829 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4830 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4831 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4832 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4833 ISSET(sc->chip, URTWN_CHIP_92EU)) 4834 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4835 else 4836 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4837 4838 /* Initialize beacon parameters. */ 4839 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4840 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4841 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4842 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4843 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4844 4845 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4846 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4847 /* Setup AMPDU aggregation. */ 4848 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4849 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4850 urtwn_write_2(sc, 0x4ca, 0x0708); 4851 4852 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4853 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4854 } 4855 4856 /* Load 8051 microcode. */ 4857 error = urtwn_load_firmware(sc); 4858 if (error != 0) 4859 goto fail; 4860 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4861 4862 /* Initialize MAC/BB/RF blocks. */ 4863 /* 4864 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4865 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4866 * XXX: This setting should be removed from rtl8192cu_mac[]. 4867 */ 4868 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4869 urtwn_rxfilter_init(sc); // reset R92C_RCR 4870 urtwn_bb_init(sc); 4871 urtwn_rf_init(sc); 4872 4873 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4874 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4875 urtwn_write_2(sc, R92C_CR, 4876 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4877 R92C_CR_MACRXEN); 4878 } 4879 4880 /* Turn CCK and OFDM blocks on. */ 4881 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4882 reg |= R92C_RFMOD_CCK_EN; 4883 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4884 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4885 reg |= R92C_RFMOD_OFDM_EN; 4886 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4887 4888 /* Clear per-station keys table. */ 4889 urtwn_cam_init(sc); 4890 4891 /* Enable hardware sequence numbering. */ 4892 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4893 4894 /* Perform LO and IQ calibrations. */ 4895 urtwn_iq_calib(sc, sc->iqk_inited); 4896 sc->iqk_inited = true; 4897 4898 /* Perform LC calibration. */ 4899 urtwn_lc_calib(sc); 4900 4901 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4902 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4903 /* Fix USB interference issue. */ 4904 urtwn_write_1(sc, 0xfe40, 0xe0); 4905 urtwn_write_1(sc, 0xfe41, 0x8d); 4906 urtwn_write_1(sc, 0xfe42, 0x80); 4907 urtwn_write_4(sc, 0x20c, 0xfd0320); 4908 4909 urtwn_pa_bias_init(sc); 4910 } 4911 4912 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4913 !(sc->chip & URTWN_CHIP_92EU)) { 4914 /* 1T1R */ 4915 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4916 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4917 } 4918 4919 /* Initialize GPIO setting. */ 4920 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4921 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4922 4923 /* Fix for lower temperature. */ 4924 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4925 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4926 urtwn_write_1(sc, 0x15, 0xe9); 4927 4928 /* Set default channel. */ 4929 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4930 4931 /* Queue Rx xfers. */ 4932 for (size_t j = 0; j < sc->rx_npipe; j++) { 4933 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4934 data = &sc->rx_data[j][i]; 4935 usbd_setup_xfer(data->xfer, data, data->buf, 4936 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4937 urtwn_rxeof); 4938 error = usbd_transfer(data->xfer); 4939 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4940 error != USBD_IN_PROGRESS)) 4941 goto fail; 4942 } 4943 } 4944 4945 /* We're ready to go. */ 4946 ifp->if_flags &= ~IFF_OACTIVE; 4947 ifp->if_flags |= IFF_RUNNING; 4948 sc->sc_running = true; 4949 4950 mutex_exit(&sc->sc_write_mtx); 4951 4952 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4953 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4954 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4955 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4956 urtwn_wait_async(sc); 4957 4958 return 0; 4959 4960 fail: 4961 mutex_exit(&sc->sc_write_mtx); 4962 4963 urtwn_stop(ifp, 1); 4964 return error; 4965 } 4966 4967 static void 4968 urtwn_stop(struct ifnet *ifp, int disable) 4969 { 4970 struct urtwn_softc *sc = ifp->if_softc; 4971 struct ieee80211com *ic = &sc->sc_ic; 4972 size_t i; 4973 int s; 4974 4975 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4976 4977 s = splusb(); 4978 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4979 urtwn_wait_async(sc); 4980 splx(s); 4981 4982 sc->tx_timer = 0; 4983 ifp->if_timer = 0; 4984 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4985 4986 callout_stop(&sc->sc_scan_to); 4987 callout_stop(&sc->sc_calib_to); 4988 4989 /* Abort Tx. */ 4990 for (i = 0; i < sc->tx_npipe; i++) { 4991 if (sc->tx_pipe[i] != NULL) 4992 usbd_abort_pipe(sc->tx_pipe[i]); 4993 } 4994 4995 /* Stop Rx pipe. */ 4996 for (i = 0; i < sc->rx_npipe; i++) { 4997 if (sc->rx_pipe[i] != NULL) 4998 usbd_abort_pipe(sc->rx_pipe[i]); 4999 } 5000 5001 /* Free Tx/Rx buffers. */ 5002 urtwn_free_tx_list(sc); 5003 urtwn_free_rx_list(sc); 5004 5005 sc->sc_running = false; 5006 if (disable) 5007 urtwn_chip_stop(sc); 5008 } 5009 5010 static int 5011 urtwn_reset(struct ifnet *ifp) 5012 { 5013 struct urtwn_softc *sc = ifp->if_softc; 5014 struct ieee80211com *ic = &sc->sc_ic; 5015 5016 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5017 return ENETRESET; 5018 5019 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5020 5021 return 0; 5022 } 5023 5024 static void 5025 urtwn_chip_stop(struct urtwn_softc *sc) 5026 { 5027 uint32_t reg; 5028 bool disabled = true; 5029 5030 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5031 5032 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5033 ISSET(sc->chip, URTWN_CHIP_92EU)) 5034 return; 5035 5036 mutex_enter(&sc->sc_write_mtx); 5037 5038 /* 5039 * RF Off Sequence 5040 */ 5041 /* Pause MAC TX queue */ 5042 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5043 5044 /* Disable RF */ 5045 urtwn_rf_write(sc, 0, 0, 0); 5046 5047 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5048 5049 /* Reset BB state machine */ 5050 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5051 R92C_SYS_FUNC_EN_USBD | 5052 R92C_SYS_FUNC_EN_USBA | 5053 R92C_SYS_FUNC_EN_BB_GLB_RST); 5054 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5055 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5056 5057 /* 5058 * Reset digital sequence 5059 */ 5060 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5061 /* Reset MCU ready status */ 5062 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5063 /* If firmware in ram code, do reset */ 5064 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5065 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5066 ISSET(sc->chip, URTWN_CHIP_92EU)) 5067 urtwn_r88e_fw_reset(sc); 5068 else 5069 urtwn_fw_reset(sc); 5070 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5071 } 5072 } 5073 5074 /* Reset MAC and Enable 8051 */ 5075 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5076 5077 /* Reset MCU ready status */ 5078 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5079 5080 if (disabled) { 5081 /* Disable MAC clock */ 5082 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5083 /* Disable AFE PLL */ 5084 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5085 /* Gated AFE DIG_CLOCK */ 5086 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5087 /* Isolated digital to PON */ 5088 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5089 } 5090 5091 /* 5092 * Pull GPIO PIN to balance level and LED control 5093 */ 5094 /* 1. Disable GPIO[7:0] */ 5095 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5096 5097 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5098 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5099 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5100 5101 /* Disable GPIO[10:8] */ 5102 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5103 5104 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5105 reg |= (((reg & 0x000f) << 4) | 0x0780); 5106 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5107 5108 /* Disable LED0 & 1 */ 5109 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5110 5111 /* 5112 * Reset digital sequence 5113 */ 5114 if (disabled) { 5115 /* Disable ELDR clock */ 5116 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5117 /* Isolated ELDR to PON */ 5118 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5119 } 5120 5121 /* 5122 * Disable analog sequence 5123 */ 5124 if (disabled) { 5125 /* Disable A15 power */ 5126 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5127 /* Disable digital core power */ 5128 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5129 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5130 ~R92C_LDOV12D_CTRL_LDV12_EN); 5131 } 5132 5133 /* Enter PFM mode */ 5134 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5135 5136 /* Set USB suspend */ 5137 urtwn_write_2(sc, R92C_APS_FSMCO, 5138 R92C_APS_FSMCO_APDM_HOST | 5139 R92C_APS_FSMCO_AFSM_HSUS | 5140 R92C_APS_FSMCO_PFM_ALDN); 5141 5142 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5143 5144 mutex_exit(&sc->sc_write_mtx); 5145 } 5146 5147 static void 5148 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5149 { 5150 if (sc->sc_running == false) 5151 DELAY(ms * 1000); 5152 else 5153 usbd_delay_ms(sc->sc_udev, ms); 5154 } 5155 5156 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5157 5158 #ifdef _MODULE 5159 #include "ioconf.c" 5160 #endif 5161 5162 static int 5163 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5164 { 5165 int error = 0; 5166 5167 switch (cmd) { 5168 case MODULE_CMD_INIT: 5169 #ifdef _MODULE 5170 error = config_init_component(cfdriver_ioconf_urtwn, 5171 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5172 #endif 5173 return error; 5174 case MODULE_CMD_FINI: 5175 #ifdef _MODULE 5176 error = config_fini_component(cfdriver_ioconf_urtwn, 5177 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5178 #endif 5179 return error; 5180 default: 5181 return ENOTTY; 5182 } 5183 } 5184
Indexes created Thu Oct 02 14:10:14 GMT 2025