if_urtwn.c revision 1.71.2.5
1 /* $NetBSD: if_urtwn.c,v 1.71.2.5 2021/03/22 18:20:38 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.71.2.5 2021/03/22 18:20:38 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/ic/rtwnreg.h> 78 #include <dev/ic/rtwn_data.h> 79 #include <dev/usb/if_urtwnreg.h> 80 #include <dev/usb/if_urtwnvar.h> 81 82 /* 83 * The sc_write_mtx locking is to prevent sequences of writes from 84 * being intermingled with each other. I don't know if this is really 85 * needed. I have added it just to be on the safe side. 86 */ 87 88 #ifdef URTWN_DEBUG 89 #define DBG_INIT __BIT(0) 90 #define DBG_FN __BIT(1) 91 #define DBG_TX __BIT(2) 92 #define DBG_RX __BIT(3) 93 #define DBG_STM __BIT(4) 94 #define DBG_RF __BIT(5) 95 #define DBG_REG __BIT(6) 96 #define DBG_ALL 0xffffffffU 97 u_int urtwn_debug = 0; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 196 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 197 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 198 199 /* URTWN_RTL8192EU */ 200 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 201 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 202 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 203 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 204 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 205 }; 206 #undef URTWN_DEV 207 #undef URTWN_RTL8188E_DEV 208 #undef URTWN_RTL8192EU_DEV 209 210 static int urtwn_match(device_t, cfdata_t, void *); 211 static void urtwn_attach(device_t, device_t, void *); 212 static int urtwn_detach(device_t, int); 213 static int urtwn_activate(device_t, enum devact); 214 215 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 216 urtwn_attach, urtwn_detach, urtwn_activate); 217 218 static int urtwn_open_pipes(struct urtwn_softc *); 219 static void urtwn_close_pipes(struct urtwn_softc *); 220 static int urtwn_alloc_rx_list(struct urtwn_softc *); 221 static void urtwn_free_rx_list(struct urtwn_softc *); 222 static int urtwn_alloc_tx_list(struct urtwn_softc *); 223 static void urtwn_free_tx_list(struct urtwn_softc *); 224 static void urtwn_task(void *); 225 static void urtwn_do_async(struct urtwn_softc *, 226 void (*)(struct urtwn_softc *, void *), void *, int); 227 static void urtwn_wait_async(struct urtwn_softc *); 228 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 229 int); 230 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 231 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 232 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 233 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 234 int); 235 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 236 int); 237 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 238 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 239 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 240 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 241 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 242 uint32_t); 243 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 244 uint32_t); 245 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 246 uint32_t); 247 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 248 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 249 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 250 static void urtwn_efuse_read(struct urtwn_softc *); 251 static void urtwn_efuse_switch_power(struct urtwn_softc *); 252 static int urtwn_read_chipid(struct urtwn_softc *); 253 #ifdef URTWN_DEBUG 254 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 255 #endif 256 static void urtwn_read_rom(struct urtwn_softc *); 257 static void urtwn_r88e_read_rom(struct urtwn_softc *); 258 static int urtwn_media_change(struct ifnet *); 259 static int urtwn_ra_init(struct urtwn_softc *); 260 static int urtwn_get_nettype(struct urtwn_softc *); 261 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 262 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 263 static void urtwn_set_led(struct urtwn_softc *, int, int); 264 static void urtwn_calib_to(void *); 265 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 266 static void urtwn_next_scan(void *); 267 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 268 int); 269 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 270 static int urtwn_wme_update(struct ieee80211com *); 271 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 272 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 273 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 274 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 275 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 276 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 277 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 278 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 279 struct ieee80211_node *, struct urtwn_tx_data *); 280 static struct urtwn_tx_data * 281 urtwn_get_tx_data(struct urtwn_softc *, size_t); 282 static void urtwn_start(struct ifnet *); 283 static void urtwn_watchdog(struct ifnet *); 284 static int urtwn_ioctl(struct ifnet *, u_long, void *); 285 static int urtwn_r92c_power_on(struct urtwn_softc *); 286 static int urtwn_r92e_power_on(struct urtwn_softc *); 287 static int urtwn_r88e_power_on(struct urtwn_softc *); 288 static int urtwn_llt_init(struct urtwn_softc *); 289 static void urtwn_fw_reset(struct urtwn_softc *); 290 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 291 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 292 static int urtwn_load_firmware(struct urtwn_softc *); 293 static int urtwn_r92c_dma_init(struct urtwn_softc *); 294 static int urtwn_r88e_dma_init(struct urtwn_softc *); 295 static void urtwn_mac_init(struct urtwn_softc *); 296 static void urtwn_bb_init(struct urtwn_softc *); 297 static void urtwn_rf_init(struct urtwn_softc *); 298 static void urtwn_cam_init(struct urtwn_softc *); 299 static void urtwn_pa_bias_init(struct urtwn_softc *); 300 static void urtwn_rxfilter_init(struct urtwn_softc *); 301 static void urtwn_edca_init(struct urtwn_softc *); 302 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 303 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 304 uint16_t[]); 305 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 306 u_int, uint16_t[]); 307 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 308 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 309 u_int); 310 static void urtwn_iq_calib(struct urtwn_softc *, bool); 311 static void urtwn_lc_calib(struct urtwn_softc *); 312 static void urtwn_temp_calib(struct urtwn_softc *); 313 static int urtwn_init(struct ifnet *); 314 static void urtwn_stop(struct ifnet *, int); 315 static int urtwn_reset(struct ifnet *); 316 static void urtwn_chip_stop(struct urtwn_softc *); 317 static void urtwn_newassoc(struct ieee80211_node *, int); 318 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 319 320 /* Aliases. */ 321 #define urtwn_bb_write urtwn_write_4 322 #define urtwn_bb_read urtwn_read_4 323 324 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 325 326 static const uint16_t addaReg[] = { 327 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 328 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 329 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 330 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 331 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 332 }; 333 334 static int 335 urtwn_match(device_t parent, cfdata_t match, void *aux) 336 { 337 struct usb_attach_arg *uaa = aux; 338 339 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 340 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 341 } 342 343 static void 344 urtwn_attach(device_t parent, device_t self, void *aux) 345 { 346 struct urtwn_softc *sc = device_private(self); 347 struct ieee80211com *ic = &sc->sc_ic; 348 struct ifnet *ifp = &sc->sc_if; 349 struct usb_attach_arg *uaa = aux; 350 char *devinfop; 351 const struct urtwn_dev *dev; 352 usb_device_request_t req; 353 size_t i; 354 int error; 355 356 sc->sc_dev = self; 357 sc->sc_udev = uaa->uaa_device; 358 359 sc->chip = 0; 360 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 361 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 362 SET(sc->chip, URTWN_CHIP_88E); 363 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 364 SET(sc->chip, URTWN_CHIP_92EU); 365 366 aprint_naive("\n"); 367 aprint_normal("\n"); 368 369 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 370 371 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 372 aprint_normal_dev(self, "%s\n", devinfop); 373 usbd_devinfo_free(devinfop); 374 375 req.bmRequestType = UT_WRITE_DEVICE; 376 req.bRequest = UR_SET_FEATURE; 377 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 378 USETW(req.wIndex, UHF_PORT_SUSPEND); 379 USETW(req.wLength, 0); 380 381 (void) usbd_do_request(sc->sc_udev, &req, 0); 382 383 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 384 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 385 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 386 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 387 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 388 389 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 390 391 callout_init(&sc->sc_scan_to, 0); 392 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 393 callout_init(&sc->sc_calib_to, 0); 394 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 395 396 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 397 RND_TYPE_NET, RND_FLAG_DEFAULT); 398 399 error = usbd_set_config_no(sc->sc_udev, 1, 0); 400 if (error != 0) { 401 aprint_error_dev(self, "failed to set configuration" 402 ", err=%s\n", usbd_errstr(error)); 403 goto fail; 404 } 405 406 /* Get the first interface handle. */ 407 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 408 if (error != 0) { 409 aprint_error_dev(self, "could not get interface handle\n"); 410 goto fail; 411 } 412 413 error = urtwn_read_chipid(sc); 414 if (error != 0) { 415 aprint_error_dev(self, "unsupported test chip\n"); 416 goto fail; 417 } 418 419 /* Determine number of Tx/Rx chains. */ 420 if (sc->chip & URTWN_CHIP_92C) { 421 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 422 sc->nrxchains = 2; 423 } else if (sc->chip & URTWN_CHIP_92EU) { 424 sc->ntxchains = 2; 425 sc->nrxchains = 2; 426 } else { 427 sc->ntxchains = 1; 428 sc->nrxchains = 1; 429 } 430 431 if (ISSET(sc->chip, URTWN_CHIP_88E) || 432 ISSET(sc->chip, URTWN_CHIP_92EU)) 433 urtwn_r88e_read_rom(sc); 434 else 435 urtwn_read_rom(sc); 436 437 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 438 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 439 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 440 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 441 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 442 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 443 "8188CUS", sc->ntxchains, sc->nrxchains, 444 ether_sprintf(ic->ic_myaddr)); 445 446 error = urtwn_open_pipes(sc); 447 if (error != 0) { 448 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 449 goto fail; 450 } 451 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 452 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 453 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 454 455 /* 456 * Setup the 802.11 device. 457 */ 458 ic->ic_ifp = ifp; 459 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 460 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 461 ic->ic_state = IEEE80211_S_INIT; 462 463 /* Set device capabilities. */ 464 ic->ic_caps = 465 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 466 IEEE80211_C_IBSS | /* IBSS mode supported */ 467 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 468 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 469 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 470 IEEE80211_C_WME | /* 802.11e */ 471 IEEE80211_C_WPA; /* 802.11i */ 472 473 /* Set supported .11b and .11g rates. */ 474 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 475 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 476 477 /* Set supported .11b and .11g channels (1 through 14). */ 478 for (i = 1; i <= 14; i++) { 479 ic->ic_channels[i].ic_freq = 480 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 481 ic->ic_channels[i].ic_flags = 482 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 483 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 484 } 485 486 ifp->if_softc = sc; 487 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 488 ifp->if_init = urtwn_init; 489 ifp->if_ioctl = urtwn_ioctl; 490 ifp->if_start = urtwn_start; 491 ifp->if_watchdog = urtwn_watchdog; 492 IFQ_SET_READY(&ifp->if_snd); 493 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 494 495 if_initialize(ifp); 496 ieee80211_ifattach(ic); 497 498 /* override default methods */ 499 ic->ic_newassoc = urtwn_newassoc; 500 ic->ic_reset = urtwn_reset; 501 ic->ic_wme.wme_update = urtwn_wme_update; 502 503 /* Override state transition machine. */ 504 sc->sc_newstate = ic->ic_newstate; 505 ic->ic_newstate = urtwn_newstate; 506 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 507 508 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 509 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 510 &sc->sc_drvbpf); 511 512 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 513 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 514 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 515 516 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 517 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 518 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 519 520 ifp->if_percpuq = if_percpuq_create(ifp); 521 if_register(ifp); 522 523 ieee80211_announce(ic); 524 525 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 526 527 if (!pmf_device_register(self, NULL, NULL)) 528 aprint_error_dev(self, "couldn't establish power handler\n"); 529 530 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 531 return; 532 533 fail: 534 sc->sc_dying = 1; 535 aprint_error_dev(self, "attach failed\n"); 536 } 537 538 static int 539 urtwn_detach(device_t self, int flags) 540 { 541 struct urtwn_softc *sc = device_private(self); 542 struct ifnet *ifp = &sc->sc_if; 543 int s; 544 545 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 546 547 pmf_device_deregister(self); 548 549 s = splusb(); 550 551 sc->sc_dying = 1; 552 553 callout_halt(&sc->sc_scan_to, NULL); 554 callout_halt(&sc->sc_calib_to, NULL); 555 556 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 557 urtwn_stop(ifp, 0); 558 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 559 NULL); 560 561 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 562 bpf_detach(ifp); 563 ieee80211_ifdetach(&sc->sc_ic); 564 if_detach(ifp); 565 566 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 567 urtwn_close_pipes(sc); 568 } 569 570 splx(s); 571 572 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 573 574 rnd_detach_source(&sc->rnd_source); 575 576 callout_destroy(&sc->sc_scan_to); 577 callout_destroy(&sc->sc_calib_to); 578 579 mutex_destroy(&sc->sc_write_mtx); 580 mutex_destroy(&sc->sc_fwcmd_mtx); 581 mutex_destroy(&sc->sc_tx_mtx); 582 mutex_destroy(&sc->sc_rx_mtx); 583 mutex_destroy(&sc->sc_task_mtx); 584 585 return 0; 586 } 587 588 static int 589 urtwn_activate(device_t self, enum devact act) 590 { 591 struct urtwn_softc *sc = device_private(self); 592 593 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 594 595 switch (act) { 596 case DVACT_DEACTIVATE: 597 if_deactivate(sc->sc_ic.ic_ifp); 598 return 0; 599 default: 600 return EOPNOTSUPP; 601 } 602 } 603 604 static int 605 urtwn_open_pipes(struct urtwn_softc *sc) 606 { 607 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 608 static uint8_t epaddr[R92C_MAX_EPOUT]; 609 static uint8_t rxepaddr[R92C_MAX_EPIN]; 610 usb_interface_descriptor_t *id; 611 usb_endpoint_descriptor_t *ed; 612 size_t i, ntx = 0, nrx = 0; 613 int error; 614 615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 616 617 /* Determine the number of bulk-out pipes. */ 618 id = usbd_get_interface_descriptor(sc->sc_iface); 619 for (i = 0; i < id->bNumEndpoints; i++) { 620 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 621 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 622 continue; 623 } 624 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 625 if (ntx < sizeof(epaddr)) 626 epaddr[ntx] = ed->bEndpointAddress; 627 ntx++; 628 } 629 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 630 if (nrx < sizeof(rxepaddr)) 631 rxepaddr[nrx] = ed->bEndpointAddress; 632 nrx++; 633 } 634 } 635 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 636 aprint_error_dev(sc->sc_dev, 637 "%zd: invalid number of Rx bulk pipes\n", nrx); 638 return EIO; 639 } 640 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 641 aprint_error_dev(sc->sc_dev, 642 "%zd: invalid number of Tx bulk pipes\n", ntx); 643 return EIO; 644 } 645 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 646 device_xname(sc->sc_dev), __func__, nrx, ntx)); 647 sc->rx_npipe = nrx; 648 sc->tx_npipe = ntx; 649 650 /* Open bulk-in pipe at address 0x81. */ 651 for (i = 0; i < nrx; i++) { 652 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 653 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 654 if (error != 0) { 655 aprint_error_dev(sc->sc_dev, 656 "could not open Rx bulk pipe 0x%02x: %d\n", 657 rxepaddr[i], error); 658 goto fail; 659 } 660 } 661 662 /* Open bulk-out pipes (up to 3). */ 663 for (i = 0; i < ntx; i++) { 664 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 665 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 666 if (error != 0) { 667 aprint_error_dev(sc->sc_dev, 668 "could not open Tx bulk pipe 0x%02x: %d\n", 669 epaddr[i], error); 670 goto fail; 671 } 672 } 673 674 /* Map 802.11 access categories to USB pipes. */ 675 sc->ac2idx[WME_AC_BK] = 676 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 677 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 678 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 679 680 fail: 681 if (error != 0) 682 urtwn_close_pipes(sc); 683 return error; 684 } 685 686 static void 687 urtwn_close_pipes(struct urtwn_softc *sc) 688 { 689 struct usbd_pipe *pipe; 690 size_t i; 691 692 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 693 694 /* Close Rx pipes. */ 695 CTASSERT(sizeof(pipe) == sizeof(void *)); 696 for (i = 0; i < sc->rx_npipe; i++) { 697 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 698 if (pipe != NULL) { 699 usbd_close_pipe(pipe); 700 } 701 } 702 703 /* Close Tx pipes. */ 704 for (i = 0; i < sc->tx_npipe; i++) { 705 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 706 if (pipe != NULL) { 707 usbd_close_pipe(pipe); 708 } 709 } 710 } 711 712 static int 713 urtwn_alloc_rx_list(struct urtwn_softc *sc) 714 { 715 struct urtwn_rx_data *data; 716 size_t i; 717 int error = 0; 718 719 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 720 721 for (size_t j = 0; j < sc->rx_npipe; j++) { 722 TAILQ_INIT(&sc->rx_free_list[j]); 723 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 724 data = &sc->rx_data[j][i]; 725 726 data->sc = sc; /* Backpointer for callbacks. */ 727 728 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 729 0, 0, &data->xfer); 730 if (error) { 731 aprint_error_dev(sc->sc_dev, 732 "could not allocate xfer\n"); 733 break; 734 } 735 736 data->buf = usbd_get_buffer(data->xfer); 737 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 738 } 739 } 740 if (error != 0) 741 urtwn_free_rx_list(sc); 742 return error; 743 } 744 745 static void 746 urtwn_free_rx_list(struct urtwn_softc *sc) 747 { 748 struct usbd_xfer *xfer; 749 size_t i; 750 751 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 752 753 /* NB: Caller must abort pipe first. */ 754 for (size_t j = 0; j < sc->rx_npipe; j++) { 755 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 756 CTASSERT(sizeof(xfer) == sizeof(void *)); 757 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 758 if (xfer != NULL) 759 usbd_destroy_xfer(xfer); 760 } 761 } 762 } 763 764 static int 765 urtwn_alloc_tx_list(struct urtwn_softc *sc) 766 { 767 struct urtwn_tx_data *data; 768 size_t i; 769 int error = 0; 770 771 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 772 773 mutex_enter(&sc->sc_tx_mtx); 774 for (size_t j = 0; j < sc->tx_npipe; j++) { 775 TAILQ_INIT(&sc->tx_free_list[j]); 776 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 777 data = &sc->tx_data[j][i]; 778 779 data->sc = sc; /* Backpointer for callbacks. */ 780 data->pidx = j; 781 782 error = usbd_create_xfer(sc->tx_pipe[j], 783 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 784 &data->xfer); 785 if (error) { 786 aprint_error_dev(sc->sc_dev, 787 "could not allocate xfer\n"); 788 goto fail; 789 } 790 791 data->buf = usbd_get_buffer(data->xfer); 792 793 /* Append this Tx buffer to our free list. */ 794 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 795 } 796 } 797 mutex_exit(&sc->sc_tx_mtx); 798 return 0; 799 800 fail: 801 urtwn_free_tx_list(sc); 802 mutex_exit(&sc->sc_tx_mtx); 803 return error; 804 } 805 806 static void 807 urtwn_free_tx_list(struct urtwn_softc *sc) 808 { 809 struct usbd_xfer *xfer; 810 size_t i; 811 812 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 813 814 /* NB: Caller must abort pipe first. */ 815 for (size_t j = 0; j < sc->tx_npipe; j++) { 816 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 817 CTASSERT(sizeof(xfer) == sizeof(void *)); 818 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 819 if (xfer != NULL) 820 usbd_destroy_xfer(xfer); 821 } 822 } 823 } 824 825 static int 826 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 827 struct ieee80211_node *ni) 828 { 829 struct urtwn_tx_data *data = 830 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 831 return urtwn_tx(sc, m, ni, data); 832 } 833 834 static void 835 urtwn_task(void *arg) 836 { 837 struct urtwn_softc *sc = arg; 838 struct ieee80211com *ic = &sc->sc_ic; 839 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 840 struct urtwn_host_cmd *cmd; 841 int s; 842 843 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 844 if (ic->ic_state == IEEE80211_S_RUN && 845 (ic->ic_opmode == IEEE80211_M_HOSTAP || 846 ic->ic_opmode == IEEE80211_M_IBSS)) { 847 848 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 849 &sc->sc_bo); 850 if (m == NULL) { 851 aprint_error_dev(sc->sc_dev, 852 "could not allocate beacon"); 853 } 854 855 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 856 m_freem(m); 857 aprint_error_dev(sc->sc_dev, "could not send beacon"); 858 } 859 860 /* beacon is no longer needed */ 861 m_freem(m); 862 } 863 864 /* Process host commands. */ 865 s = splusb(); 866 mutex_spin_enter(&sc->sc_task_mtx); 867 while (ring->next != ring->cur) { 868 cmd = &ring->cmd[ring->next]; 869 mutex_spin_exit(&sc->sc_task_mtx); 870 splx(s); 871 /* Invoke callback with kernel lock held. */ 872 cmd->cb(sc, cmd->data); 873 s = splusb(); 874 mutex_spin_enter(&sc->sc_task_mtx); 875 ring->queued--; 876 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 877 } 878 mutex_spin_exit(&sc->sc_task_mtx); 879 wakeup(&sc->cmdq); 880 splx(s); 881 } 882 883 static void 884 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 885 void *arg, int len) 886 { 887 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 888 struct urtwn_host_cmd *cmd; 889 int s; 890 891 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 892 device_xname(sc->sc_dev), __func__, cb, arg, len)); 893 894 s = splusb(); 895 mutex_spin_enter(&sc->sc_task_mtx); 896 cmd = &ring->cmd[ring->cur]; 897 cmd->cb = cb; 898 KASSERT(len <= sizeof(cmd->data)); 899 memcpy(cmd->data, arg, len); 900 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 901 902 /* If there is no pending command already, schedule a task. */ 903 if (!sc->sc_dying && ++ring->queued == 1) { 904 mutex_spin_exit(&sc->sc_task_mtx); 905 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 906 } else 907 mutex_spin_exit(&sc->sc_task_mtx); 908 splx(s); 909 } 910 911 static void 912 urtwn_wait_async(struct urtwn_softc *sc) 913 { 914 915 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 916 917 /* Wait for all queued asynchronous commands to complete. */ 918 while (sc->cmdq.queued > 0) 919 tsleep(&sc->cmdq, 0, "endtask", 0); 920 } 921 922 static int 923 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 924 int len) 925 { 926 usb_device_request_t req; 927 usbd_status error; 928 929 KASSERT(mutex_owned(&sc->sc_write_mtx)); 930 931 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 932 req.bRequest = R92C_REQ_REGS; 933 USETW(req.wValue, addr); 934 USETW(req.wIndex, 0); 935 USETW(req.wLength, len); 936 error = usbd_do_request(sc->sc_udev, &req, buf); 937 if (error != USBD_NORMAL_COMPLETION) { 938 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 939 device_xname(sc->sc_dev), __func__, error, addr, len)); 940 } 941 return error; 942 } 943 944 static void 945 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 946 { 947 948 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 949 device_xname(sc->sc_dev), __func__, addr, val)); 950 951 urtwn_write_region_1(sc, addr, &val, 1); 952 } 953 954 static void 955 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 956 { 957 uint8_t buf[2]; 958 959 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 960 device_xname(sc->sc_dev), __func__, addr, val)); 961 962 buf[0] = (uint8_t)val; 963 buf[1] = (uint8_t)(val >> 8); 964 urtwn_write_region_1(sc, addr, buf, 2); 965 } 966 967 static void 968 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 969 { 970 uint8_t buf[4]; 971 972 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 973 device_xname(sc->sc_dev), __func__, addr, val)); 974 975 buf[0] = (uint8_t)val; 976 buf[1] = (uint8_t)(val >> 8); 977 buf[2] = (uint8_t)(val >> 16); 978 buf[3] = (uint8_t)(val >> 24); 979 urtwn_write_region_1(sc, addr, buf, 4); 980 } 981 982 static int 983 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 984 { 985 986 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 987 device_xname(sc->sc_dev), __func__, addr, len)); 988 989 return urtwn_write_region_1(sc, addr, buf, len); 990 } 991 992 static int 993 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 994 int len) 995 { 996 usb_device_request_t req; 997 usbd_status error; 998 999 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1000 req.bRequest = R92C_REQ_REGS; 1001 USETW(req.wValue, addr); 1002 USETW(req.wIndex, 0); 1003 USETW(req.wLength, len); 1004 error = usbd_do_request(sc->sc_udev, &req, buf); 1005 if (error != USBD_NORMAL_COMPLETION) { 1006 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1007 device_xname(sc->sc_dev), __func__, error, addr, len)); 1008 } 1009 return error; 1010 } 1011 1012 static uint8_t 1013 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1014 { 1015 uint8_t val; 1016 1017 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1018 return 0xff; 1019 1020 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1021 device_xname(sc->sc_dev), __func__, addr, val)); 1022 return val; 1023 } 1024 1025 static uint16_t 1026 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1027 { 1028 uint8_t buf[2]; 1029 uint16_t val; 1030 1031 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1032 return 0xffff; 1033 1034 val = LE_READ_2(&buf[0]); 1035 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1036 device_xname(sc->sc_dev), __func__, addr, val)); 1037 return val; 1038 } 1039 1040 static uint32_t 1041 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1042 { 1043 uint8_t buf[4]; 1044 uint32_t val; 1045 1046 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1047 return 0xffffffff; 1048 1049 val = LE_READ_4(&buf[0]); 1050 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1051 device_xname(sc->sc_dev), __func__, addr, val)); 1052 return val; 1053 } 1054 1055 static int 1056 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1057 { 1058 struct r92c_fw_cmd cmd; 1059 uint8_t *cp; 1060 int fwcur; 1061 int ntries; 1062 1063 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1064 device_xname(sc->sc_dev), __func__, id, buf, len)); 1065 1066 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1067 1068 mutex_enter(&sc->sc_fwcmd_mtx); 1069 fwcur = sc->fwcur; 1070 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1071 mutex_exit(&sc->sc_fwcmd_mtx); 1072 1073 /* Wait for current FW box to be empty. */ 1074 for (ntries = 0; ntries < 100; ntries++) { 1075 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1076 break; 1077 DELAY(2000); 1078 } 1079 if (ntries == 100) { 1080 aprint_error_dev(sc->sc_dev, 1081 "could not send firmware command %d\n", id); 1082 return ETIMEDOUT; 1083 } 1084 1085 memset(&cmd, 0, sizeof(cmd)); 1086 KASSERT(len <= sizeof(cmd.msg)); 1087 memcpy(cmd.msg, buf, len); 1088 1089 /* Write the first word last since that will trigger the FW. */ 1090 cp = (uint8_t *)&cmd; 1091 cmd.id = id; 1092 if (len >= 4) { 1093 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1094 cmd.id |= R92C_CMD_FLAG_EXT; 1095 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1096 &cp[1], 2); 1097 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1098 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1099 ((uint32_t)cp[5] << 24)); 1100 } else { 1101 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1102 &cp[4], 2); 1103 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1104 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1105 ((uint32_t)cp[3] << 24)); 1106 } 1107 } else { 1108 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1109 } 1110 1111 return 0; 1112 } 1113 1114 static __inline void 1115 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1116 { 1117 1118 sc->sc_rf_write(sc, chain, addr, val); 1119 } 1120 1121 static void 1122 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1123 uint32_t val) 1124 { 1125 1126 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1127 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1128 } 1129 1130 static void 1131 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1132 uint32_t val) 1133 { 1134 1135 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1136 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1137 } 1138 1139 static void 1140 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1141 uint32_t val) 1142 { 1143 1144 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1145 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1146 } 1147 1148 static uint32_t 1149 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1150 { 1151 uint32_t reg[R92C_MAX_CHAINS], val; 1152 1153 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1154 if (chain != 0) { 1155 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1156 } 1157 1158 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1159 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1160 DELAY(1000); 1161 1162 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1163 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1164 R92C_HSSI_PARAM2_READ_EDGE); 1165 DELAY(1000); 1166 1167 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1168 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1169 DELAY(1000); 1170 1171 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1172 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1173 } else { 1174 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1175 } 1176 return MS(val, R92C_LSSI_READBACK_DATA); 1177 } 1178 1179 static int 1180 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1181 { 1182 int ntries; 1183 1184 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1185 1186 urtwn_write_4(sc, R92C_LLT_INIT, 1187 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1188 SM(R92C_LLT_INIT_ADDR, addr) | 1189 SM(R92C_LLT_INIT_DATA, data)); 1190 /* Wait for write operation to complete. */ 1191 for (ntries = 0; ntries < 20; ntries++) { 1192 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1193 R92C_LLT_INIT_OP_NO_ACTIVE) { 1194 /* Done */ 1195 return 0; 1196 } 1197 DELAY(5); 1198 } 1199 return ETIMEDOUT; 1200 } 1201 1202 static uint8_t 1203 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1204 { 1205 uint32_t reg; 1206 int ntries; 1207 1208 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1209 1210 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1211 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1212 reg &= ~R92C_EFUSE_CTRL_VALID; 1213 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1214 1215 /* Wait for read operation to complete. */ 1216 for (ntries = 0; ntries < 100; ntries++) { 1217 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1218 if (reg & R92C_EFUSE_CTRL_VALID) { 1219 /* Done */ 1220 return MS(reg, R92C_EFUSE_CTRL_DATA); 1221 } 1222 DELAY(5); 1223 } 1224 aprint_error_dev(sc->sc_dev, 1225 "could not read efuse byte at address 0x%04x\n", addr); 1226 return 0xff; 1227 } 1228 1229 static void 1230 urtwn_efuse_read(struct urtwn_softc *sc) 1231 { 1232 uint8_t *rom = (uint8_t *)&sc->rom; 1233 uint32_t reg; 1234 uint16_t addr = 0; 1235 uint8_t off, msk; 1236 size_t i; 1237 1238 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1239 1240 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1241 1242 urtwn_efuse_switch_power(sc); 1243 1244 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1245 while (addr < 512) { 1246 reg = urtwn_efuse_read_1(sc, addr); 1247 if (reg == 0xff) 1248 break; 1249 addr++; 1250 off = reg >> 4; 1251 msk = reg & 0xf; 1252 for (i = 0; i < 4; i++) { 1253 if (msk & (1U << i)) 1254 continue; 1255 1256 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1257 addr++; 1258 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1259 addr++; 1260 } 1261 } 1262 #ifdef URTWN_DEBUG 1263 if (urtwn_debug & DBG_INIT) { 1264 /* Dump ROM content. */ 1265 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1266 for (i = 0; i < (int)sizeof(sc->rom); i++) 1267 printf(":%02x", rom[i]); 1268 printf("\n"); 1269 } 1270 #endif 1271 } 1272 1273 static void 1274 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1275 { 1276 uint32_t reg; 1277 1278 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1279 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1280 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1281 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1282 } 1283 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1284 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1285 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1286 reg | R92C_SYS_FUNC_EN_ELDR); 1287 } 1288 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1289 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1290 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1291 urtwn_write_2(sc, R92C_SYS_CLKR, 1292 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1293 } 1294 } 1295 1296 static int 1297 urtwn_read_chipid(struct urtwn_softc *sc) 1298 { 1299 uint32_t reg; 1300 1301 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1302 1303 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1304 ISSET(sc->chip, URTWN_CHIP_92EU)) 1305 return 0; 1306 1307 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1308 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1309 /* test chip, not supported */ 1310 return EIO; 1311 } 1312 if (reg & R92C_SYS_CFG_TYPE_92C) { 1313 sc->chip |= URTWN_CHIP_92C; 1314 /* Check if it is a castrated 8192C. */ 1315 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1316 R92C_HPON_FSM_CHIP_BONDING_ID) == 1317 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1318 sc->chip |= URTWN_CHIP_92C_1T2R; 1319 } 1320 } 1321 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1322 sc->chip |= URTWN_CHIP_UMC; 1323 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1324 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1325 } 1326 } 1327 return 0; 1328 } 1329 1330 #ifdef URTWN_DEBUG 1331 static void 1332 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1333 { 1334 1335 aprint_normal_dev(sc->sc_dev, 1336 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1337 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1338 1339 aprint_normal_dev(sc->sc_dev, 1340 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1341 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1342 1343 aprint_normal_dev(sc->sc_dev, 1344 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1345 rp->macaddr[0], rp->macaddr[1], 1346 rp->macaddr[2], rp->macaddr[3], 1347 rp->macaddr[4], rp->macaddr[5]); 1348 1349 aprint_normal_dev(sc->sc_dev, 1350 "string %s, subcustomer_id 0x%x\n", 1351 rp->string, rp->subcustomer_id); 1352 1353 aprint_normal_dev(sc->sc_dev, 1354 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1355 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1356 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1357 1358 aprint_normal_dev(sc->sc_dev, 1359 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1360 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1361 rp->ht40_1s_tx_pwr[0][2], 1362 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1363 rp->ht40_1s_tx_pwr[1][2]); 1364 1365 aprint_normal_dev(sc->sc_dev, 1366 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1367 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1368 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1369 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1370 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1371 1372 aprint_normal_dev(sc->sc_dev, 1373 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1374 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1375 rp->ht20_tx_pwr_diff[2] & 0xf, 1376 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1377 rp->ht20_tx_pwr_diff[2] >> 4); 1378 1379 aprint_normal_dev(sc->sc_dev, 1380 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1381 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1382 rp->ofdm_tx_pwr_diff[2] & 0xf, 1383 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1384 rp->ofdm_tx_pwr_diff[2] >> 4); 1385 1386 aprint_normal_dev(sc->sc_dev, 1387 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1388 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1389 rp->ht40_max_pwr[2] & 0xf, 1390 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1391 rp->ht40_max_pwr[2] >> 4); 1392 1393 aprint_normal_dev(sc->sc_dev, 1394 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1395 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1396 rp->ht20_max_pwr[2] & 0xf, 1397 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1398 rp->ht20_max_pwr[2] >> 4); 1399 1400 aprint_normal_dev(sc->sc_dev, 1401 "xtal_calib %d, tssi %d %d, thermal %d\n", 1402 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1403 1404 aprint_normal_dev(sc->sc_dev, 1405 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1406 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1407 1408 aprint_normal_dev(sc->sc_dev, 1409 "channnel_plan %d, version %d customer_id 0x%x\n", 1410 rp->channel_plan, rp->version, rp->curstomer_id); 1411 } 1412 #endif 1413 1414 static void 1415 urtwn_read_rom(struct urtwn_softc *sc) 1416 { 1417 struct ieee80211com *ic = &sc->sc_ic; 1418 struct r92c_rom *rom = &sc->rom; 1419 1420 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1421 1422 mutex_enter(&sc->sc_write_mtx); 1423 1424 /* Read full ROM image. */ 1425 urtwn_efuse_read(sc); 1426 #ifdef URTWN_DEBUG 1427 if (urtwn_debug & DBG_REG) 1428 urtwn_dump_rom(sc, rom); 1429 #endif 1430 1431 /* XXX Weird but this is what the vendor driver does. */ 1432 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1433 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1434 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1435 1436 DPRINTFN(DBG_INIT, 1437 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1438 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1439 sc->board_type, sc->regulatory)); 1440 1441 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1442 1443 sc->sc_rf_write = urtwn_r92c_rf_write; 1444 sc->sc_power_on = urtwn_r92c_power_on; 1445 sc->sc_dma_init = urtwn_r92c_dma_init; 1446 1447 mutex_exit(&sc->sc_write_mtx); 1448 } 1449 1450 static void 1451 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1452 { 1453 struct ieee80211com *ic = &sc->sc_ic; 1454 uint8_t *rom = sc->r88e_rom; 1455 uint32_t reg; 1456 uint16_t addr = 0; 1457 uint8_t off, msk, tmp; 1458 int i; 1459 1460 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1461 1462 mutex_enter(&sc->sc_write_mtx); 1463 1464 off = 0; 1465 urtwn_efuse_switch_power(sc); 1466 1467 /* Read full ROM image. */ 1468 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1469 while (addr < 4096) { 1470 reg = urtwn_efuse_read_1(sc, addr); 1471 if (reg == 0xff) 1472 break; 1473 addr++; 1474 if ((reg & 0x1f) == 0x0f) { 1475 tmp = (reg & 0xe0) >> 5; 1476 reg = urtwn_efuse_read_1(sc, addr); 1477 if ((reg & 0x0f) != 0x0f) 1478 off = ((reg & 0xf0) >> 1) | tmp; 1479 addr++; 1480 } else 1481 off = reg >> 4; 1482 msk = reg & 0xf; 1483 for (i = 0; i < 4; i++) { 1484 if (msk & (1 << i)) 1485 continue; 1486 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1487 addr++; 1488 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1489 addr++; 1490 } 1491 } 1492 #ifdef URTWN_DEBUG 1493 if (urtwn_debug & DBG_REG) { 1494 } 1495 #endif 1496 1497 addr = 0x10; 1498 for (i = 0; i < 6; i++) 1499 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1500 for (i = 0; i < 5; i++) 1501 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1502 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1503 if (sc->bw20_tx_pwr_diff & 0x08) 1504 sc->bw20_tx_pwr_diff |= 0xf0; 1505 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1506 if (sc->ofdm_tx_pwr_diff & 0x08) 1507 sc->ofdm_tx_pwr_diff |= 0xf0; 1508 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1509 1510 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1511 1512 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1513 sc->sc_power_on = urtwn_r92e_power_on; 1514 sc->sc_rf_write = urtwn_r92e_rf_write; 1515 } else { 1516 sc->sc_power_on = urtwn_r88e_power_on; 1517 sc->sc_rf_write = urtwn_r88e_rf_write; 1518 } 1519 sc->sc_dma_init = urtwn_r88e_dma_init; 1520 1521 mutex_exit(&sc->sc_write_mtx); 1522 } 1523 1524 static int 1525 urtwn_media_change(struct ifnet *ifp) 1526 { 1527 #ifdef URTWN_DEBUG 1528 struct urtwn_softc *sc = ifp->if_softc; 1529 #endif 1530 int error; 1531 1532 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1533 1534 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1535 return error; 1536 1537 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1538 (IFF_UP | IFF_RUNNING)) { 1539 urtwn_init(ifp); 1540 } 1541 return 0; 1542 } 1543 1544 /* 1545 * Initialize rate adaptation in firmware. 1546 */ 1547 static int 1548 urtwn_ra_init(struct urtwn_softc *sc) 1549 { 1550 static const uint8_t map[] = { 1551 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1552 }; 1553 struct ieee80211com *ic = &sc->sc_ic; 1554 struct ieee80211_node *ni = ic->ic_bss; 1555 struct ieee80211_rateset *rs = &ni->ni_rates; 1556 struct r92c_fw_cmd_macid_cfg cmd; 1557 uint32_t rates, basicrates; 1558 uint32_t rrsr_mask, rrsr_rate; 1559 uint8_t mode; 1560 size_t maxrate, maxbasicrate, i, j; 1561 int error; 1562 1563 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1564 1565 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1566 1567 /* Get normal and basic rates mask. */ 1568 rates = basicrates = 1; 1569 maxrate = maxbasicrate = 0; 1570 for (i = 0; i < rs->rs_nrates; i++) { 1571 /* Convert 802.11 rate to HW rate index. */ 1572 for (j = 0; j < __arraycount(map); j++) { 1573 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1574 break; 1575 } 1576 } 1577 if (j == __arraycount(map)) { 1578 /* Unknown rate, skip. */ 1579 continue; 1580 } 1581 1582 rates |= 1U << j; 1583 if (j > maxrate) { 1584 maxrate = j; 1585 } 1586 1587 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1588 basicrates |= 1U << j; 1589 if (j > maxbasicrate) { 1590 maxbasicrate = j; 1591 } 1592 } 1593 } 1594 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1595 mode = R92C_RAID_11B; 1596 } else { 1597 mode = R92C_RAID_11BG; 1598 } 1599 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1600 "maxrate=%zx, maxbasicrate=%zx\n", 1601 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1602 maxrate, maxbasicrate)); 1603 1604 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1605 maxbasicrate |= R92C_RATE_SHORTGI; 1606 maxrate |= R92C_RATE_SHORTGI; 1607 } 1608 1609 /* Set rates mask for group addressed frames. */ 1610 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1611 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1612 cmd.macid |= RTWN_MACID_SHORTGI; 1613 cmd.mask = htole32((mode << 28) | basicrates); 1614 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1615 if (error != 0) { 1616 aprint_error_dev(sc->sc_dev, 1617 "could not add broadcast station\n"); 1618 return error; 1619 } 1620 /* Set initial MRR rate. */ 1621 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1622 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1623 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1624 1625 /* Set rates mask for unicast frames. */ 1626 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1627 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1628 cmd.macid |= RTWN_MACID_SHORTGI; 1629 cmd.mask = htole32((mode << 28) | rates); 1630 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1631 if (error != 0) { 1632 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1633 return error; 1634 } 1635 /* Set initial MRR rate. */ 1636 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1637 __func__, maxrate)); 1638 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1639 1640 rrsr_rate = ic->ic_fixed_rate; 1641 if (rrsr_rate == -1) 1642 rrsr_rate = 11; 1643 1644 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1645 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1646 1647 /* Indicate highest supported rate. */ 1648 ni->ni_txrate = rs->rs_nrates - 1; 1649 1650 return 0; 1651 } 1652 1653 static int 1654 urtwn_get_nettype(struct urtwn_softc *sc) 1655 { 1656 struct ieee80211com *ic = &sc->sc_ic; 1657 int type; 1658 1659 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1660 1661 switch (ic->ic_opmode) { 1662 case IEEE80211_M_STA: 1663 type = R92C_CR_NETTYPE_INFRA; 1664 break; 1665 1666 case IEEE80211_M_IBSS: 1667 type = R92C_CR_NETTYPE_ADHOC; 1668 break; 1669 1670 default: 1671 type = R92C_CR_NETTYPE_NOLINK; 1672 break; 1673 } 1674 1675 return type; 1676 } 1677 1678 static void 1679 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1680 { 1681 uint8_t reg; 1682 1683 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1684 __func__, type)); 1685 1686 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1687 1688 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1689 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1690 } 1691 1692 static void 1693 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1694 { 1695 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1696 uint64_t tsf; 1697 1698 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1699 1700 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1701 1702 /* Enable TSF synchronization. */ 1703 urtwn_write_1(sc, R92C_BCN_CTRL, 1704 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1705 1706 /* Correct TSF */ 1707 urtwn_write_1(sc, R92C_BCN_CTRL, 1708 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1709 1710 /* Set initial TSF. */ 1711 tsf = ni->ni_tstamp.tsf; 1712 tsf = le64toh(tsf); 1713 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1714 tsf -= IEEE80211_DUR_TU; 1715 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1716 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1717 1718 urtwn_write_1(sc, R92C_BCN_CTRL, 1719 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1720 } 1721 1722 static void 1723 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1724 { 1725 uint8_t reg; 1726 1727 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1728 __func__, led, on)); 1729 1730 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1731 1732 if (led == URTWN_LED_LINK) { 1733 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1734 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1735 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1736 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1737 (R92C_LEDCFG0_DIS << 1)); 1738 if (on) { 1739 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1740 R92E_LEDSON; 1741 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1742 } 1743 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1744 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1745 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1746 if (!on) { 1747 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1748 urtwn_write_1(sc, R92C_LEDCFG2, 1749 reg | R92C_LEDCFG0_DIS); 1750 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1751 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1752 reg & 0xfe); 1753 } 1754 } else { 1755 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1756 if (!on) { 1757 reg |= R92C_LEDCFG0_DIS; 1758 } 1759 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1760 } 1761 sc->ledlink = on; /* Save LED state. */ 1762 } 1763 } 1764 1765 static void 1766 urtwn_calib_to(void *arg) 1767 { 1768 struct urtwn_softc *sc = arg; 1769 1770 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1771 1772 if (sc->sc_dying) 1773 return; 1774 1775 /* Do it in a process context. */ 1776 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1777 } 1778 1779 /* ARGSUSED */ 1780 static void 1781 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1782 { 1783 struct r92c_fw_cmd_rssi cmd; 1784 struct r92e_fw_cmd_rssi cmde; 1785 1786 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1787 1788 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1789 goto restart_timer; 1790 1791 mutex_enter(&sc->sc_write_mtx); 1792 if (sc->avg_pwdb != -1) { 1793 /* Indicate Rx signal strength to FW for rate adaptation. */ 1794 memset(&cmd, 0, sizeof(cmd)); 1795 memset(&cmde, 0, sizeof(cmde)); 1796 cmd.macid = 0; /* BSS. */ 1797 cmde.macid = 0; /* BSS. */ 1798 cmd.pwdb = sc->avg_pwdb; 1799 cmde.pwdb = sc->avg_pwdb; 1800 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1801 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1802 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1803 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1804 sizeof(cmd)); 1805 } else { 1806 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1807 sizeof(cmde)); 1808 } 1809 } 1810 1811 /* Do temperature compensation. */ 1812 urtwn_temp_calib(sc); 1813 mutex_exit(&sc->sc_write_mtx); 1814 1815 restart_timer: 1816 if (!sc->sc_dying) { 1817 /* Restart calibration timer. */ 1818 callout_schedule(&sc->sc_calib_to, hz); 1819 } 1820 } 1821 1822 static void 1823 urtwn_next_scan(void *arg) 1824 { 1825 struct urtwn_softc *sc = arg; 1826 int s; 1827 1828 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1829 1830 if (sc->sc_dying) 1831 return; 1832 1833 s = splnet(); 1834 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1835 ieee80211_next_scan(&sc->sc_ic); 1836 splx(s); 1837 } 1838 1839 static void 1840 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1841 { 1842 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1843 ether_sprintf(ni->ni_macaddr))); 1844 /* start with lowest Tx rate */ 1845 ni->ni_txrate = 0; 1846 } 1847 1848 static int 1849 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1850 { 1851 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1852 struct urtwn_cmd_newstate cmd; 1853 1854 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1855 device_xname(sc->sc_dev), __func__, 1856 ieee80211_state_name[nstate], nstate, arg)); 1857 1858 callout_stop(&sc->sc_scan_to); 1859 callout_stop(&sc->sc_calib_to); 1860 1861 /* Do it in a process context. */ 1862 cmd.state = nstate; 1863 cmd.arg = arg; 1864 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1865 return 0; 1866 } 1867 1868 static void 1869 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1870 { 1871 struct urtwn_cmd_newstate *cmd = arg; 1872 struct ieee80211com *ic = &sc->sc_ic; 1873 struct ieee80211_node *ni; 1874 enum ieee80211_state ostate = ic->ic_state; 1875 enum ieee80211_state nstate = cmd->state; 1876 uint32_t reg; 1877 uint8_t sifs_time, msr; 1878 int s; 1879 1880 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1881 device_xname(sc->sc_dev), __func__, 1882 ieee80211_state_name[ostate], ostate, 1883 ieee80211_state_name[nstate], nstate)); 1884 1885 s = splnet(); 1886 mutex_enter(&sc->sc_write_mtx); 1887 1888 callout_stop(&sc->sc_scan_to); 1889 callout_stop(&sc->sc_calib_to); 1890 1891 switch (ostate) { 1892 case IEEE80211_S_INIT: 1893 break; 1894 1895 case IEEE80211_S_SCAN: 1896 if (nstate != IEEE80211_S_SCAN) { 1897 /* 1898 * End of scanning 1899 */ 1900 /* flush 4-AC Queue after site_survey */ 1901 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1902 1903 /* Allow Rx from our BSSID only. */ 1904 urtwn_write_4(sc, R92C_RCR, 1905 urtwn_read_4(sc, R92C_RCR) | 1906 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1907 } 1908 break; 1909 1910 case IEEE80211_S_AUTH: 1911 case IEEE80211_S_ASSOC: 1912 break; 1913 1914 case IEEE80211_S_RUN: 1915 /* Turn link LED off. */ 1916 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1917 1918 /* Set media status to 'No Link'. */ 1919 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1920 1921 /* Stop Rx of data frames. */ 1922 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1923 1924 /* Reset TSF. */ 1925 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1926 1927 /* Disable TSF synchronization. */ 1928 urtwn_write_1(sc, R92C_BCN_CTRL, 1929 urtwn_read_1(sc, R92C_BCN_CTRL) | 1930 R92C_BCN_CTRL_DIS_TSF_UDT0); 1931 1932 /* Back to 20MHz mode */ 1933 urtwn_set_chan(sc, ic->ic_curchan, 1934 IEEE80211_HTINFO_2NDCHAN_NONE); 1935 1936 if (ic->ic_opmode == IEEE80211_M_IBSS || 1937 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1938 /* Stop BCN */ 1939 urtwn_write_1(sc, R92C_BCN_CTRL, 1940 urtwn_read_1(sc, R92C_BCN_CTRL) & 1941 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1942 } 1943 1944 /* Reset EDCA parameters. */ 1945 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1946 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1947 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1948 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1949 1950 /* flush all cam entries */ 1951 urtwn_cam_init(sc); 1952 break; 1953 } 1954 1955 switch (nstate) { 1956 case IEEE80211_S_INIT: 1957 /* Turn link LED off. */ 1958 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1959 break; 1960 1961 case IEEE80211_S_SCAN: 1962 if (ostate != IEEE80211_S_SCAN) { 1963 /* 1964 * Begin of scanning 1965 */ 1966 1967 /* Set gain for scanning. */ 1968 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1969 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1970 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1971 1972 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1973 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1974 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1975 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1976 } 1977 1978 /* Set media status to 'No Link'. */ 1979 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1980 1981 /* Allow Rx from any BSSID. */ 1982 urtwn_write_4(sc, R92C_RCR, 1983 urtwn_read_4(sc, R92C_RCR) & 1984 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1985 1986 /* Stop Rx of data frames. */ 1987 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1988 1989 /* Disable update TSF */ 1990 urtwn_write_1(sc, R92C_BCN_CTRL, 1991 urtwn_read_1(sc, R92C_BCN_CTRL) | 1992 R92C_BCN_CTRL_DIS_TSF_UDT0); 1993 } 1994 1995 /* Make link LED blink during scan. */ 1996 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1997 1998 /* Pause AC Tx queues. */ 1999 urtwn_write_1(sc, R92C_TXPAUSE, 2000 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2001 2002 urtwn_set_chan(sc, ic->ic_curchan, 2003 IEEE80211_HTINFO_2NDCHAN_NONE); 2004 2005 /* Start periodic scan. */ 2006 if (!sc->sc_dying) 2007 callout_schedule(&sc->sc_scan_to, hz / 5); 2008 break; 2009 2010 case IEEE80211_S_AUTH: 2011 /* Set initial gain under link. */ 2012 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2013 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2014 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2015 2016 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2017 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2018 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2019 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2020 } 2021 2022 /* Set media status to 'No Link'. */ 2023 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2024 2025 /* Allow Rx from any BSSID. */ 2026 urtwn_write_4(sc, R92C_RCR, 2027 urtwn_read_4(sc, R92C_RCR) & 2028 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2029 2030 urtwn_set_chan(sc, ic->ic_curchan, 2031 IEEE80211_HTINFO_2NDCHAN_NONE); 2032 break; 2033 2034 case IEEE80211_S_ASSOC: 2035 break; 2036 2037 case IEEE80211_S_RUN: 2038 ni = ic->ic_bss; 2039 2040 /* XXX: Set 20MHz mode */ 2041 urtwn_set_chan(sc, ic->ic_curchan, 2042 IEEE80211_HTINFO_2NDCHAN_NONE); 2043 2044 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2045 /* Back to 20MHz mode */ 2046 urtwn_set_chan(sc, ic->ic_curchan, 2047 IEEE80211_HTINFO_2NDCHAN_NONE); 2048 2049 /* Set media status to 'No Link'. */ 2050 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2051 2052 /* Enable Rx of data frames. */ 2053 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2054 2055 /* Allow Rx from any BSSID. */ 2056 urtwn_write_4(sc, R92C_RCR, 2057 urtwn_read_4(sc, R92C_RCR) & 2058 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2059 2060 /* Accept Rx data/control/management frames */ 2061 urtwn_write_4(sc, R92C_RCR, 2062 urtwn_read_4(sc, R92C_RCR) | 2063 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2064 2065 /* Turn link LED on. */ 2066 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2067 break; 2068 } 2069 2070 /* Set media status to 'Associated'. */ 2071 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2072 2073 /* Set BSSID. */ 2074 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2075 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2076 2077 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2078 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2079 } else { 2080 /* 802.11b/g */ 2081 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2082 } 2083 2084 /* Enable Rx of data frames. */ 2085 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2086 2087 /* Set beacon interval. */ 2088 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2089 2090 msr = urtwn_read_1(sc, R92C_MSR); 2091 msr &= R92C_MSR_MASK; 2092 switch (ic->ic_opmode) { 2093 case IEEE80211_M_STA: 2094 /* Allow Rx from our BSSID only. */ 2095 urtwn_write_4(sc, R92C_RCR, 2096 urtwn_read_4(sc, R92C_RCR) | 2097 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2098 2099 /* Enable TSF synchronization. */ 2100 urtwn_tsf_sync_enable(sc); 2101 2102 msr |= R92C_MSR_INFRA; 2103 break; 2104 case IEEE80211_M_HOSTAP: 2105 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2106 2107 /* Allow Rx from any BSSID. */ 2108 urtwn_write_4(sc, R92C_RCR, 2109 urtwn_read_4(sc, R92C_RCR) & 2110 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2111 2112 /* Reset TSF timer to zero. */ 2113 reg = urtwn_read_4(sc, R92C_TCR); 2114 reg &= ~0x01; 2115 urtwn_write_4(sc, R92C_TCR, reg); 2116 reg |= 0x01; 2117 urtwn_write_4(sc, R92C_TCR, reg); 2118 2119 msr |= R92C_MSR_AP; 2120 break; 2121 default: 2122 msr |= R92C_MSR_ADHOC; 2123 break; 2124 } 2125 urtwn_write_1(sc, R92C_MSR, msr); 2126 2127 sifs_time = 10; 2128 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2129 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2130 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2131 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2132 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2133 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2134 2135 /* Initialize rate adaptation. */ 2136 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2137 ISSET(sc->chip, URTWN_CHIP_92EU)) 2138 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2139 else 2140 urtwn_ra_init(sc); 2141 2142 /* Turn link LED on. */ 2143 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2144 2145 /* Reset average RSSI. */ 2146 sc->avg_pwdb = -1; 2147 2148 /* Reset temperature calibration state machine. */ 2149 sc->thcal_state = 0; 2150 sc->thcal_lctemp = 0; 2151 2152 /* Start periodic calibration. */ 2153 if (!sc->sc_dying) 2154 callout_schedule(&sc->sc_calib_to, hz); 2155 break; 2156 } 2157 2158 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2159 2160 mutex_exit(&sc->sc_write_mtx); 2161 splx(s); 2162 } 2163 2164 static int 2165 urtwn_wme_update(struct ieee80211com *ic) 2166 { 2167 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2168 2169 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2170 2171 /* don't override default WME values if WME is not actually enabled */ 2172 if (!(ic->ic_flags & IEEE80211_F_WME)) 2173 return 0; 2174 2175 /* Do it in a process context. */ 2176 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2177 return 0; 2178 } 2179 2180 static void 2181 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2182 { 2183 static const uint16_t ac2reg[WME_NUM_AC] = { 2184 R92C_EDCA_BE_PARAM, 2185 R92C_EDCA_BK_PARAM, 2186 R92C_EDCA_VI_PARAM, 2187 R92C_EDCA_VO_PARAM 2188 }; 2189 struct ieee80211com *ic = &sc->sc_ic; 2190 const struct wmeParams *wmep; 2191 int ac, aifs, slottime; 2192 int s; 2193 2194 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2195 __func__)); 2196 2197 s = splnet(); 2198 mutex_enter(&sc->sc_write_mtx); 2199 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2200 for (ac = 0; ac < WME_NUM_AC; ac++) { 2201 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2202 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2203 aifs = wmep->wmep_aifsn * slottime + 10; 2204 urtwn_write_4(sc, ac2reg[ac], 2205 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2206 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2207 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2208 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2209 } 2210 mutex_exit(&sc->sc_write_mtx); 2211 splx(s); 2212 } 2213 2214 static void 2215 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2216 { 2217 int pwdb; 2218 2219 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2220 device_xname(sc->sc_dev), __func__, rate, rssi)); 2221 2222 /* Convert antenna signal to percentage. */ 2223 if (rssi <= -100 || rssi >= 20) 2224 pwdb = 0; 2225 else if (rssi >= 0) 2226 pwdb = 100; 2227 else 2228 pwdb = 100 + rssi; 2229 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2230 if (rate <= 3) { 2231 /* CCK gain is smaller than OFDM/MCS gain. */ 2232 pwdb += 6; 2233 if (pwdb > 100) 2234 pwdb = 100; 2235 if (pwdb <= 14) 2236 pwdb -= 4; 2237 else if (pwdb <= 26) 2238 pwdb -= 8; 2239 else if (pwdb <= 34) 2240 pwdb -= 6; 2241 else if (pwdb <= 42) 2242 pwdb -= 2; 2243 } 2244 } 2245 if (sc->avg_pwdb == -1) /* Init. */ 2246 sc->avg_pwdb = pwdb; 2247 else if (sc->avg_pwdb < pwdb) 2248 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2249 else 2250 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2251 2252 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2253 device_xname(sc->sc_dev), __func__, 2254 rate, rssi, pwdb, sc->avg_pwdb)); 2255 } 2256 2257 static int8_t 2258 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2259 { 2260 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2261 struct r92c_rx_phystat *phy; 2262 struct r92c_rx_cck *cck; 2263 uint8_t rpt; 2264 int8_t rssi; 2265 2266 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2267 __func__, rate)); 2268 2269 if (rate <= 3) { 2270 cck = (struct r92c_rx_cck *)physt; 2271 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2272 rpt = (cck->agc_rpt >> 5) & 0x3; 2273 rssi = (cck->agc_rpt & 0x1f) << 1; 2274 } else { 2275 rpt = (cck->agc_rpt >> 6) & 0x3; 2276 rssi = cck->agc_rpt & 0x3e; 2277 } 2278 rssi = cckoff[rpt] - rssi; 2279 } else { /* OFDM/HT. */ 2280 phy = (struct r92c_rx_phystat *)physt; 2281 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2282 } 2283 return rssi; 2284 } 2285 2286 static int8_t 2287 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2288 { 2289 struct r92c_rx_phystat *phy; 2290 struct r88e_rx_cck *cck; 2291 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2292 int8_t rssi; 2293 2294 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2295 __func__, rate)); 2296 2297 rssi = 0; 2298 if (rate <= 3) { 2299 cck = (struct r88e_rx_cck *)physt; 2300 cck_agc_rpt = cck->agc_rpt; 2301 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2302 vga_idx = cck_agc_rpt & 0x1f; 2303 switch (lna_idx) { 2304 case 7: 2305 if (vga_idx <= 27) 2306 rssi = -100 + 2* (27 - vga_idx); 2307 else 2308 rssi = -100; 2309 break; 2310 case 6: 2311 rssi = -48 + 2 * (2 - vga_idx); 2312 break; 2313 case 5: 2314 rssi = -42 + 2 * (7 - vga_idx); 2315 break; 2316 case 4: 2317 rssi = -36 + 2 * (7 - vga_idx); 2318 break; 2319 case 3: 2320 rssi = -24 + 2 * (7 - vga_idx); 2321 break; 2322 case 2: 2323 rssi = -12 + 2 * (5 - vga_idx); 2324 break; 2325 case 1: 2326 rssi = 8 - (2 * vga_idx); 2327 break; 2328 case 0: 2329 rssi = 14 - (2 * vga_idx); 2330 break; 2331 } 2332 rssi += 6; 2333 } else { /* OFDM/HT. */ 2334 phy = (struct r92c_rx_phystat *)physt; 2335 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2336 } 2337 return rssi; 2338 } 2339 2340 static void 2341 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2342 { 2343 struct ieee80211com *ic = &sc->sc_ic; 2344 struct ifnet *ifp = ic->ic_ifp; 2345 struct ieee80211_frame *wh; 2346 struct ieee80211_node *ni; 2347 struct r92c_rx_desc_usb *stat; 2348 uint32_t rxdw0, rxdw3; 2349 struct mbuf *m; 2350 uint8_t rate; 2351 int8_t rssi = 0; 2352 int s, infosz; 2353 2354 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2355 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2356 2357 stat = (struct r92c_rx_desc_usb *)buf; 2358 rxdw0 = le32toh(stat->rxdw0); 2359 rxdw3 = le32toh(stat->rxdw3); 2360 2361 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2362 /* 2363 * This should not happen since we setup our Rx filter 2364 * to not receive these frames. 2365 */ 2366 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2367 device_xname(sc->sc_dev), __func__)); 2368 ifp->if_ierrors++; 2369 return; 2370 } 2371 /* 2372 * XXX: This will drop most control packets. Do we really 2373 * want this in IEEE80211_M_MONITOR mode? 2374 */ 2375 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2376 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2377 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2378 device_xname(sc->sc_dev), __func__, pktlen)); 2379 ic->ic_stats.is_rx_tooshort++; 2380 ifp->if_ierrors++; 2381 return; 2382 } 2383 if (__predict_false(pktlen > MCLBYTES)) { 2384 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2385 device_xname(sc->sc_dev), __func__, pktlen)); 2386 ifp->if_ierrors++; 2387 return; 2388 } 2389 2390 rate = MS(rxdw3, R92C_RXDW3_RATE); 2391 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2392 2393 /* Get RSSI from PHY status descriptor if present. */ 2394 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2395 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2396 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2397 else 2398 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2399 /* Update our average RSSI. */ 2400 urtwn_update_avgrssi(sc, rate, rssi); 2401 } 2402 2403 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2404 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2405 2406 MGETHDR(m, M_DONTWAIT, MT_DATA); 2407 if (__predict_false(m == NULL)) { 2408 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2409 ic->ic_stats.is_rx_nobuf++; 2410 ifp->if_ierrors++; 2411 return; 2412 } 2413 if (pktlen > (int)MHLEN) { 2414 MCLGET(m, M_DONTWAIT); 2415 if (__predict_false(!(m->m_flags & M_EXT))) { 2416 aprint_error_dev(sc->sc_dev, 2417 "couldn't allocate rx mbuf cluster\n"); 2418 m_freem(m); 2419 ic->ic_stats.is_rx_nobuf++; 2420 ifp->if_ierrors++; 2421 return; 2422 } 2423 } 2424 2425 /* Finalize mbuf. */ 2426 m_set_rcvif(m, ifp); 2427 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2428 memcpy(mtod(m, uint8_t *), wh, pktlen); 2429 m->m_pkthdr.len = m->m_len = pktlen; 2430 2431 s = splnet(); 2432 if (__predict_false(sc->sc_drvbpf != NULL)) { 2433 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2434 2435 tap->wr_flags = 0; 2436 if (!(rxdw3 & R92C_RXDW3_HT)) { 2437 switch (rate) { 2438 /* CCK. */ 2439 case 0: tap->wr_rate = 2; break; 2440 case 1: tap->wr_rate = 4; break; 2441 case 2: tap->wr_rate = 11; break; 2442 case 3: tap->wr_rate = 22; break; 2443 /* OFDM. */ 2444 case 4: tap->wr_rate = 12; break; 2445 case 5: tap->wr_rate = 18; break; 2446 case 6: tap->wr_rate = 24; break; 2447 case 7: tap->wr_rate = 36; break; 2448 case 8: tap->wr_rate = 48; break; 2449 case 9: tap->wr_rate = 72; break; 2450 case 10: tap->wr_rate = 96; break; 2451 case 11: tap->wr_rate = 108; break; 2452 } 2453 } else if (rate >= 12) { /* MCS0~15. */ 2454 /* Bit 7 set means HT MCS instead of rate. */ 2455 tap->wr_rate = 0x80 | (rate - 12); 2456 } 2457 tap->wr_dbm_antsignal = rssi; 2458 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2459 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2460 2461 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2462 } 2463 2464 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2465 2466 /* push the frame up to the 802.11 stack */ 2467 ieee80211_input(ic, m, ni, rssi, 0); 2468 2469 /* Node is no longer needed. */ 2470 ieee80211_free_node(ni); 2471 2472 splx(s); 2473 } 2474 2475 static void 2476 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2477 { 2478 struct urtwn_rx_data *data = priv; 2479 struct urtwn_softc *sc = data->sc; 2480 struct r92c_rx_desc_usb *stat; 2481 size_t pidx = data->pidx; 2482 uint32_t rxdw0; 2483 uint8_t *buf; 2484 int len, totlen, pktlen, infosz, npkts; 2485 2486 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2487 device_xname(sc->sc_dev), __func__, status)); 2488 2489 mutex_enter(&sc->sc_rx_mtx); 2490 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2491 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2492 /* Put this Rx buffer back to our free list. */ 2493 mutex_exit(&sc->sc_rx_mtx); 2494 2495 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2496 if (status == USBD_STALLED) 2497 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2498 else if (status != USBD_CANCELLED) 2499 goto resubmit; 2500 return; 2501 } 2502 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2503 2504 if (__predict_false(len < (int)sizeof(*stat))) { 2505 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2506 device_xname(sc->sc_dev), __func__, len)); 2507 goto resubmit; 2508 } 2509 buf = data->buf; 2510 2511 /* Get the number of encapsulated frames. */ 2512 stat = (struct r92c_rx_desc_usb *)buf; 2513 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2514 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2515 device_xname(sc->sc_dev), __func__, npkts)); 2516 2517 if (npkts != 0) 2518 rnd_add_uint32(&sc->rnd_source, npkts); 2519 2520 /* Process all of them. */ 2521 while (npkts-- > 0) { 2522 if (__predict_false(len < (int)sizeof(*stat))) { 2523 DPRINTFN(DBG_RX, 2524 ("%s: %s: len(%d) is short than header\n", 2525 device_xname(sc->sc_dev), __func__, len)); 2526 break; 2527 } 2528 stat = (struct r92c_rx_desc_usb *)buf; 2529 rxdw0 = le32toh(stat->rxdw0); 2530 2531 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2532 if (__predict_false(pktlen == 0)) { 2533 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2534 device_xname(sc->sc_dev), __func__)); 2535 break; 2536 } 2537 2538 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2539 2540 /* Make sure everything fits in xfer. */ 2541 totlen = sizeof(*stat) + infosz + pktlen; 2542 if (__predict_false(totlen > len)) { 2543 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2544 device_xname(sc->sc_dev), __func__, totlen, 2545 (int)sizeof(*stat), infosz, pktlen, len)); 2546 break; 2547 } 2548 2549 /* Process 802.11 frame. */ 2550 urtwn_rx_frame(sc, buf, pktlen); 2551 2552 /* Next chunk is 128-byte aligned. */ 2553 totlen = roundup2(totlen, 128); 2554 buf += totlen; 2555 len -= totlen; 2556 } 2557 2558 resubmit: 2559 /* Setup a new transfer. */ 2560 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2561 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2562 (void)usbd_transfer(xfer); 2563 } 2564 2565 static void 2566 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2567 { 2568 size_t pidx = data->pidx; 2569 2570 mutex_enter(&sc->sc_tx_mtx); 2571 /* Put this Tx buffer back to our free list. */ 2572 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2573 mutex_exit(&sc->sc_tx_mtx); 2574 } 2575 2576 static void 2577 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2578 { 2579 struct urtwn_tx_data *data = priv; 2580 struct urtwn_softc *sc = data->sc; 2581 struct ifnet *ifp = &sc->sc_if; 2582 size_t pidx = data->pidx; 2583 int s; 2584 2585 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2586 device_xname(sc->sc_dev), __func__, status)); 2587 2588 urtwn_put_tx_data(sc, data); 2589 2590 s = splnet(); 2591 sc->tx_timer = 0; 2592 ifp->if_flags &= ~IFF_OACTIVE; 2593 2594 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2595 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2596 if (status == USBD_STALLED) { 2597 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2598 usbd_clear_endpoint_stall_async(pipe); 2599 } 2600 printf("ERROR1\n"); 2601 ifp->if_oerrors++; 2602 } 2603 splx(s); 2604 return; 2605 } 2606 2607 ifp->if_opackets++; 2608 urtwn_start(ifp); 2609 splx(s); 2610 2611 } 2612 2613 static int 2614 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2615 struct urtwn_tx_data *data) 2616 { 2617 struct ieee80211com *ic = &sc->sc_ic; 2618 struct ieee80211_frame *wh; 2619 struct ieee80211_key *k = NULL; 2620 struct r92c_tx_desc_usb *txd; 2621 size_t i, padsize, xferlen, txd_len; 2622 uint16_t seq, sum; 2623 uint8_t raid, type, tid; 2624 int s, hasqos, error; 2625 2626 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2627 2628 wh = mtod(m, struct ieee80211_frame *); 2629 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2630 txd_len = sizeof(*txd); 2631 2632 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2633 txd_len = 32; 2634 2635 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2636 k = ieee80211_crypto_encap(ic, ni, m); 2637 if (k == NULL) { 2638 urtwn_put_tx_data(sc, data); 2639 m_free(m); 2640 return ENOBUFS; 2641 } 2642 2643 /* packet header may have moved, reset our local pointer */ 2644 wh = mtod(m, struct ieee80211_frame *); 2645 } 2646 2647 if (__predict_false(sc->sc_drvbpf != NULL)) { 2648 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2649 2650 tap->wt_flags = 0; 2651 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2652 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2653 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2654 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2655 2656 /* XXX: set tap->wt_rate? */ 2657 2658 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2659 } 2660 2661 /* non-qos data frames */ 2662 tid = R92C_TXDW1_QSEL_BE; 2663 if ((hasqos = ieee80211_has_qos(wh))) { 2664 /* data frames in 11n mode */ 2665 struct ieee80211_qosframe *qwh = (void *)wh; 2666 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2667 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2668 tid = R92C_TXDW1_QSEL_MGNT; 2669 } 2670 2671 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2672 padsize = 8; 2673 else 2674 padsize = 0; 2675 2676 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2677 padsize = 0; 2678 2679 /* Fill Tx descriptor. */ 2680 txd = (struct r92c_tx_desc_usb *)data->buf; 2681 memset(txd, 0, txd_len + padsize); 2682 2683 txd->txdw0 |= htole32( 2684 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2685 SM(R92C_TXDW0_OFFSET, txd_len)); 2686 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2687 txd->txdw0 |= htole32( 2688 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2689 } 2690 2691 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2692 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2693 2694 /* fix pad field */ 2695 if (padsize > 0) { 2696 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2697 device_xname(sc->sc_dev), __func__, padsize)); 2698 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2699 } 2700 2701 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2702 type == IEEE80211_FC0_TYPE_DATA) { 2703 if (ic->ic_curmode == IEEE80211_MODE_11B) 2704 raid = R92C_RAID_11B; 2705 else 2706 raid = R92C_RAID_11BG; 2707 DPRINTFN(DBG_TX, 2708 ("%s: %s: data packet: tid=%d, raid=%d\n", 2709 device_xname(sc->sc_dev), __func__, tid, raid)); 2710 2711 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2712 txd->txdw1 |= htole32( 2713 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2714 SM(R92C_TXDW1_QSEL, tid) | 2715 SM(R92C_TXDW1_RAID, raid) | 2716 R92C_TXDW1_AGGBK); 2717 } else 2718 txd->txdw1 |= htole32( 2719 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2720 SM(R92C_TXDW1_QSEL, tid) | 2721 SM(R92C_TXDW1_RAID, raid) | 2722 R92C_TXDW1_AGGBK); 2723 2724 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2725 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2726 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2727 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2728 2729 if (hasqos) { 2730 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2731 } 2732 2733 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2734 /* for 11g */ 2735 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2736 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2737 R92C_TXDW4_HWRTSEN); 2738 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2739 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2740 R92C_TXDW4_HWRTSEN); 2741 } 2742 } 2743 /* Send RTS at OFDM24. */ 2744 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2745 txd->txdw5 |= htole32(0x0001ff00); 2746 /* Send data at OFDM54. */ 2747 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2748 txd->txdw5 |= htole32(0x13 & 0x3f); 2749 else 2750 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2751 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2752 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2753 device_xname(sc->sc_dev), __func__)); 2754 txd->txdw1 |= htole32( 2755 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2756 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2757 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2758 2759 /* Force CCK1. */ 2760 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2761 /* Use 1Mbps */ 2762 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2763 } else { 2764 /* broadcast or multicast packets */ 2765 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2766 device_xname(sc->sc_dev), __func__)); 2767 txd->txdw1 |= htole32( 2768 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2769 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2770 2771 /* Force CCK1. */ 2772 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2773 /* Use 1Mbps */ 2774 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2775 } 2776 /* Set sequence number */ 2777 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2778 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2779 txd->txdseq |= htole16(seq); 2780 2781 if (!hasqos) { 2782 /* Use HW sequence numbering for non-QoS frames. */ 2783 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2784 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2785 } 2786 } else { 2787 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2788 R92E_HWSEQ_SHIFT); 2789 if (!hasqos) { 2790 /* Use HW sequence numbering for non-QoS frames. */ 2791 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2792 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2793 } 2794 } 2795 2796 /* Compute Tx descriptor checksum. */ 2797 sum = 0; 2798 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2799 sum ^= ((uint16_t *)txd)[i]; 2800 txd->txdsum = sum; /* NB: already little endian. */ 2801 2802 xferlen = txd_len + m->m_pkthdr.len + padsize; 2803 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2804 2805 s = splnet(); 2806 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2807 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2808 urtwn_txeof); 2809 error = usbd_transfer(data->xfer); 2810 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2811 error != USBD_IN_PROGRESS)) { 2812 splx(s); 2813 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2814 device_xname(sc->sc_dev), __func__, error)); 2815 return error; 2816 } 2817 splx(s); 2818 return 0; 2819 } 2820 2821 struct urtwn_tx_data * 2822 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2823 { 2824 struct urtwn_tx_data *data = NULL; 2825 2826 mutex_enter(&sc->sc_tx_mtx); 2827 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2828 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2829 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2830 } 2831 mutex_exit(&sc->sc_tx_mtx); 2832 2833 return data; 2834 } 2835 2836 static void 2837 urtwn_start(struct ifnet *ifp) 2838 { 2839 struct urtwn_softc *sc = ifp->if_softc; 2840 struct ieee80211com *ic = &sc->sc_ic; 2841 struct urtwn_tx_data *data; 2842 struct ether_header *eh; 2843 struct ieee80211_node *ni; 2844 struct mbuf *m; 2845 2846 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2847 2848 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2849 return; 2850 2851 data = NULL; 2852 for (;;) { 2853 /* Send pending management frames first. */ 2854 IF_POLL(&ic->ic_mgtq, m); 2855 if (m != NULL) { 2856 /* Use AC_VO for management frames. */ 2857 2858 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2859 2860 if (data == NULL) { 2861 ifp->if_flags |= IFF_OACTIVE; 2862 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2863 device_xname(sc->sc_dev))); 2864 return; 2865 } 2866 IF_DEQUEUE(&ic->ic_mgtq, m); 2867 ni = M_GETCTX(m, struct ieee80211_node *); 2868 M_CLEARCTX(m); 2869 goto sendit; 2870 } 2871 if (ic->ic_state != IEEE80211_S_RUN) 2872 break; 2873 2874 /* Encapsulate and send data frames. */ 2875 IFQ_POLL(&ifp->if_snd, m); 2876 if (m == NULL) 2877 break; 2878 2879 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2880 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2881 uint8_t qid = WME_AC_BE; 2882 if (ieee80211_has_qos(wh)) { 2883 /* data frames in 11n mode */ 2884 struct ieee80211_qosframe *qwh = (void *)wh; 2885 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2886 qid = TID_TO_WME_AC(tid); 2887 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2888 qid = WME_AC_VO; 2889 } 2890 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2891 2892 if (data == NULL) { 2893 ifp->if_flags |= IFF_OACTIVE; 2894 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2895 device_xname(sc->sc_dev))); 2896 return; 2897 } 2898 IFQ_DEQUEUE(&ifp->if_snd, m); 2899 2900 if (m->m_len < (int)sizeof(*eh) && 2901 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2902 printf("ERROR6\n"); 2903 ifp->if_oerrors++; 2904 urtwn_put_tx_data(sc, data); 2905 m_freem(m); 2906 continue; 2907 } 2908 eh = mtod(m, struct ether_header *); 2909 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2910 if (ni == NULL) { 2911 printf("ERROR5\n"); 2912 ifp->if_oerrors++; 2913 urtwn_put_tx_data(sc, data); 2914 m_freem(m); 2915 continue; 2916 } 2917 2918 bpf_mtap(ifp, m, BPF_D_OUT); 2919 2920 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2921 ieee80211_free_node(ni); 2922 printf("ERROR4\n"); 2923 ifp->if_oerrors++; 2924 urtwn_put_tx_data(sc, data); 2925 m_freem(m); 2926 continue; 2927 } 2928 sendit: 2929 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2930 2931 if (urtwn_tx(sc, m, ni, data) != 0) { 2932 m_freem(m); 2933 ieee80211_free_node(ni); 2934 printf("ERROR3\n"); 2935 ifp->if_oerrors++; 2936 continue; 2937 } 2938 m_freem(m); 2939 ieee80211_free_node(ni); 2940 sc->tx_timer = 5; 2941 ifp->if_timer = 1; 2942 } 2943 } 2944 2945 static void 2946 urtwn_watchdog(struct ifnet *ifp) 2947 { 2948 struct urtwn_softc *sc = ifp->if_softc; 2949 2950 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2951 2952 ifp->if_timer = 0; 2953 2954 if (sc->tx_timer > 0) { 2955 if (--sc->tx_timer == 0) { 2956 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2957 /* urtwn_init(ifp); XXX needs a process context! */ 2958 printf("ERROR2\n"); 2959 ifp->if_oerrors++; 2960 return; 2961 } 2962 ifp->if_timer = 1; 2963 } 2964 ieee80211_watchdog(&sc->sc_ic); 2965 } 2966 2967 static int 2968 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2969 { 2970 struct urtwn_softc *sc = ifp->if_softc; 2971 struct ieee80211com *ic = &sc->sc_ic; 2972 int s, error = 0; 2973 2974 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2975 device_xname(sc->sc_dev), __func__, cmd, data)); 2976 2977 s = splnet(); 2978 2979 switch (cmd) { 2980 case SIOCSIFFLAGS: 2981 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2982 break; 2983 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2984 case IFF_UP | IFF_RUNNING: 2985 break; 2986 case IFF_UP: 2987 urtwn_init(ifp); 2988 break; 2989 case IFF_RUNNING: 2990 urtwn_stop(ifp, 1); 2991 break; 2992 case 0: 2993 break; 2994 } 2995 break; 2996 2997 case SIOCADDMULTI: 2998 case SIOCDELMULTI: 2999 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3000 /* setup multicast filter, etc */ 3001 error = 0; 3002 } 3003 break; 3004 3005 case SIOCS80211CHANNEL: 3006 /* 3007 * This allows for fast channel switching in monitor mode 3008 * (used by kismet). In IBSS mode, we must explicitly reset 3009 * the interface to generate a new beacon frame. 3010 */ 3011 error = ieee80211_ioctl(ic, cmd, data); 3012 if (error == ENETRESET && 3013 ic->ic_opmode == IEEE80211_M_MONITOR) { 3014 urtwn_set_chan(sc, ic->ic_curchan, 3015 IEEE80211_HTINFO_2NDCHAN_NONE); 3016 error = 0; 3017 } 3018 break; 3019 3020 default: 3021 error = ieee80211_ioctl(ic, cmd, data); 3022 break; 3023 } 3024 if (error == ENETRESET) { 3025 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3026 (IFF_UP | IFF_RUNNING) && 3027 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3028 urtwn_init(ifp); 3029 } 3030 error = 0; 3031 } 3032 3033 splx(s); 3034 3035 return error; 3036 } 3037 3038 static __inline int 3039 urtwn_power_on(struct urtwn_softc *sc) 3040 { 3041 3042 return sc->sc_power_on(sc); 3043 } 3044 3045 static int 3046 urtwn_r92c_power_on(struct urtwn_softc *sc) 3047 { 3048 uint32_t reg; 3049 int ntries; 3050 3051 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3052 3053 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3054 3055 /* Wait for autoload done bit. */ 3056 for (ntries = 0; ntries < 1000; ntries++) { 3057 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3058 break; 3059 DELAY(5); 3060 } 3061 if (ntries == 1000) { 3062 aprint_error_dev(sc->sc_dev, 3063 "timeout waiting for chip autoload\n"); 3064 return ETIMEDOUT; 3065 } 3066 3067 /* Unlock ISO/CLK/Power control register. */ 3068 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3069 /* Move SPS into PWM mode. */ 3070 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3071 DELAY(5); 3072 3073 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3074 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3075 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3076 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3077 DELAY(100); 3078 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3079 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3080 ~R92C_SYS_ISO_CTRL_MD2PP); 3081 } 3082 3083 /* Auto enable WLAN. */ 3084 urtwn_write_2(sc, R92C_APS_FSMCO, 3085 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3086 for (ntries = 0; ntries < 1000; ntries++) { 3087 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3088 R92C_APS_FSMCO_APFM_ONMAC)) 3089 break; 3090 DELAY(100); 3091 } 3092 if (ntries == 1000) { 3093 aprint_error_dev(sc->sc_dev, 3094 "timeout waiting for MAC auto ON\n"); 3095 return ETIMEDOUT; 3096 } 3097 3098 /* Enable radio, GPIO and LED functions. */ 3099 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3100 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3101 urtwn_write_2(sc, R92C_APS_FSMCO, 3102 R92C_APS_FSMCO_AFSM_HSUS | 3103 R92C_APS_FSMCO_PDN_EN | 3104 R92C_APS_FSMCO_PFM_ALDN); 3105 3106 /* Release RF digital isolation. */ 3107 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3108 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3109 3110 /* Initialize MAC. */ 3111 urtwn_write_1(sc, R92C_APSD_CTRL, 3112 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3113 for (ntries = 0; ntries < 200; ntries++) { 3114 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3115 R92C_APSD_CTRL_OFF_STATUS)) 3116 break; 3117 DELAY(5); 3118 } 3119 if (ntries == 200) { 3120 aprint_error_dev(sc->sc_dev, 3121 "timeout waiting for MAC initialization\n"); 3122 return ETIMEDOUT; 3123 } 3124 3125 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3126 reg = urtwn_read_2(sc, R92C_CR); 3127 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3128 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3129 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3130 R92C_CR_ENSEC; 3131 urtwn_write_2(sc, R92C_CR, reg); 3132 3133 urtwn_write_1(sc, 0xfe10, 0x19); 3134 return 0; 3135 } 3136 3137 static int 3138 urtwn_r92e_power_on(struct urtwn_softc *sc) 3139 { 3140 uint32_t reg; 3141 uint32_t val; 3142 int ntries; 3143 3144 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3145 3146 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3147 3148 /* Enable radio, GPIO and LED functions. */ 3149 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3150 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3151 urtwn_write_2(sc, R92C_APS_FSMCO, 3152 R92C_APS_FSMCO_AFSM_HSUS | 3153 R92C_APS_FSMCO_PDN_EN | 3154 R92C_APS_FSMCO_PFM_ALDN); 3155 3156 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3157 /* LDO. */ 3158 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3159 } 3160 else { 3161 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3162 R92C_SYS_SWR_CTRL2) & 0xffff); 3163 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3164 } 3165 3166 for (ntries = 0; ntries < 2; ntries++) { 3167 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3168 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3169 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3170 R92C_AFE_CTRL4)); 3171 } 3172 3173 /* Reset BB. */ 3174 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3175 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3176 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3177 3178 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3179 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3180 3181 /* Disable HWPDN. */ 3182 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3183 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3184 3185 /* Disable WL suspend. */ 3186 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3187 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3188 R92C_APS_FSMCO_AFSM_HSUS)); 3189 3190 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3191 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3192 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3193 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3194 for (ntries = 0; ntries < 10000; ntries++) { 3195 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3196 R92C_APS_FSMCO_APFM_ONMAC; 3197 if (val == 0x0) 3198 break; 3199 DELAY(10); 3200 } 3201 if (ntries == 10000) { 3202 aprint_error_dev(sc->sc_dev, 3203 "timeout waiting for chip power up\n"); 3204 return ETIMEDOUT; 3205 } 3206 3207 urtwn_write_2(sc, R92C_CR, 0x00); 3208 reg = urtwn_read_2(sc, R92C_CR); 3209 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3210 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3211 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3212 urtwn_write_2(sc, R92C_CR, reg); 3213 3214 return 0; 3215 } 3216 3217 static int 3218 urtwn_r88e_power_on(struct urtwn_softc *sc) 3219 { 3220 uint32_t reg; 3221 uint8_t val; 3222 int ntries; 3223 3224 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3225 3226 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3227 3228 /* Wait for power ready bit. */ 3229 for (ntries = 0; ntries < 5000; ntries++) { 3230 val = urtwn_read_1(sc, 0x6) & 0x2; 3231 if (val == 0x2) 3232 break; 3233 DELAY(10); 3234 } 3235 if (ntries == 5000) { 3236 aprint_error_dev(sc->sc_dev, 3237 "timeout waiting for chip power up\n"); 3238 return ETIMEDOUT; 3239 } 3240 3241 /* Reset BB. */ 3242 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3243 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3244 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3245 3246 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3247 3248 /* Disable HWPDN. */ 3249 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3250 3251 /* Disable WL suspend. */ 3252 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3253 3254 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3255 for (ntries = 0; ntries < 5000; ntries++) { 3256 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3257 break; 3258 DELAY(10); 3259 } 3260 if (ntries == 5000) 3261 return ETIMEDOUT; 3262 3263 /* Enable LDO normal mode. */ 3264 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3265 3266 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3267 urtwn_write_2(sc, R92C_CR, 0); 3268 reg = urtwn_read_2(sc, R92C_CR); 3269 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3270 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3271 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3272 urtwn_write_2(sc, R92C_CR, reg); 3273 3274 return 0; 3275 } 3276 3277 static int 3278 urtwn_llt_init(struct urtwn_softc *sc) 3279 { 3280 size_t i, page_count, pktbuf_count; 3281 uint32_t val; 3282 int error; 3283 3284 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3285 3286 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3287 3288 if (sc->chip & URTWN_CHIP_88E) 3289 page_count = R88E_TX_PAGE_COUNT; 3290 else if (sc->chip & URTWN_CHIP_92EU) 3291 page_count = R92E_TX_PAGE_COUNT; 3292 else 3293 page_count = R92C_TX_PAGE_COUNT; 3294 if (sc->chip & URTWN_CHIP_88E) 3295 pktbuf_count = R88E_TXPKTBUF_COUNT; 3296 else if (sc->chip & URTWN_CHIP_92EU) 3297 pktbuf_count = R88E_TXPKTBUF_COUNT; 3298 else 3299 pktbuf_count = R92C_TXPKTBUF_COUNT; 3300 3301 if (sc->chip & URTWN_CHIP_92EU) { 3302 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3303 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3304 DELAY(100); 3305 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3306 if (val & R92E_AUTO_LLT_EN) 3307 return EIO; 3308 return 0; 3309 } 3310 3311 /* Reserve pages [0; page_count]. */ 3312 for (i = 0; i < page_count; i++) { 3313 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3314 return error; 3315 } 3316 /* NB: 0xff indicates end-of-list. */ 3317 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3318 return error; 3319 /* 3320 * Use pages [page_count + 1; pktbuf_count - 1] 3321 * as ring buffer. 3322 */ 3323 for (++i; i < pktbuf_count - 1; i++) { 3324 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3325 return error; 3326 } 3327 /* Make the last page point to the beginning of the ring buffer. */ 3328 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3329 return error; 3330 } 3331 3332 static void 3333 urtwn_fw_reset(struct urtwn_softc *sc) 3334 { 3335 uint16_t reg; 3336 int ntries; 3337 3338 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3339 3340 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3341 3342 /* Tell 8051 to reset itself. */ 3343 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3344 3345 /* Wait until 8051 resets by itself. */ 3346 for (ntries = 0; ntries < 100; ntries++) { 3347 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3348 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3349 return; 3350 DELAY(50); 3351 } 3352 /* Force 8051 reset. */ 3353 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3354 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3355 } 3356 3357 static void 3358 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3359 { 3360 uint16_t reg; 3361 3362 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3363 3364 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3365 3366 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3367 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3368 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3369 } 3370 DELAY(50); 3371 3372 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3373 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3374 DELAY(50); 3375 3376 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3377 DELAY(50); 3378 3379 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3380 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3381 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3382 } 3383 DELAY(50); 3384 3385 } 3386 3387 static int 3388 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3389 { 3390 uint32_t reg; 3391 int off, mlen, error = 0; 3392 3393 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3394 device_xname(sc->sc_dev), __func__, page, buf, len)); 3395 3396 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3397 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3398 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3399 3400 off = R92C_FW_START_ADDR; 3401 while (len > 0) { 3402 if (len > 196) 3403 mlen = 196; 3404 else if (len > 4) 3405 mlen = 4; 3406 else 3407 mlen = 1; 3408 error = urtwn_write_region(sc, off, buf, mlen); 3409 if (error != 0) 3410 break; 3411 off += mlen; 3412 buf += mlen; 3413 len -= mlen; 3414 } 3415 return error; 3416 } 3417 3418 static int 3419 urtwn_load_firmware(struct urtwn_softc *sc) 3420 { 3421 firmware_handle_t fwh; 3422 const struct r92c_fw_hdr *hdr; 3423 const char *name; 3424 u_char *fw, *ptr; 3425 size_t len; 3426 uint32_t reg; 3427 int mlen, ntries, page, error; 3428 3429 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3430 3431 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3432 3433 /* Read firmware image from the filesystem. */ 3434 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3435 name = "rtl8188eufw.bin"; 3436 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3437 name = "rtl8192eefw.bin"; 3438 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3439 URTWN_CHIP_UMC_A_CUT) 3440 name = "rtl8192cfwU.bin"; 3441 else 3442 name = "rtl8192cfw.bin"; 3443 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3444 aprint_error_dev(sc->sc_dev, 3445 "failed load firmware of file %s (error %d)\n", name, 3446 error); 3447 return error; 3448 } 3449 const size_t fwlen = len = firmware_get_size(fwh); 3450 fw = firmware_malloc(len); 3451 if (fw == NULL) { 3452 aprint_error_dev(sc->sc_dev, 3453 "failed to allocate firmware memory\n"); 3454 firmware_close(fwh); 3455 return ENOMEM; 3456 } 3457 error = firmware_read(fwh, 0, fw, len); 3458 firmware_close(fwh); 3459 if (error != 0) { 3460 aprint_error_dev(sc->sc_dev, 3461 "failed to read firmware (error %d)\n", error); 3462 firmware_free(fw, fwlen); 3463 return error; 3464 } 3465 3466 len = fwlen; 3467 ptr = fw; 3468 hdr = (const struct r92c_fw_hdr *)ptr; 3469 /* Check if there is a valid FW header and skip it. */ 3470 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3471 (le16toh(hdr->signature) >> 4) == 0x88e || 3472 (le16toh(hdr->signature) >> 4) == 0x92e || 3473 (le16toh(hdr->signature) >> 4) == 0x92c) { 3474 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3475 device_xname(sc->sc_dev), __func__, 3476 le16toh(hdr->version), le16toh(hdr->subversion), 3477 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3478 ptr += sizeof(*hdr); 3479 len -= sizeof(*hdr); 3480 } 3481 3482 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3483 /* Reset MCU ready status */ 3484 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3485 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3486 ISSET(sc->chip, URTWN_CHIP_92EU)) 3487 urtwn_r88e_fw_reset(sc); 3488 else 3489 urtwn_fw_reset(sc); 3490 } 3491 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3492 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3493 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3494 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3495 R92C_SYS_FUNC_EN_CPUEN); 3496 } 3497 3498 /* download enabled */ 3499 urtwn_write_1(sc, R92C_MCUFWDL, 3500 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3501 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3502 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3503 3504 /* Reset the FWDL checksum. */ 3505 urtwn_write_1(sc, R92C_MCUFWDL, 3506 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3507 3508 DELAY(50); 3509 /* download firmware */ 3510 for (page = 0; len > 0; page++) { 3511 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3512 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3513 if (error != 0) { 3514 aprint_error_dev(sc->sc_dev, 3515 "could not load firmware page %d\n", page); 3516 goto fail; 3517 } 3518 ptr += mlen; 3519 len -= mlen; 3520 } 3521 3522 /* download disable */ 3523 urtwn_write_1(sc, R92C_MCUFWDL, 3524 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3525 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3526 3527 /* Wait for checksum report. */ 3528 for (ntries = 0; ntries < 1000; ntries++) { 3529 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3530 break; 3531 DELAY(5); 3532 } 3533 if (ntries == 1000) { 3534 aprint_error_dev(sc->sc_dev, 3535 "timeout waiting for checksum report\n"); 3536 error = ETIMEDOUT; 3537 goto fail; 3538 } 3539 3540 /* Wait for firmware readiness. */ 3541 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3542 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3543 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3544 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3545 ISSET(sc->chip, URTWN_CHIP_92EU)) 3546 urtwn_r88e_fw_reset(sc); 3547 for (ntries = 0; ntries < 6000; ntries++) { 3548 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3549 break; 3550 DELAY(5); 3551 } 3552 if (ntries == 6000) { 3553 aprint_error_dev(sc->sc_dev, 3554 "timeout waiting for firmware readiness\n"); 3555 error = ETIMEDOUT; 3556 goto fail; 3557 } 3558 fail: 3559 firmware_free(fw, fwlen); 3560 return error; 3561 } 3562 3563 static __inline int 3564 urtwn_dma_init(struct urtwn_softc *sc) 3565 { 3566 3567 return sc->sc_dma_init(sc); 3568 } 3569 3570 static int 3571 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3572 { 3573 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3574 uint32_t reg; 3575 int error; 3576 3577 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3578 3579 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3580 3581 /* Initialize LLT table. */ 3582 error = urtwn_llt_init(sc); 3583 if (error != 0) 3584 return error; 3585 3586 /* Get Tx queues to USB endpoints mapping. */ 3587 hashq = hasnq = haslq = 0; 3588 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3589 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3590 device_xname(sc->sc_dev), __func__, reg)); 3591 if (MS(reg, R92C_USB_EP_HQ) != 0) 3592 hashq = 1; 3593 if (MS(reg, R92C_USB_EP_NQ) != 0) 3594 hasnq = 1; 3595 if (MS(reg, R92C_USB_EP_LQ) != 0) 3596 haslq = 1; 3597 nqueues = hashq + hasnq + haslq; 3598 if (nqueues == 0) 3599 return EIO; 3600 /* Get the number of pages for each queue. */ 3601 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3602 /* The remaining pages are assigned to the high priority queue. */ 3603 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3604 3605 /* Set number of pages for normal priority queue. */ 3606 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3607 urtwn_write_4(sc, R92C_RQPN, 3608 /* Set number of pages for public queue. */ 3609 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3610 /* Set number of pages for high priority queue. */ 3611 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3612 /* Set number of pages for low priority queue. */ 3613 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3614 /* Load values. */ 3615 R92C_RQPN_LD); 3616 3617 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3618 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3619 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3620 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3621 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3622 3623 /* Set queue to USB pipe mapping. */ 3624 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3625 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3626 if (nqueues == 1) { 3627 if (hashq) { 3628 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3629 } else if (hasnq) { 3630 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3631 } else { 3632 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3633 } 3634 } else if (nqueues == 2) { 3635 /* All 2-endpoints configs have a high priority queue. */ 3636 if (!hashq) { 3637 return EIO; 3638 } 3639 if (hasnq) { 3640 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3641 } else { 3642 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3643 } 3644 } else { 3645 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3646 } 3647 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3648 3649 /* Set Tx/Rx transfer page boundary. */ 3650 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3651 3652 /* Set Tx/Rx transfer page size. */ 3653 urtwn_write_1(sc, R92C_PBP, 3654 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3655 return 0; 3656 } 3657 3658 static int 3659 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3660 { 3661 usb_interface_descriptor_t *id; 3662 uint32_t reg; 3663 int nqueues; 3664 int error; 3665 3666 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3667 3668 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3669 3670 /* Initialize LLT table. */ 3671 error = urtwn_llt_init(sc); 3672 if (error != 0) 3673 return error; 3674 3675 /* Get Tx queues to USB endpoints mapping. */ 3676 id = usbd_get_interface_descriptor(sc->sc_iface); 3677 nqueues = id->bNumEndpoints - 1; 3678 if (nqueues == 0) 3679 return EIO; 3680 3681 /* Set number of pages for normal priority queue. */ 3682 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3683 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3684 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3685 3686 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3687 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3688 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3689 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3690 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3691 3692 /* Set queue to USB pipe mapping. */ 3693 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3694 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3695 if (nqueues == 1) 3696 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3697 else if (nqueues == 2) 3698 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3699 else 3700 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3701 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3702 3703 /* Set Tx/Rx transfer page boundary. */ 3704 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3705 3706 /* Set Tx/Rx transfer page size. */ 3707 urtwn_write_1(sc, R92C_PBP, 3708 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3709 3710 return 0; 3711 } 3712 3713 static void 3714 urtwn_mac_init(struct urtwn_softc *sc) 3715 { 3716 size_t i; 3717 3718 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3719 3720 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3721 3722 /* Write MAC initialization values. */ 3723 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3724 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3725 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3726 rtl8188eu_mac[i].val); 3727 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3728 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3729 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3730 rtl8192eu_mac[i].val); 3731 } else { 3732 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3733 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3734 rtl8192cu_mac[i].val); 3735 } 3736 } 3737 3738 static void 3739 urtwn_bb_init(struct urtwn_softc *sc) 3740 { 3741 const struct rtwn_bb_prog *prog; 3742 uint32_t reg; 3743 uint8_t crystalcap; 3744 size_t i; 3745 3746 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3747 3748 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3749 3750 /* Enable BB and RF. */ 3751 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3752 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3753 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3754 R92C_SYS_FUNC_EN_DIO_RF); 3755 3756 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3757 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3758 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3759 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3760 } 3761 3762 urtwn_write_1(sc, R92C_RF_CTRL, 3763 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3764 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3765 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3766 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3767 3768 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3769 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3770 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3771 urtwn_write_1(sc, 0x15, 0xe9); 3772 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3773 } 3774 3775 /* Select BB programming based on board type. */ 3776 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3777 prog = &rtl8188eu_bb_prog; 3778 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3779 prog = &rtl8192eu_bb_prog; 3780 else if (!(sc->chip & URTWN_CHIP_92C)) { 3781 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3782 prog = &rtl8188ce_bb_prog; 3783 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3784 prog = &rtl8188ru_bb_prog; 3785 } else { 3786 prog = &rtl8188cu_bb_prog; 3787 } 3788 } else { 3789 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3790 prog = &rtl8192ce_bb_prog; 3791 } else { 3792 prog = &rtl8192cu_bb_prog; 3793 } 3794 } 3795 /* Write BB initialization values. */ 3796 for (i = 0; i < prog->count; i++) { 3797 /* additional delay depend on registers */ 3798 switch (prog->regs[i]) { 3799 case 0xfe: 3800 urtwn_delay_ms(sc, 50); 3801 break; 3802 case 0xfd: 3803 urtwn_delay_ms(sc, 5); 3804 break; 3805 case 0xfc: 3806 urtwn_delay_ms(sc, 1); 3807 break; 3808 case 0xfb: 3809 DELAY(50); 3810 break; 3811 case 0xfa: 3812 DELAY(5); 3813 break; 3814 case 0xf9: 3815 DELAY(1); 3816 break; 3817 } 3818 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3819 DELAY(1); 3820 } 3821 3822 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3823 /* 8192C 1T only configuration. */ 3824 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3825 reg = (reg & ~0x00000003) | 0x2; 3826 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3827 3828 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3829 reg = (reg & ~0x00300033) | 0x00200022; 3830 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3831 3832 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3833 reg = (reg & ~0xff000000) | (0x45 << 24); 3834 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3835 3836 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3837 reg = (reg & ~0x000000ff) | 0x23; 3838 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3839 3840 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3841 reg = (reg & ~0x00000030) | (1 << 4); 3842 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3843 3844 reg = urtwn_bb_read(sc, 0xe74); 3845 reg = (reg & ~0x0c000000) | (2 << 26); 3846 urtwn_bb_write(sc, 0xe74, reg); 3847 reg = urtwn_bb_read(sc, 0xe78); 3848 reg = (reg & ~0x0c000000) | (2 << 26); 3849 urtwn_bb_write(sc, 0xe78, reg); 3850 reg = urtwn_bb_read(sc, 0xe7c); 3851 reg = (reg & ~0x0c000000) | (2 << 26); 3852 urtwn_bb_write(sc, 0xe7c, reg); 3853 reg = urtwn_bb_read(sc, 0xe80); 3854 reg = (reg & ~0x0c000000) | (2 << 26); 3855 urtwn_bb_write(sc, 0xe80, reg); 3856 reg = urtwn_bb_read(sc, 0xe88); 3857 reg = (reg & ~0x0c000000) | (2 << 26); 3858 urtwn_bb_write(sc, 0xe88, reg); 3859 } 3860 3861 /* Write AGC values. */ 3862 for (i = 0; i < prog->agccount; i++) { 3863 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3864 DELAY(1); 3865 } 3866 3867 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3868 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3869 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3870 DELAY(1); 3871 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3872 DELAY(1); 3873 } 3874 3875 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3876 crystalcap = sc->r88e_rom[0xb9]; 3877 if (crystalcap == 0x00) 3878 crystalcap = 0x20; 3879 crystalcap &= 0x3f; 3880 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3881 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3882 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3883 crystalcap | crystalcap << 6)); 3884 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3885 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3886 crystalcap = sc->r88e_rom[0xb9]; 3887 if (crystalcap == 0xff) 3888 crystalcap = 0x20; 3889 crystalcap &= 0x3f; 3890 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3891 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3892 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3893 crystalcap | crystalcap << 6)); 3894 } else { 3895 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3896 R92C_HSSI_PARAM2_CCK_HIPWR) { 3897 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3898 } 3899 } 3900 } 3901 3902 static void 3903 urtwn_rf_init(struct urtwn_softc *sc) 3904 { 3905 const struct rtwn_rf_prog *prog; 3906 uint32_t reg, mask, saved; 3907 size_t i, j, idx; 3908 3909 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3910 3911 /* Select RF programming based on board type. */ 3912 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3913 prog = rtl8188eu_rf_prog; 3914 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3915 prog = rtl8192eu_rf_prog; 3916 else if (!(sc->chip & URTWN_CHIP_92C)) { 3917 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3918 prog = rtl8188ce_rf_prog; 3919 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3920 prog = rtl8188ru_rf_prog; 3921 } else { 3922 prog = rtl8188cu_rf_prog; 3923 } 3924 } else { 3925 prog = rtl8192ce_rf_prog; 3926 } 3927 3928 for (i = 0; i < sc->nrxchains; i++) { 3929 /* Save RF_ENV control type. */ 3930 idx = i / 2; 3931 mask = 0xffffU << ((i % 2) * 16); 3932 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3933 3934 /* Set RF_ENV enable. */ 3935 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3936 reg |= 0x100000; 3937 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3938 DELAY(50); 3939 3940 /* Set RF_ENV output high. */ 3941 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3942 reg |= 0x10; 3943 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3944 DELAY(50); 3945 3946 /* Set address and data lengths of RF registers. */ 3947 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3948 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3949 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3950 DELAY(50); 3951 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3952 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3953 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3954 DELAY(50); 3955 3956 /* Write RF initialization values for this chain. */ 3957 for (j = 0; j < prog[i].count; j++) { 3958 if (prog[i].regs[j] >= 0xf9 && 3959 prog[i].regs[j] <= 0xfe) { 3960 /* 3961 * These are fake RF registers offsets that 3962 * indicate a delay is required. 3963 */ 3964 urtwn_delay_ms(sc, 50); 3965 continue; 3966 } 3967 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3968 DELAY(5); 3969 } 3970 3971 /* Restore RF_ENV control type. */ 3972 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3973 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3974 } 3975 3976 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3977 URTWN_CHIP_UMC_A_CUT) { 3978 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3979 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3980 } 3981 3982 /* Cache RF register CHNLBW. */ 3983 for (i = 0; i < 2; i++) { 3984 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3985 } 3986 } 3987 3988 static void 3989 urtwn_cam_init(struct urtwn_softc *sc) 3990 { 3991 uint32_t content, command; 3992 uint8_t idx; 3993 size_t i; 3994 3995 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3996 3997 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3998 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3999 return; 4000 4001 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4002 content = (idx & 3) 4003 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4004 | R92C_CAM_VALID; 4005 4006 command = R92C_CAMCMD_POLLING 4007 | R92C_CAMCMD_WRITE 4008 | R92C_CAM_CTL0(idx); 4009 4010 urtwn_write_4(sc, R92C_CAMWRITE, content); 4011 urtwn_write_4(sc, R92C_CAMCMD, command); 4012 } 4013 4014 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4015 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4016 if (i == 0) { 4017 content = (idx & 3) 4018 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4019 | R92C_CAM_VALID; 4020 } else { 4021 content = 0; 4022 } 4023 4024 command = R92C_CAMCMD_POLLING 4025 | R92C_CAMCMD_WRITE 4026 | R92C_CAM_CTL0(idx) 4027 | i; 4028 4029 urtwn_write_4(sc, R92C_CAMWRITE, content); 4030 urtwn_write_4(sc, R92C_CAMCMD, command); 4031 } 4032 } 4033 4034 /* Invalidate all CAM entries. */ 4035 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4036 } 4037 4038 static void 4039 urtwn_pa_bias_init(struct urtwn_softc *sc) 4040 { 4041 uint8_t reg; 4042 size_t i; 4043 4044 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4045 4046 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4047 4048 for (i = 0; i < sc->nrxchains; i++) { 4049 if (sc->pa_setting & (1U << i)) 4050 continue; 4051 4052 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4053 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4054 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4055 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4056 } 4057 if (!(sc->pa_setting & 0x10)) { 4058 reg = urtwn_read_1(sc, 0x16); 4059 reg = (reg & ~0xf0) | 0x90; 4060 urtwn_write_1(sc, 0x16, reg); 4061 } 4062 } 4063 4064 static void 4065 urtwn_rxfilter_init(struct urtwn_softc *sc) 4066 { 4067 4068 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4069 4070 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4071 4072 /* Initialize Rx filter. */ 4073 /* TODO: use better filter for monitor mode. */ 4074 urtwn_write_4(sc, R92C_RCR, 4075 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4076 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4077 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4078 /* Accept all multicast frames. */ 4079 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4080 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4081 /* Accept all management frames. */ 4082 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4083 /* Reject all control frames. */ 4084 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4085 /* Accept all data frames. */ 4086 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4087 } 4088 4089 static void 4090 urtwn_edca_init(struct urtwn_softc *sc) 4091 { 4092 4093 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4094 4095 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4096 4097 /* set spec SIFS (used in NAV) */ 4098 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4099 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4100 4101 /* set SIFS CCK/OFDM */ 4102 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4103 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4104 4105 /* TXOP */ 4106 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4107 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4108 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4109 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4110 } 4111 4112 static void 4113 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4114 uint16_t power[URTWN_RIDX_COUNT]) 4115 { 4116 uint32_t reg; 4117 4118 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4119 __func__, chain)); 4120 4121 /* Write per-CCK rate Tx power. */ 4122 if (chain == 0) { 4123 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4124 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4125 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4126 4127 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4128 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4129 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4130 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4131 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4132 } else { 4133 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4134 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4135 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4136 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4137 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4138 4139 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4140 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4141 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4142 } 4143 /* Write per-OFDM rate Tx power. */ 4144 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4145 SM(R92C_TXAGC_RATE06, power[ 4]) | 4146 SM(R92C_TXAGC_RATE09, power[ 5]) | 4147 SM(R92C_TXAGC_RATE12, power[ 6]) | 4148 SM(R92C_TXAGC_RATE18, power[ 7])); 4149 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4150 SM(R92C_TXAGC_RATE24, power[ 8]) | 4151 SM(R92C_TXAGC_RATE36, power[ 9]) | 4152 SM(R92C_TXAGC_RATE48, power[10]) | 4153 SM(R92C_TXAGC_RATE54, power[11])); 4154 /* Write per-MCS Tx power. */ 4155 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4156 SM(R92C_TXAGC_MCS00, power[12]) | 4157 SM(R92C_TXAGC_MCS01, power[13]) | 4158 SM(R92C_TXAGC_MCS02, power[14]) | 4159 SM(R92C_TXAGC_MCS03, power[15])); 4160 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4161 SM(R92C_TXAGC_MCS04, power[16]) | 4162 SM(R92C_TXAGC_MCS05, power[17]) | 4163 SM(R92C_TXAGC_MCS06, power[18]) | 4164 SM(R92C_TXAGC_MCS07, power[19])); 4165 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4166 SM(R92C_TXAGC_MCS08, power[20]) | 4167 SM(R92C_TXAGC_MCS09, power[21]) | 4168 SM(R92C_TXAGC_MCS10, power[22]) | 4169 SM(R92C_TXAGC_MCS11, power[23])); 4170 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4171 SM(R92C_TXAGC_MCS12, power[24]) | 4172 SM(R92C_TXAGC_MCS13, power[25]) | 4173 SM(R92C_TXAGC_MCS14, power[26]) | 4174 SM(R92C_TXAGC_MCS15, power[27])); 4175 } 4176 4177 static void 4178 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4179 uint16_t power[URTWN_RIDX_COUNT]) 4180 { 4181 struct r92c_rom *rom = &sc->rom; 4182 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4183 const struct rtwn_txpwr *base; 4184 int ridx, group; 4185 4186 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4187 device_xname(sc->sc_dev), __func__, chain, chan)); 4188 4189 /* Determine channel group. */ 4190 if (chan <= 3) { 4191 group = 0; 4192 } else if (chan <= 9) { 4193 group = 1; 4194 } else { 4195 group = 2; 4196 } 4197 4198 /* Get original Tx power based on board type and RF chain. */ 4199 if (!(sc->chip & URTWN_CHIP_92C)) { 4200 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4201 base = &rtl8188ru_txagc[chain]; 4202 } else { 4203 base = &rtl8192cu_txagc[chain]; 4204 } 4205 } else { 4206 base = &rtl8192cu_txagc[chain]; 4207 } 4208 4209 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4210 if (sc->regulatory == 0) { 4211 for (ridx = 0; ridx <= 3; ridx++) { 4212 power[ridx] = base->pwr[0][ridx]; 4213 } 4214 } 4215 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4216 if (sc->regulatory == 3) { 4217 power[ridx] = base->pwr[0][ridx]; 4218 /* Apply vendor limits. */ 4219 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4220 maxpow = rom->ht40_max_pwr[group]; 4221 } else { 4222 maxpow = rom->ht20_max_pwr[group]; 4223 } 4224 maxpow = (maxpow >> (chain * 4)) & 0xf; 4225 if (power[ridx] > maxpow) { 4226 power[ridx] = maxpow; 4227 } 4228 } else if (sc->regulatory == 1) { 4229 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4230 power[ridx] = base->pwr[group][ridx]; 4231 } 4232 } else if (sc->regulatory != 2) { 4233 power[ridx] = base->pwr[0][ridx]; 4234 } 4235 } 4236 4237 /* Compute per-CCK rate Tx power. */ 4238 cckpow = rom->cck_tx_pwr[chain][group]; 4239 for (ridx = 0; ridx <= 3; ridx++) { 4240 power[ridx] += cckpow; 4241 if (power[ridx] > R92C_MAX_TX_PWR) { 4242 power[ridx] = R92C_MAX_TX_PWR; 4243 } 4244 } 4245 4246 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4247 if (sc->ntxchains > 1) { 4248 /* Apply reduction for 2 spatial streams. */ 4249 diff = rom->ht40_2s_tx_pwr_diff[group]; 4250 diff = (diff >> (chain * 4)) & 0xf; 4251 htpow = (htpow > diff) ? htpow - diff : 0; 4252 } 4253 4254 /* Compute per-OFDM rate Tx power. */ 4255 diff = rom->ofdm_tx_pwr_diff[group]; 4256 diff = (diff >> (chain * 4)) & 0xf; 4257 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4258 for (ridx = 4; ridx <= 11; ridx++) { 4259 power[ridx] += ofdmpow; 4260 if (power[ridx] > R92C_MAX_TX_PWR) { 4261 power[ridx] = R92C_MAX_TX_PWR; 4262 } 4263 } 4264 4265 /* Compute per-MCS Tx power. */ 4266 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4267 diff = rom->ht20_tx_pwr_diff[group]; 4268 diff = (diff >> (chain * 4)) & 0xf; 4269 htpow += diff; /* HT40->HT20 correction. */ 4270 } 4271 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4272 power[ridx] += htpow; 4273 if (power[ridx] > R92C_MAX_TX_PWR) { 4274 power[ridx] = R92C_MAX_TX_PWR; 4275 } 4276 } 4277 #ifdef URTWN_DEBUG 4278 if (urtwn_debug & DBG_RF) { 4279 /* Dump per-rate Tx power values. */ 4280 printf("%s: %s: Tx power for chain %zd:\n", 4281 device_xname(sc->sc_dev), __func__, chain); 4282 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4283 printf("%s: %s: Rate %d = %u\n", 4284 device_xname(sc->sc_dev), __func__, ridx, 4285 power[ridx]); 4286 } 4287 } 4288 #endif 4289 } 4290 4291 void 4292 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4293 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4294 { 4295 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4296 const struct rtwn_r88e_txpwr *base; 4297 int ridx, group; 4298 4299 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4300 device_xname(sc->sc_dev), __func__, chain, chan)); 4301 4302 /* Determine channel group. */ 4303 if (chan <= 2) 4304 group = 0; 4305 else if (chan <= 5) 4306 group = 1; 4307 else if (chan <= 8) 4308 group = 2; 4309 else if (chan <= 11) 4310 group = 3; 4311 else if (chan <= 13) 4312 group = 4; 4313 else 4314 group = 5; 4315 4316 /* Get original Tx power based on board type and RF chain. */ 4317 base = &rtl8188eu_txagc[chain]; 4318 4319 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4320 if (sc->regulatory == 0) { 4321 for (ridx = 0; ridx <= 3; ridx++) 4322 power[ridx] = base->pwr[0][ridx]; 4323 } 4324 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4325 if (sc->regulatory == 3) 4326 power[ridx] = base->pwr[0][ridx]; 4327 else if (sc->regulatory == 1) { 4328 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4329 power[ridx] = base->pwr[group][ridx]; 4330 } else if (sc->regulatory != 2) 4331 power[ridx] = base->pwr[0][ridx]; 4332 } 4333 4334 /* Compute per-CCK rate Tx power. */ 4335 cckpow = sc->cck_tx_pwr[group]; 4336 for (ridx = 0; ridx <= 3; ridx++) { 4337 power[ridx] += cckpow; 4338 if (power[ridx] > R92C_MAX_TX_PWR) 4339 power[ridx] = R92C_MAX_TX_PWR; 4340 } 4341 4342 htpow = sc->ht40_tx_pwr[group]; 4343 4344 /* Compute per-OFDM rate Tx power. */ 4345 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4346 for (ridx = 4; ridx <= 11; ridx++) { 4347 power[ridx] += ofdmpow; 4348 if (power[ridx] > R92C_MAX_TX_PWR) 4349 power[ridx] = R92C_MAX_TX_PWR; 4350 } 4351 4352 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4353 for (ridx = 12; ridx <= 27; ridx++) { 4354 power[ridx] += bw20pow; 4355 if (power[ridx] > R92C_MAX_TX_PWR) 4356 power[ridx] = R92C_MAX_TX_PWR; 4357 } 4358 } 4359 4360 static void 4361 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4362 { 4363 uint16_t power[URTWN_RIDX_COUNT]; 4364 size_t i; 4365 4366 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4367 4368 for (i = 0; i < sc->ntxchains; i++) { 4369 /* Compute per-rate Tx power values. */ 4370 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4371 ISSET(sc->chip, URTWN_CHIP_92EU)) 4372 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4373 else 4374 urtwn_get_txpower(sc, i, chan, ht40m, power); 4375 /* Write per-rate Tx power values to hardware. */ 4376 urtwn_write_txpower(sc, i, power); 4377 } 4378 } 4379 4380 static void 4381 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4382 { 4383 struct ieee80211com *ic = &sc->sc_ic; 4384 u_int chan; 4385 size_t i; 4386 4387 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4388 4389 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4390 __func__, chan)); 4391 4392 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4393 4394 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4395 chan += 2; 4396 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4397 chan -= 2; 4398 } 4399 4400 /* Set Tx power for this new channel. */ 4401 urtwn_set_txpower(sc, chan, ht40m); 4402 4403 for (i = 0; i < sc->nrxchains; i++) { 4404 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4405 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4406 } 4407 4408 if (ht40m) { 4409 /* Is secondary channel below or above primary? */ 4410 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4411 uint32_t reg; 4412 4413 urtwn_write_1(sc, R92C_BWOPMODE, 4414 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4415 4416 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4417 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4418 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4419 4420 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4421 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4422 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4423 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4424 4425 /* Set CCK side band. */ 4426 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4427 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4428 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4429 4430 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4431 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4432 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4433 4434 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4435 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4436 ~R92C_FPGA0_ANAPARAM2_CBW20); 4437 4438 reg = urtwn_bb_read(sc, 0x818); 4439 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4440 urtwn_bb_write(sc, 0x818, reg); 4441 4442 /* Select 40MHz bandwidth. */ 4443 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4444 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4445 } else { 4446 urtwn_write_1(sc, R92C_BWOPMODE, 4447 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4448 4449 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4450 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4451 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4452 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4453 4454 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4455 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4456 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4457 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4458 R92C_FPGA0_ANAPARAM2_CBW20); 4459 } 4460 4461 /* Select 20MHz bandwidth. */ 4462 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4463 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4464 (ISSET(sc->chip, URTWN_CHIP_88E) || 4465 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4466 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4467 } 4468 } 4469 4470 static void 4471 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4472 { 4473 4474 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4475 __func__, inited)); 4476 4477 uint32_t addaBackup[16], iqkBackup[4], piMode; 4478 4479 #ifdef notyet 4480 uint32_t odfm0_agccore_regs[3]; 4481 uint32_t ant_regs[3]; 4482 uint32_t rf_regs[8]; 4483 #endif 4484 uint32_t reg0, reg1, reg2; 4485 int i, attempt; 4486 4487 #ifdef notyet 4488 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4489 R92E_STBC_SETTING + 2)); 4490 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4491 /* Save AGCCORE regs. */ 4492 for (i = 0; i < sc->nrxchains; i++) { 4493 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4494 R92C_OFDM0_AGCCORE1(i)); 4495 } 4496 #endif 4497 /* Save BB regs. */ 4498 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4499 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4500 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4501 4502 /* Save adda regs to be restored when finished. */ 4503 for (i = 0; i < __arraycount(addaReg); i++) 4504 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4505 /* Save mac regs. */ 4506 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4507 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4508 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4509 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4510 4511 #ifdef notyet 4512 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4513 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4514 4515 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4516 for (i = 0; i < sc->nrxchains; i++) 4517 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4518 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4519 #endif 4520 4521 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4522 R92C_HSSI_PARAM1_PI); 4523 if (piMode == 0) { 4524 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4525 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4526 R92C_HSSI_PARAM1_PI); 4527 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4528 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4529 R92C_HSSI_PARAM1_PI); 4530 } 4531 4532 attempt = 1; 4533 4534 next_attempt: 4535 4536 /* Set mac regs for calibration. */ 4537 for (i = 0; i < __arraycount(addaReg); i++) { 4538 urtwn_bb_write(sc, addaReg[i], 4539 addaReg[__arraycount(addaReg) - 1]); 4540 } 4541 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4542 R92C_CCK0_AFESETTING)); 4543 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4544 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4545 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4546 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4547 4548 if (sc->ntxchains > 1) 4549 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4550 4551 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4552 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4553 ~R92C_BCN_CTRL_EN_BCN)); 4554 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4555 ~R92C_BCN_CTRL_EN_BCN)); 4556 4557 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4558 ~R92C_GPIO_MUXCFG_ENBT)); 4559 4560 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4561 4562 if (sc->ntxchains > 1) 4563 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4564 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4565 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4566 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4567 4568 /* Restore BB regs. */ 4569 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4570 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4571 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4572 4573 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4574 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4575 if (sc->nrxchains > 1) 4576 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4577 4578 if (attempt-- > 0) 4579 goto next_attempt; 4580 4581 /* Restore mode. */ 4582 if (piMode == 0) { 4583 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4584 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4585 ~R92C_HSSI_PARAM1_PI); 4586 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4587 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4588 ~R92C_HSSI_PARAM1_PI); 4589 } 4590 4591 #ifdef notyet 4592 for (i = 0; i < sc->nrxchains; i++) { 4593 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4594 odfm0_agccore_regs[i]); 4595 } 4596 #endif 4597 4598 /* Restore adda regs. */ 4599 for (i = 0; i < __arraycount(addaReg); i++) 4600 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4601 /* Restore mac regs. */ 4602 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4603 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4604 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4605 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4606 4607 #ifdef notyet 4608 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4609 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4610 4611 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4612 for (i = 0; i < sc->nrxchains; i++) 4613 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4614 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4615 #endif 4616 } 4617 4618 static void 4619 urtwn_lc_calib(struct urtwn_softc *sc) 4620 { 4621 uint32_t rf_ac[2]; 4622 uint8_t txmode; 4623 size_t i; 4624 4625 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4626 4627 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4628 4629 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4630 if ((txmode & 0x70) != 0) { 4631 /* Disable all continuous Tx. */ 4632 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4633 4634 /* Set RF mode to standby mode. */ 4635 for (i = 0; i < sc->nrxchains; i++) { 4636 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4637 urtwn_rf_write(sc, i, R92C_RF_AC, 4638 RW(rf_ac[i], R92C_RF_AC_MODE, 4639 R92C_RF_AC_MODE_STANDBY)); 4640 } 4641 } else { 4642 /* Block all Tx queues. */ 4643 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4644 } 4645 /* Start calibration. */ 4646 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4647 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4648 4649 /* Give calibration the time to complete. */ 4650 urtwn_delay_ms(sc, 100); 4651 4652 /* Restore configuration. */ 4653 if ((txmode & 0x70) != 0) { 4654 /* Restore Tx mode. */ 4655 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4656 /* Restore RF mode. */ 4657 for (i = 0; i < sc->nrxchains; i++) { 4658 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4659 } 4660 } else { 4661 /* Unblock all Tx queues. */ 4662 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4663 } 4664 } 4665 4666 static void 4667 urtwn_temp_calib(struct urtwn_softc *sc) 4668 { 4669 int temp, t_meter_reg; 4670 4671 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4672 4673 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4674 4675 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4676 t_meter_reg = R92C_RF_T_METER; 4677 else 4678 t_meter_reg = R92E_RF_T_METER; 4679 4680 if (sc->thcal_state == 0) { 4681 /* Start measuring temperature. */ 4682 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4683 device_xname(sc->sc_dev), __func__)); 4684 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4685 sc->thcal_state = 1; 4686 return; 4687 } 4688 sc->thcal_state = 0; 4689 4690 /* Read measured temperature. */ 4691 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4692 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4693 __func__, temp)); 4694 if (temp == 0) /* Read failed, skip. */ 4695 return; 4696 4697 /* 4698 * Redo LC calibration if temperature changed significantly since 4699 * last calibration. 4700 */ 4701 if (sc->thcal_lctemp == 0) { 4702 /* First LC calibration is performed in urtwn_init(). */ 4703 sc->thcal_lctemp = temp; 4704 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4705 DPRINTFN(DBG_RF, 4706 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4707 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4708 temp)); 4709 urtwn_lc_calib(sc); 4710 /* Record temperature of last LC calibration. */ 4711 sc->thcal_lctemp = temp; 4712 } 4713 } 4714 4715 static int 4716 urtwn_init(struct ifnet *ifp) 4717 { 4718 struct urtwn_softc *sc = ifp->if_softc; 4719 struct ieee80211com *ic = &sc->sc_ic; 4720 struct urtwn_rx_data *data; 4721 uint32_t reg; 4722 size_t i; 4723 int error; 4724 4725 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4726 4727 urtwn_stop(ifp, 0); 4728 4729 mutex_enter(&sc->sc_write_mtx); 4730 4731 mutex_enter(&sc->sc_task_mtx); 4732 /* Init host async commands ring. */ 4733 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4734 mutex_exit(&sc->sc_task_mtx); 4735 4736 mutex_enter(&sc->sc_fwcmd_mtx); 4737 /* Init firmware commands ring. */ 4738 sc->fwcur = 0; 4739 mutex_exit(&sc->sc_fwcmd_mtx); 4740 4741 /* Allocate Tx/Rx buffers. */ 4742 error = urtwn_alloc_rx_list(sc); 4743 if (error != 0) { 4744 aprint_error_dev(sc->sc_dev, 4745 "could not allocate Rx buffers\n"); 4746 goto fail; 4747 } 4748 error = urtwn_alloc_tx_list(sc); 4749 if (error != 0) { 4750 aprint_error_dev(sc->sc_dev, 4751 "could not allocate Tx buffers\n"); 4752 goto fail; 4753 } 4754 4755 /* Power on adapter. */ 4756 error = urtwn_power_on(sc); 4757 if (error != 0) 4758 goto fail; 4759 4760 /* Initialize DMA. */ 4761 error = urtwn_dma_init(sc); 4762 if (error != 0) 4763 goto fail; 4764 4765 /* Set info size in Rx descriptors (in 64-bit words). */ 4766 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4767 4768 /* Init interrupts. */ 4769 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4770 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4771 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4772 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4773 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4774 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4775 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4776 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4777 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4778 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4779 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4780 } 4781 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4782 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4783 } else { 4784 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4785 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4786 } 4787 4788 /* Set MAC address. */ 4789 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4790 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4791 4792 /* Set initial network type. */ 4793 reg = urtwn_read_4(sc, R92C_CR); 4794 switch (ic->ic_opmode) { 4795 case IEEE80211_M_STA: 4796 default: 4797 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4798 break; 4799 4800 case IEEE80211_M_IBSS: 4801 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4802 break; 4803 } 4804 urtwn_write_4(sc, R92C_CR, reg); 4805 4806 /* Set response rate */ 4807 reg = urtwn_read_4(sc, R92C_RRSR); 4808 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4809 urtwn_write_4(sc, R92C_RRSR, reg); 4810 4811 /* SIFS (used in NAV) */ 4812 urtwn_write_2(sc, R92C_SPEC_SIFS, 4813 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4814 4815 /* Set short/long retry limits. */ 4816 urtwn_write_2(sc, R92C_RL, 4817 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4818 4819 /* Initialize EDCA parameters. */ 4820 urtwn_edca_init(sc); 4821 4822 /* Setup rate fallback. */ 4823 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4824 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4825 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4826 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4827 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4828 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4829 } 4830 4831 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4832 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4833 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4834 /* Set ACK timeout. */ 4835 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4836 4837 /* Setup USB aggregation. */ 4838 /* Tx */ 4839 reg = urtwn_read_4(sc, R92C_TDECTRL); 4840 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4841 urtwn_write_4(sc, R92C_TDECTRL, reg); 4842 /* Rx */ 4843 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4844 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4845 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4846 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4847 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4848 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4849 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4850 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4851 ISSET(sc->chip, URTWN_CHIP_92EU)) 4852 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4853 else 4854 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4855 4856 /* Initialize beacon parameters. */ 4857 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4858 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4859 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4860 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4861 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4862 4863 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4864 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4865 /* Setup AMPDU aggregation. */ 4866 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4867 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4868 urtwn_write_2(sc, 0x4ca, 0x0708); 4869 4870 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4871 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4872 } 4873 4874 /* Load 8051 microcode. */ 4875 error = urtwn_load_firmware(sc); 4876 if (error != 0) 4877 goto fail; 4878 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4879 4880 /* Initialize MAC/BB/RF blocks. */ 4881 /* 4882 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4883 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4884 * XXX: This setting should be removed from rtl8192cu_mac[]. 4885 */ 4886 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4887 urtwn_rxfilter_init(sc); // reset R92C_RCR 4888 urtwn_bb_init(sc); 4889 urtwn_rf_init(sc); 4890 4891 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4892 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4893 urtwn_write_2(sc, R92C_CR, 4894 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4895 R92C_CR_MACRXEN); 4896 } 4897 4898 /* Turn CCK and OFDM blocks on. */ 4899 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4900 reg |= R92C_RFMOD_CCK_EN; 4901 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4902 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4903 reg |= R92C_RFMOD_OFDM_EN; 4904 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4905 4906 /* Clear per-station keys table. */ 4907 urtwn_cam_init(sc); 4908 4909 /* Enable hardware sequence numbering. */ 4910 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4911 4912 /* Perform LO and IQ calibrations. */ 4913 urtwn_iq_calib(sc, sc->iqk_inited); 4914 sc->iqk_inited = true; 4915 4916 /* Perform LC calibration. */ 4917 urtwn_lc_calib(sc); 4918 4919 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4920 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4921 /* Fix USB interference issue. */ 4922 urtwn_write_1(sc, 0xfe40, 0xe0); 4923 urtwn_write_1(sc, 0xfe41, 0x8d); 4924 urtwn_write_1(sc, 0xfe42, 0x80); 4925 urtwn_write_4(sc, 0x20c, 0xfd0320); 4926 4927 urtwn_pa_bias_init(sc); 4928 } 4929 4930 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4931 !(sc->chip & URTWN_CHIP_92EU)) { 4932 /* 1T1R */ 4933 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4934 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4935 } 4936 4937 /* Initialize GPIO setting. */ 4938 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4939 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4940 4941 /* Fix for lower temperature. */ 4942 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4943 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4944 urtwn_write_1(sc, 0x15, 0xe9); 4945 4946 /* Set default channel. */ 4947 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4948 4949 /* Queue Rx xfers. */ 4950 for (size_t j = 0; j < sc->rx_npipe; j++) { 4951 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4952 data = &sc->rx_data[j][i]; 4953 usbd_setup_xfer(data->xfer, data, data->buf, 4954 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4955 urtwn_rxeof); 4956 error = usbd_transfer(data->xfer); 4957 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4958 error != USBD_IN_PROGRESS)) 4959 goto fail; 4960 } 4961 } 4962 4963 /* We're ready to go. */ 4964 ifp->if_flags &= ~IFF_OACTIVE; 4965 ifp->if_flags |= IFF_RUNNING; 4966 sc->sc_running = true; 4967 4968 mutex_exit(&sc->sc_write_mtx); 4969 4970 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4971 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4972 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4973 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4974 urtwn_wait_async(sc); 4975 4976 return 0; 4977 4978 fail: 4979 mutex_exit(&sc->sc_write_mtx); 4980 4981 urtwn_stop(ifp, 1); 4982 return error; 4983 } 4984 4985 static void 4986 urtwn_stop(struct ifnet *ifp, int disable) 4987 { 4988 struct urtwn_softc *sc = ifp->if_softc; 4989 struct ieee80211com *ic = &sc->sc_ic; 4990 size_t i; 4991 int s; 4992 4993 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4994 4995 s = splusb(); 4996 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4997 urtwn_wait_async(sc); 4998 splx(s); 4999 5000 sc->tx_timer = 0; 5001 ifp->if_timer = 0; 5002 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5003 5004 callout_stop(&sc->sc_scan_to); 5005 callout_stop(&sc->sc_calib_to); 5006 5007 /* Abort Tx. */ 5008 for (i = 0; i < sc->tx_npipe; i++) { 5009 if (sc->tx_pipe[i] != NULL) 5010 usbd_abort_pipe(sc->tx_pipe[i]); 5011 } 5012 5013 /* Stop Rx pipe. */ 5014 for (i = 0; i < sc->rx_npipe; i++) { 5015 if (sc->rx_pipe[i] != NULL) 5016 usbd_abort_pipe(sc->rx_pipe[i]); 5017 } 5018 5019 /* Free Tx/Rx buffers. */ 5020 urtwn_free_tx_list(sc); 5021 urtwn_free_rx_list(sc); 5022 5023 sc->sc_running = false; 5024 if (disable) 5025 urtwn_chip_stop(sc); 5026 } 5027 5028 static int 5029 urtwn_reset(struct ifnet *ifp) 5030 { 5031 struct urtwn_softc *sc = ifp->if_softc; 5032 struct ieee80211com *ic = &sc->sc_ic; 5033 5034 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5035 return ENETRESET; 5036 5037 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5038 5039 return 0; 5040 } 5041 5042 static void 5043 urtwn_chip_stop(struct urtwn_softc *sc) 5044 { 5045 uint32_t reg; 5046 bool disabled = true; 5047 5048 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5049 5050 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5051 ISSET(sc->chip, URTWN_CHIP_92EU)) 5052 return; 5053 5054 mutex_enter(&sc->sc_write_mtx); 5055 5056 /* 5057 * RF Off Sequence 5058 */ 5059 /* Pause MAC TX queue */ 5060 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5061 5062 /* Disable RF */ 5063 urtwn_rf_write(sc, 0, 0, 0); 5064 5065 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5066 5067 /* Reset BB state machine */ 5068 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5069 R92C_SYS_FUNC_EN_USBD | 5070 R92C_SYS_FUNC_EN_USBA | 5071 R92C_SYS_FUNC_EN_BB_GLB_RST); 5072 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5073 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5074 5075 /* 5076 * Reset digital sequence 5077 */ 5078 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5079 /* Reset MCU ready status */ 5080 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5081 /* If firmware in ram code, do reset */ 5082 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5083 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5084 ISSET(sc->chip, URTWN_CHIP_92EU)) 5085 urtwn_r88e_fw_reset(sc); 5086 else 5087 urtwn_fw_reset(sc); 5088 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5089 } 5090 } 5091 5092 /* Reset MAC and Enable 8051 */ 5093 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5094 5095 /* Reset MCU ready status */ 5096 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5097 5098 if (disabled) { 5099 /* Disable MAC clock */ 5100 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5101 /* Disable AFE PLL */ 5102 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5103 /* Gated AFE DIG_CLOCK */ 5104 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5105 /* Isolated digital to PON */ 5106 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5107 } 5108 5109 /* 5110 * Pull GPIO PIN to balance level and LED control 5111 */ 5112 /* 1. Disable GPIO[7:0] */ 5113 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5114 5115 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5116 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5117 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5118 5119 /* Disable GPIO[10:8] */ 5120 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5121 5122 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5123 reg |= (((reg & 0x000f) << 4) | 0x0780); 5124 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5125 5126 /* Disable LED0 & 1 */ 5127 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5128 5129 /* 5130 * Reset digital sequence 5131 */ 5132 if (disabled) { 5133 /* Disable ELDR clock */ 5134 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5135 /* Isolated ELDR to PON */ 5136 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5137 } 5138 5139 /* 5140 * Disable analog sequence 5141 */ 5142 if (disabled) { 5143 /* Disable A15 power */ 5144 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5145 /* Disable digital core power */ 5146 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5147 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5148 ~R92C_LDOV12D_CTRL_LDV12_EN); 5149 } 5150 5151 /* Enter PFM mode */ 5152 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5153 5154 /* Set USB suspend */ 5155 urtwn_write_2(sc, R92C_APS_FSMCO, 5156 R92C_APS_FSMCO_APDM_HOST | 5157 R92C_APS_FSMCO_AFSM_HSUS | 5158 R92C_APS_FSMCO_PFM_ALDN); 5159 5160 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5161 5162 mutex_exit(&sc->sc_write_mtx); 5163 } 5164 5165 static void 5166 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5167 { 5168 if (sc->sc_running == false) 5169 DELAY(ms * 1000); 5170 else 5171 usbd_delay_ms(sc->sc_udev, ms); 5172 } 5173 5174 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5175 5176 #ifdef _MODULE 5177 #include "ioconf.c" 5178 #endif 5179 5180 static int 5181 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5182 { 5183 int error = 0; 5184 5185 switch (cmd) { 5186 case MODULE_CMD_INIT: 5187 #ifdef _MODULE 5188 error = config_init_component(cfdriver_ioconf_urtwn, 5189 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5190 #endif 5191 return error; 5192 case MODULE_CMD_FINI: 5193 #ifdef _MODULE 5194 error = config_fini_component(cfdriver_ioconf_urtwn, 5195 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5196 #endif 5197 return error; 5198 default: 5199 return ENOTTY; 5200 } 5201 } 5202
Indexes created Thu Oct 02 14:10:14 GMT 2025