if_urtwn.c revision 1.71.2.8
1 /* $NetBSD: if_urtwn.c,v 1.71.2.8 2024/06/20 17:55:11 martin Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.71.2.8 2024/06/20 17:55:11 martin Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/ic/rtwnreg.h> 78 #include <dev/ic/rtwn_data.h> 79 #include <dev/usb/if_urtwnreg.h> 80 #include <dev/usb/if_urtwnvar.h> 81 82 /* 83 * The sc_write_mtx locking is to prevent sequences of writes from 84 * being intermingled with each other. I don't know if this is really 85 * needed. I have added it just to be on the safe side. 86 */ 87 88 #ifdef URTWN_DEBUG 89 #define DBG_INIT __BIT(0) 90 #define DBG_FN __BIT(1) 91 #define DBG_TX __BIT(2) 92 #define DBG_RX __BIT(3) 93 #define DBG_STM __BIT(4) 94 #define DBG_RF __BIT(5) 95 #define DBG_REG __BIT(6) 96 #define DBG_ALL 0xffffffffU 97 u_int urtwn_debug = 0; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 195 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 196 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 197 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 198 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 199 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 200 201 /* URTWN_RTL8192EU */ 202 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 203 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 204 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 205 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 206 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 207 }; 208 #undef URTWN_DEV 209 #undef URTWN_RTL8188E_DEV 210 #undef URTWN_RTL8192EU_DEV 211 212 static int urtwn_match(device_t, cfdata_t, void *); 213 static void urtwn_attach(device_t, device_t, void *); 214 static int urtwn_detach(device_t, int); 215 static int urtwn_activate(device_t, enum devact); 216 217 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 218 urtwn_attach, urtwn_detach, urtwn_activate); 219 220 static int urtwn_open_pipes(struct urtwn_softc *); 221 static void urtwn_close_pipes(struct urtwn_softc *); 222 static int urtwn_alloc_rx_list(struct urtwn_softc *); 223 static void urtwn_free_rx_list(struct urtwn_softc *); 224 static int urtwn_alloc_tx_list(struct urtwn_softc *); 225 static void urtwn_free_tx_list(struct urtwn_softc *); 226 static void urtwn_task(void *); 227 static void urtwn_do_async(struct urtwn_softc *, 228 void (*)(struct urtwn_softc *, void *), void *, int); 229 static void urtwn_wait_async(struct urtwn_softc *); 230 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 231 int); 232 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 233 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 234 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 235 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 236 int); 237 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 238 int); 239 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 240 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 241 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 242 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 243 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 244 uint32_t); 245 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 246 uint32_t); 247 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 248 uint32_t); 249 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 250 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 251 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 252 static void urtwn_efuse_read(struct urtwn_softc *); 253 static void urtwn_efuse_switch_power(struct urtwn_softc *); 254 static int urtwn_read_chipid(struct urtwn_softc *); 255 #ifdef URTWN_DEBUG 256 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 257 #endif 258 static void urtwn_read_rom(struct urtwn_softc *); 259 static void urtwn_r88e_read_rom(struct urtwn_softc *); 260 static int urtwn_media_change(struct ifnet *); 261 static int urtwn_ra_init(struct urtwn_softc *); 262 static int urtwn_get_nettype(struct urtwn_softc *); 263 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 264 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 265 static void urtwn_set_led(struct urtwn_softc *, int, int); 266 static void urtwn_calib_to(void *); 267 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 268 static void urtwn_next_scan(void *); 269 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 270 int); 271 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 272 static int urtwn_wme_update(struct ieee80211com *); 273 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 274 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 275 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 276 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 277 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 278 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 279 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 280 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 281 struct ieee80211_node *, struct urtwn_tx_data *); 282 static struct urtwn_tx_data * 283 urtwn_get_tx_data(struct urtwn_softc *, size_t); 284 static void urtwn_start(struct ifnet *); 285 static void urtwn_watchdog(struct ifnet *); 286 static int urtwn_ioctl(struct ifnet *, u_long, void *); 287 static int urtwn_r92c_power_on(struct urtwn_softc *); 288 static int urtwn_r92e_power_on(struct urtwn_softc *); 289 static int urtwn_r88e_power_on(struct urtwn_softc *); 290 static int urtwn_llt_init(struct urtwn_softc *); 291 static void urtwn_fw_reset(struct urtwn_softc *); 292 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 293 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 294 static int urtwn_load_firmware(struct urtwn_softc *); 295 static int urtwn_r92c_dma_init(struct urtwn_softc *); 296 static int urtwn_r88e_dma_init(struct urtwn_softc *); 297 static void urtwn_mac_init(struct urtwn_softc *); 298 static void urtwn_bb_init(struct urtwn_softc *); 299 static void urtwn_rf_init(struct urtwn_softc *); 300 static void urtwn_cam_init(struct urtwn_softc *); 301 static void urtwn_pa_bias_init(struct urtwn_softc *); 302 static void urtwn_rxfilter_init(struct urtwn_softc *); 303 static void urtwn_edca_init(struct urtwn_softc *); 304 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 305 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 306 uint16_t[]); 307 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 308 u_int, uint16_t[]); 309 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 310 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 311 u_int); 312 static void urtwn_iq_calib(struct urtwn_softc *, bool); 313 static void urtwn_lc_calib(struct urtwn_softc *); 314 static void urtwn_temp_calib(struct urtwn_softc *); 315 static int urtwn_init(struct ifnet *); 316 static void urtwn_stop(struct ifnet *, int); 317 static int urtwn_reset(struct ifnet *); 318 static void urtwn_chip_stop(struct urtwn_softc *); 319 static void urtwn_newassoc(struct ieee80211_node *, int); 320 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 321 322 /* Aliases. */ 323 #define urtwn_bb_write urtwn_write_4 324 #define urtwn_bb_read urtwn_read_4 325 326 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 327 328 static const uint16_t addaReg[] = { 329 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 330 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 331 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 332 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 333 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 334 }; 335 336 static int 337 urtwn_match(device_t parent, cfdata_t match, void *aux) 338 { 339 struct usb_attach_arg *uaa = aux; 340 341 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 342 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 343 } 344 345 static void 346 urtwn_attach(device_t parent, device_t self, void *aux) 347 { 348 struct urtwn_softc *sc = device_private(self); 349 struct ieee80211com *ic = &sc->sc_ic; 350 struct ifnet *ifp = &sc->sc_if; 351 struct usb_attach_arg *uaa = aux; 352 char *devinfop; 353 const struct urtwn_dev *dev; 354 usb_device_request_t req; 355 size_t i; 356 int error; 357 358 sc->sc_dev = self; 359 sc->sc_udev = uaa->uaa_device; 360 361 sc->chip = 0; 362 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 363 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 364 SET(sc->chip, URTWN_CHIP_88E); 365 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 366 SET(sc->chip, URTWN_CHIP_92EU); 367 368 aprint_naive("\n"); 369 aprint_normal("\n"); 370 371 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 372 373 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 374 aprint_normal_dev(self, "%s\n", devinfop); 375 usbd_devinfo_free(devinfop); 376 377 req.bmRequestType = UT_WRITE_DEVICE; 378 req.bRequest = UR_SET_FEATURE; 379 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 380 USETW(req.wIndex, UHF_PORT_SUSPEND); 381 USETW(req.wLength, 0); 382 383 (void) usbd_do_request(sc->sc_udev, &req, 0); 384 385 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 386 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 387 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 388 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 389 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 390 391 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 392 393 callout_init(&sc->sc_scan_to, 0); 394 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 395 callout_init(&sc->sc_calib_to, 0); 396 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 397 398 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 399 RND_TYPE_NET, RND_FLAG_DEFAULT); 400 401 error = usbd_set_config_no(sc->sc_udev, 1, 0); 402 if (error != 0) { 403 aprint_error_dev(self, "failed to set configuration" 404 ", err=%s\n", usbd_errstr(error)); 405 goto fail; 406 } 407 408 /* Get the first interface handle. */ 409 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 410 if (error != 0) { 411 aprint_error_dev(self, "could not get interface handle\n"); 412 goto fail; 413 } 414 415 error = urtwn_read_chipid(sc); 416 if (error != 0) { 417 aprint_error_dev(self, "unsupported test chip\n"); 418 goto fail; 419 } 420 421 /* Determine number of Tx/Rx chains. */ 422 if (sc->chip & URTWN_CHIP_92C) { 423 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 424 sc->nrxchains = 2; 425 } else if (sc->chip & URTWN_CHIP_92EU) { 426 sc->ntxchains = 2; 427 sc->nrxchains = 2; 428 } else { 429 sc->ntxchains = 1; 430 sc->nrxchains = 1; 431 } 432 433 if (ISSET(sc->chip, URTWN_CHIP_88E) || 434 ISSET(sc->chip, URTWN_CHIP_92EU)) 435 urtwn_r88e_read_rom(sc); 436 else 437 urtwn_read_rom(sc); 438 439 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 440 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 441 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 442 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 443 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 444 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 445 "8188CUS", sc->ntxchains, sc->nrxchains, 446 ether_sprintf(ic->ic_myaddr)); 447 448 error = urtwn_open_pipes(sc); 449 if (error != 0) { 450 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 451 goto fail; 452 } 453 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 454 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 455 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 456 457 /* 458 * Setup the 802.11 device. 459 */ 460 ic->ic_ifp = ifp; 461 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 462 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 463 ic->ic_state = IEEE80211_S_INIT; 464 465 /* Set device capabilities. */ 466 ic->ic_caps = 467 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 468 IEEE80211_C_IBSS | /* IBSS mode supported */ 469 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 470 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 471 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 472 IEEE80211_C_WME | /* 802.11e */ 473 IEEE80211_C_WPA; /* 802.11i */ 474 475 /* Set supported .11b and .11g rates. */ 476 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 477 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 478 479 /* Set supported .11b and .11g channels (1 through 14). */ 480 for (i = 1; i <= 14; i++) { 481 ic->ic_channels[i].ic_freq = 482 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 483 ic->ic_channels[i].ic_flags = 484 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 485 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 486 } 487 488 ifp->if_softc = sc; 489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 490 ifp->if_init = urtwn_init; 491 ifp->if_ioctl = urtwn_ioctl; 492 ifp->if_start = urtwn_start; 493 ifp->if_watchdog = urtwn_watchdog; 494 IFQ_SET_READY(&ifp->if_snd); 495 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 496 497 if_initialize(ifp); 498 ieee80211_ifattach(ic); 499 500 /* override default methods */ 501 ic->ic_newassoc = urtwn_newassoc; 502 ic->ic_reset = urtwn_reset; 503 ic->ic_wme.wme_update = urtwn_wme_update; 504 505 /* Override state transition machine. */ 506 sc->sc_newstate = ic->ic_newstate; 507 ic->ic_newstate = urtwn_newstate; 508 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 509 510 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 511 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 512 &sc->sc_drvbpf); 513 514 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 515 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 516 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 517 518 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 519 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 520 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 521 522 ifp->if_percpuq = if_percpuq_create(ifp); 523 if_register(ifp); 524 525 ieee80211_announce(ic); 526 527 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 528 529 if (!pmf_device_register(self, NULL, NULL)) 530 aprint_error_dev(self, "couldn't establish power handler\n"); 531 532 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 533 return; 534 535 fail: 536 sc->sc_dying = 1; 537 aprint_error_dev(self, "attach failed\n"); 538 } 539 540 static int 541 urtwn_detach(device_t self, int flags) 542 { 543 struct urtwn_softc *sc = device_private(self); 544 struct ifnet *ifp = &sc->sc_if; 545 int s; 546 547 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 548 549 pmf_device_deregister(self); 550 551 s = splusb(); 552 553 sc->sc_dying = 1; 554 555 callout_halt(&sc->sc_scan_to, NULL); 556 callout_halt(&sc->sc_calib_to, NULL); 557 558 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 559 urtwn_stop(ifp, 0); 560 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 561 NULL); 562 563 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 564 bpf_detach(ifp); 565 ieee80211_ifdetach(&sc->sc_ic); 566 if_detach(ifp); 567 568 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 569 urtwn_close_pipes(sc); 570 } 571 572 splx(s); 573 574 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 575 576 rnd_detach_source(&sc->rnd_source); 577 578 callout_destroy(&sc->sc_scan_to); 579 callout_destroy(&sc->sc_calib_to); 580 581 mutex_destroy(&sc->sc_write_mtx); 582 mutex_destroy(&sc->sc_fwcmd_mtx); 583 mutex_destroy(&sc->sc_tx_mtx); 584 mutex_destroy(&sc->sc_rx_mtx); 585 mutex_destroy(&sc->sc_task_mtx); 586 587 return 0; 588 } 589 590 static int 591 urtwn_activate(device_t self, enum devact act) 592 { 593 struct urtwn_softc *sc = device_private(self); 594 595 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 596 597 switch (act) { 598 case DVACT_DEACTIVATE: 599 if_deactivate(sc->sc_ic.ic_ifp); 600 return 0; 601 default: 602 return EOPNOTSUPP; 603 } 604 } 605 606 static int 607 urtwn_open_pipes(struct urtwn_softc *sc) 608 { 609 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 610 static uint8_t epaddr[R92C_MAX_EPOUT]; 611 static uint8_t rxepaddr[R92C_MAX_EPIN]; 612 usb_interface_descriptor_t *id; 613 usb_endpoint_descriptor_t *ed; 614 size_t i, ntx = 0, nrx = 0; 615 int error; 616 617 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 618 619 /* Determine the number of bulk-out pipes. */ 620 id = usbd_get_interface_descriptor(sc->sc_iface); 621 for (i = 0; i < id->bNumEndpoints; i++) { 622 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 623 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 624 continue; 625 } 626 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 627 if (ntx < sizeof(epaddr)) 628 epaddr[ntx] = ed->bEndpointAddress; 629 ntx++; 630 } 631 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 632 if (nrx < sizeof(rxepaddr)) 633 rxepaddr[nrx] = ed->bEndpointAddress; 634 nrx++; 635 } 636 } 637 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 638 aprint_error_dev(sc->sc_dev, 639 "%zd: invalid number of Rx bulk pipes\n", nrx); 640 return EIO; 641 } 642 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 643 aprint_error_dev(sc->sc_dev, 644 "%zd: invalid number of Tx bulk pipes\n", ntx); 645 return EIO; 646 } 647 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 648 device_xname(sc->sc_dev), __func__, nrx, ntx)); 649 sc->rx_npipe = nrx; 650 sc->tx_npipe = ntx; 651 652 /* Open bulk-in pipe at address 0x81. */ 653 for (i = 0; i < nrx; i++) { 654 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 655 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 656 if (error != 0) { 657 aprint_error_dev(sc->sc_dev, 658 "could not open Rx bulk pipe 0x%02x: %d\n", 659 rxepaddr[i], error); 660 goto fail; 661 } 662 } 663 664 /* Open bulk-out pipes (up to 3). */ 665 for (i = 0; i < ntx; i++) { 666 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 667 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 668 if (error != 0) { 669 aprint_error_dev(sc->sc_dev, 670 "could not open Tx bulk pipe 0x%02x: %d\n", 671 epaddr[i], error); 672 goto fail; 673 } 674 } 675 676 /* Map 802.11 access categories to USB pipes. */ 677 sc->ac2idx[WME_AC_BK] = 678 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 679 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 680 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 681 682 fail: 683 if (error != 0) 684 urtwn_close_pipes(sc); 685 return error; 686 } 687 688 static void 689 urtwn_close_pipes(struct urtwn_softc *sc) 690 { 691 struct usbd_pipe *pipe; 692 size_t i; 693 694 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 695 696 /* Close Rx pipes. */ 697 CTASSERT(sizeof(pipe) == sizeof(void *)); 698 for (i = 0; i < sc->rx_npipe; i++) { 699 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 700 if (pipe != NULL) { 701 usbd_close_pipe(pipe); 702 } 703 } 704 705 /* Close Tx pipes. */ 706 for (i = 0; i < sc->tx_npipe; i++) { 707 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 708 if (pipe != NULL) { 709 usbd_close_pipe(pipe); 710 } 711 } 712 } 713 714 static int 715 urtwn_alloc_rx_list(struct urtwn_softc *sc) 716 { 717 struct urtwn_rx_data *data; 718 size_t i; 719 int error = 0; 720 721 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 722 723 for (size_t j = 0; j < sc->rx_npipe; j++) { 724 TAILQ_INIT(&sc->rx_free_list[j]); 725 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 726 data = &sc->rx_data[j][i]; 727 728 data->sc = sc; /* Backpointer for callbacks. */ 729 730 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 731 0, 0, &data->xfer); 732 if (error) { 733 aprint_error_dev(sc->sc_dev, 734 "could not allocate xfer\n"); 735 break; 736 } 737 738 data->buf = usbd_get_buffer(data->xfer); 739 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 740 } 741 } 742 if (error != 0) 743 urtwn_free_rx_list(sc); 744 return error; 745 } 746 747 static void 748 urtwn_free_rx_list(struct urtwn_softc *sc) 749 { 750 struct usbd_xfer *xfer; 751 size_t i; 752 753 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 754 755 /* NB: Caller must abort pipe first. */ 756 for (size_t j = 0; j < sc->rx_npipe; j++) { 757 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 758 CTASSERT(sizeof(xfer) == sizeof(void *)); 759 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 760 if (xfer != NULL) 761 usbd_destroy_xfer(xfer); 762 } 763 } 764 } 765 766 static int 767 urtwn_alloc_tx_list(struct urtwn_softc *sc) 768 { 769 struct urtwn_tx_data *data; 770 size_t i; 771 int error = 0; 772 773 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 774 775 mutex_enter(&sc->sc_tx_mtx); 776 for (size_t j = 0; j < sc->tx_npipe; j++) { 777 TAILQ_INIT(&sc->tx_free_list[j]); 778 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 779 data = &sc->tx_data[j][i]; 780 781 data->sc = sc; /* Backpointer for callbacks. */ 782 data->pidx = j; 783 784 error = usbd_create_xfer(sc->tx_pipe[j], 785 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 786 &data->xfer); 787 if (error) { 788 aprint_error_dev(sc->sc_dev, 789 "could not allocate xfer\n"); 790 goto fail; 791 } 792 793 data->buf = usbd_get_buffer(data->xfer); 794 795 /* Append this Tx buffer to our free list. */ 796 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 797 } 798 } 799 mutex_exit(&sc->sc_tx_mtx); 800 return 0; 801 802 fail: 803 urtwn_free_tx_list(sc); 804 mutex_exit(&sc->sc_tx_mtx); 805 return error; 806 } 807 808 static void 809 urtwn_free_tx_list(struct urtwn_softc *sc) 810 { 811 struct usbd_xfer *xfer; 812 size_t i; 813 814 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 815 816 /* NB: Caller must abort pipe first. */ 817 for (size_t j = 0; j < sc->tx_npipe; j++) { 818 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 819 CTASSERT(sizeof(xfer) == sizeof(void *)); 820 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 821 if (xfer != NULL) 822 usbd_destroy_xfer(xfer); 823 } 824 } 825 } 826 827 static int 828 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 829 struct ieee80211_node *ni) 830 { 831 struct urtwn_tx_data *data = 832 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 833 return urtwn_tx(sc, m, ni, data); 834 } 835 836 static void 837 urtwn_cmdq_invariants(struct urtwn_softc *sc) 838 { 839 struct urtwn_host_cmd_ring *const ring __diagused = &sc->cmdq; 840 841 KASSERT(mutex_owned(&sc->sc_task_mtx)); 842 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 843 "%s: cur=%d next=%d queued=%d", 844 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 845 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 846 "%s: cur=%d next=%d queued=%d", 847 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 848 KASSERTMSG((ring->queued >= 0 && 849 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 850 "%s: %d commands queued", 851 device_xname(sc->sc_dev), ring->queued); 852 } 853 854 static void 855 urtwn_task(void *arg) 856 { 857 struct urtwn_softc *sc = arg; 858 struct ieee80211com *ic = &sc->sc_ic; 859 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 860 struct urtwn_host_cmd *cmd; 861 int s; 862 863 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 864 if (ic->ic_state == IEEE80211_S_RUN && 865 (ic->ic_opmode == IEEE80211_M_HOSTAP || 866 ic->ic_opmode == IEEE80211_M_IBSS)) { 867 868 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 869 &sc->sc_bo); 870 if (m == NULL) { 871 aprint_error_dev(sc->sc_dev, 872 "could not allocate beacon"); 873 } 874 875 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 876 m_freem(m); 877 aprint_error_dev(sc->sc_dev, "could not send beacon"); 878 } 879 880 /* beacon is no longer needed */ 881 m_freem(m); 882 } 883 884 /* Process host commands. */ 885 s = splusb(); 886 mutex_spin_enter(&sc->sc_task_mtx); 887 urtwn_cmdq_invariants(sc); 888 while (ring->next != ring->cur) { 889 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 890 device_xname(sc->sc_dev), 891 ring->cur, ring->next, ring->queued); 892 cmd = &ring->cmd[ring->next]; 893 mutex_spin_exit(&sc->sc_task_mtx); 894 splx(s); 895 /* Invoke callback with kernel lock held. */ 896 cmd->cb(sc, cmd->data); 897 s = splusb(); 898 mutex_spin_enter(&sc->sc_task_mtx); 899 urtwn_cmdq_invariants(sc); 900 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 901 device_xname(sc->sc_dev), 902 ring->cur, ring->next, ring->queued); 903 ring->queued--; 904 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 905 } 906 mutex_spin_exit(&sc->sc_task_mtx); 907 wakeup(&sc->cmdq); 908 splx(s); 909 } 910 911 static void 912 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 913 void *arg, int len) 914 { 915 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 916 struct urtwn_host_cmd *cmd; 917 bool schedtask = false; 918 int s; 919 920 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 921 device_xname(sc->sc_dev), __func__, cb, arg, len)); 922 923 s = splusb(); 924 mutex_spin_enter(&sc->sc_task_mtx); 925 urtwn_cmdq_invariants(sc); 926 cmd = &ring->cmd[ring->cur]; 927 cmd->cb = cb; 928 KASSERT(len <= sizeof(cmd->data)); 929 memcpy(cmd->data, arg, len); 930 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 931 932 /* 933 * Schedule a task to process the command if need be. 934 */ 935 if (!sc->sc_dying) { 936 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 937 device_printf(sc->sc_dev, "command queue overflow\n"); 938 else if (ring->queued++ == 0) 939 schedtask = true; 940 } 941 mutex_spin_exit(&sc->sc_task_mtx); 942 splx(s); 943 944 if (schedtask) 945 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 946 } 947 948 static void 949 urtwn_wait_async(struct urtwn_softc *sc) 950 { 951 952 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 953 954 /* Wait for all queued asynchronous commands to complete. */ 955 while (sc->cmdq.queued > 0) 956 tsleep(&sc->cmdq, 0, "endtask", 0); 957 } 958 959 static int 960 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 961 int len) 962 { 963 usb_device_request_t req; 964 usbd_status error; 965 966 KASSERT(mutex_owned(&sc->sc_write_mtx)); 967 968 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 969 req.bRequest = R92C_REQ_REGS; 970 USETW(req.wValue, addr); 971 USETW(req.wIndex, 0); 972 USETW(req.wLength, len); 973 error = usbd_do_request(sc->sc_udev, &req, buf); 974 if (error != USBD_NORMAL_COMPLETION) { 975 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 976 device_xname(sc->sc_dev), __func__, error, addr, len)); 977 } 978 return error; 979 } 980 981 static void 982 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 983 { 984 985 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 986 device_xname(sc->sc_dev), __func__, addr, val)); 987 988 urtwn_write_region_1(sc, addr, &val, 1); 989 } 990 991 static void 992 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 993 { 994 uint8_t buf[2]; 995 996 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 997 device_xname(sc->sc_dev), __func__, addr, val)); 998 999 buf[0] = (uint8_t)val; 1000 buf[1] = (uint8_t)(val >> 8); 1001 urtwn_write_region_1(sc, addr, buf, 2); 1002 } 1003 1004 static void 1005 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1006 { 1007 uint8_t buf[4]; 1008 1009 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1010 device_xname(sc->sc_dev), __func__, addr, val)); 1011 1012 buf[0] = (uint8_t)val; 1013 buf[1] = (uint8_t)(val >> 8); 1014 buf[2] = (uint8_t)(val >> 16); 1015 buf[3] = (uint8_t)(val >> 24); 1016 urtwn_write_region_1(sc, addr, buf, 4); 1017 } 1018 1019 static int 1020 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1021 { 1022 1023 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 1024 device_xname(sc->sc_dev), __func__, addr, len)); 1025 1026 return urtwn_write_region_1(sc, addr, buf, len); 1027 } 1028 1029 static int 1030 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1031 int len) 1032 { 1033 usb_device_request_t req; 1034 usbd_status error; 1035 1036 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1037 req.bRequest = R92C_REQ_REGS; 1038 USETW(req.wValue, addr); 1039 USETW(req.wIndex, 0); 1040 USETW(req.wLength, len); 1041 error = usbd_do_request(sc->sc_udev, &req, buf); 1042 if (error != USBD_NORMAL_COMPLETION) { 1043 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1044 device_xname(sc->sc_dev), __func__, error, addr, len)); 1045 } 1046 return error; 1047 } 1048 1049 static uint8_t 1050 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1051 { 1052 uint8_t val; 1053 1054 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1055 return 0xff; 1056 1057 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1058 device_xname(sc->sc_dev), __func__, addr, val)); 1059 return val; 1060 } 1061 1062 static uint16_t 1063 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1064 { 1065 uint8_t buf[2]; 1066 uint16_t val; 1067 1068 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1069 return 0xffff; 1070 1071 val = LE_READ_2(&buf[0]); 1072 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1073 device_xname(sc->sc_dev), __func__, addr, val)); 1074 return val; 1075 } 1076 1077 static uint32_t 1078 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1079 { 1080 uint8_t buf[4]; 1081 uint32_t val; 1082 1083 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1084 return 0xffffffff; 1085 1086 val = LE_READ_4(&buf[0]); 1087 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1088 device_xname(sc->sc_dev), __func__, addr, val)); 1089 return val; 1090 } 1091 1092 static int 1093 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1094 { 1095 struct r92c_fw_cmd cmd; 1096 uint8_t *cp; 1097 int fwcur; 1098 int ntries; 1099 1100 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1101 device_xname(sc->sc_dev), __func__, id, buf, len)); 1102 1103 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1104 1105 mutex_enter(&sc->sc_fwcmd_mtx); 1106 fwcur = sc->fwcur; 1107 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1108 mutex_exit(&sc->sc_fwcmd_mtx); 1109 1110 /* Wait for current FW box to be empty. */ 1111 for (ntries = 0; ntries < 100; ntries++) { 1112 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1113 break; 1114 DELAY(2000); 1115 } 1116 if (ntries == 100) { 1117 aprint_error_dev(sc->sc_dev, 1118 "could not send firmware command %d\n", id); 1119 return ETIMEDOUT; 1120 } 1121 1122 memset(&cmd, 0, sizeof(cmd)); 1123 KASSERT(len <= sizeof(cmd.msg)); 1124 memcpy(cmd.msg, buf, len); 1125 1126 /* Write the first word last since that will trigger the FW. */ 1127 cp = (uint8_t *)&cmd; 1128 cmd.id = id; 1129 if (len >= 4) { 1130 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1131 cmd.id |= R92C_CMD_FLAG_EXT; 1132 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1133 &cp[1], 2); 1134 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1135 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1136 ((uint32_t)cp[5] << 24)); 1137 } else { 1138 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1139 &cp[4], 2); 1140 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1141 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1142 ((uint32_t)cp[3] << 24)); 1143 } 1144 } else { 1145 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1146 } 1147 1148 return 0; 1149 } 1150 1151 static __inline void 1152 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1153 { 1154 1155 sc->sc_rf_write(sc, chain, addr, val); 1156 } 1157 1158 static void 1159 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1160 uint32_t val) 1161 { 1162 1163 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1164 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1165 } 1166 1167 static void 1168 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1169 uint32_t val) 1170 { 1171 1172 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1173 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1174 } 1175 1176 static void 1177 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1178 uint32_t val) 1179 { 1180 1181 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1182 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1183 } 1184 1185 static uint32_t 1186 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1187 { 1188 uint32_t reg[R92C_MAX_CHAINS], val; 1189 1190 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1191 if (chain != 0) { 1192 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1193 } 1194 1195 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1196 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1197 DELAY(1000); 1198 1199 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1200 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1201 R92C_HSSI_PARAM2_READ_EDGE); 1202 DELAY(1000); 1203 1204 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1205 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1206 DELAY(1000); 1207 1208 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1209 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1210 } else { 1211 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1212 } 1213 return MS(val, R92C_LSSI_READBACK_DATA); 1214 } 1215 1216 static int 1217 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1218 { 1219 int ntries; 1220 1221 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1222 1223 urtwn_write_4(sc, R92C_LLT_INIT, 1224 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1225 SM(R92C_LLT_INIT_ADDR, addr) | 1226 SM(R92C_LLT_INIT_DATA, data)); 1227 /* Wait for write operation to complete. */ 1228 for (ntries = 0; ntries < 20; ntries++) { 1229 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1230 R92C_LLT_INIT_OP_NO_ACTIVE) { 1231 /* Done */ 1232 return 0; 1233 } 1234 DELAY(5); 1235 } 1236 return ETIMEDOUT; 1237 } 1238 1239 static uint8_t 1240 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1241 { 1242 uint32_t reg; 1243 int ntries; 1244 1245 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1246 1247 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1248 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1249 reg &= ~R92C_EFUSE_CTRL_VALID; 1250 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1251 1252 /* Wait for read operation to complete. */ 1253 for (ntries = 0; ntries < 100; ntries++) { 1254 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1255 if (reg & R92C_EFUSE_CTRL_VALID) { 1256 /* Done */ 1257 return MS(reg, R92C_EFUSE_CTRL_DATA); 1258 } 1259 DELAY(5); 1260 } 1261 aprint_error_dev(sc->sc_dev, 1262 "could not read efuse byte at address 0x%04x\n", addr); 1263 return 0xff; 1264 } 1265 1266 static void 1267 urtwn_efuse_read(struct urtwn_softc *sc) 1268 { 1269 uint8_t *rom = (uint8_t *)&sc->rom; 1270 uint32_t reg; 1271 uint16_t addr = 0; 1272 uint8_t off, msk; 1273 size_t i; 1274 1275 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1276 1277 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1278 1279 urtwn_efuse_switch_power(sc); 1280 1281 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1282 while (addr < 512) { 1283 reg = urtwn_efuse_read_1(sc, addr); 1284 if (reg == 0xff) 1285 break; 1286 addr++; 1287 off = reg >> 4; 1288 msk = reg & 0xf; 1289 for (i = 0; i < 4; i++) { 1290 if (msk & (1U << i)) 1291 continue; 1292 1293 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1294 addr++; 1295 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1296 addr++; 1297 } 1298 } 1299 #ifdef URTWN_DEBUG 1300 if (urtwn_debug & DBG_INIT) { 1301 /* Dump ROM content. */ 1302 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1303 for (i = 0; i < (int)sizeof(sc->rom); i++) 1304 printf(":%02x", rom[i]); 1305 printf("\n"); 1306 } 1307 #endif 1308 } 1309 1310 static void 1311 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1312 { 1313 uint32_t reg; 1314 1315 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1316 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1317 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1318 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1319 } 1320 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1321 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1322 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1323 reg | R92C_SYS_FUNC_EN_ELDR); 1324 } 1325 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1326 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1327 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1328 urtwn_write_2(sc, R92C_SYS_CLKR, 1329 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1330 } 1331 } 1332 1333 static int 1334 urtwn_read_chipid(struct urtwn_softc *sc) 1335 { 1336 uint32_t reg; 1337 1338 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1339 1340 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1341 ISSET(sc->chip, URTWN_CHIP_92EU)) 1342 return 0; 1343 1344 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1345 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1346 /* test chip, not supported */ 1347 return EIO; 1348 } 1349 if (reg & R92C_SYS_CFG_TYPE_92C) { 1350 sc->chip |= URTWN_CHIP_92C; 1351 /* Check if it is a castrated 8192C. */ 1352 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1353 R92C_HPON_FSM_CHIP_BONDING_ID) == 1354 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1355 sc->chip |= URTWN_CHIP_92C_1T2R; 1356 } 1357 } 1358 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1359 sc->chip |= URTWN_CHIP_UMC; 1360 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1361 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1362 } 1363 } 1364 return 0; 1365 } 1366 1367 #ifdef URTWN_DEBUG 1368 static void 1369 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1370 { 1371 1372 aprint_normal_dev(sc->sc_dev, 1373 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1374 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1375 1376 aprint_normal_dev(sc->sc_dev, 1377 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1378 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1379 1380 aprint_normal_dev(sc->sc_dev, 1381 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1382 rp->macaddr[0], rp->macaddr[1], 1383 rp->macaddr[2], rp->macaddr[3], 1384 rp->macaddr[4], rp->macaddr[5]); 1385 1386 aprint_normal_dev(sc->sc_dev, 1387 "string %s, subcustomer_id 0x%x\n", 1388 rp->string, rp->subcustomer_id); 1389 1390 aprint_normal_dev(sc->sc_dev, 1391 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1392 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1393 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1394 1395 aprint_normal_dev(sc->sc_dev, 1396 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1397 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1398 rp->ht40_1s_tx_pwr[0][2], 1399 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1400 rp->ht40_1s_tx_pwr[1][2]); 1401 1402 aprint_normal_dev(sc->sc_dev, 1403 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1404 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1405 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1406 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1407 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1408 1409 aprint_normal_dev(sc->sc_dev, 1410 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1411 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1412 rp->ht20_tx_pwr_diff[2] & 0xf, 1413 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1414 rp->ht20_tx_pwr_diff[2] >> 4); 1415 1416 aprint_normal_dev(sc->sc_dev, 1417 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1418 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1419 rp->ofdm_tx_pwr_diff[2] & 0xf, 1420 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1421 rp->ofdm_tx_pwr_diff[2] >> 4); 1422 1423 aprint_normal_dev(sc->sc_dev, 1424 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1425 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1426 rp->ht40_max_pwr[2] & 0xf, 1427 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1428 rp->ht40_max_pwr[2] >> 4); 1429 1430 aprint_normal_dev(sc->sc_dev, 1431 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1432 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1433 rp->ht20_max_pwr[2] & 0xf, 1434 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1435 rp->ht20_max_pwr[2] >> 4); 1436 1437 aprint_normal_dev(sc->sc_dev, 1438 "xtal_calib %d, tssi %d %d, thermal %d\n", 1439 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1440 1441 aprint_normal_dev(sc->sc_dev, 1442 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1443 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1444 1445 aprint_normal_dev(sc->sc_dev, 1446 "channnel_plan %d, version %d customer_id 0x%x\n", 1447 rp->channel_plan, rp->version, rp->curstomer_id); 1448 } 1449 #endif 1450 1451 static void 1452 urtwn_read_rom(struct urtwn_softc *sc) 1453 { 1454 struct ieee80211com *ic = &sc->sc_ic; 1455 struct r92c_rom *rom = &sc->rom; 1456 1457 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1458 1459 mutex_enter(&sc->sc_write_mtx); 1460 1461 /* Read full ROM image. */ 1462 urtwn_efuse_read(sc); 1463 #ifdef URTWN_DEBUG 1464 if (urtwn_debug & DBG_REG) 1465 urtwn_dump_rom(sc, rom); 1466 #endif 1467 1468 /* XXX Weird but this is what the vendor driver does. */ 1469 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1470 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1471 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1472 1473 DPRINTFN(DBG_INIT, 1474 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1475 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1476 sc->board_type, sc->regulatory)); 1477 1478 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1479 1480 sc->sc_rf_write = urtwn_r92c_rf_write; 1481 sc->sc_power_on = urtwn_r92c_power_on; 1482 sc->sc_dma_init = urtwn_r92c_dma_init; 1483 1484 mutex_exit(&sc->sc_write_mtx); 1485 } 1486 1487 static void 1488 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1489 { 1490 struct ieee80211com *ic = &sc->sc_ic; 1491 uint8_t *rom = sc->r88e_rom; 1492 uint32_t reg; 1493 uint16_t addr = 0; 1494 uint8_t off, msk, tmp; 1495 int i; 1496 1497 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1498 1499 mutex_enter(&sc->sc_write_mtx); 1500 1501 off = 0; 1502 urtwn_efuse_switch_power(sc); 1503 1504 /* Read full ROM image. */ 1505 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1506 while (addr < 4096) { 1507 reg = urtwn_efuse_read_1(sc, addr); 1508 if (reg == 0xff) 1509 break; 1510 addr++; 1511 if ((reg & 0x1f) == 0x0f) { 1512 tmp = (reg & 0xe0) >> 5; 1513 reg = urtwn_efuse_read_1(sc, addr); 1514 if ((reg & 0x0f) != 0x0f) 1515 off = ((reg & 0xf0) >> 1) | tmp; 1516 addr++; 1517 } else 1518 off = reg >> 4; 1519 msk = reg & 0xf; 1520 for (i = 0; i < 4; i++) { 1521 if (msk & (1 << i)) 1522 continue; 1523 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1524 addr++; 1525 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1526 addr++; 1527 } 1528 } 1529 #ifdef URTWN_DEBUG 1530 if (urtwn_debug & DBG_REG) { 1531 } 1532 #endif 1533 1534 addr = 0x10; 1535 for (i = 0; i < 6; i++) 1536 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1537 for (i = 0; i < 5; i++) 1538 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1539 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1540 if (sc->bw20_tx_pwr_diff & 0x08) 1541 sc->bw20_tx_pwr_diff |= 0xf0; 1542 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1543 if (sc->ofdm_tx_pwr_diff & 0x08) 1544 sc->ofdm_tx_pwr_diff |= 0xf0; 1545 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1546 1547 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1548 1549 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1550 sc->sc_power_on = urtwn_r92e_power_on; 1551 sc->sc_rf_write = urtwn_r92e_rf_write; 1552 } else { 1553 sc->sc_power_on = urtwn_r88e_power_on; 1554 sc->sc_rf_write = urtwn_r88e_rf_write; 1555 } 1556 sc->sc_dma_init = urtwn_r88e_dma_init; 1557 1558 mutex_exit(&sc->sc_write_mtx); 1559 } 1560 1561 static int 1562 urtwn_media_change(struct ifnet *ifp) 1563 { 1564 #ifdef URTWN_DEBUG 1565 struct urtwn_softc *sc = ifp->if_softc; 1566 #endif 1567 int error; 1568 1569 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1570 1571 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1572 return error; 1573 1574 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1575 (IFF_UP | IFF_RUNNING)) { 1576 urtwn_init(ifp); 1577 } 1578 return 0; 1579 } 1580 1581 /* 1582 * Initialize rate adaptation in firmware. 1583 */ 1584 static int 1585 urtwn_ra_init(struct urtwn_softc *sc) 1586 { 1587 static const uint8_t map[] = { 1588 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1589 }; 1590 struct ieee80211com *ic = &sc->sc_ic; 1591 struct ieee80211_node *ni = ic->ic_bss; 1592 struct ieee80211_rateset *rs = &ni->ni_rates; 1593 struct r92c_fw_cmd_macid_cfg cmd; 1594 uint32_t rates, basicrates; 1595 uint32_t rrsr_mask, rrsr_rate; 1596 uint8_t mode; 1597 size_t maxrate, maxbasicrate, i, j; 1598 int error; 1599 1600 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1601 1602 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1603 1604 /* Get normal and basic rates mask. */ 1605 rates = basicrates = 1; 1606 maxrate = maxbasicrate = 0; 1607 for (i = 0; i < rs->rs_nrates; i++) { 1608 /* Convert 802.11 rate to HW rate index. */ 1609 for (j = 0; j < __arraycount(map); j++) { 1610 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1611 break; 1612 } 1613 } 1614 if (j == __arraycount(map)) { 1615 /* Unknown rate, skip. */ 1616 continue; 1617 } 1618 1619 rates |= 1U << j; 1620 if (j > maxrate) { 1621 maxrate = j; 1622 } 1623 1624 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1625 basicrates |= 1U << j; 1626 if (j > maxbasicrate) { 1627 maxbasicrate = j; 1628 } 1629 } 1630 } 1631 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1632 mode = R92C_RAID_11B; 1633 } else { 1634 mode = R92C_RAID_11BG; 1635 } 1636 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1637 "maxrate=%zx, maxbasicrate=%zx\n", 1638 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1639 maxrate, maxbasicrate)); 1640 1641 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1642 maxbasicrate |= R92C_RATE_SHORTGI; 1643 maxrate |= R92C_RATE_SHORTGI; 1644 } 1645 1646 /* Set rates mask for group addressed frames. */ 1647 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1648 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1649 cmd.macid |= RTWN_MACID_SHORTGI; 1650 cmd.mask = htole32((mode << 28) | basicrates); 1651 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1652 if (error != 0) { 1653 aprint_error_dev(sc->sc_dev, 1654 "could not add broadcast station\n"); 1655 return error; 1656 } 1657 /* Set initial MRR rate. */ 1658 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1659 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1660 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1661 1662 /* Set rates mask for unicast frames. */ 1663 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1664 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1665 cmd.macid |= RTWN_MACID_SHORTGI; 1666 cmd.mask = htole32((mode << 28) | rates); 1667 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1668 if (error != 0) { 1669 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1670 return error; 1671 } 1672 /* Set initial MRR rate. */ 1673 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1674 __func__, maxrate)); 1675 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1676 1677 rrsr_rate = ic->ic_fixed_rate; 1678 if (rrsr_rate == -1) 1679 rrsr_rate = 11; 1680 1681 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1682 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1683 1684 /* Indicate highest supported rate. */ 1685 ni->ni_txrate = rs->rs_nrates - 1; 1686 1687 return 0; 1688 } 1689 1690 static int 1691 urtwn_get_nettype(struct urtwn_softc *sc) 1692 { 1693 struct ieee80211com *ic = &sc->sc_ic; 1694 int type; 1695 1696 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1697 1698 switch (ic->ic_opmode) { 1699 case IEEE80211_M_STA: 1700 type = R92C_CR_NETTYPE_INFRA; 1701 break; 1702 1703 case IEEE80211_M_IBSS: 1704 type = R92C_CR_NETTYPE_ADHOC; 1705 break; 1706 1707 default: 1708 type = R92C_CR_NETTYPE_NOLINK; 1709 break; 1710 } 1711 1712 return type; 1713 } 1714 1715 static void 1716 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1717 { 1718 uint8_t reg; 1719 1720 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1721 __func__, type)); 1722 1723 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1724 1725 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1726 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1727 } 1728 1729 static void 1730 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1731 { 1732 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1733 uint64_t tsf; 1734 1735 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1736 1737 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1738 1739 /* Enable TSF synchronization. */ 1740 urtwn_write_1(sc, R92C_BCN_CTRL, 1741 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1742 1743 /* Correct TSF */ 1744 urtwn_write_1(sc, R92C_BCN_CTRL, 1745 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1746 1747 /* Set initial TSF. */ 1748 tsf = ni->ni_tstamp.tsf; 1749 tsf = le64toh(tsf); 1750 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1751 tsf -= IEEE80211_DUR_TU; 1752 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1753 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1754 1755 urtwn_write_1(sc, R92C_BCN_CTRL, 1756 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1757 } 1758 1759 static void 1760 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1761 { 1762 uint8_t reg; 1763 1764 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1765 __func__, led, on)); 1766 1767 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1768 1769 if (led == URTWN_LED_LINK) { 1770 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1771 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1772 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1773 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1774 (R92C_LEDCFG0_DIS << 1)); 1775 if (on) { 1776 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1777 R92E_LEDSON; 1778 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1779 } 1780 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1781 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1782 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1783 if (!on) { 1784 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1785 urtwn_write_1(sc, R92C_LEDCFG2, 1786 reg | R92C_LEDCFG0_DIS); 1787 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1788 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1789 reg & 0xfe); 1790 } 1791 } else { 1792 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1793 if (!on) { 1794 reg |= R92C_LEDCFG0_DIS; 1795 } 1796 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1797 } 1798 sc->ledlink = on; /* Save LED state. */ 1799 } 1800 } 1801 1802 static void 1803 urtwn_calib_to(void *arg) 1804 { 1805 struct urtwn_softc *sc = arg; 1806 1807 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1808 1809 if (sc->sc_dying) 1810 return; 1811 1812 /* Do it in a process context. */ 1813 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1814 } 1815 1816 /* ARGSUSED */ 1817 static void 1818 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1819 { 1820 struct r92c_fw_cmd_rssi cmd; 1821 struct r92e_fw_cmd_rssi cmde; 1822 1823 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1824 1825 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1826 goto restart_timer; 1827 1828 mutex_enter(&sc->sc_write_mtx); 1829 if (sc->avg_pwdb != -1) { 1830 /* Indicate Rx signal strength to FW for rate adaptation. */ 1831 memset(&cmd, 0, sizeof(cmd)); 1832 memset(&cmde, 0, sizeof(cmde)); 1833 cmd.macid = 0; /* BSS. */ 1834 cmde.macid = 0; /* BSS. */ 1835 cmd.pwdb = sc->avg_pwdb; 1836 cmde.pwdb = sc->avg_pwdb; 1837 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1838 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1839 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1840 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1841 sizeof(cmd)); 1842 } else { 1843 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1844 sizeof(cmde)); 1845 } 1846 } 1847 1848 /* Do temperature compensation. */ 1849 urtwn_temp_calib(sc); 1850 mutex_exit(&sc->sc_write_mtx); 1851 1852 restart_timer: 1853 if (!sc->sc_dying) { 1854 /* Restart calibration timer. */ 1855 callout_schedule(&sc->sc_calib_to, hz); 1856 } 1857 } 1858 1859 static void 1860 urtwn_next_scan(void *arg) 1861 { 1862 struct urtwn_softc *sc = arg; 1863 int s; 1864 1865 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1866 1867 if (sc->sc_dying) 1868 return; 1869 1870 s = splnet(); 1871 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1872 ieee80211_next_scan(&sc->sc_ic); 1873 splx(s); 1874 } 1875 1876 static void 1877 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1878 { 1879 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1880 ether_sprintf(ni->ni_macaddr))); 1881 /* start with lowest Tx rate */ 1882 ni->ni_txrate = 0; 1883 } 1884 1885 static int 1886 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1887 { 1888 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1889 struct urtwn_cmd_newstate cmd; 1890 1891 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1892 device_xname(sc->sc_dev), __func__, 1893 ieee80211_state_name[nstate], nstate, arg)); 1894 1895 callout_stop(&sc->sc_scan_to); 1896 callout_stop(&sc->sc_calib_to); 1897 1898 /* Do it in a process context. */ 1899 cmd.state = nstate; 1900 cmd.arg = arg; 1901 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1902 return 0; 1903 } 1904 1905 static void 1906 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1907 { 1908 struct urtwn_cmd_newstate *cmd = arg; 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 struct ieee80211_node *ni; 1911 enum ieee80211_state ostate = ic->ic_state; 1912 enum ieee80211_state nstate = cmd->state; 1913 uint32_t reg; 1914 uint8_t sifs_time, msr; 1915 int s; 1916 1917 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1918 device_xname(sc->sc_dev), __func__, 1919 ieee80211_state_name[ostate], ostate, 1920 ieee80211_state_name[nstate], nstate)); 1921 1922 s = splnet(); 1923 mutex_enter(&sc->sc_write_mtx); 1924 1925 callout_stop(&sc->sc_scan_to); 1926 callout_stop(&sc->sc_calib_to); 1927 1928 switch (ostate) { 1929 case IEEE80211_S_INIT: 1930 break; 1931 1932 case IEEE80211_S_SCAN: 1933 if (nstate != IEEE80211_S_SCAN) { 1934 /* 1935 * End of scanning 1936 */ 1937 /* flush 4-AC Queue after site_survey */ 1938 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1939 1940 /* Allow Rx from our BSSID only. */ 1941 urtwn_write_4(sc, R92C_RCR, 1942 urtwn_read_4(sc, R92C_RCR) | 1943 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1944 } 1945 break; 1946 1947 case IEEE80211_S_AUTH: 1948 case IEEE80211_S_ASSOC: 1949 break; 1950 1951 case IEEE80211_S_RUN: 1952 /* Turn link LED off. */ 1953 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1954 1955 /* Set media status to 'No Link'. */ 1956 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1957 1958 /* Stop Rx of data frames. */ 1959 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1960 1961 /* Reset TSF. */ 1962 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1963 1964 /* Disable TSF synchronization. */ 1965 urtwn_write_1(sc, R92C_BCN_CTRL, 1966 urtwn_read_1(sc, R92C_BCN_CTRL) | 1967 R92C_BCN_CTRL_DIS_TSF_UDT0); 1968 1969 /* Back to 20MHz mode */ 1970 urtwn_set_chan(sc, ic->ic_curchan, 1971 IEEE80211_HTINFO_2NDCHAN_NONE); 1972 1973 if (ic->ic_opmode == IEEE80211_M_IBSS || 1974 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1975 /* Stop BCN */ 1976 urtwn_write_1(sc, R92C_BCN_CTRL, 1977 urtwn_read_1(sc, R92C_BCN_CTRL) & 1978 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1979 } 1980 1981 /* Reset EDCA parameters. */ 1982 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1983 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1984 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1985 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1986 1987 /* flush all cam entries */ 1988 urtwn_cam_init(sc); 1989 break; 1990 } 1991 1992 switch (nstate) { 1993 case IEEE80211_S_INIT: 1994 /* Turn link LED off. */ 1995 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1996 break; 1997 1998 case IEEE80211_S_SCAN: 1999 if (ostate != IEEE80211_S_SCAN) { 2000 /* 2001 * Begin of scanning 2002 */ 2003 2004 /* Set gain for scanning. */ 2005 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2006 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2007 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2008 2009 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2010 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2011 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2012 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2013 } 2014 2015 /* Set media status to 'No Link'. */ 2016 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2017 2018 /* Allow Rx from any BSSID. */ 2019 urtwn_write_4(sc, R92C_RCR, 2020 urtwn_read_4(sc, R92C_RCR) & 2021 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2022 2023 /* Stop Rx of data frames. */ 2024 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2025 2026 /* Disable update TSF */ 2027 urtwn_write_1(sc, R92C_BCN_CTRL, 2028 urtwn_read_1(sc, R92C_BCN_CTRL) | 2029 R92C_BCN_CTRL_DIS_TSF_UDT0); 2030 } 2031 2032 /* Make link LED blink during scan. */ 2033 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2034 2035 /* Pause AC Tx queues. */ 2036 urtwn_write_1(sc, R92C_TXPAUSE, 2037 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2038 2039 urtwn_set_chan(sc, ic->ic_curchan, 2040 IEEE80211_HTINFO_2NDCHAN_NONE); 2041 2042 /* Start periodic scan. */ 2043 if (!sc->sc_dying) 2044 callout_schedule(&sc->sc_scan_to, hz / 5); 2045 break; 2046 2047 case IEEE80211_S_AUTH: 2048 /* Set initial gain under link. */ 2049 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2050 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2051 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2052 2053 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2054 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2055 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2056 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2057 } 2058 2059 /* Set media status to 'No Link'. */ 2060 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2061 2062 /* Allow Rx from any BSSID. */ 2063 urtwn_write_4(sc, R92C_RCR, 2064 urtwn_read_4(sc, R92C_RCR) & 2065 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2066 2067 urtwn_set_chan(sc, ic->ic_curchan, 2068 IEEE80211_HTINFO_2NDCHAN_NONE); 2069 break; 2070 2071 case IEEE80211_S_ASSOC: 2072 break; 2073 2074 case IEEE80211_S_RUN: 2075 ni = ic->ic_bss; 2076 2077 /* XXX: Set 20MHz mode */ 2078 urtwn_set_chan(sc, ic->ic_curchan, 2079 IEEE80211_HTINFO_2NDCHAN_NONE); 2080 2081 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2082 /* Back to 20MHz mode */ 2083 urtwn_set_chan(sc, ic->ic_curchan, 2084 IEEE80211_HTINFO_2NDCHAN_NONE); 2085 2086 /* Set media status to 'No Link'. */ 2087 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2088 2089 /* Enable Rx of data frames. */ 2090 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2091 2092 /* Allow Rx from any BSSID. */ 2093 urtwn_write_4(sc, R92C_RCR, 2094 urtwn_read_4(sc, R92C_RCR) & 2095 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2096 2097 /* Accept Rx data/control/management frames */ 2098 urtwn_write_4(sc, R92C_RCR, 2099 urtwn_read_4(sc, R92C_RCR) | 2100 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2101 2102 /* Turn link LED on. */ 2103 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2104 break; 2105 } 2106 2107 /* Set media status to 'Associated'. */ 2108 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2109 2110 /* Set BSSID. */ 2111 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2112 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2113 2114 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2115 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2116 } else { 2117 /* 802.11b/g */ 2118 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2119 } 2120 2121 /* Enable Rx of data frames. */ 2122 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2123 2124 /* Set beacon interval. */ 2125 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2126 2127 msr = urtwn_read_1(sc, R92C_MSR); 2128 msr &= R92C_MSR_MASK; 2129 switch (ic->ic_opmode) { 2130 case IEEE80211_M_STA: 2131 /* Allow Rx from our BSSID only. */ 2132 urtwn_write_4(sc, R92C_RCR, 2133 urtwn_read_4(sc, R92C_RCR) | 2134 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2135 2136 /* Enable TSF synchronization. */ 2137 urtwn_tsf_sync_enable(sc); 2138 2139 msr |= R92C_MSR_INFRA; 2140 break; 2141 case IEEE80211_M_HOSTAP: 2142 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2143 2144 /* Allow Rx from any BSSID. */ 2145 urtwn_write_4(sc, R92C_RCR, 2146 urtwn_read_4(sc, R92C_RCR) & 2147 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2148 2149 /* Reset TSF timer to zero. */ 2150 reg = urtwn_read_4(sc, R92C_TCR); 2151 reg &= ~0x01; 2152 urtwn_write_4(sc, R92C_TCR, reg); 2153 reg |= 0x01; 2154 urtwn_write_4(sc, R92C_TCR, reg); 2155 2156 msr |= R92C_MSR_AP; 2157 break; 2158 default: 2159 msr |= R92C_MSR_ADHOC; 2160 break; 2161 } 2162 urtwn_write_1(sc, R92C_MSR, msr); 2163 2164 sifs_time = 10; 2165 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2166 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2167 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2168 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2169 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2170 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2171 2172 /* Initialize rate adaptation. */ 2173 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2174 ISSET(sc->chip, URTWN_CHIP_92EU)) 2175 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2176 else 2177 urtwn_ra_init(sc); 2178 2179 /* Turn link LED on. */ 2180 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2181 2182 /* Reset average RSSI. */ 2183 sc->avg_pwdb = -1; 2184 2185 /* Reset temperature calibration state machine. */ 2186 sc->thcal_state = 0; 2187 sc->thcal_lctemp = 0; 2188 2189 /* Start periodic calibration. */ 2190 if (!sc->sc_dying) 2191 callout_schedule(&sc->sc_calib_to, hz); 2192 break; 2193 } 2194 2195 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2196 2197 mutex_exit(&sc->sc_write_mtx); 2198 splx(s); 2199 } 2200 2201 static int 2202 urtwn_wme_update(struct ieee80211com *ic) 2203 { 2204 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2205 2206 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2207 2208 /* don't override default WME values if WME is not actually enabled */ 2209 if (!(ic->ic_flags & IEEE80211_F_WME)) 2210 return 0; 2211 2212 /* Do it in a process context. */ 2213 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2214 return 0; 2215 } 2216 2217 static void 2218 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2219 { 2220 static const uint16_t ac2reg[WME_NUM_AC] = { 2221 R92C_EDCA_BE_PARAM, 2222 R92C_EDCA_BK_PARAM, 2223 R92C_EDCA_VI_PARAM, 2224 R92C_EDCA_VO_PARAM 2225 }; 2226 struct ieee80211com *ic = &sc->sc_ic; 2227 const struct wmeParams *wmep; 2228 int ac, aifs, slottime; 2229 int s; 2230 2231 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2232 __func__)); 2233 2234 s = splnet(); 2235 mutex_enter(&sc->sc_write_mtx); 2236 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2237 for (ac = 0; ac < WME_NUM_AC; ac++) { 2238 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2239 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2240 aifs = wmep->wmep_aifsn * slottime + 10; 2241 urtwn_write_4(sc, ac2reg[ac], 2242 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2243 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2244 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2245 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2246 } 2247 mutex_exit(&sc->sc_write_mtx); 2248 splx(s); 2249 } 2250 2251 static void 2252 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2253 { 2254 int pwdb; 2255 2256 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2257 device_xname(sc->sc_dev), __func__, rate, rssi)); 2258 2259 /* Convert antenna signal to percentage. */ 2260 if (rssi <= -100 || rssi >= 20) 2261 pwdb = 0; 2262 else if (rssi >= 0) 2263 pwdb = 100; 2264 else 2265 pwdb = 100 + rssi; 2266 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2267 if (rate <= 3) { 2268 /* CCK gain is smaller than OFDM/MCS gain. */ 2269 pwdb += 6; 2270 if (pwdb > 100) 2271 pwdb = 100; 2272 if (pwdb <= 14) 2273 pwdb -= 4; 2274 else if (pwdb <= 26) 2275 pwdb -= 8; 2276 else if (pwdb <= 34) 2277 pwdb -= 6; 2278 else if (pwdb <= 42) 2279 pwdb -= 2; 2280 } 2281 } 2282 if (sc->avg_pwdb == -1) /* Init. */ 2283 sc->avg_pwdb = pwdb; 2284 else if (sc->avg_pwdb < pwdb) 2285 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2286 else 2287 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2288 2289 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2290 device_xname(sc->sc_dev), __func__, 2291 rate, rssi, pwdb, sc->avg_pwdb)); 2292 } 2293 2294 static int8_t 2295 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2296 { 2297 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2298 struct r92c_rx_phystat *phy; 2299 struct r92c_rx_cck *cck; 2300 uint8_t rpt; 2301 int8_t rssi; 2302 2303 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2304 __func__, rate)); 2305 2306 if (rate <= 3) { 2307 cck = (struct r92c_rx_cck *)physt; 2308 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2309 rpt = (cck->agc_rpt >> 5) & 0x3; 2310 rssi = (cck->agc_rpt & 0x1f) << 1; 2311 } else { 2312 rpt = (cck->agc_rpt >> 6) & 0x3; 2313 rssi = cck->agc_rpt & 0x3e; 2314 } 2315 rssi = cckoff[rpt] - rssi; 2316 } else { /* OFDM/HT. */ 2317 phy = (struct r92c_rx_phystat *)physt; 2318 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2319 } 2320 return rssi; 2321 } 2322 2323 static int8_t 2324 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2325 { 2326 struct r92c_rx_phystat *phy; 2327 struct r88e_rx_cck *cck; 2328 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2329 int8_t rssi; 2330 2331 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2332 __func__, rate)); 2333 2334 rssi = 0; 2335 if (rate <= 3) { 2336 cck = (struct r88e_rx_cck *)physt; 2337 cck_agc_rpt = cck->agc_rpt; 2338 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2339 vga_idx = cck_agc_rpt & 0x1f; 2340 switch (lna_idx) { 2341 case 7: 2342 if (vga_idx <= 27) 2343 rssi = -100 + 2* (27 - vga_idx); 2344 else 2345 rssi = -100; 2346 break; 2347 case 6: 2348 rssi = -48 + 2 * (2 - vga_idx); 2349 break; 2350 case 5: 2351 rssi = -42 + 2 * (7 - vga_idx); 2352 break; 2353 case 4: 2354 rssi = -36 + 2 * (7 - vga_idx); 2355 break; 2356 case 3: 2357 rssi = -24 + 2 * (7 - vga_idx); 2358 break; 2359 case 2: 2360 rssi = -12 + 2 * (5 - vga_idx); 2361 break; 2362 case 1: 2363 rssi = 8 - (2 * vga_idx); 2364 break; 2365 case 0: 2366 rssi = 14 - (2 * vga_idx); 2367 break; 2368 } 2369 rssi += 6; 2370 } else { /* OFDM/HT. */ 2371 phy = (struct r92c_rx_phystat *)physt; 2372 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2373 } 2374 return rssi; 2375 } 2376 2377 static void 2378 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2379 { 2380 struct ieee80211com *ic = &sc->sc_ic; 2381 struct ifnet *ifp = ic->ic_ifp; 2382 struct ieee80211_frame *wh; 2383 struct ieee80211_node *ni; 2384 struct r92c_rx_desc_usb *stat; 2385 uint32_t rxdw0, rxdw3; 2386 struct mbuf *m; 2387 uint8_t rate; 2388 int8_t rssi = 0; 2389 int s, infosz; 2390 2391 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2392 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2393 2394 stat = (struct r92c_rx_desc_usb *)buf; 2395 rxdw0 = le32toh(stat->rxdw0); 2396 rxdw3 = le32toh(stat->rxdw3); 2397 2398 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2399 /* 2400 * This should not happen since we setup our Rx filter 2401 * to not receive these frames. 2402 */ 2403 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2404 device_xname(sc->sc_dev), __func__)); 2405 ifp->if_ierrors++; 2406 return; 2407 } 2408 /* 2409 * XXX: This will drop most control packets. Do we really 2410 * want this in IEEE80211_M_MONITOR mode? 2411 */ 2412 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2413 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2414 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2415 device_xname(sc->sc_dev), __func__, pktlen)); 2416 ic->ic_stats.is_rx_tooshort++; 2417 ifp->if_ierrors++; 2418 return; 2419 } 2420 if (__predict_false(pktlen > MCLBYTES)) { 2421 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2422 device_xname(sc->sc_dev), __func__, pktlen)); 2423 ifp->if_ierrors++; 2424 return; 2425 } 2426 2427 rate = MS(rxdw3, R92C_RXDW3_RATE); 2428 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2429 2430 /* Get RSSI from PHY status descriptor if present. */ 2431 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2432 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2433 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2434 else 2435 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2436 /* Update our average RSSI. */ 2437 urtwn_update_avgrssi(sc, rate, rssi); 2438 } 2439 2440 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2441 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2442 2443 MGETHDR(m, M_DONTWAIT, MT_DATA); 2444 if (__predict_false(m == NULL)) { 2445 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2446 ic->ic_stats.is_rx_nobuf++; 2447 ifp->if_ierrors++; 2448 return; 2449 } 2450 if (pktlen > (int)MHLEN) { 2451 MCLGET(m, M_DONTWAIT); 2452 if (__predict_false(!(m->m_flags & M_EXT))) { 2453 aprint_error_dev(sc->sc_dev, 2454 "couldn't allocate rx mbuf cluster\n"); 2455 m_freem(m); 2456 ic->ic_stats.is_rx_nobuf++; 2457 ifp->if_ierrors++; 2458 return; 2459 } 2460 } 2461 2462 /* Finalize mbuf. */ 2463 m_set_rcvif(m, ifp); 2464 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2465 memcpy(mtod(m, uint8_t *), wh, pktlen); 2466 m->m_pkthdr.len = m->m_len = pktlen; 2467 2468 s = splnet(); 2469 if (__predict_false(sc->sc_drvbpf != NULL)) { 2470 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2471 2472 tap->wr_flags = 0; 2473 if (!(rxdw3 & R92C_RXDW3_HT)) { 2474 switch (rate) { 2475 /* CCK. */ 2476 case 0: tap->wr_rate = 2; break; 2477 case 1: tap->wr_rate = 4; break; 2478 case 2: tap->wr_rate = 11; break; 2479 case 3: tap->wr_rate = 22; break; 2480 /* OFDM. */ 2481 case 4: tap->wr_rate = 12; break; 2482 case 5: tap->wr_rate = 18; break; 2483 case 6: tap->wr_rate = 24; break; 2484 case 7: tap->wr_rate = 36; break; 2485 case 8: tap->wr_rate = 48; break; 2486 case 9: tap->wr_rate = 72; break; 2487 case 10: tap->wr_rate = 96; break; 2488 case 11: tap->wr_rate = 108; break; 2489 } 2490 } else if (rate >= 12) { /* MCS0~15. */ 2491 /* Bit 7 set means HT MCS instead of rate. */ 2492 tap->wr_rate = 0x80 | (rate - 12); 2493 } 2494 tap->wr_dbm_antsignal = rssi; 2495 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2496 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2497 2498 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2499 } 2500 2501 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2502 2503 /* push the frame up to the 802.11 stack */ 2504 ieee80211_input(ic, m, ni, rssi, 0); 2505 2506 /* Node is no longer needed. */ 2507 ieee80211_free_node(ni); 2508 2509 splx(s); 2510 } 2511 2512 static void 2513 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2514 { 2515 struct urtwn_rx_data *data = priv; 2516 struct urtwn_softc *sc = data->sc; 2517 struct r92c_rx_desc_usb *stat; 2518 size_t pidx = data->pidx; 2519 uint32_t rxdw0; 2520 uint8_t *buf; 2521 int len, totlen, pktlen, infosz, npkts; 2522 2523 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2524 device_xname(sc->sc_dev), __func__, status)); 2525 2526 mutex_enter(&sc->sc_rx_mtx); 2527 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2528 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2529 /* Put this Rx buffer back to our free list. */ 2530 mutex_exit(&sc->sc_rx_mtx); 2531 2532 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2533 if (status == USBD_STALLED) 2534 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2535 else if (status != USBD_CANCELLED) 2536 goto resubmit; 2537 return; 2538 } 2539 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2540 2541 if (__predict_false(len < (int)sizeof(*stat))) { 2542 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2543 device_xname(sc->sc_dev), __func__, len)); 2544 goto resubmit; 2545 } 2546 buf = data->buf; 2547 2548 /* Get the number of encapsulated frames. */ 2549 stat = (struct r92c_rx_desc_usb *)buf; 2550 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2551 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2552 device_xname(sc->sc_dev), __func__, npkts)); 2553 2554 if (npkts != 0) 2555 rnd_add_uint32(&sc->rnd_source, npkts); 2556 2557 /* Process all of them. */ 2558 while (npkts-- > 0) { 2559 if (__predict_false(len < (int)sizeof(*stat))) { 2560 DPRINTFN(DBG_RX, 2561 ("%s: %s: len(%d) is short than header\n", 2562 device_xname(sc->sc_dev), __func__, len)); 2563 break; 2564 } 2565 stat = (struct r92c_rx_desc_usb *)buf; 2566 rxdw0 = le32toh(stat->rxdw0); 2567 2568 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2569 if (__predict_false(pktlen == 0)) { 2570 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2571 device_xname(sc->sc_dev), __func__)); 2572 break; 2573 } 2574 2575 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2576 2577 /* Make sure everything fits in xfer. */ 2578 totlen = sizeof(*stat) + infosz + pktlen; 2579 if (__predict_false(totlen > len)) { 2580 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2581 device_xname(sc->sc_dev), __func__, totlen, 2582 (int)sizeof(*stat), infosz, pktlen, len)); 2583 break; 2584 } 2585 2586 /* Process 802.11 frame. */ 2587 urtwn_rx_frame(sc, buf, pktlen); 2588 2589 /* Next chunk is 128-byte aligned. */ 2590 totlen = roundup2(totlen, 128); 2591 buf += totlen; 2592 len -= totlen; 2593 } 2594 2595 resubmit: 2596 /* Setup a new transfer. */ 2597 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2598 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2599 (void)usbd_transfer(xfer); 2600 } 2601 2602 static void 2603 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2604 { 2605 size_t pidx = data->pidx; 2606 2607 mutex_enter(&sc->sc_tx_mtx); 2608 /* Put this Tx buffer back to our free list. */ 2609 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2610 mutex_exit(&sc->sc_tx_mtx); 2611 } 2612 2613 static void 2614 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2615 { 2616 struct urtwn_tx_data *data = priv; 2617 struct urtwn_softc *sc = data->sc; 2618 struct ifnet *ifp = &sc->sc_if; 2619 size_t pidx = data->pidx; 2620 int s; 2621 2622 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2623 device_xname(sc->sc_dev), __func__, status)); 2624 2625 urtwn_put_tx_data(sc, data); 2626 2627 s = splnet(); 2628 sc->tx_timer = 0; 2629 ifp->if_flags &= ~IFF_OACTIVE; 2630 2631 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2632 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2633 if (status == USBD_STALLED) { 2634 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2635 usbd_clear_endpoint_stall_async(pipe); 2636 } 2637 printf("ERROR1\n"); 2638 ifp->if_oerrors++; 2639 } 2640 splx(s); 2641 return; 2642 } 2643 2644 ifp->if_opackets++; 2645 urtwn_start(ifp); 2646 splx(s); 2647 2648 } 2649 2650 static int 2651 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2652 struct urtwn_tx_data *data) 2653 { 2654 struct ieee80211com *ic = &sc->sc_ic; 2655 struct ieee80211_frame *wh; 2656 struct ieee80211_key *k = NULL; 2657 struct r92c_tx_desc_usb *txd; 2658 size_t i, padsize, xferlen, txd_len; 2659 uint16_t seq, sum; 2660 uint8_t raid, type, tid; 2661 int s, hasqos, error; 2662 2663 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2664 2665 wh = mtod(m, struct ieee80211_frame *); 2666 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2667 txd_len = sizeof(*txd); 2668 2669 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2670 txd_len = 32; 2671 2672 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2673 k = ieee80211_crypto_encap(ic, ni, m); 2674 if (k == NULL) { 2675 urtwn_put_tx_data(sc, data); 2676 m_free(m); 2677 return ENOBUFS; 2678 } 2679 2680 /* packet header may have moved, reset our local pointer */ 2681 wh = mtod(m, struct ieee80211_frame *); 2682 } 2683 2684 if (__predict_false(sc->sc_drvbpf != NULL)) { 2685 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2686 2687 tap->wt_flags = 0; 2688 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2689 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2690 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2691 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2692 2693 /* XXX: set tap->wt_rate? */ 2694 2695 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2696 } 2697 2698 /* non-qos data frames */ 2699 tid = R92C_TXDW1_QSEL_BE; 2700 if ((hasqos = ieee80211_has_qos(wh))) { 2701 /* data frames in 11n mode */ 2702 struct ieee80211_qosframe *qwh = (void *)wh; 2703 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2704 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2705 tid = R92C_TXDW1_QSEL_MGNT; 2706 } 2707 2708 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2709 padsize = 8; 2710 else 2711 padsize = 0; 2712 2713 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2714 padsize = 0; 2715 2716 /* Fill Tx descriptor. */ 2717 txd = (struct r92c_tx_desc_usb *)data->buf; 2718 memset(txd, 0, txd_len + padsize); 2719 2720 txd->txdw0 |= htole32( 2721 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2722 SM(R92C_TXDW0_OFFSET, txd_len)); 2723 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2724 txd->txdw0 |= htole32( 2725 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2726 } 2727 2728 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2729 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2730 2731 /* fix pad field */ 2732 if (padsize > 0) { 2733 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2734 device_xname(sc->sc_dev), __func__, padsize)); 2735 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2736 } 2737 2738 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2739 type == IEEE80211_FC0_TYPE_DATA) { 2740 if (ic->ic_curmode == IEEE80211_MODE_11B) 2741 raid = R92C_RAID_11B; 2742 else 2743 raid = R92C_RAID_11BG; 2744 DPRINTFN(DBG_TX, 2745 ("%s: %s: data packet: tid=%d, raid=%d\n", 2746 device_xname(sc->sc_dev), __func__, tid, raid)); 2747 2748 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2749 txd->txdw1 |= htole32( 2750 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2751 SM(R92C_TXDW1_QSEL, tid) | 2752 SM(R92C_TXDW1_RAID, raid) | 2753 R92C_TXDW1_AGGBK); 2754 } else 2755 txd->txdw1 |= htole32( 2756 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2757 SM(R92C_TXDW1_QSEL, tid) | 2758 SM(R92C_TXDW1_RAID, raid) | 2759 R92C_TXDW1_AGGBK); 2760 2761 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2762 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2763 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2764 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2765 2766 if (hasqos) { 2767 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2768 } 2769 2770 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2771 /* for 11g */ 2772 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2773 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2774 R92C_TXDW4_HWRTSEN); 2775 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2776 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2777 R92C_TXDW4_HWRTSEN); 2778 } 2779 } 2780 /* Send RTS at OFDM24. */ 2781 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2782 txd->txdw5 |= htole32(0x0001ff00); 2783 /* Send data at OFDM54. */ 2784 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2785 txd->txdw5 |= htole32(0x13 & 0x3f); 2786 else 2787 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2788 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2789 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2790 device_xname(sc->sc_dev), __func__)); 2791 txd->txdw1 |= htole32( 2792 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2793 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2794 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2795 2796 /* Force CCK1. */ 2797 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2798 /* Use 1Mbps */ 2799 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2800 } else { 2801 /* broadcast or multicast packets */ 2802 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2803 device_xname(sc->sc_dev), __func__)); 2804 txd->txdw1 |= htole32( 2805 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2806 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2807 2808 /* Force CCK1. */ 2809 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2810 /* Use 1Mbps */ 2811 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2812 } 2813 /* Set sequence number */ 2814 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2815 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2816 txd->txdseq |= htole16(seq); 2817 2818 if (!hasqos) { 2819 /* Use HW sequence numbering for non-QoS frames. */ 2820 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2821 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2822 } 2823 } else { 2824 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2825 R92E_HWSEQ_SHIFT); 2826 if (!hasqos) { 2827 /* Use HW sequence numbering for non-QoS frames. */ 2828 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2829 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2830 } 2831 } 2832 2833 /* Compute Tx descriptor checksum. */ 2834 sum = 0; 2835 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2836 sum ^= ((uint16_t *)txd)[i]; 2837 txd->txdsum = sum; /* NB: already little endian. */ 2838 2839 xferlen = txd_len + m->m_pkthdr.len + padsize; 2840 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2841 2842 s = splnet(); 2843 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2844 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2845 urtwn_txeof); 2846 error = usbd_transfer(data->xfer); 2847 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2848 error != USBD_IN_PROGRESS)) { 2849 splx(s); 2850 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2851 device_xname(sc->sc_dev), __func__, error)); 2852 return error; 2853 } 2854 splx(s); 2855 return 0; 2856 } 2857 2858 struct urtwn_tx_data * 2859 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2860 { 2861 struct urtwn_tx_data *data = NULL; 2862 2863 mutex_enter(&sc->sc_tx_mtx); 2864 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2865 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2866 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2867 } 2868 mutex_exit(&sc->sc_tx_mtx); 2869 2870 return data; 2871 } 2872 2873 static void 2874 urtwn_start(struct ifnet *ifp) 2875 { 2876 struct urtwn_softc *sc = ifp->if_softc; 2877 struct ieee80211com *ic = &sc->sc_ic; 2878 struct urtwn_tx_data *data; 2879 struct ether_header *eh; 2880 struct ieee80211_node *ni; 2881 struct mbuf *m; 2882 2883 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2884 2885 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2886 return; 2887 2888 data = NULL; 2889 for (;;) { 2890 /* Send pending management frames first. */ 2891 IF_POLL(&ic->ic_mgtq, m); 2892 if (m != NULL) { 2893 /* Use AC_VO for management frames. */ 2894 2895 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2896 2897 if (data == NULL) { 2898 ifp->if_flags |= IFF_OACTIVE; 2899 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2900 device_xname(sc->sc_dev))); 2901 return; 2902 } 2903 IF_DEQUEUE(&ic->ic_mgtq, m); 2904 ni = M_GETCTX(m, struct ieee80211_node *); 2905 M_CLEARCTX(m); 2906 goto sendit; 2907 } 2908 if (ic->ic_state != IEEE80211_S_RUN) 2909 break; 2910 2911 /* Encapsulate and send data frames. */ 2912 IFQ_POLL(&ifp->if_snd, m); 2913 if (m == NULL) 2914 break; 2915 2916 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2917 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2918 uint8_t qid = WME_AC_BE; 2919 if (ieee80211_has_qos(wh)) { 2920 /* data frames in 11n mode */ 2921 struct ieee80211_qosframe *qwh = (void *)wh; 2922 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2923 qid = TID_TO_WME_AC(tid); 2924 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2925 qid = WME_AC_VO; 2926 } 2927 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2928 2929 if (data == NULL) { 2930 ifp->if_flags |= IFF_OACTIVE; 2931 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2932 device_xname(sc->sc_dev))); 2933 return; 2934 } 2935 IFQ_DEQUEUE(&ifp->if_snd, m); 2936 2937 if (m->m_len < (int)sizeof(*eh) && 2938 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2939 printf("ERROR6\n"); 2940 ifp->if_oerrors++; 2941 urtwn_put_tx_data(sc, data); 2942 m_freem(m); 2943 continue; 2944 } 2945 eh = mtod(m, struct ether_header *); 2946 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2947 if (ni == NULL) { 2948 printf("ERROR5\n"); 2949 ifp->if_oerrors++; 2950 urtwn_put_tx_data(sc, data); 2951 m_freem(m); 2952 continue; 2953 } 2954 2955 bpf_mtap(ifp, m, BPF_D_OUT); 2956 2957 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2958 ieee80211_free_node(ni); 2959 printf("ERROR4\n"); 2960 ifp->if_oerrors++; 2961 urtwn_put_tx_data(sc, data); 2962 m_freem(m); 2963 continue; 2964 } 2965 sendit: 2966 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2967 2968 if (urtwn_tx(sc, m, ni, data) != 0) { 2969 m_freem(m); 2970 ieee80211_free_node(ni); 2971 printf("ERROR3\n"); 2972 ifp->if_oerrors++; 2973 continue; 2974 } 2975 m_freem(m); 2976 ieee80211_free_node(ni); 2977 sc->tx_timer = 5; 2978 ifp->if_timer = 1; 2979 } 2980 } 2981 2982 static void 2983 urtwn_watchdog(struct ifnet *ifp) 2984 { 2985 struct urtwn_softc *sc = ifp->if_softc; 2986 2987 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2988 2989 ifp->if_timer = 0; 2990 2991 if (sc->tx_timer > 0) { 2992 if (--sc->tx_timer == 0) { 2993 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2994 /* urtwn_init(ifp); XXX needs a process context! */ 2995 printf("ERROR2\n"); 2996 ifp->if_oerrors++; 2997 return; 2998 } 2999 ifp->if_timer = 1; 3000 } 3001 ieee80211_watchdog(&sc->sc_ic); 3002 } 3003 3004 static int 3005 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3006 { 3007 struct urtwn_softc *sc = ifp->if_softc; 3008 struct ieee80211com *ic = &sc->sc_ic; 3009 int s, error = 0; 3010 3011 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 3012 device_xname(sc->sc_dev), __func__, cmd, data)); 3013 3014 s = splnet(); 3015 3016 switch (cmd) { 3017 case SIOCSIFFLAGS: 3018 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3019 break; 3020 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3021 case IFF_UP | IFF_RUNNING: 3022 break; 3023 case IFF_UP: 3024 urtwn_init(ifp); 3025 break; 3026 case IFF_RUNNING: 3027 urtwn_stop(ifp, 1); 3028 break; 3029 case 0: 3030 break; 3031 } 3032 break; 3033 3034 case SIOCADDMULTI: 3035 case SIOCDELMULTI: 3036 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3037 /* setup multicast filter, etc */ 3038 error = 0; 3039 } 3040 break; 3041 3042 case SIOCS80211CHANNEL: 3043 /* 3044 * This allows for fast channel switching in monitor mode 3045 * (used by kismet). In IBSS mode, we must explicitly reset 3046 * the interface to generate a new beacon frame. 3047 */ 3048 error = ieee80211_ioctl(ic, cmd, data); 3049 if (error == ENETRESET && 3050 ic->ic_opmode == IEEE80211_M_MONITOR) { 3051 urtwn_set_chan(sc, ic->ic_curchan, 3052 IEEE80211_HTINFO_2NDCHAN_NONE); 3053 error = 0; 3054 } 3055 break; 3056 3057 default: 3058 error = ieee80211_ioctl(ic, cmd, data); 3059 break; 3060 } 3061 if (error == ENETRESET) { 3062 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3063 (IFF_UP | IFF_RUNNING) && 3064 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3065 urtwn_init(ifp); 3066 } 3067 error = 0; 3068 } 3069 3070 splx(s); 3071 3072 return error; 3073 } 3074 3075 static __inline int 3076 urtwn_power_on(struct urtwn_softc *sc) 3077 { 3078 3079 return sc->sc_power_on(sc); 3080 } 3081 3082 static int 3083 urtwn_r92c_power_on(struct urtwn_softc *sc) 3084 { 3085 uint32_t reg; 3086 int ntries; 3087 3088 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3089 3090 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3091 3092 /* Wait for autoload done bit. */ 3093 for (ntries = 0; ntries < 1000; ntries++) { 3094 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3095 break; 3096 DELAY(5); 3097 } 3098 if (ntries == 1000) { 3099 aprint_error_dev(sc->sc_dev, 3100 "timeout waiting for chip autoload\n"); 3101 return ETIMEDOUT; 3102 } 3103 3104 /* Unlock ISO/CLK/Power control register. */ 3105 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3106 /* Move SPS into PWM mode. */ 3107 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3108 DELAY(5); 3109 3110 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3111 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3112 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3113 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3114 DELAY(100); 3115 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3116 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3117 ~R92C_SYS_ISO_CTRL_MD2PP); 3118 } 3119 3120 /* Auto enable WLAN. */ 3121 urtwn_write_2(sc, R92C_APS_FSMCO, 3122 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3123 for (ntries = 0; ntries < 1000; ntries++) { 3124 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3125 R92C_APS_FSMCO_APFM_ONMAC)) 3126 break; 3127 DELAY(100); 3128 } 3129 if (ntries == 1000) { 3130 aprint_error_dev(sc->sc_dev, 3131 "timeout waiting for MAC auto ON\n"); 3132 return ETIMEDOUT; 3133 } 3134 3135 /* Enable radio, GPIO and LED functions. */ 3136 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3137 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3138 urtwn_write_2(sc, R92C_APS_FSMCO, 3139 R92C_APS_FSMCO_AFSM_HSUS | 3140 R92C_APS_FSMCO_PDN_EN | 3141 R92C_APS_FSMCO_PFM_ALDN); 3142 3143 /* Release RF digital isolation. */ 3144 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3145 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3146 3147 /* Initialize MAC. */ 3148 urtwn_write_1(sc, R92C_APSD_CTRL, 3149 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3150 for (ntries = 0; ntries < 200; ntries++) { 3151 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3152 R92C_APSD_CTRL_OFF_STATUS)) 3153 break; 3154 DELAY(5); 3155 } 3156 if (ntries == 200) { 3157 aprint_error_dev(sc->sc_dev, 3158 "timeout waiting for MAC initialization\n"); 3159 return ETIMEDOUT; 3160 } 3161 3162 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3163 reg = urtwn_read_2(sc, R92C_CR); 3164 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3165 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3166 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3167 R92C_CR_ENSEC; 3168 urtwn_write_2(sc, R92C_CR, reg); 3169 3170 urtwn_write_1(sc, 0xfe10, 0x19); 3171 return 0; 3172 } 3173 3174 static int 3175 urtwn_r92e_power_on(struct urtwn_softc *sc) 3176 { 3177 uint32_t reg; 3178 uint32_t val; 3179 int ntries; 3180 3181 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3182 3183 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3184 3185 /* Enable radio, GPIO and LED functions. */ 3186 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3187 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3188 urtwn_write_2(sc, R92C_APS_FSMCO, 3189 R92C_APS_FSMCO_AFSM_HSUS | 3190 R92C_APS_FSMCO_PDN_EN | 3191 R92C_APS_FSMCO_PFM_ALDN); 3192 3193 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3194 /* LDO. */ 3195 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3196 } 3197 else { 3198 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3199 R92C_SYS_SWR_CTRL2) & 0xffff); 3200 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3201 } 3202 3203 for (ntries = 0; ntries < 2; ntries++) { 3204 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3205 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3206 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3207 R92C_AFE_CTRL4)); 3208 } 3209 3210 /* Reset BB. */ 3211 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3212 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3213 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3214 3215 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3216 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3217 3218 /* Disable HWPDN. */ 3219 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3220 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3221 3222 /* Disable WL suspend. */ 3223 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3224 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3225 R92C_APS_FSMCO_AFSM_HSUS)); 3226 3227 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3228 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3229 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3230 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3231 for (ntries = 0; ntries < 10000; ntries++) { 3232 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3233 R92C_APS_FSMCO_APFM_ONMAC; 3234 if (val == 0x0) 3235 break; 3236 DELAY(10); 3237 } 3238 if (ntries == 10000) { 3239 aprint_error_dev(sc->sc_dev, 3240 "timeout waiting for chip power up\n"); 3241 return ETIMEDOUT; 3242 } 3243 3244 urtwn_write_2(sc, R92C_CR, 0x00); 3245 reg = urtwn_read_2(sc, R92C_CR); 3246 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3247 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3248 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3249 urtwn_write_2(sc, R92C_CR, reg); 3250 3251 return 0; 3252 } 3253 3254 static int 3255 urtwn_r88e_power_on(struct urtwn_softc *sc) 3256 { 3257 uint32_t reg; 3258 uint8_t val; 3259 int ntries; 3260 3261 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3262 3263 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3264 3265 /* Wait for power ready bit. */ 3266 for (ntries = 0; ntries < 5000; ntries++) { 3267 val = urtwn_read_1(sc, 0x6) & 0x2; 3268 if (val == 0x2) 3269 break; 3270 DELAY(10); 3271 } 3272 if (ntries == 5000) { 3273 aprint_error_dev(sc->sc_dev, 3274 "timeout waiting for chip power up\n"); 3275 return ETIMEDOUT; 3276 } 3277 3278 /* Reset BB. */ 3279 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3280 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3281 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3282 3283 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3284 3285 /* Disable HWPDN. */ 3286 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3287 3288 /* Disable WL suspend. */ 3289 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3290 3291 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3292 for (ntries = 0; ntries < 5000; ntries++) { 3293 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3294 break; 3295 DELAY(10); 3296 } 3297 if (ntries == 5000) 3298 return ETIMEDOUT; 3299 3300 /* Enable LDO normal mode. */ 3301 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3302 3303 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3304 urtwn_write_2(sc, R92C_CR, 0); 3305 reg = urtwn_read_2(sc, R92C_CR); 3306 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3307 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3308 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3309 urtwn_write_2(sc, R92C_CR, reg); 3310 3311 return 0; 3312 } 3313 3314 static int 3315 urtwn_llt_init(struct urtwn_softc *sc) 3316 { 3317 size_t i, page_count, pktbuf_count; 3318 uint32_t val; 3319 int error; 3320 3321 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3322 3323 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3324 3325 if (sc->chip & URTWN_CHIP_88E) 3326 page_count = R88E_TX_PAGE_COUNT; 3327 else if (sc->chip & URTWN_CHIP_92EU) 3328 page_count = R92E_TX_PAGE_COUNT; 3329 else 3330 page_count = R92C_TX_PAGE_COUNT; 3331 if (sc->chip & URTWN_CHIP_88E) 3332 pktbuf_count = R88E_TXPKTBUF_COUNT; 3333 else if (sc->chip & URTWN_CHIP_92EU) 3334 pktbuf_count = R88E_TXPKTBUF_COUNT; 3335 else 3336 pktbuf_count = R92C_TXPKTBUF_COUNT; 3337 3338 if (sc->chip & URTWN_CHIP_92EU) { 3339 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3340 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3341 DELAY(100); 3342 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3343 if (val & R92E_AUTO_LLT_EN) 3344 return EIO; 3345 return 0; 3346 } 3347 3348 /* Reserve pages [0; page_count]. */ 3349 for (i = 0; i < page_count; i++) { 3350 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3351 return error; 3352 } 3353 /* NB: 0xff indicates end-of-list. */ 3354 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3355 return error; 3356 /* 3357 * Use pages [page_count + 1; pktbuf_count - 1] 3358 * as ring buffer. 3359 */ 3360 for (++i; i < pktbuf_count - 1; i++) { 3361 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3362 return error; 3363 } 3364 /* Make the last page point to the beginning of the ring buffer. */ 3365 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3366 return error; 3367 } 3368 3369 static void 3370 urtwn_fw_reset(struct urtwn_softc *sc) 3371 { 3372 uint16_t reg; 3373 int ntries; 3374 3375 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3376 3377 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3378 3379 /* Tell 8051 to reset itself. */ 3380 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3381 3382 /* Wait until 8051 resets by itself. */ 3383 for (ntries = 0; ntries < 100; ntries++) { 3384 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3385 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3386 return; 3387 DELAY(50); 3388 } 3389 /* Force 8051 reset. */ 3390 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3391 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3392 } 3393 3394 static void 3395 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3396 { 3397 uint16_t reg; 3398 3399 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3400 3401 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3402 3403 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3404 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3405 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3406 } 3407 DELAY(50); 3408 3409 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3410 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3411 DELAY(50); 3412 3413 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3414 DELAY(50); 3415 3416 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3417 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3418 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3419 } 3420 DELAY(50); 3421 3422 } 3423 3424 static int 3425 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3426 { 3427 uint32_t reg; 3428 int off, mlen, error = 0; 3429 3430 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3431 device_xname(sc->sc_dev), __func__, page, buf, len)); 3432 3433 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3434 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3435 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3436 3437 off = R92C_FW_START_ADDR; 3438 while (len > 0) { 3439 if (len > 196) 3440 mlen = 196; 3441 else if (len > 4) 3442 mlen = 4; 3443 else 3444 mlen = 1; 3445 error = urtwn_write_region(sc, off, buf, mlen); 3446 if (error != 0) 3447 break; 3448 off += mlen; 3449 buf += mlen; 3450 len -= mlen; 3451 } 3452 return error; 3453 } 3454 3455 static int 3456 urtwn_load_firmware(struct urtwn_softc *sc) 3457 { 3458 firmware_handle_t fwh; 3459 const struct r92c_fw_hdr *hdr; 3460 const char *name; 3461 u_char *fw, *ptr; 3462 size_t len; 3463 uint32_t reg; 3464 int mlen, ntries, page, error; 3465 3466 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3467 3468 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3469 3470 /* Read firmware image from the filesystem. */ 3471 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3472 name = "rtl8188eufw.bin"; 3473 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3474 name = "rtl8192eefw.bin"; 3475 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3476 URTWN_CHIP_UMC_A_CUT) 3477 name = "rtl8192cfwU.bin"; 3478 else 3479 name = "rtl8192cfw.bin"; 3480 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3481 aprint_error_dev(sc->sc_dev, 3482 "failed load firmware of file %s (error %d)\n", name, 3483 error); 3484 return error; 3485 } 3486 const size_t fwlen = len = firmware_get_size(fwh); 3487 fw = firmware_malloc(len); 3488 if (fw == NULL) { 3489 aprint_error_dev(sc->sc_dev, 3490 "failed to allocate firmware memory\n"); 3491 firmware_close(fwh); 3492 return ENOMEM; 3493 } 3494 error = firmware_read(fwh, 0, fw, len); 3495 firmware_close(fwh); 3496 if (error != 0) { 3497 aprint_error_dev(sc->sc_dev, 3498 "failed to read firmware (error %d)\n", error); 3499 firmware_free(fw, fwlen); 3500 return error; 3501 } 3502 3503 len = fwlen; 3504 ptr = fw; 3505 hdr = (const struct r92c_fw_hdr *)ptr; 3506 /* Check if there is a valid FW header and skip it. */ 3507 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3508 (le16toh(hdr->signature) >> 4) == 0x88e || 3509 (le16toh(hdr->signature) >> 4) == 0x92e || 3510 (le16toh(hdr->signature) >> 4) == 0x92c) { 3511 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3512 device_xname(sc->sc_dev), __func__, 3513 le16toh(hdr->version), le16toh(hdr->subversion), 3514 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3515 ptr += sizeof(*hdr); 3516 len -= sizeof(*hdr); 3517 } 3518 3519 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3520 /* Reset MCU ready status */ 3521 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3522 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3523 ISSET(sc->chip, URTWN_CHIP_92EU)) 3524 urtwn_r88e_fw_reset(sc); 3525 else 3526 urtwn_fw_reset(sc); 3527 } 3528 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3529 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3530 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3531 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3532 R92C_SYS_FUNC_EN_CPUEN); 3533 } 3534 3535 /* download enabled */ 3536 urtwn_write_1(sc, R92C_MCUFWDL, 3537 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3538 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3539 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3540 3541 /* Reset the FWDL checksum. */ 3542 urtwn_write_1(sc, R92C_MCUFWDL, 3543 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3544 3545 DELAY(50); 3546 /* download firmware */ 3547 for (page = 0; len > 0; page++) { 3548 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3549 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3550 if (error != 0) { 3551 aprint_error_dev(sc->sc_dev, 3552 "could not load firmware page %d\n", page); 3553 goto fail; 3554 } 3555 ptr += mlen; 3556 len -= mlen; 3557 } 3558 3559 /* download disable */ 3560 urtwn_write_1(sc, R92C_MCUFWDL, 3561 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3562 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3563 3564 /* Wait for checksum report. */ 3565 for (ntries = 0; ntries < 1000; ntries++) { 3566 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3567 break; 3568 DELAY(5); 3569 } 3570 if (ntries == 1000) { 3571 aprint_error_dev(sc->sc_dev, 3572 "timeout waiting for checksum report\n"); 3573 error = ETIMEDOUT; 3574 goto fail; 3575 } 3576 3577 /* Wait for firmware readiness. */ 3578 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3579 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3580 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3581 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3582 ISSET(sc->chip, URTWN_CHIP_92EU)) 3583 urtwn_r88e_fw_reset(sc); 3584 for (ntries = 0; ntries < 6000; ntries++) { 3585 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3586 break; 3587 DELAY(5); 3588 } 3589 if (ntries == 6000) { 3590 aprint_error_dev(sc->sc_dev, 3591 "timeout waiting for firmware readiness\n"); 3592 error = ETIMEDOUT; 3593 goto fail; 3594 } 3595 fail: 3596 firmware_free(fw, fwlen); 3597 return error; 3598 } 3599 3600 static __inline int 3601 urtwn_dma_init(struct urtwn_softc *sc) 3602 { 3603 3604 return sc->sc_dma_init(sc); 3605 } 3606 3607 static int 3608 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3609 { 3610 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3611 uint32_t reg; 3612 int error; 3613 3614 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3615 3616 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3617 3618 /* Initialize LLT table. */ 3619 error = urtwn_llt_init(sc); 3620 if (error != 0) 3621 return error; 3622 3623 /* Get Tx queues to USB endpoints mapping. */ 3624 hashq = hasnq = haslq = 0; 3625 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3626 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3627 device_xname(sc->sc_dev), __func__, reg)); 3628 if (MS(reg, R92C_USB_EP_HQ) != 0) 3629 hashq = 1; 3630 if (MS(reg, R92C_USB_EP_NQ) != 0) 3631 hasnq = 1; 3632 if (MS(reg, R92C_USB_EP_LQ) != 0) 3633 haslq = 1; 3634 nqueues = hashq + hasnq + haslq; 3635 if (nqueues == 0) 3636 return EIO; 3637 /* Get the number of pages for each queue. */ 3638 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3639 /* The remaining pages are assigned to the high priority queue. */ 3640 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3641 3642 /* Set number of pages for normal priority queue. */ 3643 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3644 urtwn_write_4(sc, R92C_RQPN, 3645 /* Set number of pages for public queue. */ 3646 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3647 /* Set number of pages for high priority queue. */ 3648 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3649 /* Set number of pages for low priority queue. */ 3650 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3651 /* Load values. */ 3652 R92C_RQPN_LD); 3653 3654 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3655 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3656 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3657 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3658 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3659 3660 /* Set queue to USB pipe mapping. */ 3661 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3662 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3663 if (nqueues == 1) { 3664 if (hashq) { 3665 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3666 } else if (hasnq) { 3667 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3668 } else { 3669 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3670 } 3671 } else if (nqueues == 2) { 3672 /* All 2-endpoints configs have a high priority queue. */ 3673 if (!hashq) { 3674 return EIO; 3675 } 3676 if (hasnq) { 3677 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3678 } else { 3679 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3680 } 3681 } else { 3682 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3683 } 3684 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3685 3686 /* Set Tx/Rx transfer page boundary. */ 3687 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3688 3689 /* Set Tx/Rx transfer page size. */ 3690 urtwn_write_1(sc, R92C_PBP, 3691 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3692 return 0; 3693 } 3694 3695 static int 3696 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3697 { 3698 usb_interface_descriptor_t *id; 3699 uint32_t reg; 3700 int nqueues; 3701 int error; 3702 3703 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3704 3705 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3706 3707 /* Initialize LLT table. */ 3708 error = urtwn_llt_init(sc); 3709 if (error != 0) 3710 return error; 3711 3712 /* Get Tx queues to USB endpoints mapping. */ 3713 id = usbd_get_interface_descriptor(sc->sc_iface); 3714 nqueues = id->bNumEndpoints - 1; 3715 if (nqueues == 0) 3716 return EIO; 3717 3718 /* Set number of pages for normal priority queue. */ 3719 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3720 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3721 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3722 3723 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3724 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3725 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3726 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3727 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3728 3729 /* Set queue to USB pipe mapping. */ 3730 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3731 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3732 if (nqueues == 1) 3733 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3734 else if (nqueues == 2) 3735 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3736 else 3737 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3738 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3739 3740 /* Set Tx/Rx transfer page boundary. */ 3741 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3742 3743 /* Set Tx/Rx transfer page size. */ 3744 urtwn_write_1(sc, R92C_PBP, 3745 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3746 3747 return 0; 3748 } 3749 3750 static void 3751 urtwn_mac_init(struct urtwn_softc *sc) 3752 { 3753 size_t i; 3754 3755 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3756 3757 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3758 3759 /* Write MAC initialization values. */ 3760 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3761 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3762 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3763 rtl8188eu_mac[i].val); 3764 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3765 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3766 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3767 rtl8192eu_mac[i].val); 3768 } else { 3769 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3770 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3771 rtl8192cu_mac[i].val); 3772 } 3773 } 3774 3775 static void 3776 urtwn_bb_init(struct urtwn_softc *sc) 3777 { 3778 const struct rtwn_bb_prog *prog; 3779 uint32_t reg; 3780 uint8_t crystalcap; 3781 size_t i; 3782 3783 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3784 3785 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3786 3787 /* Enable BB and RF. */ 3788 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3789 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3790 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3791 R92C_SYS_FUNC_EN_DIO_RF); 3792 3793 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3794 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3795 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3796 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3797 } 3798 3799 urtwn_write_1(sc, R92C_RF_CTRL, 3800 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3801 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3802 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3803 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3804 3805 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3806 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3807 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3808 urtwn_write_1(sc, 0x15, 0xe9); 3809 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3810 } 3811 3812 /* Select BB programming based on board type. */ 3813 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3814 prog = &rtl8188eu_bb_prog; 3815 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3816 prog = &rtl8192eu_bb_prog; 3817 else if (!(sc->chip & URTWN_CHIP_92C)) { 3818 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3819 prog = &rtl8188ce_bb_prog; 3820 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3821 prog = &rtl8188ru_bb_prog; 3822 } else { 3823 prog = &rtl8188cu_bb_prog; 3824 } 3825 } else { 3826 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3827 prog = &rtl8192ce_bb_prog; 3828 } else { 3829 prog = &rtl8192cu_bb_prog; 3830 } 3831 } 3832 /* Write BB initialization values. */ 3833 for (i = 0; i < prog->count; i++) { 3834 /* additional delay depend on registers */ 3835 switch (prog->regs[i]) { 3836 case 0xfe: 3837 urtwn_delay_ms(sc, 50); 3838 break; 3839 case 0xfd: 3840 urtwn_delay_ms(sc, 5); 3841 break; 3842 case 0xfc: 3843 urtwn_delay_ms(sc, 1); 3844 break; 3845 case 0xfb: 3846 DELAY(50); 3847 break; 3848 case 0xfa: 3849 DELAY(5); 3850 break; 3851 case 0xf9: 3852 DELAY(1); 3853 break; 3854 } 3855 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3856 DELAY(1); 3857 } 3858 3859 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3860 /* 8192C 1T only configuration. */ 3861 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3862 reg = (reg & ~0x00000003) | 0x2; 3863 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3864 3865 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3866 reg = (reg & ~0x00300033) | 0x00200022; 3867 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3868 3869 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3870 reg = (reg & ~0xff000000) | (0x45 << 24); 3871 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3872 3873 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3874 reg = (reg & ~0x000000ff) | 0x23; 3875 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3876 3877 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3878 reg = (reg & ~0x00000030) | (1 << 4); 3879 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3880 3881 reg = urtwn_bb_read(sc, 0xe74); 3882 reg = (reg & ~0x0c000000) | (2 << 26); 3883 urtwn_bb_write(sc, 0xe74, reg); 3884 reg = urtwn_bb_read(sc, 0xe78); 3885 reg = (reg & ~0x0c000000) | (2 << 26); 3886 urtwn_bb_write(sc, 0xe78, reg); 3887 reg = urtwn_bb_read(sc, 0xe7c); 3888 reg = (reg & ~0x0c000000) | (2 << 26); 3889 urtwn_bb_write(sc, 0xe7c, reg); 3890 reg = urtwn_bb_read(sc, 0xe80); 3891 reg = (reg & ~0x0c000000) | (2 << 26); 3892 urtwn_bb_write(sc, 0xe80, reg); 3893 reg = urtwn_bb_read(sc, 0xe88); 3894 reg = (reg & ~0x0c000000) | (2 << 26); 3895 urtwn_bb_write(sc, 0xe88, reg); 3896 } 3897 3898 /* Write AGC values. */ 3899 for (i = 0; i < prog->agccount; i++) { 3900 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3901 DELAY(1); 3902 } 3903 3904 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3905 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3906 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3907 DELAY(1); 3908 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3909 DELAY(1); 3910 } 3911 3912 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3913 crystalcap = sc->r88e_rom[0xb9]; 3914 if (crystalcap == 0x00) 3915 crystalcap = 0x20; 3916 crystalcap &= 0x3f; 3917 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3918 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3919 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3920 crystalcap | crystalcap << 6)); 3921 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3922 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3923 crystalcap = sc->r88e_rom[0xb9]; 3924 if (crystalcap == 0xff) 3925 crystalcap = 0x20; 3926 crystalcap &= 0x3f; 3927 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3928 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3929 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3930 crystalcap | crystalcap << 6)); 3931 } else { 3932 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3933 R92C_HSSI_PARAM2_CCK_HIPWR) { 3934 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3935 } 3936 } 3937 } 3938 3939 static void 3940 urtwn_rf_init(struct urtwn_softc *sc) 3941 { 3942 const struct rtwn_rf_prog *prog; 3943 uint32_t reg, mask, saved; 3944 size_t i, j, idx; 3945 3946 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3947 3948 /* Select RF programming based on board type. */ 3949 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3950 prog = rtl8188eu_rf_prog; 3951 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3952 prog = rtl8192eu_rf_prog; 3953 else if (!(sc->chip & URTWN_CHIP_92C)) { 3954 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3955 prog = rtl8188ce_rf_prog; 3956 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3957 prog = rtl8188ru_rf_prog; 3958 } else { 3959 prog = rtl8188cu_rf_prog; 3960 } 3961 } else { 3962 prog = rtl8192ce_rf_prog; 3963 } 3964 3965 for (i = 0; i < sc->nrxchains; i++) { 3966 /* Save RF_ENV control type. */ 3967 idx = i / 2; 3968 mask = 0xffffU << ((i % 2) * 16); 3969 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3970 3971 /* Set RF_ENV enable. */ 3972 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3973 reg |= 0x100000; 3974 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3975 DELAY(50); 3976 3977 /* Set RF_ENV output high. */ 3978 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3979 reg |= 0x10; 3980 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3981 DELAY(50); 3982 3983 /* Set address and data lengths of RF registers. */ 3984 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3985 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3986 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3987 DELAY(50); 3988 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3989 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3990 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3991 DELAY(50); 3992 3993 /* Write RF initialization values for this chain. */ 3994 for (j = 0; j < prog[i].count; j++) { 3995 if (prog[i].regs[j] >= 0xf9 && 3996 prog[i].regs[j] <= 0xfe) { 3997 /* 3998 * These are fake RF registers offsets that 3999 * indicate a delay is required. 4000 */ 4001 urtwn_delay_ms(sc, 50); 4002 continue; 4003 } 4004 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4005 DELAY(5); 4006 } 4007 4008 /* Restore RF_ENV control type. */ 4009 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4010 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4011 } 4012 4013 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4014 URTWN_CHIP_UMC_A_CUT) { 4015 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4016 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4017 } 4018 4019 /* Cache RF register CHNLBW. */ 4020 for (i = 0; i < 2; i++) { 4021 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4022 } 4023 } 4024 4025 static void 4026 urtwn_cam_init(struct urtwn_softc *sc) 4027 { 4028 uint32_t content, command; 4029 uint8_t idx; 4030 size_t i; 4031 4032 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4033 4034 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4035 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4036 return; 4037 4038 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4039 content = (idx & 3) 4040 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4041 | R92C_CAM_VALID; 4042 4043 command = R92C_CAMCMD_POLLING 4044 | R92C_CAMCMD_WRITE 4045 | R92C_CAM_CTL0(idx); 4046 4047 urtwn_write_4(sc, R92C_CAMWRITE, content); 4048 urtwn_write_4(sc, R92C_CAMCMD, command); 4049 } 4050 4051 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4052 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4053 if (i == 0) { 4054 content = (idx & 3) 4055 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4056 | R92C_CAM_VALID; 4057 } else { 4058 content = 0; 4059 } 4060 4061 command = R92C_CAMCMD_POLLING 4062 | R92C_CAMCMD_WRITE 4063 | R92C_CAM_CTL0(idx) 4064 | i; 4065 4066 urtwn_write_4(sc, R92C_CAMWRITE, content); 4067 urtwn_write_4(sc, R92C_CAMCMD, command); 4068 } 4069 } 4070 4071 /* Invalidate all CAM entries. */ 4072 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4073 } 4074 4075 static void 4076 urtwn_pa_bias_init(struct urtwn_softc *sc) 4077 { 4078 uint8_t reg; 4079 size_t i; 4080 4081 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4082 4083 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4084 4085 for (i = 0; i < sc->nrxchains; i++) { 4086 if (sc->pa_setting & (1U << i)) 4087 continue; 4088 4089 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4090 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4091 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4092 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4093 } 4094 if (!(sc->pa_setting & 0x10)) { 4095 reg = urtwn_read_1(sc, 0x16); 4096 reg = (reg & ~0xf0) | 0x90; 4097 urtwn_write_1(sc, 0x16, reg); 4098 } 4099 } 4100 4101 static void 4102 urtwn_rxfilter_init(struct urtwn_softc *sc) 4103 { 4104 4105 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4106 4107 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4108 4109 /* Initialize Rx filter. */ 4110 /* TODO: use better filter for monitor mode. */ 4111 urtwn_write_4(sc, R92C_RCR, 4112 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4113 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4114 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4115 /* Accept all multicast frames. */ 4116 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4117 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4118 /* Accept all management frames. */ 4119 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4120 /* Reject all control frames. */ 4121 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4122 /* Accept all data frames. */ 4123 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4124 } 4125 4126 static void 4127 urtwn_edca_init(struct urtwn_softc *sc) 4128 { 4129 4130 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4131 4132 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4133 4134 /* set spec SIFS (used in NAV) */ 4135 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4136 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4137 4138 /* set SIFS CCK/OFDM */ 4139 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4140 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4141 4142 /* TXOP */ 4143 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4144 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4145 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4146 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4147 } 4148 4149 static void 4150 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4151 uint16_t power[URTWN_RIDX_COUNT]) 4152 { 4153 uint32_t reg; 4154 4155 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4156 __func__, chain)); 4157 4158 /* Write per-CCK rate Tx power. */ 4159 if (chain == 0) { 4160 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4161 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4162 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4163 4164 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4165 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4166 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4167 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4168 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4169 } else { 4170 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4171 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4172 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4173 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4174 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4175 4176 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4177 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4178 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4179 } 4180 /* Write per-OFDM rate Tx power. */ 4181 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4182 SM(R92C_TXAGC_RATE06, power[ 4]) | 4183 SM(R92C_TXAGC_RATE09, power[ 5]) | 4184 SM(R92C_TXAGC_RATE12, power[ 6]) | 4185 SM(R92C_TXAGC_RATE18, power[ 7])); 4186 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4187 SM(R92C_TXAGC_RATE24, power[ 8]) | 4188 SM(R92C_TXAGC_RATE36, power[ 9]) | 4189 SM(R92C_TXAGC_RATE48, power[10]) | 4190 SM(R92C_TXAGC_RATE54, power[11])); 4191 /* Write per-MCS Tx power. */ 4192 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4193 SM(R92C_TXAGC_MCS00, power[12]) | 4194 SM(R92C_TXAGC_MCS01, power[13]) | 4195 SM(R92C_TXAGC_MCS02, power[14]) | 4196 SM(R92C_TXAGC_MCS03, power[15])); 4197 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4198 SM(R92C_TXAGC_MCS04, power[16]) | 4199 SM(R92C_TXAGC_MCS05, power[17]) | 4200 SM(R92C_TXAGC_MCS06, power[18]) | 4201 SM(R92C_TXAGC_MCS07, power[19])); 4202 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4203 SM(R92C_TXAGC_MCS08, power[20]) | 4204 SM(R92C_TXAGC_MCS09, power[21]) | 4205 SM(R92C_TXAGC_MCS10, power[22]) | 4206 SM(R92C_TXAGC_MCS11, power[23])); 4207 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4208 SM(R92C_TXAGC_MCS12, power[24]) | 4209 SM(R92C_TXAGC_MCS13, power[25]) | 4210 SM(R92C_TXAGC_MCS14, power[26]) | 4211 SM(R92C_TXAGC_MCS15, power[27])); 4212 } 4213 4214 static void 4215 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4216 uint16_t power[URTWN_RIDX_COUNT]) 4217 { 4218 struct r92c_rom *rom = &sc->rom; 4219 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4220 const struct rtwn_txpwr *base; 4221 int ridx, group; 4222 4223 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4224 device_xname(sc->sc_dev), __func__, chain, chan)); 4225 4226 /* Determine channel group. */ 4227 if (chan <= 3) { 4228 group = 0; 4229 } else if (chan <= 9) { 4230 group = 1; 4231 } else { 4232 group = 2; 4233 } 4234 4235 /* Get original Tx power based on board type and RF chain. */ 4236 if (!(sc->chip & URTWN_CHIP_92C)) { 4237 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4238 base = &rtl8188ru_txagc[chain]; 4239 } else { 4240 base = &rtl8192cu_txagc[chain]; 4241 } 4242 } else { 4243 base = &rtl8192cu_txagc[chain]; 4244 } 4245 4246 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4247 if (sc->regulatory == 0) { 4248 for (ridx = 0; ridx <= 3; ridx++) { 4249 power[ridx] = base->pwr[0][ridx]; 4250 } 4251 } 4252 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4253 if (sc->regulatory == 3) { 4254 power[ridx] = base->pwr[0][ridx]; 4255 /* Apply vendor limits. */ 4256 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4257 maxpow = rom->ht40_max_pwr[group]; 4258 } else { 4259 maxpow = rom->ht20_max_pwr[group]; 4260 } 4261 maxpow = (maxpow >> (chain * 4)) & 0xf; 4262 if (power[ridx] > maxpow) { 4263 power[ridx] = maxpow; 4264 } 4265 } else if (sc->regulatory == 1) { 4266 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4267 power[ridx] = base->pwr[group][ridx]; 4268 } 4269 } else if (sc->regulatory != 2) { 4270 power[ridx] = base->pwr[0][ridx]; 4271 } 4272 } 4273 4274 /* Compute per-CCK rate Tx power. */ 4275 cckpow = rom->cck_tx_pwr[chain][group]; 4276 for (ridx = 0; ridx <= 3; ridx++) { 4277 power[ridx] += cckpow; 4278 if (power[ridx] > R92C_MAX_TX_PWR) { 4279 power[ridx] = R92C_MAX_TX_PWR; 4280 } 4281 } 4282 4283 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4284 if (sc->ntxchains > 1) { 4285 /* Apply reduction for 2 spatial streams. */ 4286 diff = rom->ht40_2s_tx_pwr_diff[group]; 4287 diff = (diff >> (chain * 4)) & 0xf; 4288 htpow = (htpow > diff) ? htpow - diff : 0; 4289 } 4290 4291 /* Compute per-OFDM rate Tx power. */ 4292 diff = rom->ofdm_tx_pwr_diff[group]; 4293 diff = (diff >> (chain * 4)) & 0xf; 4294 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4295 for (ridx = 4; ridx <= 11; ridx++) { 4296 power[ridx] += ofdmpow; 4297 if (power[ridx] > R92C_MAX_TX_PWR) { 4298 power[ridx] = R92C_MAX_TX_PWR; 4299 } 4300 } 4301 4302 /* Compute per-MCS Tx power. */ 4303 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4304 diff = rom->ht20_tx_pwr_diff[group]; 4305 diff = (diff >> (chain * 4)) & 0xf; 4306 htpow += diff; /* HT40->HT20 correction. */ 4307 } 4308 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4309 power[ridx] += htpow; 4310 if (power[ridx] > R92C_MAX_TX_PWR) { 4311 power[ridx] = R92C_MAX_TX_PWR; 4312 } 4313 } 4314 #ifdef URTWN_DEBUG 4315 if (urtwn_debug & DBG_RF) { 4316 /* Dump per-rate Tx power values. */ 4317 printf("%s: %s: Tx power for chain %zd:\n", 4318 device_xname(sc->sc_dev), __func__, chain); 4319 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4320 printf("%s: %s: Rate %d = %u\n", 4321 device_xname(sc->sc_dev), __func__, ridx, 4322 power[ridx]); 4323 } 4324 } 4325 #endif 4326 } 4327 4328 void 4329 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4330 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4331 { 4332 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4333 const struct rtwn_r88e_txpwr *base; 4334 int ridx, group; 4335 4336 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4337 device_xname(sc->sc_dev), __func__, chain, chan)); 4338 4339 /* Determine channel group. */ 4340 if (chan <= 2) 4341 group = 0; 4342 else if (chan <= 5) 4343 group = 1; 4344 else if (chan <= 8) 4345 group = 2; 4346 else if (chan <= 11) 4347 group = 3; 4348 else if (chan <= 13) 4349 group = 4; 4350 else 4351 group = 5; 4352 4353 /* Get original Tx power based on board type and RF chain. */ 4354 base = &rtl8188eu_txagc[chain]; 4355 4356 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4357 if (sc->regulatory == 0) { 4358 for (ridx = 0; ridx <= 3; ridx++) 4359 power[ridx] = base->pwr[0][ridx]; 4360 } 4361 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4362 if (sc->regulatory == 3) 4363 power[ridx] = base->pwr[0][ridx]; 4364 else if (sc->regulatory == 1) { 4365 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4366 power[ridx] = base->pwr[group][ridx]; 4367 } else if (sc->regulatory != 2) 4368 power[ridx] = base->pwr[0][ridx]; 4369 } 4370 4371 /* Compute per-CCK rate Tx power. */ 4372 cckpow = sc->cck_tx_pwr[group]; 4373 for (ridx = 0; ridx <= 3; ridx++) { 4374 power[ridx] += cckpow; 4375 if (power[ridx] > R92C_MAX_TX_PWR) 4376 power[ridx] = R92C_MAX_TX_PWR; 4377 } 4378 4379 htpow = sc->ht40_tx_pwr[group]; 4380 4381 /* Compute per-OFDM rate Tx power. */ 4382 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4383 for (ridx = 4; ridx <= 11; ridx++) { 4384 power[ridx] += ofdmpow; 4385 if (power[ridx] > R92C_MAX_TX_PWR) 4386 power[ridx] = R92C_MAX_TX_PWR; 4387 } 4388 4389 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4390 for (ridx = 12; ridx <= 27; ridx++) { 4391 power[ridx] += bw20pow; 4392 if (power[ridx] > R92C_MAX_TX_PWR) 4393 power[ridx] = R92C_MAX_TX_PWR; 4394 } 4395 } 4396 4397 static void 4398 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4399 { 4400 uint16_t power[URTWN_RIDX_COUNT]; 4401 size_t i; 4402 4403 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4404 4405 for (i = 0; i < sc->ntxchains; i++) { 4406 /* Compute per-rate Tx power values. */ 4407 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4408 ISSET(sc->chip, URTWN_CHIP_92EU)) 4409 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4410 else 4411 urtwn_get_txpower(sc, i, chan, ht40m, power); 4412 /* Write per-rate Tx power values to hardware. */ 4413 urtwn_write_txpower(sc, i, power); 4414 } 4415 } 4416 4417 static void 4418 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4419 { 4420 struct ieee80211com *ic = &sc->sc_ic; 4421 u_int chan; 4422 size_t i; 4423 4424 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4425 4426 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4427 __func__, chan)); 4428 4429 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4430 4431 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4432 chan += 2; 4433 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4434 chan -= 2; 4435 } 4436 4437 /* Set Tx power for this new channel. */ 4438 urtwn_set_txpower(sc, chan, ht40m); 4439 4440 for (i = 0; i < sc->nrxchains; i++) { 4441 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4442 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4443 } 4444 4445 if (ht40m) { 4446 /* Is secondary channel below or above primary? */ 4447 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4448 uint32_t reg; 4449 4450 urtwn_write_1(sc, R92C_BWOPMODE, 4451 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4452 4453 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4454 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4455 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4456 4457 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4458 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4459 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4460 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4461 4462 /* Set CCK side band. */ 4463 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4464 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4465 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4466 4467 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4468 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4469 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4470 4471 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4472 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4473 ~R92C_FPGA0_ANAPARAM2_CBW20); 4474 4475 reg = urtwn_bb_read(sc, 0x818); 4476 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4477 urtwn_bb_write(sc, 0x818, reg); 4478 4479 /* Select 40MHz bandwidth. */ 4480 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4481 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4482 } else { 4483 urtwn_write_1(sc, R92C_BWOPMODE, 4484 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4485 4486 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4487 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4488 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4489 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4490 4491 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4492 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4493 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4494 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4495 R92C_FPGA0_ANAPARAM2_CBW20); 4496 } 4497 4498 /* Select 20MHz bandwidth. */ 4499 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4500 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4501 (ISSET(sc->chip, URTWN_CHIP_88E) || 4502 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4503 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4504 } 4505 } 4506 4507 static void 4508 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4509 { 4510 4511 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4512 __func__, inited)); 4513 4514 uint32_t addaBackup[16], iqkBackup[4], piMode; 4515 4516 #ifdef notyet 4517 uint32_t odfm0_agccore_regs[3]; 4518 uint32_t ant_regs[3]; 4519 uint32_t rf_regs[8]; 4520 #endif 4521 uint32_t reg0, reg1, reg2; 4522 int i, attempt; 4523 4524 #ifdef notyet 4525 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4526 R92E_STBC_SETTING + 2)); 4527 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4528 /* Save AGCCORE regs. */ 4529 for (i = 0; i < sc->nrxchains; i++) { 4530 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4531 R92C_OFDM0_AGCCORE1(i)); 4532 } 4533 #endif 4534 /* Save BB regs. */ 4535 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4536 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4537 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4538 4539 /* Save adda regs to be restored when finished. */ 4540 for (i = 0; i < __arraycount(addaReg); i++) 4541 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4542 /* Save mac regs. */ 4543 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4544 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4545 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4546 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4547 4548 #ifdef notyet 4549 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4550 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4551 4552 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4553 for (i = 0; i < sc->nrxchains; i++) 4554 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4555 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4556 #endif 4557 4558 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4559 R92C_HSSI_PARAM1_PI); 4560 if (piMode == 0) { 4561 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4562 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4563 R92C_HSSI_PARAM1_PI); 4564 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4565 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4566 R92C_HSSI_PARAM1_PI); 4567 } 4568 4569 attempt = 1; 4570 4571 next_attempt: 4572 4573 /* Set mac regs for calibration. */ 4574 for (i = 0; i < __arraycount(addaReg); i++) { 4575 urtwn_bb_write(sc, addaReg[i], 4576 addaReg[__arraycount(addaReg) - 1]); 4577 } 4578 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4579 R92C_CCK0_AFESETTING)); 4580 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4581 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4582 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4583 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4584 4585 if (sc->ntxchains > 1) 4586 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4587 4588 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4589 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4590 ~R92C_BCN_CTRL_EN_BCN)); 4591 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4592 ~R92C_BCN_CTRL_EN_BCN)); 4593 4594 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4595 ~R92C_GPIO_MUXCFG_ENBT)); 4596 4597 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4598 4599 if (sc->ntxchains > 1) 4600 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4601 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4602 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4603 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4604 4605 /* Restore BB regs. */ 4606 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4607 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4608 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4609 4610 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4611 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4612 if (sc->nrxchains > 1) 4613 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4614 4615 if (attempt-- > 0) 4616 goto next_attempt; 4617 4618 /* Restore mode. */ 4619 if (piMode == 0) { 4620 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4621 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4622 ~R92C_HSSI_PARAM1_PI); 4623 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4624 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4625 ~R92C_HSSI_PARAM1_PI); 4626 } 4627 4628 #ifdef notyet 4629 for (i = 0; i < sc->nrxchains; i++) { 4630 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4631 odfm0_agccore_regs[i]); 4632 } 4633 #endif 4634 4635 /* Restore adda regs. */ 4636 for (i = 0; i < __arraycount(addaReg); i++) 4637 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4638 /* Restore mac regs. */ 4639 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4640 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4641 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4642 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4643 4644 #ifdef notyet 4645 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4646 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4647 4648 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4649 for (i = 0; i < sc->nrxchains; i++) 4650 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4651 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4652 #endif 4653 } 4654 4655 static void 4656 urtwn_lc_calib(struct urtwn_softc *sc) 4657 { 4658 uint32_t rf_ac[2]; 4659 uint8_t txmode; 4660 size_t i; 4661 4662 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4663 4664 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4665 4666 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4667 if ((txmode & 0x70) != 0) { 4668 /* Disable all continuous Tx. */ 4669 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4670 4671 /* Set RF mode to standby mode. */ 4672 for (i = 0; i < sc->nrxchains; i++) { 4673 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4674 urtwn_rf_write(sc, i, R92C_RF_AC, 4675 RW(rf_ac[i], R92C_RF_AC_MODE, 4676 R92C_RF_AC_MODE_STANDBY)); 4677 } 4678 } else { 4679 /* Block all Tx queues. */ 4680 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4681 } 4682 /* Start calibration. */ 4683 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4684 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4685 4686 /* Give calibration the time to complete. */ 4687 urtwn_delay_ms(sc, 100); 4688 4689 /* Restore configuration. */ 4690 if ((txmode & 0x70) != 0) { 4691 /* Restore Tx mode. */ 4692 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4693 /* Restore RF mode. */ 4694 for (i = 0; i < sc->nrxchains; i++) { 4695 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4696 } 4697 } else { 4698 /* Unblock all Tx queues. */ 4699 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4700 } 4701 } 4702 4703 static void 4704 urtwn_temp_calib(struct urtwn_softc *sc) 4705 { 4706 int temp, t_meter_reg; 4707 4708 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4709 4710 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4711 4712 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4713 t_meter_reg = R92C_RF_T_METER; 4714 else 4715 t_meter_reg = R92E_RF_T_METER; 4716 4717 if (sc->thcal_state == 0) { 4718 /* Start measuring temperature. */ 4719 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4720 device_xname(sc->sc_dev), __func__)); 4721 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4722 sc->thcal_state = 1; 4723 return; 4724 } 4725 sc->thcal_state = 0; 4726 4727 /* Read measured temperature. */ 4728 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4729 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4730 __func__, temp)); 4731 if (temp == 0) /* Read failed, skip. */ 4732 return; 4733 4734 /* 4735 * Redo LC calibration if temperature changed significantly since 4736 * last calibration. 4737 */ 4738 if (sc->thcal_lctemp == 0) { 4739 /* First LC calibration is performed in urtwn_init(). */ 4740 sc->thcal_lctemp = temp; 4741 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4742 DPRINTFN(DBG_RF, 4743 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4744 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4745 temp)); 4746 urtwn_lc_calib(sc); 4747 /* Record temperature of last LC calibration. */ 4748 sc->thcal_lctemp = temp; 4749 } 4750 } 4751 4752 static int 4753 urtwn_init(struct ifnet *ifp) 4754 { 4755 struct urtwn_softc *sc = ifp->if_softc; 4756 struct ieee80211com *ic = &sc->sc_ic; 4757 struct urtwn_rx_data *data; 4758 uint32_t reg; 4759 size_t i; 4760 int error; 4761 4762 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4763 4764 urtwn_stop(ifp, 0); 4765 4766 mutex_enter(&sc->sc_write_mtx); 4767 4768 mutex_enter(&sc->sc_task_mtx); 4769 /* Init host async commands ring. */ 4770 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4771 mutex_exit(&sc->sc_task_mtx); 4772 4773 mutex_enter(&sc->sc_fwcmd_mtx); 4774 /* Init firmware commands ring. */ 4775 sc->fwcur = 0; 4776 mutex_exit(&sc->sc_fwcmd_mtx); 4777 4778 /* Allocate Tx/Rx buffers. */ 4779 error = urtwn_alloc_rx_list(sc); 4780 if (error != 0) { 4781 aprint_error_dev(sc->sc_dev, 4782 "could not allocate Rx buffers\n"); 4783 goto fail; 4784 } 4785 error = urtwn_alloc_tx_list(sc); 4786 if (error != 0) { 4787 aprint_error_dev(sc->sc_dev, 4788 "could not allocate Tx buffers\n"); 4789 goto fail; 4790 } 4791 4792 /* Power on adapter. */ 4793 error = urtwn_power_on(sc); 4794 if (error != 0) 4795 goto fail; 4796 4797 /* Initialize DMA. */ 4798 error = urtwn_dma_init(sc); 4799 if (error != 0) 4800 goto fail; 4801 4802 /* Set info size in Rx descriptors (in 64-bit words). */ 4803 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4804 4805 /* Init interrupts. */ 4806 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4807 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4808 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4809 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4810 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4811 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4812 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4813 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4814 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4815 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4816 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4817 } 4818 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4819 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4820 } else { 4821 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4822 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4823 } 4824 4825 /* Set MAC address. */ 4826 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4827 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4828 4829 /* Set initial network type. */ 4830 reg = urtwn_read_4(sc, R92C_CR); 4831 switch (ic->ic_opmode) { 4832 case IEEE80211_M_STA: 4833 default: 4834 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4835 break; 4836 4837 case IEEE80211_M_IBSS: 4838 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4839 break; 4840 } 4841 urtwn_write_4(sc, R92C_CR, reg); 4842 4843 /* Set response rate */ 4844 reg = urtwn_read_4(sc, R92C_RRSR); 4845 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4846 urtwn_write_4(sc, R92C_RRSR, reg); 4847 4848 /* SIFS (used in NAV) */ 4849 urtwn_write_2(sc, R92C_SPEC_SIFS, 4850 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4851 4852 /* Set short/long retry limits. */ 4853 urtwn_write_2(sc, R92C_RL, 4854 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4855 4856 /* Initialize EDCA parameters. */ 4857 urtwn_edca_init(sc); 4858 4859 /* Setup rate fallback. */ 4860 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4861 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4862 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4863 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4864 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4865 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4866 } 4867 4868 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4869 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4870 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4871 /* Set ACK timeout. */ 4872 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4873 4874 /* Setup USB aggregation. */ 4875 /* Tx */ 4876 reg = urtwn_read_4(sc, R92C_TDECTRL); 4877 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4878 urtwn_write_4(sc, R92C_TDECTRL, reg); 4879 /* Rx */ 4880 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4881 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4882 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4883 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4884 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4885 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4886 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4887 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4888 ISSET(sc->chip, URTWN_CHIP_92EU)) 4889 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4890 else 4891 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4892 4893 /* Initialize beacon parameters. */ 4894 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4895 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4896 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4897 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4898 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4899 4900 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4901 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4902 /* Setup AMPDU aggregation. */ 4903 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4904 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4905 urtwn_write_2(sc, 0x4ca, 0x0708); 4906 4907 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4908 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4909 } 4910 4911 /* Load 8051 microcode. */ 4912 error = urtwn_load_firmware(sc); 4913 if (error != 0) 4914 goto fail; 4915 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4916 4917 /* Initialize MAC/BB/RF blocks. */ 4918 /* 4919 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4920 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4921 * XXX: This setting should be removed from rtl8192cu_mac[]. 4922 */ 4923 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4924 urtwn_rxfilter_init(sc); // reset R92C_RCR 4925 urtwn_bb_init(sc); 4926 urtwn_rf_init(sc); 4927 4928 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4929 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4930 urtwn_write_2(sc, R92C_CR, 4931 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4932 R92C_CR_MACRXEN); 4933 } 4934 4935 /* Turn CCK and OFDM blocks on. */ 4936 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4937 reg |= R92C_RFMOD_CCK_EN; 4938 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4939 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4940 reg |= R92C_RFMOD_OFDM_EN; 4941 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4942 4943 /* Clear per-station keys table. */ 4944 urtwn_cam_init(sc); 4945 4946 /* Enable hardware sequence numbering. */ 4947 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4948 4949 /* Perform LO and IQ calibrations. */ 4950 urtwn_iq_calib(sc, sc->iqk_inited); 4951 sc->iqk_inited = true; 4952 4953 /* Perform LC calibration. */ 4954 urtwn_lc_calib(sc); 4955 4956 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4957 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4958 /* Fix USB interference issue. */ 4959 urtwn_write_1(sc, 0xfe40, 0xe0); 4960 urtwn_write_1(sc, 0xfe41, 0x8d); 4961 urtwn_write_1(sc, 0xfe42, 0x80); 4962 urtwn_write_4(sc, 0x20c, 0xfd0320); 4963 4964 urtwn_pa_bias_init(sc); 4965 } 4966 4967 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4968 !(sc->chip & URTWN_CHIP_92EU)) { 4969 /* 1T1R */ 4970 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4971 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4972 } 4973 4974 /* Initialize GPIO setting. */ 4975 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4976 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4977 4978 /* Fix for lower temperature. */ 4979 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4980 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4981 urtwn_write_1(sc, 0x15, 0xe9); 4982 4983 /* Set default channel. */ 4984 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4985 4986 /* Queue Rx xfers. */ 4987 for (size_t j = 0; j < sc->rx_npipe; j++) { 4988 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4989 data = &sc->rx_data[j][i]; 4990 usbd_setup_xfer(data->xfer, data, data->buf, 4991 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4992 urtwn_rxeof); 4993 error = usbd_transfer(data->xfer); 4994 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4995 error != USBD_IN_PROGRESS)) 4996 goto fail; 4997 } 4998 } 4999 5000 /* We're ready to go. */ 5001 ifp->if_flags &= ~IFF_OACTIVE; 5002 ifp->if_flags |= IFF_RUNNING; 5003 sc->sc_running = true; 5004 5005 mutex_exit(&sc->sc_write_mtx); 5006 5007 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5008 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5009 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5010 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5011 urtwn_wait_async(sc); 5012 5013 return 0; 5014 5015 fail: 5016 mutex_exit(&sc->sc_write_mtx); 5017 5018 urtwn_stop(ifp, 1); 5019 return error; 5020 } 5021 5022 static void 5023 urtwn_stop(struct ifnet *ifp, int disable) 5024 { 5025 struct urtwn_softc *sc = ifp->if_softc; 5026 struct ieee80211com *ic = &sc->sc_ic; 5027 size_t i; 5028 int s; 5029 5030 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5031 5032 s = splusb(); 5033 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5034 urtwn_wait_async(sc); 5035 splx(s); 5036 5037 sc->tx_timer = 0; 5038 ifp->if_timer = 0; 5039 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5040 5041 callout_stop(&sc->sc_scan_to); 5042 callout_stop(&sc->sc_calib_to); 5043 5044 /* Abort Tx. */ 5045 for (i = 0; i < sc->tx_npipe; i++) { 5046 if (sc->tx_pipe[i] != NULL) 5047 usbd_abort_pipe(sc->tx_pipe[i]); 5048 } 5049 5050 /* Stop Rx pipe. */ 5051 for (i = 0; i < sc->rx_npipe; i++) { 5052 if (sc->rx_pipe[i] != NULL) 5053 usbd_abort_pipe(sc->rx_pipe[i]); 5054 } 5055 5056 /* Free Tx/Rx buffers. */ 5057 urtwn_free_tx_list(sc); 5058 urtwn_free_rx_list(sc); 5059 5060 sc->sc_running = false; 5061 if (disable) 5062 urtwn_chip_stop(sc); 5063 } 5064 5065 static int 5066 urtwn_reset(struct ifnet *ifp) 5067 { 5068 struct urtwn_softc *sc = ifp->if_softc; 5069 struct ieee80211com *ic = &sc->sc_ic; 5070 5071 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5072 return ENETRESET; 5073 5074 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5075 5076 return 0; 5077 } 5078 5079 static void 5080 urtwn_chip_stop(struct urtwn_softc *sc) 5081 { 5082 uint32_t reg; 5083 bool disabled = true; 5084 5085 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5086 5087 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5088 ISSET(sc->chip, URTWN_CHIP_92EU)) 5089 return; 5090 5091 mutex_enter(&sc->sc_write_mtx); 5092 5093 /* 5094 * RF Off Sequence 5095 */ 5096 /* Pause MAC TX queue */ 5097 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5098 5099 /* Disable RF */ 5100 urtwn_rf_write(sc, 0, 0, 0); 5101 5102 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5103 5104 /* Reset BB state machine */ 5105 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5106 R92C_SYS_FUNC_EN_USBD | 5107 R92C_SYS_FUNC_EN_USBA | 5108 R92C_SYS_FUNC_EN_BB_GLB_RST); 5109 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5110 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5111 5112 /* 5113 * Reset digital sequence 5114 */ 5115 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5116 /* Reset MCU ready status */ 5117 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5118 /* If firmware in ram code, do reset */ 5119 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5120 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5121 ISSET(sc->chip, URTWN_CHIP_92EU)) 5122 urtwn_r88e_fw_reset(sc); 5123 else 5124 urtwn_fw_reset(sc); 5125 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5126 } 5127 } 5128 5129 /* Reset MAC and Enable 8051 */ 5130 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5131 5132 /* Reset MCU ready status */ 5133 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5134 5135 if (disabled) { 5136 /* Disable MAC clock */ 5137 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5138 /* Disable AFE PLL */ 5139 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5140 /* Gated AFE DIG_CLOCK */ 5141 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5142 /* Isolated digital to PON */ 5143 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5144 } 5145 5146 /* 5147 * Pull GPIO PIN to balance level and LED control 5148 */ 5149 /* 1. Disable GPIO[7:0] */ 5150 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5151 5152 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5153 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5154 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5155 5156 /* Disable GPIO[10:8] */ 5157 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5158 5159 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5160 reg |= (((reg & 0x000f) << 4) | 0x0780); 5161 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5162 5163 /* Disable LED0 & 1 */ 5164 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5165 5166 /* 5167 * Reset digital sequence 5168 */ 5169 if (disabled) { 5170 /* Disable ELDR clock */ 5171 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5172 /* Isolated ELDR to PON */ 5173 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5174 } 5175 5176 /* 5177 * Disable analog sequence 5178 */ 5179 if (disabled) { 5180 /* Disable A15 power */ 5181 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5182 /* Disable digital core power */ 5183 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5184 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5185 ~R92C_LDOV12D_CTRL_LDV12_EN); 5186 } 5187 5188 /* Enter PFM mode */ 5189 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5190 5191 /* Set USB suspend */ 5192 urtwn_write_2(sc, R92C_APS_FSMCO, 5193 R92C_APS_FSMCO_APDM_HOST | 5194 R92C_APS_FSMCO_AFSM_HSUS | 5195 R92C_APS_FSMCO_PFM_ALDN); 5196 5197 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5198 5199 mutex_exit(&sc->sc_write_mtx); 5200 } 5201 5202 static void 5203 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5204 { 5205 if (sc->sc_running == false) 5206 DELAY(ms * 1000); 5207 else 5208 usbd_delay_ms(sc->sc_udev, ms); 5209 } 5210 5211 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5212 5213 #ifdef _MODULE 5214 #include "ioconf.c" 5215 #endif 5216 5217 static int 5218 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5219 { 5220 int error = 0; 5221 5222 switch (cmd) { 5223 case MODULE_CMD_INIT: 5224 #ifdef _MODULE 5225 error = config_init_component(cfdriver_ioconf_urtwn, 5226 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5227 #endif 5228 return error; 5229 case MODULE_CMD_FINI: 5230 #ifdef _MODULE 5231 error = config_fini_component(cfdriver_ioconf_urtwn, 5232 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5233 #endif 5234 return error; 5235 default: 5236 return ENOTTY; 5237 } 5238 } 5239
Indexes created Thu Oct 02 14:10:14 GMT 2025