if_urtwn.c revision 1.78
1 /* $NetBSD: if_urtwn.c,v 1.78 2019/12/13 14:10:32 maxv Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.78 2019/12/13 14:10:32 maxv Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 216 /* URTWN_RTL8192EU */ 217 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 218 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 219 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 220 }; 221 #undef URTWN_DEV 222 #undef URTWN_RTL8188E_DEV 223 #undef URTWN_RTL8192EU_DEV 224 225 static int urtwn_match(device_t, cfdata_t, void *); 226 static void urtwn_attach(device_t, device_t, void *); 227 static int urtwn_detach(device_t, int); 228 static int urtwn_activate(device_t, enum devact); 229 230 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 231 urtwn_attach, urtwn_detach, urtwn_activate); 232 233 static int urtwn_open_pipes(struct urtwn_softc *); 234 static void urtwn_close_pipes(struct urtwn_softc *); 235 static int urtwn_alloc_rx_list(struct urtwn_softc *); 236 static void urtwn_free_rx_list(struct urtwn_softc *); 237 static int urtwn_alloc_tx_list(struct urtwn_softc *); 238 static void urtwn_free_tx_list(struct urtwn_softc *); 239 static void urtwn_task(void *); 240 static void urtwn_do_async(struct urtwn_softc *, 241 void (*)(struct urtwn_softc *, void *), void *, int); 242 static void urtwn_wait_async(struct urtwn_softc *); 243 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 244 int); 245 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 246 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 247 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 248 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 249 int); 250 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 251 int); 252 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 253 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 254 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 255 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 256 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 257 uint32_t); 258 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 259 uint32_t); 260 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 261 uint32_t); 262 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 263 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 264 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 265 static void urtwn_efuse_read(struct urtwn_softc *); 266 static void urtwn_efuse_switch_power(struct urtwn_softc *); 267 static int urtwn_read_chipid(struct urtwn_softc *); 268 #ifdef URTWN_DEBUG 269 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 270 #endif 271 static void urtwn_read_rom(struct urtwn_softc *); 272 static void urtwn_r88e_read_rom(struct urtwn_softc *); 273 static int urtwn_media_change(struct ifnet *); 274 static int urtwn_ra_init(struct urtwn_softc *); 275 static int urtwn_get_nettype(struct urtwn_softc *); 276 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 277 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 278 static void urtwn_set_led(struct urtwn_softc *, int, int); 279 static void urtwn_calib_to(void *); 280 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 281 static void urtwn_next_scan(void *); 282 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 283 int); 284 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 285 static int urtwn_wme_update(struct ieee80211com *); 286 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 287 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 288 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 289 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 290 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 291 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 292 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 293 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 294 struct ieee80211_node *, struct urtwn_tx_data *); 295 static struct urtwn_tx_data * 296 urtwn_get_tx_data(struct urtwn_softc *, size_t); 297 static void urtwn_start(struct ifnet *); 298 static void urtwn_watchdog(struct ifnet *); 299 static int urtwn_ioctl(struct ifnet *, u_long, void *); 300 static int urtwn_r92c_power_on(struct urtwn_softc *); 301 static int urtwn_r92e_power_on(struct urtwn_softc *); 302 static int urtwn_r88e_power_on(struct urtwn_softc *); 303 static int urtwn_llt_init(struct urtwn_softc *); 304 static void urtwn_fw_reset(struct urtwn_softc *); 305 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 306 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 307 static int urtwn_load_firmware(struct urtwn_softc *); 308 static int urtwn_r92c_dma_init(struct urtwn_softc *); 309 static int urtwn_r88e_dma_init(struct urtwn_softc *); 310 static void urtwn_mac_init(struct urtwn_softc *); 311 static void urtwn_bb_init(struct urtwn_softc *); 312 static void urtwn_rf_init(struct urtwn_softc *); 313 static void urtwn_cam_init(struct urtwn_softc *); 314 static void urtwn_pa_bias_init(struct urtwn_softc *); 315 static void urtwn_rxfilter_init(struct urtwn_softc *); 316 static void urtwn_edca_init(struct urtwn_softc *); 317 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 318 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 319 uint16_t[]); 320 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 321 u_int, uint16_t[]); 322 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 323 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 324 u_int); 325 static void urtwn_iq_calib(struct urtwn_softc *, bool); 326 static void urtwn_lc_calib(struct urtwn_softc *); 327 static void urtwn_temp_calib(struct urtwn_softc *); 328 static int urtwn_init(struct ifnet *); 329 static void urtwn_stop(struct ifnet *, int); 330 static int urtwn_reset(struct ifnet *); 331 static void urtwn_chip_stop(struct urtwn_softc *); 332 static void urtwn_newassoc(struct ieee80211_node *, int); 333 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 334 335 /* Aliases. */ 336 #define urtwn_bb_write urtwn_write_4 337 #define urtwn_bb_read urtwn_read_4 338 339 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 340 341 static const uint16_t addaReg[] = { 342 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 343 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 344 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 345 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 346 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 347 }; 348 349 static int 350 urtwn_match(device_t parent, cfdata_t match, void *aux) 351 { 352 struct usb_attach_arg *uaa = aux; 353 354 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 355 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 356 } 357 358 static void 359 urtwn_attach(device_t parent, device_t self, void *aux) 360 { 361 struct urtwn_softc *sc = device_private(self); 362 struct ieee80211com *ic = &sc->sc_ic; 363 struct ifnet *ifp = &sc->sc_if; 364 struct usb_attach_arg *uaa = aux; 365 char *devinfop; 366 const struct urtwn_dev *dev; 367 usb_device_request_t req; 368 size_t i; 369 int error; 370 371 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 372 373 sc->sc_dev = self; 374 sc->sc_udev = uaa->uaa_device; 375 376 sc->chip = 0; 377 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 378 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 379 SET(sc->chip, URTWN_CHIP_88E); 380 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 381 SET(sc->chip, URTWN_CHIP_92EU); 382 383 aprint_naive("\n"); 384 aprint_normal("\n"); 385 386 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 387 aprint_normal_dev(self, "%s\n", devinfop); 388 usbd_devinfo_free(devinfop); 389 390 req.bmRequestType = UT_WRITE_DEVICE; 391 req.bRequest = UR_SET_FEATURE; 392 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 393 USETW(req.wIndex, UHF_PORT_SUSPEND); 394 USETW(req.wLength, 0); 395 396 (void) usbd_do_request(sc->sc_udev, &req, 0); 397 398 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 399 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 400 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 401 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 402 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 403 404 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 405 406 callout_init(&sc->sc_scan_to, 0); 407 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 408 callout_init(&sc->sc_calib_to, 0); 409 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 410 411 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 412 RND_TYPE_NET, RND_FLAG_DEFAULT); 413 414 error = usbd_set_config_no(sc->sc_udev, 1, 0); 415 if (error != 0) { 416 aprint_error_dev(self, "failed to set configuration" 417 ", err=%s\n", usbd_errstr(error)); 418 goto fail; 419 } 420 421 /* Get the first interface handle. */ 422 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 423 if (error != 0) { 424 aprint_error_dev(self, "could not get interface handle\n"); 425 goto fail; 426 } 427 428 error = urtwn_read_chipid(sc); 429 if (error != 0) { 430 aprint_error_dev(self, "unsupported test chip\n"); 431 goto fail; 432 } 433 434 /* Determine number of Tx/Rx chains. */ 435 if (sc->chip & URTWN_CHIP_92C) { 436 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 437 sc->nrxchains = 2; 438 } else if (sc->chip & URTWN_CHIP_92EU) { 439 sc->ntxchains = 2; 440 sc->nrxchains = 2; 441 } else { 442 sc->ntxchains = 1; 443 sc->nrxchains = 1; 444 } 445 446 if (ISSET(sc->chip, URTWN_CHIP_88E) || 447 ISSET(sc->chip, URTWN_CHIP_92EU)) 448 urtwn_r88e_read_rom(sc); 449 else 450 urtwn_read_rom(sc); 451 452 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 453 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 454 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 455 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 456 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 457 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 458 "8188CUS", sc->ntxchains, sc->nrxchains, 459 ether_sprintf(ic->ic_myaddr)); 460 461 error = urtwn_open_pipes(sc); 462 if (error != 0) { 463 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 464 goto fail; 465 } 466 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 467 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 468 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 469 470 /* 471 * Setup the 802.11 device. 472 */ 473 ic->ic_ifp = ifp; 474 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 475 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 476 ic->ic_state = IEEE80211_S_INIT; 477 478 /* Set device capabilities. */ 479 ic->ic_caps = 480 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 481 IEEE80211_C_IBSS | /* IBSS mode supported */ 482 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 483 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 484 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 485 IEEE80211_C_WME | /* 802.11e */ 486 IEEE80211_C_WPA; /* 802.11i */ 487 488 /* Set supported .11b and .11g rates. */ 489 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 490 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 491 492 /* Set supported .11b and .11g channels (1 through 14). */ 493 for (i = 1; i <= 14; i++) { 494 ic->ic_channels[i].ic_freq = 495 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 496 ic->ic_channels[i].ic_flags = 497 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 498 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 499 } 500 501 ifp->if_softc = sc; 502 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 503 ifp->if_init = urtwn_init; 504 ifp->if_ioctl = urtwn_ioctl; 505 ifp->if_start = urtwn_start; 506 ifp->if_watchdog = urtwn_watchdog; 507 IFQ_SET_READY(&ifp->if_snd); 508 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 509 510 if_initialize(ifp); 511 ieee80211_ifattach(ic); 512 513 /* override default methods */ 514 ic->ic_newassoc = urtwn_newassoc; 515 ic->ic_reset = urtwn_reset; 516 ic->ic_wme.wme_update = urtwn_wme_update; 517 518 /* Override state transition machine. */ 519 sc->sc_newstate = ic->ic_newstate; 520 ic->ic_newstate = urtwn_newstate; 521 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 522 523 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 524 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 525 &sc->sc_drvbpf); 526 527 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 528 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 529 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 530 531 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 532 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 533 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 534 535 ifp->if_percpuq = if_percpuq_create(ifp); 536 if_register(ifp); 537 538 ieee80211_announce(ic); 539 540 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 541 542 if (!pmf_device_register(self, NULL, NULL)) 543 aprint_error_dev(self, "couldn't establish power handler\n"); 544 545 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 546 return; 547 548 fail: 549 sc->sc_dying = 1; 550 aprint_error_dev(self, "attach failed\n"); 551 } 552 553 static int 554 urtwn_detach(device_t self, int flags) 555 { 556 struct urtwn_softc *sc = device_private(self); 557 struct ifnet *ifp = &sc->sc_if; 558 int s; 559 560 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 561 562 pmf_device_deregister(self); 563 564 s = splusb(); 565 566 sc->sc_dying = 1; 567 568 callout_halt(&sc->sc_scan_to, NULL); 569 callout_halt(&sc->sc_calib_to, NULL); 570 571 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 572 urtwn_stop(ifp, 0); 573 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 574 NULL); 575 576 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 577 bpf_detach(ifp); 578 ieee80211_ifdetach(&sc->sc_ic); 579 if_detach(ifp); 580 581 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 582 urtwn_close_pipes(sc); 583 } 584 585 splx(s); 586 587 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 588 589 rnd_detach_source(&sc->rnd_source); 590 591 callout_destroy(&sc->sc_scan_to); 592 callout_destroy(&sc->sc_calib_to); 593 594 mutex_destroy(&sc->sc_write_mtx); 595 mutex_destroy(&sc->sc_fwcmd_mtx); 596 mutex_destroy(&sc->sc_tx_mtx); 597 mutex_destroy(&sc->sc_rx_mtx); 598 mutex_destroy(&sc->sc_task_mtx); 599 600 return 0; 601 } 602 603 static int 604 urtwn_activate(device_t self, enum devact act) 605 { 606 struct urtwn_softc *sc = device_private(self); 607 608 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 609 610 switch (act) { 611 case DVACT_DEACTIVATE: 612 if_deactivate(sc->sc_ic.ic_ifp); 613 return 0; 614 default: 615 return EOPNOTSUPP; 616 } 617 } 618 619 static int 620 urtwn_open_pipes(struct urtwn_softc *sc) 621 { 622 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 623 static uint8_t epaddr[R92C_MAX_EPOUT]; 624 static uint8_t rxepaddr[R92C_MAX_EPIN]; 625 usb_interface_descriptor_t *id; 626 usb_endpoint_descriptor_t *ed; 627 size_t i, ntx = 0, nrx = 0; 628 int error; 629 630 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 631 632 /* Determine the number of bulk-out pipes. */ 633 id = usbd_get_interface_descriptor(sc->sc_iface); 634 for (i = 0; i < id->bNumEndpoints; i++) { 635 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 636 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 637 continue; 638 } 639 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 640 if (ntx < sizeof(epaddr)) 641 epaddr[ntx] = ed->bEndpointAddress; 642 ntx++; 643 } 644 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 645 if (nrx < sizeof(rxepaddr)) 646 rxepaddr[nrx] = ed->bEndpointAddress; 647 nrx++; 648 } 649 } 650 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 651 aprint_error_dev(sc->sc_dev, 652 "%zd: invalid number of Rx bulk pipes\n", nrx); 653 return EIO; 654 } 655 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 656 aprint_error_dev(sc->sc_dev, 657 "%zd: invalid number of Tx bulk pipes\n", ntx); 658 return EIO; 659 } 660 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 661 nrx, ntx, 0, 0); 662 sc->rx_npipe = nrx; 663 sc->tx_npipe = ntx; 664 665 /* Open bulk-in pipe at address 0x81. */ 666 for (i = 0; i < nrx; i++) { 667 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 668 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 669 if (error != 0) { 670 aprint_error_dev(sc->sc_dev, 671 "could not open Rx bulk pipe 0x%02x: %d\n", 672 rxepaddr[i], error); 673 goto fail; 674 } 675 } 676 677 /* Open bulk-out pipes (up to 3). */ 678 for (i = 0; i < ntx; i++) { 679 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 680 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 681 if (error != 0) { 682 aprint_error_dev(sc->sc_dev, 683 "could not open Tx bulk pipe 0x%02x: %d\n", 684 epaddr[i], error); 685 goto fail; 686 } 687 } 688 689 /* Map 802.11 access categories to USB pipes. */ 690 sc->ac2idx[WME_AC_BK] = 691 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 692 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 693 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 694 695 fail: 696 if (error != 0) 697 urtwn_close_pipes(sc); 698 return error; 699 } 700 701 static void 702 urtwn_close_pipes(struct urtwn_softc *sc) 703 { 704 struct usbd_pipe *pipe; 705 size_t i; 706 707 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 708 709 /* Close Rx pipes. */ 710 CTASSERT(sizeof(pipe) == sizeof(void *)); 711 for (i = 0; i < sc->rx_npipe; i++) { 712 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 713 if (pipe != NULL) { 714 usbd_close_pipe(pipe); 715 } 716 } 717 718 /* Close Tx pipes. */ 719 for (i = 0; i < sc->tx_npipe; i++) { 720 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 721 if (pipe != NULL) { 722 usbd_close_pipe(pipe); 723 } 724 } 725 } 726 727 static int 728 urtwn_alloc_rx_list(struct urtwn_softc *sc) 729 { 730 struct urtwn_rx_data *data; 731 size_t i; 732 int error = 0; 733 734 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 735 736 for (size_t j = 0; j < sc->rx_npipe; j++) { 737 TAILQ_INIT(&sc->rx_free_list[j]); 738 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 739 data = &sc->rx_data[j][i]; 740 741 data->sc = sc; /* Backpointer for callbacks. */ 742 743 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 744 0, 0, &data->xfer); 745 if (error) { 746 aprint_error_dev(sc->sc_dev, 747 "could not allocate xfer\n"); 748 break; 749 } 750 751 data->buf = usbd_get_buffer(data->xfer); 752 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 753 } 754 } 755 if (error != 0) 756 urtwn_free_rx_list(sc); 757 return error; 758 } 759 760 static void 761 urtwn_free_rx_list(struct urtwn_softc *sc) 762 { 763 struct usbd_xfer *xfer; 764 size_t i; 765 766 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 767 768 /* NB: Caller must abort pipe first. */ 769 for (size_t j = 0; j < sc->rx_npipe; j++) { 770 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 771 CTASSERT(sizeof(xfer) == sizeof(void *)); 772 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 773 if (xfer != NULL) 774 usbd_destroy_xfer(xfer); 775 } 776 } 777 } 778 779 static int 780 urtwn_alloc_tx_list(struct urtwn_softc *sc) 781 { 782 struct urtwn_tx_data *data; 783 size_t i; 784 int error = 0; 785 786 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 787 788 mutex_enter(&sc->sc_tx_mtx); 789 for (size_t j = 0; j < sc->tx_npipe; j++) { 790 TAILQ_INIT(&sc->tx_free_list[j]); 791 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 792 data = &sc->tx_data[j][i]; 793 794 data->sc = sc; /* Backpointer for callbacks. */ 795 data->pidx = j; 796 797 error = usbd_create_xfer(sc->tx_pipe[j], 798 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 799 &data->xfer); 800 if (error) { 801 aprint_error_dev(sc->sc_dev, 802 "could not allocate xfer\n"); 803 goto fail; 804 } 805 806 data->buf = usbd_get_buffer(data->xfer); 807 808 /* Append this Tx buffer to our free list. */ 809 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 810 } 811 } 812 mutex_exit(&sc->sc_tx_mtx); 813 return 0; 814 815 fail: 816 urtwn_free_tx_list(sc); 817 mutex_exit(&sc->sc_tx_mtx); 818 return error; 819 } 820 821 static void 822 urtwn_free_tx_list(struct urtwn_softc *sc) 823 { 824 struct usbd_xfer *xfer; 825 size_t i; 826 827 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 828 829 /* NB: Caller must abort pipe first. */ 830 for (size_t j = 0; j < sc->tx_npipe; j++) { 831 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 832 CTASSERT(sizeof(xfer) == sizeof(void *)); 833 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 834 if (xfer != NULL) 835 usbd_destroy_xfer(xfer); 836 } 837 } 838 } 839 840 static int 841 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 842 struct ieee80211_node *ni) 843 { 844 struct urtwn_tx_data *data = 845 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 846 return urtwn_tx(sc, m, ni, data); 847 } 848 849 static void 850 urtwn_task(void *arg) 851 { 852 struct urtwn_softc *sc = arg; 853 struct ieee80211com *ic = &sc->sc_ic; 854 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 855 struct urtwn_host_cmd *cmd; 856 int s; 857 858 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 859 if (ic->ic_state == IEEE80211_S_RUN && 860 (ic->ic_opmode == IEEE80211_M_HOSTAP || 861 ic->ic_opmode == IEEE80211_M_IBSS)) { 862 863 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 864 &sc->sc_bo); 865 if (m == NULL) { 866 aprint_error_dev(sc->sc_dev, 867 "could not allocate beacon"); 868 } 869 870 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 871 aprint_error_dev(sc->sc_dev, "could not send beacon"); 872 } 873 874 /* beacon is no longer needed */ 875 m_freem(m); 876 } 877 878 /* Process host commands. */ 879 s = splusb(); 880 mutex_spin_enter(&sc->sc_task_mtx); 881 while (ring->next != ring->cur) { 882 cmd = &ring->cmd[ring->next]; 883 mutex_spin_exit(&sc->sc_task_mtx); 884 splx(s); 885 /* Invoke callback with kernel lock held. */ 886 cmd->cb(sc, cmd->data); 887 s = splusb(); 888 mutex_spin_enter(&sc->sc_task_mtx); 889 ring->queued--; 890 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 891 } 892 mutex_spin_exit(&sc->sc_task_mtx); 893 wakeup(&sc->cmdq); 894 splx(s); 895 } 896 897 static void 898 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 899 void *arg, int len) 900 { 901 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 902 struct urtwn_host_cmd *cmd; 903 int s; 904 905 URTWNHIST_FUNC(); 906 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 907 (uintptr_t)cb, (uintptr_t)arg, len, 0); 908 909 s = splusb(); 910 mutex_spin_enter(&sc->sc_task_mtx); 911 cmd = &ring->cmd[ring->cur]; 912 cmd->cb = cb; 913 KASSERT(len <= sizeof(cmd->data)); 914 memcpy(cmd->data, arg, len); 915 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 916 917 /* If there is no pending command already, schedule a task. */ 918 if (!sc->sc_dying && ++ring->queued == 1) { 919 mutex_spin_exit(&sc->sc_task_mtx); 920 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 921 } else 922 mutex_spin_exit(&sc->sc_task_mtx); 923 splx(s); 924 } 925 926 static void 927 urtwn_wait_async(struct urtwn_softc *sc) 928 { 929 930 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 931 932 /* Wait for all queued asynchronous commands to complete. */ 933 while (sc->cmdq.queued > 0) 934 tsleep(&sc->cmdq, 0, "endtask", 0); 935 } 936 937 static int 938 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 939 int len) 940 { 941 usb_device_request_t req; 942 usbd_status error; 943 944 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 945 KASSERT(mutex_owned(&sc->sc_write_mtx)); 946 947 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 948 req.bRequest = R92C_REQ_REGS; 949 USETW(req.wValue, addr); 950 USETW(req.wIndex, 0); 951 USETW(req.wLength, len); 952 error = usbd_do_request(sc->sc_udev, &req, buf); 953 if (error != USBD_NORMAL_COMPLETION) { 954 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 955 error, addr, len, 0); 956 } 957 return error; 958 } 959 960 static void 961 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 962 { 963 964 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 965 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 966 967 urtwn_write_region_1(sc, addr, &val, 1); 968 } 969 970 static void 971 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 972 { 973 uint8_t buf[2]; 974 975 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 976 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 977 978 buf[0] = (uint8_t)val; 979 buf[1] = (uint8_t)(val >> 8); 980 urtwn_write_region_1(sc, addr, buf, 2); 981 } 982 983 static void 984 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 985 { 986 uint8_t buf[4]; 987 988 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 989 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 990 991 buf[0] = (uint8_t)val; 992 buf[1] = (uint8_t)(val >> 8); 993 buf[2] = (uint8_t)(val >> 16); 994 buf[3] = (uint8_t)(val >> 24); 995 urtwn_write_region_1(sc, addr, buf, 4); 996 } 997 998 static int 999 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1000 { 1001 1002 URTWNHIST_FUNC(); 1003 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1004 1005 return urtwn_write_region_1(sc, addr, buf, len); 1006 } 1007 1008 static int 1009 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1010 int len) 1011 { 1012 usb_device_request_t req; 1013 usbd_status error; 1014 1015 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1016 1017 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1018 req.bRequest = R92C_REQ_REGS; 1019 USETW(req.wValue, addr); 1020 USETW(req.wIndex, 0); 1021 USETW(req.wLength, len); 1022 error = usbd_do_request(sc->sc_udev, &req, buf); 1023 if (error != USBD_NORMAL_COMPLETION) { 1024 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1025 error, addr, len, 0); 1026 } 1027 return error; 1028 } 1029 1030 static uint8_t 1031 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1032 { 1033 uint8_t val; 1034 1035 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1036 1037 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1038 return 0xff; 1039 1040 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1041 return val; 1042 } 1043 1044 static uint16_t 1045 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1046 { 1047 uint8_t buf[2]; 1048 uint16_t val; 1049 1050 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1051 1052 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1053 return 0xffff; 1054 1055 val = LE_READ_2(&buf[0]); 1056 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1057 return val; 1058 } 1059 1060 static uint32_t 1061 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1062 { 1063 uint8_t buf[4]; 1064 uint32_t val; 1065 1066 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1067 1068 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1069 return 0xffffffff; 1070 1071 val = LE_READ_4(&buf[0]); 1072 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1073 return val; 1074 } 1075 1076 static int 1077 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1078 { 1079 struct r92c_fw_cmd cmd; 1080 uint8_t *cp; 1081 int fwcur; 1082 int ntries; 1083 1084 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1085 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1086 1087 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1088 1089 mutex_enter(&sc->sc_fwcmd_mtx); 1090 fwcur = sc->fwcur; 1091 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1092 mutex_exit(&sc->sc_fwcmd_mtx); 1093 1094 /* Wait for current FW box to be empty. */ 1095 for (ntries = 0; ntries < 100; ntries++) { 1096 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1097 break; 1098 DELAY(2000); 1099 } 1100 if (ntries == 100) { 1101 aprint_error_dev(sc->sc_dev, 1102 "could not send firmware command %d\n", id); 1103 return ETIMEDOUT; 1104 } 1105 1106 memset(&cmd, 0, sizeof(cmd)); 1107 KASSERT(len <= sizeof(cmd.msg)); 1108 memcpy(cmd.msg, buf, len); 1109 1110 /* Write the first word last since that will trigger the FW. */ 1111 cp = (uint8_t *)&cmd; 1112 cmd.id = id; 1113 if (len >= 4) { 1114 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1115 cmd.id |= R92C_CMD_FLAG_EXT; 1116 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1117 &cp[1], 2); 1118 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1119 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1120 ((uint32_t)cp[5] << 24)); 1121 } else { 1122 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1123 &cp[4], 2); 1124 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1125 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1126 ((uint32_t)cp[3] << 24)); 1127 } 1128 } else { 1129 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1130 } 1131 1132 return 0; 1133 } 1134 1135 static __inline void 1136 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1137 { 1138 1139 sc->sc_rf_write(sc, chain, addr, val); 1140 } 1141 1142 static void 1143 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1144 uint32_t val) 1145 { 1146 1147 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1148 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1149 } 1150 1151 static void 1152 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1153 uint32_t val) 1154 { 1155 1156 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1157 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1158 } 1159 1160 static void 1161 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1162 uint32_t val) 1163 { 1164 1165 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1166 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1167 } 1168 1169 static uint32_t 1170 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1171 { 1172 uint32_t reg[R92C_MAX_CHAINS], val; 1173 1174 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1175 if (chain != 0) { 1176 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1177 } 1178 1179 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1180 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1181 DELAY(1000); 1182 1183 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1184 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1185 R92C_HSSI_PARAM2_READ_EDGE); 1186 DELAY(1000); 1187 1188 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1189 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1190 DELAY(1000); 1191 1192 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1193 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1194 } else { 1195 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1196 } 1197 return MS(val, R92C_LSSI_READBACK_DATA); 1198 } 1199 1200 static int 1201 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1202 { 1203 int ntries; 1204 1205 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1206 1207 urtwn_write_4(sc, R92C_LLT_INIT, 1208 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1209 SM(R92C_LLT_INIT_ADDR, addr) | 1210 SM(R92C_LLT_INIT_DATA, data)); 1211 /* Wait for write operation to complete. */ 1212 for (ntries = 0; ntries < 20; ntries++) { 1213 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1214 R92C_LLT_INIT_OP_NO_ACTIVE) { 1215 /* Done */ 1216 return 0; 1217 } 1218 DELAY(5); 1219 } 1220 return ETIMEDOUT; 1221 } 1222 1223 static uint8_t 1224 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1225 { 1226 uint32_t reg; 1227 int ntries; 1228 1229 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1230 1231 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1232 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1233 reg &= ~R92C_EFUSE_CTRL_VALID; 1234 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1235 1236 /* Wait for read operation to complete. */ 1237 for (ntries = 0; ntries < 100; ntries++) { 1238 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1239 if (reg & R92C_EFUSE_CTRL_VALID) { 1240 /* Done */ 1241 return MS(reg, R92C_EFUSE_CTRL_DATA); 1242 } 1243 DELAY(5); 1244 } 1245 aprint_error_dev(sc->sc_dev, 1246 "could not read efuse byte at address 0x%04x\n", addr); 1247 return 0xff; 1248 } 1249 1250 static void 1251 urtwn_efuse_read(struct urtwn_softc *sc) 1252 { 1253 uint8_t *rom = (uint8_t *)&sc->rom; 1254 uint32_t reg; 1255 uint16_t addr = 0; 1256 uint8_t off, msk; 1257 size_t i; 1258 1259 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1260 1261 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1262 1263 urtwn_efuse_switch_power(sc); 1264 1265 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1266 while (addr < 512) { 1267 reg = urtwn_efuse_read_1(sc, addr); 1268 if (reg == 0xff) 1269 break; 1270 addr++; 1271 off = reg >> 4; 1272 msk = reg & 0xf; 1273 for (i = 0; i < 4; i++) { 1274 if (msk & (1U << i)) 1275 continue; 1276 1277 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1278 addr++; 1279 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1280 addr++; 1281 } 1282 } 1283 #ifdef URTWN_DEBUG 1284 /* Dump ROM content. */ 1285 for (i = 0; i < (int)sizeof(sc->rom); i++) 1286 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1287 #endif 1288 } 1289 1290 static void 1291 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1292 { 1293 uint32_t reg; 1294 1295 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1296 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1297 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1298 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1299 } 1300 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1301 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1302 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1303 reg | R92C_SYS_FUNC_EN_ELDR); 1304 } 1305 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1306 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1307 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1308 urtwn_write_2(sc, R92C_SYS_CLKR, 1309 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1310 } 1311 } 1312 1313 static int 1314 urtwn_read_chipid(struct urtwn_softc *sc) 1315 { 1316 uint32_t reg; 1317 1318 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1319 1320 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1321 ISSET(sc->chip, URTWN_CHIP_92EU)) 1322 return 0; 1323 1324 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1325 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1326 /* test chip, not supported */ 1327 return EIO; 1328 } 1329 if (reg & R92C_SYS_CFG_TYPE_92C) { 1330 sc->chip |= URTWN_CHIP_92C; 1331 /* Check if it is a castrated 8192C. */ 1332 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1333 R92C_HPON_FSM_CHIP_BONDING_ID) == 1334 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1335 sc->chip |= URTWN_CHIP_92C_1T2R; 1336 } 1337 } 1338 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1339 sc->chip |= URTWN_CHIP_UMC; 1340 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1341 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1342 } 1343 } 1344 return 0; 1345 } 1346 1347 #ifdef URTWN_DEBUG 1348 static void 1349 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1350 { 1351 1352 aprint_normal_dev(sc->sc_dev, 1353 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1354 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1355 1356 aprint_normal_dev(sc->sc_dev, 1357 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1358 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1359 1360 aprint_normal_dev(sc->sc_dev, 1361 "macaddr %s\n", 1362 ether_sprintf(rp->macaddr)); 1363 1364 aprint_normal_dev(sc->sc_dev, 1365 "string %s, subcustomer_id 0x%x\n", 1366 rp->string, rp->subcustomer_id); 1367 1368 aprint_normal_dev(sc->sc_dev, 1369 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1370 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1371 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1372 1373 aprint_normal_dev(sc->sc_dev, 1374 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1375 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1376 rp->ht40_1s_tx_pwr[0][2], 1377 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1378 rp->ht40_1s_tx_pwr[1][2]); 1379 1380 aprint_normal_dev(sc->sc_dev, 1381 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1382 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1383 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1384 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1385 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1386 1387 aprint_normal_dev(sc->sc_dev, 1388 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1389 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1390 rp->ht20_tx_pwr_diff[2] & 0xf, 1391 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1392 rp->ht20_tx_pwr_diff[2] >> 4); 1393 1394 aprint_normal_dev(sc->sc_dev, 1395 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1396 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1397 rp->ofdm_tx_pwr_diff[2] & 0xf, 1398 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1399 rp->ofdm_tx_pwr_diff[2] >> 4); 1400 1401 aprint_normal_dev(sc->sc_dev, 1402 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1403 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1404 rp->ht40_max_pwr[2] & 0xf, 1405 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1406 rp->ht40_max_pwr[2] >> 4); 1407 1408 aprint_normal_dev(sc->sc_dev, 1409 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1410 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1411 rp->ht20_max_pwr[2] & 0xf, 1412 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1413 rp->ht20_max_pwr[2] >> 4); 1414 1415 aprint_normal_dev(sc->sc_dev, 1416 "xtal_calib %d, tssi %d %d, thermal %d\n", 1417 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1418 1419 aprint_normal_dev(sc->sc_dev, 1420 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1421 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1422 1423 aprint_normal_dev(sc->sc_dev, 1424 "channnel_plan %d, version %d customer_id 0x%x\n", 1425 rp->channel_plan, rp->version, rp->curstomer_id); 1426 } 1427 #endif 1428 1429 static void 1430 urtwn_read_rom(struct urtwn_softc *sc) 1431 { 1432 struct ieee80211com *ic = &sc->sc_ic; 1433 struct r92c_rom *rom = &sc->rom; 1434 1435 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1436 1437 mutex_enter(&sc->sc_write_mtx); 1438 1439 /* Read full ROM image. */ 1440 urtwn_efuse_read(sc); 1441 #ifdef URTWN_DEBUG 1442 if (urtwn_debug & DBG_REG) 1443 urtwn_dump_rom(sc, rom); 1444 #endif 1445 1446 /* XXX Weird but this is what the vendor driver does. */ 1447 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1448 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1449 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1450 1451 DPRINTFN(DBG_INIT, 1452 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1453 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1454 1455 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1456 1457 sc->sc_rf_write = urtwn_r92c_rf_write; 1458 sc->sc_power_on = urtwn_r92c_power_on; 1459 sc->sc_dma_init = urtwn_r92c_dma_init; 1460 1461 mutex_exit(&sc->sc_write_mtx); 1462 } 1463 1464 static void 1465 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1466 { 1467 struct ieee80211com *ic = &sc->sc_ic; 1468 uint8_t *rom = sc->r88e_rom; 1469 uint32_t reg; 1470 uint16_t addr = 0; 1471 uint8_t off, msk, tmp; 1472 int i; 1473 1474 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1475 1476 mutex_enter(&sc->sc_write_mtx); 1477 1478 off = 0; 1479 urtwn_efuse_switch_power(sc); 1480 1481 /* Read full ROM image. */ 1482 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1483 while (addr < 4096) { 1484 reg = urtwn_efuse_read_1(sc, addr); 1485 if (reg == 0xff) 1486 break; 1487 addr++; 1488 if ((reg & 0x1f) == 0x0f) { 1489 tmp = (reg & 0xe0) >> 5; 1490 reg = urtwn_efuse_read_1(sc, addr); 1491 if ((reg & 0x0f) != 0x0f) 1492 off = ((reg & 0xf0) >> 1) | tmp; 1493 addr++; 1494 } else 1495 off = reg >> 4; 1496 msk = reg & 0xf; 1497 for (i = 0; i < 4; i++) { 1498 if (msk & (1 << i)) 1499 continue; 1500 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1501 addr++; 1502 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1503 addr++; 1504 } 1505 } 1506 #ifdef URTWN_DEBUG 1507 if (urtwn_debug & DBG_REG) { 1508 } 1509 #endif 1510 1511 addr = 0x10; 1512 for (i = 0; i < 6; i++) 1513 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1514 for (i = 0; i < 5; i++) 1515 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1516 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1517 if (sc->bw20_tx_pwr_diff & 0x08) 1518 sc->bw20_tx_pwr_diff |= 0xf0; 1519 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1520 if (sc->ofdm_tx_pwr_diff & 0x08) 1521 sc->ofdm_tx_pwr_diff |= 0xf0; 1522 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1523 1524 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1525 1526 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1527 sc->sc_power_on = urtwn_r92e_power_on; 1528 sc->sc_rf_write = urtwn_r92e_rf_write; 1529 } else { 1530 sc->sc_power_on = urtwn_r88e_power_on; 1531 sc->sc_rf_write = urtwn_r88e_rf_write; 1532 } 1533 sc->sc_dma_init = urtwn_r88e_dma_init; 1534 1535 mutex_exit(&sc->sc_write_mtx); 1536 } 1537 1538 static int 1539 urtwn_media_change(struct ifnet *ifp) 1540 { 1541 int error; 1542 1543 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1544 1545 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1546 return error; 1547 1548 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1549 (IFF_UP | IFF_RUNNING)) { 1550 urtwn_init(ifp); 1551 } 1552 return 0; 1553 } 1554 1555 /* 1556 * Initialize rate adaptation in firmware. 1557 */ 1558 static int 1559 urtwn_ra_init(struct urtwn_softc *sc) 1560 { 1561 static const uint8_t map[] = { 1562 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1563 }; 1564 struct ieee80211com *ic = &sc->sc_ic; 1565 struct ieee80211_node *ni = ic->ic_bss; 1566 struct ieee80211_rateset *rs = &ni->ni_rates; 1567 struct r92c_fw_cmd_macid_cfg cmd; 1568 uint32_t rates, basicrates; 1569 uint32_t rrsr_mask, rrsr_rate; 1570 uint8_t mode; 1571 size_t maxrate, maxbasicrate, i, j; 1572 int error; 1573 1574 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1575 1576 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1577 1578 /* Get normal and basic rates mask. */ 1579 rates = basicrates = 1; 1580 maxrate = maxbasicrate = 0; 1581 for (i = 0; i < rs->rs_nrates; i++) { 1582 /* Convert 802.11 rate to HW rate index. */ 1583 for (j = 0; j < __arraycount(map); j++) { 1584 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1585 break; 1586 } 1587 } 1588 if (j == __arraycount(map)) { 1589 /* Unknown rate, skip. */ 1590 continue; 1591 } 1592 1593 rates |= 1U << j; 1594 if (j > maxrate) { 1595 maxrate = j; 1596 } 1597 1598 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1599 basicrates |= 1U << j; 1600 if (j > maxbasicrate) { 1601 maxbasicrate = j; 1602 } 1603 } 1604 } 1605 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1606 mode = R92C_RAID_11B; 1607 } else { 1608 mode = R92C_RAID_11BG; 1609 } 1610 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1611 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1612 "maxrate=%jx, maxbasicrate=%jx", 1613 rates, basicrates, maxrate, maxbasicrate); 1614 1615 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1616 maxbasicrate |= R92C_RATE_SHORTGI; 1617 maxrate |= R92C_RATE_SHORTGI; 1618 } 1619 1620 /* Set rates mask for group addressed frames. */ 1621 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1622 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1623 cmd.macid |= RTWN_MACID_SHORTGI; 1624 cmd.mask = htole32((mode << 28) | basicrates); 1625 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1626 if (error != 0) { 1627 aprint_error_dev(sc->sc_dev, 1628 "could not add broadcast station\n"); 1629 return error; 1630 } 1631 /* Set initial MRR rate. */ 1632 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1633 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1634 1635 /* Set rates mask for unicast frames. */ 1636 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1637 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1638 cmd.macid |= RTWN_MACID_SHORTGI; 1639 cmd.mask = htole32((mode << 28) | rates); 1640 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1641 if (error != 0) { 1642 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1643 return error; 1644 } 1645 /* Set initial MRR rate. */ 1646 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1647 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1648 1649 rrsr_rate = ic->ic_fixed_rate; 1650 if (rrsr_rate == -1) 1651 rrsr_rate = 11; 1652 1653 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1654 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1655 1656 /* Indicate highest supported rate. */ 1657 ni->ni_txrate = rs->rs_nrates - 1; 1658 1659 return 0; 1660 } 1661 1662 static int 1663 urtwn_get_nettype(struct urtwn_softc *sc) 1664 { 1665 struct ieee80211com *ic = &sc->sc_ic; 1666 int type; 1667 1668 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1669 1670 switch (ic->ic_opmode) { 1671 case IEEE80211_M_STA: 1672 type = R92C_CR_NETTYPE_INFRA; 1673 break; 1674 1675 case IEEE80211_M_IBSS: 1676 type = R92C_CR_NETTYPE_ADHOC; 1677 break; 1678 1679 default: 1680 type = R92C_CR_NETTYPE_NOLINK; 1681 break; 1682 } 1683 1684 return type; 1685 } 1686 1687 static void 1688 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1689 { 1690 uint8_t reg; 1691 1692 URTWNHIST_FUNC(); 1693 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1694 1695 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1696 1697 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1698 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1699 } 1700 1701 static void 1702 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1703 { 1704 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1705 uint64_t tsf; 1706 1707 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1708 1709 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1710 1711 /* Enable TSF synchronization. */ 1712 urtwn_write_1(sc, R92C_BCN_CTRL, 1713 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1714 1715 /* Correct TSF */ 1716 urtwn_write_1(sc, R92C_BCN_CTRL, 1717 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1718 1719 /* Set initial TSF. */ 1720 tsf = ni->ni_tstamp.tsf; 1721 tsf = le64toh(tsf); 1722 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1723 tsf -= IEEE80211_DUR_TU; 1724 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1725 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1726 1727 urtwn_write_1(sc, R92C_BCN_CTRL, 1728 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1729 } 1730 1731 static void 1732 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1733 { 1734 uint8_t reg; 1735 1736 URTWNHIST_FUNC(); 1737 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1738 1739 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1740 1741 if (led == URTWN_LED_LINK) { 1742 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1743 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1744 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1745 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1746 (R92C_LEDCFG0_DIS << 1)); 1747 if (on) { 1748 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1749 R92E_LEDSON; 1750 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1751 } 1752 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1753 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1754 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1755 if (!on) { 1756 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1757 urtwn_write_1(sc, R92C_LEDCFG2, 1758 reg | R92C_LEDCFG0_DIS); 1759 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1760 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1761 reg & 0xfe); 1762 } 1763 } else { 1764 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1765 if (!on) { 1766 reg |= R92C_LEDCFG0_DIS; 1767 } 1768 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1769 } 1770 sc->ledlink = on; /* Save LED state. */ 1771 } 1772 } 1773 1774 static void 1775 urtwn_calib_to(void *arg) 1776 { 1777 struct urtwn_softc *sc = arg; 1778 1779 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1780 1781 if (sc->sc_dying) 1782 return; 1783 1784 /* Do it in a process context. */ 1785 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1786 } 1787 1788 /* ARGSUSED */ 1789 static void 1790 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1791 { 1792 struct r92c_fw_cmd_rssi cmd; 1793 struct r92e_fw_cmd_rssi cmde; 1794 1795 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1796 1797 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1798 goto restart_timer; 1799 1800 mutex_enter(&sc->sc_write_mtx); 1801 if (sc->avg_pwdb != -1) { 1802 /* Indicate Rx signal strength to FW for rate adaptation. */ 1803 memset(&cmd, 0, sizeof(cmd)); 1804 memset(&cmde, 0, sizeof(cmde)); 1805 cmd.macid = 0; /* BSS. */ 1806 cmde.macid = 0; /* BSS. */ 1807 cmd.pwdb = sc->avg_pwdb; 1808 cmde.pwdb = sc->avg_pwdb; 1809 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1810 sc->avg_pwdb, 0, 0, 0); 1811 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1812 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1813 sizeof(cmd)); 1814 } else { 1815 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1816 sizeof(cmde)); 1817 } 1818 } 1819 1820 /* Do temperature compensation. */ 1821 urtwn_temp_calib(sc); 1822 mutex_exit(&sc->sc_write_mtx); 1823 1824 restart_timer: 1825 if (!sc->sc_dying) { 1826 /* Restart calibration timer. */ 1827 callout_schedule(&sc->sc_calib_to, hz); 1828 } 1829 } 1830 1831 static void 1832 urtwn_next_scan(void *arg) 1833 { 1834 struct urtwn_softc *sc = arg; 1835 int s; 1836 1837 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1838 1839 if (sc->sc_dying) 1840 return; 1841 1842 s = splnet(); 1843 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1844 ieee80211_next_scan(&sc->sc_ic); 1845 splx(s); 1846 } 1847 1848 static void 1849 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1850 { 1851 URTWNHIST_FUNC(); 1852 URTWNHIST_CALLARGS("new node %06jx%06jx", 1853 ni->ni_macaddr[0] << 2 | 1854 ni->ni_macaddr[1] << 1 | 1855 ni->ni_macaddr[2], 1856 ni->ni_macaddr[3] << 2 | 1857 ni->ni_macaddr[4] << 1 | 1858 ni->ni_macaddr[5], 1859 0, 0); 1860 /* start with lowest Tx rate */ 1861 ni->ni_txrate = 0; 1862 } 1863 1864 static int 1865 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1866 { 1867 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1868 struct urtwn_cmd_newstate cmd; 1869 1870 URTWNHIST_FUNC(); 1871 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1872 1873 callout_stop(&sc->sc_scan_to); 1874 callout_stop(&sc->sc_calib_to); 1875 1876 /* Do it in a process context. */ 1877 cmd.state = nstate; 1878 cmd.arg = arg; 1879 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1880 return 0; 1881 } 1882 1883 static void 1884 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1885 { 1886 struct urtwn_cmd_newstate *cmd = arg; 1887 struct ieee80211com *ic = &sc->sc_ic; 1888 struct ieee80211_node *ni; 1889 enum ieee80211_state ostate = ic->ic_state; 1890 enum ieee80211_state nstate = cmd->state; 1891 uint32_t reg; 1892 uint8_t sifs_time, msr; 1893 int s; 1894 1895 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1896 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1897 1898 s = splnet(); 1899 mutex_enter(&sc->sc_write_mtx); 1900 1901 callout_stop(&sc->sc_scan_to); 1902 callout_stop(&sc->sc_calib_to); 1903 1904 switch (ostate) { 1905 case IEEE80211_S_INIT: 1906 break; 1907 1908 case IEEE80211_S_SCAN: 1909 if (nstate != IEEE80211_S_SCAN) { 1910 /* 1911 * End of scanning 1912 */ 1913 /* flush 4-AC Queue after site_survey */ 1914 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1915 1916 /* Allow Rx from our BSSID only. */ 1917 urtwn_write_4(sc, R92C_RCR, 1918 urtwn_read_4(sc, R92C_RCR) | 1919 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1920 } 1921 break; 1922 1923 case IEEE80211_S_AUTH: 1924 case IEEE80211_S_ASSOC: 1925 break; 1926 1927 case IEEE80211_S_RUN: 1928 /* Turn link LED off. */ 1929 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1930 1931 /* Set media status to 'No Link'. */ 1932 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1933 1934 /* Stop Rx of data frames. */ 1935 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1936 1937 /* Reset TSF. */ 1938 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1939 1940 /* Disable TSF synchronization. */ 1941 urtwn_write_1(sc, R92C_BCN_CTRL, 1942 urtwn_read_1(sc, R92C_BCN_CTRL) | 1943 R92C_BCN_CTRL_DIS_TSF_UDT0); 1944 1945 /* Back to 20MHz mode */ 1946 urtwn_set_chan(sc, ic->ic_curchan, 1947 IEEE80211_HTINFO_2NDCHAN_NONE); 1948 1949 if (ic->ic_opmode == IEEE80211_M_IBSS || 1950 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1951 /* Stop BCN */ 1952 urtwn_write_1(sc, R92C_BCN_CTRL, 1953 urtwn_read_1(sc, R92C_BCN_CTRL) & 1954 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1955 } 1956 1957 /* Reset EDCA parameters. */ 1958 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1959 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1960 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1961 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1962 1963 /* flush all cam entries */ 1964 urtwn_cam_init(sc); 1965 break; 1966 } 1967 1968 switch (nstate) { 1969 case IEEE80211_S_INIT: 1970 /* Turn link LED off. */ 1971 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1972 break; 1973 1974 case IEEE80211_S_SCAN: 1975 if (ostate != IEEE80211_S_SCAN) { 1976 /* 1977 * Begin of scanning 1978 */ 1979 1980 /* Set gain for scanning. */ 1981 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1982 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1983 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1984 1985 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1986 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1987 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1988 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1989 } 1990 1991 /* Set media status to 'No Link'. */ 1992 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1993 1994 /* Allow Rx from any BSSID. */ 1995 urtwn_write_4(sc, R92C_RCR, 1996 urtwn_read_4(sc, R92C_RCR) & 1997 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1998 1999 /* Stop Rx of data frames. */ 2000 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2001 2002 /* Disable update TSF */ 2003 urtwn_write_1(sc, R92C_BCN_CTRL, 2004 urtwn_read_1(sc, R92C_BCN_CTRL) | 2005 R92C_BCN_CTRL_DIS_TSF_UDT0); 2006 } 2007 2008 /* Make link LED blink during scan. */ 2009 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2010 2011 /* Pause AC Tx queues. */ 2012 urtwn_write_1(sc, R92C_TXPAUSE, 2013 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2014 2015 urtwn_set_chan(sc, ic->ic_curchan, 2016 IEEE80211_HTINFO_2NDCHAN_NONE); 2017 2018 /* Start periodic scan. */ 2019 if (!sc->sc_dying) 2020 callout_schedule(&sc->sc_scan_to, hz / 5); 2021 break; 2022 2023 case IEEE80211_S_AUTH: 2024 /* Set initial gain under link. */ 2025 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2026 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2027 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2028 2029 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2030 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2031 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2032 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2033 } 2034 2035 /* Set media status to 'No Link'. */ 2036 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2037 2038 /* Allow Rx from any BSSID. */ 2039 urtwn_write_4(sc, R92C_RCR, 2040 urtwn_read_4(sc, R92C_RCR) & 2041 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2042 2043 urtwn_set_chan(sc, ic->ic_curchan, 2044 IEEE80211_HTINFO_2NDCHAN_NONE); 2045 break; 2046 2047 case IEEE80211_S_ASSOC: 2048 break; 2049 2050 case IEEE80211_S_RUN: 2051 ni = ic->ic_bss; 2052 2053 /* XXX: Set 20MHz mode */ 2054 urtwn_set_chan(sc, ic->ic_curchan, 2055 IEEE80211_HTINFO_2NDCHAN_NONE); 2056 2057 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2058 /* Back to 20MHz mode */ 2059 urtwn_set_chan(sc, ic->ic_curchan, 2060 IEEE80211_HTINFO_2NDCHAN_NONE); 2061 2062 /* Set media status to 'No Link'. */ 2063 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2064 2065 /* Enable Rx of data frames. */ 2066 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2067 2068 /* Allow Rx from any BSSID. */ 2069 urtwn_write_4(sc, R92C_RCR, 2070 urtwn_read_4(sc, R92C_RCR) & 2071 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2072 2073 /* Accept Rx data/control/management frames */ 2074 urtwn_write_4(sc, R92C_RCR, 2075 urtwn_read_4(sc, R92C_RCR) | 2076 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2077 2078 /* Turn link LED on. */ 2079 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2080 break; 2081 } 2082 2083 /* Set media status to 'Associated'. */ 2084 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2085 2086 /* Set BSSID. */ 2087 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2088 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2089 2090 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2091 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2092 } else { 2093 /* 802.11b/g */ 2094 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2095 } 2096 2097 /* Enable Rx of data frames. */ 2098 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2099 2100 /* Set beacon interval. */ 2101 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2102 2103 msr = urtwn_read_1(sc, R92C_MSR); 2104 msr &= R92C_MSR_MASK; 2105 switch (ic->ic_opmode) { 2106 case IEEE80211_M_STA: 2107 /* Allow Rx from our BSSID only. */ 2108 urtwn_write_4(sc, R92C_RCR, 2109 urtwn_read_4(sc, R92C_RCR) | 2110 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2111 2112 /* Enable TSF synchronization. */ 2113 urtwn_tsf_sync_enable(sc); 2114 2115 msr |= R92C_MSR_INFRA; 2116 break; 2117 case IEEE80211_M_HOSTAP: 2118 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2119 2120 /* Allow Rx from any BSSID. */ 2121 urtwn_write_4(sc, R92C_RCR, 2122 urtwn_read_4(sc, R92C_RCR) & 2123 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2124 2125 /* Reset TSF timer to zero. */ 2126 reg = urtwn_read_4(sc, R92C_TCR); 2127 reg &= ~0x01; 2128 urtwn_write_4(sc, R92C_TCR, reg); 2129 reg |= 0x01; 2130 urtwn_write_4(sc, R92C_TCR, reg); 2131 2132 msr |= R92C_MSR_AP; 2133 break; 2134 default: 2135 msr |= R92C_MSR_ADHOC; 2136 break; 2137 } 2138 urtwn_write_1(sc, R92C_MSR, msr); 2139 2140 sifs_time = 10; 2141 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2142 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2143 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2144 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2145 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2146 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2147 2148 /* Initialize rate adaptation. */ 2149 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2150 ISSET(sc->chip, URTWN_CHIP_92EU)) 2151 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2152 else 2153 urtwn_ra_init(sc); 2154 2155 /* Turn link LED on. */ 2156 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2157 2158 /* Reset average RSSI. */ 2159 sc->avg_pwdb = -1; 2160 2161 /* Reset temperature calibration state machine. */ 2162 sc->thcal_state = 0; 2163 sc->thcal_lctemp = 0; 2164 2165 /* Start periodic calibration. */ 2166 if (!sc->sc_dying) 2167 callout_schedule(&sc->sc_calib_to, hz); 2168 break; 2169 } 2170 2171 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2172 2173 mutex_exit(&sc->sc_write_mtx); 2174 splx(s); 2175 } 2176 2177 static int 2178 urtwn_wme_update(struct ieee80211com *ic) 2179 { 2180 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2181 2182 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2183 2184 /* don't override default WME values if WME is not actually enabled */ 2185 if (!(ic->ic_flags & IEEE80211_F_WME)) 2186 return 0; 2187 2188 /* Do it in a process context. */ 2189 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2190 return 0; 2191 } 2192 2193 static void 2194 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2195 { 2196 static const uint16_t ac2reg[WME_NUM_AC] = { 2197 R92C_EDCA_BE_PARAM, 2198 R92C_EDCA_BK_PARAM, 2199 R92C_EDCA_VI_PARAM, 2200 R92C_EDCA_VO_PARAM 2201 }; 2202 struct ieee80211com *ic = &sc->sc_ic; 2203 const struct wmeParams *wmep; 2204 int ac, aifs, slottime; 2205 int s; 2206 2207 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2208 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2209 2210 s = splnet(); 2211 mutex_enter(&sc->sc_write_mtx); 2212 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2213 for (ac = 0; ac < WME_NUM_AC; ac++) { 2214 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2215 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2216 aifs = wmep->wmep_aifsn * slottime + 10; 2217 urtwn_write_4(sc, ac2reg[ac], 2218 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2219 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2220 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2221 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2222 } 2223 mutex_exit(&sc->sc_write_mtx); 2224 splx(s); 2225 } 2226 2227 static void 2228 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2229 { 2230 int pwdb; 2231 2232 URTWNHIST_FUNC(); 2233 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2234 2235 /* Convert antenna signal to percentage. */ 2236 if (rssi <= -100 || rssi >= 20) 2237 pwdb = 0; 2238 else if (rssi >= 0) 2239 pwdb = 100; 2240 else 2241 pwdb = 100 + rssi; 2242 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2243 if (rate <= 3) { 2244 /* CCK gain is smaller than OFDM/MCS gain. */ 2245 pwdb += 6; 2246 if (pwdb > 100) 2247 pwdb = 100; 2248 if (pwdb <= 14) 2249 pwdb -= 4; 2250 else if (pwdb <= 26) 2251 pwdb -= 8; 2252 else if (pwdb <= 34) 2253 pwdb -= 6; 2254 else if (pwdb <= 42) 2255 pwdb -= 2; 2256 } 2257 } 2258 if (sc->avg_pwdb == -1) /* Init. */ 2259 sc->avg_pwdb = pwdb; 2260 else if (sc->avg_pwdb < pwdb) 2261 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2262 else 2263 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2264 2265 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2266 rate, rssi, pwdb, sc->avg_pwdb); 2267 } 2268 2269 static int8_t 2270 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2271 { 2272 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2273 struct r92c_rx_phystat *phy; 2274 struct r92c_rx_cck *cck; 2275 uint8_t rpt; 2276 int8_t rssi; 2277 2278 URTWNHIST_FUNC(); 2279 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2280 2281 if (rate <= 3) { 2282 cck = (struct r92c_rx_cck *)physt; 2283 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2284 rpt = (cck->agc_rpt >> 5) & 0x3; 2285 rssi = (cck->agc_rpt & 0x1f) << 1; 2286 } else { 2287 rpt = (cck->agc_rpt >> 6) & 0x3; 2288 rssi = cck->agc_rpt & 0x3e; 2289 } 2290 rssi = cckoff[rpt] - rssi; 2291 } else { /* OFDM/HT. */ 2292 phy = (struct r92c_rx_phystat *)physt; 2293 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2294 } 2295 return rssi; 2296 } 2297 2298 static int8_t 2299 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2300 { 2301 struct r92c_rx_phystat *phy; 2302 struct r88e_rx_cck *cck; 2303 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2304 int8_t rssi; 2305 2306 URTWNHIST_FUNC(); 2307 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2308 2309 rssi = 0; 2310 if (rate <= 3) { 2311 cck = (struct r88e_rx_cck *)physt; 2312 cck_agc_rpt = cck->agc_rpt; 2313 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2314 vga_idx = cck_agc_rpt & 0x1f; 2315 switch (lna_idx) { 2316 case 7: 2317 if (vga_idx <= 27) 2318 rssi = -100 + 2* (27 - vga_idx); 2319 else 2320 rssi = -100; 2321 break; 2322 case 6: 2323 rssi = -48 + 2 * (2 - vga_idx); 2324 break; 2325 case 5: 2326 rssi = -42 + 2 * (7 - vga_idx); 2327 break; 2328 case 4: 2329 rssi = -36 + 2 * (7 - vga_idx); 2330 break; 2331 case 3: 2332 rssi = -24 + 2 * (7 - vga_idx); 2333 break; 2334 case 2: 2335 rssi = -12 + 2 * (5 - vga_idx); 2336 break; 2337 case 1: 2338 rssi = 8 - (2 * vga_idx); 2339 break; 2340 case 0: 2341 rssi = 14 - (2 * vga_idx); 2342 break; 2343 } 2344 rssi += 6; 2345 } else { /* OFDM/HT. */ 2346 phy = (struct r92c_rx_phystat *)physt; 2347 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2348 } 2349 return rssi; 2350 } 2351 2352 static void 2353 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2354 { 2355 struct ieee80211com *ic = &sc->sc_ic; 2356 struct ifnet *ifp = ic->ic_ifp; 2357 struct ieee80211_frame *wh; 2358 struct ieee80211_node *ni; 2359 struct r92c_rx_desc_usb *stat; 2360 uint32_t rxdw0, rxdw3; 2361 struct mbuf *m; 2362 uint8_t rate; 2363 int8_t rssi = 0; 2364 int s, infosz; 2365 2366 URTWNHIST_FUNC(); 2367 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2368 2369 stat = (struct r92c_rx_desc_usb *)buf; 2370 rxdw0 = le32toh(stat->rxdw0); 2371 rxdw3 = le32toh(stat->rxdw3); 2372 2373 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2374 /* 2375 * This should not happen since we setup our Rx filter 2376 * to not receive these frames. 2377 */ 2378 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2379 ifp->if_ierrors++; 2380 return; 2381 } 2382 /* 2383 * XXX: This will drop most control packets. Do we really 2384 * want this in IEEE80211_M_MONITOR mode? 2385 */ 2386 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2387 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2388 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2389 ic->ic_stats.is_rx_tooshort++; 2390 ifp->if_ierrors++; 2391 return; 2392 } 2393 if (__predict_false(pktlen > MCLBYTES)) { 2394 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2395 ifp->if_ierrors++; 2396 return; 2397 } 2398 2399 rate = MS(rxdw3, R92C_RXDW3_RATE); 2400 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2401 2402 /* Get RSSI from PHY status descriptor if present. */ 2403 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2404 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2405 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2406 else 2407 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2408 /* Update our average RSSI. */ 2409 urtwn_update_avgrssi(sc, rate, rssi); 2410 } 2411 2412 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2413 pktlen, rate, infosz, rssi); 2414 2415 MGETHDR(m, M_DONTWAIT, MT_DATA); 2416 if (__predict_false(m == NULL)) { 2417 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2418 ic->ic_stats.is_rx_nobuf++; 2419 ifp->if_ierrors++; 2420 return; 2421 } 2422 if (pktlen > (int)MHLEN) { 2423 MCLGET(m, M_DONTWAIT); 2424 if (__predict_false(!(m->m_flags & M_EXT))) { 2425 aprint_error_dev(sc->sc_dev, 2426 "couldn't allocate rx mbuf cluster\n"); 2427 m_freem(m); 2428 ic->ic_stats.is_rx_nobuf++; 2429 ifp->if_ierrors++; 2430 return; 2431 } 2432 } 2433 2434 /* Finalize mbuf. */ 2435 m_set_rcvif(m, ifp); 2436 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2437 memcpy(mtod(m, uint8_t *), wh, pktlen); 2438 m->m_pkthdr.len = m->m_len = pktlen; 2439 2440 s = splnet(); 2441 if (__predict_false(sc->sc_drvbpf != NULL)) { 2442 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2443 2444 tap->wr_flags = 0; 2445 if (!(rxdw3 & R92C_RXDW3_HT)) { 2446 switch (rate) { 2447 /* CCK. */ 2448 case 0: tap->wr_rate = 2; break; 2449 case 1: tap->wr_rate = 4; break; 2450 case 2: tap->wr_rate = 11; break; 2451 case 3: tap->wr_rate = 22; break; 2452 /* OFDM. */ 2453 case 4: tap->wr_rate = 12; break; 2454 case 5: tap->wr_rate = 18; break; 2455 case 6: tap->wr_rate = 24; break; 2456 case 7: tap->wr_rate = 36; break; 2457 case 8: tap->wr_rate = 48; break; 2458 case 9: tap->wr_rate = 72; break; 2459 case 10: tap->wr_rate = 96; break; 2460 case 11: tap->wr_rate = 108; break; 2461 } 2462 } else if (rate >= 12) { /* MCS0~15. */ 2463 /* Bit 7 set means HT MCS instead of rate. */ 2464 tap->wr_rate = 0x80 | (rate - 12); 2465 } 2466 tap->wr_dbm_antsignal = rssi; 2467 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2468 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2469 2470 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2471 } 2472 2473 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2474 2475 /* push the frame up to the 802.11 stack */ 2476 ieee80211_input(ic, m, ni, rssi, 0); 2477 2478 /* Node is no longer needed. */ 2479 ieee80211_free_node(ni); 2480 2481 splx(s); 2482 } 2483 2484 static void 2485 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2486 { 2487 struct urtwn_rx_data *data = priv; 2488 struct urtwn_softc *sc = data->sc; 2489 struct r92c_rx_desc_usb *stat; 2490 size_t pidx = data->pidx; 2491 uint32_t rxdw0; 2492 uint8_t *buf; 2493 int len, totlen, pktlen, infosz, npkts; 2494 2495 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2496 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2497 2498 mutex_enter(&sc->sc_rx_mtx); 2499 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2500 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2501 /* Put this Rx buffer back to our free list. */ 2502 mutex_exit(&sc->sc_rx_mtx); 2503 2504 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2505 if (status == USBD_STALLED) 2506 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2507 else if (status != USBD_CANCELLED) 2508 goto resubmit; 2509 return; 2510 } 2511 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2512 2513 if (__predict_false(len < (int)sizeof(*stat))) { 2514 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2515 goto resubmit; 2516 } 2517 buf = data->buf; 2518 2519 /* Get the number of encapsulated frames. */ 2520 stat = (struct r92c_rx_desc_usb *)buf; 2521 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2522 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2523 2524 if (npkts != 0) 2525 rnd_add_uint32(&sc->rnd_source, npkts); 2526 2527 /* Process all of them. */ 2528 while (npkts-- > 0) { 2529 if (__predict_false(len < (int)sizeof(*stat))) { 2530 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2531 len, 0, 0, 0); 2532 break; 2533 } 2534 stat = (struct r92c_rx_desc_usb *)buf; 2535 rxdw0 = le32toh(stat->rxdw0); 2536 2537 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2538 if (__predict_false(pktlen == 0)) { 2539 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2540 break; 2541 } 2542 2543 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2544 2545 /* Make sure everything fits in xfer. */ 2546 totlen = sizeof(*stat) + infosz + pktlen; 2547 if (__predict_false(totlen > len)) { 2548 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2549 (int)sizeof(*stat), infosz, pktlen, len); 2550 break; 2551 } 2552 2553 /* Process 802.11 frame. */ 2554 urtwn_rx_frame(sc, buf, pktlen); 2555 2556 /* Next chunk is 128-byte aligned. */ 2557 totlen = roundup2(totlen, 128); 2558 buf += totlen; 2559 len -= totlen; 2560 } 2561 2562 resubmit: 2563 /* Setup a new transfer. */ 2564 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2565 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2566 (void)usbd_transfer(xfer); 2567 } 2568 2569 static void 2570 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2571 { 2572 struct urtwn_tx_data *data = priv; 2573 struct urtwn_softc *sc = data->sc; 2574 struct ifnet *ifp = &sc->sc_if; 2575 size_t pidx = data->pidx; 2576 int s; 2577 2578 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2579 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2580 2581 mutex_enter(&sc->sc_tx_mtx); 2582 /* Put this Tx buffer back to our free list. */ 2583 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2584 mutex_exit(&sc->sc_tx_mtx); 2585 2586 s = splnet(); 2587 sc->tx_timer = 0; 2588 ifp->if_flags &= ~IFF_OACTIVE; 2589 2590 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2591 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2592 if (status == USBD_STALLED) { 2593 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2594 usbd_clear_endpoint_stall_async(pipe); 2595 } 2596 printf("ERROR1\n"); 2597 ifp->if_oerrors++; 2598 } 2599 splx(s); 2600 return; 2601 } 2602 2603 ifp->if_opackets++; 2604 urtwn_start(ifp); 2605 splx(s); 2606 2607 } 2608 2609 static int 2610 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2611 struct urtwn_tx_data *data) 2612 { 2613 struct ieee80211com *ic = &sc->sc_ic; 2614 struct ieee80211_frame *wh; 2615 struct ieee80211_key *k = NULL; 2616 struct r92c_tx_desc_usb *txd; 2617 size_t i, padsize, xferlen, txd_len; 2618 uint16_t seq, sum; 2619 uint8_t raid, type, tid; 2620 int s, hasqos, error; 2621 2622 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2623 2624 wh = mtod(m, struct ieee80211_frame *); 2625 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2626 txd_len = sizeof(*txd); 2627 2628 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2629 txd_len = 32; 2630 2631 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2632 k = ieee80211_crypto_encap(ic, ni, m); 2633 if (k == NULL) 2634 return ENOBUFS; 2635 2636 /* packet header may have moved, reset our local pointer */ 2637 wh = mtod(m, struct ieee80211_frame *); 2638 } 2639 2640 if (__predict_false(sc->sc_drvbpf != NULL)) { 2641 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2642 2643 tap->wt_flags = 0; 2644 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2645 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2646 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2647 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2648 2649 /* XXX: set tap->wt_rate? */ 2650 2651 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2652 } 2653 2654 /* non-qos data frames */ 2655 tid = R92C_TXDW1_QSEL_BE; 2656 if ((hasqos = ieee80211_has_qos(wh))) { 2657 /* data frames in 11n mode */ 2658 struct ieee80211_qosframe *qwh = (void *)wh; 2659 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2660 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2661 tid = R92C_TXDW1_QSEL_MGNT; 2662 } 2663 2664 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2665 padsize = 8; 2666 else 2667 padsize = 0; 2668 2669 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2670 padsize = 0; 2671 2672 /* Fill Tx descriptor. */ 2673 txd = (struct r92c_tx_desc_usb *)data->buf; 2674 memset(txd, 0, txd_len + padsize); 2675 2676 txd->txdw0 |= htole32( 2677 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2678 SM(R92C_TXDW0_OFFSET, txd_len)); 2679 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2680 txd->txdw0 |= htole32( 2681 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2682 } 2683 2684 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2685 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2686 2687 /* fix pad field */ 2688 if (padsize > 0) { 2689 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2690 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2691 } 2692 2693 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2694 type == IEEE80211_FC0_TYPE_DATA) { 2695 if (ic->ic_curmode == IEEE80211_MODE_11B) 2696 raid = R92C_RAID_11B; 2697 else 2698 raid = R92C_RAID_11BG; 2699 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2700 tid, raid, 0, 0); 2701 2702 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2703 txd->txdw1 |= htole32( 2704 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2705 SM(R92C_TXDW1_QSEL, tid) | 2706 SM(R92C_TXDW1_RAID, raid) | 2707 R92C_TXDW1_AGGBK); 2708 } else 2709 txd->txdw1 |= htole32( 2710 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2711 SM(R92C_TXDW1_QSEL, tid) | 2712 SM(R92C_TXDW1_RAID, raid) | 2713 R92C_TXDW1_AGGBK); 2714 2715 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2716 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2717 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2718 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2719 2720 if (hasqos) { 2721 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2722 } 2723 2724 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2725 /* for 11g */ 2726 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2727 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2728 R92C_TXDW4_HWRTSEN); 2729 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2730 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2731 R92C_TXDW4_HWRTSEN); 2732 } 2733 } 2734 /* Send RTS at OFDM24. */ 2735 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2736 txd->txdw5 |= htole32(0x0001ff00); 2737 /* Send data at OFDM54. */ 2738 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2739 txd->txdw5 |= htole32(0x13 & 0x3f); 2740 else 2741 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2742 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2743 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2744 txd->txdw1 |= htole32( 2745 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2746 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2747 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2748 2749 /* Force CCK1. */ 2750 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2751 /* Use 1Mbps */ 2752 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2753 } else { 2754 /* broadcast or multicast packets */ 2755 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2756 txd->txdw1 |= htole32( 2757 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2758 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2759 2760 /* Force CCK1. */ 2761 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2762 /* Use 1Mbps */ 2763 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2764 } 2765 /* Set sequence number */ 2766 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2767 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2768 txd->txdseq |= htole16(seq); 2769 2770 if (!hasqos) { 2771 /* Use HW sequence numbering for non-QoS frames. */ 2772 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2773 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2774 } 2775 } else { 2776 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2777 R92E_HWSEQ_SHIFT); 2778 if (!hasqos) { 2779 /* Use HW sequence numbering for non-QoS frames. */ 2780 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2781 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2782 } 2783 } 2784 2785 /* Compute Tx descriptor checksum. */ 2786 sum = 0; 2787 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2788 sum ^= ((uint16_t *)txd)[i]; 2789 txd->txdsum = sum; /* NB: already little endian. */ 2790 2791 xferlen = txd_len + m->m_pkthdr.len + padsize; 2792 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2793 2794 s = splnet(); 2795 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2796 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2797 urtwn_txeof); 2798 error = usbd_transfer(data->xfer); 2799 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2800 error != USBD_IN_PROGRESS)) { 2801 splx(s); 2802 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2803 return error; 2804 } 2805 splx(s); 2806 return 0; 2807 } 2808 2809 struct urtwn_tx_data * 2810 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2811 { 2812 struct urtwn_tx_data *data = NULL; 2813 2814 mutex_enter(&sc->sc_tx_mtx); 2815 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2816 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2817 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2818 } 2819 mutex_exit(&sc->sc_tx_mtx); 2820 2821 return data; 2822 } 2823 2824 static void 2825 urtwn_start(struct ifnet *ifp) 2826 { 2827 struct urtwn_softc *sc = ifp->if_softc; 2828 struct ieee80211com *ic = &sc->sc_ic; 2829 struct urtwn_tx_data *data; 2830 struct ether_header *eh; 2831 struct ieee80211_node *ni; 2832 struct mbuf *m; 2833 2834 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2835 2836 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2837 return; 2838 2839 data = NULL; 2840 for (;;) { 2841 /* Send pending management frames first. */ 2842 IF_POLL(&ic->ic_mgtq, m); 2843 if (m != NULL) { 2844 /* Use AC_VO for management frames. */ 2845 2846 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2847 2848 if (data == NULL) { 2849 ifp->if_flags |= IFF_OACTIVE; 2850 DPRINTFN(DBG_TX, "empty tx_free_list", 2851 0, 0, 0, 0); 2852 return; 2853 } 2854 IF_DEQUEUE(&ic->ic_mgtq, m); 2855 ni = M_GETCTX(m, struct ieee80211_node *); 2856 M_CLEARCTX(m); 2857 goto sendit; 2858 } 2859 if (ic->ic_state != IEEE80211_S_RUN) 2860 break; 2861 2862 /* Encapsulate and send data frames. */ 2863 IFQ_POLL(&ifp->if_snd, m); 2864 if (m == NULL) 2865 break; 2866 2867 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2868 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2869 uint8_t qid = WME_AC_BE; 2870 if (ieee80211_has_qos(wh)) { 2871 /* data frames in 11n mode */ 2872 struct ieee80211_qosframe *qwh = (void *)wh; 2873 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2874 qid = TID_TO_WME_AC(tid); 2875 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2876 qid = WME_AC_VO; 2877 } 2878 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2879 2880 if (data == NULL) { 2881 ifp->if_flags |= IFF_OACTIVE; 2882 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2883 return; 2884 } 2885 IFQ_DEQUEUE(&ifp->if_snd, m); 2886 2887 if (m->m_len < (int)sizeof(*eh) && 2888 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2889 printf("ERROR6\n"); 2890 ifp->if_oerrors++; 2891 continue; 2892 } 2893 eh = mtod(m, struct ether_header *); 2894 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2895 if (ni == NULL) { 2896 m_freem(m); 2897 printf("ERROR5\n"); 2898 ifp->if_oerrors++; 2899 continue; 2900 } 2901 2902 bpf_mtap(ifp, m, BPF_D_OUT); 2903 2904 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2905 ieee80211_free_node(ni); 2906 printf("ERROR4\n"); 2907 ifp->if_oerrors++; 2908 continue; 2909 } 2910 sendit: 2911 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2912 2913 if (urtwn_tx(sc, m, ni, data) != 0) { 2914 m_freem(m); 2915 ieee80211_free_node(ni); 2916 printf("ERROR3\n"); 2917 ifp->if_oerrors++; 2918 continue; 2919 } 2920 m_freem(m); 2921 ieee80211_free_node(ni); 2922 sc->tx_timer = 5; 2923 ifp->if_timer = 1; 2924 } 2925 } 2926 2927 static void 2928 urtwn_watchdog(struct ifnet *ifp) 2929 { 2930 struct urtwn_softc *sc = ifp->if_softc; 2931 2932 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2933 2934 ifp->if_timer = 0; 2935 2936 if (sc->tx_timer > 0) { 2937 if (--sc->tx_timer == 0) { 2938 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2939 /* urtwn_init(ifp); XXX needs a process context! */ 2940 printf("ERROR2\n"); 2941 ifp->if_oerrors++; 2942 return; 2943 } 2944 ifp->if_timer = 1; 2945 } 2946 ieee80211_watchdog(&sc->sc_ic); 2947 } 2948 2949 static int 2950 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2951 { 2952 struct urtwn_softc *sc = ifp->if_softc; 2953 struct ieee80211com *ic = &sc->sc_ic; 2954 int s, error = 0; 2955 2956 URTWNHIST_FUNC(); 2957 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2958 0, 0); 2959 2960 s = splnet(); 2961 2962 switch (cmd) { 2963 case SIOCSIFFLAGS: 2964 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2965 break; 2966 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2967 case IFF_UP | IFF_RUNNING: 2968 break; 2969 case IFF_UP: 2970 urtwn_init(ifp); 2971 break; 2972 case IFF_RUNNING: 2973 urtwn_stop(ifp, 1); 2974 break; 2975 case 0: 2976 break; 2977 } 2978 break; 2979 2980 case SIOCADDMULTI: 2981 case SIOCDELMULTI: 2982 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2983 /* setup multicast filter, etc */ 2984 error = 0; 2985 } 2986 break; 2987 2988 case SIOCS80211CHANNEL: 2989 /* 2990 * This allows for fast channel switching in monitor mode 2991 * (used by kismet). In IBSS mode, we must explicitly reset 2992 * the interface to generate a new beacon frame. 2993 */ 2994 error = ieee80211_ioctl(ic, cmd, data); 2995 if (error == ENETRESET && 2996 ic->ic_opmode == IEEE80211_M_MONITOR) { 2997 urtwn_set_chan(sc, ic->ic_curchan, 2998 IEEE80211_HTINFO_2NDCHAN_NONE); 2999 error = 0; 3000 } 3001 break; 3002 3003 default: 3004 error = ieee80211_ioctl(ic, cmd, data); 3005 break; 3006 } 3007 if (error == ENETRESET) { 3008 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3009 (IFF_UP | IFF_RUNNING) && 3010 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3011 urtwn_init(ifp); 3012 } 3013 error = 0; 3014 } 3015 3016 splx(s); 3017 3018 return error; 3019 } 3020 3021 static __inline int 3022 urtwn_power_on(struct urtwn_softc *sc) 3023 { 3024 3025 return sc->sc_power_on(sc); 3026 } 3027 3028 static int 3029 urtwn_r92c_power_on(struct urtwn_softc *sc) 3030 { 3031 uint32_t reg; 3032 int ntries; 3033 3034 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3035 3036 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3037 3038 /* Wait for autoload done bit. */ 3039 for (ntries = 0; ntries < 1000; ntries++) { 3040 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3041 break; 3042 DELAY(5); 3043 } 3044 if (ntries == 1000) { 3045 aprint_error_dev(sc->sc_dev, 3046 "timeout waiting for chip autoload\n"); 3047 return ETIMEDOUT; 3048 } 3049 3050 /* Unlock ISO/CLK/Power control register. */ 3051 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3052 /* Move SPS into PWM mode. */ 3053 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3054 DELAY(5); 3055 3056 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3057 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3058 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3059 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3060 DELAY(100); 3061 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3062 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3063 ~R92C_SYS_ISO_CTRL_MD2PP); 3064 } 3065 3066 /* Auto enable WLAN. */ 3067 urtwn_write_2(sc, R92C_APS_FSMCO, 3068 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3069 for (ntries = 0; ntries < 1000; ntries++) { 3070 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3071 R92C_APS_FSMCO_APFM_ONMAC)) 3072 break; 3073 DELAY(100); 3074 } 3075 if (ntries == 1000) { 3076 aprint_error_dev(sc->sc_dev, 3077 "timeout waiting for MAC auto ON\n"); 3078 return ETIMEDOUT; 3079 } 3080 3081 /* Enable radio, GPIO and LED functions. */ 3082 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3083 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3084 urtwn_write_2(sc, R92C_APS_FSMCO, 3085 R92C_APS_FSMCO_AFSM_HSUS | 3086 R92C_APS_FSMCO_PDN_EN | 3087 R92C_APS_FSMCO_PFM_ALDN); 3088 3089 /* Release RF digital isolation. */ 3090 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3091 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3092 3093 /* Initialize MAC. */ 3094 urtwn_write_1(sc, R92C_APSD_CTRL, 3095 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3096 for (ntries = 0; ntries < 200; ntries++) { 3097 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3098 R92C_APSD_CTRL_OFF_STATUS)) 3099 break; 3100 DELAY(5); 3101 } 3102 if (ntries == 200) { 3103 aprint_error_dev(sc->sc_dev, 3104 "timeout waiting for MAC initialization\n"); 3105 return ETIMEDOUT; 3106 } 3107 3108 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3109 reg = urtwn_read_2(sc, R92C_CR); 3110 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3111 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3112 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3113 R92C_CR_ENSEC; 3114 urtwn_write_2(sc, R92C_CR, reg); 3115 3116 urtwn_write_1(sc, 0xfe10, 0x19); 3117 return 0; 3118 } 3119 3120 static int 3121 urtwn_r92e_power_on(struct urtwn_softc *sc) 3122 { 3123 uint32_t reg; 3124 uint32_t val; 3125 int ntries; 3126 3127 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3128 3129 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3130 3131 /* Enable radio, GPIO and LED functions. */ 3132 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3133 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3134 urtwn_write_2(sc, R92C_APS_FSMCO, 3135 R92C_APS_FSMCO_AFSM_HSUS | 3136 R92C_APS_FSMCO_PDN_EN | 3137 R92C_APS_FSMCO_PFM_ALDN); 3138 3139 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3140 /* LDO. */ 3141 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3142 } 3143 else { 3144 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3145 R92C_SYS_SWR_CTRL2) & 0xffff); 3146 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3147 } 3148 3149 for (ntries = 0; ntries < 2; ntries++) { 3150 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3151 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3152 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3153 R92C_AFE_CTRL4)); 3154 } 3155 3156 /* Reset BB. */ 3157 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3158 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3159 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3160 3161 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3162 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3163 3164 /* Disable HWPDN. */ 3165 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3166 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3167 3168 /* Disable WL suspend. */ 3169 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3170 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3171 R92C_APS_FSMCO_AFSM_HSUS)); 3172 3173 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3174 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3175 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3176 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3177 for (ntries = 0; ntries < 10000; ntries++) { 3178 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3179 R92C_APS_FSMCO_APFM_ONMAC; 3180 if (val == 0x0) 3181 break; 3182 DELAY(10); 3183 } 3184 if (ntries == 10000) { 3185 aprint_error_dev(sc->sc_dev, 3186 "timeout waiting for chip power up\n"); 3187 return ETIMEDOUT; 3188 } 3189 3190 urtwn_write_2(sc, R92C_CR, 0x00); 3191 reg = urtwn_read_2(sc, R92C_CR); 3192 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3193 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3194 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3195 urtwn_write_2(sc, R92C_CR, reg); 3196 3197 return 0; 3198 } 3199 3200 static int 3201 urtwn_r88e_power_on(struct urtwn_softc *sc) 3202 { 3203 uint32_t reg; 3204 uint8_t val; 3205 int ntries; 3206 3207 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3208 3209 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3210 3211 /* Wait for power ready bit. */ 3212 for (ntries = 0; ntries < 5000; ntries++) { 3213 val = urtwn_read_1(sc, 0x6) & 0x2; 3214 if (val == 0x2) 3215 break; 3216 DELAY(10); 3217 } 3218 if (ntries == 5000) { 3219 aprint_error_dev(sc->sc_dev, 3220 "timeout waiting for chip power up\n"); 3221 return ETIMEDOUT; 3222 } 3223 3224 /* Reset BB. */ 3225 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3226 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3227 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3228 3229 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3230 3231 /* Disable HWPDN. */ 3232 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3233 3234 /* Disable WL suspend. */ 3235 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3236 3237 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3238 for (ntries = 0; ntries < 5000; ntries++) { 3239 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3240 break; 3241 DELAY(10); 3242 } 3243 if (ntries == 5000) 3244 return ETIMEDOUT; 3245 3246 /* Enable LDO normal mode. */ 3247 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3248 3249 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3250 urtwn_write_2(sc, R92C_CR, 0); 3251 reg = urtwn_read_2(sc, R92C_CR); 3252 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3253 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3254 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3255 urtwn_write_2(sc, R92C_CR, reg); 3256 3257 return 0; 3258 } 3259 3260 static int 3261 urtwn_llt_init(struct urtwn_softc *sc) 3262 { 3263 size_t i, page_count, pktbuf_count; 3264 uint32_t val; 3265 int error; 3266 3267 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3268 3269 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3270 3271 if (sc->chip & URTWN_CHIP_88E) 3272 page_count = R88E_TX_PAGE_COUNT; 3273 else if (sc->chip & URTWN_CHIP_92EU) 3274 page_count = R92E_TX_PAGE_COUNT; 3275 else 3276 page_count = R92C_TX_PAGE_COUNT; 3277 if (sc->chip & URTWN_CHIP_88E) 3278 pktbuf_count = R88E_TXPKTBUF_COUNT; 3279 else if (sc->chip & URTWN_CHIP_92EU) 3280 pktbuf_count = R88E_TXPKTBUF_COUNT; 3281 else 3282 pktbuf_count = R92C_TXPKTBUF_COUNT; 3283 3284 if (sc->chip & URTWN_CHIP_92EU) { 3285 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3286 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3287 DELAY(100); 3288 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3289 if (val & R92E_AUTO_LLT_EN) 3290 return EIO; 3291 return 0; 3292 } 3293 3294 /* Reserve pages [0; page_count]. */ 3295 for (i = 0; i < page_count; i++) { 3296 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3297 return error; 3298 } 3299 /* NB: 0xff indicates end-of-list. */ 3300 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3301 return error; 3302 /* 3303 * Use pages [page_count + 1; pktbuf_count - 1] 3304 * as ring buffer. 3305 */ 3306 for (++i; i < pktbuf_count - 1; i++) { 3307 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3308 return error; 3309 } 3310 /* Make the last page point to the beginning of the ring buffer. */ 3311 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3312 return error; 3313 } 3314 3315 static void 3316 urtwn_fw_reset(struct urtwn_softc *sc) 3317 { 3318 uint16_t reg; 3319 int ntries; 3320 3321 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3322 3323 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3324 3325 /* Tell 8051 to reset itself. */ 3326 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3327 3328 /* Wait until 8051 resets by itself. */ 3329 for (ntries = 0; ntries < 100; ntries++) { 3330 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3331 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3332 return; 3333 DELAY(50); 3334 } 3335 /* Force 8051 reset. */ 3336 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3337 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3338 } 3339 3340 static void 3341 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3342 { 3343 uint16_t reg; 3344 3345 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3346 3347 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3348 3349 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3350 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3351 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3352 } 3353 DELAY(50); 3354 3355 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3356 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3357 DELAY(50); 3358 3359 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3360 DELAY(50); 3361 3362 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3363 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3364 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3365 } 3366 DELAY(50); 3367 3368 } 3369 3370 static int 3371 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3372 { 3373 uint32_t reg; 3374 int off, mlen, error = 0; 3375 3376 URTWNHIST_FUNC(); 3377 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3378 page, (uintptr_t)buf, len, 0); 3379 3380 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3381 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3382 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3383 3384 off = R92C_FW_START_ADDR; 3385 while (len > 0) { 3386 if (len > 196) 3387 mlen = 196; 3388 else if (len > 4) 3389 mlen = 4; 3390 else 3391 mlen = 1; 3392 error = urtwn_write_region(sc, off, buf, mlen); 3393 if (error != 0) 3394 break; 3395 off += mlen; 3396 buf += mlen; 3397 len -= mlen; 3398 } 3399 return error; 3400 } 3401 3402 static int 3403 urtwn_load_firmware(struct urtwn_softc *sc) 3404 { 3405 firmware_handle_t fwh; 3406 const struct r92c_fw_hdr *hdr; 3407 const char *name; 3408 u_char *fw, *ptr; 3409 size_t len; 3410 uint32_t reg; 3411 int mlen, ntries, page, error; 3412 3413 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3414 3415 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3416 3417 /* Read firmware image from the filesystem. */ 3418 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3419 name = "rtl8188eufw.bin"; 3420 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3421 name = "rtl8192eefw.bin"; 3422 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3423 URTWN_CHIP_UMC_A_CUT) 3424 name = "rtl8192cfwU.bin"; 3425 else 3426 name = "rtl8192cfw.bin"; 3427 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3428 aprint_error_dev(sc->sc_dev, 3429 "failed load firmware of file %s (error %d)\n", name, 3430 error); 3431 return error; 3432 } 3433 const size_t fwlen = len = firmware_get_size(fwh); 3434 fw = firmware_malloc(len); 3435 if (fw == NULL) { 3436 aprint_error_dev(sc->sc_dev, 3437 "failed to allocate firmware memory\n"); 3438 firmware_close(fwh); 3439 return ENOMEM; 3440 } 3441 error = firmware_read(fwh, 0, fw, len); 3442 firmware_close(fwh); 3443 if (error != 0) { 3444 aprint_error_dev(sc->sc_dev, 3445 "failed to read firmware (error %d)\n", error); 3446 firmware_free(fw, fwlen); 3447 return error; 3448 } 3449 3450 len = fwlen; 3451 ptr = fw; 3452 hdr = (const struct r92c_fw_hdr *)ptr; 3453 /* Check if there is a valid FW header and skip it. */ 3454 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3455 (le16toh(hdr->signature) >> 4) == 0x88e || 3456 (le16toh(hdr->signature) >> 4) == 0x92e || 3457 (le16toh(hdr->signature) >> 4) == 0x92c) { 3458 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3459 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3460 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3461 hdr->month, hdr->date, hdr->hour, hdr->minute); 3462 ptr += sizeof(*hdr); 3463 len -= sizeof(*hdr); 3464 } 3465 3466 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3467 /* Reset MCU ready status */ 3468 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3469 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3470 ISSET(sc->chip, URTWN_CHIP_92EU)) 3471 urtwn_r88e_fw_reset(sc); 3472 else 3473 urtwn_fw_reset(sc); 3474 } 3475 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3476 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3477 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3478 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3479 R92C_SYS_FUNC_EN_CPUEN); 3480 } 3481 3482 /* download enabled */ 3483 urtwn_write_1(sc, R92C_MCUFWDL, 3484 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3485 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3486 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3487 3488 /* Reset the FWDL checksum. */ 3489 urtwn_write_1(sc, R92C_MCUFWDL, 3490 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3491 3492 DELAY(50); 3493 /* download firmware */ 3494 for (page = 0; len > 0; page++) { 3495 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3496 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3497 if (error != 0) { 3498 aprint_error_dev(sc->sc_dev, 3499 "could not load firmware page %d\n", page); 3500 goto fail; 3501 } 3502 ptr += mlen; 3503 len -= mlen; 3504 } 3505 3506 /* download disable */ 3507 urtwn_write_1(sc, R92C_MCUFWDL, 3508 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3509 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3510 3511 /* Wait for checksum report. */ 3512 for (ntries = 0; ntries < 1000; ntries++) { 3513 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3514 break; 3515 DELAY(5); 3516 } 3517 if (ntries == 1000) { 3518 aprint_error_dev(sc->sc_dev, 3519 "timeout waiting for checksum report\n"); 3520 error = ETIMEDOUT; 3521 goto fail; 3522 } 3523 3524 /* Wait for firmware readiness. */ 3525 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3526 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3527 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3528 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3529 ISSET(sc->chip, URTWN_CHIP_92EU)) 3530 urtwn_r88e_fw_reset(sc); 3531 for (ntries = 0; ntries < 6000; ntries++) { 3532 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3533 break; 3534 DELAY(5); 3535 } 3536 if (ntries == 6000) { 3537 aprint_error_dev(sc->sc_dev, 3538 "timeout waiting for firmware readiness\n"); 3539 error = ETIMEDOUT; 3540 goto fail; 3541 } 3542 fail: 3543 firmware_free(fw, fwlen); 3544 return error; 3545 } 3546 3547 static __inline int 3548 urtwn_dma_init(struct urtwn_softc *sc) 3549 { 3550 3551 return sc->sc_dma_init(sc); 3552 } 3553 3554 static int 3555 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3556 { 3557 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3558 uint32_t reg; 3559 int error; 3560 3561 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3562 3563 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3564 3565 /* Initialize LLT table. */ 3566 error = urtwn_llt_init(sc); 3567 if (error != 0) 3568 return error; 3569 3570 /* Get Tx queues to USB endpoints mapping. */ 3571 hashq = hasnq = haslq = 0; 3572 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3573 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3574 if (MS(reg, R92C_USB_EP_HQ) != 0) 3575 hashq = 1; 3576 if (MS(reg, R92C_USB_EP_NQ) != 0) 3577 hasnq = 1; 3578 if (MS(reg, R92C_USB_EP_LQ) != 0) 3579 haslq = 1; 3580 nqueues = hashq + hasnq + haslq; 3581 if (nqueues == 0) 3582 return EIO; 3583 /* Get the number of pages for each queue. */ 3584 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3585 /* The remaining pages are assigned to the high priority queue. */ 3586 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3587 3588 /* Set number of pages for normal priority queue. */ 3589 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3590 urtwn_write_4(sc, R92C_RQPN, 3591 /* Set number of pages for public queue. */ 3592 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3593 /* Set number of pages for high priority queue. */ 3594 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3595 /* Set number of pages for low priority queue. */ 3596 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3597 /* Load values. */ 3598 R92C_RQPN_LD); 3599 3600 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3601 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3602 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3603 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3604 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3605 3606 /* Set queue to USB pipe mapping. */ 3607 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3608 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3609 if (nqueues == 1) { 3610 if (hashq) { 3611 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3612 } else if (hasnq) { 3613 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3614 } else { 3615 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3616 } 3617 } else if (nqueues == 2) { 3618 /* All 2-endpoints configs have a high priority queue. */ 3619 if (!hashq) { 3620 return EIO; 3621 } 3622 if (hasnq) { 3623 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3624 } else { 3625 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3626 } 3627 } else { 3628 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3629 } 3630 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3631 3632 /* Set Tx/Rx transfer page boundary. */ 3633 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3634 3635 /* Set Tx/Rx transfer page size. */ 3636 urtwn_write_1(sc, R92C_PBP, 3637 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3638 return 0; 3639 } 3640 3641 static int 3642 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3643 { 3644 usb_interface_descriptor_t *id; 3645 uint32_t reg; 3646 int nqueues; 3647 int error; 3648 3649 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3650 3651 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3652 3653 /* Initialize LLT table. */ 3654 error = urtwn_llt_init(sc); 3655 if (error != 0) 3656 return error; 3657 3658 /* Get Tx queues to USB endpoints mapping. */ 3659 id = usbd_get_interface_descriptor(sc->sc_iface); 3660 nqueues = id->bNumEndpoints - 1; 3661 if (nqueues == 0) 3662 return EIO; 3663 3664 /* Set number of pages for normal priority queue. */ 3665 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3666 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3667 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3668 3669 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3670 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3671 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3672 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3673 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3674 3675 /* Set queue to USB pipe mapping. */ 3676 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3677 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3678 if (nqueues == 1) 3679 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3680 else if (nqueues == 2) 3681 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3682 else 3683 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3684 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3685 3686 /* Set Tx/Rx transfer page boundary. */ 3687 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3688 3689 /* Set Tx/Rx transfer page size. */ 3690 urtwn_write_1(sc, R92C_PBP, 3691 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3692 3693 return 0; 3694 } 3695 3696 static void 3697 urtwn_mac_init(struct urtwn_softc *sc) 3698 { 3699 size_t i; 3700 3701 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3702 3703 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3704 3705 /* Write MAC initialization values. */ 3706 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3707 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3708 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3709 rtl8188eu_mac[i].val); 3710 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3711 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3712 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3713 rtl8192eu_mac[i].val); 3714 } else { 3715 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3716 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3717 rtl8192cu_mac[i].val); 3718 } 3719 } 3720 3721 static void 3722 urtwn_bb_init(struct urtwn_softc *sc) 3723 { 3724 const struct rtwn_bb_prog *prog; 3725 uint32_t reg; 3726 uint8_t crystalcap; 3727 size_t i; 3728 3729 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3730 3731 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3732 3733 /* Enable BB and RF. */ 3734 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3735 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3736 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3737 R92C_SYS_FUNC_EN_DIO_RF); 3738 3739 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3740 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3741 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3742 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3743 } 3744 3745 urtwn_write_1(sc, R92C_RF_CTRL, 3746 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3747 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3748 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3749 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3750 3751 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3752 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3753 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3754 urtwn_write_1(sc, 0x15, 0xe9); 3755 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3756 } 3757 3758 /* Select BB programming based on board type. */ 3759 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3760 prog = &rtl8188eu_bb_prog; 3761 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3762 prog = &rtl8192eu_bb_prog; 3763 else if (!(sc->chip & URTWN_CHIP_92C)) { 3764 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3765 prog = &rtl8188ce_bb_prog; 3766 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3767 prog = &rtl8188ru_bb_prog; 3768 } else { 3769 prog = &rtl8188cu_bb_prog; 3770 } 3771 } else { 3772 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3773 prog = &rtl8192ce_bb_prog; 3774 } else { 3775 prog = &rtl8192cu_bb_prog; 3776 } 3777 } 3778 /* Write BB initialization values. */ 3779 for (i = 0; i < prog->count; i++) { 3780 /* additional delay depend on registers */ 3781 switch (prog->regs[i]) { 3782 case 0xfe: 3783 urtwn_delay_ms(sc, 50); 3784 break; 3785 case 0xfd: 3786 urtwn_delay_ms(sc, 5); 3787 break; 3788 case 0xfc: 3789 urtwn_delay_ms(sc, 1); 3790 break; 3791 case 0xfb: 3792 DELAY(50); 3793 break; 3794 case 0xfa: 3795 DELAY(5); 3796 break; 3797 case 0xf9: 3798 DELAY(1); 3799 break; 3800 } 3801 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3802 DELAY(1); 3803 } 3804 3805 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3806 /* 8192C 1T only configuration. */ 3807 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3808 reg = (reg & ~0x00000003) | 0x2; 3809 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3810 3811 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3812 reg = (reg & ~0x00300033) | 0x00200022; 3813 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3814 3815 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3816 reg = (reg & ~0xff000000) | (0x45 << 24); 3817 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3818 3819 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3820 reg = (reg & ~0x000000ff) | 0x23; 3821 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3822 3823 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3824 reg = (reg & ~0x00000030) | (1 << 4); 3825 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3826 3827 reg = urtwn_bb_read(sc, 0xe74); 3828 reg = (reg & ~0x0c000000) | (2 << 26); 3829 urtwn_bb_write(sc, 0xe74, reg); 3830 reg = urtwn_bb_read(sc, 0xe78); 3831 reg = (reg & ~0x0c000000) | (2 << 26); 3832 urtwn_bb_write(sc, 0xe78, reg); 3833 reg = urtwn_bb_read(sc, 0xe7c); 3834 reg = (reg & ~0x0c000000) | (2 << 26); 3835 urtwn_bb_write(sc, 0xe7c, reg); 3836 reg = urtwn_bb_read(sc, 0xe80); 3837 reg = (reg & ~0x0c000000) | (2 << 26); 3838 urtwn_bb_write(sc, 0xe80, reg); 3839 reg = urtwn_bb_read(sc, 0xe88); 3840 reg = (reg & ~0x0c000000) | (2 << 26); 3841 urtwn_bb_write(sc, 0xe88, reg); 3842 } 3843 3844 /* Write AGC values. */ 3845 for (i = 0; i < prog->agccount; i++) { 3846 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3847 DELAY(1); 3848 } 3849 3850 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3851 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3852 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3853 DELAY(1); 3854 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3855 DELAY(1); 3856 } 3857 3858 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3859 crystalcap = sc->r88e_rom[0xb9]; 3860 if (crystalcap == 0x00) 3861 crystalcap = 0x20; 3862 crystalcap &= 0x3f; 3863 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3864 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3865 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3866 crystalcap | crystalcap << 6)); 3867 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3868 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3869 crystalcap = sc->r88e_rom[0xb9]; 3870 if (crystalcap == 0xff) 3871 crystalcap = 0x20; 3872 crystalcap &= 0x3f; 3873 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3874 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3875 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3876 crystalcap | crystalcap << 6)); 3877 } else { 3878 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3879 R92C_HSSI_PARAM2_CCK_HIPWR) { 3880 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3881 } 3882 } 3883 } 3884 3885 static void 3886 urtwn_rf_init(struct urtwn_softc *sc) 3887 { 3888 const struct rtwn_rf_prog *prog; 3889 uint32_t reg, mask, saved; 3890 size_t i, j, idx; 3891 3892 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3893 3894 /* Select RF programming based on board type. */ 3895 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3896 prog = rtl8188eu_rf_prog; 3897 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3898 prog = rtl8192eu_rf_prog; 3899 else if (!(sc->chip & URTWN_CHIP_92C)) { 3900 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3901 prog = rtl8188ce_rf_prog; 3902 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3903 prog = rtl8188ru_rf_prog; 3904 } else { 3905 prog = rtl8188cu_rf_prog; 3906 } 3907 } else { 3908 prog = rtl8192ce_rf_prog; 3909 } 3910 3911 for (i = 0; i < sc->nrxchains; i++) { 3912 /* Save RF_ENV control type. */ 3913 idx = i / 2; 3914 mask = 0xffffU << ((i % 2) * 16); 3915 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3916 3917 /* Set RF_ENV enable. */ 3918 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3919 reg |= 0x100000; 3920 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3921 DELAY(50); 3922 3923 /* Set RF_ENV output high. */ 3924 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3925 reg |= 0x10; 3926 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3927 DELAY(50); 3928 3929 /* Set address and data lengths of RF registers. */ 3930 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3931 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3932 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3933 DELAY(50); 3934 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3935 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3936 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3937 DELAY(50); 3938 3939 /* Write RF initialization values for this chain. */ 3940 for (j = 0; j < prog[i].count; j++) { 3941 if (prog[i].regs[j] >= 0xf9 && 3942 prog[i].regs[j] <= 0xfe) { 3943 /* 3944 * These are fake RF registers offsets that 3945 * indicate a delay is required. 3946 */ 3947 urtwn_delay_ms(sc, 50); 3948 continue; 3949 } 3950 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3951 DELAY(5); 3952 } 3953 3954 /* Restore RF_ENV control type. */ 3955 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3956 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3957 } 3958 3959 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3960 URTWN_CHIP_UMC_A_CUT) { 3961 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3962 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3963 } 3964 3965 /* Cache RF register CHNLBW. */ 3966 for (i = 0; i < 2; i++) { 3967 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3968 } 3969 } 3970 3971 static void 3972 urtwn_cam_init(struct urtwn_softc *sc) 3973 { 3974 uint32_t content, command; 3975 uint8_t idx; 3976 size_t i; 3977 3978 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3979 3980 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3981 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3982 return; 3983 3984 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3985 content = (idx & 3) 3986 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3987 | R92C_CAM_VALID; 3988 3989 command = R92C_CAMCMD_POLLING 3990 | R92C_CAMCMD_WRITE 3991 | R92C_CAM_CTL0(idx); 3992 3993 urtwn_write_4(sc, R92C_CAMWRITE, content); 3994 urtwn_write_4(sc, R92C_CAMCMD, command); 3995 } 3996 3997 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3998 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3999 if (i == 0) { 4000 content = (idx & 3) 4001 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4002 | R92C_CAM_VALID; 4003 } else { 4004 content = 0; 4005 } 4006 4007 command = R92C_CAMCMD_POLLING 4008 | R92C_CAMCMD_WRITE 4009 | R92C_CAM_CTL0(idx) 4010 | i; 4011 4012 urtwn_write_4(sc, R92C_CAMWRITE, content); 4013 urtwn_write_4(sc, R92C_CAMCMD, command); 4014 } 4015 } 4016 4017 /* Invalidate all CAM entries. */ 4018 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4019 } 4020 4021 static void 4022 urtwn_pa_bias_init(struct urtwn_softc *sc) 4023 { 4024 uint8_t reg; 4025 size_t i; 4026 4027 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4028 4029 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4030 4031 for (i = 0; i < sc->nrxchains; i++) { 4032 if (sc->pa_setting & (1U << i)) 4033 continue; 4034 4035 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4036 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4037 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4038 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4039 } 4040 if (!(sc->pa_setting & 0x10)) { 4041 reg = urtwn_read_1(sc, 0x16); 4042 reg = (reg & ~0xf0) | 0x90; 4043 urtwn_write_1(sc, 0x16, reg); 4044 } 4045 } 4046 4047 static void 4048 urtwn_rxfilter_init(struct urtwn_softc *sc) 4049 { 4050 4051 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4052 4053 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4054 4055 /* Initialize Rx filter. */ 4056 /* TODO: use better filter for monitor mode. */ 4057 urtwn_write_4(sc, R92C_RCR, 4058 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4059 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4060 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4061 /* Accept all multicast frames. */ 4062 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4063 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4064 /* Accept all management frames. */ 4065 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4066 /* Reject all control frames. */ 4067 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4068 /* Accept all data frames. */ 4069 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4070 } 4071 4072 static void 4073 urtwn_edca_init(struct urtwn_softc *sc) 4074 { 4075 4076 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4077 4078 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4079 4080 /* set spec SIFS (used in NAV) */ 4081 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4082 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4083 4084 /* set SIFS CCK/OFDM */ 4085 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4086 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4087 4088 /* TXOP */ 4089 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4090 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4091 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4092 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4093 } 4094 4095 static void 4096 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4097 uint16_t power[URTWN_RIDX_COUNT]) 4098 { 4099 uint32_t reg; 4100 4101 URTWNHIST_FUNC(); 4102 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4103 4104 /* Write per-CCK rate Tx power. */ 4105 if (chain == 0) { 4106 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4107 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4108 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4109 4110 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4111 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4112 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4113 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4114 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4115 } else { 4116 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4117 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4118 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4119 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4120 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4121 4122 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4123 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4124 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4125 } 4126 /* Write per-OFDM rate Tx power. */ 4127 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4128 SM(R92C_TXAGC_RATE06, power[ 4]) | 4129 SM(R92C_TXAGC_RATE09, power[ 5]) | 4130 SM(R92C_TXAGC_RATE12, power[ 6]) | 4131 SM(R92C_TXAGC_RATE18, power[ 7])); 4132 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4133 SM(R92C_TXAGC_RATE24, power[ 8]) | 4134 SM(R92C_TXAGC_RATE36, power[ 9]) | 4135 SM(R92C_TXAGC_RATE48, power[10]) | 4136 SM(R92C_TXAGC_RATE54, power[11])); 4137 /* Write per-MCS Tx power. */ 4138 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4139 SM(R92C_TXAGC_MCS00, power[12]) | 4140 SM(R92C_TXAGC_MCS01, power[13]) | 4141 SM(R92C_TXAGC_MCS02, power[14]) | 4142 SM(R92C_TXAGC_MCS03, power[15])); 4143 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4144 SM(R92C_TXAGC_MCS04, power[16]) | 4145 SM(R92C_TXAGC_MCS05, power[17]) | 4146 SM(R92C_TXAGC_MCS06, power[18]) | 4147 SM(R92C_TXAGC_MCS07, power[19])); 4148 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4149 SM(R92C_TXAGC_MCS08, power[20]) | 4150 SM(R92C_TXAGC_MCS09, power[21]) | 4151 SM(R92C_TXAGC_MCS10, power[22]) | 4152 SM(R92C_TXAGC_MCS11, power[23])); 4153 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4154 SM(R92C_TXAGC_MCS12, power[24]) | 4155 SM(R92C_TXAGC_MCS13, power[25]) | 4156 SM(R92C_TXAGC_MCS14, power[26]) | 4157 SM(R92C_TXAGC_MCS15, power[27])); 4158 } 4159 4160 static void 4161 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4162 uint16_t power[URTWN_RIDX_COUNT]) 4163 { 4164 struct r92c_rom *rom = &sc->rom; 4165 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4166 const struct rtwn_txpwr *base; 4167 int ridx, group; 4168 4169 URTWNHIST_FUNC(); 4170 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4171 4172 /* Determine channel group. */ 4173 if (chan <= 3) { 4174 group = 0; 4175 } else if (chan <= 9) { 4176 group = 1; 4177 } else { 4178 group = 2; 4179 } 4180 4181 /* Get original Tx power based on board type and RF chain. */ 4182 if (!(sc->chip & URTWN_CHIP_92C)) { 4183 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4184 base = &rtl8188ru_txagc[chain]; 4185 } else { 4186 base = &rtl8192cu_txagc[chain]; 4187 } 4188 } else { 4189 base = &rtl8192cu_txagc[chain]; 4190 } 4191 4192 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4193 if (sc->regulatory == 0) { 4194 for (ridx = 0; ridx <= 3; ridx++) { 4195 power[ridx] = base->pwr[0][ridx]; 4196 } 4197 } 4198 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4199 if (sc->regulatory == 3) { 4200 power[ridx] = base->pwr[0][ridx]; 4201 /* Apply vendor limits. */ 4202 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4203 maxpow = rom->ht40_max_pwr[group]; 4204 } else { 4205 maxpow = rom->ht20_max_pwr[group]; 4206 } 4207 maxpow = (maxpow >> (chain * 4)) & 0xf; 4208 if (power[ridx] > maxpow) { 4209 power[ridx] = maxpow; 4210 } 4211 } else if (sc->regulatory == 1) { 4212 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4213 power[ridx] = base->pwr[group][ridx]; 4214 } 4215 } else if (sc->regulatory != 2) { 4216 power[ridx] = base->pwr[0][ridx]; 4217 } 4218 } 4219 4220 /* Compute per-CCK rate Tx power. */ 4221 cckpow = rom->cck_tx_pwr[chain][group]; 4222 for (ridx = 0; ridx <= 3; ridx++) { 4223 power[ridx] += cckpow; 4224 if (power[ridx] > R92C_MAX_TX_PWR) { 4225 power[ridx] = R92C_MAX_TX_PWR; 4226 } 4227 } 4228 4229 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4230 if (sc->ntxchains > 1) { 4231 /* Apply reduction for 2 spatial streams. */ 4232 diff = rom->ht40_2s_tx_pwr_diff[group]; 4233 diff = (diff >> (chain * 4)) & 0xf; 4234 htpow = (htpow > diff) ? htpow - diff : 0; 4235 } 4236 4237 /* Compute per-OFDM rate Tx power. */ 4238 diff = rom->ofdm_tx_pwr_diff[group]; 4239 diff = (diff >> (chain * 4)) & 0xf; 4240 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4241 for (ridx = 4; ridx <= 11; ridx++) { 4242 power[ridx] += ofdmpow; 4243 if (power[ridx] > R92C_MAX_TX_PWR) { 4244 power[ridx] = R92C_MAX_TX_PWR; 4245 } 4246 } 4247 4248 /* Compute per-MCS Tx power. */ 4249 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4250 diff = rom->ht20_tx_pwr_diff[group]; 4251 diff = (diff >> (chain * 4)) & 0xf; 4252 htpow += diff; /* HT40->HT20 correction. */ 4253 } 4254 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4255 power[ridx] += htpow; 4256 if (power[ridx] > R92C_MAX_TX_PWR) { 4257 power[ridx] = R92C_MAX_TX_PWR; 4258 } 4259 } 4260 #ifdef URTWN_DEBUG 4261 if (urtwn_debug & DBG_RF) { 4262 /* Dump per-rate Tx power values. */ 4263 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4264 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4265 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4266 } 4267 #endif 4268 } 4269 4270 void 4271 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4272 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4273 { 4274 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4275 const struct rtwn_r88e_txpwr *base; 4276 int ridx, group; 4277 4278 URTWNHIST_FUNC(); 4279 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4280 4281 /* Determine channel group. */ 4282 if (chan <= 2) 4283 group = 0; 4284 else if (chan <= 5) 4285 group = 1; 4286 else if (chan <= 8) 4287 group = 2; 4288 else if (chan <= 11) 4289 group = 3; 4290 else if (chan <= 13) 4291 group = 4; 4292 else 4293 group = 5; 4294 4295 /* Get original Tx power based on board type and RF chain. */ 4296 base = &rtl8188eu_txagc[chain]; 4297 4298 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4299 if (sc->regulatory == 0) { 4300 for (ridx = 0; ridx <= 3; ridx++) 4301 power[ridx] = base->pwr[0][ridx]; 4302 } 4303 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4304 if (sc->regulatory == 3) 4305 power[ridx] = base->pwr[0][ridx]; 4306 else if (sc->regulatory == 1) { 4307 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4308 power[ridx] = base->pwr[group][ridx]; 4309 } else if (sc->regulatory != 2) 4310 power[ridx] = base->pwr[0][ridx]; 4311 } 4312 4313 /* Compute per-CCK rate Tx power. */ 4314 cckpow = sc->cck_tx_pwr[group]; 4315 for (ridx = 0; ridx <= 3; ridx++) { 4316 power[ridx] += cckpow; 4317 if (power[ridx] > R92C_MAX_TX_PWR) 4318 power[ridx] = R92C_MAX_TX_PWR; 4319 } 4320 4321 htpow = sc->ht40_tx_pwr[group]; 4322 4323 /* Compute per-OFDM rate Tx power. */ 4324 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4325 for (ridx = 4; ridx <= 11; ridx++) { 4326 power[ridx] += ofdmpow; 4327 if (power[ridx] > R92C_MAX_TX_PWR) 4328 power[ridx] = R92C_MAX_TX_PWR; 4329 } 4330 4331 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4332 for (ridx = 12; ridx <= 27; ridx++) { 4333 power[ridx] += bw20pow; 4334 if (power[ridx] > R92C_MAX_TX_PWR) 4335 power[ridx] = R92C_MAX_TX_PWR; 4336 } 4337 } 4338 4339 static void 4340 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4341 { 4342 uint16_t power[URTWN_RIDX_COUNT]; 4343 size_t i; 4344 4345 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4346 4347 for (i = 0; i < sc->ntxchains; i++) { 4348 /* Compute per-rate Tx power values. */ 4349 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4350 ISSET(sc->chip, URTWN_CHIP_92EU)) 4351 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4352 else 4353 urtwn_get_txpower(sc, i, chan, ht40m, power); 4354 /* Write per-rate Tx power values to hardware. */ 4355 urtwn_write_txpower(sc, i, power); 4356 } 4357 } 4358 4359 static void 4360 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4361 { 4362 struct ieee80211com *ic = &sc->sc_ic; 4363 u_int chan; 4364 size_t i; 4365 4366 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4367 4368 URTWNHIST_FUNC(); 4369 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4370 4371 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4372 4373 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4374 chan += 2; 4375 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4376 chan -= 2; 4377 } 4378 4379 /* Set Tx power for this new channel. */ 4380 urtwn_set_txpower(sc, chan, ht40m); 4381 4382 for (i = 0; i < sc->nrxchains; i++) { 4383 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4384 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4385 } 4386 4387 if (ht40m) { 4388 /* Is secondary channel below or above primary? */ 4389 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4390 uint32_t reg; 4391 4392 urtwn_write_1(sc, R92C_BWOPMODE, 4393 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4394 4395 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4396 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4397 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4398 4399 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4400 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4401 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4402 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4403 4404 /* Set CCK side band. */ 4405 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4406 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4407 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4408 4409 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4410 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4411 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4412 4413 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4414 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4415 ~R92C_FPGA0_ANAPARAM2_CBW20); 4416 4417 reg = urtwn_bb_read(sc, 0x818); 4418 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4419 urtwn_bb_write(sc, 0x818, reg); 4420 4421 /* Select 40MHz bandwidth. */ 4422 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4423 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4424 } else { 4425 urtwn_write_1(sc, R92C_BWOPMODE, 4426 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4427 4428 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4429 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4430 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4431 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4432 4433 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4434 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4435 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4436 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4437 R92C_FPGA0_ANAPARAM2_CBW20); 4438 } 4439 4440 /* Select 20MHz bandwidth. */ 4441 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4442 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4443 (ISSET(sc->chip, URTWN_CHIP_88E) || 4444 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4445 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4446 } 4447 } 4448 4449 static void 4450 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4451 { 4452 4453 URTWNHIST_FUNC(); 4454 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4455 4456 uint32_t addaBackup[16], iqkBackup[4], piMode; 4457 4458 #ifdef notyet 4459 uint32_t odfm0_agccore_regs[3]; 4460 uint32_t ant_regs[3]; 4461 uint32_t rf_regs[8]; 4462 #endif 4463 uint32_t reg0, reg1, reg2; 4464 int i, attempt; 4465 4466 #ifdef notyet 4467 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4468 R92E_STBC_SETTING + 2)); 4469 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4470 /* Save AGCCORE regs. */ 4471 for (i = 0; i < sc->nrxchains; i++) { 4472 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4473 R92C_OFDM0_AGCCORE1(i)); 4474 } 4475 #endif 4476 /* Save BB regs. */ 4477 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4478 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4479 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4480 4481 /* Save adda regs to be restored when finished. */ 4482 for (i = 0; i < __arraycount(addaReg); i++) 4483 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4484 /* Save mac regs. */ 4485 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4486 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4487 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4488 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4489 4490 #ifdef notyet 4491 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4492 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4493 4494 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4495 for (i = 0; i < sc->nrxchains; i++) 4496 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4497 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4498 #endif 4499 4500 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4501 R92C_HSSI_PARAM1_PI); 4502 if (piMode == 0) { 4503 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4504 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4505 R92C_HSSI_PARAM1_PI); 4506 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4507 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4508 R92C_HSSI_PARAM1_PI); 4509 } 4510 4511 attempt = 1; 4512 4513 next_attempt: 4514 4515 /* Set mac regs for calibration. */ 4516 for (i = 0; i < __arraycount(addaReg); i++) { 4517 urtwn_bb_write(sc, addaReg[i], 4518 addaReg[__arraycount(addaReg) - 1]); 4519 } 4520 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4521 R92C_CCK0_AFESETTING)); 4522 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4523 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4524 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4525 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4526 4527 if (sc->ntxchains > 1) 4528 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4529 4530 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4531 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4532 ~R92C_BCN_CTRL_EN_BCN)); 4533 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4534 ~R92C_BCN_CTRL_EN_BCN)); 4535 4536 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4537 ~R92C_GPIO_MUXCFG_ENBT)); 4538 4539 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4540 4541 if (sc->ntxchains > 1) 4542 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4543 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4544 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4545 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4546 4547 /* Restore BB regs. */ 4548 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4549 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4550 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4551 4552 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4553 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4554 if (sc->nrxchains > 1) 4555 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4556 4557 if (attempt-- > 0) 4558 goto next_attempt; 4559 4560 /* Restore mode. */ 4561 if (piMode == 0) { 4562 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4563 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4564 ~R92C_HSSI_PARAM1_PI); 4565 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4566 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4567 ~R92C_HSSI_PARAM1_PI); 4568 } 4569 4570 #ifdef notyet 4571 for (i = 0; i < sc->nrxchains; i++) { 4572 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4573 odfm0_agccore_regs[i]); 4574 } 4575 #endif 4576 4577 /* Restore adda regs. */ 4578 for (i = 0; i < __arraycount(addaReg); i++) 4579 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4580 /* Restore mac regs. */ 4581 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4582 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4583 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4584 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4585 4586 #ifdef notyet 4587 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4588 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4589 4590 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4591 for (i = 0; i < sc->nrxchains; i++) 4592 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4593 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4594 #endif 4595 } 4596 4597 static void 4598 urtwn_lc_calib(struct urtwn_softc *sc) 4599 { 4600 uint32_t rf_ac[2]; 4601 uint8_t txmode; 4602 size_t i; 4603 4604 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4605 4606 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4607 4608 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4609 if ((txmode & 0x70) != 0) { 4610 /* Disable all continuous Tx. */ 4611 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4612 4613 /* Set RF mode to standby mode. */ 4614 for (i = 0; i < sc->nrxchains; i++) { 4615 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4616 urtwn_rf_write(sc, i, R92C_RF_AC, 4617 RW(rf_ac[i], R92C_RF_AC_MODE, 4618 R92C_RF_AC_MODE_STANDBY)); 4619 } 4620 } else { 4621 /* Block all Tx queues. */ 4622 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4623 } 4624 /* Start calibration. */ 4625 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4626 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4627 4628 /* Give calibration the time to complete. */ 4629 urtwn_delay_ms(sc, 100); 4630 4631 /* Restore configuration. */ 4632 if ((txmode & 0x70) != 0) { 4633 /* Restore Tx mode. */ 4634 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4635 /* Restore RF mode. */ 4636 for (i = 0; i < sc->nrxchains; i++) { 4637 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4638 } 4639 } else { 4640 /* Unblock all Tx queues. */ 4641 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4642 } 4643 } 4644 4645 static void 4646 urtwn_temp_calib(struct urtwn_softc *sc) 4647 { 4648 int temp, t_meter_reg; 4649 4650 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4651 4652 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4653 4654 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4655 t_meter_reg = R92C_RF_T_METER; 4656 else 4657 t_meter_reg = R92E_RF_T_METER; 4658 4659 if (sc->thcal_state == 0) { 4660 /* Start measuring temperature. */ 4661 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4662 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4663 sc->thcal_state = 1; 4664 return; 4665 } 4666 sc->thcal_state = 0; 4667 4668 /* Read measured temperature. */ 4669 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4670 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4671 if (temp == 0) /* Read failed, skip. */ 4672 return; 4673 4674 /* 4675 * Redo LC calibration if temperature changed significantly since 4676 * last calibration. 4677 */ 4678 if (sc->thcal_lctemp == 0) { 4679 /* First LC calibration is performed in urtwn_init(). */ 4680 sc->thcal_lctemp = temp; 4681 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4682 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4683 sc->thcal_lctemp, temp, 0, 0); 4684 urtwn_lc_calib(sc); 4685 /* Record temperature of last LC calibration. */ 4686 sc->thcal_lctemp = temp; 4687 } 4688 } 4689 4690 static int 4691 urtwn_init(struct ifnet *ifp) 4692 { 4693 struct urtwn_softc *sc = ifp->if_softc; 4694 struct ieee80211com *ic = &sc->sc_ic; 4695 struct urtwn_rx_data *data; 4696 uint32_t reg; 4697 size_t i; 4698 int error; 4699 4700 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4701 4702 urtwn_stop(ifp, 0); 4703 4704 mutex_enter(&sc->sc_write_mtx); 4705 4706 mutex_enter(&sc->sc_task_mtx); 4707 /* Init host async commands ring. */ 4708 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4709 mutex_exit(&sc->sc_task_mtx); 4710 4711 mutex_enter(&sc->sc_fwcmd_mtx); 4712 /* Init firmware commands ring. */ 4713 sc->fwcur = 0; 4714 mutex_exit(&sc->sc_fwcmd_mtx); 4715 4716 /* Allocate Tx/Rx buffers. */ 4717 error = urtwn_alloc_rx_list(sc); 4718 if (error != 0) { 4719 aprint_error_dev(sc->sc_dev, 4720 "could not allocate Rx buffers\n"); 4721 goto fail; 4722 } 4723 error = urtwn_alloc_tx_list(sc); 4724 if (error != 0) { 4725 aprint_error_dev(sc->sc_dev, 4726 "could not allocate Tx buffers\n"); 4727 goto fail; 4728 } 4729 4730 /* Power on adapter. */ 4731 error = urtwn_power_on(sc); 4732 if (error != 0) 4733 goto fail; 4734 4735 /* Initialize DMA. */ 4736 error = urtwn_dma_init(sc); 4737 if (error != 0) 4738 goto fail; 4739 4740 /* Set info size in Rx descriptors (in 64-bit words). */ 4741 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4742 4743 /* Init interrupts. */ 4744 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4745 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4746 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4747 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4748 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4749 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4750 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4751 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4752 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4753 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4754 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4755 } 4756 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4757 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4758 } else { 4759 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4760 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4761 } 4762 4763 /* Set MAC address. */ 4764 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4765 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4766 4767 /* Set initial network type. */ 4768 reg = urtwn_read_4(sc, R92C_CR); 4769 switch (ic->ic_opmode) { 4770 case IEEE80211_M_STA: 4771 default: 4772 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4773 break; 4774 4775 case IEEE80211_M_IBSS: 4776 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4777 break; 4778 } 4779 urtwn_write_4(sc, R92C_CR, reg); 4780 4781 /* Set response rate */ 4782 reg = urtwn_read_4(sc, R92C_RRSR); 4783 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4784 urtwn_write_4(sc, R92C_RRSR, reg); 4785 4786 /* SIFS (used in NAV) */ 4787 urtwn_write_2(sc, R92C_SPEC_SIFS, 4788 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4789 4790 /* Set short/long retry limits. */ 4791 urtwn_write_2(sc, R92C_RL, 4792 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4793 4794 /* Initialize EDCA parameters. */ 4795 urtwn_edca_init(sc); 4796 4797 /* Setup rate fallback. */ 4798 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4799 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4800 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4801 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4802 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4803 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4804 } 4805 4806 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4807 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4808 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4809 /* Set ACK timeout. */ 4810 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4811 4812 /* Setup USB aggregation. */ 4813 /* Tx */ 4814 reg = urtwn_read_4(sc, R92C_TDECTRL); 4815 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4816 urtwn_write_4(sc, R92C_TDECTRL, reg); 4817 /* Rx */ 4818 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4819 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4820 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4821 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4822 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4823 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4824 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4825 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4826 ISSET(sc->chip, URTWN_CHIP_92EU)) 4827 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4828 else 4829 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4830 4831 /* Initialize beacon parameters. */ 4832 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4833 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4834 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4835 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4836 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4837 4838 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4839 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4840 /* Setup AMPDU aggregation. */ 4841 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4842 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4843 urtwn_write_2(sc, 0x4ca, 0x0708); 4844 4845 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4846 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4847 } 4848 4849 /* Load 8051 microcode. */ 4850 error = urtwn_load_firmware(sc); 4851 if (error != 0) 4852 goto fail; 4853 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4854 4855 /* Initialize MAC/BB/RF blocks. */ 4856 /* 4857 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4858 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4859 * XXX: This setting should be removed from rtl8192cu_mac[]. 4860 */ 4861 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4862 urtwn_rxfilter_init(sc); // reset R92C_RCR 4863 urtwn_bb_init(sc); 4864 urtwn_rf_init(sc); 4865 4866 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4867 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4868 urtwn_write_2(sc, R92C_CR, 4869 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4870 R92C_CR_MACRXEN); 4871 } 4872 4873 /* Turn CCK and OFDM blocks on. */ 4874 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4875 reg |= R92C_RFMOD_CCK_EN; 4876 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4877 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4878 reg |= R92C_RFMOD_OFDM_EN; 4879 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4880 4881 /* Clear per-station keys table. */ 4882 urtwn_cam_init(sc); 4883 4884 /* Enable hardware sequence numbering. */ 4885 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4886 4887 /* Perform LO and IQ calibrations. */ 4888 urtwn_iq_calib(sc, sc->iqk_inited); 4889 sc->iqk_inited = true; 4890 4891 /* Perform LC calibration. */ 4892 urtwn_lc_calib(sc); 4893 4894 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4895 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4896 /* Fix USB interference issue. */ 4897 urtwn_write_1(sc, 0xfe40, 0xe0); 4898 urtwn_write_1(sc, 0xfe41, 0x8d); 4899 urtwn_write_1(sc, 0xfe42, 0x80); 4900 urtwn_write_4(sc, 0x20c, 0xfd0320); 4901 4902 urtwn_pa_bias_init(sc); 4903 } 4904 4905 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4906 !(sc->chip & URTWN_CHIP_92EU)) { 4907 /* 1T1R */ 4908 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4909 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4910 } 4911 4912 /* Initialize GPIO setting. */ 4913 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4914 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4915 4916 /* Fix for lower temperature. */ 4917 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4918 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4919 urtwn_write_1(sc, 0x15, 0xe9); 4920 4921 /* Set default channel. */ 4922 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4923 4924 /* Queue Rx xfers. */ 4925 for (size_t j = 0; j < sc->rx_npipe; j++) { 4926 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4927 data = &sc->rx_data[j][i]; 4928 usbd_setup_xfer(data->xfer, data, data->buf, 4929 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4930 urtwn_rxeof); 4931 error = usbd_transfer(data->xfer); 4932 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4933 error != USBD_IN_PROGRESS)) 4934 goto fail; 4935 } 4936 } 4937 4938 /* We're ready to go. */ 4939 ifp->if_flags &= ~IFF_OACTIVE; 4940 ifp->if_flags |= IFF_RUNNING; 4941 sc->sc_running = true; 4942 4943 mutex_exit(&sc->sc_write_mtx); 4944 4945 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4946 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4947 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4948 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4949 urtwn_wait_async(sc); 4950 4951 return 0; 4952 4953 fail: 4954 mutex_exit(&sc->sc_write_mtx); 4955 4956 urtwn_stop(ifp, 1); 4957 return error; 4958 } 4959 4960 static void 4961 urtwn_stop(struct ifnet *ifp, int disable) 4962 { 4963 struct urtwn_softc *sc = ifp->if_softc; 4964 struct ieee80211com *ic = &sc->sc_ic; 4965 size_t i; 4966 int s; 4967 4968 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4969 4970 s = splusb(); 4971 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4972 urtwn_wait_async(sc); 4973 splx(s); 4974 4975 sc->tx_timer = 0; 4976 ifp->if_timer = 0; 4977 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4978 4979 callout_stop(&sc->sc_scan_to); 4980 callout_stop(&sc->sc_calib_to); 4981 4982 /* Abort Tx. */ 4983 for (i = 0; i < sc->tx_npipe; i++) { 4984 if (sc->tx_pipe[i] != NULL) 4985 usbd_abort_pipe(sc->tx_pipe[i]); 4986 } 4987 4988 /* Stop Rx pipe. */ 4989 for (i = 0; i < sc->rx_npipe; i++) { 4990 if (sc->rx_pipe[i] != NULL) 4991 usbd_abort_pipe(sc->rx_pipe[i]); 4992 } 4993 4994 /* Free Tx/Rx buffers. */ 4995 urtwn_free_tx_list(sc); 4996 urtwn_free_rx_list(sc); 4997 4998 sc->sc_running = false; 4999 if (disable) 5000 urtwn_chip_stop(sc); 5001 } 5002 5003 static int 5004 urtwn_reset(struct ifnet *ifp) 5005 { 5006 struct urtwn_softc *sc = ifp->if_softc; 5007 struct ieee80211com *ic = &sc->sc_ic; 5008 5009 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5010 return ENETRESET; 5011 5012 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5013 5014 return 0; 5015 } 5016 5017 static void 5018 urtwn_chip_stop(struct urtwn_softc *sc) 5019 { 5020 uint32_t reg; 5021 bool disabled = true; 5022 5023 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5024 5025 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5026 ISSET(sc->chip, URTWN_CHIP_92EU)) 5027 return; 5028 5029 mutex_enter(&sc->sc_write_mtx); 5030 5031 /* 5032 * RF Off Sequence 5033 */ 5034 /* Pause MAC TX queue */ 5035 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5036 5037 /* Disable RF */ 5038 urtwn_rf_write(sc, 0, 0, 0); 5039 5040 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5041 5042 /* Reset BB state machine */ 5043 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5044 R92C_SYS_FUNC_EN_USBD | 5045 R92C_SYS_FUNC_EN_USBA | 5046 R92C_SYS_FUNC_EN_BB_GLB_RST); 5047 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5048 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5049 5050 /* 5051 * Reset digital sequence 5052 */ 5053 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5054 /* Reset MCU ready status */ 5055 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5056 /* If firmware in ram code, do reset */ 5057 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5058 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5059 ISSET(sc->chip, URTWN_CHIP_92EU)) 5060 urtwn_r88e_fw_reset(sc); 5061 else 5062 urtwn_fw_reset(sc); 5063 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5064 } 5065 } 5066 5067 /* Reset MAC and Enable 8051 */ 5068 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5069 5070 /* Reset MCU ready status */ 5071 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5072 5073 if (disabled) { 5074 /* Disable MAC clock */ 5075 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5076 /* Disable AFE PLL */ 5077 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5078 /* Gated AFE DIG_CLOCK */ 5079 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5080 /* Isolated digital to PON */ 5081 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5082 } 5083 5084 /* 5085 * Pull GPIO PIN to balance level and LED control 5086 */ 5087 /* 1. Disable GPIO[7:0] */ 5088 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5089 5090 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5091 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5092 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5093 5094 /* Disable GPIO[10:8] */ 5095 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5096 5097 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5098 reg |= (((reg & 0x000f) << 4) | 0x0780); 5099 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5100 5101 /* Disable LED0 & 1 */ 5102 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5103 5104 /* 5105 * Reset digital sequence 5106 */ 5107 if (disabled) { 5108 /* Disable ELDR clock */ 5109 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5110 /* Isolated ELDR to PON */ 5111 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5112 } 5113 5114 /* 5115 * Disable analog sequence 5116 */ 5117 if (disabled) { 5118 /* Disable A15 power */ 5119 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5120 /* Disable digital core power */ 5121 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5122 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5123 ~R92C_LDOV12D_CTRL_LDV12_EN); 5124 } 5125 5126 /* Enter PFM mode */ 5127 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5128 5129 /* Set USB suspend */ 5130 urtwn_write_2(sc, R92C_APS_FSMCO, 5131 R92C_APS_FSMCO_APDM_HOST | 5132 R92C_APS_FSMCO_AFSM_HSUS | 5133 R92C_APS_FSMCO_PFM_ALDN); 5134 5135 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5136 5137 mutex_exit(&sc->sc_write_mtx); 5138 } 5139 5140 static void 5141 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5142 { 5143 if (sc->sc_running == false) 5144 DELAY(ms * 1000); 5145 else 5146 usbd_delay_ms(sc->sc_udev, ms); 5147 } 5148 5149 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5150 5151 #ifdef _MODULE 5152 #include "ioconf.c" 5153 #endif 5154 5155 static int 5156 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5157 { 5158 int error = 0; 5159 5160 switch (cmd) { 5161 case MODULE_CMD_INIT: 5162 #ifdef _MODULE 5163 error = config_init_component(cfdriver_ioconf_urtwn, 5164 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5165 #endif 5166 return error; 5167 case MODULE_CMD_FINI: 5168 #ifdef _MODULE 5169 error = config_fini_component(cfdriver_ioconf_urtwn, 5170 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5171 #endif 5172 return error; 5173 default: 5174 return ENOTTY; 5175 } 5176 } 5177
Indexes created Fri Oct 03 02:09:57 GMT 2025