if_urtwn.c revision 1.84
1 /* $NetBSD: if_urtwn.c,v 1.84 2020/03/15 23:04:51 thorpej Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.84 2020/03/15 23:04:51 thorpej Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 216 /* URTWN_RTL8192EU */ 217 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 218 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 219 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 220 }; 221 #undef URTWN_DEV 222 #undef URTWN_RTL8188E_DEV 223 #undef URTWN_RTL8192EU_DEV 224 225 static int urtwn_match(device_t, cfdata_t, void *); 226 static void urtwn_attach(device_t, device_t, void *); 227 static int urtwn_detach(device_t, int); 228 static int urtwn_activate(device_t, enum devact); 229 230 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 231 urtwn_attach, urtwn_detach, urtwn_activate); 232 233 static int urtwn_open_pipes(struct urtwn_softc *); 234 static void urtwn_close_pipes(struct urtwn_softc *); 235 static int urtwn_alloc_rx_list(struct urtwn_softc *); 236 static void urtwn_free_rx_list(struct urtwn_softc *); 237 static int urtwn_alloc_tx_list(struct urtwn_softc *); 238 static void urtwn_free_tx_list(struct urtwn_softc *); 239 static void urtwn_task(void *); 240 static void urtwn_do_async(struct urtwn_softc *, 241 void (*)(struct urtwn_softc *, void *), void *, int); 242 static void urtwn_wait_async(struct urtwn_softc *); 243 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 244 int); 245 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 246 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 247 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 248 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 249 int); 250 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 251 int); 252 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 253 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 254 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 255 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 256 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 257 uint32_t); 258 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 259 uint32_t); 260 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 261 uint32_t); 262 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 263 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 264 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 265 static void urtwn_efuse_read(struct urtwn_softc *); 266 static void urtwn_efuse_switch_power(struct urtwn_softc *); 267 static int urtwn_read_chipid(struct urtwn_softc *); 268 #ifdef URTWN_DEBUG 269 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 270 #endif 271 static void urtwn_read_rom(struct urtwn_softc *); 272 static void urtwn_r88e_read_rom(struct urtwn_softc *); 273 static int urtwn_media_change(struct ifnet *); 274 static int urtwn_ra_init(struct urtwn_softc *); 275 static int urtwn_get_nettype(struct urtwn_softc *); 276 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 277 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 278 static void urtwn_set_led(struct urtwn_softc *, int, int); 279 static void urtwn_calib_to(void *); 280 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 281 static void urtwn_next_scan(void *); 282 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 283 int); 284 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 285 static int urtwn_wme_update(struct ieee80211com *); 286 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 287 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 288 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 289 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 290 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 291 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 292 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 293 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 294 struct ieee80211_node *, struct urtwn_tx_data *); 295 static struct urtwn_tx_data * 296 urtwn_get_tx_data(struct urtwn_softc *, size_t); 297 static void urtwn_start(struct ifnet *); 298 static void urtwn_watchdog(struct ifnet *); 299 static int urtwn_ioctl(struct ifnet *, u_long, void *); 300 static int urtwn_r92c_power_on(struct urtwn_softc *); 301 static int urtwn_r92e_power_on(struct urtwn_softc *); 302 static int urtwn_r88e_power_on(struct urtwn_softc *); 303 static int urtwn_llt_init(struct urtwn_softc *); 304 static void urtwn_fw_reset(struct urtwn_softc *); 305 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 306 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 307 static int urtwn_load_firmware(struct urtwn_softc *); 308 static int urtwn_r92c_dma_init(struct urtwn_softc *); 309 static int urtwn_r88e_dma_init(struct urtwn_softc *); 310 static void urtwn_mac_init(struct urtwn_softc *); 311 static void urtwn_bb_init(struct urtwn_softc *); 312 static void urtwn_rf_init(struct urtwn_softc *); 313 static void urtwn_cam_init(struct urtwn_softc *); 314 static void urtwn_pa_bias_init(struct urtwn_softc *); 315 static void urtwn_rxfilter_init(struct urtwn_softc *); 316 static void urtwn_edca_init(struct urtwn_softc *); 317 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 318 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 319 uint16_t[]); 320 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 321 u_int, uint16_t[]); 322 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 323 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 324 u_int); 325 static void urtwn_iq_calib(struct urtwn_softc *, bool); 326 static void urtwn_lc_calib(struct urtwn_softc *); 327 static void urtwn_temp_calib(struct urtwn_softc *); 328 static int urtwn_init(struct ifnet *); 329 static void urtwn_stop(struct ifnet *, int); 330 static int urtwn_reset(struct ifnet *); 331 static void urtwn_chip_stop(struct urtwn_softc *); 332 static void urtwn_newassoc(struct ieee80211_node *, int); 333 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 334 335 /* Aliases. */ 336 #define urtwn_bb_write urtwn_write_4 337 #define urtwn_bb_read urtwn_read_4 338 339 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 340 341 static const uint16_t addaReg[] = { 342 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 343 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 344 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 345 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 346 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 347 }; 348 349 static int 350 urtwn_match(device_t parent, cfdata_t match, void *aux) 351 { 352 struct usb_attach_arg *uaa = aux; 353 354 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 355 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 356 } 357 358 static void 359 urtwn_attach(device_t parent, device_t self, void *aux) 360 { 361 struct urtwn_softc *sc = device_private(self); 362 struct ieee80211com *ic = &sc->sc_ic; 363 struct ifnet *ifp = &sc->sc_if; 364 struct usb_attach_arg *uaa = aux; 365 char *devinfop; 366 const struct urtwn_dev *dev; 367 usb_device_request_t req; 368 size_t i; 369 int error; 370 371 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 372 373 sc->sc_dev = self; 374 sc->sc_udev = uaa->uaa_device; 375 376 sc->chip = 0; 377 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 378 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 379 SET(sc->chip, URTWN_CHIP_88E); 380 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 381 SET(sc->chip, URTWN_CHIP_92EU); 382 383 aprint_naive("\n"); 384 aprint_normal("\n"); 385 386 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 387 aprint_normal_dev(self, "%s\n", devinfop); 388 usbd_devinfo_free(devinfop); 389 390 req.bmRequestType = UT_WRITE_DEVICE; 391 req.bRequest = UR_SET_FEATURE; 392 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 393 USETW(req.wIndex, UHF_PORT_SUSPEND); 394 USETW(req.wLength, 0); 395 396 (void) usbd_do_request(sc->sc_udev, &req, 0); 397 398 cv_init(&sc->sc_task_cv, "urtwntsk"); 399 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 400 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 401 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 402 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 403 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 404 405 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 406 407 callout_init(&sc->sc_scan_to, 0); 408 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 409 callout_init(&sc->sc_calib_to, 0); 410 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 411 412 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 413 RND_TYPE_NET, RND_FLAG_DEFAULT); 414 415 error = usbd_set_config_no(sc->sc_udev, 1, 0); 416 if (error != 0) { 417 aprint_error_dev(self, "failed to set configuration" 418 ", err=%s\n", usbd_errstr(error)); 419 goto fail; 420 } 421 422 /* Get the first interface handle. */ 423 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 424 if (error != 0) { 425 aprint_error_dev(self, "could not get interface handle\n"); 426 goto fail; 427 } 428 429 error = urtwn_read_chipid(sc); 430 if (error != 0) { 431 aprint_error_dev(self, "unsupported test chip\n"); 432 goto fail; 433 } 434 435 /* Determine number of Tx/Rx chains. */ 436 if (sc->chip & URTWN_CHIP_92C) { 437 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 438 sc->nrxchains = 2; 439 } else if (sc->chip & URTWN_CHIP_92EU) { 440 sc->ntxchains = 2; 441 sc->nrxchains = 2; 442 } else { 443 sc->ntxchains = 1; 444 sc->nrxchains = 1; 445 } 446 447 if (ISSET(sc->chip, URTWN_CHIP_88E) || 448 ISSET(sc->chip, URTWN_CHIP_92EU)) 449 urtwn_r88e_read_rom(sc); 450 else 451 urtwn_read_rom(sc); 452 453 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 454 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 455 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 456 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 457 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 458 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 459 "8188CUS", sc->ntxchains, sc->nrxchains, 460 ether_sprintf(ic->ic_myaddr)); 461 462 error = urtwn_open_pipes(sc); 463 if (error != 0) { 464 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 465 goto fail; 466 } 467 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 468 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 469 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 470 471 /* 472 * Setup the 802.11 device. 473 */ 474 ic->ic_ifp = ifp; 475 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 476 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 477 ic->ic_state = IEEE80211_S_INIT; 478 479 /* Set device capabilities. */ 480 ic->ic_caps = 481 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 482 IEEE80211_C_IBSS | /* IBSS mode supported */ 483 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 484 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 485 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 486 IEEE80211_C_WME | /* 802.11e */ 487 IEEE80211_C_WPA; /* 802.11i */ 488 489 /* Set supported .11b and .11g rates. */ 490 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 491 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 492 493 /* Set supported .11b and .11g channels (1 through 14). */ 494 for (i = 1; i <= 14; i++) { 495 ic->ic_channels[i].ic_freq = 496 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 497 ic->ic_channels[i].ic_flags = 498 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 499 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 500 } 501 502 ifp->if_softc = sc; 503 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 504 ifp->if_init = urtwn_init; 505 ifp->if_ioctl = urtwn_ioctl; 506 ifp->if_start = urtwn_start; 507 ifp->if_watchdog = urtwn_watchdog; 508 IFQ_SET_READY(&ifp->if_snd); 509 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 510 511 if_initialize(ifp); 512 ieee80211_ifattach(ic); 513 514 /* override default methods */ 515 ic->ic_newassoc = urtwn_newassoc; 516 ic->ic_reset = urtwn_reset; 517 ic->ic_wme.wme_update = urtwn_wme_update; 518 519 /* Override state transition machine. */ 520 sc->sc_newstate = ic->ic_newstate; 521 ic->ic_newstate = urtwn_newstate; 522 523 /* XXX media locking needs revisiting */ 524 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 525 ieee80211_media_init_with_lock(ic, 526 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 527 528 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 529 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 530 &sc->sc_drvbpf); 531 532 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 533 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 534 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 535 536 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 537 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 538 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 539 540 ifp->if_percpuq = if_percpuq_create(ifp); 541 if_register(ifp); 542 543 ieee80211_announce(ic); 544 545 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 546 547 if (!pmf_device_register(self, NULL, NULL)) 548 aprint_error_dev(self, "couldn't establish power handler\n"); 549 550 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 551 return; 552 553 fail: 554 sc->sc_dying = 1; 555 aprint_error_dev(self, "attach failed\n"); 556 } 557 558 static int 559 urtwn_detach(device_t self, int flags) 560 { 561 struct urtwn_softc *sc = device_private(self); 562 struct ifnet *ifp = &sc->sc_if; 563 int s; 564 565 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 566 567 pmf_device_deregister(self); 568 569 s = splusb(); 570 571 sc->sc_dying = 1; 572 573 callout_halt(&sc->sc_scan_to, NULL); 574 callout_halt(&sc->sc_calib_to, NULL); 575 576 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 577 urtwn_stop(ifp, 0); 578 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 579 NULL); 580 581 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 582 bpf_detach(ifp); 583 ieee80211_ifdetach(&sc->sc_ic); 584 if_detach(ifp); 585 586 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 587 urtwn_close_pipes(sc); 588 } 589 590 splx(s); 591 592 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 593 594 rnd_detach_source(&sc->rnd_source); 595 596 callout_destroy(&sc->sc_scan_to); 597 callout_destroy(&sc->sc_calib_to); 598 599 cv_destroy(&sc->sc_task_cv); 600 mutex_destroy(&sc->sc_write_mtx); 601 mutex_destroy(&sc->sc_fwcmd_mtx); 602 mutex_destroy(&sc->sc_tx_mtx); 603 mutex_destroy(&sc->sc_rx_mtx); 604 mutex_destroy(&sc->sc_task_mtx); 605 606 return 0; 607 } 608 609 static int 610 urtwn_activate(device_t self, enum devact act) 611 { 612 struct urtwn_softc *sc = device_private(self); 613 614 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 615 616 switch (act) { 617 case DVACT_DEACTIVATE: 618 if_deactivate(sc->sc_ic.ic_ifp); 619 return 0; 620 default: 621 return EOPNOTSUPP; 622 } 623 } 624 625 static int 626 urtwn_open_pipes(struct urtwn_softc *sc) 627 { 628 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 629 static uint8_t epaddr[R92C_MAX_EPOUT]; 630 static uint8_t rxepaddr[R92C_MAX_EPIN]; 631 usb_interface_descriptor_t *id; 632 usb_endpoint_descriptor_t *ed; 633 size_t i, ntx = 0, nrx = 0; 634 int error; 635 636 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 637 638 /* Determine the number of bulk-out pipes. */ 639 id = usbd_get_interface_descriptor(sc->sc_iface); 640 for (i = 0; i < id->bNumEndpoints; i++) { 641 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 642 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 643 continue; 644 } 645 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 646 if (ntx < sizeof(epaddr)) 647 epaddr[ntx] = ed->bEndpointAddress; 648 ntx++; 649 } 650 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 651 if (nrx < sizeof(rxepaddr)) 652 rxepaddr[nrx] = ed->bEndpointAddress; 653 nrx++; 654 } 655 } 656 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 657 aprint_error_dev(sc->sc_dev, 658 "%zd: invalid number of Rx bulk pipes\n", nrx); 659 return EIO; 660 } 661 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 662 aprint_error_dev(sc->sc_dev, 663 "%zd: invalid number of Tx bulk pipes\n", ntx); 664 return EIO; 665 } 666 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 667 nrx, ntx, 0, 0); 668 sc->rx_npipe = nrx; 669 sc->tx_npipe = ntx; 670 671 /* Open bulk-in pipe at address 0x81. */ 672 for (i = 0; i < nrx; i++) { 673 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 674 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 675 if (error != 0) { 676 aprint_error_dev(sc->sc_dev, 677 "could not open Rx bulk pipe 0x%02x: %d\n", 678 rxepaddr[i], error); 679 goto fail; 680 } 681 } 682 683 /* Open bulk-out pipes (up to 3). */ 684 for (i = 0; i < ntx; i++) { 685 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 686 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 687 if (error != 0) { 688 aprint_error_dev(sc->sc_dev, 689 "could not open Tx bulk pipe 0x%02x: %d\n", 690 epaddr[i], error); 691 goto fail; 692 } 693 } 694 695 /* Map 802.11 access categories to USB pipes. */ 696 sc->ac2idx[WME_AC_BK] = 697 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 698 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 699 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 700 701 fail: 702 if (error != 0) 703 urtwn_close_pipes(sc); 704 return error; 705 } 706 707 static void 708 urtwn_close_pipes(struct urtwn_softc *sc) 709 { 710 struct usbd_pipe *pipe; 711 size_t i; 712 713 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 714 715 /* Close Rx pipes. */ 716 CTASSERT(sizeof(pipe) == sizeof(void *)); 717 for (i = 0; i < sc->rx_npipe; i++) { 718 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 719 if (pipe != NULL) { 720 usbd_close_pipe(pipe); 721 } 722 } 723 724 /* Close Tx pipes. */ 725 for (i = 0; i < sc->tx_npipe; i++) { 726 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 727 if (pipe != NULL) { 728 usbd_close_pipe(pipe); 729 } 730 } 731 } 732 733 static int 734 urtwn_alloc_rx_list(struct urtwn_softc *sc) 735 { 736 struct urtwn_rx_data *data; 737 size_t i; 738 int error = 0; 739 740 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 741 742 for (size_t j = 0; j < sc->rx_npipe; j++) { 743 TAILQ_INIT(&sc->rx_free_list[j]); 744 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 745 data = &sc->rx_data[j][i]; 746 747 data->sc = sc; /* Backpointer for callbacks. */ 748 749 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 750 0, 0, &data->xfer); 751 if (error) { 752 aprint_error_dev(sc->sc_dev, 753 "could not allocate xfer\n"); 754 break; 755 } 756 757 data->buf = usbd_get_buffer(data->xfer); 758 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 759 } 760 } 761 if (error != 0) 762 urtwn_free_rx_list(sc); 763 return error; 764 } 765 766 static void 767 urtwn_free_rx_list(struct urtwn_softc *sc) 768 { 769 struct usbd_xfer *xfer; 770 size_t i; 771 772 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 773 774 /* NB: Caller must abort pipe first. */ 775 for (size_t j = 0; j < sc->rx_npipe; j++) { 776 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 777 CTASSERT(sizeof(xfer) == sizeof(void *)); 778 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 779 if (xfer != NULL) 780 usbd_destroy_xfer(xfer); 781 } 782 } 783 } 784 785 static int 786 urtwn_alloc_tx_list(struct urtwn_softc *sc) 787 { 788 struct urtwn_tx_data *data; 789 size_t i; 790 int error = 0; 791 792 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 793 794 mutex_enter(&sc->sc_tx_mtx); 795 for (size_t j = 0; j < sc->tx_npipe; j++) { 796 TAILQ_INIT(&sc->tx_free_list[j]); 797 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 798 data = &sc->tx_data[j][i]; 799 800 data->sc = sc; /* Backpointer for callbacks. */ 801 data->pidx = j; 802 803 error = usbd_create_xfer(sc->tx_pipe[j], 804 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 805 &data->xfer); 806 if (error) { 807 aprint_error_dev(sc->sc_dev, 808 "could not allocate xfer\n"); 809 goto fail; 810 } 811 812 data->buf = usbd_get_buffer(data->xfer); 813 814 /* Append this Tx buffer to our free list. */ 815 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 816 } 817 } 818 mutex_exit(&sc->sc_tx_mtx); 819 return 0; 820 821 fail: 822 urtwn_free_tx_list(sc); 823 mutex_exit(&sc->sc_tx_mtx); 824 return error; 825 } 826 827 static void 828 urtwn_free_tx_list(struct urtwn_softc *sc) 829 { 830 struct usbd_xfer *xfer; 831 size_t i; 832 833 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 834 835 /* NB: Caller must abort pipe first. */ 836 for (size_t j = 0; j < sc->tx_npipe; j++) { 837 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 838 CTASSERT(sizeof(xfer) == sizeof(void *)); 839 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 840 if (xfer != NULL) 841 usbd_destroy_xfer(xfer); 842 } 843 } 844 } 845 846 static int 847 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 848 struct ieee80211_node *ni) 849 { 850 struct urtwn_tx_data *data = 851 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 852 return urtwn_tx(sc, m, ni, data); 853 } 854 855 static void 856 urtwn_task(void *arg) 857 { 858 struct urtwn_softc *sc = arg; 859 struct ieee80211com *ic = &sc->sc_ic; 860 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 861 struct urtwn_host_cmd *cmd; 862 int s; 863 864 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 865 if (ic->ic_state == IEEE80211_S_RUN && 866 (ic->ic_opmode == IEEE80211_M_HOSTAP || 867 ic->ic_opmode == IEEE80211_M_IBSS)) { 868 869 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 870 &sc->sc_bo); 871 if (m == NULL) { 872 aprint_error_dev(sc->sc_dev, 873 "could not allocate beacon"); 874 } 875 876 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 877 aprint_error_dev(sc->sc_dev, "could not send beacon"); 878 } 879 880 /* beacon is no longer needed */ 881 m_freem(m); 882 } 883 884 /* Process host commands. */ 885 s = splusb(); 886 mutex_spin_enter(&sc->sc_task_mtx); 887 while (ring->next != ring->cur) { 888 cmd = &ring->cmd[ring->next]; 889 mutex_spin_exit(&sc->sc_task_mtx); 890 splx(s); 891 /* Invoke callback with kernel lock held. */ 892 cmd->cb(sc, cmd->data); 893 s = splusb(); 894 mutex_spin_enter(&sc->sc_task_mtx); 895 ring->queued--; 896 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 897 } 898 cv_broadcast(&sc->sc_task_cv); 899 mutex_spin_exit(&sc->sc_task_mtx); 900 splx(s); 901 } 902 903 static void 904 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 905 void *arg, int len) 906 { 907 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 908 struct urtwn_host_cmd *cmd; 909 int s; 910 911 URTWNHIST_FUNC(); 912 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 913 (uintptr_t)cb, (uintptr_t)arg, len, 0); 914 915 s = splusb(); 916 mutex_spin_enter(&sc->sc_task_mtx); 917 cmd = &ring->cmd[ring->cur]; 918 cmd->cb = cb; 919 KASSERT(len <= sizeof(cmd->data)); 920 memcpy(cmd->data, arg, len); 921 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 922 923 /* If there is no pending command already, schedule a task. */ 924 if (!sc->sc_dying && ++ring->queued == 1) { 925 mutex_spin_exit(&sc->sc_task_mtx); 926 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 927 } else 928 mutex_spin_exit(&sc->sc_task_mtx); 929 splx(s); 930 } 931 932 static void 933 urtwn_wait_async(struct urtwn_softc *sc) 934 { 935 936 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 937 938 /* Wait for all queued asynchronous commands to complete. */ 939 mutex_spin_enter(&sc->sc_task_mtx); 940 while (sc->cmdq.queued > 0) 941 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 942 mutex_spin_exit(&sc->sc_task_mtx); 943 } 944 945 static int 946 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 947 int len) 948 { 949 usb_device_request_t req; 950 usbd_status error; 951 952 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 953 KASSERT(mutex_owned(&sc->sc_write_mtx)); 954 955 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 956 req.bRequest = R92C_REQ_REGS; 957 USETW(req.wValue, addr); 958 USETW(req.wIndex, 0); 959 USETW(req.wLength, len); 960 error = usbd_do_request(sc->sc_udev, &req, buf); 961 if (error != USBD_NORMAL_COMPLETION) { 962 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 963 error, addr, len, 0); 964 } 965 return error; 966 } 967 968 static void 969 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 970 { 971 972 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 973 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 974 975 urtwn_write_region_1(sc, addr, &val, 1); 976 } 977 978 static void 979 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 980 { 981 uint8_t buf[2]; 982 983 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 984 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 985 986 buf[0] = (uint8_t)val; 987 buf[1] = (uint8_t)(val >> 8); 988 urtwn_write_region_1(sc, addr, buf, 2); 989 } 990 991 static void 992 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 993 { 994 uint8_t buf[4]; 995 996 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 997 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 998 999 buf[0] = (uint8_t)val; 1000 buf[1] = (uint8_t)(val >> 8); 1001 buf[2] = (uint8_t)(val >> 16); 1002 buf[3] = (uint8_t)(val >> 24); 1003 urtwn_write_region_1(sc, addr, buf, 4); 1004 } 1005 1006 static int 1007 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1008 { 1009 1010 URTWNHIST_FUNC(); 1011 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1012 1013 return urtwn_write_region_1(sc, addr, buf, len); 1014 } 1015 1016 static int 1017 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1018 int len) 1019 { 1020 usb_device_request_t req; 1021 usbd_status error; 1022 1023 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1024 1025 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1026 req.bRequest = R92C_REQ_REGS; 1027 USETW(req.wValue, addr); 1028 USETW(req.wIndex, 0); 1029 USETW(req.wLength, len); 1030 error = usbd_do_request(sc->sc_udev, &req, buf); 1031 if (error != USBD_NORMAL_COMPLETION) { 1032 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1033 error, addr, len, 0); 1034 } 1035 return error; 1036 } 1037 1038 static uint8_t 1039 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1040 { 1041 uint8_t val; 1042 1043 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1044 1045 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1046 return 0xff; 1047 1048 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1049 return val; 1050 } 1051 1052 static uint16_t 1053 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1054 { 1055 uint8_t buf[2]; 1056 uint16_t val; 1057 1058 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1059 1060 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1061 return 0xffff; 1062 1063 val = LE_READ_2(&buf[0]); 1064 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1065 return val; 1066 } 1067 1068 static uint32_t 1069 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1070 { 1071 uint8_t buf[4]; 1072 uint32_t val; 1073 1074 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1075 1076 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1077 return 0xffffffff; 1078 1079 val = LE_READ_4(&buf[0]); 1080 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1081 return val; 1082 } 1083 1084 static int 1085 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1086 { 1087 struct r92c_fw_cmd cmd; 1088 uint8_t *cp; 1089 int fwcur; 1090 int ntries; 1091 1092 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1093 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1094 1095 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1096 1097 mutex_enter(&sc->sc_fwcmd_mtx); 1098 fwcur = sc->fwcur; 1099 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1100 mutex_exit(&sc->sc_fwcmd_mtx); 1101 1102 /* Wait for current FW box to be empty. */ 1103 for (ntries = 0; ntries < 100; ntries++) { 1104 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1105 break; 1106 DELAY(2000); 1107 } 1108 if (ntries == 100) { 1109 aprint_error_dev(sc->sc_dev, 1110 "could not send firmware command %d\n", id); 1111 return ETIMEDOUT; 1112 } 1113 1114 memset(&cmd, 0, sizeof(cmd)); 1115 KASSERT(len <= sizeof(cmd.msg)); 1116 memcpy(cmd.msg, buf, len); 1117 1118 /* Write the first word last since that will trigger the FW. */ 1119 cp = (uint8_t *)&cmd; 1120 cmd.id = id; 1121 if (len >= 4) { 1122 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1123 cmd.id |= R92C_CMD_FLAG_EXT; 1124 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1125 &cp[1], 2); 1126 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1127 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1128 ((uint32_t)cp[5] << 24)); 1129 } else { 1130 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1131 &cp[4], 2); 1132 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1133 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1134 ((uint32_t)cp[3] << 24)); 1135 } 1136 } else { 1137 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1138 } 1139 1140 return 0; 1141 } 1142 1143 static __inline void 1144 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1145 { 1146 1147 sc->sc_rf_write(sc, chain, addr, val); 1148 } 1149 1150 static void 1151 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1152 uint32_t val) 1153 { 1154 1155 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1156 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1157 } 1158 1159 static void 1160 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1161 uint32_t val) 1162 { 1163 1164 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1165 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1166 } 1167 1168 static void 1169 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1170 uint32_t val) 1171 { 1172 1173 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1174 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1175 } 1176 1177 static uint32_t 1178 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1179 { 1180 uint32_t reg[R92C_MAX_CHAINS], val; 1181 1182 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1183 if (chain != 0) { 1184 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1185 } 1186 1187 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1188 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1189 DELAY(1000); 1190 1191 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1192 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1193 R92C_HSSI_PARAM2_READ_EDGE); 1194 DELAY(1000); 1195 1196 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1197 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1198 DELAY(1000); 1199 1200 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1201 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1202 } else { 1203 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1204 } 1205 return MS(val, R92C_LSSI_READBACK_DATA); 1206 } 1207 1208 static int 1209 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1210 { 1211 int ntries; 1212 1213 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1214 1215 urtwn_write_4(sc, R92C_LLT_INIT, 1216 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1217 SM(R92C_LLT_INIT_ADDR, addr) | 1218 SM(R92C_LLT_INIT_DATA, data)); 1219 /* Wait for write operation to complete. */ 1220 for (ntries = 0; ntries < 20; ntries++) { 1221 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1222 R92C_LLT_INIT_OP_NO_ACTIVE) { 1223 /* Done */ 1224 return 0; 1225 } 1226 DELAY(5); 1227 } 1228 return ETIMEDOUT; 1229 } 1230 1231 static uint8_t 1232 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1233 { 1234 uint32_t reg; 1235 int ntries; 1236 1237 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1238 1239 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1240 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1241 reg &= ~R92C_EFUSE_CTRL_VALID; 1242 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1243 1244 /* Wait for read operation to complete. */ 1245 for (ntries = 0; ntries < 100; ntries++) { 1246 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1247 if (reg & R92C_EFUSE_CTRL_VALID) { 1248 /* Done */ 1249 return MS(reg, R92C_EFUSE_CTRL_DATA); 1250 } 1251 DELAY(5); 1252 } 1253 aprint_error_dev(sc->sc_dev, 1254 "could not read efuse byte at address 0x%04x\n", addr); 1255 return 0xff; 1256 } 1257 1258 static void 1259 urtwn_efuse_read(struct urtwn_softc *sc) 1260 { 1261 uint8_t *rom = (uint8_t *)&sc->rom; 1262 uint32_t reg; 1263 uint16_t addr = 0; 1264 uint8_t off, msk; 1265 size_t i; 1266 1267 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1268 1269 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1270 1271 urtwn_efuse_switch_power(sc); 1272 1273 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1274 while (addr < 512) { 1275 reg = urtwn_efuse_read_1(sc, addr); 1276 if (reg == 0xff) 1277 break; 1278 addr++; 1279 off = reg >> 4; 1280 msk = reg & 0xf; 1281 for (i = 0; i < 4; i++) { 1282 if (msk & (1U << i)) 1283 continue; 1284 1285 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1286 addr++; 1287 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1288 addr++; 1289 } 1290 } 1291 #ifdef URTWN_DEBUG 1292 /* Dump ROM content. */ 1293 for (i = 0; i < (int)sizeof(sc->rom); i++) 1294 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1295 #endif 1296 } 1297 1298 static void 1299 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1300 { 1301 uint32_t reg; 1302 1303 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1304 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1305 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1306 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1307 } 1308 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1309 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1310 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1311 reg | R92C_SYS_FUNC_EN_ELDR); 1312 } 1313 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1314 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1315 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1316 urtwn_write_2(sc, R92C_SYS_CLKR, 1317 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1318 } 1319 } 1320 1321 static int 1322 urtwn_read_chipid(struct urtwn_softc *sc) 1323 { 1324 uint32_t reg; 1325 1326 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1327 1328 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1329 ISSET(sc->chip, URTWN_CHIP_92EU)) 1330 return 0; 1331 1332 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1333 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1334 /* test chip, not supported */ 1335 return EIO; 1336 } 1337 if (reg & R92C_SYS_CFG_TYPE_92C) { 1338 sc->chip |= URTWN_CHIP_92C; 1339 /* Check if it is a castrated 8192C. */ 1340 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1341 R92C_HPON_FSM_CHIP_BONDING_ID) == 1342 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1343 sc->chip |= URTWN_CHIP_92C_1T2R; 1344 } 1345 } 1346 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1347 sc->chip |= URTWN_CHIP_UMC; 1348 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1349 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1350 } 1351 } 1352 return 0; 1353 } 1354 1355 #ifdef URTWN_DEBUG 1356 static void 1357 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1358 { 1359 1360 aprint_normal_dev(sc->sc_dev, 1361 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1362 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1363 1364 aprint_normal_dev(sc->sc_dev, 1365 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1366 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1367 1368 aprint_normal_dev(sc->sc_dev, 1369 "macaddr %s\n", 1370 ether_sprintf(rp->macaddr)); 1371 1372 aprint_normal_dev(sc->sc_dev, 1373 "string %s, subcustomer_id %#x\n", 1374 rp->string, rp->subcustomer_id); 1375 1376 aprint_normal_dev(sc->sc_dev, 1377 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1378 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1379 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1380 1381 aprint_normal_dev(sc->sc_dev, 1382 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1383 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1384 rp->ht40_1s_tx_pwr[0][2], 1385 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1386 rp->ht40_1s_tx_pwr[1][2]); 1387 1388 aprint_normal_dev(sc->sc_dev, 1389 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1390 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1391 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1392 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1393 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1394 1395 aprint_normal_dev(sc->sc_dev, 1396 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1397 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1398 rp->ht20_tx_pwr_diff[2] & 0xf, 1399 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1400 rp->ht20_tx_pwr_diff[2] >> 4); 1401 1402 aprint_normal_dev(sc->sc_dev, 1403 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1404 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1405 rp->ofdm_tx_pwr_diff[2] & 0xf, 1406 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1407 rp->ofdm_tx_pwr_diff[2] >> 4); 1408 1409 aprint_normal_dev(sc->sc_dev, 1410 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1411 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1412 rp->ht40_max_pwr[2] & 0xf, 1413 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1414 rp->ht40_max_pwr[2] >> 4); 1415 1416 aprint_normal_dev(sc->sc_dev, 1417 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1418 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1419 rp->ht20_max_pwr[2] & 0xf, 1420 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1421 rp->ht20_max_pwr[2] >> 4); 1422 1423 aprint_normal_dev(sc->sc_dev, 1424 "xtal_calib %d, tssi %d %d, thermal %d\n", 1425 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1426 1427 aprint_normal_dev(sc->sc_dev, 1428 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1429 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1430 1431 aprint_normal_dev(sc->sc_dev, 1432 "channnel_plan %d, version %d customer_id %#x\n", 1433 rp->channel_plan, rp->version, rp->curstomer_id); 1434 } 1435 #endif 1436 1437 static void 1438 urtwn_read_rom(struct urtwn_softc *sc) 1439 { 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 struct r92c_rom *rom = &sc->rom; 1442 1443 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1444 1445 mutex_enter(&sc->sc_write_mtx); 1446 1447 /* Read full ROM image. */ 1448 urtwn_efuse_read(sc); 1449 #ifdef URTWN_DEBUG 1450 if (urtwn_debug & DBG_REG) 1451 urtwn_dump_rom(sc, rom); 1452 #endif 1453 1454 /* XXX Weird but this is what the vendor driver does. */ 1455 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1456 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1457 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1458 1459 DPRINTFN(DBG_INIT, 1460 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1461 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1462 1463 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1464 1465 sc->sc_rf_write = urtwn_r92c_rf_write; 1466 sc->sc_power_on = urtwn_r92c_power_on; 1467 sc->sc_dma_init = urtwn_r92c_dma_init; 1468 1469 mutex_exit(&sc->sc_write_mtx); 1470 } 1471 1472 static void 1473 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1474 { 1475 struct ieee80211com *ic = &sc->sc_ic; 1476 uint8_t *rom = sc->r88e_rom; 1477 uint32_t reg; 1478 uint16_t addr = 0; 1479 uint8_t off, msk, tmp; 1480 int i; 1481 1482 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1483 1484 mutex_enter(&sc->sc_write_mtx); 1485 1486 off = 0; 1487 urtwn_efuse_switch_power(sc); 1488 1489 /* Read full ROM image. */ 1490 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1491 while (addr < 4096) { 1492 reg = urtwn_efuse_read_1(sc, addr); 1493 if (reg == 0xff) 1494 break; 1495 addr++; 1496 if ((reg & 0x1f) == 0x0f) { 1497 tmp = (reg & 0xe0) >> 5; 1498 reg = urtwn_efuse_read_1(sc, addr); 1499 if ((reg & 0x0f) != 0x0f) 1500 off = ((reg & 0xf0) >> 1) | tmp; 1501 addr++; 1502 } else 1503 off = reg >> 4; 1504 msk = reg & 0xf; 1505 for (i = 0; i < 4; i++) { 1506 if (msk & (1 << i)) 1507 continue; 1508 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1509 addr++; 1510 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1511 addr++; 1512 } 1513 } 1514 #ifdef URTWN_DEBUG 1515 if (urtwn_debug & DBG_REG) { 1516 } 1517 #endif 1518 1519 addr = 0x10; 1520 for (i = 0; i < 6; i++) 1521 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1522 for (i = 0; i < 5; i++) 1523 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1524 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1525 if (sc->bw20_tx_pwr_diff & 0x08) 1526 sc->bw20_tx_pwr_diff |= 0xf0; 1527 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1528 if (sc->ofdm_tx_pwr_diff & 0x08) 1529 sc->ofdm_tx_pwr_diff |= 0xf0; 1530 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1531 1532 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1533 1534 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1535 sc->sc_power_on = urtwn_r92e_power_on; 1536 sc->sc_rf_write = urtwn_r92e_rf_write; 1537 } else { 1538 sc->sc_power_on = urtwn_r88e_power_on; 1539 sc->sc_rf_write = urtwn_r88e_rf_write; 1540 } 1541 sc->sc_dma_init = urtwn_r88e_dma_init; 1542 1543 mutex_exit(&sc->sc_write_mtx); 1544 } 1545 1546 static int 1547 urtwn_media_change(struct ifnet *ifp) 1548 { 1549 int error; 1550 1551 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1552 1553 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1554 return error; 1555 1556 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1557 (IFF_UP | IFF_RUNNING)) { 1558 urtwn_init(ifp); 1559 } 1560 return 0; 1561 } 1562 1563 /* 1564 * Initialize rate adaptation in firmware. 1565 */ 1566 static int 1567 urtwn_ra_init(struct urtwn_softc *sc) 1568 { 1569 static const uint8_t map[] = { 1570 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1571 }; 1572 struct ieee80211com *ic = &sc->sc_ic; 1573 struct ieee80211_node *ni = ic->ic_bss; 1574 struct ieee80211_rateset *rs = &ni->ni_rates; 1575 struct r92c_fw_cmd_macid_cfg cmd; 1576 uint32_t rates, basicrates; 1577 uint32_t rrsr_mask, rrsr_rate; 1578 uint8_t mode; 1579 size_t maxrate, maxbasicrate, i, j; 1580 int error; 1581 1582 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1583 1584 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1585 1586 /* Get normal and basic rates mask. */ 1587 rates = basicrates = 1; 1588 maxrate = maxbasicrate = 0; 1589 for (i = 0; i < rs->rs_nrates; i++) { 1590 /* Convert 802.11 rate to HW rate index. */ 1591 for (j = 0; j < __arraycount(map); j++) { 1592 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1593 break; 1594 } 1595 } 1596 if (j == __arraycount(map)) { 1597 /* Unknown rate, skip. */ 1598 continue; 1599 } 1600 1601 rates |= 1U << j; 1602 if (j > maxrate) { 1603 maxrate = j; 1604 } 1605 1606 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1607 basicrates |= 1U << j; 1608 if (j > maxbasicrate) { 1609 maxbasicrate = j; 1610 } 1611 } 1612 } 1613 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1614 mode = R92C_RAID_11B; 1615 } else { 1616 mode = R92C_RAID_11BG; 1617 } 1618 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1619 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1620 "maxrate=%jx, maxbasicrate=%jx", 1621 rates, basicrates, maxrate, maxbasicrate); 1622 1623 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1624 maxbasicrate |= R92C_RATE_SHORTGI; 1625 maxrate |= R92C_RATE_SHORTGI; 1626 } 1627 1628 /* Set rates mask for group addressed frames. */ 1629 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1630 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1631 cmd.macid |= RTWN_MACID_SHORTGI; 1632 cmd.mask = htole32((mode << 28) | basicrates); 1633 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1634 if (error != 0) { 1635 aprint_error_dev(sc->sc_dev, 1636 "could not add broadcast station\n"); 1637 return error; 1638 } 1639 /* Set initial MRR rate. */ 1640 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1641 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1642 1643 /* Set rates mask for unicast frames. */ 1644 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1645 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1646 cmd.macid |= RTWN_MACID_SHORTGI; 1647 cmd.mask = htole32((mode << 28) | rates); 1648 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1649 if (error != 0) { 1650 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1651 return error; 1652 } 1653 /* Set initial MRR rate. */ 1654 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1655 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1656 1657 rrsr_rate = ic->ic_fixed_rate; 1658 if (rrsr_rate == -1) 1659 rrsr_rate = 11; 1660 1661 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1662 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1663 1664 /* Indicate highest supported rate. */ 1665 ni->ni_txrate = rs->rs_nrates - 1; 1666 1667 return 0; 1668 } 1669 1670 static int 1671 urtwn_get_nettype(struct urtwn_softc *sc) 1672 { 1673 struct ieee80211com *ic = &sc->sc_ic; 1674 int type; 1675 1676 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1677 1678 switch (ic->ic_opmode) { 1679 case IEEE80211_M_STA: 1680 type = R92C_CR_NETTYPE_INFRA; 1681 break; 1682 1683 case IEEE80211_M_IBSS: 1684 type = R92C_CR_NETTYPE_ADHOC; 1685 break; 1686 1687 default: 1688 type = R92C_CR_NETTYPE_NOLINK; 1689 break; 1690 } 1691 1692 return type; 1693 } 1694 1695 static void 1696 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1697 { 1698 uint8_t reg; 1699 1700 URTWNHIST_FUNC(); 1701 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1702 1703 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1704 1705 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1706 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1707 } 1708 1709 static void 1710 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1711 { 1712 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1713 uint64_t tsf; 1714 1715 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1716 1717 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1718 1719 /* Enable TSF synchronization. */ 1720 urtwn_write_1(sc, R92C_BCN_CTRL, 1721 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1722 1723 /* Correct TSF */ 1724 urtwn_write_1(sc, R92C_BCN_CTRL, 1725 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1726 1727 /* Set initial TSF. */ 1728 tsf = ni->ni_tstamp.tsf; 1729 tsf = le64toh(tsf); 1730 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1731 tsf -= IEEE80211_DUR_TU; 1732 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1733 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1734 1735 urtwn_write_1(sc, R92C_BCN_CTRL, 1736 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1737 } 1738 1739 static void 1740 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1741 { 1742 uint8_t reg; 1743 1744 URTWNHIST_FUNC(); 1745 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1746 1747 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1748 1749 if (led == URTWN_LED_LINK) { 1750 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1751 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1752 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1753 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1754 (R92C_LEDCFG0_DIS << 1)); 1755 if (on) { 1756 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1757 R92E_LEDSON; 1758 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1759 } 1760 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1761 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1762 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1763 if (!on) { 1764 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1765 urtwn_write_1(sc, R92C_LEDCFG2, 1766 reg | R92C_LEDCFG0_DIS); 1767 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1768 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1769 reg & 0xfe); 1770 } 1771 } else { 1772 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1773 if (!on) { 1774 reg |= R92C_LEDCFG0_DIS; 1775 } 1776 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1777 } 1778 sc->ledlink = on; /* Save LED state. */ 1779 } 1780 } 1781 1782 static void 1783 urtwn_calib_to(void *arg) 1784 { 1785 struct urtwn_softc *sc = arg; 1786 1787 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1788 1789 if (sc->sc_dying) 1790 return; 1791 1792 /* Do it in a process context. */ 1793 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1794 } 1795 1796 /* ARGSUSED */ 1797 static void 1798 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1799 { 1800 struct r92c_fw_cmd_rssi cmd; 1801 struct r92e_fw_cmd_rssi cmde; 1802 1803 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1804 1805 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1806 goto restart_timer; 1807 1808 mutex_enter(&sc->sc_write_mtx); 1809 if (sc->avg_pwdb != -1) { 1810 /* Indicate Rx signal strength to FW for rate adaptation. */ 1811 memset(&cmd, 0, sizeof(cmd)); 1812 memset(&cmde, 0, sizeof(cmde)); 1813 cmd.macid = 0; /* BSS. */ 1814 cmde.macid = 0; /* BSS. */ 1815 cmd.pwdb = sc->avg_pwdb; 1816 cmde.pwdb = sc->avg_pwdb; 1817 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1818 sc->avg_pwdb, 0, 0, 0); 1819 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1820 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1821 sizeof(cmd)); 1822 } else { 1823 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1824 sizeof(cmde)); 1825 } 1826 } 1827 1828 /* Do temperature compensation. */ 1829 urtwn_temp_calib(sc); 1830 mutex_exit(&sc->sc_write_mtx); 1831 1832 restart_timer: 1833 if (!sc->sc_dying) { 1834 /* Restart calibration timer. */ 1835 callout_schedule(&sc->sc_calib_to, hz); 1836 } 1837 } 1838 1839 static void 1840 urtwn_next_scan(void *arg) 1841 { 1842 struct urtwn_softc *sc = arg; 1843 int s; 1844 1845 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1846 1847 if (sc->sc_dying) 1848 return; 1849 1850 s = splnet(); 1851 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1852 ieee80211_next_scan(&sc->sc_ic); 1853 splx(s); 1854 } 1855 1856 static void 1857 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1858 { 1859 URTWNHIST_FUNC(); 1860 URTWNHIST_CALLARGS("new node %06jx%06jx", 1861 ni->ni_macaddr[0] << 2 | 1862 ni->ni_macaddr[1] << 1 | 1863 ni->ni_macaddr[2], 1864 ni->ni_macaddr[3] << 2 | 1865 ni->ni_macaddr[4] << 1 | 1866 ni->ni_macaddr[5], 1867 0, 0); 1868 /* start with lowest Tx rate */ 1869 ni->ni_txrate = 0; 1870 } 1871 1872 static int 1873 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1874 { 1875 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1876 struct urtwn_cmd_newstate cmd; 1877 1878 URTWNHIST_FUNC(); 1879 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1880 1881 callout_stop(&sc->sc_scan_to); 1882 callout_stop(&sc->sc_calib_to); 1883 1884 /* Do it in a process context. */ 1885 cmd.state = nstate; 1886 cmd.arg = arg; 1887 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1888 return 0; 1889 } 1890 1891 static void 1892 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1893 { 1894 struct urtwn_cmd_newstate *cmd = arg; 1895 struct ieee80211com *ic = &sc->sc_ic; 1896 struct ieee80211_node *ni; 1897 enum ieee80211_state ostate = ic->ic_state; 1898 enum ieee80211_state nstate = cmd->state; 1899 uint32_t reg; 1900 uint8_t sifs_time, msr; 1901 int s; 1902 1903 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1904 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1905 1906 s = splnet(); 1907 mutex_enter(&sc->sc_write_mtx); 1908 1909 callout_stop(&sc->sc_scan_to); 1910 callout_stop(&sc->sc_calib_to); 1911 1912 switch (ostate) { 1913 case IEEE80211_S_INIT: 1914 break; 1915 1916 case IEEE80211_S_SCAN: 1917 if (nstate != IEEE80211_S_SCAN) { 1918 /* 1919 * End of scanning 1920 */ 1921 /* flush 4-AC Queue after site_survey */ 1922 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1923 1924 /* Allow Rx from our BSSID only. */ 1925 urtwn_write_4(sc, R92C_RCR, 1926 urtwn_read_4(sc, R92C_RCR) | 1927 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1928 } 1929 break; 1930 1931 case IEEE80211_S_AUTH: 1932 case IEEE80211_S_ASSOC: 1933 break; 1934 1935 case IEEE80211_S_RUN: 1936 /* Turn link LED off. */ 1937 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1938 1939 /* Set media status to 'No Link'. */ 1940 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1941 1942 /* Stop Rx of data frames. */ 1943 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1944 1945 /* Reset TSF. */ 1946 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1947 1948 /* Disable TSF synchronization. */ 1949 urtwn_write_1(sc, R92C_BCN_CTRL, 1950 urtwn_read_1(sc, R92C_BCN_CTRL) | 1951 R92C_BCN_CTRL_DIS_TSF_UDT0); 1952 1953 /* Back to 20MHz mode */ 1954 urtwn_set_chan(sc, ic->ic_curchan, 1955 IEEE80211_HTINFO_2NDCHAN_NONE); 1956 1957 if (ic->ic_opmode == IEEE80211_M_IBSS || 1958 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1959 /* Stop BCN */ 1960 urtwn_write_1(sc, R92C_BCN_CTRL, 1961 urtwn_read_1(sc, R92C_BCN_CTRL) & 1962 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1963 } 1964 1965 /* Reset EDCA parameters. */ 1966 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1967 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1968 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1969 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1970 1971 /* flush all cam entries */ 1972 urtwn_cam_init(sc); 1973 break; 1974 } 1975 1976 switch (nstate) { 1977 case IEEE80211_S_INIT: 1978 /* Turn link LED off. */ 1979 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1980 break; 1981 1982 case IEEE80211_S_SCAN: 1983 if (ostate != IEEE80211_S_SCAN) { 1984 /* 1985 * Begin of scanning 1986 */ 1987 1988 /* Set gain for scanning. */ 1989 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1990 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1991 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1992 1993 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1994 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1995 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1996 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1997 } 1998 1999 /* Set media status to 'No Link'. */ 2000 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2001 2002 /* Allow Rx from any BSSID. */ 2003 urtwn_write_4(sc, R92C_RCR, 2004 urtwn_read_4(sc, R92C_RCR) & 2005 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2006 2007 /* Stop Rx of data frames. */ 2008 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2009 2010 /* Disable update TSF */ 2011 urtwn_write_1(sc, R92C_BCN_CTRL, 2012 urtwn_read_1(sc, R92C_BCN_CTRL) | 2013 R92C_BCN_CTRL_DIS_TSF_UDT0); 2014 } 2015 2016 /* Make link LED blink during scan. */ 2017 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2018 2019 /* Pause AC Tx queues. */ 2020 urtwn_write_1(sc, R92C_TXPAUSE, 2021 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2022 2023 urtwn_set_chan(sc, ic->ic_curchan, 2024 IEEE80211_HTINFO_2NDCHAN_NONE); 2025 2026 /* Start periodic scan. */ 2027 if (!sc->sc_dying) 2028 callout_schedule(&sc->sc_scan_to, hz / 5); 2029 break; 2030 2031 case IEEE80211_S_AUTH: 2032 /* Set initial gain under link. */ 2033 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2034 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2035 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2036 2037 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2038 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2039 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2040 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2041 } 2042 2043 /* Set media status to 'No Link'. */ 2044 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2045 2046 /* Allow Rx from any BSSID. */ 2047 urtwn_write_4(sc, R92C_RCR, 2048 urtwn_read_4(sc, R92C_RCR) & 2049 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2050 2051 urtwn_set_chan(sc, ic->ic_curchan, 2052 IEEE80211_HTINFO_2NDCHAN_NONE); 2053 break; 2054 2055 case IEEE80211_S_ASSOC: 2056 break; 2057 2058 case IEEE80211_S_RUN: 2059 ni = ic->ic_bss; 2060 2061 /* XXX: Set 20MHz mode */ 2062 urtwn_set_chan(sc, ic->ic_curchan, 2063 IEEE80211_HTINFO_2NDCHAN_NONE); 2064 2065 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2066 /* Back to 20MHz mode */ 2067 urtwn_set_chan(sc, ic->ic_curchan, 2068 IEEE80211_HTINFO_2NDCHAN_NONE); 2069 2070 /* Set media status to 'No Link'. */ 2071 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2072 2073 /* Enable Rx of data frames. */ 2074 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2075 2076 /* Allow Rx from any BSSID. */ 2077 urtwn_write_4(sc, R92C_RCR, 2078 urtwn_read_4(sc, R92C_RCR) & 2079 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2080 2081 /* Accept Rx data/control/management frames */ 2082 urtwn_write_4(sc, R92C_RCR, 2083 urtwn_read_4(sc, R92C_RCR) | 2084 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2085 2086 /* Turn link LED on. */ 2087 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2088 break; 2089 } 2090 2091 /* Set media status to 'Associated'. */ 2092 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2093 2094 /* Set BSSID. */ 2095 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2096 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2097 2098 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2099 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2100 } else { 2101 /* 802.11b/g */ 2102 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2103 } 2104 2105 /* Enable Rx of data frames. */ 2106 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2107 2108 /* Set beacon interval. */ 2109 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2110 2111 msr = urtwn_read_1(sc, R92C_MSR); 2112 msr &= R92C_MSR_MASK; 2113 switch (ic->ic_opmode) { 2114 case IEEE80211_M_STA: 2115 /* Allow Rx from our BSSID only. */ 2116 urtwn_write_4(sc, R92C_RCR, 2117 urtwn_read_4(sc, R92C_RCR) | 2118 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2119 2120 /* Enable TSF synchronization. */ 2121 urtwn_tsf_sync_enable(sc); 2122 2123 msr |= R92C_MSR_INFRA; 2124 break; 2125 case IEEE80211_M_HOSTAP: 2126 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2127 2128 /* Allow Rx from any BSSID. */ 2129 urtwn_write_4(sc, R92C_RCR, 2130 urtwn_read_4(sc, R92C_RCR) & 2131 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2132 2133 /* Reset TSF timer to zero. */ 2134 reg = urtwn_read_4(sc, R92C_TCR); 2135 reg &= ~0x01; 2136 urtwn_write_4(sc, R92C_TCR, reg); 2137 reg |= 0x01; 2138 urtwn_write_4(sc, R92C_TCR, reg); 2139 2140 msr |= R92C_MSR_AP; 2141 break; 2142 default: 2143 msr |= R92C_MSR_ADHOC; 2144 break; 2145 } 2146 urtwn_write_1(sc, R92C_MSR, msr); 2147 2148 sifs_time = 10; 2149 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2150 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2151 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2152 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2153 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2154 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2155 2156 /* Initialize rate adaptation. */ 2157 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2158 ISSET(sc->chip, URTWN_CHIP_92EU)) 2159 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2160 else 2161 urtwn_ra_init(sc); 2162 2163 /* Turn link LED on. */ 2164 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2165 2166 /* Reset average RSSI. */ 2167 sc->avg_pwdb = -1; 2168 2169 /* Reset temperature calibration state machine. */ 2170 sc->thcal_state = 0; 2171 sc->thcal_lctemp = 0; 2172 2173 /* Start periodic calibration. */ 2174 if (!sc->sc_dying) 2175 callout_schedule(&sc->sc_calib_to, hz); 2176 break; 2177 } 2178 2179 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2180 2181 mutex_exit(&sc->sc_write_mtx); 2182 splx(s); 2183 } 2184 2185 static int 2186 urtwn_wme_update(struct ieee80211com *ic) 2187 { 2188 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2189 2190 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2191 2192 /* don't override default WME values if WME is not actually enabled */ 2193 if (!(ic->ic_flags & IEEE80211_F_WME)) 2194 return 0; 2195 2196 /* Do it in a process context. */ 2197 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2198 return 0; 2199 } 2200 2201 static void 2202 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2203 { 2204 static const uint16_t ac2reg[WME_NUM_AC] = { 2205 R92C_EDCA_BE_PARAM, 2206 R92C_EDCA_BK_PARAM, 2207 R92C_EDCA_VI_PARAM, 2208 R92C_EDCA_VO_PARAM 2209 }; 2210 struct ieee80211com *ic = &sc->sc_ic; 2211 const struct wmeParams *wmep; 2212 int ac, aifs, slottime; 2213 int s; 2214 2215 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2216 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2217 2218 s = splnet(); 2219 mutex_enter(&sc->sc_write_mtx); 2220 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2221 for (ac = 0; ac < WME_NUM_AC; ac++) { 2222 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2223 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2224 aifs = wmep->wmep_aifsn * slottime + 10; 2225 urtwn_write_4(sc, ac2reg[ac], 2226 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2227 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2228 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2229 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2230 } 2231 mutex_exit(&sc->sc_write_mtx); 2232 splx(s); 2233 } 2234 2235 static void 2236 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2237 { 2238 int pwdb; 2239 2240 URTWNHIST_FUNC(); 2241 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2242 2243 /* Convert antenna signal to percentage. */ 2244 if (rssi <= -100 || rssi >= 20) 2245 pwdb = 0; 2246 else if (rssi >= 0) 2247 pwdb = 100; 2248 else 2249 pwdb = 100 + rssi; 2250 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2251 if (rate <= 3) { 2252 /* CCK gain is smaller than OFDM/MCS gain. */ 2253 pwdb += 6; 2254 if (pwdb > 100) 2255 pwdb = 100; 2256 if (pwdb <= 14) 2257 pwdb -= 4; 2258 else if (pwdb <= 26) 2259 pwdb -= 8; 2260 else if (pwdb <= 34) 2261 pwdb -= 6; 2262 else if (pwdb <= 42) 2263 pwdb -= 2; 2264 } 2265 } 2266 if (sc->avg_pwdb == -1) /* Init. */ 2267 sc->avg_pwdb = pwdb; 2268 else if (sc->avg_pwdb < pwdb) 2269 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2270 else 2271 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2272 2273 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2274 rate, rssi, pwdb, sc->avg_pwdb); 2275 } 2276 2277 static int8_t 2278 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2279 { 2280 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2281 struct r92c_rx_phystat *phy; 2282 struct r92c_rx_cck *cck; 2283 uint8_t rpt; 2284 int8_t rssi; 2285 2286 URTWNHIST_FUNC(); 2287 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2288 2289 if (rate <= 3) { 2290 cck = (struct r92c_rx_cck *)physt; 2291 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2292 rpt = (cck->agc_rpt >> 5) & 0x3; 2293 rssi = (cck->agc_rpt & 0x1f) << 1; 2294 } else { 2295 rpt = (cck->agc_rpt >> 6) & 0x3; 2296 rssi = cck->agc_rpt & 0x3e; 2297 } 2298 rssi = cckoff[rpt] - rssi; 2299 } else { /* OFDM/HT. */ 2300 phy = (struct r92c_rx_phystat *)physt; 2301 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2302 } 2303 return rssi; 2304 } 2305 2306 static int8_t 2307 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2308 { 2309 struct r92c_rx_phystat *phy; 2310 struct r88e_rx_cck *cck; 2311 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2312 int8_t rssi; 2313 2314 URTWNHIST_FUNC(); 2315 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2316 2317 rssi = 0; 2318 if (rate <= 3) { 2319 cck = (struct r88e_rx_cck *)physt; 2320 cck_agc_rpt = cck->agc_rpt; 2321 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2322 vga_idx = cck_agc_rpt & 0x1f; 2323 switch (lna_idx) { 2324 case 7: 2325 if (vga_idx <= 27) 2326 rssi = -100 + 2* (27 - vga_idx); 2327 else 2328 rssi = -100; 2329 break; 2330 case 6: 2331 rssi = -48 + 2 * (2 - vga_idx); 2332 break; 2333 case 5: 2334 rssi = -42 + 2 * (7 - vga_idx); 2335 break; 2336 case 4: 2337 rssi = -36 + 2 * (7 - vga_idx); 2338 break; 2339 case 3: 2340 rssi = -24 + 2 * (7 - vga_idx); 2341 break; 2342 case 2: 2343 rssi = -12 + 2 * (5 - vga_idx); 2344 break; 2345 case 1: 2346 rssi = 8 - (2 * vga_idx); 2347 break; 2348 case 0: 2349 rssi = 14 - (2 * vga_idx); 2350 break; 2351 } 2352 rssi += 6; 2353 } else { /* OFDM/HT. */ 2354 phy = (struct r92c_rx_phystat *)physt; 2355 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2356 } 2357 return rssi; 2358 } 2359 2360 static void 2361 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2362 { 2363 struct ieee80211com *ic = &sc->sc_ic; 2364 struct ifnet *ifp = ic->ic_ifp; 2365 struct ieee80211_frame *wh; 2366 struct ieee80211_node *ni; 2367 struct r92c_rx_desc_usb *stat; 2368 uint32_t rxdw0, rxdw3; 2369 struct mbuf *m; 2370 uint8_t rate; 2371 int8_t rssi = 0; 2372 int s, infosz; 2373 2374 URTWNHIST_FUNC(); 2375 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2376 2377 stat = (struct r92c_rx_desc_usb *)buf; 2378 rxdw0 = le32toh(stat->rxdw0); 2379 rxdw3 = le32toh(stat->rxdw3); 2380 2381 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2382 /* 2383 * This should not happen since we setup our Rx filter 2384 * to not receive these frames. 2385 */ 2386 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2387 if_statinc(ifp, if_ierrors); 2388 return; 2389 } 2390 /* 2391 * XXX: This will drop most control packets. Do we really 2392 * want this in IEEE80211_M_MONITOR mode? 2393 */ 2394 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2395 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2396 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2397 ic->ic_stats.is_rx_tooshort++; 2398 if_statinc(ifp, if_ierrors); 2399 return; 2400 } 2401 if (__predict_false(pktlen > MCLBYTES)) { 2402 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2403 if_statinc(ifp, if_ierrors); 2404 return; 2405 } 2406 2407 rate = MS(rxdw3, R92C_RXDW3_RATE); 2408 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2409 2410 /* Get RSSI from PHY status descriptor if present. */ 2411 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2412 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2413 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2414 else 2415 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2416 /* Update our average RSSI. */ 2417 urtwn_update_avgrssi(sc, rate, rssi); 2418 } 2419 2420 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2421 pktlen, rate, infosz, rssi); 2422 2423 MGETHDR(m, M_DONTWAIT, MT_DATA); 2424 if (__predict_false(m == NULL)) { 2425 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2426 ic->ic_stats.is_rx_nobuf++; 2427 if_statinc(ifp, if_ierrors); 2428 return; 2429 } 2430 if (pktlen > (int)MHLEN) { 2431 MCLGET(m, M_DONTWAIT); 2432 if (__predict_false(!(m->m_flags & M_EXT))) { 2433 aprint_error_dev(sc->sc_dev, 2434 "couldn't allocate rx mbuf cluster\n"); 2435 m_freem(m); 2436 ic->ic_stats.is_rx_nobuf++; 2437 if_statinc(ifp, if_ierrors); 2438 return; 2439 } 2440 } 2441 2442 /* Finalize mbuf. */ 2443 m_set_rcvif(m, ifp); 2444 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2445 memcpy(mtod(m, uint8_t *), wh, pktlen); 2446 m->m_pkthdr.len = m->m_len = pktlen; 2447 2448 s = splnet(); 2449 if (__predict_false(sc->sc_drvbpf != NULL)) { 2450 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2451 2452 tap->wr_flags = 0; 2453 if (!(rxdw3 & R92C_RXDW3_HT)) { 2454 switch (rate) { 2455 /* CCK. */ 2456 case 0: tap->wr_rate = 2; break; 2457 case 1: tap->wr_rate = 4; break; 2458 case 2: tap->wr_rate = 11; break; 2459 case 3: tap->wr_rate = 22; break; 2460 /* OFDM. */ 2461 case 4: tap->wr_rate = 12; break; 2462 case 5: tap->wr_rate = 18; break; 2463 case 6: tap->wr_rate = 24; break; 2464 case 7: tap->wr_rate = 36; break; 2465 case 8: tap->wr_rate = 48; break; 2466 case 9: tap->wr_rate = 72; break; 2467 case 10: tap->wr_rate = 96; break; 2468 case 11: tap->wr_rate = 108; break; 2469 } 2470 } else if (rate >= 12) { /* MCS0~15. */ 2471 /* Bit 7 set means HT MCS instead of rate. */ 2472 tap->wr_rate = 0x80 | (rate - 12); 2473 } 2474 tap->wr_dbm_antsignal = rssi; 2475 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2476 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2477 2478 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2479 } 2480 2481 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2482 2483 /* push the frame up to the 802.11 stack */ 2484 ieee80211_input(ic, m, ni, rssi, 0); 2485 2486 /* Node is no longer needed. */ 2487 ieee80211_free_node(ni); 2488 2489 splx(s); 2490 } 2491 2492 static void 2493 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2494 { 2495 struct urtwn_rx_data *data = priv; 2496 struct urtwn_softc *sc = data->sc; 2497 struct r92c_rx_desc_usb *stat; 2498 size_t pidx = data->pidx; 2499 uint32_t rxdw0; 2500 uint8_t *buf; 2501 int len, totlen, pktlen, infosz, npkts; 2502 2503 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2504 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2505 2506 mutex_enter(&sc->sc_rx_mtx); 2507 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2508 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2509 /* Put this Rx buffer back to our free list. */ 2510 mutex_exit(&sc->sc_rx_mtx); 2511 2512 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2513 if (status == USBD_STALLED) 2514 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2515 else if (status != USBD_CANCELLED) 2516 goto resubmit; 2517 return; 2518 } 2519 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2520 2521 if (__predict_false(len < (int)sizeof(*stat))) { 2522 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2523 goto resubmit; 2524 } 2525 buf = data->buf; 2526 2527 /* Get the number of encapsulated frames. */ 2528 stat = (struct r92c_rx_desc_usb *)buf; 2529 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2530 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2531 2532 if (npkts != 0) 2533 rnd_add_uint32(&sc->rnd_source, npkts); 2534 2535 /* Process all of them. */ 2536 while (npkts-- > 0) { 2537 if (__predict_false(len < (int)sizeof(*stat))) { 2538 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2539 len, 0, 0, 0); 2540 break; 2541 } 2542 stat = (struct r92c_rx_desc_usb *)buf; 2543 rxdw0 = le32toh(stat->rxdw0); 2544 2545 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2546 if (__predict_false(pktlen == 0)) { 2547 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2548 break; 2549 } 2550 2551 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2552 2553 /* Make sure everything fits in xfer. */ 2554 totlen = sizeof(*stat) + infosz + pktlen; 2555 if (__predict_false(totlen > len)) { 2556 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2557 (int)sizeof(*stat), infosz, pktlen, len); 2558 break; 2559 } 2560 2561 /* Process 802.11 frame. */ 2562 urtwn_rx_frame(sc, buf, pktlen); 2563 2564 /* Next chunk is 128-byte aligned. */ 2565 totlen = roundup2(totlen, 128); 2566 buf += totlen; 2567 len -= totlen; 2568 } 2569 2570 resubmit: 2571 /* Setup a new transfer. */ 2572 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2573 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2574 (void)usbd_transfer(xfer); 2575 } 2576 2577 static void 2578 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2579 { 2580 struct urtwn_tx_data *data = priv; 2581 struct urtwn_softc *sc = data->sc; 2582 struct ifnet *ifp = &sc->sc_if; 2583 size_t pidx = data->pidx; 2584 int s; 2585 2586 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2587 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2588 2589 mutex_enter(&sc->sc_tx_mtx); 2590 /* Put this Tx buffer back to our free list. */ 2591 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2592 mutex_exit(&sc->sc_tx_mtx); 2593 2594 s = splnet(); 2595 sc->tx_timer = 0; 2596 ifp->if_flags &= ~IFF_OACTIVE; 2597 2598 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2599 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2600 if (status == USBD_STALLED) { 2601 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2602 usbd_clear_endpoint_stall_async(pipe); 2603 } 2604 printf("ERROR1\n"); 2605 if_statinc(ifp, if_oerrors); 2606 } 2607 splx(s); 2608 return; 2609 } 2610 2611 if_statinc(ifp, if_opackets); 2612 urtwn_start(ifp); 2613 splx(s); 2614 2615 } 2616 2617 static int 2618 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2619 struct urtwn_tx_data *data) 2620 { 2621 struct ieee80211com *ic = &sc->sc_ic; 2622 struct ieee80211_frame *wh; 2623 struct ieee80211_key *k = NULL; 2624 struct r92c_tx_desc_usb *txd; 2625 size_t i, padsize, xferlen, txd_len; 2626 uint16_t seq, sum; 2627 uint8_t raid, type, tid; 2628 int s, hasqos, error; 2629 2630 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2631 2632 wh = mtod(m, struct ieee80211_frame *); 2633 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2634 txd_len = sizeof(*txd); 2635 2636 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2637 txd_len = 32; 2638 2639 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2640 k = ieee80211_crypto_encap(ic, ni, m); 2641 if (k == NULL) 2642 return ENOBUFS; 2643 2644 /* packet header may have moved, reset our local pointer */ 2645 wh = mtod(m, struct ieee80211_frame *); 2646 } 2647 2648 if (__predict_false(sc->sc_drvbpf != NULL)) { 2649 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2650 2651 tap->wt_flags = 0; 2652 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2653 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2654 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2655 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2656 2657 /* XXX: set tap->wt_rate? */ 2658 2659 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2660 } 2661 2662 /* non-qos data frames */ 2663 tid = R92C_TXDW1_QSEL_BE; 2664 if ((hasqos = ieee80211_has_qos(wh))) { 2665 /* data frames in 11n mode */ 2666 struct ieee80211_qosframe *qwh = (void *)wh; 2667 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2668 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2669 tid = R92C_TXDW1_QSEL_MGNT; 2670 } 2671 2672 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2673 padsize = 8; 2674 else 2675 padsize = 0; 2676 2677 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2678 padsize = 0; 2679 2680 /* Fill Tx descriptor. */ 2681 txd = (struct r92c_tx_desc_usb *)data->buf; 2682 memset(txd, 0, txd_len + padsize); 2683 2684 txd->txdw0 |= htole32( 2685 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2686 SM(R92C_TXDW0_OFFSET, txd_len)); 2687 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2688 txd->txdw0 |= htole32( 2689 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2690 } 2691 2692 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2693 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2694 2695 /* fix pad field */ 2696 if (padsize > 0) { 2697 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2698 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2699 } 2700 2701 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2702 type == IEEE80211_FC0_TYPE_DATA) { 2703 if (ic->ic_curmode == IEEE80211_MODE_11B) 2704 raid = R92C_RAID_11B; 2705 else 2706 raid = R92C_RAID_11BG; 2707 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2708 tid, raid, 0, 0); 2709 2710 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2711 txd->txdw1 |= htole32( 2712 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2713 SM(R92C_TXDW1_QSEL, tid) | 2714 SM(R92C_TXDW1_RAID, raid) | 2715 R92C_TXDW1_AGGBK); 2716 } else 2717 txd->txdw1 |= htole32( 2718 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2719 SM(R92C_TXDW1_QSEL, tid) | 2720 SM(R92C_TXDW1_RAID, raid) | 2721 R92C_TXDW1_AGGBK); 2722 2723 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2724 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2725 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2726 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2727 2728 if (hasqos) { 2729 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2730 } 2731 2732 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2733 /* for 11g */ 2734 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2735 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2736 R92C_TXDW4_HWRTSEN); 2737 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2738 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2739 R92C_TXDW4_HWRTSEN); 2740 } 2741 } 2742 /* Send RTS at OFDM24. */ 2743 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2744 txd->txdw5 |= htole32(0x0001ff00); 2745 /* Send data at OFDM54. */ 2746 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2747 txd->txdw5 |= htole32(0x13 & 0x3f); 2748 else 2749 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2750 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2751 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2752 txd->txdw1 |= htole32( 2753 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2754 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2755 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2756 2757 /* Force CCK1. */ 2758 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2759 /* Use 1Mbps */ 2760 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2761 } else { 2762 /* broadcast or multicast packets */ 2763 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2764 txd->txdw1 |= htole32( 2765 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2766 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2767 2768 /* Force CCK1. */ 2769 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2770 /* Use 1Mbps */ 2771 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2772 } 2773 /* Set sequence number */ 2774 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2775 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2776 txd->txdseq |= htole16(seq); 2777 2778 if (!hasqos) { 2779 /* Use HW sequence numbering for non-QoS frames. */ 2780 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2781 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2782 } 2783 } else { 2784 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2785 R92E_HWSEQ_SHIFT); 2786 if (!hasqos) { 2787 /* Use HW sequence numbering for non-QoS frames. */ 2788 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2789 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2790 } 2791 } 2792 2793 /* Compute Tx descriptor checksum. */ 2794 sum = 0; 2795 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2796 sum ^= ((uint16_t *)txd)[i]; 2797 txd->txdsum = sum; /* NB: already little endian. */ 2798 2799 xferlen = txd_len + m->m_pkthdr.len + padsize; 2800 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2801 2802 s = splnet(); 2803 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2804 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2805 urtwn_txeof); 2806 error = usbd_transfer(data->xfer); 2807 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2808 error != USBD_IN_PROGRESS)) { 2809 splx(s); 2810 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2811 return error; 2812 } 2813 splx(s); 2814 return 0; 2815 } 2816 2817 struct urtwn_tx_data * 2818 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2819 { 2820 struct urtwn_tx_data *data = NULL; 2821 2822 mutex_enter(&sc->sc_tx_mtx); 2823 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2824 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2825 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2826 } 2827 mutex_exit(&sc->sc_tx_mtx); 2828 2829 return data; 2830 } 2831 2832 static void 2833 urtwn_start(struct ifnet *ifp) 2834 { 2835 struct urtwn_softc *sc = ifp->if_softc; 2836 struct ieee80211com *ic = &sc->sc_ic; 2837 struct urtwn_tx_data *data; 2838 struct ether_header *eh; 2839 struct ieee80211_node *ni; 2840 struct mbuf *m; 2841 2842 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2843 2844 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2845 return; 2846 2847 data = NULL; 2848 for (;;) { 2849 /* Send pending management frames first. */ 2850 IF_POLL(&ic->ic_mgtq, m); 2851 if (m != NULL) { 2852 /* Use AC_VO for management frames. */ 2853 2854 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2855 2856 if (data == NULL) { 2857 ifp->if_flags |= IFF_OACTIVE; 2858 DPRINTFN(DBG_TX, "empty tx_free_list", 2859 0, 0, 0, 0); 2860 return; 2861 } 2862 IF_DEQUEUE(&ic->ic_mgtq, m); 2863 ni = M_GETCTX(m, struct ieee80211_node *); 2864 M_CLEARCTX(m); 2865 goto sendit; 2866 } 2867 if (ic->ic_state != IEEE80211_S_RUN) 2868 break; 2869 2870 /* Encapsulate and send data frames. */ 2871 IFQ_POLL(&ifp->if_snd, m); 2872 if (m == NULL) 2873 break; 2874 2875 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2876 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2877 uint8_t qid = WME_AC_BE; 2878 if (ieee80211_has_qos(wh)) { 2879 /* data frames in 11n mode */ 2880 struct ieee80211_qosframe *qwh = (void *)wh; 2881 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2882 qid = TID_TO_WME_AC(tid); 2883 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2884 qid = WME_AC_VO; 2885 } 2886 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2887 2888 if (data == NULL) { 2889 ifp->if_flags |= IFF_OACTIVE; 2890 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2891 return; 2892 } 2893 IFQ_DEQUEUE(&ifp->if_snd, m); 2894 2895 if (m->m_len < (int)sizeof(*eh) && 2896 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2897 printf("ERROR6\n"); 2898 if_statinc(ifp, if_oerrors); 2899 continue; 2900 } 2901 eh = mtod(m, struct ether_header *); 2902 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2903 if (ni == NULL) { 2904 m_freem(m); 2905 printf("ERROR5\n"); 2906 if_statinc(ifp, if_oerrors); 2907 continue; 2908 } 2909 2910 bpf_mtap(ifp, m, BPF_D_OUT); 2911 2912 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2913 ieee80211_free_node(ni); 2914 printf("ERROR4\n"); 2915 if_statinc(ifp, if_oerrors); 2916 continue; 2917 } 2918 sendit: 2919 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2920 2921 if (urtwn_tx(sc, m, ni, data) != 0) { 2922 m_freem(m); 2923 ieee80211_free_node(ni); 2924 printf("ERROR3\n"); 2925 if_statinc(ifp, if_oerrors); 2926 continue; 2927 } 2928 m_freem(m); 2929 ieee80211_free_node(ni); 2930 sc->tx_timer = 5; 2931 ifp->if_timer = 1; 2932 } 2933 } 2934 2935 static void 2936 urtwn_watchdog(struct ifnet *ifp) 2937 { 2938 struct urtwn_softc *sc = ifp->if_softc; 2939 2940 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2941 2942 ifp->if_timer = 0; 2943 2944 if (sc->tx_timer > 0) { 2945 if (--sc->tx_timer == 0) { 2946 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2947 /* urtwn_init(ifp); XXX needs a process context! */ 2948 printf("ERROR2\n"); 2949 if_statinc(ifp, if_oerrors); 2950 return; 2951 } 2952 ifp->if_timer = 1; 2953 } 2954 ieee80211_watchdog(&sc->sc_ic); 2955 } 2956 2957 static int 2958 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2959 { 2960 struct urtwn_softc *sc = ifp->if_softc; 2961 struct ieee80211com *ic = &sc->sc_ic; 2962 int s, error = 0; 2963 2964 URTWNHIST_FUNC(); 2965 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2966 0, 0); 2967 2968 s = splnet(); 2969 2970 switch (cmd) { 2971 case SIOCSIFFLAGS: 2972 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2973 break; 2974 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2975 case IFF_UP | IFF_RUNNING: 2976 break; 2977 case IFF_UP: 2978 urtwn_init(ifp); 2979 break; 2980 case IFF_RUNNING: 2981 urtwn_stop(ifp, 1); 2982 break; 2983 case 0: 2984 break; 2985 } 2986 break; 2987 2988 case SIOCADDMULTI: 2989 case SIOCDELMULTI: 2990 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2991 /* setup multicast filter, etc */ 2992 error = 0; 2993 } 2994 break; 2995 2996 case SIOCS80211CHANNEL: 2997 /* 2998 * This allows for fast channel switching in monitor mode 2999 * (used by kismet). In IBSS mode, we must explicitly reset 3000 * the interface to generate a new beacon frame. 3001 */ 3002 error = ieee80211_ioctl(ic, cmd, data); 3003 if (error == ENETRESET && 3004 ic->ic_opmode == IEEE80211_M_MONITOR) { 3005 urtwn_set_chan(sc, ic->ic_curchan, 3006 IEEE80211_HTINFO_2NDCHAN_NONE); 3007 error = 0; 3008 } 3009 break; 3010 3011 default: 3012 error = ieee80211_ioctl(ic, cmd, data); 3013 break; 3014 } 3015 if (error == ENETRESET) { 3016 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3017 (IFF_UP | IFF_RUNNING) && 3018 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3019 urtwn_init(ifp); 3020 } 3021 error = 0; 3022 } 3023 3024 splx(s); 3025 3026 return error; 3027 } 3028 3029 static __inline int 3030 urtwn_power_on(struct urtwn_softc *sc) 3031 { 3032 3033 return sc->sc_power_on(sc); 3034 } 3035 3036 static int 3037 urtwn_r92c_power_on(struct urtwn_softc *sc) 3038 { 3039 uint32_t reg; 3040 int ntries; 3041 3042 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3043 3044 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3045 3046 /* Wait for autoload done bit. */ 3047 for (ntries = 0; ntries < 1000; ntries++) { 3048 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3049 break; 3050 DELAY(5); 3051 } 3052 if (ntries == 1000) { 3053 aprint_error_dev(sc->sc_dev, 3054 "timeout waiting for chip autoload\n"); 3055 return ETIMEDOUT; 3056 } 3057 3058 /* Unlock ISO/CLK/Power control register. */ 3059 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3060 /* Move SPS into PWM mode. */ 3061 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3062 DELAY(5); 3063 3064 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3065 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3066 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3067 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3068 DELAY(100); 3069 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3070 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3071 ~R92C_SYS_ISO_CTRL_MD2PP); 3072 } 3073 3074 /* Auto enable WLAN. */ 3075 urtwn_write_2(sc, R92C_APS_FSMCO, 3076 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3077 for (ntries = 0; ntries < 1000; ntries++) { 3078 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3079 R92C_APS_FSMCO_APFM_ONMAC)) 3080 break; 3081 DELAY(100); 3082 } 3083 if (ntries == 1000) { 3084 aprint_error_dev(sc->sc_dev, 3085 "timeout waiting for MAC auto ON\n"); 3086 return ETIMEDOUT; 3087 } 3088 3089 /* Enable radio, GPIO and LED functions. */ 3090 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3091 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3092 urtwn_write_2(sc, R92C_APS_FSMCO, 3093 R92C_APS_FSMCO_AFSM_HSUS | 3094 R92C_APS_FSMCO_PDN_EN | 3095 R92C_APS_FSMCO_PFM_ALDN); 3096 3097 /* Release RF digital isolation. */ 3098 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3099 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3100 3101 /* Initialize MAC. */ 3102 urtwn_write_1(sc, R92C_APSD_CTRL, 3103 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3104 for (ntries = 0; ntries < 200; ntries++) { 3105 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3106 R92C_APSD_CTRL_OFF_STATUS)) 3107 break; 3108 DELAY(5); 3109 } 3110 if (ntries == 200) { 3111 aprint_error_dev(sc->sc_dev, 3112 "timeout waiting for MAC initialization\n"); 3113 return ETIMEDOUT; 3114 } 3115 3116 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3117 reg = urtwn_read_2(sc, R92C_CR); 3118 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3119 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3120 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3121 R92C_CR_ENSEC; 3122 urtwn_write_2(sc, R92C_CR, reg); 3123 3124 urtwn_write_1(sc, 0xfe10, 0x19); 3125 return 0; 3126 } 3127 3128 static int 3129 urtwn_r92e_power_on(struct urtwn_softc *sc) 3130 { 3131 uint32_t reg; 3132 uint32_t val; 3133 int ntries; 3134 3135 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3136 3137 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3138 3139 /* Enable radio, GPIO and LED functions. */ 3140 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3141 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3142 urtwn_write_2(sc, R92C_APS_FSMCO, 3143 R92C_APS_FSMCO_AFSM_HSUS | 3144 R92C_APS_FSMCO_PDN_EN | 3145 R92C_APS_FSMCO_PFM_ALDN); 3146 3147 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3148 /* LDO. */ 3149 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3150 } 3151 else { 3152 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3153 R92C_SYS_SWR_CTRL2) & 0xffff); 3154 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3155 } 3156 3157 for (ntries = 0; ntries < 2; ntries++) { 3158 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3159 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3160 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3161 R92C_AFE_CTRL4)); 3162 } 3163 3164 /* Reset BB. */ 3165 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3166 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3167 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3168 3169 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3170 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3171 3172 /* Disable HWPDN. */ 3173 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3174 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3175 3176 /* Disable WL suspend. */ 3177 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3178 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3179 R92C_APS_FSMCO_AFSM_HSUS)); 3180 3181 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3182 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3183 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3184 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3185 for (ntries = 0; ntries < 10000; ntries++) { 3186 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3187 R92C_APS_FSMCO_APFM_ONMAC; 3188 if (val == 0x0) 3189 break; 3190 DELAY(10); 3191 } 3192 if (ntries == 10000) { 3193 aprint_error_dev(sc->sc_dev, 3194 "timeout waiting for chip power up\n"); 3195 return ETIMEDOUT; 3196 } 3197 3198 urtwn_write_2(sc, R92C_CR, 0x00); 3199 reg = urtwn_read_2(sc, R92C_CR); 3200 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3201 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3202 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3203 urtwn_write_2(sc, R92C_CR, reg); 3204 3205 return 0; 3206 } 3207 3208 static int 3209 urtwn_r88e_power_on(struct urtwn_softc *sc) 3210 { 3211 uint32_t reg; 3212 uint8_t val; 3213 int ntries; 3214 3215 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3216 3217 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3218 3219 /* Wait for power ready bit. */ 3220 for (ntries = 0; ntries < 5000; ntries++) { 3221 val = urtwn_read_1(sc, 0x6) & 0x2; 3222 if (val == 0x2) 3223 break; 3224 DELAY(10); 3225 } 3226 if (ntries == 5000) { 3227 aprint_error_dev(sc->sc_dev, 3228 "timeout waiting for chip power up\n"); 3229 return ETIMEDOUT; 3230 } 3231 3232 /* Reset BB. */ 3233 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3234 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3235 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3236 3237 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3238 3239 /* Disable HWPDN. */ 3240 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3241 3242 /* Disable WL suspend. */ 3243 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3244 3245 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3246 for (ntries = 0; ntries < 5000; ntries++) { 3247 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3248 break; 3249 DELAY(10); 3250 } 3251 if (ntries == 5000) 3252 return ETIMEDOUT; 3253 3254 /* Enable LDO normal mode. */ 3255 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3256 3257 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3258 urtwn_write_2(sc, R92C_CR, 0); 3259 reg = urtwn_read_2(sc, R92C_CR); 3260 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3261 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3262 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3263 urtwn_write_2(sc, R92C_CR, reg); 3264 3265 return 0; 3266 } 3267 3268 static int 3269 urtwn_llt_init(struct urtwn_softc *sc) 3270 { 3271 size_t i, page_count, pktbuf_count; 3272 uint32_t val; 3273 int error; 3274 3275 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3276 3277 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3278 3279 if (sc->chip & URTWN_CHIP_88E) 3280 page_count = R88E_TX_PAGE_COUNT; 3281 else if (sc->chip & URTWN_CHIP_92EU) 3282 page_count = R92E_TX_PAGE_COUNT; 3283 else 3284 page_count = R92C_TX_PAGE_COUNT; 3285 if (sc->chip & URTWN_CHIP_88E) 3286 pktbuf_count = R88E_TXPKTBUF_COUNT; 3287 else if (sc->chip & URTWN_CHIP_92EU) 3288 pktbuf_count = R88E_TXPKTBUF_COUNT; 3289 else 3290 pktbuf_count = R92C_TXPKTBUF_COUNT; 3291 3292 if (sc->chip & URTWN_CHIP_92EU) { 3293 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3294 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3295 DELAY(100); 3296 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3297 if (val & R92E_AUTO_LLT_EN) 3298 return EIO; 3299 return 0; 3300 } 3301 3302 /* Reserve pages [0; page_count]. */ 3303 for (i = 0; i < page_count; i++) { 3304 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3305 return error; 3306 } 3307 /* NB: 0xff indicates end-of-list. */ 3308 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3309 return error; 3310 /* 3311 * Use pages [page_count + 1; pktbuf_count - 1] 3312 * as ring buffer. 3313 */ 3314 for (++i; i < pktbuf_count - 1; i++) { 3315 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3316 return error; 3317 } 3318 /* Make the last page point to the beginning of the ring buffer. */ 3319 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3320 return error; 3321 } 3322 3323 static void 3324 urtwn_fw_reset(struct urtwn_softc *sc) 3325 { 3326 uint16_t reg; 3327 int ntries; 3328 3329 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3330 3331 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3332 3333 /* Tell 8051 to reset itself. */ 3334 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3335 3336 /* Wait until 8051 resets by itself. */ 3337 for (ntries = 0; ntries < 100; ntries++) { 3338 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3339 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3340 return; 3341 DELAY(50); 3342 } 3343 /* Force 8051 reset. */ 3344 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3345 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3346 } 3347 3348 static void 3349 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3350 { 3351 uint16_t reg; 3352 3353 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3354 3355 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3356 3357 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3358 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3359 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3360 } 3361 DELAY(50); 3362 3363 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3364 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3365 DELAY(50); 3366 3367 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3368 DELAY(50); 3369 3370 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3371 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3372 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3373 } 3374 DELAY(50); 3375 3376 } 3377 3378 static int 3379 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3380 { 3381 uint32_t reg; 3382 int off, mlen, error = 0; 3383 3384 URTWNHIST_FUNC(); 3385 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3386 page, (uintptr_t)buf, len, 0); 3387 3388 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3389 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3390 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3391 3392 off = R92C_FW_START_ADDR; 3393 while (len > 0) { 3394 if (len > 196) 3395 mlen = 196; 3396 else if (len > 4) 3397 mlen = 4; 3398 else 3399 mlen = 1; 3400 error = urtwn_write_region(sc, off, buf, mlen); 3401 if (error != 0) 3402 break; 3403 off += mlen; 3404 buf += mlen; 3405 len -= mlen; 3406 } 3407 return error; 3408 } 3409 3410 static int 3411 urtwn_load_firmware(struct urtwn_softc *sc) 3412 { 3413 firmware_handle_t fwh; 3414 const struct r92c_fw_hdr *hdr; 3415 const char *name; 3416 u_char *fw, *ptr; 3417 size_t len; 3418 uint32_t reg; 3419 int mlen, ntries, page, error; 3420 3421 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3422 3423 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3424 3425 /* Read firmware image from the filesystem. */ 3426 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3427 name = "rtl8188eufw.bin"; 3428 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3429 name = "rtl8192eefw.bin"; 3430 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3431 URTWN_CHIP_UMC_A_CUT) 3432 name = "rtl8192cfwU.bin"; 3433 else 3434 name = "rtl8192cfw.bin"; 3435 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3436 aprint_error_dev(sc->sc_dev, 3437 "failed load firmware of file %s (error %d)\n", name, 3438 error); 3439 return error; 3440 } 3441 const size_t fwlen = len = firmware_get_size(fwh); 3442 fw = firmware_malloc(len); 3443 if (fw == NULL) { 3444 aprint_error_dev(sc->sc_dev, 3445 "failed to allocate firmware memory\n"); 3446 firmware_close(fwh); 3447 return ENOMEM; 3448 } 3449 error = firmware_read(fwh, 0, fw, len); 3450 firmware_close(fwh); 3451 if (error != 0) { 3452 aprint_error_dev(sc->sc_dev, 3453 "failed to read firmware (error %d)\n", error); 3454 firmware_free(fw, fwlen); 3455 return error; 3456 } 3457 3458 len = fwlen; 3459 ptr = fw; 3460 hdr = (const struct r92c_fw_hdr *)ptr; 3461 /* Check if there is a valid FW header and skip it. */ 3462 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3463 (le16toh(hdr->signature) >> 4) == 0x88e || 3464 (le16toh(hdr->signature) >> 4) == 0x92e || 3465 (le16toh(hdr->signature) >> 4) == 0x92c) { 3466 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3467 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3468 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3469 hdr->month, hdr->date, hdr->hour, hdr->minute); 3470 ptr += sizeof(*hdr); 3471 len -= sizeof(*hdr); 3472 } 3473 3474 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3475 /* Reset MCU ready status */ 3476 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3477 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3478 ISSET(sc->chip, URTWN_CHIP_92EU)) 3479 urtwn_r88e_fw_reset(sc); 3480 else 3481 urtwn_fw_reset(sc); 3482 } 3483 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3484 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3485 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3486 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3487 R92C_SYS_FUNC_EN_CPUEN); 3488 } 3489 3490 /* download enabled */ 3491 urtwn_write_1(sc, R92C_MCUFWDL, 3492 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3493 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3494 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3495 3496 /* Reset the FWDL checksum. */ 3497 urtwn_write_1(sc, R92C_MCUFWDL, 3498 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3499 3500 DELAY(50); 3501 /* download firmware */ 3502 for (page = 0; len > 0; page++) { 3503 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3504 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3505 if (error != 0) { 3506 aprint_error_dev(sc->sc_dev, 3507 "could not load firmware page %d\n", page); 3508 goto fail; 3509 } 3510 ptr += mlen; 3511 len -= mlen; 3512 } 3513 3514 /* download disable */ 3515 urtwn_write_1(sc, R92C_MCUFWDL, 3516 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3517 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3518 3519 /* Wait for checksum report. */ 3520 for (ntries = 0; ntries < 1000; ntries++) { 3521 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3522 break; 3523 DELAY(5); 3524 } 3525 if (ntries == 1000) { 3526 aprint_error_dev(sc->sc_dev, 3527 "timeout waiting for checksum report\n"); 3528 error = ETIMEDOUT; 3529 goto fail; 3530 } 3531 3532 /* Wait for firmware readiness. */ 3533 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3534 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3535 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3536 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3537 ISSET(sc->chip, URTWN_CHIP_92EU)) 3538 urtwn_r88e_fw_reset(sc); 3539 for (ntries = 0; ntries < 6000; ntries++) { 3540 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3541 break; 3542 DELAY(5); 3543 } 3544 if (ntries == 6000) { 3545 aprint_error_dev(sc->sc_dev, 3546 "timeout waiting for firmware readiness\n"); 3547 error = ETIMEDOUT; 3548 goto fail; 3549 } 3550 fail: 3551 firmware_free(fw, fwlen); 3552 return error; 3553 } 3554 3555 static __inline int 3556 urtwn_dma_init(struct urtwn_softc *sc) 3557 { 3558 3559 return sc->sc_dma_init(sc); 3560 } 3561 3562 static int 3563 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3564 { 3565 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3566 uint32_t reg; 3567 int error; 3568 3569 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3570 3571 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3572 3573 /* Initialize LLT table. */ 3574 error = urtwn_llt_init(sc); 3575 if (error != 0) 3576 return error; 3577 3578 /* Get Tx queues to USB endpoints mapping. */ 3579 hashq = hasnq = haslq = 0; 3580 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3581 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3582 if (MS(reg, R92C_USB_EP_HQ) != 0) 3583 hashq = 1; 3584 if (MS(reg, R92C_USB_EP_NQ) != 0) 3585 hasnq = 1; 3586 if (MS(reg, R92C_USB_EP_LQ) != 0) 3587 haslq = 1; 3588 nqueues = hashq + hasnq + haslq; 3589 if (nqueues == 0) 3590 return EIO; 3591 /* Get the number of pages for each queue. */ 3592 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3593 /* The remaining pages are assigned to the high priority queue. */ 3594 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3595 3596 /* Set number of pages for normal priority queue. */ 3597 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3598 urtwn_write_4(sc, R92C_RQPN, 3599 /* Set number of pages for public queue. */ 3600 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3601 /* Set number of pages for high priority queue. */ 3602 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3603 /* Set number of pages for low priority queue. */ 3604 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3605 /* Load values. */ 3606 R92C_RQPN_LD); 3607 3608 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3609 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3610 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3611 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3612 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3613 3614 /* Set queue to USB pipe mapping. */ 3615 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3616 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3617 if (nqueues == 1) { 3618 if (hashq) { 3619 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3620 } else if (hasnq) { 3621 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3622 } else { 3623 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3624 } 3625 } else if (nqueues == 2) { 3626 /* All 2-endpoints configs have a high priority queue. */ 3627 if (!hashq) { 3628 return EIO; 3629 } 3630 if (hasnq) { 3631 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3632 } else { 3633 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3634 } 3635 } else { 3636 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3637 } 3638 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3639 3640 /* Set Tx/Rx transfer page boundary. */ 3641 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3642 3643 /* Set Tx/Rx transfer page size. */ 3644 urtwn_write_1(sc, R92C_PBP, 3645 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3646 return 0; 3647 } 3648 3649 static int 3650 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3651 { 3652 usb_interface_descriptor_t *id; 3653 uint32_t reg; 3654 int nqueues; 3655 int error; 3656 3657 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3658 3659 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3660 3661 /* Initialize LLT table. */ 3662 error = urtwn_llt_init(sc); 3663 if (error != 0) 3664 return error; 3665 3666 /* Get Tx queues to USB endpoints mapping. */ 3667 id = usbd_get_interface_descriptor(sc->sc_iface); 3668 nqueues = id->bNumEndpoints - 1; 3669 if (nqueues == 0) 3670 return EIO; 3671 3672 /* Set number of pages for normal priority queue. */ 3673 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3674 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3675 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3676 3677 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3678 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3679 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3680 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3681 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3682 3683 /* Set queue to USB pipe mapping. */ 3684 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3685 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3686 if (nqueues == 1) 3687 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3688 else if (nqueues == 2) 3689 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3690 else 3691 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3692 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3693 3694 /* Set Tx/Rx transfer page boundary. */ 3695 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3696 3697 /* Set Tx/Rx transfer page size. */ 3698 urtwn_write_1(sc, R92C_PBP, 3699 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3700 3701 return 0; 3702 } 3703 3704 static void 3705 urtwn_mac_init(struct urtwn_softc *sc) 3706 { 3707 size_t i; 3708 3709 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3710 3711 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3712 3713 /* Write MAC initialization values. */ 3714 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3715 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3716 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3717 rtl8188eu_mac[i].val); 3718 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3719 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3720 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3721 rtl8192eu_mac[i].val); 3722 } else { 3723 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3724 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3725 rtl8192cu_mac[i].val); 3726 } 3727 } 3728 3729 static void 3730 urtwn_bb_init(struct urtwn_softc *sc) 3731 { 3732 const struct rtwn_bb_prog *prog; 3733 uint32_t reg; 3734 uint8_t crystalcap; 3735 size_t i; 3736 3737 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3738 3739 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3740 3741 /* Enable BB and RF. */ 3742 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3743 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3744 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3745 R92C_SYS_FUNC_EN_DIO_RF); 3746 3747 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3748 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3749 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3750 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3751 } 3752 3753 urtwn_write_1(sc, R92C_RF_CTRL, 3754 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3755 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3756 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3757 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3758 3759 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3760 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3761 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3762 urtwn_write_1(sc, 0x15, 0xe9); 3763 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3764 } 3765 3766 /* Select BB programming based on board type. */ 3767 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3768 prog = &rtl8188eu_bb_prog; 3769 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3770 prog = &rtl8192eu_bb_prog; 3771 else if (!(sc->chip & URTWN_CHIP_92C)) { 3772 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3773 prog = &rtl8188ce_bb_prog; 3774 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3775 prog = &rtl8188ru_bb_prog; 3776 } else { 3777 prog = &rtl8188cu_bb_prog; 3778 } 3779 } else { 3780 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3781 prog = &rtl8192ce_bb_prog; 3782 } else { 3783 prog = &rtl8192cu_bb_prog; 3784 } 3785 } 3786 /* Write BB initialization values. */ 3787 for (i = 0; i < prog->count; i++) { 3788 /* additional delay depend on registers */ 3789 switch (prog->regs[i]) { 3790 case 0xfe: 3791 urtwn_delay_ms(sc, 50); 3792 break; 3793 case 0xfd: 3794 urtwn_delay_ms(sc, 5); 3795 break; 3796 case 0xfc: 3797 urtwn_delay_ms(sc, 1); 3798 break; 3799 case 0xfb: 3800 DELAY(50); 3801 break; 3802 case 0xfa: 3803 DELAY(5); 3804 break; 3805 case 0xf9: 3806 DELAY(1); 3807 break; 3808 } 3809 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3810 DELAY(1); 3811 } 3812 3813 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3814 /* 8192C 1T only configuration. */ 3815 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3816 reg = (reg & ~0x00000003) | 0x2; 3817 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3818 3819 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3820 reg = (reg & ~0x00300033) | 0x00200022; 3821 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3822 3823 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3824 reg = (reg & ~0xff000000) | (0x45 << 24); 3825 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3826 3827 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3828 reg = (reg & ~0x000000ff) | 0x23; 3829 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3830 3831 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3832 reg = (reg & ~0x00000030) | (1 << 4); 3833 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3834 3835 reg = urtwn_bb_read(sc, 0xe74); 3836 reg = (reg & ~0x0c000000) | (2 << 26); 3837 urtwn_bb_write(sc, 0xe74, reg); 3838 reg = urtwn_bb_read(sc, 0xe78); 3839 reg = (reg & ~0x0c000000) | (2 << 26); 3840 urtwn_bb_write(sc, 0xe78, reg); 3841 reg = urtwn_bb_read(sc, 0xe7c); 3842 reg = (reg & ~0x0c000000) | (2 << 26); 3843 urtwn_bb_write(sc, 0xe7c, reg); 3844 reg = urtwn_bb_read(sc, 0xe80); 3845 reg = (reg & ~0x0c000000) | (2 << 26); 3846 urtwn_bb_write(sc, 0xe80, reg); 3847 reg = urtwn_bb_read(sc, 0xe88); 3848 reg = (reg & ~0x0c000000) | (2 << 26); 3849 urtwn_bb_write(sc, 0xe88, reg); 3850 } 3851 3852 /* Write AGC values. */ 3853 for (i = 0; i < prog->agccount; i++) { 3854 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3855 DELAY(1); 3856 } 3857 3858 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3859 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3860 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3861 DELAY(1); 3862 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3863 DELAY(1); 3864 } 3865 3866 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3867 crystalcap = sc->r88e_rom[0xb9]; 3868 if (crystalcap == 0x00) 3869 crystalcap = 0x20; 3870 crystalcap &= 0x3f; 3871 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3872 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3873 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3874 crystalcap | crystalcap << 6)); 3875 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3876 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3877 crystalcap = sc->r88e_rom[0xb9]; 3878 if (crystalcap == 0xff) 3879 crystalcap = 0x20; 3880 crystalcap &= 0x3f; 3881 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3882 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3883 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3884 crystalcap | crystalcap << 6)); 3885 } else { 3886 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3887 R92C_HSSI_PARAM2_CCK_HIPWR) { 3888 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3889 } 3890 } 3891 } 3892 3893 static void 3894 urtwn_rf_init(struct urtwn_softc *sc) 3895 { 3896 const struct rtwn_rf_prog *prog; 3897 uint32_t reg, mask, saved; 3898 size_t i, j, idx; 3899 3900 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3901 3902 /* Select RF programming based on board type. */ 3903 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3904 prog = rtl8188eu_rf_prog; 3905 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3906 prog = rtl8192eu_rf_prog; 3907 else if (!(sc->chip & URTWN_CHIP_92C)) { 3908 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3909 prog = rtl8188ce_rf_prog; 3910 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3911 prog = rtl8188ru_rf_prog; 3912 } else { 3913 prog = rtl8188cu_rf_prog; 3914 } 3915 } else { 3916 prog = rtl8192ce_rf_prog; 3917 } 3918 3919 for (i = 0; i < sc->nrxchains; i++) { 3920 /* Save RF_ENV control type. */ 3921 idx = i / 2; 3922 mask = 0xffffU << ((i % 2) * 16); 3923 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3924 3925 /* Set RF_ENV enable. */ 3926 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3927 reg |= 0x100000; 3928 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3929 DELAY(50); 3930 3931 /* Set RF_ENV output high. */ 3932 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3933 reg |= 0x10; 3934 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3935 DELAY(50); 3936 3937 /* Set address and data lengths of RF registers. */ 3938 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3939 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3940 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3941 DELAY(50); 3942 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3943 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3944 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3945 DELAY(50); 3946 3947 /* Write RF initialization values for this chain. */ 3948 for (j = 0; j < prog[i].count; j++) { 3949 if (prog[i].regs[j] >= 0xf9 && 3950 prog[i].regs[j] <= 0xfe) { 3951 /* 3952 * These are fake RF registers offsets that 3953 * indicate a delay is required. 3954 */ 3955 urtwn_delay_ms(sc, 50); 3956 continue; 3957 } 3958 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3959 DELAY(5); 3960 } 3961 3962 /* Restore RF_ENV control type. */ 3963 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3964 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3965 } 3966 3967 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3968 URTWN_CHIP_UMC_A_CUT) { 3969 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3970 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3971 } 3972 3973 /* Cache RF register CHNLBW. */ 3974 for (i = 0; i < 2; i++) { 3975 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3976 } 3977 } 3978 3979 static void 3980 urtwn_cam_init(struct urtwn_softc *sc) 3981 { 3982 uint32_t content, command; 3983 uint8_t idx; 3984 size_t i; 3985 3986 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3987 3988 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3989 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3990 return; 3991 3992 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3993 content = (idx & 3) 3994 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3995 | R92C_CAM_VALID; 3996 3997 command = R92C_CAMCMD_POLLING 3998 | R92C_CAMCMD_WRITE 3999 | R92C_CAM_CTL0(idx); 4000 4001 urtwn_write_4(sc, R92C_CAMWRITE, content); 4002 urtwn_write_4(sc, R92C_CAMCMD, command); 4003 } 4004 4005 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4006 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4007 if (i == 0) { 4008 content = (idx & 3) 4009 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4010 | R92C_CAM_VALID; 4011 } else { 4012 content = 0; 4013 } 4014 4015 command = R92C_CAMCMD_POLLING 4016 | R92C_CAMCMD_WRITE 4017 | R92C_CAM_CTL0(idx) 4018 | i; 4019 4020 urtwn_write_4(sc, R92C_CAMWRITE, content); 4021 urtwn_write_4(sc, R92C_CAMCMD, command); 4022 } 4023 } 4024 4025 /* Invalidate all CAM entries. */ 4026 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4027 } 4028 4029 static void 4030 urtwn_pa_bias_init(struct urtwn_softc *sc) 4031 { 4032 uint8_t reg; 4033 size_t i; 4034 4035 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4036 4037 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4038 4039 for (i = 0; i < sc->nrxchains; i++) { 4040 if (sc->pa_setting & (1U << i)) 4041 continue; 4042 4043 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4044 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4045 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4046 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4047 } 4048 if (!(sc->pa_setting & 0x10)) { 4049 reg = urtwn_read_1(sc, 0x16); 4050 reg = (reg & ~0xf0) | 0x90; 4051 urtwn_write_1(sc, 0x16, reg); 4052 } 4053 } 4054 4055 static void 4056 urtwn_rxfilter_init(struct urtwn_softc *sc) 4057 { 4058 4059 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4060 4061 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4062 4063 /* Initialize Rx filter. */ 4064 /* TODO: use better filter for monitor mode. */ 4065 urtwn_write_4(sc, R92C_RCR, 4066 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4067 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4068 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4069 /* Accept all multicast frames. */ 4070 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4071 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4072 /* Accept all management frames. */ 4073 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4074 /* Reject all control frames. */ 4075 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4076 /* Accept all data frames. */ 4077 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4078 } 4079 4080 static void 4081 urtwn_edca_init(struct urtwn_softc *sc) 4082 { 4083 4084 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4085 4086 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4087 4088 /* set spec SIFS (used in NAV) */ 4089 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4090 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4091 4092 /* set SIFS CCK/OFDM */ 4093 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4094 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4095 4096 /* TXOP */ 4097 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4098 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4099 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4100 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4101 } 4102 4103 static void 4104 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4105 uint16_t power[URTWN_RIDX_COUNT]) 4106 { 4107 uint32_t reg; 4108 4109 URTWNHIST_FUNC(); 4110 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4111 4112 /* Write per-CCK rate Tx power. */ 4113 if (chain == 0) { 4114 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4115 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4116 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4117 4118 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4119 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4120 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4121 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4122 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4123 } else { 4124 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4125 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4126 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4127 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4128 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4129 4130 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4131 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4132 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4133 } 4134 /* Write per-OFDM rate Tx power. */ 4135 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4136 SM(R92C_TXAGC_RATE06, power[ 4]) | 4137 SM(R92C_TXAGC_RATE09, power[ 5]) | 4138 SM(R92C_TXAGC_RATE12, power[ 6]) | 4139 SM(R92C_TXAGC_RATE18, power[ 7])); 4140 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4141 SM(R92C_TXAGC_RATE24, power[ 8]) | 4142 SM(R92C_TXAGC_RATE36, power[ 9]) | 4143 SM(R92C_TXAGC_RATE48, power[10]) | 4144 SM(R92C_TXAGC_RATE54, power[11])); 4145 /* Write per-MCS Tx power. */ 4146 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4147 SM(R92C_TXAGC_MCS00, power[12]) | 4148 SM(R92C_TXAGC_MCS01, power[13]) | 4149 SM(R92C_TXAGC_MCS02, power[14]) | 4150 SM(R92C_TXAGC_MCS03, power[15])); 4151 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4152 SM(R92C_TXAGC_MCS04, power[16]) | 4153 SM(R92C_TXAGC_MCS05, power[17]) | 4154 SM(R92C_TXAGC_MCS06, power[18]) | 4155 SM(R92C_TXAGC_MCS07, power[19])); 4156 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4157 SM(R92C_TXAGC_MCS08, power[20]) | 4158 SM(R92C_TXAGC_MCS09, power[21]) | 4159 SM(R92C_TXAGC_MCS10, power[22]) | 4160 SM(R92C_TXAGC_MCS11, power[23])); 4161 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4162 SM(R92C_TXAGC_MCS12, power[24]) | 4163 SM(R92C_TXAGC_MCS13, power[25]) | 4164 SM(R92C_TXAGC_MCS14, power[26]) | 4165 SM(R92C_TXAGC_MCS15, power[27])); 4166 } 4167 4168 static void 4169 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4170 uint16_t power[URTWN_RIDX_COUNT]) 4171 { 4172 struct r92c_rom *rom = &sc->rom; 4173 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4174 const struct rtwn_txpwr *base; 4175 int ridx, group; 4176 4177 URTWNHIST_FUNC(); 4178 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4179 4180 /* Determine channel group. */ 4181 if (chan <= 3) { 4182 group = 0; 4183 } else if (chan <= 9) { 4184 group = 1; 4185 } else { 4186 group = 2; 4187 } 4188 4189 /* Get original Tx power based on board type and RF chain. */ 4190 if (!(sc->chip & URTWN_CHIP_92C)) { 4191 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4192 base = &rtl8188ru_txagc[chain]; 4193 } else { 4194 base = &rtl8192cu_txagc[chain]; 4195 } 4196 } else { 4197 base = &rtl8192cu_txagc[chain]; 4198 } 4199 4200 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4201 if (sc->regulatory == 0) { 4202 for (ridx = 0; ridx <= 3; ridx++) { 4203 power[ridx] = base->pwr[0][ridx]; 4204 } 4205 } 4206 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4207 if (sc->regulatory == 3) { 4208 power[ridx] = base->pwr[0][ridx]; 4209 /* Apply vendor limits. */ 4210 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4211 maxpow = rom->ht40_max_pwr[group]; 4212 } else { 4213 maxpow = rom->ht20_max_pwr[group]; 4214 } 4215 maxpow = (maxpow >> (chain * 4)) & 0xf; 4216 if (power[ridx] > maxpow) { 4217 power[ridx] = maxpow; 4218 } 4219 } else if (sc->regulatory == 1) { 4220 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4221 power[ridx] = base->pwr[group][ridx]; 4222 } 4223 } else if (sc->regulatory != 2) { 4224 power[ridx] = base->pwr[0][ridx]; 4225 } 4226 } 4227 4228 /* Compute per-CCK rate Tx power. */ 4229 cckpow = rom->cck_tx_pwr[chain][group]; 4230 for (ridx = 0; ridx <= 3; ridx++) { 4231 power[ridx] += cckpow; 4232 if (power[ridx] > R92C_MAX_TX_PWR) { 4233 power[ridx] = R92C_MAX_TX_PWR; 4234 } 4235 } 4236 4237 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4238 if (sc->ntxchains > 1) { 4239 /* Apply reduction for 2 spatial streams. */ 4240 diff = rom->ht40_2s_tx_pwr_diff[group]; 4241 diff = (diff >> (chain * 4)) & 0xf; 4242 htpow = (htpow > diff) ? htpow - diff : 0; 4243 } 4244 4245 /* Compute per-OFDM rate Tx power. */ 4246 diff = rom->ofdm_tx_pwr_diff[group]; 4247 diff = (diff >> (chain * 4)) & 0xf; 4248 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4249 for (ridx = 4; ridx <= 11; ridx++) { 4250 power[ridx] += ofdmpow; 4251 if (power[ridx] > R92C_MAX_TX_PWR) { 4252 power[ridx] = R92C_MAX_TX_PWR; 4253 } 4254 } 4255 4256 /* Compute per-MCS Tx power. */ 4257 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4258 diff = rom->ht20_tx_pwr_diff[group]; 4259 diff = (diff >> (chain * 4)) & 0xf; 4260 htpow += diff; /* HT40->HT20 correction. */ 4261 } 4262 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4263 power[ridx] += htpow; 4264 if (power[ridx] > R92C_MAX_TX_PWR) { 4265 power[ridx] = R92C_MAX_TX_PWR; 4266 } 4267 } 4268 #ifdef URTWN_DEBUG 4269 if (urtwn_debug & DBG_RF) { 4270 /* Dump per-rate Tx power values. */ 4271 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4272 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4273 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4274 } 4275 #endif 4276 } 4277 4278 void 4279 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4280 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4281 { 4282 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4283 const struct rtwn_r88e_txpwr *base; 4284 int ridx, group; 4285 4286 URTWNHIST_FUNC(); 4287 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4288 4289 /* Determine channel group. */ 4290 if (chan <= 2) 4291 group = 0; 4292 else if (chan <= 5) 4293 group = 1; 4294 else if (chan <= 8) 4295 group = 2; 4296 else if (chan <= 11) 4297 group = 3; 4298 else if (chan <= 13) 4299 group = 4; 4300 else 4301 group = 5; 4302 4303 /* Get original Tx power based on board type and RF chain. */ 4304 base = &rtl8188eu_txagc[chain]; 4305 4306 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4307 if (sc->regulatory == 0) { 4308 for (ridx = 0; ridx <= 3; ridx++) 4309 power[ridx] = base->pwr[0][ridx]; 4310 } 4311 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4312 if (sc->regulatory == 3) 4313 power[ridx] = base->pwr[0][ridx]; 4314 else if (sc->regulatory == 1) { 4315 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4316 power[ridx] = base->pwr[group][ridx]; 4317 } else if (sc->regulatory != 2) 4318 power[ridx] = base->pwr[0][ridx]; 4319 } 4320 4321 /* Compute per-CCK rate Tx power. */ 4322 cckpow = sc->cck_tx_pwr[group]; 4323 for (ridx = 0; ridx <= 3; ridx++) { 4324 power[ridx] += cckpow; 4325 if (power[ridx] > R92C_MAX_TX_PWR) 4326 power[ridx] = R92C_MAX_TX_PWR; 4327 } 4328 4329 htpow = sc->ht40_tx_pwr[group]; 4330 4331 /* Compute per-OFDM rate Tx power. */ 4332 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4333 for (ridx = 4; ridx <= 11; ridx++) { 4334 power[ridx] += ofdmpow; 4335 if (power[ridx] > R92C_MAX_TX_PWR) 4336 power[ridx] = R92C_MAX_TX_PWR; 4337 } 4338 4339 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4340 for (ridx = 12; ridx <= 27; ridx++) { 4341 power[ridx] += bw20pow; 4342 if (power[ridx] > R92C_MAX_TX_PWR) 4343 power[ridx] = R92C_MAX_TX_PWR; 4344 } 4345 } 4346 4347 static void 4348 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4349 { 4350 uint16_t power[URTWN_RIDX_COUNT]; 4351 size_t i; 4352 4353 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4354 4355 for (i = 0; i < sc->ntxchains; i++) { 4356 /* Compute per-rate Tx power values. */ 4357 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4358 ISSET(sc->chip, URTWN_CHIP_92EU)) 4359 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4360 else 4361 urtwn_get_txpower(sc, i, chan, ht40m, power); 4362 /* Write per-rate Tx power values to hardware. */ 4363 urtwn_write_txpower(sc, i, power); 4364 } 4365 } 4366 4367 static void 4368 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4369 { 4370 struct ieee80211com *ic = &sc->sc_ic; 4371 u_int chan; 4372 size_t i; 4373 4374 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4375 4376 URTWNHIST_FUNC(); 4377 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4378 4379 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4380 4381 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4382 chan += 2; 4383 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4384 chan -= 2; 4385 } 4386 4387 /* Set Tx power for this new channel. */ 4388 urtwn_set_txpower(sc, chan, ht40m); 4389 4390 for (i = 0; i < sc->nrxchains; i++) { 4391 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4392 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4393 } 4394 4395 if (ht40m) { 4396 /* Is secondary channel below or above primary? */ 4397 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4398 uint32_t reg; 4399 4400 urtwn_write_1(sc, R92C_BWOPMODE, 4401 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4402 4403 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4404 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4405 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4406 4407 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4408 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4409 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4410 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4411 4412 /* Set CCK side band. */ 4413 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4414 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4415 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4416 4417 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4418 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4419 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4420 4421 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4422 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4423 ~R92C_FPGA0_ANAPARAM2_CBW20); 4424 4425 reg = urtwn_bb_read(sc, 0x818); 4426 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4427 urtwn_bb_write(sc, 0x818, reg); 4428 4429 /* Select 40MHz bandwidth. */ 4430 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4431 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4432 } else { 4433 urtwn_write_1(sc, R92C_BWOPMODE, 4434 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4435 4436 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4437 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4438 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4439 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4440 4441 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4442 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4443 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4444 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4445 R92C_FPGA0_ANAPARAM2_CBW20); 4446 } 4447 4448 /* Select 20MHz bandwidth. */ 4449 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4450 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4451 (ISSET(sc->chip, URTWN_CHIP_88E) || 4452 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4453 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4454 } 4455 } 4456 4457 static void 4458 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4459 { 4460 4461 URTWNHIST_FUNC(); 4462 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4463 4464 uint32_t addaBackup[16], iqkBackup[4], piMode; 4465 4466 #ifdef notyet 4467 uint32_t odfm0_agccore_regs[3]; 4468 uint32_t ant_regs[3]; 4469 uint32_t rf_regs[8]; 4470 #endif 4471 uint32_t reg0, reg1, reg2; 4472 int i, attempt; 4473 4474 #ifdef notyet 4475 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4476 R92E_STBC_SETTING + 2)); 4477 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4478 /* Save AGCCORE regs. */ 4479 for (i = 0; i < sc->nrxchains; i++) { 4480 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4481 R92C_OFDM0_AGCCORE1(i)); 4482 } 4483 #endif 4484 /* Save BB regs. */ 4485 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4486 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4487 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4488 4489 /* Save adda regs to be restored when finished. */ 4490 for (i = 0; i < __arraycount(addaReg); i++) 4491 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4492 /* Save mac regs. */ 4493 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4494 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4495 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4496 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4497 4498 #ifdef notyet 4499 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4500 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4501 4502 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4503 for (i = 0; i < sc->nrxchains; i++) 4504 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4505 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4506 #endif 4507 4508 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4509 R92C_HSSI_PARAM1_PI); 4510 if (piMode == 0) { 4511 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4512 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4513 R92C_HSSI_PARAM1_PI); 4514 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4515 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4516 R92C_HSSI_PARAM1_PI); 4517 } 4518 4519 attempt = 1; 4520 4521 next_attempt: 4522 4523 /* Set mac regs for calibration. */ 4524 for (i = 0; i < __arraycount(addaReg); i++) { 4525 urtwn_bb_write(sc, addaReg[i], 4526 addaReg[__arraycount(addaReg) - 1]); 4527 } 4528 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4529 R92C_CCK0_AFESETTING)); 4530 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4531 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4532 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4533 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4534 4535 if (sc->ntxchains > 1) 4536 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4537 4538 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4539 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4540 ~R92C_BCN_CTRL_EN_BCN)); 4541 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4542 ~R92C_BCN_CTRL_EN_BCN)); 4543 4544 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4545 ~R92C_GPIO_MUXCFG_ENBT)); 4546 4547 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4548 4549 if (sc->ntxchains > 1) 4550 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4551 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4552 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4553 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4554 4555 /* Restore BB regs. */ 4556 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4557 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4558 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4559 4560 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4561 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4562 if (sc->nrxchains > 1) 4563 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4564 4565 if (attempt-- > 0) 4566 goto next_attempt; 4567 4568 /* Restore mode. */ 4569 if (piMode == 0) { 4570 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4571 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4572 ~R92C_HSSI_PARAM1_PI); 4573 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4574 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4575 ~R92C_HSSI_PARAM1_PI); 4576 } 4577 4578 #ifdef notyet 4579 for (i = 0; i < sc->nrxchains; i++) { 4580 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4581 odfm0_agccore_regs[i]); 4582 } 4583 #endif 4584 4585 /* Restore adda regs. */ 4586 for (i = 0; i < __arraycount(addaReg); i++) 4587 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4588 /* Restore mac regs. */ 4589 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4590 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4591 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4592 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4593 4594 #ifdef notyet 4595 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4596 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4597 4598 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4599 for (i = 0; i < sc->nrxchains; i++) 4600 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4601 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4602 #endif 4603 } 4604 4605 static void 4606 urtwn_lc_calib(struct urtwn_softc *sc) 4607 { 4608 uint32_t rf_ac[2]; 4609 uint8_t txmode; 4610 size_t i; 4611 4612 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4613 4614 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4615 4616 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4617 if ((txmode & 0x70) != 0) { 4618 /* Disable all continuous Tx. */ 4619 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4620 4621 /* Set RF mode to standby mode. */ 4622 for (i = 0; i < sc->nrxchains; i++) { 4623 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4624 urtwn_rf_write(sc, i, R92C_RF_AC, 4625 RW(rf_ac[i], R92C_RF_AC_MODE, 4626 R92C_RF_AC_MODE_STANDBY)); 4627 } 4628 } else { 4629 /* Block all Tx queues. */ 4630 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4631 } 4632 /* Start calibration. */ 4633 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4634 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4635 4636 /* Give calibration the time to complete. */ 4637 urtwn_delay_ms(sc, 100); 4638 4639 /* Restore configuration. */ 4640 if ((txmode & 0x70) != 0) { 4641 /* Restore Tx mode. */ 4642 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4643 /* Restore RF mode. */ 4644 for (i = 0; i < sc->nrxchains; i++) { 4645 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4646 } 4647 } else { 4648 /* Unblock all Tx queues. */ 4649 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4650 } 4651 } 4652 4653 static void 4654 urtwn_temp_calib(struct urtwn_softc *sc) 4655 { 4656 int temp, t_meter_reg; 4657 4658 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4659 4660 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4661 4662 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4663 t_meter_reg = R92C_RF_T_METER; 4664 else 4665 t_meter_reg = R92E_RF_T_METER; 4666 4667 if (sc->thcal_state == 0) { 4668 /* Start measuring temperature. */ 4669 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4670 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4671 sc->thcal_state = 1; 4672 return; 4673 } 4674 sc->thcal_state = 0; 4675 4676 /* Read measured temperature. */ 4677 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4678 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4679 if (temp == 0) /* Read failed, skip. */ 4680 return; 4681 4682 /* 4683 * Redo LC calibration if temperature changed significantly since 4684 * last calibration. 4685 */ 4686 if (sc->thcal_lctemp == 0) { 4687 /* First LC calibration is performed in urtwn_init(). */ 4688 sc->thcal_lctemp = temp; 4689 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4690 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4691 sc->thcal_lctemp, temp, 0, 0); 4692 urtwn_lc_calib(sc); 4693 /* Record temperature of last LC calibration. */ 4694 sc->thcal_lctemp = temp; 4695 } 4696 } 4697 4698 static int 4699 urtwn_init(struct ifnet *ifp) 4700 { 4701 struct urtwn_softc *sc = ifp->if_softc; 4702 struct ieee80211com *ic = &sc->sc_ic; 4703 struct urtwn_rx_data *data; 4704 uint32_t reg; 4705 size_t i; 4706 int error; 4707 4708 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4709 4710 urtwn_stop(ifp, 0); 4711 4712 mutex_enter(&sc->sc_write_mtx); 4713 4714 mutex_enter(&sc->sc_task_mtx); 4715 /* Init host async commands ring. */ 4716 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4717 mutex_exit(&sc->sc_task_mtx); 4718 4719 mutex_enter(&sc->sc_fwcmd_mtx); 4720 /* Init firmware commands ring. */ 4721 sc->fwcur = 0; 4722 mutex_exit(&sc->sc_fwcmd_mtx); 4723 4724 /* Allocate Tx/Rx buffers. */ 4725 error = urtwn_alloc_rx_list(sc); 4726 if (error != 0) { 4727 aprint_error_dev(sc->sc_dev, 4728 "could not allocate Rx buffers\n"); 4729 goto fail; 4730 } 4731 error = urtwn_alloc_tx_list(sc); 4732 if (error != 0) { 4733 aprint_error_dev(sc->sc_dev, 4734 "could not allocate Tx buffers\n"); 4735 goto fail; 4736 } 4737 4738 /* Power on adapter. */ 4739 error = urtwn_power_on(sc); 4740 if (error != 0) 4741 goto fail; 4742 4743 /* Initialize DMA. */ 4744 error = urtwn_dma_init(sc); 4745 if (error != 0) 4746 goto fail; 4747 4748 /* Set info size in Rx descriptors (in 64-bit words). */ 4749 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4750 4751 /* Init interrupts. */ 4752 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4753 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4754 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4755 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4756 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4757 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4758 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4759 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4760 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4761 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4762 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4763 } 4764 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4765 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4766 } else { 4767 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4768 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4769 } 4770 4771 /* Set MAC address. */ 4772 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4773 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4774 4775 /* Set initial network type. */ 4776 reg = urtwn_read_4(sc, R92C_CR); 4777 switch (ic->ic_opmode) { 4778 case IEEE80211_M_STA: 4779 default: 4780 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4781 break; 4782 4783 case IEEE80211_M_IBSS: 4784 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4785 break; 4786 } 4787 urtwn_write_4(sc, R92C_CR, reg); 4788 4789 /* Set response rate */ 4790 reg = urtwn_read_4(sc, R92C_RRSR); 4791 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4792 urtwn_write_4(sc, R92C_RRSR, reg); 4793 4794 /* SIFS (used in NAV) */ 4795 urtwn_write_2(sc, R92C_SPEC_SIFS, 4796 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4797 4798 /* Set short/long retry limits. */ 4799 urtwn_write_2(sc, R92C_RL, 4800 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4801 4802 /* Initialize EDCA parameters. */ 4803 urtwn_edca_init(sc); 4804 4805 /* Setup rate fallback. */ 4806 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4807 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4808 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4809 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4810 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4811 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4812 } 4813 4814 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4815 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4816 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4817 /* Set ACK timeout. */ 4818 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4819 4820 /* Setup USB aggregation. */ 4821 /* Tx */ 4822 reg = urtwn_read_4(sc, R92C_TDECTRL); 4823 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4824 urtwn_write_4(sc, R92C_TDECTRL, reg); 4825 /* Rx */ 4826 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4827 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4828 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4829 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4830 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4831 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4832 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4833 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4834 ISSET(sc->chip, URTWN_CHIP_92EU)) 4835 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4836 else 4837 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4838 4839 /* Initialize beacon parameters. */ 4840 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4841 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4842 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4843 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4844 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4845 4846 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4847 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4848 /* Setup AMPDU aggregation. */ 4849 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4850 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4851 urtwn_write_2(sc, 0x4ca, 0x0708); 4852 4853 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4854 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4855 } 4856 4857 /* Load 8051 microcode. */ 4858 error = urtwn_load_firmware(sc); 4859 if (error != 0) 4860 goto fail; 4861 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4862 4863 /* Initialize MAC/BB/RF blocks. */ 4864 /* 4865 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4866 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4867 * XXX: This setting should be removed from rtl8192cu_mac[]. 4868 */ 4869 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4870 urtwn_rxfilter_init(sc); // reset R92C_RCR 4871 urtwn_bb_init(sc); 4872 urtwn_rf_init(sc); 4873 4874 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4875 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4876 urtwn_write_2(sc, R92C_CR, 4877 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4878 R92C_CR_MACRXEN); 4879 } 4880 4881 /* Turn CCK and OFDM blocks on. */ 4882 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4883 reg |= R92C_RFMOD_CCK_EN; 4884 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4885 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4886 reg |= R92C_RFMOD_OFDM_EN; 4887 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4888 4889 /* Clear per-station keys table. */ 4890 urtwn_cam_init(sc); 4891 4892 /* Enable hardware sequence numbering. */ 4893 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4894 4895 /* Perform LO and IQ calibrations. */ 4896 urtwn_iq_calib(sc, sc->iqk_inited); 4897 sc->iqk_inited = true; 4898 4899 /* Perform LC calibration. */ 4900 urtwn_lc_calib(sc); 4901 4902 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4903 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4904 /* Fix USB interference issue. */ 4905 urtwn_write_1(sc, 0xfe40, 0xe0); 4906 urtwn_write_1(sc, 0xfe41, 0x8d); 4907 urtwn_write_1(sc, 0xfe42, 0x80); 4908 urtwn_write_4(sc, 0x20c, 0xfd0320); 4909 4910 urtwn_pa_bias_init(sc); 4911 } 4912 4913 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4914 !(sc->chip & URTWN_CHIP_92EU)) { 4915 /* 1T1R */ 4916 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4917 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4918 } 4919 4920 /* Initialize GPIO setting. */ 4921 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4922 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4923 4924 /* Fix for lower temperature. */ 4925 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4926 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4927 urtwn_write_1(sc, 0x15, 0xe9); 4928 4929 /* Set default channel. */ 4930 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4931 4932 /* Queue Rx xfers. */ 4933 for (size_t j = 0; j < sc->rx_npipe; j++) { 4934 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4935 data = &sc->rx_data[j][i]; 4936 usbd_setup_xfer(data->xfer, data, data->buf, 4937 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4938 urtwn_rxeof); 4939 error = usbd_transfer(data->xfer); 4940 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4941 error != USBD_IN_PROGRESS)) 4942 goto fail; 4943 } 4944 } 4945 4946 /* We're ready to go. */ 4947 ifp->if_flags &= ~IFF_OACTIVE; 4948 ifp->if_flags |= IFF_RUNNING; 4949 sc->sc_running = true; 4950 4951 mutex_exit(&sc->sc_write_mtx); 4952 4953 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4954 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4955 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4956 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4957 urtwn_wait_async(sc); 4958 4959 return 0; 4960 4961 fail: 4962 mutex_exit(&sc->sc_write_mtx); 4963 4964 urtwn_stop(ifp, 1); 4965 return error; 4966 } 4967 4968 static void 4969 urtwn_stop(struct ifnet *ifp, int disable) 4970 { 4971 struct urtwn_softc *sc = ifp->if_softc; 4972 struct ieee80211com *ic = &sc->sc_ic; 4973 size_t i; 4974 int s; 4975 4976 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4977 4978 s = splusb(); 4979 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4980 urtwn_wait_async(sc); 4981 splx(s); 4982 4983 sc->tx_timer = 0; 4984 ifp->if_timer = 0; 4985 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4986 4987 callout_stop(&sc->sc_scan_to); 4988 callout_stop(&sc->sc_calib_to); 4989 4990 /* Abort Tx. */ 4991 for (i = 0; i < sc->tx_npipe; i++) { 4992 if (sc->tx_pipe[i] != NULL) 4993 usbd_abort_pipe(sc->tx_pipe[i]); 4994 } 4995 4996 /* Stop Rx pipe. */ 4997 for (i = 0; i < sc->rx_npipe; i++) { 4998 if (sc->rx_pipe[i] != NULL) 4999 usbd_abort_pipe(sc->rx_pipe[i]); 5000 } 5001 5002 /* Free Tx/Rx buffers. */ 5003 urtwn_free_tx_list(sc); 5004 urtwn_free_rx_list(sc); 5005 5006 sc->sc_running = false; 5007 if (disable) 5008 urtwn_chip_stop(sc); 5009 } 5010 5011 static int 5012 urtwn_reset(struct ifnet *ifp) 5013 { 5014 struct urtwn_softc *sc = ifp->if_softc; 5015 struct ieee80211com *ic = &sc->sc_ic; 5016 5017 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5018 return ENETRESET; 5019 5020 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5021 5022 return 0; 5023 } 5024 5025 static void 5026 urtwn_chip_stop(struct urtwn_softc *sc) 5027 { 5028 uint32_t reg; 5029 bool disabled = true; 5030 5031 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5032 5033 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5034 ISSET(sc->chip, URTWN_CHIP_92EU)) 5035 return; 5036 5037 mutex_enter(&sc->sc_write_mtx); 5038 5039 /* 5040 * RF Off Sequence 5041 */ 5042 /* Pause MAC TX queue */ 5043 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5044 5045 /* Disable RF */ 5046 urtwn_rf_write(sc, 0, 0, 0); 5047 5048 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5049 5050 /* Reset BB state machine */ 5051 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5052 R92C_SYS_FUNC_EN_USBD | 5053 R92C_SYS_FUNC_EN_USBA | 5054 R92C_SYS_FUNC_EN_BB_GLB_RST); 5055 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5056 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5057 5058 /* 5059 * Reset digital sequence 5060 */ 5061 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5062 /* Reset MCU ready status */ 5063 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5064 /* If firmware in ram code, do reset */ 5065 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5066 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5067 ISSET(sc->chip, URTWN_CHIP_92EU)) 5068 urtwn_r88e_fw_reset(sc); 5069 else 5070 urtwn_fw_reset(sc); 5071 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5072 } 5073 } 5074 5075 /* Reset MAC and Enable 8051 */ 5076 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5077 5078 /* Reset MCU ready status */ 5079 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5080 5081 if (disabled) { 5082 /* Disable MAC clock */ 5083 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5084 /* Disable AFE PLL */ 5085 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5086 /* Gated AFE DIG_CLOCK */ 5087 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5088 /* Isolated digital to PON */ 5089 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5090 } 5091 5092 /* 5093 * Pull GPIO PIN to balance level and LED control 5094 */ 5095 /* 1. Disable GPIO[7:0] */ 5096 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5097 5098 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5099 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5100 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5101 5102 /* Disable GPIO[10:8] */ 5103 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5104 5105 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5106 reg |= (((reg & 0x000f) << 4) | 0x0780); 5107 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5108 5109 /* Disable LED0 & 1 */ 5110 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5111 5112 /* 5113 * Reset digital sequence 5114 */ 5115 if (disabled) { 5116 /* Disable ELDR clock */ 5117 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5118 /* Isolated ELDR to PON */ 5119 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5120 } 5121 5122 /* 5123 * Disable analog sequence 5124 */ 5125 if (disabled) { 5126 /* Disable A15 power */ 5127 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5128 /* Disable digital core power */ 5129 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5130 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5131 ~R92C_LDOV12D_CTRL_LDV12_EN); 5132 } 5133 5134 /* Enter PFM mode */ 5135 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5136 5137 /* Set USB suspend */ 5138 urtwn_write_2(sc, R92C_APS_FSMCO, 5139 R92C_APS_FSMCO_APDM_HOST | 5140 R92C_APS_FSMCO_AFSM_HSUS | 5141 R92C_APS_FSMCO_PFM_ALDN); 5142 5143 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5144 5145 mutex_exit(&sc->sc_write_mtx); 5146 } 5147 5148 static void 5149 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5150 { 5151 if (sc->sc_running == false) 5152 DELAY(ms * 1000); 5153 else 5154 usbd_delay_ms(sc->sc_udev, ms); 5155 } 5156 5157 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5158 5159 #ifdef _MODULE 5160 #include "ioconf.c" 5161 #endif 5162 5163 static int 5164 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5165 { 5166 int error = 0; 5167 5168 switch (cmd) { 5169 case MODULE_CMD_INIT: 5170 #ifdef _MODULE 5171 error = config_init_component(cfdriver_ioconf_urtwn, 5172 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5173 #endif 5174 return error; 5175 case MODULE_CMD_FINI: 5176 #ifdef _MODULE 5177 error = config_fini_component(cfdriver_ioconf_urtwn, 5178 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5179 #endif 5180 return error; 5181 default: 5182 return ENOTTY; 5183 } 5184 } 5185
Indexes created Tue Sep 30 17:09:57 GMT 2025