if_urtwn.c revision 1.88
1 /* $NetBSD: if_urtwn.c,v 1.88 2020/06/27 14:34:45 jdolecek Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.88 2020/06/27 14:34:45 jdolecek Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 221 }; 222 #undef URTWN_DEV 223 #undef URTWN_RTL8188E_DEV 224 #undef URTWN_RTL8192EU_DEV 225 226 static int urtwn_match(device_t, cfdata_t, void *); 227 static void urtwn_attach(device_t, device_t, void *); 228 static int urtwn_detach(device_t, int); 229 static int urtwn_activate(device_t, enum devact); 230 231 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 232 urtwn_attach, urtwn_detach, urtwn_activate); 233 234 static int urtwn_open_pipes(struct urtwn_softc *); 235 static void urtwn_close_pipes(struct urtwn_softc *); 236 static int urtwn_alloc_rx_list(struct urtwn_softc *); 237 static void urtwn_free_rx_list(struct urtwn_softc *); 238 static int urtwn_alloc_tx_list(struct urtwn_softc *); 239 static void urtwn_free_tx_list(struct urtwn_softc *); 240 static void urtwn_task(void *); 241 static void urtwn_do_async(struct urtwn_softc *, 242 void (*)(struct urtwn_softc *, void *), void *, int); 243 static void urtwn_wait_async(struct urtwn_softc *); 244 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 245 int); 246 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 247 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 248 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 249 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 250 int); 251 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 252 int); 253 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 254 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 255 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 256 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 257 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 258 uint32_t); 259 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 260 uint32_t); 261 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 262 uint32_t); 263 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 264 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 265 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 266 static void urtwn_efuse_read(struct urtwn_softc *); 267 static void urtwn_efuse_switch_power(struct urtwn_softc *); 268 static int urtwn_read_chipid(struct urtwn_softc *); 269 #ifdef URTWN_DEBUG 270 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 271 #endif 272 static void urtwn_read_rom(struct urtwn_softc *); 273 static void urtwn_r88e_read_rom(struct urtwn_softc *); 274 static int urtwn_media_change(struct ifnet *); 275 static int urtwn_ra_init(struct urtwn_softc *); 276 static int urtwn_get_nettype(struct urtwn_softc *); 277 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 278 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 279 static void urtwn_set_led(struct urtwn_softc *, int, int); 280 static void urtwn_calib_to(void *); 281 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 282 static void urtwn_next_scan(void *); 283 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 284 int); 285 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 286 static int urtwn_wme_update(struct ieee80211com *); 287 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 288 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 289 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 290 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 291 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 292 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 293 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 294 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 295 struct ieee80211_node *, struct urtwn_tx_data *); 296 static struct urtwn_tx_data * 297 urtwn_get_tx_data(struct urtwn_softc *, size_t); 298 static void urtwn_start(struct ifnet *); 299 static void urtwn_watchdog(struct ifnet *); 300 static int urtwn_ioctl(struct ifnet *, u_long, void *); 301 static int urtwn_r92c_power_on(struct urtwn_softc *); 302 static int urtwn_r92e_power_on(struct urtwn_softc *); 303 static int urtwn_r88e_power_on(struct urtwn_softc *); 304 static int urtwn_llt_init(struct urtwn_softc *); 305 static void urtwn_fw_reset(struct urtwn_softc *); 306 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 307 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 308 static int urtwn_load_firmware(struct urtwn_softc *); 309 static int urtwn_r92c_dma_init(struct urtwn_softc *); 310 static int urtwn_r88e_dma_init(struct urtwn_softc *); 311 static void urtwn_mac_init(struct urtwn_softc *); 312 static void urtwn_bb_init(struct urtwn_softc *); 313 static void urtwn_rf_init(struct urtwn_softc *); 314 static void urtwn_cam_init(struct urtwn_softc *); 315 static void urtwn_pa_bias_init(struct urtwn_softc *); 316 static void urtwn_rxfilter_init(struct urtwn_softc *); 317 static void urtwn_edca_init(struct urtwn_softc *); 318 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 319 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 320 uint16_t[]); 321 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 322 u_int, uint16_t[]); 323 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 324 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 325 u_int); 326 static void urtwn_iq_calib(struct urtwn_softc *, bool); 327 static void urtwn_lc_calib(struct urtwn_softc *); 328 static void urtwn_temp_calib(struct urtwn_softc *); 329 static int urtwn_init(struct ifnet *); 330 static void urtwn_stop(struct ifnet *, int); 331 static int urtwn_reset(struct ifnet *); 332 static void urtwn_chip_stop(struct urtwn_softc *); 333 static void urtwn_newassoc(struct ieee80211_node *, int); 334 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 335 336 /* Aliases. */ 337 #define urtwn_bb_write urtwn_write_4 338 #define urtwn_bb_read urtwn_read_4 339 340 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 341 342 static const uint16_t addaReg[] = { 343 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 344 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 345 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 346 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 347 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 348 }; 349 350 static int 351 urtwn_match(device_t parent, cfdata_t match, void *aux) 352 { 353 struct usb_attach_arg *uaa = aux; 354 355 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 356 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 357 } 358 359 static void 360 urtwn_attach(device_t parent, device_t self, void *aux) 361 { 362 struct urtwn_softc *sc = device_private(self); 363 struct ieee80211com *ic = &sc->sc_ic; 364 struct ifnet *ifp = &sc->sc_if; 365 struct usb_attach_arg *uaa = aux; 366 char *devinfop; 367 const struct urtwn_dev *dev; 368 usb_device_request_t req; 369 size_t i; 370 int error; 371 372 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 373 374 sc->sc_dev = self; 375 sc->sc_udev = uaa->uaa_device; 376 377 sc->chip = 0; 378 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 379 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 380 SET(sc->chip, URTWN_CHIP_88E); 381 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 382 SET(sc->chip, URTWN_CHIP_92EU); 383 384 aprint_naive("\n"); 385 aprint_normal("\n"); 386 387 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 388 aprint_normal_dev(self, "%s\n", devinfop); 389 usbd_devinfo_free(devinfop); 390 391 req.bmRequestType = UT_WRITE_DEVICE; 392 req.bRequest = UR_SET_FEATURE; 393 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 394 USETW(req.wIndex, UHF_PORT_SUSPEND); 395 USETW(req.wLength, 0); 396 397 (void) usbd_do_request(sc->sc_udev, &req, 0); 398 399 cv_init(&sc->sc_task_cv, "urtwntsk"); 400 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 401 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 402 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 403 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 404 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 405 406 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 407 408 callout_init(&sc->sc_scan_to, 0); 409 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 410 callout_init(&sc->sc_calib_to, 0); 411 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 412 413 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 414 RND_TYPE_NET, RND_FLAG_DEFAULT); 415 416 error = usbd_set_config_no(sc->sc_udev, 1, 0); 417 if (error != 0) { 418 aprint_error_dev(self, "failed to set configuration" 419 ", err=%s\n", usbd_errstr(error)); 420 goto fail; 421 } 422 423 /* Get the first interface handle. */ 424 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 425 if (error != 0) { 426 aprint_error_dev(self, "could not get interface handle\n"); 427 goto fail; 428 } 429 430 error = urtwn_read_chipid(sc); 431 if (error != 0) { 432 aprint_error_dev(self, "unsupported test chip\n"); 433 goto fail; 434 } 435 436 /* Determine number of Tx/Rx chains. */ 437 if (sc->chip & URTWN_CHIP_92C) { 438 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 439 sc->nrxchains = 2; 440 } else if (sc->chip & URTWN_CHIP_92EU) { 441 sc->ntxchains = 2; 442 sc->nrxchains = 2; 443 } else { 444 sc->ntxchains = 1; 445 sc->nrxchains = 1; 446 } 447 448 if (ISSET(sc->chip, URTWN_CHIP_88E) || 449 ISSET(sc->chip, URTWN_CHIP_92EU)) 450 urtwn_r88e_read_rom(sc); 451 else 452 urtwn_read_rom(sc); 453 454 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 455 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 456 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 457 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 458 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 459 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 460 "8188CUS", sc->ntxchains, sc->nrxchains, 461 ether_sprintf(ic->ic_myaddr)); 462 463 error = urtwn_open_pipes(sc); 464 if (error != 0) { 465 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 466 goto fail; 467 } 468 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 469 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 470 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 471 472 /* 473 * Setup the 802.11 device. 474 */ 475 ic->ic_ifp = ifp; 476 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 477 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 478 ic->ic_state = IEEE80211_S_INIT; 479 480 /* Set device capabilities. */ 481 ic->ic_caps = 482 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 483 IEEE80211_C_IBSS | /* IBSS mode supported */ 484 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 485 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 486 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 487 IEEE80211_C_WME | /* 802.11e */ 488 IEEE80211_C_WPA; /* 802.11i */ 489 490 /* Set supported .11b and .11g rates. */ 491 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 492 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 493 494 /* Set supported .11b and .11g channels (1 through 14). */ 495 for (i = 1; i <= 14; i++) { 496 ic->ic_channels[i].ic_freq = 497 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 498 ic->ic_channels[i].ic_flags = 499 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 500 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 501 } 502 503 ifp->if_softc = sc; 504 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 505 ifp->if_init = urtwn_init; 506 ifp->if_ioctl = urtwn_ioctl; 507 ifp->if_start = urtwn_start; 508 ifp->if_watchdog = urtwn_watchdog; 509 IFQ_SET_READY(&ifp->if_snd); 510 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 511 512 if_initialize(ifp); 513 ieee80211_ifattach(ic); 514 515 /* override default methods */ 516 ic->ic_newassoc = urtwn_newassoc; 517 ic->ic_reset = urtwn_reset; 518 ic->ic_wme.wme_update = urtwn_wme_update; 519 520 /* Override state transition machine. */ 521 sc->sc_newstate = ic->ic_newstate; 522 ic->ic_newstate = urtwn_newstate; 523 524 /* XXX media locking needs revisiting */ 525 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 526 ieee80211_media_init_with_lock(ic, 527 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 528 529 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 530 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 531 &sc->sc_drvbpf); 532 533 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 534 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 535 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 536 537 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 538 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 539 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 540 541 ifp->if_percpuq = if_percpuq_create(ifp); 542 if_register(ifp); 543 544 ieee80211_announce(ic); 545 546 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 547 548 if (!pmf_device_register(self, NULL, NULL)) 549 aprint_error_dev(self, "couldn't establish power handler\n"); 550 551 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 552 return; 553 554 fail: 555 sc->sc_dying = 1; 556 aprint_error_dev(self, "attach failed\n"); 557 } 558 559 static int 560 urtwn_detach(device_t self, int flags) 561 { 562 struct urtwn_softc *sc = device_private(self); 563 struct ifnet *ifp = &sc->sc_if; 564 int s; 565 566 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 567 568 pmf_device_deregister(self); 569 570 s = splusb(); 571 572 sc->sc_dying = 1; 573 574 callout_halt(&sc->sc_scan_to, NULL); 575 callout_halt(&sc->sc_calib_to, NULL); 576 577 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 578 urtwn_stop(ifp, 0); 579 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 580 NULL); 581 582 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 583 bpf_detach(ifp); 584 ieee80211_ifdetach(&sc->sc_ic); 585 if_detach(ifp); 586 587 mutex_destroy(&sc->sc_media_mtx); 588 589 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 590 urtwn_close_pipes(sc); 591 } 592 593 splx(s); 594 595 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 596 597 rnd_detach_source(&sc->rnd_source); 598 599 callout_destroy(&sc->sc_scan_to); 600 callout_destroy(&sc->sc_calib_to); 601 602 cv_destroy(&sc->sc_task_cv); 603 mutex_destroy(&sc->sc_write_mtx); 604 mutex_destroy(&sc->sc_fwcmd_mtx); 605 mutex_destroy(&sc->sc_tx_mtx); 606 mutex_destroy(&sc->sc_rx_mtx); 607 mutex_destroy(&sc->sc_task_mtx); 608 609 return 0; 610 } 611 612 static int 613 urtwn_activate(device_t self, enum devact act) 614 { 615 struct urtwn_softc *sc = device_private(self); 616 617 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 618 619 switch (act) { 620 case DVACT_DEACTIVATE: 621 if_deactivate(sc->sc_ic.ic_ifp); 622 return 0; 623 default: 624 return EOPNOTSUPP; 625 } 626 } 627 628 static int 629 urtwn_open_pipes(struct urtwn_softc *sc) 630 { 631 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 632 static uint8_t epaddr[R92C_MAX_EPOUT]; 633 static uint8_t rxepaddr[R92C_MAX_EPIN]; 634 usb_interface_descriptor_t *id; 635 usb_endpoint_descriptor_t *ed; 636 size_t i, ntx = 0, nrx = 0; 637 int error; 638 639 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 640 641 /* Determine the number of bulk-out pipes. */ 642 id = usbd_get_interface_descriptor(sc->sc_iface); 643 for (i = 0; i < id->bNumEndpoints; i++) { 644 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 645 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 646 continue; 647 } 648 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 649 if (ntx < sizeof(epaddr)) 650 epaddr[ntx] = ed->bEndpointAddress; 651 ntx++; 652 } 653 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 654 if (nrx < sizeof(rxepaddr)) 655 rxepaddr[nrx] = ed->bEndpointAddress; 656 nrx++; 657 } 658 } 659 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 660 aprint_error_dev(sc->sc_dev, 661 "%zd: invalid number of Rx bulk pipes\n", nrx); 662 return EIO; 663 } 664 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 665 aprint_error_dev(sc->sc_dev, 666 "%zd: invalid number of Tx bulk pipes\n", ntx); 667 return EIO; 668 } 669 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 670 nrx, ntx, 0, 0); 671 sc->rx_npipe = nrx; 672 sc->tx_npipe = ntx; 673 674 /* Open bulk-in pipe at address 0x81. */ 675 for (i = 0; i < nrx; i++) { 676 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 677 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 678 if (error != 0) { 679 aprint_error_dev(sc->sc_dev, 680 "could not open Rx bulk pipe 0x%02x: %d\n", 681 rxepaddr[i], error); 682 goto fail; 683 } 684 } 685 686 /* Open bulk-out pipes (up to 3). */ 687 for (i = 0; i < ntx; i++) { 688 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 689 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 690 if (error != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "could not open Tx bulk pipe 0x%02x: %d\n", 693 epaddr[i], error); 694 goto fail; 695 } 696 } 697 698 /* Map 802.11 access categories to USB pipes. */ 699 sc->ac2idx[WME_AC_BK] = 700 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 701 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 702 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 703 704 fail: 705 if (error != 0) 706 urtwn_close_pipes(sc); 707 return error; 708 } 709 710 static void 711 urtwn_close_pipes(struct urtwn_softc *sc) 712 { 713 struct usbd_pipe *pipe; 714 size_t i; 715 716 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 717 718 /* Close Rx pipes. */ 719 CTASSERT(sizeof(pipe) == sizeof(void *)); 720 for (i = 0; i < sc->rx_npipe; i++) { 721 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 722 if (pipe != NULL) { 723 usbd_close_pipe(pipe); 724 } 725 } 726 727 /* Close Tx pipes. */ 728 for (i = 0; i < sc->tx_npipe; i++) { 729 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 730 if (pipe != NULL) { 731 usbd_close_pipe(pipe); 732 } 733 } 734 } 735 736 static int __noinline 737 urtwn_alloc_rx_list(struct urtwn_softc *sc) 738 { 739 struct urtwn_rx_data *data; 740 size_t i; 741 int error = 0; 742 743 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 744 745 for (size_t j = 0; j < sc->rx_npipe; j++) { 746 TAILQ_INIT(&sc->rx_free_list[j]); 747 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 748 data = &sc->rx_data[j][i]; 749 750 data->sc = sc; /* Backpointer for callbacks. */ 751 752 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 753 0, 0, &data->xfer); 754 if (error) { 755 aprint_error_dev(sc->sc_dev, 756 "could not allocate xfer\n"); 757 break; 758 } 759 760 data->buf = usbd_get_buffer(data->xfer); 761 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 762 } 763 } 764 if (error != 0) 765 urtwn_free_rx_list(sc); 766 return error; 767 } 768 769 static void 770 urtwn_free_rx_list(struct urtwn_softc *sc) 771 { 772 struct usbd_xfer *xfer; 773 size_t i; 774 775 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 776 777 /* NB: Caller must abort pipe first. */ 778 for (size_t j = 0; j < sc->rx_npipe; j++) { 779 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 780 CTASSERT(sizeof(xfer) == sizeof(void *)); 781 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 782 if (xfer != NULL) 783 usbd_destroy_xfer(xfer); 784 } 785 } 786 } 787 788 static int __noinline 789 urtwn_alloc_tx_list(struct urtwn_softc *sc) 790 { 791 struct urtwn_tx_data *data; 792 size_t i; 793 int error = 0; 794 795 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 796 797 mutex_enter(&sc->sc_tx_mtx); 798 for (size_t j = 0; j < sc->tx_npipe; j++) { 799 TAILQ_INIT(&sc->tx_free_list[j]); 800 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 801 data = &sc->tx_data[j][i]; 802 803 data->sc = sc; /* Backpointer for callbacks. */ 804 data->pidx = j; 805 806 error = usbd_create_xfer(sc->tx_pipe[j], 807 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 808 &data->xfer); 809 if (error) { 810 aprint_error_dev(sc->sc_dev, 811 "could not allocate xfer\n"); 812 goto fail; 813 } 814 815 data->buf = usbd_get_buffer(data->xfer); 816 817 /* Append this Tx buffer to our free list. */ 818 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 819 } 820 } 821 mutex_exit(&sc->sc_tx_mtx); 822 return 0; 823 824 fail: 825 urtwn_free_tx_list(sc); 826 mutex_exit(&sc->sc_tx_mtx); 827 return error; 828 } 829 830 static void 831 urtwn_free_tx_list(struct urtwn_softc *sc) 832 { 833 struct usbd_xfer *xfer; 834 size_t i; 835 836 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 837 838 /* NB: Caller must abort pipe first. */ 839 for (size_t j = 0; j < sc->tx_npipe; j++) { 840 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 841 CTASSERT(sizeof(xfer) == sizeof(void *)); 842 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 843 if (xfer != NULL) 844 usbd_destroy_xfer(xfer); 845 } 846 } 847 } 848 849 static int 850 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 851 struct ieee80211_node *ni) 852 { 853 struct urtwn_tx_data *data = 854 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 855 return urtwn_tx(sc, m, ni, data); 856 } 857 858 static void 859 urtwn_task(void *arg) 860 { 861 struct urtwn_softc *sc = arg; 862 struct ieee80211com *ic = &sc->sc_ic; 863 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 864 struct urtwn_host_cmd *cmd; 865 int s; 866 867 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 868 if (ic->ic_state == IEEE80211_S_RUN && 869 (ic->ic_opmode == IEEE80211_M_HOSTAP || 870 ic->ic_opmode == IEEE80211_M_IBSS)) { 871 872 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 873 &sc->sc_bo); 874 if (m == NULL) { 875 aprint_error_dev(sc->sc_dev, 876 "could not allocate beacon"); 877 } 878 879 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 880 aprint_error_dev(sc->sc_dev, "could not send beacon"); 881 } 882 883 /* beacon is no longer needed */ 884 m_freem(m); 885 } 886 887 /* Process host commands. */ 888 s = splusb(); 889 mutex_spin_enter(&sc->sc_task_mtx); 890 while (ring->next != ring->cur) { 891 cmd = &ring->cmd[ring->next]; 892 mutex_spin_exit(&sc->sc_task_mtx); 893 splx(s); 894 /* Invoke callback with kernel lock held. */ 895 cmd->cb(sc, cmd->data); 896 s = splusb(); 897 mutex_spin_enter(&sc->sc_task_mtx); 898 ring->queued--; 899 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 900 } 901 cv_broadcast(&sc->sc_task_cv); 902 mutex_spin_exit(&sc->sc_task_mtx); 903 splx(s); 904 } 905 906 static void 907 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 908 void *arg, int len) 909 { 910 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 911 struct urtwn_host_cmd *cmd; 912 int s; 913 914 URTWNHIST_FUNC(); 915 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 916 (uintptr_t)cb, (uintptr_t)arg, len, 0); 917 918 s = splusb(); 919 mutex_spin_enter(&sc->sc_task_mtx); 920 cmd = &ring->cmd[ring->cur]; 921 cmd->cb = cb; 922 KASSERT(len <= sizeof(cmd->data)); 923 memcpy(cmd->data, arg, len); 924 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 925 926 /* If there is no pending command already, schedule a task. */ 927 if (!sc->sc_dying && ++ring->queued == 1) { 928 mutex_spin_exit(&sc->sc_task_mtx); 929 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 930 } else 931 mutex_spin_exit(&sc->sc_task_mtx); 932 splx(s); 933 } 934 935 static void 936 urtwn_wait_async(struct urtwn_softc *sc) 937 { 938 939 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 940 941 /* Wait for all queued asynchronous commands to complete. */ 942 mutex_spin_enter(&sc->sc_task_mtx); 943 while (sc->cmdq.queued > 0) 944 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 945 mutex_spin_exit(&sc->sc_task_mtx); 946 } 947 948 static int 949 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 950 int len) 951 { 952 usb_device_request_t req; 953 usbd_status error; 954 955 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 956 KASSERT(mutex_owned(&sc->sc_write_mtx)); 957 958 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 959 req.bRequest = R92C_REQ_REGS; 960 USETW(req.wValue, addr); 961 USETW(req.wIndex, 0); 962 USETW(req.wLength, len); 963 error = usbd_do_request(sc->sc_udev, &req, buf); 964 if (error != USBD_NORMAL_COMPLETION) { 965 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 966 error, addr, len, 0); 967 } 968 return error; 969 } 970 971 static void 972 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 973 { 974 975 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 976 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 977 978 urtwn_write_region_1(sc, addr, &val, 1); 979 } 980 981 static void 982 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 983 { 984 uint8_t buf[2]; 985 986 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 987 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 988 989 buf[0] = (uint8_t)val; 990 buf[1] = (uint8_t)(val >> 8); 991 urtwn_write_region_1(sc, addr, buf, 2); 992 } 993 994 static void 995 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 996 { 997 uint8_t buf[4]; 998 999 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1000 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1001 1002 buf[0] = (uint8_t)val; 1003 buf[1] = (uint8_t)(val >> 8); 1004 buf[2] = (uint8_t)(val >> 16); 1005 buf[3] = (uint8_t)(val >> 24); 1006 urtwn_write_region_1(sc, addr, buf, 4); 1007 } 1008 1009 static int 1010 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1011 { 1012 1013 URTWNHIST_FUNC(); 1014 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1015 1016 return urtwn_write_region_1(sc, addr, buf, len); 1017 } 1018 1019 static int 1020 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1021 int len) 1022 { 1023 usb_device_request_t req; 1024 usbd_status error; 1025 1026 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1027 1028 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1029 req.bRequest = R92C_REQ_REGS; 1030 USETW(req.wValue, addr); 1031 USETW(req.wIndex, 0); 1032 USETW(req.wLength, len); 1033 error = usbd_do_request(sc->sc_udev, &req, buf); 1034 if (error != USBD_NORMAL_COMPLETION) { 1035 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1036 error, addr, len, 0); 1037 } 1038 return error; 1039 } 1040 1041 static uint8_t 1042 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1043 { 1044 uint8_t val; 1045 1046 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1047 1048 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1049 return 0xff; 1050 1051 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1052 return val; 1053 } 1054 1055 static uint16_t 1056 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1057 { 1058 uint8_t buf[2]; 1059 uint16_t val; 1060 1061 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1062 1063 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1064 return 0xffff; 1065 1066 val = LE_READ_2(&buf[0]); 1067 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1068 return val; 1069 } 1070 1071 static uint32_t 1072 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1073 { 1074 uint8_t buf[4]; 1075 uint32_t val; 1076 1077 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1078 1079 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1080 return 0xffffffff; 1081 1082 val = LE_READ_4(&buf[0]); 1083 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1084 return val; 1085 } 1086 1087 static int 1088 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1089 { 1090 struct r92c_fw_cmd cmd; 1091 uint8_t *cp; 1092 int fwcur; 1093 int ntries; 1094 1095 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1096 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1097 1098 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1099 1100 mutex_enter(&sc->sc_fwcmd_mtx); 1101 fwcur = sc->fwcur; 1102 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1103 mutex_exit(&sc->sc_fwcmd_mtx); 1104 1105 /* Wait for current FW box to be empty. */ 1106 for (ntries = 0; ntries < 100; ntries++) { 1107 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1108 break; 1109 DELAY(2000); 1110 } 1111 if (ntries == 100) { 1112 aprint_error_dev(sc->sc_dev, 1113 "could not send firmware command %d\n", id); 1114 return ETIMEDOUT; 1115 } 1116 1117 memset(&cmd, 0, sizeof(cmd)); 1118 KASSERT(len <= sizeof(cmd.msg)); 1119 memcpy(cmd.msg, buf, len); 1120 1121 /* Write the first word last since that will trigger the FW. */ 1122 cp = (uint8_t *)&cmd; 1123 cmd.id = id; 1124 if (len >= 4) { 1125 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1126 cmd.id |= R92C_CMD_FLAG_EXT; 1127 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1128 &cp[1], 2); 1129 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1130 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1131 ((uint32_t)cp[5] << 24)); 1132 } else { 1133 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1134 &cp[4], 2); 1135 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1136 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1137 ((uint32_t)cp[3] << 24)); 1138 } 1139 } else { 1140 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1141 } 1142 1143 return 0; 1144 } 1145 1146 static __inline void 1147 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1148 { 1149 1150 sc->sc_rf_write(sc, chain, addr, val); 1151 } 1152 1153 static void 1154 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1155 uint32_t val) 1156 { 1157 1158 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1159 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1160 } 1161 1162 static void 1163 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1164 uint32_t val) 1165 { 1166 1167 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1168 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1169 } 1170 1171 static void 1172 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1173 uint32_t val) 1174 { 1175 1176 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1177 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1178 } 1179 1180 static uint32_t 1181 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1182 { 1183 uint32_t reg[R92C_MAX_CHAINS], val; 1184 1185 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1186 if (chain != 0) { 1187 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1188 } 1189 1190 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1191 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1192 DELAY(1000); 1193 1194 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1195 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1196 R92C_HSSI_PARAM2_READ_EDGE); 1197 DELAY(1000); 1198 1199 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1200 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1201 DELAY(1000); 1202 1203 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1204 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1205 } else { 1206 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1207 } 1208 return MS(val, R92C_LSSI_READBACK_DATA); 1209 } 1210 1211 static int 1212 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1213 { 1214 int ntries; 1215 1216 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1217 1218 urtwn_write_4(sc, R92C_LLT_INIT, 1219 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1220 SM(R92C_LLT_INIT_ADDR, addr) | 1221 SM(R92C_LLT_INIT_DATA, data)); 1222 /* Wait for write operation to complete. */ 1223 for (ntries = 0; ntries < 20; ntries++) { 1224 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1225 R92C_LLT_INIT_OP_NO_ACTIVE) { 1226 /* Done */ 1227 return 0; 1228 } 1229 DELAY(5); 1230 } 1231 return ETIMEDOUT; 1232 } 1233 1234 static uint8_t 1235 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1236 { 1237 uint32_t reg; 1238 int ntries; 1239 1240 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1241 1242 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1243 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1244 reg &= ~R92C_EFUSE_CTRL_VALID; 1245 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1246 1247 /* Wait for read operation to complete. */ 1248 for (ntries = 0; ntries < 100; ntries++) { 1249 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1250 if (reg & R92C_EFUSE_CTRL_VALID) { 1251 /* Done */ 1252 return MS(reg, R92C_EFUSE_CTRL_DATA); 1253 } 1254 DELAY(5); 1255 } 1256 aprint_error_dev(sc->sc_dev, 1257 "could not read efuse byte at address 0x%04x\n", addr); 1258 return 0xff; 1259 } 1260 1261 static void 1262 urtwn_efuse_read(struct urtwn_softc *sc) 1263 { 1264 uint8_t *rom = (uint8_t *)&sc->rom; 1265 uint32_t reg; 1266 uint16_t addr = 0; 1267 uint8_t off, msk; 1268 size_t i; 1269 1270 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1271 1272 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1273 1274 urtwn_efuse_switch_power(sc); 1275 1276 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1277 while (addr < 512) { 1278 reg = urtwn_efuse_read_1(sc, addr); 1279 if (reg == 0xff) 1280 break; 1281 addr++; 1282 off = reg >> 4; 1283 msk = reg & 0xf; 1284 for (i = 0; i < 4; i++) { 1285 if (msk & (1U << i)) 1286 continue; 1287 1288 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1289 addr++; 1290 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1291 addr++; 1292 } 1293 } 1294 #ifdef URTWN_DEBUG 1295 /* Dump ROM content. */ 1296 for (i = 0; i < (int)sizeof(sc->rom); i++) 1297 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1298 #endif 1299 } 1300 1301 static void 1302 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1303 { 1304 uint32_t reg; 1305 1306 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1307 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1308 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1309 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1310 } 1311 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1312 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1313 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1314 reg | R92C_SYS_FUNC_EN_ELDR); 1315 } 1316 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1317 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1318 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1319 urtwn_write_2(sc, R92C_SYS_CLKR, 1320 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1321 } 1322 } 1323 1324 static int 1325 urtwn_read_chipid(struct urtwn_softc *sc) 1326 { 1327 uint32_t reg; 1328 1329 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1330 1331 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1332 ISSET(sc->chip, URTWN_CHIP_92EU)) 1333 return 0; 1334 1335 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1336 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1337 /* test chip, not supported */ 1338 return EIO; 1339 } 1340 if (reg & R92C_SYS_CFG_TYPE_92C) { 1341 sc->chip |= URTWN_CHIP_92C; 1342 /* Check if it is a castrated 8192C. */ 1343 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1344 R92C_HPON_FSM_CHIP_BONDING_ID) == 1345 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1346 sc->chip |= URTWN_CHIP_92C_1T2R; 1347 } 1348 } 1349 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1350 sc->chip |= URTWN_CHIP_UMC; 1351 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1352 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1353 } 1354 } 1355 return 0; 1356 } 1357 1358 #ifdef URTWN_DEBUG 1359 static void 1360 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1361 { 1362 1363 aprint_normal_dev(sc->sc_dev, 1364 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1365 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1366 1367 aprint_normal_dev(sc->sc_dev, 1368 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1369 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1370 1371 aprint_normal_dev(sc->sc_dev, 1372 "macaddr %s\n", 1373 ether_sprintf(rp->macaddr)); 1374 1375 aprint_normal_dev(sc->sc_dev, 1376 "string %s, subcustomer_id %#x\n", 1377 rp->string, rp->subcustomer_id); 1378 1379 aprint_normal_dev(sc->sc_dev, 1380 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1381 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1382 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1383 1384 aprint_normal_dev(sc->sc_dev, 1385 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1386 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1387 rp->ht40_1s_tx_pwr[0][2], 1388 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1389 rp->ht40_1s_tx_pwr[1][2]); 1390 1391 aprint_normal_dev(sc->sc_dev, 1392 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1393 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1394 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1395 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1396 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1397 1398 aprint_normal_dev(sc->sc_dev, 1399 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1400 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1401 rp->ht20_tx_pwr_diff[2] & 0xf, 1402 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1403 rp->ht20_tx_pwr_diff[2] >> 4); 1404 1405 aprint_normal_dev(sc->sc_dev, 1406 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1407 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1408 rp->ofdm_tx_pwr_diff[2] & 0xf, 1409 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1410 rp->ofdm_tx_pwr_diff[2] >> 4); 1411 1412 aprint_normal_dev(sc->sc_dev, 1413 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1414 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1415 rp->ht40_max_pwr[2] & 0xf, 1416 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1417 rp->ht40_max_pwr[2] >> 4); 1418 1419 aprint_normal_dev(sc->sc_dev, 1420 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1421 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1422 rp->ht20_max_pwr[2] & 0xf, 1423 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1424 rp->ht20_max_pwr[2] >> 4); 1425 1426 aprint_normal_dev(sc->sc_dev, 1427 "xtal_calib %d, tssi %d %d, thermal %d\n", 1428 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1429 1430 aprint_normal_dev(sc->sc_dev, 1431 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1432 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1433 1434 aprint_normal_dev(sc->sc_dev, 1435 "channnel_plan %d, version %d customer_id %#x\n", 1436 rp->channel_plan, rp->version, rp->curstomer_id); 1437 } 1438 #endif 1439 1440 static void 1441 urtwn_read_rom(struct urtwn_softc *sc) 1442 { 1443 struct ieee80211com *ic = &sc->sc_ic; 1444 struct r92c_rom *rom = &sc->rom; 1445 1446 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1447 1448 mutex_enter(&sc->sc_write_mtx); 1449 1450 /* Read full ROM image. */ 1451 urtwn_efuse_read(sc); 1452 #ifdef URTWN_DEBUG 1453 if (urtwn_debug & DBG_REG) 1454 urtwn_dump_rom(sc, rom); 1455 #endif 1456 1457 /* XXX Weird but this is what the vendor driver does. */ 1458 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1459 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1460 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1461 1462 DPRINTFN(DBG_INIT, 1463 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1464 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1465 1466 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1467 1468 sc->sc_rf_write = urtwn_r92c_rf_write; 1469 sc->sc_power_on = urtwn_r92c_power_on; 1470 sc->sc_dma_init = urtwn_r92c_dma_init; 1471 1472 mutex_exit(&sc->sc_write_mtx); 1473 } 1474 1475 static void 1476 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1477 { 1478 struct ieee80211com *ic = &sc->sc_ic; 1479 uint8_t *rom = sc->r88e_rom; 1480 uint32_t reg; 1481 uint16_t addr = 0; 1482 uint8_t off, msk, tmp; 1483 int i; 1484 1485 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1486 1487 mutex_enter(&sc->sc_write_mtx); 1488 1489 off = 0; 1490 urtwn_efuse_switch_power(sc); 1491 1492 /* Read full ROM image. */ 1493 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1494 while (addr < 4096) { 1495 reg = urtwn_efuse_read_1(sc, addr); 1496 if (reg == 0xff) 1497 break; 1498 addr++; 1499 if ((reg & 0x1f) == 0x0f) { 1500 tmp = (reg & 0xe0) >> 5; 1501 reg = urtwn_efuse_read_1(sc, addr); 1502 if ((reg & 0x0f) != 0x0f) 1503 off = ((reg & 0xf0) >> 1) | tmp; 1504 addr++; 1505 } else 1506 off = reg >> 4; 1507 msk = reg & 0xf; 1508 for (i = 0; i < 4; i++) { 1509 if (msk & (1 << i)) 1510 continue; 1511 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1512 addr++; 1513 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1514 addr++; 1515 } 1516 } 1517 #ifdef URTWN_DEBUG 1518 if (urtwn_debug & DBG_REG) { 1519 } 1520 #endif 1521 1522 addr = 0x10; 1523 for (i = 0; i < 6; i++) 1524 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1525 for (i = 0; i < 5; i++) 1526 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1527 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1528 if (sc->bw20_tx_pwr_diff & 0x08) 1529 sc->bw20_tx_pwr_diff |= 0xf0; 1530 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1531 if (sc->ofdm_tx_pwr_diff & 0x08) 1532 sc->ofdm_tx_pwr_diff |= 0xf0; 1533 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1534 1535 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1536 1537 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1538 sc->sc_power_on = urtwn_r92e_power_on; 1539 sc->sc_rf_write = urtwn_r92e_rf_write; 1540 } else { 1541 sc->sc_power_on = urtwn_r88e_power_on; 1542 sc->sc_rf_write = urtwn_r88e_rf_write; 1543 } 1544 sc->sc_dma_init = urtwn_r88e_dma_init; 1545 1546 mutex_exit(&sc->sc_write_mtx); 1547 } 1548 1549 static int 1550 urtwn_media_change(struct ifnet *ifp) 1551 { 1552 int error; 1553 1554 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1555 1556 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1557 return error; 1558 1559 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1560 (IFF_UP | IFF_RUNNING)) { 1561 urtwn_init(ifp); 1562 } 1563 return 0; 1564 } 1565 1566 /* 1567 * Initialize rate adaptation in firmware. 1568 */ 1569 static int __noinline 1570 urtwn_ra_init(struct urtwn_softc *sc) 1571 { 1572 static const uint8_t map[] = { 1573 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1574 }; 1575 struct ieee80211com *ic = &sc->sc_ic; 1576 struct ieee80211_node *ni = ic->ic_bss; 1577 struct ieee80211_rateset *rs = &ni->ni_rates; 1578 struct r92c_fw_cmd_macid_cfg cmd; 1579 uint32_t rates, basicrates; 1580 uint32_t rrsr_mask, rrsr_rate; 1581 uint8_t mode; 1582 size_t maxrate, maxbasicrate, i, j; 1583 int error; 1584 1585 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1586 1587 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1588 1589 /* Get normal and basic rates mask. */ 1590 rates = basicrates = 1; 1591 maxrate = maxbasicrate = 0; 1592 for (i = 0; i < rs->rs_nrates; i++) { 1593 /* Convert 802.11 rate to HW rate index. */ 1594 for (j = 0; j < __arraycount(map); j++) { 1595 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1596 break; 1597 } 1598 } 1599 if (j == __arraycount(map)) { 1600 /* Unknown rate, skip. */ 1601 continue; 1602 } 1603 1604 rates |= 1U << j; 1605 if (j > maxrate) { 1606 maxrate = j; 1607 } 1608 1609 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1610 basicrates |= 1U << j; 1611 if (j > maxbasicrate) { 1612 maxbasicrate = j; 1613 } 1614 } 1615 } 1616 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1617 mode = R92C_RAID_11B; 1618 } else { 1619 mode = R92C_RAID_11BG; 1620 } 1621 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1622 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1623 "maxrate=%jx, maxbasicrate=%jx", 1624 rates, basicrates, maxrate, maxbasicrate); 1625 1626 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1627 maxbasicrate |= R92C_RATE_SHORTGI; 1628 maxrate |= R92C_RATE_SHORTGI; 1629 } 1630 1631 /* Set rates mask for group addressed frames. */ 1632 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1633 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1634 cmd.macid |= RTWN_MACID_SHORTGI; 1635 cmd.mask = htole32((mode << 28) | basicrates); 1636 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1637 if (error != 0) { 1638 aprint_error_dev(sc->sc_dev, 1639 "could not add broadcast station\n"); 1640 return error; 1641 } 1642 /* Set initial MRR rate. */ 1643 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1644 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1645 1646 /* Set rates mask for unicast frames. */ 1647 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1648 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1649 cmd.macid |= RTWN_MACID_SHORTGI; 1650 cmd.mask = htole32((mode << 28) | rates); 1651 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1652 if (error != 0) { 1653 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1654 return error; 1655 } 1656 /* Set initial MRR rate. */ 1657 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1658 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1659 1660 rrsr_rate = ic->ic_fixed_rate; 1661 if (rrsr_rate == -1) 1662 rrsr_rate = 11; 1663 1664 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1665 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1666 1667 /* Indicate highest supported rate. */ 1668 ni->ni_txrate = rs->rs_nrates - 1; 1669 1670 return 0; 1671 } 1672 1673 static int 1674 urtwn_get_nettype(struct urtwn_softc *sc) 1675 { 1676 struct ieee80211com *ic = &sc->sc_ic; 1677 int type; 1678 1679 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1680 1681 switch (ic->ic_opmode) { 1682 case IEEE80211_M_STA: 1683 type = R92C_CR_NETTYPE_INFRA; 1684 break; 1685 1686 case IEEE80211_M_IBSS: 1687 type = R92C_CR_NETTYPE_ADHOC; 1688 break; 1689 1690 default: 1691 type = R92C_CR_NETTYPE_NOLINK; 1692 break; 1693 } 1694 1695 return type; 1696 } 1697 1698 static void 1699 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1700 { 1701 uint8_t reg; 1702 1703 URTWNHIST_FUNC(); 1704 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1705 1706 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1707 1708 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1709 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1710 } 1711 1712 static void 1713 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1714 { 1715 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1716 uint64_t tsf; 1717 1718 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1719 1720 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1721 1722 /* Enable TSF synchronization. */ 1723 urtwn_write_1(sc, R92C_BCN_CTRL, 1724 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1725 1726 /* Correct TSF */ 1727 urtwn_write_1(sc, R92C_BCN_CTRL, 1728 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1729 1730 /* Set initial TSF. */ 1731 tsf = ni->ni_tstamp.tsf; 1732 tsf = le64toh(tsf); 1733 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1734 tsf -= IEEE80211_DUR_TU; 1735 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1736 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1737 1738 urtwn_write_1(sc, R92C_BCN_CTRL, 1739 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1740 } 1741 1742 static void 1743 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1744 { 1745 uint8_t reg; 1746 1747 URTWNHIST_FUNC(); 1748 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1749 1750 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1751 1752 if (led == URTWN_LED_LINK) { 1753 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1754 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1755 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1756 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1757 (R92C_LEDCFG0_DIS << 1)); 1758 if (on) { 1759 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1760 R92E_LEDSON; 1761 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1762 } 1763 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1764 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1765 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1766 if (!on) { 1767 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1768 urtwn_write_1(sc, R92C_LEDCFG2, 1769 reg | R92C_LEDCFG0_DIS); 1770 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1771 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1772 reg & 0xfe); 1773 } 1774 } else { 1775 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1776 if (!on) { 1777 reg |= R92C_LEDCFG0_DIS; 1778 } 1779 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1780 } 1781 sc->ledlink = on; /* Save LED state. */ 1782 } 1783 } 1784 1785 static void 1786 urtwn_calib_to(void *arg) 1787 { 1788 struct urtwn_softc *sc = arg; 1789 1790 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1791 1792 if (sc->sc_dying) 1793 return; 1794 1795 /* Do it in a process context. */ 1796 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1797 } 1798 1799 /* ARGSUSED */ 1800 static void 1801 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1802 { 1803 struct r92c_fw_cmd_rssi cmd; 1804 struct r92e_fw_cmd_rssi cmde; 1805 1806 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1807 1808 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1809 goto restart_timer; 1810 1811 mutex_enter(&sc->sc_write_mtx); 1812 if (sc->avg_pwdb != -1) { 1813 /* Indicate Rx signal strength to FW for rate adaptation. */ 1814 memset(&cmd, 0, sizeof(cmd)); 1815 memset(&cmde, 0, sizeof(cmde)); 1816 cmd.macid = 0; /* BSS. */ 1817 cmde.macid = 0; /* BSS. */ 1818 cmd.pwdb = sc->avg_pwdb; 1819 cmde.pwdb = sc->avg_pwdb; 1820 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1821 sc->avg_pwdb, 0, 0, 0); 1822 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1823 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1824 sizeof(cmd)); 1825 } else { 1826 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1827 sizeof(cmde)); 1828 } 1829 } 1830 1831 /* Do temperature compensation. */ 1832 urtwn_temp_calib(sc); 1833 mutex_exit(&sc->sc_write_mtx); 1834 1835 restart_timer: 1836 if (!sc->sc_dying) { 1837 /* Restart calibration timer. */ 1838 callout_schedule(&sc->sc_calib_to, hz); 1839 } 1840 } 1841 1842 static void 1843 urtwn_next_scan(void *arg) 1844 { 1845 struct urtwn_softc *sc = arg; 1846 int s; 1847 1848 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1849 1850 if (sc->sc_dying) 1851 return; 1852 1853 s = splnet(); 1854 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1855 ieee80211_next_scan(&sc->sc_ic); 1856 splx(s); 1857 } 1858 1859 static void 1860 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1861 { 1862 URTWNHIST_FUNC(); 1863 URTWNHIST_CALLARGS("new node %06jx%06jx", 1864 ni->ni_macaddr[0] << 2 | 1865 ni->ni_macaddr[1] << 1 | 1866 ni->ni_macaddr[2], 1867 ni->ni_macaddr[3] << 2 | 1868 ni->ni_macaddr[4] << 1 | 1869 ni->ni_macaddr[5], 1870 0, 0); 1871 /* start with lowest Tx rate */ 1872 ni->ni_txrate = 0; 1873 } 1874 1875 static int 1876 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1877 { 1878 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1879 struct urtwn_cmd_newstate cmd; 1880 1881 URTWNHIST_FUNC(); 1882 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1883 1884 callout_stop(&sc->sc_scan_to); 1885 callout_stop(&sc->sc_calib_to); 1886 1887 /* Do it in a process context. */ 1888 cmd.state = nstate; 1889 cmd.arg = arg; 1890 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1891 return 0; 1892 } 1893 1894 static void 1895 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1896 { 1897 struct urtwn_cmd_newstate *cmd = arg; 1898 struct ieee80211com *ic = &sc->sc_ic; 1899 struct ieee80211_node *ni; 1900 enum ieee80211_state ostate = ic->ic_state; 1901 enum ieee80211_state nstate = cmd->state; 1902 uint32_t reg; 1903 uint8_t sifs_time, msr; 1904 int s; 1905 1906 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1907 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1908 1909 s = splnet(); 1910 mutex_enter(&sc->sc_write_mtx); 1911 1912 callout_stop(&sc->sc_scan_to); 1913 callout_stop(&sc->sc_calib_to); 1914 1915 switch (ostate) { 1916 case IEEE80211_S_INIT: 1917 break; 1918 1919 case IEEE80211_S_SCAN: 1920 if (nstate != IEEE80211_S_SCAN) { 1921 /* 1922 * End of scanning 1923 */ 1924 /* flush 4-AC Queue after site_survey */ 1925 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1926 1927 /* Allow Rx from our BSSID only. */ 1928 urtwn_write_4(sc, R92C_RCR, 1929 urtwn_read_4(sc, R92C_RCR) | 1930 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1931 } 1932 break; 1933 1934 case IEEE80211_S_AUTH: 1935 case IEEE80211_S_ASSOC: 1936 break; 1937 1938 case IEEE80211_S_RUN: 1939 /* Turn link LED off. */ 1940 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1941 1942 /* Set media status to 'No Link'. */ 1943 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1944 1945 /* Stop Rx of data frames. */ 1946 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1947 1948 /* Reset TSF. */ 1949 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1950 1951 /* Disable TSF synchronization. */ 1952 urtwn_write_1(sc, R92C_BCN_CTRL, 1953 urtwn_read_1(sc, R92C_BCN_CTRL) | 1954 R92C_BCN_CTRL_DIS_TSF_UDT0); 1955 1956 /* Back to 20MHz mode */ 1957 urtwn_set_chan(sc, ic->ic_curchan, 1958 IEEE80211_HTINFO_2NDCHAN_NONE); 1959 1960 if (ic->ic_opmode == IEEE80211_M_IBSS || 1961 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1962 /* Stop BCN */ 1963 urtwn_write_1(sc, R92C_BCN_CTRL, 1964 urtwn_read_1(sc, R92C_BCN_CTRL) & 1965 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1966 } 1967 1968 /* Reset EDCA parameters. */ 1969 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1970 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1971 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1972 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1973 1974 /* flush all cam entries */ 1975 urtwn_cam_init(sc); 1976 break; 1977 } 1978 1979 switch (nstate) { 1980 case IEEE80211_S_INIT: 1981 /* Turn link LED off. */ 1982 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1983 break; 1984 1985 case IEEE80211_S_SCAN: 1986 if (ostate != IEEE80211_S_SCAN) { 1987 /* 1988 * Begin of scanning 1989 */ 1990 1991 /* Set gain for scanning. */ 1992 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1993 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1994 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1995 1996 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1997 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1998 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1999 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2000 } 2001 2002 /* Set media status to 'No Link'. */ 2003 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2004 2005 /* Allow Rx from any BSSID. */ 2006 urtwn_write_4(sc, R92C_RCR, 2007 urtwn_read_4(sc, R92C_RCR) & 2008 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2009 2010 /* Stop Rx of data frames. */ 2011 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2012 2013 /* Disable update TSF */ 2014 urtwn_write_1(sc, R92C_BCN_CTRL, 2015 urtwn_read_1(sc, R92C_BCN_CTRL) | 2016 R92C_BCN_CTRL_DIS_TSF_UDT0); 2017 } 2018 2019 /* Make link LED blink during scan. */ 2020 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2021 2022 /* Pause AC Tx queues. */ 2023 urtwn_write_1(sc, R92C_TXPAUSE, 2024 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2025 2026 urtwn_set_chan(sc, ic->ic_curchan, 2027 IEEE80211_HTINFO_2NDCHAN_NONE); 2028 2029 /* Start periodic scan. */ 2030 if (!sc->sc_dying) 2031 callout_schedule(&sc->sc_scan_to, hz / 5); 2032 break; 2033 2034 case IEEE80211_S_AUTH: 2035 /* Set initial gain under link. */ 2036 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2037 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2038 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2039 2040 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2041 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2042 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2043 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2044 } 2045 2046 /* Set media status to 'No Link'. */ 2047 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2048 2049 /* Allow Rx from any BSSID. */ 2050 urtwn_write_4(sc, R92C_RCR, 2051 urtwn_read_4(sc, R92C_RCR) & 2052 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2053 2054 urtwn_set_chan(sc, ic->ic_curchan, 2055 IEEE80211_HTINFO_2NDCHAN_NONE); 2056 break; 2057 2058 case IEEE80211_S_ASSOC: 2059 break; 2060 2061 case IEEE80211_S_RUN: 2062 ni = ic->ic_bss; 2063 2064 /* XXX: Set 20MHz mode */ 2065 urtwn_set_chan(sc, ic->ic_curchan, 2066 IEEE80211_HTINFO_2NDCHAN_NONE); 2067 2068 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2069 /* Back to 20MHz mode */ 2070 urtwn_set_chan(sc, ic->ic_curchan, 2071 IEEE80211_HTINFO_2NDCHAN_NONE); 2072 2073 /* Set media status to 'No Link'. */ 2074 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2075 2076 /* Enable Rx of data frames. */ 2077 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2078 2079 /* Allow Rx from any BSSID. */ 2080 urtwn_write_4(sc, R92C_RCR, 2081 urtwn_read_4(sc, R92C_RCR) & 2082 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2083 2084 /* Accept Rx data/control/management frames */ 2085 urtwn_write_4(sc, R92C_RCR, 2086 urtwn_read_4(sc, R92C_RCR) | 2087 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2088 2089 /* Turn link LED on. */ 2090 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2091 break; 2092 } 2093 2094 /* Set media status to 'Associated'. */ 2095 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2096 2097 /* Set BSSID. */ 2098 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2099 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2100 2101 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2102 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2103 } else { 2104 /* 802.11b/g */ 2105 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2106 } 2107 2108 /* Enable Rx of data frames. */ 2109 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2110 2111 /* Set beacon interval. */ 2112 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2113 2114 msr = urtwn_read_1(sc, R92C_MSR); 2115 msr &= R92C_MSR_MASK; 2116 switch (ic->ic_opmode) { 2117 case IEEE80211_M_STA: 2118 /* Allow Rx from our BSSID only. */ 2119 urtwn_write_4(sc, R92C_RCR, 2120 urtwn_read_4(sc, R92C_RCR) | 2121 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2122 2123 /* Enable TSF synchronization. */ 2124 urtwn_tsf_sync_enable(sc); 2125 2126 msr |= R92C_MSR_INFRA; 2127 break; 2128 case IEEE80211_M_HOSTAP: 2129 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2130 2131 /* Allow Rx from any BSSID. */ 2132 urtwn_write_4(sc, R92C_RCR, 2133 urtwn_read_4(sc, R92C_RCR) & 2134 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2135 2136 /* Reset TSF timer to zero. */ 2137 reg = urtwn_read_4(sc, R92C_TCR); 2138 reg &= ~0x01; 2139 urtwn_write_4(sc, R92C_TCR, reg); 2140 reg |= 0x01; 2141 urtwn_write_4(sc, R92C_TCR, reg); 2142 2143 msr |= R92C_MSR_AP; 2144 break; 2145 default: 2146 msr |= R92C_MSR_ADHOC; 2147 break; 2148 } 2149 urtwn_write_1(sc, R92C_MSR, msr); 2150 2151 sifs_time = 10; 2152 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2153 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2154 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2155 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2156 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2157 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2158 2159 /* Initialize rate adaptation. */ 2160 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2161 ISSET(sc->chip, URTWN_CHIP_92EU)) 2162 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2163 else 2164 urtwn_ra_init(sc); 2165 2166 /* Turn link LED on. */ 2167 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2168 2169 /* Reset average RSSI. */ 2170 sc->avg_pwdb = -1; 2171 2172 /* Reset temperature calibration state machine. */ 2173 sc->thcal_state = 0; 2174 sc->thcal_lctemp = 0; 2175 2176 /* Start periodic calibration. */ 2177 if (!sc->sc_dying) 2178 callout_schedule(&sc->sc_calib_to, hz); 2179 break; 2180 } 2181 2182 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2183 2184 mutex_exit(&sc->sc_write_mtx); 2185 splx(s); 2186 } 2187 2188 static int 2189 urtwn_wme_update(struct ieee80211com *ic) 2190 { 2191 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2192 2193 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2194 2195 /* don't override default WME values if WME is not actually enabled */ 2196 if (!(ic->ic_flags & IEEE80211_F_WME)) 2197 return 0; 2198 2199 /* Do it in a process context. */ 2200 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2201 return 0; 2202 } 2203 2204 static void 2205 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2206 { 2207 static const uint16_t ac2reg[WME_NUM_AC] = { 2208 R92C_EDCA_BE_PARAM, 2209 R92C_EDCA_BK_PARAM, 2210 R92C_EDCA_VI_PARAM, 2211 R92C_EDCA_VO_PARAM 2212 }; 2213 struct ieee80211com *ic = &sc->sc_ic; 2214 const struct wmeParams *wmep; 2215 int ac, aifs, slottime; 2216 int s; 2217 2218 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2219 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2220 2221 s = splnet(); 2222 mutex_enter(&sc->sc_write_mtx); 2223 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2224 for (ac = 0; ac < WME_NUM_AC; ac++) { 2225 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2226 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2227 aifs = wmep->wmep_aifsn * slottime + 10; 2228 urtwn_write_4(sc, ac2reg[ac], 2229 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2230 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2231 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2232 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2233 } 2234 mutex_exit(&sc->sc_write_mtx); 2235 splx(s); 2236 } 2237 2238 static void 2239 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2240 { 2241 int pwdb; 2242 2243 URTWNHIST_FUNC(); 2244 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2245 2246 /* Convert antenna signal to percentage. */ 2247 if (rssi <= -100 || rssi >= 20) 2248 pwdb = 0; 2249 else if (rssi >= 0) 2250 pwdb = 100; 2251 else 2252 pwdb = 100 + rssi; 2253 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2254 if (rate <= 3) { 2255 /* CCK gain is smaller than OFDM/MCS gain. */ 2256 pwdb += 6; 2257 if (pwdb > 100) 2258 pwdb = 100; 2259 if (pwdb <= 14) 2260 pwdb -= 4; 2261 else if (pwdb <= 26) 2262 pwdb -= 8; 2263 else if (pwdb <= 34) 2264 pwdb -= 6; 2265 else if (pwdb <= 42) 2266 pwdb -= 2; 2267 } 2268 } 2269 if (sc->avg_pwdb == -1) /* Init. */ 2270 sc->avg_pwdb = pwdb; 2271 else if (sc->avg_pwdb < pwdb) 2272 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2273 else 2274 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2275 2276 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2277 rate, rssi, pwdb, sc->avg_pwdb); 2278 } 2279 2280 static int8_t 2281 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2282 { 2283 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2284 struct r92c_rx_phystat *phy; 2285 struct r92c_rx_cck *cck; 2286 uint8_t rpt; 2287 int8_t rssi; 2288 2289 URTWNHIST_FUNC(); 2290 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2291 2292 if (rate <= 3) { 2293 cck = (struct r92c_rx_cck *)physt; 2294 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2295 rpt = (cck->agc_rpt >> 5) & 0x3; 2296 rssi = (cck->agc_rpt & 0x1f) << 1; 2297 } else { 2298 rpt = (cck->agc_rpt >> 6) & 0x3; 2299 rssi = cck->agc_rpt & 0x3e; 2300 } 2301 rssi = cckoff[rpt] - rssi; 2302 } else { /* OFDM/HT. */ 2303 phy = (struct r92c_rx_phystat *)physt; 2304 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2305 } 2306 return rssi; 2307 } 2308 2309 static int8_t 2310 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2311 { 2312 struct r92c_rx_phystat *phy; 2313 struct r88e_rx_cck *cck; 2314 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2315 int8_t rssi; 2316 2317 URTWNHIST_FUNC(); 2318 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2319 2320 rssi = 0; 2321 if (rate <= 3) { 2322 cck = (struct r88e_rx_cck *)physt; 2323 cck_agc_rpt = cck->agc_rpt; 2324 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2325 vga_idx = cck_agc_rpt & 0x1f; 2326 switch (lna_idx) { 2327 case 7: 2328 if (vga_idx <= 27) 2329 rssi = -100 + 2* (27 - vga_idx); 2330 else 2331 rssi = -100; 2332 break; 2333 case 6: 2334 rssi = -48 + 2 * (2 - vga_idx); 2335 break; 2336 case 5: 2337 rssi = -42 + 2 * (7 - vga_idx); 2338 break; 2339 case 4: 2340 rssi = -36 + 2 * (7 - vga_idx); 2341 break; 2342 case 3: 2343 rssi = -24 + 2 * (7 - vga_idx); 2344 break; 2345 case 2: 2346 rssi = -12 + 2 * (5 - vga_idx); 2347 break; 2348 case 1: 2349 rssi = 8 - (2 * vga_idx); 2350 break; 2351 case 0: 2352 rssi = 14 - (2 * vga_idx); 2353 break; 2354 } 2355 rssi += 6; 2356 } else { /* OFDM/HT. */ 2357 phy = (struct r92c_rx_phystat *)physt; 2358 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2359 } 2360 return rssi; 2361 } 2362 2363 static void 2364 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2365 { 2366 struct ieee80211com *ic = &sc->sc_ic; 2367 struct ifnet *ifp = ic->ic_ifp; 2368 struct ieee80211_frame *wh; 2369 struct ieee80211_node *ni; 2370 struct r92c_rx_desc_usb *stat; 2371 uint32_t rxdw0, rxdw3; 2372 struct mbuf *m; 2373 uint8_t rate; 2374 int8_t rssi = 0; 2375 int s, infosz; 2376 2377 URTWNHIST_FUNC(); 2378 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2379 2380 stat = (struct r92c_rx_desc_usb *)buf; 2381 rxdw0 = le32toh(stat->rxdw0); 2382 rxdw3 = le32toh(stat->rxdw3); 2383 2384 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2385 /* 2386 * This should not happen since we setup our Rx filter 2387 * to not receive these frames. 2388 */ 2389 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2390 if_statinc(ifp, if_ierrors); 2391 return; 2392 } 2393 /* 2394 * XXX: This will drop most control packets. Do we really 2395 * want this in IEEE80211_M_MONITOR mode? 2396 */ 2397 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2398 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2399 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2400 ic->ic_stats.is_rx_tooshort++; 2401 if_statinc(ifp, if_ierrors); 2402 return; 2403 } 2404 if (__predict_false(pktlen > MCLBYTES)) { 2405 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2406 if_statinc(ifp, if_ierrors); 2407 return; 2408 } 2409 2410 rate = MS(rxdw3, R92C_RXDW3_RATE); 2411 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2412 2413 /* Get RSSI from PHY status descriptor if present. */ 2414 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2415 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2416 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2417 else 2418 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2419 /* Update our average RSSI. */ 2420 urtwn_update_avgrssi(sc, rate, rssi); 2421 } 2422 2423 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2424 pktlen, rate, infosz, rssi); 2425 2426 MGETHDR(m, M_DONTWAIT, MT_DATA); 2427 if (__predict_false(m == NULL)) { 2428 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2429 ic->ic_stats.is_rx_nobuf++; 2430 if_statinc(ifp, if_ierrors); 2431 return; 2432 } 2433 if (pktlen > (int)MHLEN) { 2434 MCLGET(m, M_DONTWAIT); 2435 if (__predict_false(!(m->m_flags & M_EXT))) { 2436 aprint_error_dev(sc->sc_dev, 2437 "couldn't allocate rx mbuf cluster\n"); 2438 m_freem(m); 2439 ic->ic_stats.is_rx_nobuf++; 2440 if_statinc(ifp, if_ierrors); 2441 return; 2442 } 2443 } 2444 2445 /* Finalize mbuf. */ 2446 m_set_rcvif(m, ifp); 2447 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2448 memcpy(mtod(m, uint8_t *), wh, pktlen); 2449 m->m_pkthdr.len = m->m_len = pktlen; 2450 2451 s = splnet(); 2452 if (__predict_false(sc->sc_drvbpf != NULL)) { 2453 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2454 2455 tap->wr_flags = 0; 2456 if (!(rxdw3 & R92C_RXDW3_HT)) { 2457 switch (rate) { 2458 /* CCK. */ 2459 case 0: tap->wr_rate = 2; break; 2460 case 1: tap->wr_rate = 4; break; 2461 case 2: tap->wr_rate = 11; break; 2462 case 3: tap->wr_rate = 22; break; 2463 /* OFDM. */ 2464 case 4: tap->wr_rate = 12; break; 2465 case 5: tap->wr_rate = 18; break; 2466 case 6: tap->wr_rate = 24; break; 2467 case 7: tap->wr_rate = 36; break; 2468 case 8: tap->wr_rate = 48; break; 2469 case 9: tap->wr_rate = 72; break; 2470 case 10: tap->wr_rate = 96; break; 2471 case 11: tap->wr_rate = 108; break; 2472 } 2473 } else if (rate >= 12) { /* MCS0~15. */ 2474 /* Bit 7 set means HT MCS instead of rate. */ 2475 tap->wr_rate = 0x80 | (rate - 12); 2476 } 2477 tap->wr_dbm_antsignal = rssi; 2478 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2479 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2480 2481 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2482 } 2483 2484 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2485 2486 /* push the frame up to the 802.11 stack */ 2487 ieee80211_input(ic, m, ni, rssi, 0); 2488 2489 /* Node is no longer needed. */ 2490 ieee80211_free_node(ni); 2491 2492 splx(s); 2493 } 2494 2495 static void 2496 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2497 { 2498 struct urtwn_rx_data *data = priv; 2499 struct urtwn_softc *sc = data->sc; 2500 struct r92c_rx_desc_usb *stat; 2501 size_t pidx = data->pidx; 2502 uint32_t rxdw0; 2503 uint8_t *buf; 2504 int len, totlen, pktlen, infosz, npkts; 2505 2506 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2507 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2508 2509 mutex_enter(&sc->sc_rx_mtx); 2510 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2511 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2512 /* Put this Rx buffer back to our free list. */ 2513 mutex_exit(&sc->sc_rx_mtx); 2514 2515 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2516 if (status == USBD_STALLED) 2517 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2518 else if (status != USBD_CANCELLED) 2519 goto resubmit; 2520 return; 2521 } 2522 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2523 2524 if (__predict_false(len < (int)sizeof(*stat))) { 2525 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2526 goto resubmit; 2527 } 2528 buf = data->buf; 2529 2530 /* Get the number of encapsulated frames. */ 2531 stat = (struct r92c_rx_desc_usb *)buf; 2532 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2533 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2534 else 2535 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2536 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2537 2538 if (npkts != 0) 2539 rnd_add_uint32(&sc->rnd_source, npkts); 2540 2541 /* Process all of them. */ 2542 while (npkts-- > 0) { 2543 if (__predict_false(len < (int)sizeof(*stat))) { 2544 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2545 len, 0, 0, 0); 2546 break; 2547 } 2548 stat = (struct r92c_rx_desc_usb *)buf; 2549 rxdw0 = le32toh(stat->rxdw0); 2550 2551 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2552 if (__predict_false(pktlen == 0)) { 2553 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2554 break; 2555 } 2556 2557 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2558 2559 /* Make sure everything fits in xfer. */ 2560 totlen = sizeof(*stat) + infosz + pktlen; 2561 if (__predict_false(totlen > len)) { 2562 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2563 (int)sizeof(*stat), infosz, pktlen, len); 2564 break; 2565 } 2566 2567 /* Process 802.11 frame. */ 2568 urtwn_rx_frame(sc, buf, pktlen); 2569 2570 /* Next chunk is 128-byte aligned. */ 2571 totlen = roundup2(totlen, 128); 2572 buf += totlen; 2573 len -= totlen; 2574 } 2575 2576 resubmit: 2577 /* Setup a new transfer. */ 2578 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2579 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2580 (void)usbd_transfer(xfer); 2581 } 2582 2583 static void 2584 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2585 { 2586 struct urtwn_tx_data *data = priv; 2587 struct urtwn_softc *sc = data->sc; 2588 struct ifnet *ifp = &sc->sc_if; 2589 size_t pidx = data->pidx; 2590 int s; 2591 2592 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2593 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2594 2595 mutex_enter(&sc->sc_tx_mtx); 2596 /* Put this Tx buffer back to our free list. */ 2597 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2598 mutex_exit(&sc->sc_tx_mtx); 2599 2600 s = splnet(); 2601 sc->tx_timer = 0; 2602 ifp->if_flags &= ~IFF_OACTIVE; 2603 2604 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2605 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2606 if (status == USBD_STALLED) { 2607 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2608 usbd_clear_endpoint_stall_async(pipe); 2609 } 2610 printf("ERROR1\n"); 2611 if_statinc(ifp, if_oerrors); 2612 } 2613 splx(s); 2614 return; 2615 } 2616 2617 if_statinc(ifp, if_opackets); 2618 urtwn_start(ifp); 2619 splx(s); 2620 2621 } 2622 2623 static int 2624 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2625 struct urtwn_tx_data *data) 2626 { 2627 struct ieee80211com *ic = &sc->sc_ic; 2628 struct ieee80211_frame *wh; 2629 struct ieee80211_key *k = NULL; 2630 struct r92c_tx_desc_usb *txd; 2631 size_t i, padsize, xferlen, txd_len; 2632 uint16_t seq, sum; 2633 uint8_t raid, type, tid; 2634 int s, hasqos, error; 2635 2636 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2637 2638 wh = mtod(m, struct ieee80211_frame *); 2639 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2640 txd_len = sizeof(*txd); 2641 2642 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2643 txd_len = 32; 2644 2645 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2646 k = ieee80211_crypto_encap(ic, ni, m); 2647 if (k == NULL) 2648 return ENOBUFS; 2649 2650 /* packet header may have moved, reset our local pointer */ 2651 wh = mtod(m, struct ieee80211_frame *); 2652 } 2653 2654 if (__predict_false(sc->sc_drvbpf != NULL)) { 2655 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2656 2657 tap->wt_flags = 0; 2658 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2659 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2660 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2661 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2662 2663 /* XXX: set tap->wt_rate? */ 2664 2665 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2666 } 2667 2668 /* non-qos data frames */ 2669 tid = R92C_TXDW1_QSEL_BE; 2670 if ((hasqos = ieee80211_has_qos(wh))) { 2671 /* data frames in 11n mode */ 2672 struct ieee80211_qosframe *qwh = (void *)wh; 2673 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2674 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2675 tid = R92C_TXDW1_QSEL_MGNT; 2676 } 2677 2678 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2679 padsize = 8; 2680 else 2681 padsize = 0; 2682 2683 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2684 padsize = 0; 2685 2686 /* Fill Tx descriptor. */ 2687 txd = (struct r92c_tx_desc_usb *)data->buf; 2688 memset(txd, 0, txd_len + padsize); 2689 2690 txd->txdw0 |= htole32( 2691 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2692 SM(R92C_TXDW0_OFFSET, txd_len)); 2693 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2694 txd->txdw0 |= htole32( 2695 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2696 } 2697 2698 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2699 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2700 2701 /* fix pad field */ 2702 if (padsize > 0) { 2703 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2704 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2705 } 2706 2707 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2708 type == IEEE80211_FC0_TYPE_DATA) { 2709 if (ic->ic_curmode == IEEE80211_MODE_11B) 2710 raid = R92C_RAID_11B; 2711 else 2712 raid = R92C_RAID_11BG; 2713 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2714 tid, raid, 0, 0); 2715 2716 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2717 txd->txdw1 |= htole32( 2718 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2719 SM(R92C_TXDW1_QSEL, tid) | 2720 SM(R92C_TXDW1_RAID, raid) | 2721 R92C_TXDW1_AGGBK); 2722 } else 2723 txd->txdw1 |= htole32( 2724 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2725 SM(R92C_TXDW1_QSEL, tid) | 2726 SM(R92C_TXDW1_RAID, raid) | 2727 R92C_TXDW1_AGGBK); 2728 2729 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2730 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2731 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2732 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2733 2734 if (hasqos) { 2735 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2736 } 2737 2738 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2739 /* for 11g */ 2740 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2741 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2742 R92C_TXDW4_HWRTSEN); 2743 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2744 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2745 R92C_TXDW4_HWRTSEN); 2746 } 2747 } 2748 /* Send RTS at OFDM24. */ 2749 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2750 txd->txdw5 |= htole32(0x0001ff00); 2751 /* Send data at OFDM54. */ 2752 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2753 txd->txdw5 |= htole32(0x13 & 0x3f); 2754 else 2755 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2756 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2757 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2758 txd->txdw1 |= htole32( 2759 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2760 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2761 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2762 2763 /* Force CCK1. */ 2764 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2765 /* Use 1Mbps */ 2766 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2767 } else { 2768 /* broadcast or multicast packets */ 2769 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2770 txd->txdw1 |= htole32( 2771 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2772 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2773 2774 /* Force CCK1. */ 2775 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2776 /* Use 1Mbps */ 2777 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2778 } 2779 /* Set sequence number */ 2780 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2781 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2782 txd->txdseq |= htole16(seq); 2783 2784 if (!hasqos) { 2785 /* Use HW sequence numbering for non-QoS frames. */ 2786 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2787 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2788 } 2789 } else { 2790 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2791 R92E_HWSEQ_SHIFT); 2792 if (!hasqos) { 2793 /* Use HW sequence numbering for non-QoS frames. */ 2794 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2795 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2796 } 2797 } 2798 2799 /* Compute Tx descriptor checksum. */ 2800 sum = 0; 2801 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2802 sum ^= ((uint16_t *)txd)[i]; 2803 txd->txdsum = sum; /* NB: already little endian. */ 2804 2805 xferlen = txd_len + m->m_pkthdr.len + padsize; 2806 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2807 2808 s = splnet(); 2809 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2810 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2811 urtwn_txeof); 2812 error = usbd_transfer(data->xfer); 2813 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2814 error != USBD_IN_PROGRESS)) { 2815 splx(s); 2816 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2817 return error; 2818 } 2819 splx(s); 2820 return 0; 2821 } 2822 2823 struct urtwn_tx_data * 2824 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2825 { 2826 struct urtwn_tx_data *data = NULL; 2827 2828 mutex_enter(&sc->sc_tx_mtx); 2829 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2830 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2831 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2832 } 2833 mutex_exit(&sc->sc_tx_mtx); 2834 2835 return data; 2836 } 2837 2838 static void 2839 urtwn_start(struct ifnet *ifp) 2840 { 2841 struct urtwn_softc *sc = ifp->if_softc; 2842 struct ieee80211com *ic = &sc->sc_ic; 2843 struct urtwn_tx_data *data; 2844 struct ether_header *eh; 2845 struct ieee80211_node *ni; 2846 struct mbuf *m; 2847 2848 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2849 2850 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2851 return; 2852 2853 data = NULL; 2854 for (;;) { 2855 /* Send pending management frames first. */ 2856 IF_POLL(&ic->ic_mgtq, m); 2857 if (m != NULL) { 2858 /* Use AC_VO for management frames. */ 2859 2860 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2861 2862 if (data == NULL) { 2863 ifp->if_flags |= IFF_OACTIVE; 2864 DPRINTFN(DBG_TX, "empty tx_free_list", 2865 0, 0, 0, 0); 2866 return; 2867 } 2868 IF_DEQUEUE(&ic->ic_mgtq, m); 2869 ni = M_GETCTX(m, struct ieee80211_node *); 2870 M_CLEARCTX(m); 2871 goto sendit; 2872 } 2873 if (ic->ic_state != IEEE80211_S_RUN) 2874 break; 2875 2876 /* Encapsulate and send data frames. */ 2877 IFQ_POLL(&ifp->if_snd, m); 2878 if (m == NULL) 2879 break; 2880 2881 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2882 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2883 uint8_t qid = WME_AC_BE; 2884 if (ieee80211_has_qos(wh)) { 2885 /* data frames in 11n mode */ 2886 struct ieee80211_qosframe *qwh = (void *)wh; 2887 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2888 qid = TID_TO_WME_AC(tid); 2889 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2890 qid = WME_AC_VO; 2891 } 2892 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2893 2894 if (data == NULL) { 2895 ifp->if_flags |= IFF_OACTIVE; 2896 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2897 return; 2898 } 2899 IFQ_DEQUEUE(&ifp->if_snd, m); 2900 2901 if (m->m_len < (int)sizeof(*eh) && 2902 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2903 printf("ERROR6\n"); 2904 if_statinc(ifp, if_oerrors); 2905 continue; 2906 } 2907 eh = mtod(m, struct ether_header *); 2908 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2909 if (ni == NULL) { 2910 m_freem(m); 2911 printf("ERROR5\n"); 2912 if_statinc(ifp, if_oerrors); 2913 continue; 2914 } 2915 2916 bpf_mtap(ifp, m, BPF_D_OUT); 2917 2918 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2919 ieee80211_free_node(ni); 2920 printf("ERROR4\n"); 2921 if_statinc(ifp, if_oerrors); 2922 continue; 2923 } 2924 sendit: 2925 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2926 2927 if (urtwn_tx(sc, m, ni, data) != 0) { 2928 m_freem(m); 2929 ieee80211_free_node(ni); 2930 printf("ERROR3\n"); 2931 if_statinc(ifp, if_oerrors); 2932 continue; 2933 } 2934 m_freem(m); 2935 ieee80211_free_node(ni); 2936 sc->tx_timer = 5; 2937 ifp->if_timer = 1; 2938 } 2939 } 2940 2941 static void 2942 urtwn_watchdog(struct ifnet *ifp) 2943 { 2944 struct urtwn_softc *sc = ifp->if_softc; 2945 2946 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2947 2948 ifp->if_timer = 0; 2949 2950 if (sc->tx_timer > 0) { 2951 if (--sc->tx_timer == 0) { 2952 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2953 /* urtwn_init(ifp); XXX needs a process context! */ 2954 printf("ERROR2\n"); 2955 if_statinc(ifp, if_oerrors); 2956 return; 2957 } 2958 ifp->if_timer = 1; 2959 } 2960 ieee80211_watchdog(&sc->sc_ic); 2961 } 2962 2963 static int 2964 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2965 { 2966 struct urtwn_softc *sc = ifp->if_softc; 2967 struct ieee80211com *ic = &sc->sc_ic; 2968 int s, error = 0; 2969 2970 URTWNHIST_FUNC(); 2971 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2972 0, 0); 2973 2974 s = splnet(); 2975 2976 switch (cmd) { 2977 case SIOCSIFFLAGS: 2978 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2979 break; 2980 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2981 case IFF_UP | IFF_RUNNING: 2982 break; 2983 case IFF_UP: 2984 urtwn_init(ifp); 2985 break; 2986 case IFF_RUNNING: 2987 urtwn_stop(ifp, 1); 2988 break; 2989 case 0: 2990 break; 2991 } 2992 break; 2993 2994 case SIOCADDMULTI: 2995 case SIOCDELMULTI: 2996 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2997 /* setup multicast filter, etc */ 2998 error = 0; 2999 } 3000 break; 3001 3002 case SIOCS80211CHANNEL: 3003 /* 3004 * This allows for fast channel switching in monitor mode 3005 * (used by kismet). In IBSS mode, we must explicitly reset 3006 * the interface to generate a new beacon frame. 3007 */ 3008 error = ieee80211_ioctl(ic, cmd, data); 3009 if (error == ENETRESET && 3010 ic->ic_opmode == IEEE80211_M_MONITOR) { 3011 urtwn_set_chan(sc, ic->ic_curchan, 3012 IEEE80211_HTINFO_2NDCHAN_NONE); 3013 error = 0; 3014 } 3015 break; 3016 3017 default: 3018 error = ieee80211_ioctl(ic, cmd, data); 3019 break; 3020 } 3021 if (error == ENETRESET) { 3022 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3023 (IFF_UP | IFF_RUNNING) && 3024 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3025 urtwn_init(ifp); 3026 } 3027 error = 0; 3028 } 3029 3030 splx(s); 3031 3032 return error; 3033 } 3034 3035 static __inline int 3036 urtwn_power_on(struct urtwn_softc *sc) 3037 { 3038 3039 return sc->sc_power_on(sc); 3040 } 3041 3042 static int 3043 urtwn_r92c_power_on(struct urtwn_softc *sc) 3044 { 3045 uint32_t reg; 3046 int ntries; 3047 3048 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3049 3050 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3051 3052 /* Wait for autoload done bit. */ 3053 for (ntries = 0; ntries < 1000; ntries++) { 3054 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3055 break; 3056 DELAY(5); 3057 } 3058 if (ntries == 1000) { 3059 aprint_error_dev(sc->sc_dev, 3060 "timeout waiting for chip autoload\n"); 3061 return ETIMEDOUT; 3062 } 3063 3064 /* Unlock ISO/CLK/Power control register. */ 3065 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3066 /* Move SPS into PWM mode. */ 3067 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3068 DELAY(5); 3069 3070 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3071 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3072 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3073 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3074 DELAY(100); 3075 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3076 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3077 ~R92C_SYS_ISO_CTRL_MD2PP); 3078 } 3079 3080 /* Auto enable WLAN. */ 3081 urtwn_write_2(sc, R92C_APS_FSMCO, 3082 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3083 for (ntries = 0; ntries < 1000; ntries++) { 3084 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3085 R92C_APS_FSMCO_APFM_ONMAC)) 3086 break; 3087 DELAY(100); 3088 } 3089 if (ntries == 1000) { 3090 aprint_error_dev(sc->sc_dev, 3091 "timeout waiting for MAC auto ON\n"); 3092 return ETIMEDOUT; 3093 } 3094 3095 /* Enable radio, GPIO and LED functions. */ 3096 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3097 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3098 urtwn_write_2(sc, R92C_APS_FSMCO, 3099 R92C_APS_FSMCO_AFSM_HSUS | 3100 R92C_APS_FSMCO_PDN_EN | 3101 R92C_APS_FSMCO_PFM_ALDN); 3102 3103 /* Release RF digital isolation. */ 3104 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3105 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3106 3107 /* Initialize MAC. */ 3108 urtwn_write_1(sc, R92C_APSD_CTRL, 3109 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3110 for (ntries = 0; ntries < 200; ntries++) { 3111 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3112 R92C_APSD_CTRL_OFF_STATUS)) 3113 break; 3114 DELAY(5); 3115 } 3116 if (ntries == 200) { 3117 aprint_error_dev(sc->sc_dev, 3118 "timeout waiting for MAC initialization\n"); 3119 return ETIMEDOUT; 3120 } 3121 3122 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3123 reg = urtwn_read_2(sc, R92C_CR); 3124 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3125 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3126 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3127 R92C_CR_ENSEC; 3128 urtwn_write_2(sc, R92C_CR, reg); 3129 3130 urtwn_write_1(sc, 0xfe10, 0x19); 3131 return 0; 3132 } 3133 3134 static int 3135 urtwn_r92e_power_on(struct urtwn_softc *sc) 3136 { 3137 uint32_t reg; 3138 uint32_t val; 3139 int ntries; 3140 3141 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3142 3143 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3144 3145 /* Enable radio, GPIO and LED functions. */ 3146 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3147 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3148 urtwn_write_2(sc, R92C_APS_FSMCO, 3149 R92C_APS_FSMCO_AFSM_HSUS | 3150 R92C_APS_FSMCO_PDN_EN | 3151 R92C_APS_FSMCO_PFM_ALDN); 3152 3153 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3154 /* LDO. */ 3155 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3156 } 3157 else { 3158 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3159 R92C_SYS_SWR_CTRL2) & 0xffff); 3160 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3161 } 3162 3163 for (ntries = 0; ntries < 2; ntries++) { 3164 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3165 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3166 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3167 R92C_AFE_CTRL4)); 3168 } 3169 3170 /* Reset BB. */ 3171 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3172 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3173 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3174 3175 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3176 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3177 3178 /* Disable HWPDN. */ 3179 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3180 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3181 3182 /* Disable WL suspend. */ 3183 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3184 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3185 R92C_APS_FSMCO_AFSM_HSUS)); 3186 3187 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3188 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3189 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3190 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3191 for (ntries = 0; ntries < 10000; ntries++) { 3192 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3193 R92C_APS_FSMCO_APFM_ONMAC; 3194 if (val == 0x0) 3195 break; 3196 DELAY(10); 3197 } 3198 if (ntries == 10000) { 3199 aprint_error_dev(sc->sc_dev, 3200 "timeout waiting for chip power up\n"); 3201 return ETIMEDOUT; 3202 } 3203 3204 urtwn_write_2(sc, R92C_CR, 0x00); 3205 reg = urtwn_read_2(sc, R92C_CR); 3206 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3207 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3208 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3209 urtwn_write_2(sc, R92C_CR, reg); 3210 3211 return 0; 3212 } 3213 3214 static int 3215 urtwn_r88e_power_on(struct urtwn_softc *sc) 3216 { 3217 uint32_t reg; 3218 uint8_t val; 3219 int ntries; 3220 3221 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3222 3223 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3224 3225 /* Wait for power ready bit. */ 3226 for (ntries = 0; ntries < 5000; ntries++) { 3227 val = urtwn_read_1(sc, 0x6) & 0x2; 3228 if (val == 0x2) 3229 break; 3230 DELAY(10); 3231 } 3232 if (ntries == 5000) { 3233 aprint_error_dev(sc->sc_dev, 3234 "timeout waiting for chip power up\n"); 3235 return ETIMEDOUT; 3236 } 3237 3238 /* Reset BB. */ 3239 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3240 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3241 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3242 3243 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3244 3245 /* Disable HWPDN. */ 3246 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3247 3248 /* Disable WL suspend. */ 3249 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3250 3251 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3252 for (ntries = 0; ntries < 5000; ntries++) { 3253 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3254 break; 3255 DELAY(10); 3256 } 3257 if (ntries == 5000) 3258 return ETIMEDOUT; 3259 3260 /* Enable LDO normal mode. */ 3261 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3262 3263 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3264 urtwn_write_2(sc, R92C_CR, 0); 3265 reg = urtwn_read_2(sc, R92C_CR); 3266 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3267 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3268 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3269 urtwn_write_2(sc, R92C_CR, reg); 3270 3271 return 0; 3272 } 3273 3274 static int __noinline 3275 urtwn_llt_init(struct urtwn_softc *sc) 3276 { 3277 size_t i, page_count, pktbuf_count; 3278 uint32_t val; 3279 int error; 3280 3281 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3282 3283 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3284 3285 if (sc->chip & URTWN_CHIP_88E) 3286 page_count = R88E_TX_PAGE_COUNT; 3287 else if (sc->chip & URTWN_CHIP_92EU) 3288 page_count = R92E_TX_PAGE_COUNT; 3289 else 3290 page_count = R92C_TX_PAGE_COUNT; 3291 if (sc->chip & URTWN_CHIP_88E) 3292 pktbuf_count = R88E_TXPKTBUF_COUNT; 3293 else if (sc->chip & URTWN_CHIP_92EU) 3294 pktbuf_count = R88E_TXPKTBUF_COUNT; 3295 else 3296 pktbuf_count = R92C_TXPKTBUF_COUNT; 3297 3298 if (sc->chip & URTWN_CHIP_92EU) { 3299 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3300 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3301 DELAY(100); 3302 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3303 if (val & R92E_AUTO_LLT_EN) 3304 return EIO; 3305 return 0; 3306 } 3307 3308 /* Reserve pages [0; page_count]. */ 3309 for (i = 0; i < page_count; i++) { 3310 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3311 return error; 3312 } 3313 /* NB: 0xff indicates end-of-list. */ 3314 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3315 return error; 3316 /* 3317 * Use pages [page_count + 1; pktbuf_count - 1] 3318 * as ring buffer. 3319 */ 3320 for (++i; i < pktbuf_count - 1; i++) { 3321 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3322 return error; 3323 } 3324 /* Make the last page point to the beginning of the ring buffer. */ 3325 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3326 return error; 3327 } 3328 3329 static void 3330 urtwn_fw_reset(struct urtwn_softc *sc) 3331 { 3332 uint16_t reg; 3333 int ntries; 3334 3335 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3336 3337 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3338 3339 /* Tell 8051 to reset itself. */ 3340 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3341 3342 /* Wait until 8051 resets by itself. */ 3343 for (ntries = 0; ntries < 100; ntries++) { 3344 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3345 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3346 return; 3347 DELAY(50); 3348 } 3349 /* Force 8051 reset. */ 3350 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3351 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3352 } 3353 3354 static void 3355 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3356 { 3357 uint16_t reg; 3358 3359 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3360 3361 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3362 3363 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3364 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3365 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3366 } 3367 DELAY(50); 3368 3369 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3370 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3371 DELAY(50); 3372 3373 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3374 DELAY(50); 3375 3376 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3377 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3378 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3379 } 3380 DELAY(50); 3381 3382 } 3383 3384 static int 3385 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3386 { 3387 uint32_t reg; 3388 int off, mlen, error = 0; 3389 3390 URTWNHIST_FUNC(); 3391 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3392 page, (uintptr_t)buf, len, 0); 3393 3394 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3395 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3396 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3397 3398 off = R92C_FW_START_ADDR; 3399 while (len > 0) { 3400 if (len > 196) 3401 mlen = 196; 3402 else if (len > 4) 3403 mlen = 4; 3404 else 3405 mlen = 1; 3406 error = urtwn_write_region(sc, off, buf, mlen); 3407 if (error != 0) 3408 break; 3409 off += mlen; 3410 buf += mlen; 3411 len -= mlen; 3412 } 3413 return error; 3414 } 3415 3416 static int __noinline 3417 urtwn_load_firmware(struct urtwn_softc *sc) 3418 { 3419 firmware_handle_t fwh; 3420 const struct r92c_fw_hdr *hdr; 3421 const char *name; 3422 u_char *fw, *ptr; 3423 size_t len; 3424 uint32_t reg; 3425 int mlen, ntries, page, error; 3426 3427 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3428 3429 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3430 3431 /* Read firmware image from the filesystem. */ 3432 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3433 name = "rtl8188eufw.bin"; 3434 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3435 name = "rtl8192eefw.bin"; 3436 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3437 URTWN_CHIP_UMC_A_CUT) 3438 name = "rtl8192cfwU.bin"; 3439 else 3440 name = "rtl8192cfw.bin"; 3441 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3442 aprint_error_dev(sc->sc_dev, 3443 "failed load firmware of file %s (error %d)\n", name, 3444 error); 3445 return error; 3446 } 3447 const size_t fwlen = len = firmware_get_size(fwh); 3448 fw = firmware_malloc(len); 3449 if (fw == NULL) { 3450 aprint_error_dev(sc->sc_dev, 3451 "failed to allocate firmware memory\n"); 3452 firmware_close(fwh); 3453 return ENOMEM; 3454 } 3455 error = firmware_read(fwh, 0, fw, len); 3456 firmware_close(fwh); 3457 if (error != 0) { 3458 aprint_error_dev(sc->sc_dev, 3459 "failed to read firmware (error %d)\n", error); 3460 firmware_free(fw, fwlen); 3461 return error; 3462 } 3463 3464 len = fwlen; 3465 ptr = fw; 3466 hdr = (const struct r92c_fw_hdr *)ptr; 3467 /* Check if there is a valid FW header and skip it. */ 3468 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3469 (le16toh(hdr->signature) >> 4) == 0x88e || 3470 (le16toh(hdr->signature) >> 4) == 0x92e || 3471 (le16toh(hdr->signature) >> 4) == 0x92c) { 3472 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3473 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3474 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3475 hdr->month, hdr->date, hdr->hour, hdr->minute); 3476 ptr += sizeof(*hdr); 3477 len -= sizeof(*hdr); 3478 } 3479 3480 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3481 /* Reset MCU ready status */ 3482 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3483 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3484 ISSET(sc->chip, URTWN_CHIP_92EU)) 3485 urtwn_r88e_fw_reset(sc); 3486 else 3487 urtwn_fw_reset(sc); 3488 } 3489 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3490 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3491 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3492 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3493 R92C_SYS_FUNC_EN_CPUEN); 3494 } 3495 3496 /* download enabled */ 3497 urtwn_write_1(sc, R92C_MCUFWDL, 3498 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3499 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3500 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3501 3502 /* Reset the FWDL checksum. */ 3503 urtwn_write_1(sc, R92C_MCUFWDL, 3504 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3505 3506 DELAY(50); 3507 /* download firmware */ 3508 for (page = 0; len > 0; page++) { 3509 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3510 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3511 if (error != 0) { 3512 aprint_error_dev(sc->sc_dev, 3513 "could not load firmware page %d\n", page); 3514 goto fail; 3515 } 3516 ptr += mlen; 3517 len -= mlen; 3518 } 3519 3520 /* download disable */ 3521 urtwn_write_1(sc, R92C_MCUFWDL, 3522 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3523 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3524 3525 /* Wait for checksum report. */ 3526 for (ntries = 0; ntries < 1000; ntries++) { 3527 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3528 break; 3529 DELAY(5); 3530 } 3531 if (ntries == 1000) { 3532 aprint_error_dev(sc->sc_dev, 3533 "timeout waiting for checksum report\n"); 3534 error = ETIMEDOUT; 3535 goto fail; 3536 } 3537 3538 /* Wait for firmware readiness. */ 3539 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3540 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3541 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3542 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3543 ISSET(sc->chip, URTWN_CHIP_92EU)) 3544 urtwn_r88e_fw_reset(sc); 3545 for (ntries = 0; ntries < 6000; ntries++) { 3546 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3547 break; 3548 DELAY(5); 3549 } 3550 if (ntries == 6000) { 3551 aprint_error_dev(sc->sc_dev, 3552 "timeout waiting for firmware readiness\n"); 3553 error = ETIMEDOUT; 3554 goto fail; 3555 } 3556 fail: 3557 firmware_free(fw, fwlen); 3558 return error; 3559 } 3560 3561 static __inline int 3562 urtwn_dma_init(struct urtwn_softc *sc) 3563 { 3564 3565 return sc->sc_dma_init(sc); 3566 } 3567 3568 static int 3569 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3570 { 3571 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3572 uint32_t reg; 3573 int error; 3574 3575 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3576 3577 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3578 3579 /* Initialize LLT table. */ 3580 error = urtwn_llt_init(sc); 3581 if (error != 0) 3582 return error; 3583 3584 /* Get Tx queues to USB endpoints mapping. */ 3585 hashq = hasnq = haslq = 0; 3586 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3587 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3588 if (MS(reg, R92C_USB_EP_HQ) != 0) 3589 hashq = 1; 3590 if (MS(reg, R92C_USB_EP_NQ) != 0) 3591 hasnq = 1; 3592 if (MS(reg, R92C_USB_EP_LQ) != 0) 3593 haslq = 1; 3594 nqueues = hashq + hasnq + haslq; 3595 if (nqueues == 0) 3596 return EIO; 3597 /* Get the number of pages for each queue. */ 3598 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3599 /* The remaining pages are assigned to the high priority queue. */ 3600 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3601 3602 /* Set number of pages for normal priority queue. */ 3603 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3604 urtwn_write_4(sc, R92C_RQPN, 3605 /* Set number of pages for public queue. */ 3606 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3607 /* Set number of pages for high priority queue. */ 3608 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3609 /* Set number of pages for low priority queue. */ 3610 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3611 /* Load values. */ 3612 R92C_RQPN_LD); 3613 3614 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3615 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3616 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3617 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3618 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3619 3620 /* Set queue to USB pipe mapping. */ 3621 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3622 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3623 if (nqueues == 1) { 3624 if (hashq) { 3625 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3626 } else if (hasnq) { 3627 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3628 } else { 3629 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3630 } 3631 } else if (nqueues == 2) { 3632 /* All 2-endpoints configs have a high priority queue. */ 3633 if (!hashq) { 3634 return EIO; 3635 } 3636 if (hasnq) { 3637 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3638 } else { 3639 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3640 } 3641 } else { 3642 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3643 } 3644 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3645 3646 /* Set Tx/Rx transfer page boundary. */ 3647 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3648 3649 /* Set Tx/Rx transfer page size. */ 3650 urtwn_write_1(sc, R92C_PBP, 3651 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3652 return 0; 3653 } 3654 3655 static int 3656 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3657 { 3658 usb_interface_descriptor_t *id; 3659 uint32_t reg; 3660 int nqueues; 3661 int error; 3662 3663 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3664 3665 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3666 3667 /* Initialize LLT table. */ 3668 error = urtwn_llt_init(sc); 3669 if (error != 0) 3670 return error; 3671 3672 /* Get Tx queues to USB endpoints mapping. */ 3673 id = usbd_get_interface_descriptor(sc->sc_iface); 3674 nqueues = id->bNumEndpoints - 1; 3675 if (nqueues == 0) 3676 return EIO; 3677 3678 /* Set number of pages for normal priority queue. */ 3679 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3680 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3681 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3682 3683 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3684 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3685 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3686 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3687 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3688 3689 /* Set queue to USB pipe mapping. */ 3690 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3691 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3692 if (nqueues == 1) 3693 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3694 else if (nqueues == 2) 3695 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3696 else 3697 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3698 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3699 3700 /* Set Tx/Rx transfer page boundary. */ 3701 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3702 3703 /* Set Tx/Rx transfer page size. */ 3704 urtwn_write_1(sc, R92C_PBP, 3705 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3706 3707 return 0; 3708 } 3709 3710 static void __noinline 3711 urtwn_mac_init(struct urtwn_softc *sc) 3712 { 3713 size_t i; 3714 3715 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3716 3717 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3718 3719 /* Write MAC initialization values. */ 3720 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3721 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3722 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3723 rtl8188eu_mac[i].val); 3724 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3725 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3726 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3727 rtl8192eu_mac[i].val); 3728 } else { 3729 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3730 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3731 rtl8192cu_mac[i].val); 3732 } 3733 } 3734 3735 static void __noinline 3736 urtwn_bb_init(struct urtwn_softc *sc) 3737 { 3738 const struct rtwn_bb_prog *prog; 3739 uint32_t reg; 3740 uint8_t crystalcap; 3741 size_t i; 3742 3743 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3744 3745 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3746 3747 /* Enable BB and RF. */ 3748 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3749 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3750 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3751 R92C_SYS_FUNC_EN_DIO_RF); 3752 3753 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3754 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3755 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3756 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3757 } 3758 3759 urtwn_write_1(sc, R92C_RF_CTRL, 3760 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3761 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3762 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3763 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3764 3765 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3766 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3767 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3768 urtwn_write_1(sc, 0x15, 0xe9); 3769 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3770 } 3771 3772 /* Select BB programming based on board type. */ 3773 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3774 prog = &rtl8188eu_bb_prog; 3775 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3776 prog = &rtl8192eu_bb_prog; 3777 else if (!(sc->chip & URTWN_CHIP_92C)) { 3778 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3779 prog = &rtl8188ce_bb_prog; 3780 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3781 prog = &rtl8188ru_bb_prog; 3782 } else { 3783 prog = &rtl8188cu_bb_prog; 3784 } 3785 } else { 3786 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3787 prog = &rtl8192ce_bb_prog; 3788 } else { 3789 prog = &rtl8192cu_bb_prog; 3790 } 3791 } 3792 /* Write BB initialization values. */ 3793 for (i = 0; i < prog->count; i++) { 3794 /* additional delay depend on registers */ 3795 switch (prog->regs[i]) { 3796 case 0xfe: 3797 urtwn_delay_ms(sc, 50); 3798 break; 3799 case 0xfd: 3800 urtwn_delay_ms(sc, 5); 3801 break; 3802 case 0xfc: 3803 urtwn_delay_ms(sc, 1); 3804 break; 3805 case 0xfb: 3806 DELAY(50); 3807 break; 3808 case 0xfa: 3809 DELAY(5); 3810 break; 3811 case 0xf9: 3812 DELAY(1); 3813 break; 3814 } 3815 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3816 DELAY(1); 3817 } 3818 3819 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3820 /* 8192C 1T only configuration. */ 3821 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3822 reg = (reg & ~0x00000003) | 0x2; 3823 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3824 3825 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3826 reg = (reg & ~0x00300033) | 0x00200022; 3827 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3828 3829 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3830 reg = (reg & ~0xff000000) | (0x45 << 24); 3831 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3832 3833 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3834 reg = (reg & ~0x000000ff) | 0x23; 3835 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3836 3837 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3838 reg = (reg & ~0x00000030) | (1 << 4); 3839 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3840 3841 reg = urtwn_bb_read(sc, 0xe74); 3842 reg = (reg & ~0x0c000000) | (2 << 26); 3843 urtwn_bb_write(sc, 0xe74, reg); 3844 reg = urtwn_bb_read(sc, 0xe78); 3845 reg = (reg & ~0x0c000000) | (2 << 26); 3846 urtwn_bb_write(sc, 0xe78, reg); 3847 reg = urtwn_bb_read(sc, 0xe7c); 3848 reg = (reg & ~0x0c000000) | (2 << 26); 3849 urtwn_bb_write(sc, 0xe7c, reg); 3850 reg = urtwn_bb_read(sc, 0xe80); 3851 reg = (reg & ~0x0c000000) | (2 << 26); 3852 urtwn_bb_write(sc, 0xe80, reg); 3853 reg = urtwn_bb_read(sc, 0xe88); 3854 reg = (reg & ~0x0c000000) | (2 << 26); 3855 urtwn_bb_write(sc, 0xe88, reg); 3856 } 3857 3858 /* Write AGC values. */ 3859 for (i = 0; i < prog->agccount; i++) { 3860 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3861 DELAY(1); 3862 } 3863 3864 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3865 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3866 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3867 DELAY(1); 3868 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3869 DELAY(1); 3870 } 3871 3872 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3873 crystalcap = sc->r88e_rom[0xb9]; 3874 if (crystalcap == 0x00) 3875 crystalcap = 0x20; 3876 crystalcap &= 0x3f; 3877 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3878 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3879 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3880 crystalcap | crystalcap << 6)); 3881 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3882 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3883 crystalcap = sc->r88e_rom[0xb9]; 3884 if (crystalcap == 0xff) 3885 crystalcap = 0x20; 3886 crystalcap &= 0x3f; 3887 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3888 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3889 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3890 crystalcap | crystalcap << 6)); 3891 } else { 3892 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3893 R92C_HSSI_PARAM2_CCK_HIPWR) { 3894 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3895 } 3896 } 3897 } 3898 3899 static void __noinline 3900 urtwn_rf_init(struct urtwn_softc *sc) 3901 { 3902 const struct rtwn_rf_prog *prog; 3903 uint32_t reg, mask, saved; 3904 size_t i, j, idx; 3905 3906 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3907 3908 /* Select RF programming based on board type. */ 3909 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3910 prog = rtl8188eu_rf_prog; 3911 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3912 prog = rtl8192eu_rf_prog; 3913 else if (!(sc->chip & URTWN_CHIP_92C)) { 3914 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3915 prog = rtl8188ce_rf_prog; 3916 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3917 prog = rtl8188ru_rf_prog; 3918 } else { 3919 prog = rtl8188cu_rf_prog; 3920 } 3921 } else { 3922 prog = rtl8192ce_rf_prog; 3923 } 3924 3925 for (i = 0; i < sc->nrxchains; i++) { 3926 /* Save RF_ENV control type. */ 3927 idx = i / 2; 3928 mask = 0xffffU << ((i % 2) * 16); 3929 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3930 3931 /* Set RF_ENV enable. */ 3932 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3933 reg |= 0x100000; 3934 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3935 DELAY(50); 3936 3937 /* Set RF_ENV output high. */ 3938 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3939 reg |= 0x10; 3940 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3941 DELAY(50); 3942 3943 /* Set address and data lengths of RF registers. */ 3944 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3945 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3946 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3947 DELAY(50); 3948 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3949 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3950 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3951 DELAY(50); 3952 3953 /* Write RF initialization values for this chain. */ 3954 for (j = 0; j < prog[i].count; j++) { 3955 if (prog[i].regs[j] >= 0xf9 && 3956 prog[i].regs[j] <= 0xfe) { 3957 /* 3958 * These are fake RF registers offsets that 3959 * indicate a delay is required. 3960 */ 3961 urtwn_delay_ms(sc, 50); 3962 continue; 3963 } 3964 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3965 DELAY(5); 3966 } 3967 3968 /* Restore RF_ENV control type. */ 3969 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3970 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3971 } 3972 3973 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3974 URTWN_CHIP_UMC_A_CUT) { 3975 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3976 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3977 } 3978 3979 /* Cache RF register CHNLBW. */ 3980 for (i = 0; i < 2; i++) { 3981 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3982 } 3983 } 3984 3985 static void __noinline 3986 urtwn_cam_init(struct urtwn_softc *sc) 3987 { 3988 uint32_t content, command; 3989 uint8_t idx; 3990 size_t i; 3991 3992 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3993 3994 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3995 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3996 return; 3997 3998 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3999 content = (idx & 3) 4000 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4001 | R92C_CAM_VALID; 4002 4003 command = R92C_CAMCMD_POLLING 4004 | R92C_CAMCMD_WRITE 4005 | R92C_CAM_CTL0(idx); 4006 4007 urtwn_write_4(sc, R92C_CAMWRITE, content); 4008 urtwn_write_4(sc, R92C_CAMCMD, command); 4009 } 4010 4011 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4012 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4013 if (i == 0) { 4014 content = (idx & 3) 4015 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4016 | R92C_CAM_VALID; 4017 } else { 4018 content = 0; 4019 } 4020 4021 command = R92C_CAMCMD_POLLING 4022 | R92C_CAMCMD_WRITE 4023 | R92C_CAM_CTL0(idx) 4024 | i; 4025 4026 urtwn_write_4(sc, R92C_CAMWRITE, content); 4027 urtwn_write_4(sc, R92C_CAMCMD, command); 4028 } 4029 } 4030 4031 /* Invalidate all CAM entries. */ 4032 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4033 } 4034 4035 static void __noinline 4036 urtwn_pa_bias_init(struct urtwn_softc *sc) 4037 { 4038 uint8_t reg; 4039 size_t i; 4040 4041 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4042 4043 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4044 4045 for (i = 0; i < sc->nrxchains; i++) { 4046 if (sc->pa_setting & (1U << i)) 4047 continue; 4048 4049 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4050 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4051 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4052 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4053 } 4054 if (!(sc->pa_setting & 0x10)) { 4055 reg = urtwn_read_1(sc, 0x16); 4056 reg = (reg & ~0xf0) | 0x90; 4057 urtwn_write_1(sc, 0x16, reg); 4058 } 4059 } 4060 4061 static void __noinline 4062 urtwn_rxfilter_init(struct urtwn_softc *sc) 4063 { 4064 4065 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4066 4067 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4068 4069 /* Initialize Rx filter. */ 4070 /* TODO: use better filter for monitor mode. */ 4071 urtwn_write_4(sc, R92C_RCR, 4072 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4073 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4074 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4075 /* Accept all multicast frames. */ 4076 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4077 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4078 /* Accept all management frames. */ 4079 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4080 /* Reject all control frames. */ 4081 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4082 /* Accept all data frames. */ 4083 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4084 } 4085 4086 static void __noinline 4087 urtwn_edca_init(struct urtwn_softc *sc) 4088 { 4089 4090 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4091 4092 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4093 4094 /* set spec SIFS (used in NAV) */ 4095 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4096 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4097 4098 /* set SIFS CCK/OFDM */ 4099 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4100 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4101 4102 /* TXOP */ 4103 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4104 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4105 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4106 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4107 } 4108 4109 static void 4110 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4111 uint16_t power[URTWN_RIDX_COUNT]) 4112 { 4113 uint32_t reg; 4114 4115 URTWNHIST_FUNC(); 4116 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4117 4118 /* Write per-CCK rate Tx power. */ 4119 if (chain == 0) { 4120 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4121 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4122 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4123 4124 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4125 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4126 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4127 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4128 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4129 } else { 4130 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4131 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4132 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4133 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4134 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4135 4136 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4137 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4138 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4139 } 4140 /* Write per-OFDM rate Tx power. */ 4141 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4142 SM(R92C_TXAGC_RATE06, power[ 4]) | 4143 SM(R92C_TXAGC_RATE09, power[ 5]) | 4144 SM(R92C_TXAGC_RATE12, power[ 6]) | 4145 SM(R92C_TXAGC_RATE18, power[ 7])); 4146 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4147 SM(R92C_TXAGC_RATE24, power[ 8]) | 4148 SM(R92C_TXAGC_RATE36, power[ 9]) | 4149 SM(R92C_TXAGC_RATE48, power[10]) | 4150 SM(R92C_TXAGC_RATE54, power[11])); 4151 /* Write per-MCS Tx power. */ 4152 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4153 SM(R92C_TXAGC_MCS00, power[12]) | 4154 SM(R92C_TXAGC_MCS01, power[13]) | 4155 SM(R92C_TXAGC_MCS02, power[14]) | 4156 SM(R92C_TXAGC_MCS03, power[15])); 4157 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4158 SM(R92C_TXAGC_MCS04, power[16]) | 4159 SM(R92C_TXAGC_MCS05, power[17]) | 4160 SM(R92C_TXAGC_MCS06, power[18]) | 4161 SM(R92C_TXAGC_MCS07, power[19])); 4162 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4163 SM(R92C_TXAGC_MCS08, power[20]) | 4164 SM(R92C_TXAGC_MCS09, power[21]) | 4165 SM(R92C_TXAGC_MCS10, power[22]) | 4166 SM(R92C_TXAGC_MCS11, power[23])); 4167 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4168 SM(R92C_TXAGC_MCS12, power[24]) | 4169 SM(R92C_TXAGC_MCS13, power[25]) | 4170 SM(R92C_TXAGC_MCS14, power[26]) | 4171 SM(R92C_TXAGC_MCS15, power[27])); 4172 } 4173 4174 static void 4175 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4176 uint16_t power[URTWN_RIDX_COUNT]) 4177 { 4178 struct r92c_rom *rom = &sc->rom; 4179 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4180 const struct rtwn_txpwr *base; 4181 int ridx, group; 4182 4183 URTWNHIST_FUNC(); 4184 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4185 4186 /* Determine channel group. */ 4187 if (chan <= 3) { 4188 group = 0; 4189 } else if (chan <= 9) { 4190 group = 1; 4191 } else { 4192 group = 2; 4193 } 4194 4195 /* Get original Tx power based on board type and RF chain. */ 4196 if (!(sc->chip & URTWN_CHIP_92C)) { 4197 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4198 base = &rtl8188ru_txagc[chain]; 4199 } else { 4200 base = &rtl8192cu_txagc[chain]; 4201 } 4202 } else { 4203 base = &rtl8192cu_txagc[chain]; 4204 } 4205 4206 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4207 if (sc->regulatory == 0) { 4208 for (ridx = 0; ridx <= 3; ridx++) { 4209 power[ridx] = base->pwr[0][ridx]; 4210 } 4211 } 4212 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4213 if (sc->regulatory == 3) { 4214 power[ridx] = base->pwr[0][ridx]; 4215 /* Apply vendor limits. */ 4216 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4217 maxpow = rom->ht40_max_pwr[group]; 4218 } else { 4219 maxpow = rom->ht20_max_pwr[group]; 4220 } 4221 maxpow = (maxpow >> (chain * 4)) & 0xf; 4222 if (power[ridx] > maxpow) { 4223 power[ridx] = maxpow; 4224 } 4225 } else if (sc->regulatory == 1) { 4226 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4227 power[ridx] = base->pwr[group][ridx]; 4228 } 4229 } else if (sc->regulatory != 2) { 4230 power[ridx] = base->pwr[0][ridx]; 4231 } 4232 } 4233 4234 /* Compute per-CCK rate Tx power. */ 4235 cckpow = rom->cck_tx_pwr[chain][group]; 4236 for (ridx = 0; ridx <= 3; ridx++) { 4237 power[ridx] += cckpow; 4238 if (power[ridx] > R92C_MAX_TX_PWR) { 4239 power[ridx] = R92C_MAX_TX_PWR; 4240 } 4241 } 4242 4243 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4244 if (sc->ntxchains > 1) { 4245 /* Apply reduction for 2 spatial streams. */ 4246 diff = rom->ht40_2s_tx_pwr_diff[group]; 4247 diff = (diff >> (chain * 4)) & 0xf; 4248 htpow = (htpow > diff) ? htpow - diff : 0; 4249 } 4250 4251 /* Compute per-OFDM rate Tx power. */ 4252 diff = rom->ofdm_tx_pwr_diff[group]; 4253 diff = (diff >> (chain * 4)) & 0xf; 4254 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4255 for (ridx = 4; ridx <= 11; ridx++) { 4256 power[ridx] += ofdmpow; 4257 if (power[ridx] > R92C_MAX_TX_PWR) { 4258 power[ridx] = R92C_MAX_TX_PWR; 4259 } 4260 } 4261 4262 /* Compute per-MCS Tx power. */ 4263 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4264 diff = rom->ht20_tx_pwr_diff[group]; 4265 diff = (diff >> (chain * 4)) & 0xf; 4266 htpow += diff; /* HT40->HT20 correction. */ 4267 } 4268 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4269 power[ridx] += htpow; 4270 if (power[ridx] > R92C_MAX_TX_PWR) { 4271 power[ridx] = R92C_MAX_TX_PWR; 4272 } 4273 } 4274 #ifdef URTWN_DEBUG 4275 if (urtwn_debug & DBG_RF) { 4276 /* Dump per-rate Tx power values. */ 4277 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4278 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4279 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4280 } 4281 #endif 4282 } 4283 4284 void 4285 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4286 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4287 { 4288 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4289 const struct rtwn_r88e_txpwr *base; 4290 int ridx, group; 4291 4292 URTWNHIST_FUNC(); 4293 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4294 4295 /* Determine channel group. */ 4296 if (chan <= 2) 4297 group = 0; 4298 else if (chan <= 5) 4299 group = 1; 4300 else if (chan <= 8) 4301 group = 2; 4302 else if (chan <= 11) 4303 group = 3; 4304 else if (chan <= 13) 4305 group = 4; 4306 else 4307 group = 5; 4308 4309 /* Get original Tx power based on board type and RF chain. */ 4310 base = &rtl8188eu_txagc[chain]; 4311 4312 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4313 if (sc->regulatory == 0) { 4314 for (ridx = 0; ridx <= 3; ridx++) 4315 power[ridx] = base->pwr[0][ridx]; 4316 } 4317 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4318 if (sc->regulatory == 3) 4319 power[ridx] = base->pwr[0][ridx]; 4320 else if (sc->regulatory == 1) { 4321 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4322 power[ridx] = base->pwr[group][ridx]; 4323 } else if (sc->regulatory != 2) 4324 power[ridx] = base->pwr[0][ridx]; 4325 } 4326 4327 /* Compute per-CCK rate Tx power. */ 4328 cckpow = sc->cck_tx_pwr[group]; 4329 for (ridx = 0; ridx <= 3; ridx++) { 4330 power[ridx] += cckpow; 4331 if (power[ridx] > R92C_MAX_TX_PWR) 4332 power[ridx] = R92C_MAX_TX_PWR; 4333 } 4334 4335 htpow = sc->ht40_tx_pwr[group]; 4336 4337 /* Compute per-OFDM rate Tx power. */ 4338 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4339 for (ridx = 4; ridx <= 11; ridx++) { 4340 power[ridx] += ofdmpow; 4341 if (power[ridx] > R92C_MAX_TX_PWR) 4342 power[ridx] = R92C_MAX_TX_PWR; 4343 } 4344 4345 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4346 for (ridx = 12; ridx <= 27; ridx++) { 4347 power[ridx] += bw20pow; 4348 if (power[ridx] > R92C_MAX_TX_PWR) 4349 power[ridx] = R92C_MAX_TX_PWR; 4350 } 4351 } 4352 4353 static void 4354 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4355 { 4356 uint16_t power[URTWN_RIDX_COUNT]; 4357 size_t i; 4358 4359 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4360 4361 for (i = 0; i < sc->ntxchains; i++) { 4362 /* Compute per-rate Tx power values. */ 4363 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4364 ISSET(sc->chip, URTWN_CHIP_92EU)) 4365 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4366 else 4367 urtwn_get_txpower(sc, i, chan, ht40m, power); 4368 /* Write per-rate Tx power values to hardware. */ 4369 urtwn_write_txpower(sc, i, power); 4370 } 4371 } 4372 4373 static void __noinline 4374 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4375 { 4376 struct ieee80211com *ic = &sc->sc_ic; 4377 u_int chan; 4378 size_t i; 4379 4380 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4381 4382 URTWNHIST_FUNC(); 4383 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4384 4385 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4386 4387 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4388 chan += 2; 4389 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4390 chan -= 2; 4391 } 4392 4393 /* Set Tx power for this new channel. */ 4394 urtwn_set_txpower(sc, chan, ht40m); 4395 4396 for (i = 0; i < sc->nrxchains; i++) { 4397 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4398 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4399 } 4400 4401 if (ht40m) { 4402 /* Is secondary channel below or above primary? */ 4403 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4404 uint32_t reg; 4405 4406 urtwn_write_1(sc, R92C_BWOPMODE, 4407 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4408 4409 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4410 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4411 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4412 4413 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4414 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4415 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4416 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4417 4418 /* Set CCK side band. */ 4419 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4420 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4421 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4422 4423 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4424 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4425 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4426 4427 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4428 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4429 ~R92C_FPGA0_ANAPARAM2_CBW20); 4430 4431 reg = urtwn_bb_read(sc, 0x818); 4432 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4433 urtwn_bb_write(sc, 0x818, reg); 4434 4435 /* Select 40MHz bandwidth. */ 4436 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4437 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4438 } else { 4439 urtwn_write_1(sc, R92C_BWOPMODE, 4440 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4441 4442 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4443 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4444 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4445 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4446 4447 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4448 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4449 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4450 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4451 R92C_FPGA0_ANAPARAM2_CBW20); 4452 } 4453 4454 /* Select 20MHz bandwidth. */ 4455 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4456 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4457 (ISSET(sc->chip, URTWN_CHIP_88E) || 4458 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4459 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4460 } 4461 } 4462 4463 static void __noinline 4464 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4465 { 4466 4467 URTWNHIST_FUNC(); 4468 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4469 4470 uint32_t addaBackup[16], iqkBackup[4], piMode; 4471 4472 #ifdef notyet 4473 uint32_t odfm0_agccore_regs[3]; 4474 uint32_t ant_regs[3]; 4475 uint32_t rf_regs[8]; 4476 #endif 4477 uint32_t reg0, reg1, reg2; 4478 int i, attempt; 4479 4480 #ifdef notyet 4481 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4482 R92E_STBC_SETTING + 2)); 4483 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4484 /* Save AGCCORE regs. */ 4485 for (i = 0; i < sc->nrxchains; i++) { 4486 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4487 R92C_OFDM0_AGCCORE1(i)); 4488 } 4489 #endif 4490 /* Save BB regs. */ 4491 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4492 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4493 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4494 4495 /* Save adda regs to be restored when finished. */ 4496 for (i = 0; i < __arraycount(addaReg); i++) 4497 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4498 /* Save mac regs. */ 4499 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4500 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4501 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4502 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4503 4504 #ifdef notyet 4505 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4506 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4507 4508 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4509 for (i = 0; i < sc->nrxchains; i++) 4510 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4511 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4512 #endif 4513 4514 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4515 R92C_HSSI_PARAM1_PI); 4516 if (piMode == 0) { 4517 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4518 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4519 R92C_HSSI_PARAM1_PI); 4520 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4521 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4522 R92C_HSSI_PARAM1_PI); 4523 } 4524 4525 attempt = 1; 4526 4527 next_attempt: 4528 4529 /* Set mac regs for calibration. */ 4530 for (i = 0; i < __arraycount(addaReg); i++) { 4531 urtwn_bb_write(sc, addaReg[i], 4532 addaReg[__arraycount(addaReg) - 1]); 4533 } 4534 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4535 R92C_CCK0_AFESETTING)); 4536 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4537 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4538 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4539 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4540 4541 if (sc->ntxchains > 1) 4542 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4543 4544 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4545 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4546 ~R92C_BCN_CTRL_EN_BCN)); 4547 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4548 ~R92C_BCN_CTRL_EN_BCN)); 4549 4550 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4551 ~R92C_GPIO_MUXCFG_ENBT)); 4552 4553 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4554 4555 if (sc->ntxchains > 1) 4556 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4557 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4558 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4559 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4560 4561 /* Restore BB regs. */ 4562 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4563 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4564 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4565 4566 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4567 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4568 if (sc->nrxchains > 1) 4569 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4570 4571 if (attempt-- > 0) 4572 goto next_attempt; 4573 4574 /* Restore mode. */ 4575 if (piMode == 0) { 4576 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4577 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4578 ~R92C_HSSI_PARAM1_PI); 4579 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4580 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4581 ~R92C_HSSI_PARAM1_PI); 4582 } 4583 4584 #ifdef notyet 4585 for (i = 0; i < sc->nrxchains; i++) { 4586 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4587 odfm0_agccore_regs[i]); 4588 } 4589 #endif 4590 4591 /* Restore adda regs. */ 4592 for (i = 0; i < __arraycount(addaReg); i++) 4593 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4594 /* Restore mac regs. */ 4595 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4596 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4597 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4598 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4599 4600 #ifdef notyet 4601 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4602 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4603 4604 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4605 for (i = 0; i < sc->nrxchains; i++) 4606 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4607 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4608 #endif 4609 } 4610 4611 static void 4612 urtwn_lc_calib(struct urtwn_softc *sc) 4613 { 4614 uint32_t rf_ac[2]; 4615 uint8_t txmode; 4616 size_t i; 4617 4618 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4619 4620 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4621 4622 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4623 if ((txmode & 0x70) != 0) { 4624 /* Disable all continuous Tx. */ 4625 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4626 4627 /* Set RF mode to standby mode. */ 4628 for (i = 0; i < sc->nrxchains; i++) { 4629 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4630 urtwn_rf_write(sc, i, R92C_RF_AC, 4631 RW(rf_ac[i], R92C_RF_AC_MODE, 4632 R92C_RF_AC_MODE_STANDBY)); 4633 } 4634 } else { 4635 /* Block all Tx queues. */ 4636 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4637 } 4638 /* Start calibration. */ 4639 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4640 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4641 4642 /* Give calibration the time to complete. */ 4643 urtwn_delay_ms(sc, 100); 4644 4645 /* Restore configuration. */ 4646 if ((txmode & 0x70) != 0) { 4647 /* Restore Tx mode. */ 4648 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4649 /* Restore RF mode. */ 4650 for (i = 0; i < sc->nrxchains; i++) { 4651 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4652 } 4653 } else { 4654 /* Unblock all Tx queues. */ 4655 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4656 } 4657 } 4658 4659 static void 4660 urtwn_temp_calib(struct urtwn_softc *sc) 4661 { 4662 int temp, t_meter_reg; 4663 4664 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4665 4666 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4667 4668 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4669 t_meter_reg = R92C_RF_T_METER; 4670 else 4671 t_meter_reg = R92E_RF_T_METER; 4672 4673 if (sc->thcal_state == 0) { 4674 /* Start measuring temperature. */ 4675 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4676 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4677 sc->thcal_state = 1; 4678 return; 4679 } 4680 sc->thcal_state = 0; 4681 4682 /* Read measured temperature. */ 4683 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4684 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4685 if (temp == 0) /* Read failed, skip. */ 4686 return; 4687 4688 /* 4689 * Redo LC calibration if temperature changed significantly since 4690 * last calibration. 4691 */ 4692 if (sc->thcal_lctemp == 0) { 4693 /* First LC calibration is performed in urtwn_init(). */ 4694 sc->thcal_lctemp = temp; 4695 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4696 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4697 sc->thcal_lctemp, temp, 0, 0); 4698 urtwn_lc_calib(sc); 4699 /* Record temperature of last LC calibration. */ 4700 sc->thcal_lctemp = temp; 4701 } 4702 } 4703 4704 static int 4705 urtwn_init(struct ifnet *ifp) 4706 { 4707 struct urtwn_softc *sc = ifp->if_softc; 4708 struct ieee80211com *ic = &sc->sc_ic; 4709 struct urtwn_rx_data *data; 4710 uint32_t reg; 4711 size_t i; 4712 int error; 4713 4714 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4715 4716 urtwn_stop(ifp, 0); 4717 4718 mutex_enter(&sc->sc_write_mtx); 4719 4720 mutex_enter(&sc->sc_task_mtx); 4721 /* Init host async commands ring. */ 4722 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4723 mutex_exit(&sc->sc_task_mtx); 4724 4725 mutex_enter(&sc->sc_fwcmd_mtx); 4726 /* Init firmware commands ring. */ 4727 sc->fwcur = 0; 4728 mutex_exit(&sc->sc_fwcmd_mtx); 4729 4730 /* Allocate Tx/Rx buffers. */ 4731 error = urtwn_alloc_rx_list(sc); 4732 if (error != 0) { 4733 aprint_error_dev(sc->sc_dev, 4734 "could not allocate Rx buffers\n"); 4735 goto fail; 4736 } 4737 error = urtwn_alloc_tx_list(sc); 4738 if (error != 0) { 4739 aprint_error_dev(sc->sc_dev, 4740 "could not allocate Tx buffers\n"); 4741 goto fail; 4742 } 4743 4744 /* Power on adapter. */ 4745 error = urtwn_power_on(sc); 4746 if (error != 0) 4747 goto fail; 4748 4749 /* Initialize DMA. */ 4750 error = urtwn_dma_init(sc); 4751 if (error != 0) 4752 goto fail; 4753 4754 /* Set info size in Rx descriptors (in 64-bit words). */ 4755 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4756 4757 /* Init interrupts. */ 4758 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4759 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4760 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4761 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4762 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4763 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4764 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4765 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4766 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4767 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4768 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4769 } 4770 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4771 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4772 } else { 4773 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4774 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4775 } 4776 4777 /* Set MAC address. */ 4778 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4779 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4780 4781 /* Set initial network type. */ 4782 reg = urtwn_read_4(sc, R92C_CR); 4783 switch (ic->ic_opmode) { 4784 case IEEE80211_M_STA: 4785 default: 4786 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4787 break; 4788 4789 case IEEE80211_M_IBSS: 4790 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4791 break; 4792 } 4793 urtwn_write_4(sc, R92C_CR, reg); 4794 4795 /* Set response rate */ 4796 reg = urtwn_read_4(sc, R92C_RRSR); 4797 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4798 urtwn_write_4(sc, R92C_RRSR, reg); 4799 4800 /* SIFS (used in NAV) */ 4801 urtwn_write_2(sc, R92C_SPEC_SIFS, 4802 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4803 4804 /* Set short/long retry limits. */ 4805 urtwn_write_2(sc, R92C_RL, 4806 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4807 4808 /* Initialize EDCA parameters. */ 4809 urtwn_edca_init(sc); 4810 4811 /* Setup rate fallback. */ 4812 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4813 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4814 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4815 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4816 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4817 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4818 } 4819 4820 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4821 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4822 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4823 /* Set ACK timeout. */ 4824 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4825 4826 /* Setup USB aggregation. */ 4827 /* Tx */ 4828 reg = urtwn_read_4(sc, R92C_TDECTRL); 4829 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4830 urtwn_write_4(sc, R92C_TDECTRL, reg); 4831 /* Rx */ 4832 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4833 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4834 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4835 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4836 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4837 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4838 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4839 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4840 ISSET(sc->chip, URTWN_CHIP_92EU)) 4841 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4842 else 4843 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4844 4845 /* Initialize beacon parameters. */ 4846 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4847 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4848 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4849 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4850 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4851 4852 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4853 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4854 /* Setup AMPDU aggregation. */ 4855 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4856 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4857 urtwn_write_2(sc, 0x4ca, 0x0708); 4858 4859 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4860 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4861 } 4862 4863 /* Load 8051 microcode. */ 4864 error = urtwn_load_firmware(sc); 4865 if (error != 0) 4866 goto fail; 4867 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4868 4869 /* Initialize MAC/BB/RF blocks. */ 4870 /* 4871 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4872 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4873 * XXX: This setting should be removed from rtl8192cu_mac[]. 4874 */ 4875 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4876 urtwn_rxfilter_init(sc); // reset R92C_RCR 4877 urtwn_bb_init(sc); 4878 urtwn_rf_init(sc); 4879 4880 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4881 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4882 urtwn_write_2(sc, R92C_CR, 4883 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4884 R92C_CR_MACRXEN); 4885 } 4886 4887 /* Turn CCK and OFDM blocks on. */ 4888 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4889 reg |= R92C_RFMOD_CCK_EN; 4890 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4891 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4892 reg |= R92C_RFMOD_OFDM_EN; 4893 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4894 4895 /* Clear per-station keys table. */ 4896 urtwn_cam_init(sc); 4897 4898 /* Enable hardware sequence numbering. */ 4899 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4900 4901 /* Perform LO and IQ calibrations. */ 4902 urtwn_iq_calib(sc, sc->iqk_inited); 4903 sc->iqk_inited = true; 4904 4905 /* Perform LC calibration. */ 4906 urtwn_lc_calib(sc); 4907 4908 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4909 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4910 /* Fix USB interference issue. */ 4911 urtwn_write_1(sc, 0xfe40, 0xe0); 4912 urtwn_write_1(sc, 0xfe41, 0x8d); 4913 urtwn_write_1(sc, 0xfe42, 0x80); 4914 urtwn_write_4(sc, 0x20c, 0xfd0320); 4915 4916 urtwn_pa_bias_init(sc); 4917 } 4918 4919 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4920 !(sc->chip & URTWN_CHIP_92EU)) { 4921 /* 1T1R */ 4922 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4923 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4924 } 4925 4926 /* Initialize GPIO setting. */ 4927 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4928 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4929 4930 /* Fix for lower temperature. */ 4931 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4932 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4933 urtwn_write_1(sc, 0x15, 0xe9); 4934 4935 /* Set default channel. */ 4936 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4937 4938 /* Queue Rx xfers. */ 4939 for (size_t j = 0; j < sc->rx_npipe; j++) { 4940 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4941 data = &sc->rx_data[j][i]; 4942 usbd_setup_xfer(data->xfer, data, data->buf, 4943 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4944 urtwn_rxeof); 4945 error = usbd_transfer(data->xfer); 4946 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4947 error != USBD_IN_PROGRESS)) 4948 goto fail; 4949 } 4950 } 4951 4952 /* We're ready to go. */ 4953 ifp->if_flags &= ~IFF_OACTIVE; 4954 ifp->if_flags |= IFF_RUNNING; 4955 sc->sc_running = true; 4956 4957 mutex_exit(&sc->sc_write_mtx); 4958 4959 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4960 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4961 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4962 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4963 urtwn_wait_async(sc); 4964 4965 return 0; 4966 4967 fail: 4968 mutex_exit(&sc->sc_write_mtx); 4969 4970 urtwn_stop(ifp, 1); 4971 return error; 4972 } 4973 4974 static void __noinline 4975 urtwn_stop(struct ifnet *ifp, int disable) 4976 { 4977 struct urtwn_softc *sc = ifp->if_softc; 4978 struct ieee80211com *ic = &sc->sc_ic; 4979 size_t i; 4980 int s; 4981 4982 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4983 4984 s = splusb(); 4985 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4986 urtwn_wait_async(sc); 4987 splx(s); 4988 4989 sc->tx_timer = 0; 4990 ifp->if_timer = 0; 4991 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4992 4993 callout_stop(&sc->sc_scan_to); 4994 callout_stop(&sc->sc_calib_to); 4995 4996 /* Abort Tx. */ 4997 for (i = 0; i < sc->tx_npipe; i++) { 4998 if (sc->tx_pipe[i] != NULL) 4999 usbd_abort_pipe(sc->tx_pipe[i]); 5000 } 5001 5002 /* Stop Rx pipe. */ 5003 for (i = 0; i < sc->rx_npipe; i++) { 5004 if (sc->rx_pipe[i] != NULL) 5005 usbd_abort_pipe(sc->rx_pipe[i]); 5006 } 5007 5008 /* Free Tx/Rx buffers. */ 5009 urtwn_free_tx_list(sc); 5010 urtwn_free_rx_list(sc); 5011 5012 sc->sc_running = false; 5013 if (disable) 5014 urtwn_chip_stop(sc); 5015 } 5016 5017 static int 5018 urtwn_reset(struct ifnet *ifp) 5019 { 5020 struct urtwn_softc *sc = ifp->if_softc; 5021 struct ieee80211com *ic = &sc->sc_ic; 5022 5023 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5024 return ENETRESET; 5025 5026 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5027 5028 return 0; 5029 } 5030 5031 static void 5032 urtwn_chip_stop(struct urtwn_softc *sc) 5033 { 5034 uint32_t reg; 5035 bool disabled = true; 5036 5037 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5038 5039 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5040 ISSET(sc->chip, URTWN_CHIP_92EU)) 5041 return; 5042 5043 mutex_enter(&sc->sc_write_mtx); 5044 5045 /* 5046 * RF Off Sequence 5047 */ 5048 /* Pause MAC TX queue */ 5049 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5050 5051 /* Disable RF */ 5052 urtwn_rf_write(sc, 0, 0, 0); 5053 5054 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5055 5056 /* Reset BB state machine */ 5057 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5058 R92C_SYS_FUNC_EN_USBD | 5059 R92C_SYS_FUNC_EN_USBA | 5060 R92C_SYS_FUNC_EN_BB_GLB_RST); 5061 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5062 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5063 5064 /* 5065 * Reset digital sequence 5066 */ 5067 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5068 /* Reset MCU ready status */ 5069 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5070 /* If firmware in ram code, do reset */ 5071 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5072 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5073 ISSET(sc->chip, URTWN_CHIP_92EU)) 5074 urtwn_r88e_fw_reset(sc); 5075 else 5076 urtwn_fw_reset(sc); 5077 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5078 } 5079 } 5080 5081 /* Reset MAC and Enable 8051 */ 5082 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5083 5084 /* Reset MCU ready status */ 5085 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5086 5087 if (disabled) { 5088 /* Disable MAC clock */ 5089 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5090 /* Disable AFE PLL */ 5091 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5092 /* Gated AFE DIG_CLOCK */ 5093 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5094 /* Isolated digital to PON */ 5095 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5096 } 5097 5098 /* 5099 * Pull GPIO PIN to balance level and LED control 5100 */ 5101 /* 1. Disable GPIO[7:0] */ 5102 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5103 5104 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5105 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5106 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5107 5108 /* Disable GPIO[10:8] */ 5109 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5110 5111 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5112 reg |= (((reg & 0x000f) << 4) | 0x0780); 5113 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5114 5115 /* Disable LED0 & 1 */ 5116 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5117 5118 /* 5119 * Reset digital sequence 5120 */ 5121 if (disabled) { 5122 /* Disable ELDR clock */ 5123 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5124 /* Isolated ELDR to PON */ 5125 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5126 } 5127 5128 /* 5129 * Disable analog sequence 5130 */ 5131 if (disabled) { 5132 /* Disable A15 power */ 5133 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5134 /* Disable digital core power */ 5135 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5136 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5137 ~R92C_LDOV12D_CTRL_LDV12_EN); 5138 } 5139 5140 /* Enter PFM mode */ 5141 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5142 5143 /* Set USB suspend */ 5144 urtwn_write_2(sc, R92C_APS_FSMCO, 5145 R92C_APS_FSMCO_APDM_HOST | 5146 R92C_APS_FSMCO_AFSM_HSUS | 5147 R92C_APS_FSMCO_PFM_ALDN); 5148 5149 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5150 5151 mutex_exit(&sc->sc_write_mtx); 5152 } 5153 5154 static void 5155 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5156 { 5157 if (sc->sc_running == false) 5158 DELAY(ms * 1000); 5159 else 5160 usbd_delay_ms(sc->sc_udev, ms); 5161 } 5162 5163 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5164 5165 #ifdef _MODULE 5166 #include "ioconf.c" 5167 #endif 5168 5169 static int 5170 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5171 { 5172 int error = 0; 5173 5174 switch (cmd) { 5175 case MODULE_CMD_INIT: 5176 #ifdef _MODULE 5177 error = config_init_component(cfdriver_ioconf_urtwn, 5178 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5179 #endif 5180 return error; 5181 case MODULE_CMD_FINI: 5182 #ifdef _MODULE 5183 error = config_fini_component(cfdriver_ioconf_urtwn, 5184 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5185 #endif 5186 return error; 5187 default: 5188 return ENOTTY; 5189 } 5190 } 5191
Indexes created Tue Sep 30 06:09:59 GMT 2025