if_urtwn.c revision 1.9
1 /* $NetBSD: if_urtwn.c,v 1.9 2013/01/05 23:34:18 christos Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.9 2013/01/05 23:34:18 christos Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/sysctl.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 #include <machine/endian.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 #include <netinet/in_systm.h> 53 #include <netinet/in_var.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_netbsd.h> 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/firmload.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usbdi_util.h> 66 #include <dev/usb/usbdevs.h> 67 68 #include <dev/usb/if_urtwnreg.h> 69 #include <dev/usb/if_urtwnvar.h> 70 #include <dev/usb/if_urtwn_data.h> 71 72 #ifdef URTWN_DEBUG 73 #define DBG_INIT __BIT(0) 74 #define DBG_FN __BIT(1) 75 #define DBG_TX __BIT(2) 76 #define DBG_RX __BIT(3) 77 #define DBG_STM __BIT(4) 78 #define DBG_RF __BIT(5) 79 #define DBG_REG __BIT(6) 80 #define DBG_ALL 0xffffffffU 81 u_int urtwn_debug = DBG_TX|DBG_RX|DBG_STM; 82 #define DPRINTFN(n, s) \ 83 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 84 #else 85 #define DPRINTFN(n, s) 86 #endif 87 88 static const struct usb_devno urtwn_devs[] = { 89 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 90 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 91 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 92 { USB_VENDOR_ASUSTEK, USB_PRODUCT_ASUSTEK_RTL8192CU }, 93 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 94 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 95 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 96 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 97 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 98 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 99 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 100 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 101 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 102 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 103 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 104 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 105 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 106 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 107 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 108 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, 109 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 110 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 111 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 112 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 113 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 114 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 115 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 116 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 117 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 118 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 119 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 120 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 121 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 122 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 123 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 124 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 125 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 126 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 127 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 128 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 129 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 130 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 131 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 132 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 133 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 134 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 135 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 136 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 137 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 138 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 139 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 140 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 141 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 142 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 143 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } 144 }; 145 146 static int urtwn_match(device_t, cfdata_t, void *); 147 static void urtwn_attach(device_t, device_t, void *); 148 static int urtwn_detach(device_t, int); 149 static int urtwn_activate(device_t, enum devact); 150 151 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 152 urtwn_attach, urtwn_detach, urtwn_activate); 153 154 static int urtwn_open_pipes(struct urtwn_softc *); 155 static void urtwn_close_pipes(struct urtwn_softc *); 156 static int urtwn_alloc_rx_list(struct urtwn_softc *); 157 static void urtwn_free_rx_list(struct urtwn_softc *); 158 static int urtwn_alloc_tx_list(struct urtwn_softc *); 159 static void urtwn_free_tx_list(struct urtwn_softc *); 160 static void urtwn_task(void *); 161 static void urtwn_do_async(struct urtwn_softc *, 162 void (*)(struct urtwn_softc *, void *), void *, int); 163 static void urtwn_wait_async(struct urtwn_softc *); 164 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 165 int); 166 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 167 int); 168 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 169 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 170 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 171 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 172 static void urtwn_efuse_read(struct urtwn_softc *); 173 static int urtwn_read_chipid(struct urtwn_softc *); 174 static void urtwn_read_rom(struct urtwn_softc *); 175 static int urtwn_media_change(struct ifnet *); 176 static int urtwn_ra_init(struct urtwn_softc *); 177 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 178 static void urtwn_set_led(struct urtwn_softc *, int, int); 179 static void urtwn_calib_to(void *); 180 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 181 static void urtwn_next_scan(void *); 182 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 183 int); 184 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 185 static int urtwn_wme_update(struct ieee80211com *); 186 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 187 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 188 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 189 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 190 static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 191 static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 192 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 193 struct ieee80211_node *); 194 static void urtwn_start(struct ifnet *); 195 static void urtwn_watchdog(struct ifnet *); 196 static int urtwn_ioctl(struct ifnet *, u_long, void *); 197 static int urtwn_power_on(struct urtwn_softc *); 198 static int urtwn_llt_init(struct urtwn_softc *); 199 static void urtwn_fw_reset(struct urtwn_softc *); 200 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 201 static int urtwn_load_firmware(struct urtwn_softc *); 202 static int urtwn_dma_init(struct urtwn_softc *); 203 static void urtwn_mac_init(struct urtwn_softc *); 204 static void urtwn_bb_init(struct urtwn_softc *); 205 static void urtwn_rf_init(struct urtwn_softc *); 206 static void urtwn_cam_init(struct urtwn_softc *); 207 static void urtwn_pa_bias_init(struct urtwn_softc *); 208 static void urtwn_rxfilter_init(struct urtwn_softc *); 209 static void urtwn_edca_init(struct urtwn_softc *); 210 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 211 static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, 212 uint16_t[]); 213 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 214 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 215 u_int); 216 static void urtwn_iq_calib(struct urtwn_softc *, bool); 217 static void urtwn_lc_calib(struct urtwn_softc *); 218 static void urtwn_temp_calib(struct urtwn_softc *); 219 static int urtwn_init(struct ifnet *); 220 static void urtwn_stop(struct ifnet *, int); 221 static void urtwn_chip_stop(struct urtwn_softc *); 222 223 /* Aliases. */ 224 #define urtwn_bb_write urtwn_write_4 225 #define urtwn_bb_read urtwn_read_4 226 227 static int 228 urtwn_match(device_t parent, cfdata_t match, void *aux) 229 { 230 struct usb_attach_arg *uaa = aux; 231 232 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 233 UMATCH_VENDOR_PRODUCT : UMATCH_NONE); 234 } 235 236 static void 237 urtwn_attach(device_t parent, device_t self, void *aux) 238 { 239 struct urtwn_softc *sc = device_private(self); 240 struct ieee80211com *ic = &sc->sc_ic; 241 struct ifnet *ifp = &sc->sc_if; 242 struct usb_attach_arg *uaa = aux; 243 char *devinfop; 244 int i, error; 245 246 sc->sc_dev = self; 247 sc->sc_udev = uaa->device; 248 249 aprint_naive("\n"); 250 aprint_normal("\n"); 251 252 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 253 aprint_normal_dev(self, "%s\n", devinfop); 254 usbd_devinfo_free(devinfop); 255 256 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 257 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NET); 258 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 259 260 usb_init_task(&sc->sc_task, urtwn_task, sc); 261 262 callout_init(&sc->sc_scan_to, 0); 263 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 264 callout_init(&sc->sc_calib_to, 0); 265 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 266 267 error = usbd_set_config_no(sc->sc_udev, 1, 0); 268 if (error != 0) { 269 aprint_error_dev(self, "failed to set configuration" 270 ", err=%s\n", usbd_errstr(error)); 271 goto fail; 272 } 273 274 /* Get the first interface handle. */ 275 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 276 if (error != 0) { 277 aprint_error_dev(self, "could not get interface handle\n"); 278 goto fail; 279 } 280 281 error = urtwn_read_chipid(sc); 282 if (error != 0) { 283 aprint_error_dev(self, "unsupported test chip\n"); 284 goto fail; 285 } 286 287 /* Determine number of Tx/Rx chains. */ 288 if (sc->chip & URTWN_CHIP_92C) { 289 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 290 sc->nrxchains = 2; 291 } else { 292 sc->ntxchains = 1; 293 sc->nrxchains = 1; 294 } 295 urtwn_read_rom(sc); 296 297 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 298 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 299 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 300 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 301 "8188CUS", sc->ntxchains, sc->nrxchains, 302 ether_sprintf(ic->ic_myaddr)); 303 304 error = urtwn_open_pipes(sc); 305 if (error != 0) { 306 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 307 goto fail; 308 } 309 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 310 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 311 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 312 313 /* 314 * Setup the 802.11 device. 315 */ 316 ic->ic_ifp = ifp; 317 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 318 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 319 ic->ic_state = IEEE80211_S_INIT; 320 321 /* Set device capabilities. */ 322 ic->ic_caps = 323 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 324 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 325 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 326 IEEE80211_C_WME | /* 802.11e */ 327 IEEE80211_C_WPA; /* 802.11i */ 328 329 /* Set supported .11b and .11g rates. */ 330 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 331 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 332 333 /* Set supported .11b and .11g channels (1 through 14). */ 334 for (i = 1; i <= 14; i++) { 335 ic->ic_channels[i].ic_freq = 336 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 337 ic->ic_channels[i].ic_flags = 338 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 339 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 340 } 341 342 ifp->if_softc = sc; 343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 344 ifp->if_init = urtwn_init; 345 ifp->if_ioctl = urtwn_ioctl; 346 ifp->if_start = urtwn_start; 347 ifp->if_watchdog = urtwn_watchdog; 348 IFQ_SET_READY(&ifp->if_snd); 349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 350 351 if_attach(ifp); 352 ieee80211_ifattach(ic); 353 /* override default methods */ 354 ic->ic_wme.wme_update = urtwn_wme_update; 355 356 /* Override state transition machine. */ 357 sc->sc_newstate = ic->ic_newstate; 358 ic->ic_newstate = urtwn_newstate; 359 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 360 361 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 362 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 363 &sc->sc_drvbpf); 364 365 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 366 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 367 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 368 369 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 370 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 371 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 372 373 ieee80211_announce(ic); 374 375 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 376 377 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 378 return; 379 380 fail: 381 sc->sc_dying = 1; 382 aprint_error_dev(self, "attach failed\n"); 383 } 384 385 static int 386 urtwn_detach(device_t self, int flags) 387 { 388 struct urtwn_softc *sc = device_private(self); 389 struct ifnet *ifp = &sc->sc_if; 390 int s; 391 392 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 393 394 s = splusb(); 395 396 sc->sc_dying = 1; 397 398 callout_stop(&sc->sc_scan_to); 399 callout_stop(&sc->sc_calib_to); 400 401 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 402 usb_rem_task(sc->sc_udev, &sc->sc_task); 403 urtwn_stop(ifp, 0); 404 405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 406 bpf_detach(ifp); 407 ieee80211_ifdetach(&sc->sc_ic); 408 if_detach(ifp); 409 410 /* Abort and close Tx/Rx pipes. */ 411 urtwn_close_pipes(sc); 412 } 413 414 splx(s); 415 416 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 417 418 callout_destroy(&sc->sc_scan_to); 419 callout_destroy(&sc->sc_calib_to); 420 mutex_destroy(&sc->sc_fwcmd_mtx); 421 mutex_destroy(&sc->sc_tx_mtx); 422 mutex_destroy(&sc->sc_task_mtx); 423 424 return (0); 425 } 426 427 static int 428 urtwn_activate(device_t self, enum devact act) 429 { 430 struct urtwn_softc *sc = device_private(self); 431 432 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 433 434 switch (act) { 435 case DVACT_DEACTIVATE: 436 if_deactivate(sc->sc_ic.ic_ifp); 437 return (0); 438 default: 439 return (EOPNOTSUPP); 440 } 441 } 442 443 static int 444 urtwn_open_pipes(struct urtwn_softc *sc) 445 { 446 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 447 static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 448 usb_interface_descriptor_t *id; 449 usb_endpoint_descriptor_t *ed; 450 int i, ntx = 0, error; 451 452 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 453 454 /* Determine the number of bulk-out pipes. */ 455 id = usbd_get_interface_descriptor(sc->sc_iface); 456 for (i = 0; i < id->bNumEndpoints; i++) { 457 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 458 if (ed != NULL && 459 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 460 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 461 ntx++; 462 } 463 DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", 464 device_xname(sc->sc_dev), __func__, ntx)); 465 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 466 aprint_error_dev(sc->sc_dev, 467 "%d: invalid number of Tx bulk pipes\n", ntx); 468 return (EIO); 469 } 470 sc->rx_npipe = 1; 471 sc->tx_npipe = ntx; 472 473 /* Open bulk-in pipe at address 0x81. */ 474 error = usbd_open_pipe(sc->sc_iface, 0x81, USBD_EXCLUSIVE_USE, 475 &sc->rx_pipe); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe\n"); 478 goto fail; 479 } 480 481 /* Open bulk-out pipes (up to 3). */ 482 for (i = 0; i < ntx; i++) { 483 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 484 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 485 if (error != 0) { 486 aprint_error_dev(sc->sc_dev, 487 "could not open Tx bulk pipe 0x%02x\n", epaddr[i]); 488 goto fail; 489 } 490 } 491 492 /* Map 802.11 access categories to USB pipes. */ 493 sc->ac2idx[WME_AC_BK] = 494 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 495 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 496 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 497 498 fail: 499 if (error != 0) 500 urtwn_close_pipes(sc); 501 return (error); 502 } 503 504 static void 505 urtwn_close_pipes(struct urtwn_softc *sc) 506 { 507 int i; 508 509 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 510 511 /* Close Rx pipe. */ 512 if (sc->rx_pipe != NULL) { 513 usbd_abort_pipe(sc->rx_pipe); 514 usbd_close_pipe(sc->rx_pipe); 515 sc->rx_pipe = NULL; 516 } 517 /* Close Tx pipes. */ 518 for (i = 0; i < R92C_MAX_EPOUT; i++) { 519 if (sc->tx_pipe[i] == NULL) 520 continue; 521 usbd_abort_pipe(sc->tx_pipe[i]); 522 usbd_close_pipe(sc->tx_pipe[i]); 523 sc->tx_pipe[i] = NULL; 524 } 525 } 526 527 static int 528 urtwn_alloc_rx_list(struct urtwn_softc *sc) 529 { 530 struct urtwn_rx_data *data; 531 int i, error = 0; 532 533 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 534 535 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 536 data = &sc->rx_data[i]; 537 538 data->sc = sc; /* Backpointer for callbacks. */ 539 540 data->xfer = usbd_alloc_xfer(sc->sc_udev); 541 if (data->xfer == NULL) { 542 aprint_error_dev(sc->sc_dev, 543 "could not allocate xfer\n"); 544 error = ENOMEM; 545 break; 546 } 547 548 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 549 if (data->buf == NULL) { 550 aprint_error_dev(sc->sc_dev, 551 "could not allocate xfer buffer\n"); 552 error = ENOMEM; 553 break; 554 } 555 } 556 if (error != 0) 557 urtwn_free_rx_list(sc); 558 return (error); 559 } 560 561 static void 562 urtwn_free_rx_list(struct urtwn_softc *sc) 563 { 564 int i; 565 566 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 567 568 /* NB: Caller must abort pipe first. */ 569 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 570 if (sc->rx_data[i].xfer != NULL) { 571 usbd_free_xfer(sc->rx_data[i].xfer); 572 sc->rx_data[i].xfer = NULL; 573 } 574 } 575 } 576 577 static int 578 urtwn_alloc_tx_list(struct urtwn_softc *sc) 579 { 580 struct urtwn_tx_data *data; 581 int i, error = 0; 582 583 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 584 585 mutex_enter(&sc->sc_tx_mtx); 586 TAILQ_INIT(&sc->tx_free_list); 587 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 588 data = &sc->tx_data[i]; 589 590 data->sc = sc; /* Backpointer for callbacks. */ 591 592 data->xfer = usbd_alloc_xfer(sc->sc_udev); 593 if (data->xfer == NULL) { 594 aprint_error_dev(sc->sc_dev, 595 "could not allocate xfer\n"); 596 error = ENOMEM; 597 goto fail; 598 } 599 600 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 601 if (data->buf == NULL) { 602 aprint_error_dev(sc->sc_dev, 603 "could not allocate xfer buffer\n"); 604 error = ENOMEM; 605 goto fail; 606 } 607 608 /* Append this Tx buffer to our free list. */ 609 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 610 } 611 mutex_exit(&sc->sc_tx_mtx); 612 return (0); 613 614 fail: 615 urtwn_free_tx_list(sc); 616 mutex_exit(&sc->sc_tx_mtx); 617 return (error); 618 } 619 620 static void 621 urtwn_free_tx_list(struct urtwn_softc *sc) 622 { 623 struct urtwn_tx_data *data; 624 int i; 625 626 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 627 628 /* NB: Caller must abort pipe first. */ 629 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 630 data = &sc->tx_data[i]; 631 632 if (data->xfer != NULL) { 633 usbd_free_xfer(data->xfer); 634 data->xfer = NULL; 635 } 636 } 637 } 638 639 static void 640 urtwn_task(void *arg) 641 { 642 struct urtwn_softc *sc = arg; 643 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 644 struct urtwn_host_cmd *cmd; 645 int s; 646 647 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 648 649 /* Process host commands. */ 650 s = splusb(); 651 mutex_spin_enter(&sc->sc_task_mtx); 652 while (ring->next != ring->cur) { 653 cmd = &ring->cmd[ring->next]; 654 mutex_spin_exit(&sc->sc_task_mtx); 655 splx(s); 656 /* Invoke callback. */ 657 cmd->cb(sc, cmd->data); 658 s = splusb(); 659 mutex_spin_enter(&sc->sc_task_mtx); 660 ring->queued--; 661 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 662 } 663 mutex_spin_exit(&sc->sc_task_mtx); 664 wakeup(&sc->cmdq); 665 splx(s); 666 } 667 668 static void 669 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 670 void *arg, int len) 671 { 672 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 673 struct urtwn_host_cmd *cmd; 674 int s; 675 676 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 677 device_xname(sc->sc_dev), __func__, cb, arg, len)); 678 679 s = splusb(); 680 mutex_spin_enter(&sc->sc_task_mtx); 681 cmd = &ring->cmd[ring->cur]; 682 cmd->cb = cb; 683 KASSERT(len <= sizeof(cmd->data)); 684 memcpy(cmd->data, arg, len); 685 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 686 687 /* If there is no pending command already, schedule a task. */ 688 if (!sc->sc_dying && ++ring->queued == 1) { 689 mutex_spin_exit(&sc->sc_task_mtx); 690 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 691 } else 692 mutex_spin_exit(&sc->sc_task_mtx); 693 splx(s); 694 } 695 696 static void 697 urtwn_wait_async(struct urtwn_softc *sc) 698 { 699 700 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 701 702 /* Wait for all queued asynchronous commands to complete. */ 703 while (sc->cmdq.queued > 0) 704 tsleep(&sc->cmdq, 0, "endtask", 0); 705 } 706 707 static int 708 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 709 int len) 710 { 711 usb_device_request_t req; 712 usbd_status error; 713 714 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 715 req.bRequest = R92C_REQ_REGS; 716 USETW(req.wValue, addr); 717 USETW(req.wIndex, 0); 718 USETW(req.wLength, len); 719 error = usbd_do_request(sc->sc_udev, &req, buf); 720 if (error != USBD_NORMAL_COMPLETION) { 721 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 722 device_xname(sc->sc_dev), __func__, error, addr, len)); 723 } 724 return (error); 725 } 726 727 static void 728 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 729 { 730 731 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 732 device_xname(sc->sc_dev), __func__, addr, val)); 733 734 urtwn_write_region_1(sc, addr, &val, 1); 735 } 736 737 static void 738 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 739 { 740 uint8_t buf[2]; 741 742 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 743 device_xname(sc->sc_dev), __func__, addr, val)); 744 745 buf[0] = (uint8_t)val; 746 buf[1] = (uint8_t)(val >> 8); 747 urtwn_write_region_1(sc, addr, buf, 2); 748 } 749 750 static void 751 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 752 { 753 uint8_t buf[4]; 754 755 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 756 device_xname(sc->sc_dev), __func__, addr, val)); 757 758 buf[0] = (uint8_t)val; 759 buf[1] = (uint8_t)(val >> 8); 760 buf[2] = (uint8_t)(val >> 16); 761 buf[3] = (uint8_t)(val >> 24); 762 urtwn_write_region_1(sc, addr, buf, 4); 763 } 764 765 static int 766 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 767 { 768 769 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 770 device_xname(sc->sc_dev), __func__, addr, len)); 771 772 return urtwn_write_region_1(sc, addr, buf, len); 773 } 774 775 static int 776 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 777 int len) 778 { 779 usb_device_request_t req; 780 usbd_status error; 781 782 req.bmRequestType = UT_READ_VENDOR_DEVICE; 783 req.bRequest = R92C_REQ_REGS; 784 USETW(req.wValue, addr); 785 USETW(req.wIndex, 0); 786 USETW(req.wLength, len); 787 error = usbd_do_request(sc->sc_udev, &req, buf); 788 if (error != USBD_NORMAL_COMPLETION) { 789 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 790 device_xname(sc->sc_dev), __func__, error, addr, len)); 791 } 792 return (error); 793 } 794 795 static uint8_t 796 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 797 { 798 uint8_t val; 799 800 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 801 return (0xff); 802 803 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 804 device_xname(sc->sc_dev), __func__, addr, val)); 805 return (val); 806 } 807 808 static uint16_t 809 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 810 { 811 uint8_t buf[2]; 812 uint16_t val; 813 814 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 815 return (0xffff); 816 817 val = LE_READ_2(&buf[0]); 818 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 819 device_xname(sc->sc_dev), __func__, addr, val)); 820 return (val); 821 } 822 823 static uint32_t 824 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 825 { 826 uint8_t buf[4]; 827 uint32_t val; 828 829 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 830 return (0xffffffff); 831 832 val = LE_READ_4(&buf[0]); 833 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 834 device_xname(sc->sc_dev), __func__, addr, val)); 835 return (val); 836 } 837 838 static int 839 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 840 { 841 struct r92c_fw_cmd cmd; 842 uint8_t *cp; 843 int fwcur; 844 int ntries; 845 846 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 847 device_xname(sc->sc_dev), __func__, id, buf, len)); 848 849 mutex_enter(&sc->sc_fwcmd_mtx); 850 fwcur = sc->fwcur; 851 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 852 mutex_exit(&sc->sc_fwcmd_mtx); 853 854 /* Wait for current FW box to be empty. */ 855 for (ntries = 0; ntries < 100; ntries++) { 856 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 857 break; 858 DELAY(1); 859 } 860 if (ntries == 100) { 861 aprint_error_dev(sc->sc_dev, 862 "could not send firmware command %d\n", id); 863 return (ETIMEDOUT); 864 } 865 866 memset(&cmd, 0, sizeof(cmd)); 867 KASSERT(len <= sizeof(cmd.msg)); 868 memcpy(cmd.msg, buf, len); 869 870 /* Write the first word last since that will trigger the FW. */ 871 cp = (uint8_t *)&cmd; 872 if (len >= 4) { 873 cmd.id = id | R92C_CMD_FLAG_EXT; 874 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), &cp[1], 2); 875 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 876 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 877 } else { 878 cmd.id = id; 879 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 880 } 881 882 return (0); 883 } 884 885 static void 886 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 887 { 888 889 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 890 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 891 } 892 893 static uint32_t 894 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 895 { 896 uint32_t reg[R92C_MAX_CHAINS], val; 897 898 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 899 if (chain != 0) { 900 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 901 } 902 903 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 904 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 905 DELAY(1000); 906 907 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 908 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 909 R92C_HSSI_PARAM2_READ_EDGE); 910 DELAY(1000); 911 912 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 913 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 914 DELAY(1000); 915 916 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 917 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 918 } else { 919 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 920 } 921 return (MS(val, R92C_LSSI_READBACK_DATA)); 922 } 923 924 static int 925 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 926 { 927 int ntries; 928 929 urtwn_write_4(sc, R92C_LLT_INIT, 930 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 931 SM(R92C_LLT_INIT_ADDR, addr) | 932 SM(R92C_LLT_INIT_DATA, data)); 933 /* Wait for write operation to complete. */ 934 for (ntries = 0; ntries < 20; ntries++) { 935 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 936 R92C_LLT_INIT_OP_NO_ACTIVE) { 937 /* Done */ 938 return (0); 939 } 940 DELAY(5); 941 } 942 return (ETIMEDOUT); 943 } 944 945 static uint8_t 946 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 947 { 948 uint32_t reg; 949 int ntries; 950 951 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 952 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 953 reg &= ~R92C_EFUSE_CTRL_VALID; 954 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 955 956 /* Wait for read operation to complete. */ 957 for (ntries = 0; ntries < 100; ntries++) { 958 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 959 if (reg & R92C_EFUSE_CTRL_VALID) { 960 /* Done */ 961 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 962 } 963 DELAY(5); 964 } 965 aprint_error_dev(sc->sc_dev, 966 "could not read efuse byte at address 0x%04x\n", addr); 967 return (0xff); 968 } 969 970 static void 971 urtwn_efuse_read(struct urtwn_softc *sc) 972 { 973 uint8_t *rom = (uint8_t *)&sc->rom; 974 uint32_t reg; 975 uint16_t addr = 0; 976 uint8_t off, msk; 977 int i; 978 979 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 980 981 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 982 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 983 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 984 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 985 } 986 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 987 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 988 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 989 reg | R92C_SYS_FUNC_EN_ELDR); 990 } 991 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 992 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 993 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 994 urtwn_write_2(sc, R92C_SYS_CLKR, 995 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 996 } 997 memset(&sc->rom, 0xff, sizeof(sc->rom)); 998 while (addr < 512) { 999 reg = urtwn_efuse_read_1(sc, addr); 1000 if (reg == 0xff) 1001 break; 1002 addr++; 1003 off = reg >> 4; 1004 msk = reg & 0xf; 1005 for (i = 0; i < 4; i++) { 1006 if (msk & (1U << i)) 1007 continue; 1008 1009 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1010 addr++; 1011 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1012 addr++; 1013 } 1014 } 1015 #ifdef URTWN_DEBUG 1016 if (urtwn_debug & DBG_INIT) { 1017 /* Dump ROM content. */ 1018 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1019 for (i = 0; i < (int)sizeof(sc->rom); i++) 1020 printf(":%02x", rom[i]); 1021 printf("\n"); 1022 } 1023 #endif 1024 } 1025 1026 static int 1027 urtwn_read_chipid(struct urtwn_softc *sc) 1028 { 1029 uint32_t reg; 1030 1031 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1032 1033 sc->chip = 0; 1034 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1035 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1036 /* test chip, not supported */ 1037 return (EIO); 1038 } 1039 if (reg & R92C_SYS_CFG_TYPE_92C) { 1040 sc->chip |= URTWN_CHIP_92C; 1041 /* Check if it is a castrated 8192C. */ 1042 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1043 R92C_HPON_FSM_CHIP_BONDING_ID) == 1044 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1045 sc->chip |= URTWN_CHIP_92C_1T2R; 1046 } 1047 } 1048 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1049 sc->chip |= URTWN_CHIP_UMC; 1050 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1051 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1052 } 1053 } 1054 return (0); 1055 } 1056 1057 #ifdef URTWN_DEBUG 1058 static void 1059 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1060 { 1061 1062 aprint_normal_dev(sc->sc_dev, 1063 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1064 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1065 1066 aprint_normal_dev(sc->sc_dev, 1067 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1068 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1069 1070 aprint_normal_dev(sc->sc_dev, 1071 "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", 1072 rp->macaddr[0], rp->macaddr[1], 1073 rp->macaddr[2], rp->macaddr[3], 1074 rp->macaddr[4], rp->macaddr[5]); 1075 1076 aprint_normal_dev(sc->sc_dev, 1077 "string %s, subcustomer_id 0x%x\n", 1078 rp->string, rp->subcustomer_id); 1079 1080 aprint_normal_dev(sc->sc_dev, 1081 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1082 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1083 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1084 1085 aprint_normal_dev(sc->sc_dev, 1086 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1087 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1088 rp->ht40_1s_tx_pwr[0][2], 1089 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1090 rp->ht40_1s_tx_pwr[1][2]); 1091 1092 aprint_normal_dev(sc->sc_dev, 1093 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1094 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1095 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1096 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1097 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1098 1099 aprint_normal_dev(sc->sc_dev, 1100 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1101 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1102 rp->ht20_tx_pwr_diff[2] & 0xf, 1103 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1104 rp->ht20_tx_pwr_diff[2] >> 4); 1105 1106 aprint_normal_dev(sc->sc_dev, 1107 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1108 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1109 rp->ofdm_tx_pwr_diff[2] & 0xf, 1110 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1111 rp->ofdm_tx_pwr_diff[2] >> 4); 1112 1113 aprint_normal_dev(sc->sc_dev, 1114 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1115 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1116 rp->ht40_max_pwr[2] & 0xf, 1117 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1118 rp->ht40_max_pwr[2] >> 4); 1119 1120 aprint_normal_dev(sc->sc_dev, 1121 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1122 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1123 rp->ht20_max_pwr[2] & 0xf, 1124 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1125 rp->ht20_max_pwr[2] >> 4); 1126 1127 aprint_normal_dev(sc->sc_dev, 1128 "xtal_calib %d, tssi %d %d, thermal %d\n", 1129 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1130 1131 aprint_normal_dev(sc->sc_dev, 1132 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1133 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1134 1135 aprint_normal_dev(sc->sc_dev, 1136 "channnel_plan %d, version %d customer_id 0x%x\n", 1137 rp->channel_plan, rp->version, rp->curstomer_id); 1138 } 1139 #endif 1140 1141 static void 1142 urtwn_read_rom(struct urtwn_softc *sc) 1143 { 1144 struct ieee80211com *ic = &sc->sc_ic; 1145 struct r92c_rom *rom = &sc->rom; 1146 1147 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1148 1149 /* Read full ROM image. */ 1150 urtwn_efuse_read(sc); 1151 #ifdef URTWN_DEBUG 1152 if (urtwn_debug & DBG_REG) 1153 urtwn_dump_rom(sc, rom); 1154 #endif 1155 1156 /* XXX Weird but this is what the vendor driver does. */ 1157 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1158 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1159 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1160 1161 DPRINTFN(DBG_INIT, 1162 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1163 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1164 sc->board_type, sc->regulatory)); 1165 1166 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1167 } 1168 1169 static int 1170 urtwn_media_change(struct ifnet *ifp) 1171 { 1172 #ifdef URTWN_DEBUG 1173 struct urtwn_softc *sc = ifp->if_softc; 1174 #endif 1175 int error; 1176 1177 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1178 1179 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1180 return (error); 1181 1182 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1183 (IFF_UP | IFF_RUNNING)) { 1184 urtwn_init(ifp); 1185 } 1186 return (0); 1187 } 1188 1189 /* 1190 * Initialize rate adaptation in firmware. 1191 */ 1192 static int 1193 urtwn_ra_init(struct urtwn_softc *sc) 1194 { 1195 static const uint8_t map[] = { 1196 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1197 }; 1198 struct ieee80211com *ic = &sc->sc_ic; 1199 struct ieee80211_node *ni = ic->ic_bss; 1200 struct ieee80211_rateset *rs = &ni->ni_rates; 1201 struct r92c_fw_cmd_macid_cfg cmd; 1202 uint32_t rates, basicrates; 1203 uint32_t mask; 1204 uint8_t mode; 1205 int maxrate, maxbasicrate, error, i, j; 1206 1207 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1208 1209 /* Get normal and basic rates mask. */ 1210 rates = basicrates = 0; 1211 maxrate = maxbasicrate = 0; 1212 for (i = 0; i < rs->rs_nrates; i++) { 1213 /* Convert 802.11 rate to HW rate index. */ 1214 for (j = 0; j < (int)__arraycount(map); j++) { 1215 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1216 break; 1217 } 1218 } 1219 if (j == __arraycount(map)) { 1220 /* Unknown rate, skip. */ 1221 continue; 1222 } 1223 1224 rates |= 1U << j; 1225 if (j > maxrate) { 1226 maxrate = j; 1227 } 1228 1229 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1230 basicrates |= 1U << j; 1231 if (j > maxbasicrate) { 1232 maxbasicrate = j; 1233 } 1234 } 1235 } 1236 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1237 mode = R92C_RAID_11B; 1238 } else { 1239 mode = R92C_RAID_11BG; 1240 } 1241 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1242 "maxrate=%x, maxbasicrate=%x\n", 1243 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1244 maxrate, maxbasicrate)); 1245 if (basicrates == 0) { 1246 basicrates |= 1; /* add 1Mbps */ 1247 } 1248 1249 /* Set rates mask for group addressed frames. */ 1250 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1251 mask = (mode << 28) | basicrates; 1252 cmd.mask[0] = (uint8_t)mask; 1253 cmd.mask[1] = (uint8_t)(mask >> 8); 1254 cmd.mask[2] = (uint8_t)(mask >> 16); 1255 cmd.mask[3] = (uint8_t)(mask >> 24); 1256 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1257 if (error != 0) { 1258 aprint_error_dev(sc->sc_dev, 1259 "could not add broadcast station\n"); 1260 return (error); 1261 } 1262 /* Set initial MRR rate. */ 1263 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", 1264 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1265 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); 1266 1267 /* Set rates mask for unicast frames. */ 1268 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1269 mask = (mode << 28) | rates; 1270 cmd.mask[0] = (uint8_t)mask; 1271 cmd.mask[1] = (uint8_t)(mask >> 8); 1272 cmd.mask[2] = (uint8_t)(mask >> 16); 1273 cmd.mask[3] = (uint8_t)(mask >> 24); 1274 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1275 if (error != 0) { 1276 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1277 return (error); 1278 } 1279 /* Set initial MRR rate. */ 1280 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), 1281 __func__, maxrate)); 1282 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); 1283 1284 /* Indicate highest supported rate. */ 1285 ni->ni_txrate = rs->rs_nrates - 1; 1286 1287 return (0); 1288 } 1289 1290 static int 1291 urtwn_get_nettype(struct urtwn_softc *sc) 1292 { 1293 struct ieee80211com *ic = &sc->sc_ic; 1294 int type; 1295 1296 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1297 1298 switch (ic->ic_opmode) { 1299 case IEEE80211_M_STA: 1300 type = R92C_CR_NETTYPE_INFRA; 1301 break; 1302 1303 case IEEE80211_M_IBSS: 1304 type = R92C_CR_NETTYPE_ADHOC; 1305 break; 1306 1307 default: 1308 type = R92C_CR_NETTYPE_NOLINK; 1309 break; 1310 } 1311 1312 return (type); 1313 } 1314 1315 static void 1316 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1317 { 1318 uint8_t reg; 1319 1320 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1321 __func__, type)); 1322 1323 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1324 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1325 } 1326 1327 static void 1328 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1329 { 1330 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1331 uint64_t tsf; 1332 1333 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1334 1335 /* Enable TSF synchronization. */ 1336 urtwn_write_1(sc, R92C_BCN_CTRL, 1337 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1338 1339 /* Correct TSF */ 1340 urtwn_write_1(sc, R92C_BCN_CTRL, 1341 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1342 1343 /* Set initial TSF. */ 1344 tsf = ni->ni_tstamp.tsf; 1345 tsf = le64toh(tsf); 1346 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1347 tsf -= IEEE80211_DUR_TU; 1348 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1349 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1350 1351 urtwn_write_1(sc, R92C_BCN_CTRL, 1352 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1353 } 1354 1355 static void 1356 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1357 { 1358 uint8_t reg; 1359 1360 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1361 __func__, led, on)); 1362 1363 if (led == URTWN_LED_LINK) { 1364 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1365 if (!on) { 1366 reg |= R92C_LEDCFG0_DIS; 1367 } 1368 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1369 sc->ledlink = on; /* Save LED state. */ 1370 } 1371 } 1372 1373 static void 1374 urtwn_calib_to(void *arg) 1375 { 1376 struct urtwn_softc *sc = arg; 1377 1378 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1379 1380 if (sc->sc_dying) 1381 return; 1382 1383 /* Do it in a process context. */ 1384 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1385 } 1386 1387 /* ARGSUSED */ 1388 static void 1389 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1390 { 1391 struct r92c_fw_cmd_rssi cmd; 1392 1393 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1394 1395 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1396 goto restart_timer; 1397 1398 if (sc->avg_pwdb != -1) { 1399 /* Indicate Rx signal strength to FW for rate adaptation. */ 1400 memset(&cmd, 0, sizeof(cmd)); 1401 cmd.macid = 0; /* BSS. */ 1402 cmd.pwdb = sc->avg_pwdb; 1403 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1404 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1405 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1406 } 1407 1408 /* Do temperature compensation. */ 1409 urtwn_temp_calib(sc); 1410 1411 restart_timer: 1412 if (!sc->sc_dying) { 1413 /* Restart calibration timer. */ 1414 callout_schedule(&sc->sc_calib_to, hz); 1415 } 1416 } 1417 1418 static void 1419 urtwn_next_scan(void *arg) 1420 { 1421 struct urtwn_softc *sc = arg; 1422 1423 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1424 1425 if (sc->sc_dying) 1426 return; 1427 1428 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1429 ieee80211_next_scan(&sc->sc_ic); 1430 } 1431 1432 static int 1433 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1434 { 1435 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1436 struct urtwn_cmd_newstate cmd; 1437 1438 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1439 device_xname(sc->sc_dev), __func__, 1440 ieee80211_state_name[nstate], nstate, arg)); 1441 1442 callout_stop(&sc->sc_scan_to); 1443 callout_stop(&sc->sc_calib_to); 1444 1445 /* Do it in a process context. */ 1446 cmd.state = nstate; 1447 cmd.arg = arg; 1448 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1449 return (0); 1450 } 1451 1452 static void 1453 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1454 { 1455 struct urtwn_cmd_newstate *cmd = arg; 1456 struct ieee80211com *ic = &sc->sc_ic; 1457 struct ieee80211_node *ni; 1458 enum ieee80211_state ostate = ic->ic_state; 1459 enum ieee80211_state nstate = cmd->state; 1460 uint32_t reg; 1461 uint8_t sifs_time; 1462 int s; 1463 1464 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1465 device_xname(sc->sc_dev), __func__, 1466 ieee80211_state_name[ostate], ostate, 1467 ieee80211_state_name[nstate], nstate)); 1468 1469 s = splnet(); 1470 1471 switch (ostate) { 1472 case IEEE80211_S_INIT: 1473 break; 1474 1475 case IEEE80211_S_SCAN: 1476 if (nstate != IEEE80211_S_SCAN) { 1477 /* 1478 * End of scanning 1479 */ 1480 /* flush 4-AC Queue after site_survey */ 1481 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1482 1483 /* Allow Rx from our BSSID only. */ 1484 urtwn_write_4(sc, R92C_RCR, 1485 urtwn_read_4(sc, R92C_RCR) | 1486 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1487 } 1488 break; 1489 1490 case IEEE80211_S_AUTH: 1491 case IEEE80211_S_ASSOC: 1492 break; 1493 1494 case IEEE80211_S_RUN: 1495 /* Turn link LED off. */ 1496 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1497 1498 /* Set media status to 'No Link'. */ 1499 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1500 1501 /* Stop Rx of data frames. */ 1502 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1503 1504 /* Reset TSF. */ 1505 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1506 1507 /* Disable TSF synchronization. */ 1508 urtwn_write_1(sc, R92C_BCN_CTRL, 1509 urtwn_read_1(sc, R92C_BCN_CTRL) | 1510 R92C_BCN_CTRL_DIS_TSF_UDT0); 1511 1512 /* Back to 20MHz mode */ 1513 urtwn_set_chan(sc, ic->ic_bss->ni_chan, 1514 IEEE80211_HTINFO_2NDCHAN_NONE); 1515 1516 if (ic->ic_opmode == IEEE80211_M_IBSS || 1517 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1518 /* Stop BCN */ 1519 urtwn_write_1(sc, R92C_BCN_CTRL, 1520 urtwn_read_1(sc, R92C_BCN_CTRL) & 1521 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1522 } 1523 1524 /* Reset EDCA parameters. */ 1525 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1526 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1527 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1528 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1529 1530 /* flush all cam entries */ 1531 urtwn_cam_init(sc); 1532 break; 1533 } 1534 1535 switch (nstate) { 1536 case IEEE80211_S_INIT: 1537 /* Turn link LED off. */ 1538 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1539 break; 1540 1541 case IEEE80211_S_SCAN: 1542 if (ostate != IEEE80211_S_SCAN) { 1543 /* 1544 * Begin of scanning 1545 */ 1546 1547 /* Set gain for scanning. */ 1548 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1549 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1550 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1551 1552 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1553 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1554 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1555 1556 /* Set media status to 'No Link'. */ 1557 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1558 1559 /* Allow Rx from any BSSID. */ 1560 urtwn_write_4(sc, R92C_RCR, 1561 urtwn_read_4(sc, R92C_RCR) & 1562 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1563 1564 /* Stop Rx of data frames. */ 1565 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1566 1567 /* Disable update TSF */ 1568 urtwn_write_1(sc, R92C_BCN_CTRL, 1569 urtwn_read_1(sc, R92C_BCN_CTRL) | 1570 R92C_BCN_CTRL_DIS_TSF_UDT0); 1571 } 1572 1573 /* Make link LED blink during scan. */ 1574 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1575 1576 /* Pause AC Tx queues. */ 1577 urtwn_write_1(sc, R92C_TXPAUSE, 1578 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1579 1580 urtwn_set_chan(sc, ic->ic_curchan, 1581 IEEE80211_HTINFO_2NDCHAN_NONE); 1582 1583 /* Start periodic scan. */ 1584 if (!sc->sc_dying) 1585 callout_schedule(&sc->sc_scan_to, hz / 5); 1586 break; 1587 1588 case IEEE80211_S_AUTH: 1589 /* Set initial gain under link. */ 1590 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1591 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1592 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1593 1594 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1595 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1596 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1597 1598 /* Set media status to 'No Link'. */ 1599 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1600 1601 /* Allow Rx from any BSSID. */ 1602 urtwn_write_4(sc, R92C_RCR, 1603 urtwn_read_4(sc, R92C_RCR) & 1604 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1605 1606 urtwn_set_chan(sc, ic->ic_curchan, 1607 IEEE80211_HTINFO_2NDCHAN_NONE); 1608 break; 1609 1610 case IEEE80211_S_ASSOC: 1611 break; 1612 1613 case IEEE80211_S_RUN: 1614 ni = ic->ic_bss; 1615 1616 /* XXX: Set 20MHz mode */ 1617 urtwn_set_chan(sc, ic->ic_curchan, 1618 IEEE80211_HTINFO_2NDCHAN_NONE); 1619 1620 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1621 /* Back to 20MHz mode */ 1622 urtwn_set_chan(sc, ic->ic_ibss_chan, 1623 IEEE80211_HTINFO_2NDCHAN_NONE); 1624 1625 /* Enable Rx of data frames. */ 1626 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1627 1628 /* Turn link LED on. */ 1629 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1630 break; 1631 } 1632 1633 /* Set media status to 'Associated'. */ 1634 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 1635 1636 /* Set BSSID. */ 1637 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1638 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1639 1640 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1641 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1642 } else { 1643 /* 802.11b/g */ 1644 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1645 } 1646 1647 /* Enable Rx of data frames. */ 1648 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1649 1650 /* Set beacon interval. */ 1651 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1652 1653 if (ic->ic_opmode == IEEE80211_M_STA) { 1654 /* Allow Rx from our BSSID only. */ 1655 urtwn_write_4(sc, R92C_RCR, 1656 urtwn_read_4(sc, R92C_RCR) | 1657 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1658 1659 /* Enable TSF synchronization. */ 1660 urtwn_tsf_sync_enable(sc); 1661 } 1662 1663 sifs_time = 10; 1664 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 1665 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 1666 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 1667 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 1668 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 1669 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 1670 1671 /* Intialize rate adaptation. */ 1672 urtwn_ra_init(sc); 1673 1674 /* Turn link LED on. */ 1675 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1676 1677 /* Reset average RSSI. */ 1678 sc->avg_pwdb = -1; 1679 1680 /* Reset temperature calibration state machine. */ 1681 sc->thcal_state = 0; 1682 sc->thcal_lctemp = 0; 1683 1684 /* Start periodic calibration. */ 1685 if (!sc->sc_dying) 1686 callout_schedule(&sc->sc_calib_to, hz); 1687 break; 1688 } 1689 1690 (*sc->sc_newstate)(ic, nstate, cmd->arg); 1691 1692 splx(s); 1693 } 1694 1695 static int 1696 urtwn_wme_update(struct ieee80211com *ic) 1697 { 1698 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1699 1700 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1701 1702 /* don't override default WME values if WME is not actually enabled */ 1703 if (!(ic->ic_flags & IEEE80211_F_WME)) 1704 return (0); 1705 1706 /* Do it in a process context. */ 1707 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 1708 return (0); 1709 } 1710 1711 static void 1712 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 1713 { 1714 static const uint16_t ac2reg[WME_NUM_AC] = { 1715 R92C_EDCA_BE_PARAM, 1716 R92C_EDCA_BK_PARAM, 1717 R92C_EDCA_VI_PARAM, 1718 R92C_EDCA_VO_PARAM 1719 }; 1720 struct ieee80211com *ic = &sc->sc_ic; 1721 const struct wmeParams *wmep; 1722 int ac, aifs, slottime; 1723 int s; 1724 1725 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 1726 __func__)); 1727 1728 s = splnet(); 1729 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1730 for (ac = 0; ac < WME_NUM_AC; ac++) { 1731 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 1732 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1733 aifs = wmep->wmep_aifsn * slottime + 10; 1734 urtwn_write_4(sc, ac2reg[ac], 1735 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1736 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1737 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1738 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1739 } 1740 splx(s); 1741 } 1742 1743 static void 1744 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1745 { 1746 int pwdb; 1747 1748 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 1749 device_xname(sc->sc_dev), __func__, rate, rssi)); 1750 1751 /* Convert antenna signal to percentage. */ 1752 if (rssi <= -100 || rssi >= 20) 1753 pwdb = 0; 1754 else if (rssi >= 0) 1755 pwdb = 100; 1756 else 1757 pwdb = 100 + rssi; 1758 if (rate <= 3) { 1759 /* CCK gain is smaller than OFDM/MCS gain. */ 1760 pwdb += 6; 1761 if (pwdb > 100) 1762 pwdb = 100; 1763 if (pwdb <= 14) 1764 pwdb -= 4; 1765 else if (pwdb <= 26) 1766 pwdb -= 8; 1767 else if (pwdb <= 34) 1768 pwdb -= 6; 1769 else if (pwdb <= 42) 1770 pwdb -= 2; 1771 } 1772 if (sc->avg_pwdb == -1) /* Init. */ 1773 sc->avg_pwdb = pwdb; 1774 else if (sc->avg_pwdb < pwdb) 1775 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1776 else 1777 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1778 1779 DPRINTFN(DBG_RF, ("%s: %s: PWDB=%d EMA=%d\n", device_xname(sc->sc_dev), 1780 __func__, pwdb, sc->avg_pwdb)); 1781 } 1782 1783 static int8_t 1784 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1785 { 1786 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1787 struct r92c_rx_phystat *phy; 1788 struct r92c_rx_cck *cck; 1789 uint8_t rpt; 1790 int8_t rssi; 1791 1792 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 1793 __func__, rate)); 1794 1795 if (rate <= 3) { 1796 cck = (struct r92c_rx_cck *)physt; 1797 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 1798 rpt = (cck->agc_rpt >> 5) & 0x3; 1799 rssi = (cck->agc_rpt & 0x1f) << 1; 1800 } else { 1801 rpt = (cck->agc_rpt >> 6) & 0x3; 1802 rssi = cck->agc_rpt & 0x3e; 1803 } 1804 rssi = cckoff[rpt] - rssi; 1805 } else { /* OFDM/HT. */ 1806 phy = (struct r92c_rx_phystat *)physt; 1807 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1808 } 1809 return (rssi); 1810 } 1811 1812 static void 1813 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1814 { 1815 struct ieee80211com *ic = &sc->sc_ic; 1816 struct ifnet *ifp = ic->ic_ifp; 1817 struct ieee80211_frame *wh; 1818 struct ieee80211_node *ni; 1819 struct r92c_rx_stat *stat; 1820 uint32_t rxdw0, rxdw3; 1821 struct mbuf *m; 1822 uint8_t rate; 1823 int8_t rssi = 0; 1824 int s, infosz; 1825 1826 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 1827 device_xname(sc->sc_dev), __func__, buf, pktlen)); 1828 1829 stat = (struct r92c_rx_stat *)buf; 1830 rxdw0 = le32toh(stat->rxdw0); 1831 rxdw3 = le32toh(stat->rxdw3); 1832 1833 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1834 /* 1835 * This should not happen since we setup our Rx filter 1836 * to not receive these frames. 1837 */ 1838 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 1839 device_xname(sc->sc_dev), __func__)); 1840 ifp->if_ierrors++; 1841 return; 1842 } 1843 if (__predict_false(pktlen < (int)sizeof(*wh))) { 1844 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 1845 device_xname(sc->sc_dev), __func__, pktlen)); 1846 ic->ic_stats.is_rx_tooshort++; 1847 ifp->if_ierrors++; 1848 return; 1849 } 1850 if (__predict_false(pktlen > MCLBYTES)) { 1851 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 1852 device_xname(sc->sc_dev), __func__, pktlen)); 1853 ifp->if_ierrors++; 1854 return; 1855 } 1856 1857 rate = MS(rxdw3, R92C_RXDW3_RATE); 1858 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1859 1860 /* Get RSSI from PHY status descriptor if present. */ 1861 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1862 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1863 /* Update our average RSSI. */ 1864 urtwn_update_avgrssi(sc, rate, rssi); 1865 } 1866 1867 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1868 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 1869 1870 MGETHDR(m, M_DONTWAIT, MT_DATA); 1871 if (__predict_false(m == NULL)) { 1872 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 1873 ic->ic_stats.is_rx_nobuf++; 1874 ifp->if_ierrors++; 1875 return; 1876 } 1877 if (pktlen > (int)MHLEN) { 1878 MCLGET(m, M_DONTWAIT); 1879 if (__predict_false(!(m->m_flags & M_EXT))) { 1880 aprint_error_dev(sc->sc_dev, 1881 "couldn't allocate rx mbuf cluster\n"); 1882 m_freem(m); 1883 ic->ic_stats.is_rx_nobuf++; 1884 ifp->if_ierrors++; 1885 return; 1886 } 1887 } 1888 1889 /* Finalize mbuf. */ 1890 m->m_pkthdr.rcvif = ifp; 1891 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1892 memcpy(mtod(m, uint8_t *), wh, pktlen); 1893 m->m_pkthdr.len = m->m_len = pktlen; 1894 1895 s = splnet(); 1896 if (__predict_false(sc->sc_drvbpf != NULL)) { 1897 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1898 1899 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1900 if (!(rxdw3 & R92C_RXDW3_HT)) { 1901 switch (rate) { 1902 /* CCK. */ 1903 case 0: tap->wr_rate = 2; break; 1904 case 1: tap->wr_rate = 4; break; 1905 case 2: tap->wr_rate = 11; break; 1906 case 3: tap->wr_rate = 22; break; 1907 /* OFDM. */ 1908 case 4: tap->wr_rate = 12; break; 1909 case 5: tap->wr_rate = 18; break; 1910 case 6: tap->wr_rate = 24; break; 1911 case 7: tap->wr_rate = 36; break; 1912 case 8: tap->wr_rate = 48; break; 1913 case 9: tap->wr_rate = 72; break; 1914 case 10: tap->wr_rate = 96; break; 1915 case 11: tap->wr_rate = 108; break; 1916 } 1917 } else if (rate >= 12) { /* MCS0~15. */ 1918 /* Bit 7 set means HT MCS instead of rate. */ 1919 tap->wr_rate = 0x80 | (rate - 12); 1920 } 1921 tap->wr_dbm_antsignal = rssi; 1922 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1923 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1924 1925 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1926 } 1927 1928 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1929 1930 /* push the frame up to the 802.11 stack */ 1931 ieee80211_input(ic, m, ni, rssi, 0); 1932 1933 /* Node is no longer needed. */ 1934 ieee80211_free_node(ni); 1935 1936 splx(s); 1937 } 1938 1939 static void 1940 urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1941 { 1942 struct urtwn_rx_data *data = priv; 1943 struct urtwn_softc *sc = data->sc; 1944 struct r92c_rx_stat *stat; 1945 uint32_t rxdw0; 1946 uint8_t *buf; 1947 int len, totlen, pktlen, infosz, npkts; 1948 1949 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 1950 device_xname(sc->sc_dev), __func__, status)); 1951 1952 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1953 if (status == USBD_STALLED) 1954 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1955 else if (status != USBD_CANCELLED) 1956 goto resubmit; 1957 return; 1958 } 1959 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1960 1961 if (__predict_false(len < (int)sizeof(*stat))) { 1962 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 1963 device_xname(sc->sc_dev), __func__, len)); 1964 goto resubmit; 1965 } 1966 buf = data->buf; 1967 1968 /* Get the number of encapsulated frames. */ 1969 stat = (struct r92c_rx_stat *)buf; 1970 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 1971 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 1972 device_xname(sc->sc_dev), __func__, npkts)); 1973 1974 /* Process all of them. */ 1975 while (npkts-- > 0) { 1976 if (__predict_false(len < (int)sizeof(*stat))) { 1977 DPRINTFN(DBG_RX, 1978 ("%s: %s: len(%d) is short than header\n", 1979 device_xname(sc->sc_dev), __func__, len)); 1980 break; 1981 } 1982 stat = (struct r92c_rx_stat *)buf; 1983 rxdw0 = le32toh(stat->rxdw0); 1984 1985 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1986 if (__predict_false(pktlen == 0)) { 1987 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 1988 device_xname(sc->sc_dev), __func__)); 1989 break; 1990 } 1991 1992 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1993 1994 /* Make sure everything fits in xfer. */ 1995 totlen = sizeof(*stat) + infosz + pktlen; 1996 if (__predict_false(totlen > len)) { 1997 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 1998 device_xname(sc->sc_dev), __func__, totlen, 1999 (int)sizeof(*stat), infosz, pktlen, len)); 2000 break; 2001 } 2002 2003 /* Process 802.11 frame. */ 2004 urtwn_rx_frame(sc, buf, pktlen); 2005 2006 /* Next chunk is 128-byte aligned. */ 2007 totlen = roundup2(totlen, 128); 2008 buf += totlen; 2009 len -= totlen; 2010 } 2011 2012 resubmit: 2013 /* Setup a new transfer. */ 2014 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 2015 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 2016 (void)usbd_transfer(xfer); 2017 } 2018 2019 static void 2020 urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 2021 { 2022 struct urtwn_tx_data *data = priv; 2023 struct urtwn_softc *sc = data->sc; 2024 struct ifnet *ifp = &sc->sc_if; 2025 int s; 2026 2027 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2028 device_xname(sc->sc_dev), __func__, status)); 2029 2030 mutex_enter(&sc->sc_tx_mtx); 2031 /* Put this Tx buffer back to our free list. */ 2032 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2033 mutex_exit(&sc->sc_tx_mtx); 2034 2035 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2036 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2037 if (status == USBD_STALLED) 2038 usbd_clear_endpoint_stall_async(data->pipe); 2039 ifp->if_oerrors++; 2040 } 2041 return; 2042 } 2043 2044 ifp->if_opackets++; 2045 2046 s = splnet(); 2047 sc->tx_timer = 0; 2048 ifp->if_flags &= ~IFF_OACTIVE; 2049 splx(s); 2050 2051 urtwn_start(ifp); 2052 } 2053 2054 static int 2055 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2056 { 2057 struct ieee80211com *ic = &sc->sc_ic; 2058 struct ieee80211_frame *wh; 2059 struct ieee80211_key *k = NULL; 2060 struct urtwn_tx_data *data; 2061 struct r92c_tx_desc *txd; 2062 usbd_pipe_handle pipe; 2063 uint16_t seq, sum; 2064 uint8_t raid, type, tid, qid; 2065 int i, s, hasqos, xferlen, padsize, error; 2066 2067 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2068 2069 wh = mtod(m, struct ieee80211_frame *); 2070 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2071 2072 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2073 k = ieee80211_crypto_encap(ic, ni, m); 2074 if (k == NULL) { 2075 m_freem(m); 2076 return (ENOBUFS); 2077 } 2078 /* packet header may have moved, reset our local pointer */ 2079 wh = mtod(m, struct ieee80211_frame *); 2080 } 2081 2082 if (__predict_false(sc->sc_drvbpf != NULL)) { 2083 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2084 2085 tap->wt_flags = 0; 2086 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2087 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2088 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2089 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2090 2091 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2092 } 2093 2094 if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { 2095 /* data frames in 11n mode */ 2096 struct ieee80211_qosframe *qwh = (void *)wh; 2097 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2098 qid = TID_TO_WME_AC(tid); 2099 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2100 /* Use AC_VO for management frames. */ 2101 qid = WME_AC_VO; 2102 tid = 0; /* compiler happy */ 2103 } else { 2104 /* non-qos data frames */ 2105 tid = R92C_TXDW1_QSEL_BE; 2106 qid = WME_AC_BE; 2107 } 2108 2109 /* Get the USB pipe to use for this AC. */ 2110 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 2111 2112 /* Grab a Tx buffer from our free list. */ 2113 mutex_enter(&sc->sc_tx_mtx); 2114 data = TAILQ_FIRST(&sc->tx_free_list); 2115 TAILQ_REMOVE(&sc->tx_free_list, data, next); 2116 mutex_exit(&sc->sc_tx_mtx); 2117 2118 if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2119 padsize = 8; 2120 else 2121 padsize = 0; 2122 2123 /* Fill Tx descriptor. */ 2124 txd = (struct r92c_tx_desc *)data->buf; 2125 memset(txd, 0, sizeof(*txd) + padsize); 2126 2127 txd->txdw0 |= htole32( 2128 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2129 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2130 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2131 2132 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2133 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2134 2135 /* fix pad field */ 2136 if (padsize > 0) { 2137 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", 2138 device_xname(sc->sc_dev), __func__, padsize)); 2139 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2140 } 2141 2142 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2143 type == IEEE80211_FC0_TYPE_DATA) { 2144 if (ic->ic_curmode == IEEE80211_MODE_11B) 2145 raid = R92C_RAID_11B; 2146 else 2147 raid = R92C_RAID_11BG; 2148 DPRINTFN(DBG_TX, 2149 ("%s: %s: data packet: tid=%d, raid=%d\n", 2150 device_xname(sc->sc_dev), __func__, tid, raid)); 2151 2152 txd->txdw1 |= htole32( 2153 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2154 SM(R92C_TXDW1_QSEL, tid) | 2155 SM(R92C_TXDW1_RAID, raid) | 2156 R92C_TXDW1_AGGBK); 2157 2158 if (hasqos) { 2159 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2160 } 2161 2162 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2163 /* for 11g */ 2164 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2165 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2166 R92C_TXDW4_HWRTSEN); 2167 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2168 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2169 R92C_TXDW4_HWRTSEN); 2170 } 2171 } 2172 /* Send RTS at OFDM24. */ 2173 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2174 txd->txdw5 |= htole32(0x0001ff00); 2175 /* Send data at OFDM54. */ 2176 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2177 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2178 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2179 device_xname(sc->sc_dev), __func__)); 2180 txd->txdw1 |= htole32( 2181 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 2182 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2183 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2184 2185 /* Force CCK1. */ 2186 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2187 /* Use 1Mbps */ 2188 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2189 } else { 2190 /* broadcast or multicast packets */ 2191 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2192 device_xname(sc->sc_dev), __func__)); 2193 txd->txdw1 |= htole32( 2194 SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | 2195 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2196 2197 /* Force CCK1. */ 2198 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2199 /* Use 1Mbps */ 2200 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2201 } 2202 2203 /* Set sequence number */ 2204 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2205 txd->txdseq |= htole16(seq); 2206 2207 if (!hasqos) { 2208 /* Use HW sequence numbering for non-QoS frames. */ 2209 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2210 txd->txdseq |= htole16(0x8000); /* WTF? */ 2211 } 2212 2213 /* Compute Tx descriptor checksum. */ 2214 sum = 0; 2215 for (i = 0; i < (int)sizeof(*txd) / 2; i++) 2216 sum ^= ((uint16_t *)txd)[i]; 2217 txd->txdsum = sum; /* NB: already little endian. */ 2218 2219 xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; 2220 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); 2221 m_freem(m); 2222 2223 s = splnet(); 2224 data->pipe = pipe; 2225 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 2226 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 2227 urtwn_txeof); 2228 error = usbd_transfer(data->xfer); 2229 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2230 error != USBD_IN_PROGRESS)) { 2231 splx(s); 2232 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2233 device_xname(sc->sc_dev), __func__, error)); 2234 mutex_enter(&sc->sc_tx_mtx); 2235 /* Put this Tx buffer back to our free list. */ 2236 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 2237 mutex_exit(&sc->sc_tx_mtx); 2238 return (error); 2239 } 2240 splx(s); 2241 ieee80211_free_node(ni); 2242 return (0); 2243 } 2244 2245 static void 2246 urtwn_start(struct ifnet *ifp) 2247 { 2248 struct urtwn_softc *sc = ifp->if_softc; 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 struct ether_header *eh; 2251 struct ieee80211_node *ni; 2252 struct mbuf *m; 2253 2254 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2255 2256 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2257 return; 2258 2259 for (;;) { 2260 mutex_enter(&sc->sc_tx_mtx); 2261 if (TAILQ_EMPTY(&sc->tx_free_list)) { 2262 mutex_exit(&sc->sc_tx_mtx); 2263 ifp->if_flags |= IFF_OACTIVE; 2264 break; 2265 } 2266 mutex_exit(&sc->sc_tx_mtx); 2267 2268 /* Send pending management frames first. */ 2269 IF_DEQUEUE(&ic->ic_mgtq, m); 2270 if (m != NULL) { 2271 ni = (void *)m->m_pkthdr.rcvif; 2272 m->m_pkthdr.rcvif = NULL; 2273 goto sendit; 2274 } 2275 if (ic->ic_state != IEEE80211_S_RUN) 2276 break; 2277 2278 /* Encapsulate and send data frames. */ 2279 IFQ_DEQUEUE(&ifp->if_snd, m); 2280 if (m == NULL) 2281 break; 2282 if (m->m_len < (int)sizeof(*eh) && 2283 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2284 ifp->if_oerrors++; 2285 continue; 2286 } 2287 eh = mtod(m, struct ether_header *); 2288 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2289 if (ni == NULL) { 2290 m_freem(m); 2291 ifp->if_oerrors++; 2292 continue; 2293 } 2294 2295 bpf_mtap(ifp, m); 2296 2297 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2298 ieee80211_free_node(ni); 2299 ifp->if_oerrors++; 2300 continue; 2301 } 2302 sendit: 2303 bpf_mtap3(ic->ic_rawbpf, m); 2304 2305 if (urtwn_tx(sc, m, ni) != 0) { 2306 ieee80211_free_node(ni); 2307 ifp->if_oerrors++; 2308 continue; 2309 } 2310 2311 sc->tx_timer = 5; 2312 ifp->if_timer = 1; 2313 } 2314 } 2315 2316 static void 2317 urtwn_watchdog(struct ifnet *ifp) 2318 { 2319 struct urtwn_softc *sc = ifp->if_softc; 2320 2321 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2322 2323 ifp->if_timer = 0; 2324 2325 if (sc->tx_timer > 0) { 2326 if (--sc->tx_timer == 0) { 2327 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2328 /* urtwn_init(ifp); XXX needs a process context! */ 2329 ifp->if_oerrors++; 2330 return; 2331 } 2332 ifp->if_timer = 1; 2333 } 2334 ieee80211_watchdog(&sc->sc_ic); 2335 } 2336 2337 static int 2338 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2339 { 2340 struct urtwn_softc *sc = ifp->if_softc; 2341 struct ieee80211com *ic = &sc->sc_ic; 2342 struct ifaddr *ifa; 2343 int s, error = 0; 2344 2345 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2346 device_xname(sc->sc_dev), __func__, cmd, data)); 2347 2348 s = splnet(); 2349 2350 switch (cmd) { 2351 case SIOCSIFADDR: 2352 ifa = (struct ifaddr *)data; 2353 ifp->if_flags |= IFF_UP; 2354 #ifdef INET 2355 if (ifa->ifa_addr->sa_family == AF_INET) 2356 arp_ifinit(&ic->ic_ac, ifa); 2357 #endif 2358 /*FALLTHROUGH*/ 2359 case SIOCSIFFLAGS: 2360 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2361 break; 2362 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2363 case IFF_UP|IFF_RUNNING: 2364 break; 2365 case IFF_UP: 2366 urtwn_init(ifp); 2367 break; 2368 case IFF_RUNNING: 2369 urtwn_stop(ifp, 1); 2370 break; 2371 case 0: 2372 break; 2373 } 2374 break; 2375 2376 case SIOCADDMULTI: 2377 case SIOCDELMULTI: 2378 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2379 /* setup multicast filter, etc */ 2380 error = 0; 2381 } 2382 break; 2383 2384 case SIOCS80211CHANNEL: 2385 error = ieee80211_ioctl(ic, cmd, data); 2386 if (error == ENETRESET && 2387 ic->ic_opmode == IEEE80211_M_MONITOR) { 2388 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2389 (IFF_UP | IFF_RUNNING)) { 2390 urtwn_set_chan(sc, ic->ic_ibss_chan, 2391 IEEE80211_HTINFO_2NDCHAN_NONE); 2392 } 2393 error = 0; 2394 } 2395 break; 2396 2397 default: 2398 error = ieee80211_ioctl(ic, cmd, data); 2399 break; 2400 } 2401 if (error == ENETRESET) { 2402 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2403 (IFF_UP | IFF_RUNNING)) { 2404 urtwn_init(ifp); 2405 } 2406 error = 0; 2407 } 2408 2409 splx(s); 2410 2411 return (error); 2412 } 2413 2414 static int 2415 urtwn_power_on(struct urtwn_softc *sc) 2416 { 2417 uint32_t reg; 2418 int ntries; 2419 2420 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2421 2422 /* Wait for autoload done bit. */ 2423 for (ntries = 0; ntries < 1000; ntries++) { 2424 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2425 break; 2426 DELAY(5); 2427 } 2428 if (ntries == 1000) { 2429 aprint_error_dev(sc->sc_dev, 2430 "timeout waiting for chip autoload\n"); 2431 return (ETIMEDOUT); 2432 } 2433 2434 /* Unlock ISO/CLK/Power control register. */ 2435 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2436 /* Move SPS into PWM mode. */ 2437 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2438 DELAY(100); 2439 2440 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2441 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2442 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2443 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2444 DELAY(100); 2445 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2446 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2447 ~R92C_SYS_ISO_CTRL_MD2PP); 2448 } 2449 2450 /* Auto enable WLAN. */ 2451 urtwn_write_2(sc, R92C_APS_FSMCO, 2452 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2453 for (ntries = 0; ntries < 1000; ntries++) { 2454 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2455 R92C_APS_FSMCO_APFM_ONMAC)) 2456 break; 2457 DELAY(5); 2458 } 2459 if (ntries == 1000) { 2460 aprint_error_dev(sc->sc_dev, 2461 "timeout waiting for MAC auto ON\n"); 2462 return (ETIMEDOUT); 2463 } 2464 2465 /* Enable radio, GPIO and LED functions. */ 2466 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 2467 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 2468 urtwn_write_2(sc, R92C_APS_FSMCO, 2469 R92C_APS_FSMCO_AFSM_HSUS | 2470 R92C_APS_FSMCO_PDN_EN | 2471 R92C_APS_FSMCO_PFM_ALDN); 2472 2473 /* Release RF digital isolation. */ 2474 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2475 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2476 2477 /* Initialize MAC. */ 2478 urtwn_write_1(sc, R92C_APSD_CTRL, 2479 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2480 for (ntries = 0; ntries < 200; ntries++) { 2481 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2482 R92C_APSD_CTRL_OFF_STATUS)) 2483 break; 2484 DELAY(5); 2485 } 2486 if (ntries == 200) { 2487 aprint_error_dev(sc->sc_dev, 2488 "timeout waiting for MAC initialization\n"); 2489 return (ETIMEDOUT); 2490 } 2491 2492 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2493 reg = urtwn_read_2(sc, R92C_CR); 2494 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2495 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2496 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2497 R92C_CR_ENSEC; 2498 urtwn_write_2(sc, R92C_CR, reg); 2499 2500 urtwn_write_1(sc, 0xfe10, 0x19); 2501 return (0); 2502 } 2503 2504 static int 2505 urtwn_llt_init(struct urtwn_softc *sc) 2506 { 2507 int i, error; 2508 2509 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2510 2511 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2512 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2513 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2514 return (error); 2515 } 2516 /* NB: 0xff indicates end-of-list. */ 2517 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2518 return (error); 2519 /* 2520 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2521 * as ring buffer. 2522 */ 2523 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2524 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2525 return (error); 2526 } 2527 /* Make the last page point to the beginning of the ring buffer. */ 2528 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2529 return (error); 2530 } 2531 2532 static void 2533 urtwn_fw_reset(struct urtwn_softc *sc) 2534 { 2535 uint16_t reg; 2536 int ntries; 2537 2538 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2539 2540 /* Tell 8051 to reset itself. */ 2541 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2542 2543 /* Wait until 8051 resets by itself. */ 2544 for (ntries = 0; ntries < 100; ntries++) { 2545 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2546 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2547 return; 2548 DELAY(50); 2549 } 2550 /* Force 8051 reset. */ 2551 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2552 } 2553 2554 static int 2555 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 2556 { 2557 uint32_t reg; 2558 int off, mlen, error = 0; 2559 2560 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 2561 device_xname(sc->sc_dev), __func__, page, buf, len)); 2562 2563 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2564 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2565 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2566 2567 off = R92C_FW_START_ADDR; 2568 while (len > 0) { 2569 if (len > 196) 2570 mlen = 196; 2571 else if (len > 4) 2572 mlen = 4; 2573 else 2574 mlen = 1; 2575 error = urtwn_write_region(sc, off, buf, mlen); 2576 if (error != 0) 2577 break; 2578 off += mlen; 2579 buf += mlen; 2580 len -= mlen; 2581 } 2582 return (error); 2583 } 2584 2585 static int 2586 urtwn_load_firmware(struct urtwn_softc *sc) 2587 { 2588 firmware_handle_t fwh; 2589 const struct r92c_fw_hdr *hdr; 2590 const char *name; 2591 u_char *fw, *ptr; 2592 size_t len; 2593 uint32_t reg; 2594 int mlen, ntries, page, error; 2595 2596 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2597 2598 /* Read firmware image from the filesystem. */ 2599 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2600 URTWN_CHIP_UMC_A_CUT) 2601 name = "rtl8192cfwU.bin"; 2602 else 2603 name = "rtl8192cfw.bin"; 2604 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 2605 aprint_error_dev(sc->sc_dev, 2606 "failed loadfirmware of file %s (error %d)\n", name, error); 2607 return (error); 2608 } 2609 len = firmware_get_size(fwh); 2610 fw = firmware_malloc(len); 2611 if (fw == NULL) { 2612 aprint_error_dev(sc->sc_dev, 2613 "failed to allocate firmware memory\n"); 2614 firmware_close(fwh); 2615 return (ENOMEM); 2616 } 2617 error = firmware_read(fwh, 0, fw, len); 2618 firmware_close(fwh); 2619 if (error != 0) { 2620 aprint_error_dev(sc->sc_dev, 2621 "failed to read firmware (error %d)\n", error); 2622 firmware_free(fw, 0); 2623 return (error); 2624 } 2625 2626 ptr = fw; 2627 hdr = (const struct r92c_fw_hdr *)ptr; 2628 /* Check if there is a valid FW header and skip it. */ 2629 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2630 (le16toh(hdr->signature) >> 4) == 0x92c) { 2631 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 2632 device_xname(sc->sc_dev), __func__, 2633 le16toh(hdr->version), le16toh(hdr->subversion), 2634 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2635 ptr += sizeof(*hdr); 2636 len -= sizeof(*hdr); 2637 } 2638 2639 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2640 urtwn_fw_reset(sc); 2641 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2642 } 2643 2644 /* download enabled */ 2645 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2646 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2647 R92C_SYS_FUNC_EN_CPUEN); 2648 urtwn_write_1(sc, R92C_MCUFWDL, 2649 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2650 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2651 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2652 2653 /* download firmware */ 2654 for (page = 0; len > 0; page++) { 2655 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2656 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2657 if (error != 0) { 2658 aprint_error_dev(sc->sc_dev, 2659 "could not load firmware page %d\n", page); 2660 goto fail; 2661 } 2662 ptr += mlen; 2663 len -= mlen; 2664 } 2665 2666 /* download disable */ 2667 urtwn_write_1(sc, R92C_MCUFWDL, 2668 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2669 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2670 2671 /* Wait for checksum report. */ 2672 for (ntries = 0; ntries < 1000; ntries++) { 2673 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2674 break; 2675 DELAY(5); 2676 } 2677 if (ntries == 1000) { 2678 aprint_error_dev(sc->sc_dev, 2679 "timeout waiting for checksum report\n"); 2680 error = ETIMEDOUT; 2681 goto fail; 2682 } 2683 2684 /* Wait for firmware readiness. */ 2685 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2686 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2687 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2688 for (ntries = 0; ntries < 1000; ntries++) { 2689 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2690 break; 2691 DELAY(5); 2692 } 2693 if (ntries == 1000) { 2694 aprint_error_dev(sc->sc_dev, 2695 "timeout waiting for firmware readiness\n"); 2696 error = ETIMEDOUT; 2697 goto fail; 2698 } 2699 fail: 2700 firmware_free(fw, 0); 2701 return (error); 2702 } 2703 2704 static int 2705 urtwn_dma_init(struct urtwn_softc *sc) 2706 { 2707 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2708 uint32_t reg; 2709 int error; 2710 2711 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2712 2713 /* Initialize LLT table. */ 2714 error = urtwn_llt_init(sc); 2715 if (error != 0) 2716 return (error); 2717 2718 /* Get Tx queues to USB endpoints mapping. */ 2719 hashq = hasnq = haslq = 0; 2720 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2721 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 2722 device_xname(sc->sc_dev), __func__, reg)); 2723 if (MS(reg, R92C_USB_EP_HQ) != 0) 2724 hashq = 1; 2725 if (MS(reg, R92C_USB_EP_NQ) != 0) 2726 hasnq = 1; 2727 if (MS(reg, R92C_USB_EP_LQ) != 0) 2728 haslq = 1; 2729 nqueues = hashq + hasnq + haslq; 2730 if (nqueues == 0) 2731 return (EIO); 2732 /* Get the number of pages for each queue. */ 2733 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2734 /* The remaining pages are assigned to the high priority queue. */ 2735 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2736 2737 /* Set number of pages for normal priority queue. */ 2738 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2739 urtwn_write_4(sc, R92C_RQPN, 2740 /* Set number of pages for public queue. */ 2741 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2742 /* Set number of pages for high priority queue. */ 2743 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2744 /* Set number of pages for low priority queue. */ 2745 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2746 /* Load values. */ 2747 R92C_RQPN_LD); 2748 2749 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2750 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2751 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2752 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2753 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2754 2755 /* Set queue to USB pipe mapping. */ 2756 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2757 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2758 if (nqueues == 1) { 2759 if (hashq) { 2760 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2761 } else if (hasnq) { 2762 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2763 } else { 2764 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2765 } 2766 } else if (nqueues == 2) { 2767 /* All 2-endpoints configs have a high priority queue. */ 2768 if (!hashq) { 2769 return (EIO); 2770 } 2771 if (hasnq) { 2772 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2773 } else { 2774 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2775 } 2776 } else { 2777 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2778 } 2779 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2780 2781 /* Set Tx/Rx transfer page boundary. */ 2782 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2783 2784 /* Set Tx/Rx transfer page size. */ 2785 urtwn_write_1(sc, R92C_PBP, 2786 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 2787 return (0); 2788 } 2789 2790 static void 2791 urtwn_mac_init(struct urtwn_softc *sc) 2792 { 2793 int i; 2794 2795 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2796 2797 /* Write MAC initialization values. */ 2798 for (i = 0; i < (int)__arraycount(rtl8192cu_mac); i++) 2799 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2800 } 2801 2802 static void 2803 urtwn_bb_init(struct urtwn_softc *sc) 2804 { 2805 const struct urtwn_bb_prog *prog; 2806 uint32_t reg; 2807 int i; 2808 2809 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2810 2811 /* Enable BB and RF. */ 2812 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2813 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2814 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2815 R92C_SYS_FUNC_EN_DIO_RF); 2816 2817 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 2818 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 2819 2820 urtwn_write_1(sc, R92C_RF_CTRL, 2821 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2822 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2823 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2824 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2825 2826 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2827 urtwn_write_1(sc, 0x15, 0xe9); 2828 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2829 2830 /* Select BB programming based on board type. */ 2831 if (!(sc->chip & URTWN_CHIP_92C)) { 2832 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2833 prog = &rtl8188ce_bb_prog; 2834 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2835 prog = &rtl8188ru_bb_prog; 2836 } else { 2837 prog = &rtl8188cu_bb_prog; 2838 } 2839 } else { 2840 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2841 prog = &rtl8192ce_bb_prog; 2842 } else { 2843 prog = &rtl8192cu_bb_prog; 2844 } 2845 } 2846 /* Write BB initialization values. */ 2847 for (i = 0; i < prog->count; i++) { 2848 /* additional delay depend on registers */ 2849 switch (prog->regs[i]) { 2850 case 0xfe: 2851 usbd_delay_ms(sc->sc_udev, 50); 2852 break; 2853 case 0xfd: 2854 usbd_delay_ms(sc->sc_udev, 5); 2855 break; 2856 case 0xfc: 2857 usbd_delay_ms(sc->sc_udev, 1); 2858 break; 2859 case 0xfb: 2860 DELAY(50); 2861 break; 2862 case 0xfa: 2863 DELAY(5); 2864 break; 2865 case 0xf9: 2866 DELAY(1); 2867 break; 2868 } 2869 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2870 DELAY(1); 2871 } 2872 2873 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2874 /* 8192C 1T only configuration. */ 2875 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2876 reg = (reg & ~0x00000003) | 0x2; 2877 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2878 2879 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2880 reg = (reg & ~0x00300033) | 0x00200022; 2881 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2882 2883 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2884 reg = (reg & ~0xff000000) | (0x45 << 24); 2885 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2886 2887 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2888 reg = (reg & ~0x000000ff) | 0x23; 2889 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2890 2891 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2892 reg = (reg & ~0x00000030) | (1 << 4); 2893 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2894 2895 reg = urtwn_bb_read(sc, 0xe74); 2896 reg = (reg & ~0x0c000000) | (2 << 26); 2897 urtwn_bb_write(sc, 0xe74, reg); 2898 reg = urtwn_bb_read(sc, 0xe78); 2899 reg = (reg & ~0x0c000000) | (2 << 26); 2900 urtwn_bb_write(sc, 0xe78, reg); 2901 reg = urtwn_bb_read(sc, 0xe7c); 2902 reg = (reg & ~0x0c000000) | (2 << 26); 2903 urtwn_bb_write(sc, 0xe7c, reg); 2904 reg = urtwn_bb_read(sc, 0xe80); 2905 reg = (reg & ~0x0c000000) | (2 << 26); 2906 urtwn_bb_write(sc, 0xe80, reg); 2907 reg = urtwn_bb_read(sc, 0xe88); 2908 reg = (reg & ~0x0c000000) | (2 << 26); 2909 urtwn_bb_write(sc, 0xe88, reg); 2910 } 2911 2912 /* Write AGC values. */ 2913 for (i = 0; i < prog->agccount; i++) { 2914 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 2915 DELAY(1); 2916 } 2917 2918 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2919 R92C_HSSI_PARAM2_CCK_HIPWR) { 2920 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 2921 } 2922 } 2923 2924 static void 2925 urtwn_rf_init(struct urtwn_softc *sc) 2926 { 2927 const struct urtwn_rf_prog *prog; 2928 uint32_t reg, mask, saved; 2929 int i, j, idx; 2930 2931 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2932 2933 /* Select RF programming based on board type. */ 2934 if (!(sc->chip & URTWN_CHIP_92C)) { 2935 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 2936 prog = rtl8188ce_rf_prog; 2937 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 2938 prog = rtl8188ru_rf_prog; 2939 } else { 2940 prog = rtl8188cu_rf_prog; 2941 } 2942 } else { 2943 prog = rtl8192ce_rf_prog; 2944 } 2945 2946 for (i = 0; i < sc->nrxchains; i++) { 2947 /* Save RF_ENV control type. */ 2948 idx = i / 2; 2949 mask = 0xffffU << ((i % 2) * 16); 2950 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 2951 2952 /* Set RF_ENV enable. */ 2953 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2954 reg |= 0x100000; 2955 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2956 DELAY(1); 2957 2958 /* Set RF_ENV output high. */ 2959 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2960 reg |= 0x10; 2961 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2962 DELAY(1); 2963 2964 /* Set address and data lengths of RF registers. */ 2965 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2966 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2967 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2968 DELAY(1); 2969 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2970 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2971 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2972 DELAY(1); 2973 2974 /* Write RF initialization values for this chain. */ 2975 for (j = 0; j < prog[i].count; j++) { 2976 if (prog[i].regs[j] >= 0xf9 && 2977 prog[i].regs[j] <= 0xfe) { 2978 /* 2979 * These are fake RF registers offsets that 2980 * indicate a delay is required. 2981 */ 2982 usbd_delay_ms(sc->sc_udev, 50); 2983 continue; 2984 } 2985 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 2986 DELAY(1); 2987 } 2988 2989 /* Restore RF_ENV control type. */ 2990 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 2991 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 2992 } 2993 2994 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2995 URTWN_CHIP_UMC_A_CUT) { 2996 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2997 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2998 } 2999 3000 /* Cache RF register CHNLBW. */ 3001 for (i = 0; i < 2; i++) { 3002 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3003 } 3004 } 3005 3006 static void 3007 urtwn_cam_init(struct urtwn_softc *sc) 3008 { 3009 uint32_t content, command; 3010 uint8_t idx; 3011 int i; 3012 3013 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3014 3015 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3016 content = (idx & 3) 3017 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3018 | R92C_CAM_VALID; 3019 3020 command = R92C_CAMCMD_POLLING 3021 | R92C_CAMCMD_WRITE 3022 | R92C_CAM_CTL0(idx); 3023 3024 urtwn_write_4(sc, R92C_CAMWRITE, content); 3025 urtwn_write_4(sc, R92C_CAMCMD, command); 3026 } 3027 3028 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3029 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3030 if (i == 0) { 3031 content = (idx & 3) 3032 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3033 | R92C_CAM_VALID; 3034 } else { 3035 content = 0; 3036 } 3037 3038 command = R92C_CAMCMD_POLLING 3039 | R92C_CAMCMD_WRITE 3040 | R92C_CAM_CTL0(idx) 3041 | (u_int)i; 3042 3043 urtwn_write_4(sc, R92C_CAMWRITE, content); 3044 urtwn_write_4(sc, R92C_CAMCMD, command); 3045 } 3046 } 3047 3048 /* Invalidate all CAM entries. */ 3049 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3050 } 3051 3052 static void 3053 urtwn_pa_bias_init(struct urtwn_softc *sc) 3054 { 3055 uint8_t reg; 3056 int i; 3057 3058 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3059 3060 for (i = 0; i < sc->nrxchains; i++) { 3061 if (sc->pa_setting & (1U << i)) 3062 continue; 3063 3064 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3065 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3066 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3067 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3068 } 3069 if (!(sc->pa_setting & 0x10)) { 3070 reg = urtwn_read_1(sc, 0x16); 3071 reg = (reg & ~0xf0) | 0x90; 3072 urtwn_write_1(sc, 0x16, reg); 3073 } 3074 } 3075 3076 static void 3077 urtwn_rxfilter_init(struct urtwn_softc *sc) 3078 { 3079 3080 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3081 3082 /* Initialize Rx filter. */ 3083 /* TODO: use better filter for monitor mode. */ 3084 urtwn_write_4(sc, R92C_RCR, 3085 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 3086 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 3087 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 3088 /* Accept all multicast frames. */ 3089 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3090 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3091 /* Accept all management frames. */ 3092 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 3093 /* Reject all control frames. */ 3094 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3095 /* Accept all data frames. */ 3096 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 3097 } 3098 3099 static void 3100 urtwn_edca_init(struct urtwn_softc *sc) 3101 { 3102 3103 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3104 3105 /* set spec SIFS (used in NAV) */ 3106 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3107 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3108 3109 /* set SIFS CCK/OFDM */ 3110 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3111 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3112 3113 /* TXOP */ 3114 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3115 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3116 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3117 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3118 } 3119 3120 static void 3121 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3122 uint16_t power[URTWN_RIDX_COUNT]) 3123 { 3124 uint32_t reg; 3125 3126 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 3127 __func__, chain)); 3128 3129 /* Write per-CCK rate Tx power. */ 3130 if (chain == 0) { 3131 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3132 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3133 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3134 3135 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3136 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3137 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3138 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3139 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3140 } else { 3141 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3142 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3143 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3144 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3145 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3146 3147 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3148 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3149 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3150 } 3151 /* Write per-OFDM rate Tx power. */ 3152 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3153 SM(R92C_TXAGC_RATE06, power[ 4]) | 3154 SM(R92C_TXAGC_RATE09, power[ 5]) | 3155 SM(R92C_TXAGC_RATE12, power[ 6]) | 3156 SM(R92C_TXAGC_RATE18, power[ 7])); 3157 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3158 SM(R92C_TXAGC_RATE24, power[ 8]) | 3159 SM(R92C_TXAGC_RATE36, power[ 9]) | 3160 SM(R92C_TXAGC_RATE48, power[10]) | 3161 SM(R92C_TXAGC_RATE54, power[11])); 3162 /* Write per-MCS Tx power. */ 3163 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3164 SM(R92C_TXAGC_MCS00, power[12]) | 3165 SM(R92C_TXAGC_MCS01, power[13]) | 3166 SM(R92C_TXAGC_MCS02, power[14]) | 3167 SM(R92C_TXAGC_MCS03, power[15])); 3168 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3169 SM(R92C_TXAGC_MCS04, power[16]) | 3170 SM(R92C_TXAGC_MCS05, power[17]) | 3171 SM(R92C_TXAGC_MCS06, power[18]) | 3172 SM(R92C_TXAGC_MCS07, power[19])); 3173 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3174 SM(R92C_TXAGC_MCS08, power[20]) | 3175 SM(R92C_TXAGC_MCS09, power[21]) | 3176 SM(R92C_TXAGC_MCS10, power[22]) | 3177 SM(R92C_TXAGC_MCS11, power[23])); 3178 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3179 SM(R92C_TXAGC_MCS12, power[24]) | 3180 SM(R92C_TXAGC_MCS13, power[25]) | 3181 SM(R92C_TXAGC_MCS14, power[26]) | 3182 SM(R92C_TXAGC_MCS15, power[27])); 3183 } 3184 3185 static void 3186 urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, 3187 uint16_t power[URTWN_RIDX_COUNT]) 3188 { 3189 struct r92c_rom *rom = &sc->rom; 3190 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 3191 const struct urtwn_txpwr *base; 3192 int ridx, group; 3193 3194 DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", 3195 device_xname(sc->sc_dev), __func__, chain, chan)); 3196 3197 /* Determine channel group. */ 3198 if (chan <= 3) { 3199 group = 0; 3200 } else if (chan <= 9) { 3201 group = 1; 3202 } else { 3203 group = 2; 3204 } 3205 3206 /* Get original Tx power based on board type and RF chain. */ 3207 if (!(sc->chip & URTWN_CHIP_92C)) { 3208 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3209 base = &rtl8188ru_txagc[chain]; 3210 } else { 3211 base = &rtl8192cu_txagc[chain]; 3212 } 3213 } else { 3214 base = &rtl8192cu_txagc[chain]; 3215 } 3216 3217 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3218 if (sc->regulatory == 0) { 3219 for (ridx = 0; ridx <= 3; ridx++) { 3220 power[ridx] = base->pwr[0][ridx]; 3221 } 3222 } 3223 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3224 if (sc->regulatory == 3) { 3225 power[ridx] = base->pwr[0][ridx]; 3226 /* Apply vendor limits. */ 3227 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 3228 maxpow = rom->ht40_max_pwr[group]; 3229 } else { 3230 maxpow = rom->ht20_max_pwr[group]; 3231 } 3232 maxpow = (maxpow >> (chain * 4)) & 0xf; 3233 if (power[ridx] > maxpow) { 3234 power[ridx] = maxpow; 3235 } 3236 } else if (sc->regulatory == 1) { 3237 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3238 power[ridx] = base->pwr[group][ridx]; 3239 } 3240 } else if (sc->regulatory != 2) { 3241 power[ridx] = base->pwr[0][ridx]; 3242 } 3243 } 3244 3245 /* Compute per-CCK rate Tx power. */ 3246 cckpow = rom->cck_tx_pwr[chain][group]; 3247 for (ridx = 0; ridx <= 3; ridx++) { 3248 power[ridx] += cckpow; 3249 if (power[ridx] > R92C_MAX_TX_PWR) { 3250 power[ridx] = R92C_MAX_TX_PWR; 3251 } 3252 } 3253 3254 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3255 if (sc->ntxchains > 1) { 3256 /* Apply reduction for 2 spatial streams. */ 3257 diff = rom->ht40_2s_tx_pwr_diff[group]; 3258 diff = (diff >> (chain * 4)) & 0xf; 3259 htpow = (htpow > diff) ? htpow - diff : 0; 3260 } 3261 3262 /* Compute per-OFDM rate Tx power. */ 3263 diff = rom->ofdm_tx_pwr_diff[group]; 3264 diff = (diff >> (chain * 4)) & 0xf; 3265 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3266 for (ridx = 4; ridx <= 11; ridx++) { 3267 power[ridx] += ofdmpow; 3268 if (power[ridx] > R92C_MAX_TX_PWR) { 3269 power[ridx] = R92C_MAX_TX_PWR; 3270 } 3271 } 3272 3273 /* Compute per-MCS Tx power. */ 3274 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 3275 diff = rom->ht20_tx_pwr_diff[group]; 3276 diff = (diff >> (chain * 4)) & 0xf; 3277 htpow += diff; /* HT40->HT20 correction. */ 3278 } 3279 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 3280 power[ridx] += htpow; 3281 if (power[ridx] > R92C_MAX_TX_PWR) { 3282 power[ridx] = R92C_MAX_TX_PWR; 3283 } 3284 } 3285 #ifdef URTWN_DEBUG 3286 if (urtwn_debug & DBG_RF) { 3287 /* Dump per-rate Tx power values. */ 3288 printf("%s: %s: Tx power for chain %d:\n", 3289 device_xname(sc->sc_dev), __func__, chain); 3290 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 3291 printf("%s: %s: Rate %d = %u\n", 3292 device_xname(sc->sc_dev), __func__, ridx, 3293 power[ridx]); 3294 } 3295 } 3296 #endif 3297 } 3298 3299 static void 3300 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 3301 { 3302 uint16_t power[URTWN_RIDX_COUNT]; 3303 int i; 3304 3305 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3306 3307 for (i = 0; i < sc->ntxchains; i++) { 3308 /* Compute per-rate Tx power values. */ 3309 urtwn_get_txpower(sc, i, chan, ht40m, power); 3310 /* Write per-rate Tx power values to hardware. */ 3311 urtwn_write_txpower(sc, i, power); 3312 } 3313 } 3314 3315 static void 3316 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 3317 { 3318 struct ieee80211com *ic = &sc->sc_ic; 3319 u_int chan; 3320 int i; 3321 3322 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3323 3324 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 3325 __func__, chan)); 3326 3327 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 3328 chan += 2; 3329 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 3330 chan -= 2; 3331 } 3332 3333 /* Set Tx power for this new channel. */ 3334 urtwn_set_txpower(sc, chan, ht40m); 3335 3336 for (i = 0; i < sc->nrxchains; i++) { 3337 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3338 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3339 } 3340 3341 if (ht40m) { 3342 /* Is secondary channel below or above primary? */ 3343 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 3344 uint32_t reg; 3345 3346 urtwn_write_1(sc, R92C_BWOPMODE, 3347 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3348 3349 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3350 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3351 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 3352 3353 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3354 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3355 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3356 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3357 3358 /* Set CCK side band. */ 3359 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3360 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3361 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3362 3363 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3364 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3365 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3366 3367 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3368 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3369 ~R92C_FPGA0_ANAPARAM2_CBW20); 3370 3371 reg = urtwn_bb_read(sc, 0x818); 3372 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3373 urtwn_bb_write(sc, 0x818, reg); 3374 3375 /* Select 40MHz bandwidth. */ 3376 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3377 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3378 } else { 3379 urtwn_write_1(sc, R92C_BWOPMODE, 3380 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3381 3382 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3383 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3384 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3385 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3386 3387 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3388 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3389 R92C_FPGA0_ANAPARAM2_CBW20); 3390 3391 /* Select 20MHz bandwidth. */ 3392 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3393 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3394 } 3395 } 3396 3397 static void 3398 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 3399 { 3400 3401 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 3402 __func__, inited)); 3403 3404 /* TODO */ 3405 } 3406 3407 static void 3408 urtwn_lc_calib(struct urtwn_softc *sc) 3409 { 3410 uint32_t rf_ac[2]; 3411 uint8_t txmode; 3412 int i; 3413 3414 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3415 3416 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3417 if ((txmode & 0x70) != 0) { 3418 /* Disable all continuous Tx. */ 3419 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3420 3421 /* Set RF mode to standby mode. */ 3422 for (i = 0; i < sc->nrxchains; i++) { 3423 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3424 urtwn_rf_write(sc, i, R92C_RF_AC, 3425 RW(rf_ac[i], R92C_RF_AC_MODE, 3426 R92C_RF_AC_MODE_STANDBY)); 3427 } 3428 } else { 3429 /* Block all Tx queues. */ 3430 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3431 } 3432 /* Start calibration. */ 3433 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3434 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3435 3436 /* Give calibration the time to complete. */ 3437 usbd_delay_ms(sc->sc_udev, 100); 3438 3439 /* Restore configuration. */ 3440 if ((txmode & 0x70) != 0) { 3441 /* Restore Tx mode. */ 3442 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3443 /* Restore RF mode. */ 3444 for (i = 0; i < sc->nrxchains; i++) { 3445 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3446 } 3447 } else { 3448 /* Unblock all Tx queues. */ 3449 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3450 } 3451 } 3452 3453 static void 3454 urtwn_temp_calib(struct urtwn_softc *sc) 3455 { 3456 int temp; 3457 3458 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3459 3460 if (sc->thcal_state == 0) { 3461 /* Start measuring temperature. */ 3462 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 3463 device_xname(sc->sc_dev), __func__)); 3464 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3465 sc->thcal_state = 1; 3466 return; 3467 } 3468 sc->thcal_state = 0; 3469 3470 /* Read measured temperature. */ 3471 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3472 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 3473 __func__, temp)); 3474 if (temp == 0) /* Read failed, skip. */ 3475 return; 3476 3477 /* 3478 * Redo LC calibration if temperature changed significantly since 3479 * last calibration. 3480 */ 3481 if (sc->thcal_lctemp == 0) { 3482 /* First LC calibration is performed in urtwn_init(). */ 3483 sc->thcal_lctemp = temp; 3484 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3485 DPRINTFN(DBG_RF, 3486 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 3487 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 3488 temp)); 3489 urtwn_lc_calib(sc); 3490 /* Record temperature of last LC calibration. */ 3491 sc->thcal_lctemp = temp; 3492 } 3493 } 3494 3495 static int 3496 urtwn_init(struct ifnet *ifp) 3497 { 3498 struct urtwn_softc *sc = ifp->if_softc; 3499 struct ieee80211com *ic = &sc->sc_ic; 3500 struct urtwn_rx_data *data; 3501 uint32_t reg; 3502 int i, error; 3503 3504 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3505 3506 urtwn_stop(ifp, 0); 3507 3508 mutex_enter(&sc->sc_task_mtx); 3509 /* Init host async commands ring. */ 3510 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 3511 mutex_exit(&sc->sc_task_mtx); 3512 3513 mutex_enter(&sc->sc_fwcmd_mtx); 3514 /* Init firmware commands ring. */ 3515 sc->fwcur = 0; 3516 mutex_exit(&sc->sc_fwcmd_mtx); 3517 3518 /* Allocate Tx/Rx buffers. */ 3519 error = urtwn_alloc_rx_list(sc); 3520 if (error != 0) { 3521 aprint_error_dev(sc->sc_dev, 3522 "could not allocate Rx buffers\n"); 3523 goto fail; 3524 } 3525 error = urtwn_alloc_tx_list(sc); 3526 if (error != 0) { 3527 aprint_error_dev(sc->sc_dev, 3528 "could not allocate Tx buffers\n"); 3529 goto fail; 3530 } 3531 3532 /* Power on adapter. */ 3533 error = urtwn_power_on(sc); 3534 if (error != 0) 3535 goto fail; 3536 3537 /* Initialize DMA. */ 3538 error = urtwn_dma_init(sc); 3539 if (error != 0) 3540 goto fail; 3541 3542 /* Set info size in Rx descriptors (in 64-bit words). */ 3543 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3544 3545 /* Init interrupts. */ 3546 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3547 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3548 3549 /* Set MAC address. */ 3550 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3551 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 3552 3553 /* Set initial network type. */ 3554 reg = urtwn_read_4(sc, R92C_CR); 3555 switch (ic->ic_opmode) { 3556 case IEEE80211_M_STA: 3557 default: 3558 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3559 break; 3560 3561 case IEEE80211_M_IBSS: 3562 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 3563 break; 3564 } 3565 urtwn_write_4(sc, R92C_CR, reg); 3566 3567 urtwn_rxfilter_init(sc); 3568 3569 /* Set response rate */ 3570 reg = urtwn_read_4(sc, R92C_RRSR); 3571 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3572 urtwn_write_4(sc, R92C_RRSR, reg); 3573 3574 /* SIFS (used in NAV) */ 3575 urtwn_write_2(sc, R92C_SPEC_SIFS, 3576 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 3577 3578 /* Set short/long retry limits. */ 3579 urtwn_write_2(sc, R92C_RL, 3580 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3581 3582 /* Initialize EDCA parameters. */ 3583 urtwn_edca_init(sc); 3584 3585 /* Setup rate fallback. */ 3586 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3587 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3588 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3589 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3590 3591 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3592 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3593 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3594 /* Set ACK timeout. */ 3595 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3596 3597 /* Setup USB aggregation. */ 3598 /* Tx */ 3599 reg = urtwn_read_4(sc, R92C_TDECTRL); 3600 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3601 urtwn_write_4(sc, R92C_TDECTRL, reg); 3602 /* Rx */ 3603 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3604 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3605 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3606 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3607 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3608 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 3609 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3610 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3611 3612 /* Initialize beacon parameters. */ 3613 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3614 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3615 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3616 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3617 3618 /* Setup AMPDU aggregation. */ 3619 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3620 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3621 urtwn_write_2(sc, 0x4ca, 0x0708); 3622 3623 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3624 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3625 3626 /* Load 8051 microcode. */ 3627 error = urtwn_load_firmware(sc); 3628 if (error != 0) 3629 goto fail; 3630 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 3631 3632 /* Initialize MAC/BB/RF blocks. */ 3633 urtwn_mac_init(sc); 3634 urtwn_write_4(sc, R92C_RCR, 3635 urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); 3636 urtwn_bb_init(sc); 3637 urtwn_rf_init(sc); 3638 3639 /* Turn CCK and OFDM blocks on. */ 3640 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3641 reg |= R92C_RFMOD_CCK_EN; 3642 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3643 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3644 reg |= R92C_RFMOD_OFDM_EN; 3645 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3646 3647 /* Clear per-station keys table. */ 3648 urtwn_cam_init(sc); 3649 3650 /* Enable hardware sequence numbering. */ 3651 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3652 3653 /* Perform LO and IQ calibrations. */ 3654 urtwn_iq_calib(sc, sc->iqk_inited); 3655 sc->iqk_inited = true; 3656 3657 /* Perform LC calibration. */ 3658 urtwn_lc_calib(sc); 3659 3660 /* Fix USB interference issue. */ 3661 urtwn_write_1(sc, 0xfe40, 0xe0); 3662 urtwn_write_1(sc, 0xfe41, 0x8d); 3663 urtwn_write_1(sc, 0xfe42, 0x80); 3664 urtwn_write_4(sc, 0x20c, 0xfd0320); 3665 3666 urtwn_pa_bias_init(sc); 3667 3668 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { 3669 /* 1T1R */ 3670 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 3671 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 3672 } 3673 3674 /* Initialize GPIO setting. */ 3675 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3676 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3677 3678 /* Fix for lower temperature. */ 3679 urtwn_write_1(sc, 0x15, 0xe9); 3680 3681 /* Set default channel. */ 3682 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3683 urtwn_set_chan(sc, ic->ic_ibss_chan, IEEE80211_HTINFO_2NDCHAN_NONE); 3684 3685 /* Queue Rx xfers. */ 3686 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 3687 data = &sc->rx_data[i]; 3688 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 3689 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 3690 USBD_NO_TIMEOUT, urtwn_rxeof); 3691 error = usbd_transfer(data->xfer); 3692 if (__predict_false(error != USBD_NORMAL_COMPLETION && 3693 error != USBD_IN_PROGRESS)) 3694 goto fail; 3695 } 3696 3697 /* We're ready to go. */ 3698 ifp->if_flags &= ~IFF_OACTIVE; 3699 ifp->if_flags |= IFF_RUNNING; 3700 3701 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3702 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3703 else 3704 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3705 return (0); 3706 3707 fail: 3708 urtwn_stop(ifp, 1); 3709 return (error); 3710 } 3711 3712 static void 3713 urtwn_stop(struct ifnet *ifp, int disable) 3714 { 3715 struct urtwn_softc *sc = ifp->if_softc; 3716 struct ieee80211com *ic = &sc->sc_ic; 3717 int i, s; 3718 3719 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3720 3721 sc->tx_timer = 0; 3722 ifp->if_timer = 0; 3723 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3724 3725 s = splusb(); 3726 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3727 urtwn_wait_async(sc); 3728 splx(s); 3729 3730 callout_stop(&sc->sc_scan_to); 3731 callout_stop(&sc->sc_calib_to); 3732 3733 /* Abort Tx. */ 3734 for (i = 0; i < R92C_MAX_EPOUT; i++) { 3735 if (sc->tx_pipe[i] != NULL) 3736 usbd_abort_pipe(sc->tx_pipe[i]); 3737 } 3738 3739 /* Stop Rx pipe. */ 3740 usbd_abort_pipe(sc->rx_pipe); 3741 3742 /* Free Tx/Rx buffers. */ 3743 urtwn_free_tx_list(sc); 3744 urtwn_free_rx_list(sc); 3745 3746 if (disable) 3747 urtwn_chip_stop(sc); 3748 } 3749 3750 static void 3751 urtwn_chip_stop(struct urtwn_softc *sc) 3752 { 3753 uint32_t reg; 3754 bool disabled = true; 3755 3756 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3757 3758 /* 3759 * RF Off Sequence 3760 */ 3761 /* Pause MAC TX queue */ 3762 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 3763 3764 /* Disable RF */ 3765 urtwn_rf_write(sc, 0, 0, 0); 3766 3767 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3768 3769 /* Reset BB state machine */ 3770 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3771 R92C_SYS_FUNC_EN_USBD | 3772 R92C_SYS_FUNC_EN_USBA | 3773 R92C_SYS_FUNC_EN_BB_GLB_RST); 3774 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3775 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3776 3777 /* 3778 * Reset digital sequence 3779 */ 3780 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3781 /* Reset MCU ready status */ 3782 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3783 /* If firmware in ram code, do reset */ 3784 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 3785 urtwn_fw_reset(sc); 3786 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 3787 } 3788 } 3789 3790 /* Reset MAC and Enable 8051 */ 3791 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3792 3793 /* Reset MCU ready status */ 3794 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3795 3796 if (disabled) { 3797 /* Disable MAC clock */ 3798 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3799 /* Disable AFE PLL */ 3800 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3801 /* Gated AFE DIG_CLOCK */ 3802 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3803 /* Isolated digital to PON */ 3804 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 3805 } 3806 3807 /* 3808 * Pull GPIO PIN to balance level and LED control 3809 */ 3810 /* 1. Disable GPIO[7:0] */ 3811 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 3812 3813 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3814 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3815 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3816 3817 /* Disable GPIO[10:8] */ 3818 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 3819 3820 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 3821 reg |= (((reg & 0x000f) << 4) | 0x0780); 3822 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL+2, reg); 3823 3824 /* Disable LED0 & 1 */ 3825 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3826 3827 /* 3828 * Reset digital sequence 3829 */ 3830 if (disabled) { 3831 /* Disable ELDR clock */ 3832 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 3833 /* Isolated ELDR to PON */ 3834 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 3835 } 3836 3837 /* 3838 * Disable analog sequence 3839 */ 3840 if (disabled) { 3841 /* Disable A15 power */ 3842 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 3843 /* Disable digital core power */ 3844 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3845 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3846 ~R92C_LDOV12D_CTRL_LDV12_EN); 3847 } 3848 3849 /* Enter PFM mode */ 3850 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3851 3852 /* Set USB suspend */ 3853 urtwn_write_2(sc, R92C_APS_FSMCO, 3854 R92C_APS_FSMCO_APDM_HOST | 3855 R92C_APS_FSMCO_AFSM_HSUS | 3856 R92C_APS_FSMCO_PFM_ALDN); 3857 3858 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3859 } 3860 3861 MODULE(MODULE_CLASS_DRIVER, if_urtwn, "bpf"); 3862 3863 #ifdef _MODULE 3864 #include "ioconf.c" 3865 #endif 3866 3867 static int 3868 if_urtwn_modcmd(modcmd_t cmd, void *aux) 3869 { 3870 int error = 0; 3871 3872 switch (cmd) { 3873 case MODULE_CMD_INIT: 3874 #ifdef _MODULE 3875 error = config_init_component(cfdriver_ioconf_urtwn, 3876 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3877 #endif 3878 return (error); 3879 case MODULE_CMD_FINI: 3880 #ifdef _MODULE 3881 error = config_fini_component(cfdriver_ioconf_urtwn, 3882 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 3883 #endif 3884 return (error); 3885 default: 3886 return (ENOTTY); 3887 } 3888 } 3889
Indexes created Fri Oct 03 02:09:57 GMT 2025