if_urtwn.c revision 1.90
1 /* $NetBSD: if_urtwn.c,v 1.90 2021/02/01 04:46:33 nia Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.90 2021/02/01 04:46:33 nia Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 221 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 222 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 223 }; 224 #undef URTWN_DEV 225 #undef URTWN_RTL8188E_DEV 226 #undef URTWN_RTL8192EU_DEV 227 228 static int urtwn_match(device_t, cfdata_t, void *); 229 static void urtwn_attach(device_t, device_t, void *); 230 static int urtwn_detach(device_t, int); 231 static int urtwn_activate(device_t, enum devact); 232 233 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 234 urtwn_attach, urtwn_detach, urtwn_activate); 235 236 static int urtwn_open_pipes(struct urtwn_softc *); 237 static void urtwn_close_pipes(struct urtwn_softc *); 238 static int urtwn_alloc_rx_list(struct urtwn_softc *); 239 static void urtwn_free_rx_list(struct urtwn_softc *); 240 static int urtwn_alloc_tx_list(struct urtwn_softc *); 241 static void urtwn_free_tx_list(struct urtwn_softc *); 242 static void urtwn_task(void *); 243 static void urtwn_do_async(struct urtwn_softc *, 244 void (*)(struct urtwn_softc *, void *), void *, int); 245 static void urtwn_wait_async(struct urtwn_softc *); 246 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 247 int); 248 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 249 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 250 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 251 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 252 int); 253 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 254 int); 255 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 256 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 257 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 258 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 259 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 260 uint32_t); 261 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 262 uint32_t); 263 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 264 uint32_t); 265 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 266 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 267 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 268 static void urtwn_efuse_read(struct urtwn_softc *); 269 static void urtwn_efuse_switch_power(struct urtwn_softc *); 270 static int urtwn_read_chipid(struct urtwn_softc *); 271 #ifdef URTWN_DEBUG 272 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 273 #endif 274 static void urtwn_read_rom(struct urtwn_softc *); 275 static void urtwn_r88e_read_rom(struct urtwn_softc *); 276 static int urtwn_media_change(struct ifnet *); 277 static int urtwn_ra_init(struct urtwn_softc *); 278 static int urtwn_get_nettype(struct urtwn_softc *); 279 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 280 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 281 static void urtwn_set_led(struct urtwn_softc *, int, int); 282 static void urtwn_calib_to(void *); 283 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 284 static void urtwn_next_scan(void *); 285 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 286 int); 287 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 288 static int urtwn_wme_update(struct ieee80211com *); 289 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 290 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 291 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 292 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 293 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 294 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 295 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 296 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 297 struct ieee80211_node *, struct urtwn_tx_data *); 298 static struct urtwn_tx_data * 299 urtwn_get_tx_data(struct urtwn_softc *, size_t); 300 static void urtwn_start(struct ifnet *); 301 static void urtwn_watchdog(struct ifnet *); 302 static int urtwn_ioctl(struct ifnet *, u_long, void *); 303 static int urtwn_r92c_power_on(struct urtwn_softc *); 304 static int urtwn_r92e_power_on(struct urtwn_softc *); 305 static int urtwn_r88e_power_on(struct urtwn_softc *); 306 static int urtwn_llt_init(struct urtwn_softc *); 307 static void urtwn_fw_reset(struct urtwn_softc *); 308 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 309 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 310 static int urtwn_load_firmware(struct urtwn_softc *); 311 static int urtwn_r92c_dma_init(struct urtwn_softc *); 312 static int urtwn_r88e_dma_init(struct urtwn_softc *); 313 static void urtwn_mac_init(struct urtwn_softc *); 314 static void urtwn_bb_init(struct urtwn_softc *); 315 static void urtwn_rf_init(struct urtwn_softc *); 316 static void urtwn_cam_init(struct urtwn_softc *); 317 static void urtwn_pa_bias_init(struct urtwn_softc *); 318 static void urtwn_rxfilter_init(struct urtwn_softc *); 319 static void urtwn_edca_init(struct urtwn_softc *); 320 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 321 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 322 uint16_t[]); 323 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 324 u_int, uint16_t[]); 325 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 326 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 327 u_int); 328 static void urtwn_iq_calib(struct urtwn_softc *, bool); 329 static void urtwn_lc_calib(struct urtwn_softc *); 330 static void urtwn_temp_calib(struct urtwn_softc *); 331 static int urtwn_init(struct ifnet *); 332 static void urtwn_stop(struct ifnet *, int); 333 static int urtwn_reset(struct ifnet *); 334 static void urtwn_chip_stop(struct urtwn_softc *); 335 static void urtwn_newassoc(struct ieee80211_node *, int); 336 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 337 338 /* Aliases. */ 339 #define urtwn_bb_write urtwn_write_4 340 #define urtwn_bb_read urtwn_read_4 341 342 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 343 344 static const uint16_t addaReg[] = { 345 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 346 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 347 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 348 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 349 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 350 }; 351 352 static int 353 urtwn_match(device_t parent, cfdata_t match, void *aux) 354 { 355 struct usb_attach_arg *uaa = aux; 356 357 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 358 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 359 } 360 361 static void 362 urtwn_attach(device_t parent, device_t self, void *aux) 363 { 364 struct urtwn_softc *sc = device_private(self); 365 struct ieee80211com *ic = &sc->sc_ic; 366 struct ifnet *ifp = &sc->sc_if; 367 struct usb_attach_arg *uaa = aux; 368 char *devinfop; 369 const struct urtwn_dev *dev; 370 usb_device_request_t req; 371 size_t i; 372 int error; 373 374 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 375 376 sc->sc_dev = self; 377 sc->sc_udev = uaa->uaa_device; 378 379 sc->chip = 0; 380 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 381 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 382 SET(sc->chip, URTWN_CHIP_88E); 383 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 384 SET(sc->chip, URTWN_CHIP_92EU); 385 386 aprint_naive("\n"); 387 aprint_normal("\n"); 388 389 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 390 aprint_normal_dev(self, "%s\n", devinfop); 391 usbd_devinfo_free(devinfop); 392 393 req.bmRequestType = UT_WRITE_DEVICE; 394 req.bRequest = UR_SET_FEATURE; 395 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 396 USETW(req.wIndex, UHF_PORT_SUSPEND); 397 USETW(req.wLength, 0); 398 399 (void) usbd_do_request(sc->sc_udev, &req, 0); 400 401 cv_init(&sc->sc_task_cv, "urtwntsk"); 402 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 403 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 404 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 405 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 406 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 407 408 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 409 410 callout_init(&sc->sc_scan_to, 0); 411 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 412 callout_init(&sc->sc_calib_to, 0); 413 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 414 415 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 416 RND_TYPE_NET, RND_FLAG_DEFAULT); 417 418 error = usbd_set_config_no(sc->sc_udev, 1, 0); 419 if (error != 0) { 420 aprint_error_dev(self, "failed to set configuration" 421 ", err=%s\n", usbd_errstr(error)); 422 goto fail; 423 } 424 425 /* Get the first interface handle. */ 426 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 427 if (error != 0) { 428 aprint_error_dev(self, "could not get interface handle\n"); 429 goto fail; 430 } 431 432 error = urtwn_read_chipid(sc); 433 if (error != 0) { 434 aprint_error_dev(self, "unsupported test chip\n"); 435 goto fail; 436 } 437 438 /* Determine number of Tx/Rx chains. */ 439 if (sc->chip & URTWN_CHIP_92C) { 440 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 441 sc->nrxchains = 2; 442 } else if (sc->chip & URTWN_CHIP_92EU) { 443 sc->ntxchains = 2; 444 sc->nrxchains = 2; 445 } else { 446 sc->ntxchains = 1; 447 sc->nrxchains = 1; 448 } 449 450 if (ISSET(sc->chip, URTWN_CHIP_88E) || 451 ISSET(sc->chip, URTWN_CHIP_92EU)) 452 urtwn_r88e_read_rom(sc); 453 else 454 urtwn_read_rom(sc); 455 456 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 457 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 458 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 459 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 460 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 461 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 462 "8188CUS", sc->ntxchains, sc->nrxchains, 463 ether_sprintf(ic->ic_myaddr)); 464 465 error = urtwn_open_pipes(sc); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 468 goto fail; 469 } 470 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 471 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 472 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 473 474 /* 475 * Setup the 802.11 device. 476 */ 477 ic->ic_ifp = ifp; 478 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 479 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 480 ic->ic_state = IEEE80211_S_INIT; 481 482 /* Set device capabilities. */ 483 ic->ic_caps = 484 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 485 IEEE80211_C_IBSS | /* IBSS mode supported */ 486 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 487 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 488 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 489 IEEE80211_C_WME | /* 802.11e */ 490 IEEE80211_C_WPA; /* 802.11i */ 491 492 /* Set supported .11b and .11g rates. */ 493 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 494 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 495 496 /* Set supported .11b and .11g channels (1 through 14). */ 497 for (i = 1; i <= 14; i++) { 498 ic->ic_channels[i].ic_freq = 499 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 500 ic->ic_channels[i].ic_flags = 501 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 502 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 503 } 504 505 ifp->if_softc = sc; 506 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 507 ifp->if_init = urtwn_init; 508 ifp->if_ioctl = urtwn_ioctl; 509 ifp->if_start = urtwn_start; 510 ifp->if_watchdog = urtwn_watchdog; 511 IFQ_SET_READY(&ifp->if_snd); 512 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 513 514 if_initialize(ifp); 515 ieee80211_ifattach(ic); 516 517 /* override default methods */ 518 ic->ic_newassoc = urtwn_newassoc; 519 ic->ic_reset = urtwn_reset; 520 ic->ic_wme.wme_update = urtwn_wme_update; 521 522 /* Override state transition machine. */ 523 sc->sc_newstate = ic->ic_newstate; 524 ic->ic_newstate = urtwn_newstate; 525 526 /* XXX media locking needs revisiting */ 527 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 528 ieee80211_media_init_with_lock(ic, 529 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 530 531 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 532 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 533 &sc->sc_drvbpf); 534 535 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 536 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 537 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 538 539 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 540 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 541 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 542 543 ifp->if_percpuq = if_percpuq_create(ifp); 544 if_register(ifp); 545 546 ieee80211_announce(ic); 547 548 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 549 550 if (!pmf_device_register(self, NULL, NULL)) 551 aprint_error_dev(self, "couldn't establish power handler\n"); 552 553 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 554 return; 555 556 fail: 557 sc->sc_dying = 1; 558 aprint_error_dev(self, "attach failed\n"); 559 } 560 561 static int 562 urtwn_detach(device_t self, int flags) 563 { 564 struct urtwn_softc *sc = device_private(self); 565 struct ifnet *ifp = &sc->sc_if; 566 int s; 567 568 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 569 570 pmf_device_deregister(self); 571 572 s = splusb(); 573 574 sc->sc_dying = 1; 575 576 callout_halt(&sc->sc_scan_to, NULL); 577 callout_halt(&sc->sc_calib_to, NULL); 578 579 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 580 urtwn_stop(ifp, 0); 581 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 582 NULL); 583 584 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 585 bpf_detach(ifp); 586 ieee80211_ifdetach(&sc->sc_ic); 587 if_detach(ifp); 588 589 mutex_destroy(&sc->sc_media_mtx); 590 591 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 592 urtwn_close_pipes(sc); 593 } 594 595 splx(s); 596 597 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 598 599 rnd_detach_source(&sc->rnd_source); 600 601 callout_destroy(&sc->sc_scan_to); 602 callout_destroy(&sc->sc_calib_to); 603 604 cv_destroy(&sc->sc_task_cv); 605 mutex_destroy(&sc->sc_write_mtx); 606 mutex_destroy(&sc->sc_fwcmd_mtx); 607 mutex_destroy(&sc->sc_tx_mtx); 608 mutex_destroy(&sc->sc_rx_mtx); 609 mutex_destroy(&sc->sc_task_mtx); 610 611 return 0; 612 } 613 614 static int 615 urtwn_activate(device_t self, enum devact act) 616 { 617 struct urtwn_softc *sc = device_private(self); 618 619 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 620 621 switch (act) { 622 case DVACT_DEACTIVATE: 623 if_deactivate(sc->sc_ic.ic_ifp); 624 return 0; 625 default: 626 return EOPNOTSUPP; 627 } 628 } 629 630 static int 631 urtwn_open_pipes(struct urtwn_softc *sc) 632 { 633 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 634 static uint8_t epaddr[R92C_MAX_EPOUT]; 635 static uint8_t rxepaddr[R92C_MAX_EPIN]; 636 usb_interface_descriptor_t *id; 637 usb_endpoint_descriptor_t *ed; 638 size_t i, ntx = 0, nrx = 0; 639 int error; 640 641 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 642 643 /* Determine the number of bulk-out pipes. */ 644 id = usbd_get_interface_descriptor(sc->sc_iface); 645 for (i = 0; i < id->bNumEndpoints; i++) { 646 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 647 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 648 continue; 649 } 650 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 651 if (ntx < sizeof(epaddr)) 652 epaddr[ntx] = ed->bEndpointAddress; 653 ntx++; 654 } 655 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 656 if (nrx < sizeof(rxepaddr)) 657 rxepaddr[nrx] = ed->bEndpointAddress; 658 nrx++; 659 } 660 } 661 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 662 aprint_error_dev(sc->sc_dev, 663 "%zd: invalid number of Rx bulk pipes\n", nrx); 664 return EIO; 665 } 666 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 667 aprint_error_dev(sc->sc_dev, 668 "%zd: invalid number of Tx bulk pipes\n", ntx); 669 return EIO; 670 } 671 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 672 nrx, ntx, 0, 0); 673 sc->rx_npipe = nrx; 674 sc->tx_npipe = ntx; 675 676 /* Open bulk-in pipe at address 0x81. */ 677 for (i = 0; i < nrx; i++) { 678 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 679 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 680 if (error != 0) { 681 aprint_error_dev(sc->sc_dev, 682 "could not open Rx bulk pipe 0x%02x: %d\n", 683 rxepaddr[i], error); 684 goto fail; 685 } 686 } 687 688 /* Open bulk-out pipes (up to 3). */ 689 for (i = 0; i < ntx; i++) { 690 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 691 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 692 if (error != 0) { 693 aprint_error_dev(sc->sc_dev, 694 "could not open Tx bulk pipe 0x%02x: %d\n", 695 epaddr[i], error); 696 goto fail; 697 } 698 } 699 700 /* Map 802.11 access categories to USB pipes. */ 701 sc->ac2idx[WME_AC_BK] = 702 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 703 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 704 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 705 706 fail: 707 if (error != 0) 708 urtwn_close_pipes(sc); 709 return error; 710 } 711 712 static void 713 urtwn_close_pipes(struct urtwn_softc *sc) 714 { 715 struct usbd_pipe *pipe; 716 size_t i; 717 718 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 719 720 /* Close Rx pipes. */ 721 CTASSERT(sizeof(pipe) == sizeof(void *)); 722 for (i = 0; i < sc->rx_npipe; i++) { 723 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 724 if (pipe != NULL) { 725 usbd_close_pipe(pipe); 726 } 727 } 728 729 /* Close Tx pipes. */ 730 for (i = 0; i < sc->tx_npipe; i++) { 731 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 732 if (pipe != NULL) { 733 usbd_close_pipe(pipe); 734 } 735 } 736 } 737 738 static int __noinline 739 urtwn_alloc_rx_list(struct urtwn_softc *sc) 740 { 741 struct urtwn_rx_data *data; 742 size_t i; 743 int error = 0; 744 745 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 746 747 for (size_t j = 0; j < sc->rx_npipe; j++) { 748 TAILQ_INIT(&sc->rx_free_list[j]); 749 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 750 data = &sc->rx_data[j][i]; 751 752 data->sc = sc; /* Backpointer for callbacks. */ 753 754 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 755 0, 0, &data->xfer); 756 if (error) { 757 aprint_error_dev(sc->sc_dev, 758 "could not allocate xfer\n"); 759 break; 760 } 761 762 data->buf = usbd_get_buffer(data->xfer); 763 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 764 } 765 } 766 if (error != 0) 767 urtwn_free_rx_list(sc); 768 return error; 769 } 770 771 static void 772 urtwn_free_rx_list(struct urtwn_softc *sc) 773 { 774 struct usbd_xfer *xfer; 775 size_t i; 776 777 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 778 779 /* NB: Caller must abort pipe first. */ 780 for (size_t j = 0; j < sc->rx_npipe; j++) { 781 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 782 CTASSERT(sizeof(xfer) == sizeof(void *)); 783 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 784 if (xfer != NULL) 785 usbd_destroy_xfer(xfer); 786 } 787 } 788 } 789 790 static int __noinline 791 urtwn_alloc_tx_list(struct urtwn_softc *sc) 792 { 793 struct urtwn_tx_data *data; 794 size_t i; 795 int error = 0; 796 797 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 798 799 mutex_enter(&sc->sc_tx_mtx); 800 for (size_t j = 0; j < sc->tx_npipe; j++) { 801 TAILQ_INIT(&sc->tx_free_list[j]); 802 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 803 data = &sc->tx_data[j][i]; 804 805 data->sc = sc; /* Backpointer for callbacks. */ 806 data->pidx = j; 807 808 error = usbd_create_xfer(sc->tx_pipe[j], 809 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 810 &data->xfer); 811 if (error) { 812 aprint_error_dev(sc->sc_dev, 813 "could not allocate xfer\n"); 814 goto fail; 815 } 816 817 data->buf = usbd_get_buffer(data->xfer); 818 819 /* Append this Tx buffer to our free list. */ 820 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 821 } 822 } 823 mutex_exit(&sc->sc_tx_mtx); 824 return 0; 825 826 fail: 827 urtwn_free_tx_list(sc); 828 mutex_exit(&sc->sc_tx_mtx); 829 return error; 830 } 831 832 static void 833 urtwn_free_tx_list(struct urtwn_softc *sc) 834 { 835 struct usbd_xfer *xfer; 836 size_t i; 837 838 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 839 840 /* NB: Caller must abort pipe first. */ 841 for (size_t j = 0; j < sc->tx_npipe; j++) { 842 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 843 CTASSERT(sizeof(xfer) == sizeof(void *)); 844 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 845 if (xfer != NULL) 846 usbd_destroy_xfer(xfer); 847 } 848 } 849 } 850 851 static int 852 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 853 struct ieee80211_node *ni) 854 { 855 struct urtwn_tx_data *data = 856 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 857 return urtwn_tx(sc, m, ni, data); 858 } 859 860 static void 861 urtwn_task(void *arg) 862 { 863 struct urtwn_softc *sc = arg; 864 struct ieee80211com *ic = &sc->sc_ic; 865 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 866 struct urtwn_host_cmd *cmd; 867 int s; 868 869 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 870 if (ic->ic_state == IEEE80211_S_RUN && 871 (ic->ic_opmode == IEEE80211_M_HOSTAP || 872 ic->ic_opmode == IEEE80211_M_IBSS)) { 873 874 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 875 &sc->sc_bo); 876 if (m == NULL) { 877 aprint_error_dev(sc->sc_dev, 878 "could not allocate beacon"); 879 } 880 881 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 882 aprint_error_dev(sc->sc_dev, "could not send beacon"); 883 } 884 885 /* beacon is no longer needed */ 886 m_freem(m); 887 } 888 889 /* Process host commands. */ 890 s = splusb(); 891 mutex_spin_enter(&sc->sc_task_mtx); 892 while (ring->next != ring->cur) { 893 cmd = &ring->cmd[ring->next]; 894 mutex_spin_exit(&sc->sc_task_mtx); 895 splx(s); 896 /* Invoke callback with kernel lock held. */ 897 cmd->cb(sc, cmd->data); 898 s = splusb(); 899 mutex_spin_enter(&sc->sc_task_mtx); 900 ring->queued--; 901 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 902 } 903 cv_broadcast(&sc->sc_task_cv); 904 mutex_spin_exit(&sc->sc_task_mtx); 905 splx(s); 906 } 907 908 static void 909 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 910 void *arg, int len) 911 { 912 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 913 struct urtwn_host_cmd *cmd; 914 int s; 915 916 URTWNHIST_FUNC(); 917 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 918 (uintptr_t)cb, (uintptr_t)arg, len, 0); 919 920 s = splusb(); 921 mutex_spin_enter(&sc->sc_task_mtx); 922 cmd = &ring->cmd[ring->cur]; 923 cmd->cb = cb; 924 KASSERT(len <= sizeof(cmd->data)); 925 memcpy(cmd->data, arg, len); 926 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 927 928 /* If there is no pending command already, schedule a task. */ 929 if (!sc->sc_dying && ++ring->queued == 1) { 930 mutex_spin_exit(&sc->sc_task_mtx); 931 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 932 } else 933 mutex_spin_exit(&sc->sc_task_mtx); 934 splx(s); 935 } 936 937 static void 938 urtwn_wait_async(struct urtwn_softc *sc) 939 { 940 941 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 942 943 /* Wait for all queued asynchronous commands to complete. */ 944 mutex_spin_enter(&sc->sc_task_mtx); 945 while (sc->cmdq.queued > 0) 946 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 947 mutex_spin_exit(&sc->sc_task_mtx); 948 } 949 950 static int 951 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 952 int len) 953 { 954 usb_device_request_t req; 955 usbd_status error; 956 957 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 958 KASSERT(mutex_owned(&sc->sc_write_mtx)); 959 960 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 961 req.bRequest = R92C_REQ_REGS; 962 USETW(req.wValue, addr); 963 USETW(req.wIndex, 0); 964 USETW(req.wLength, len); 965 error = usbd_do_request(sc->sc_udev, &req, buf); 966 if (error != USBD_NORMAL_COMPLETION) { 967 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 968 error, addr, len, 0); 969 } 970 return error; 971 } 972 973 static void 974 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 975 { 976 977 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 978 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 979 980 urtwn_write_region_1(sc, addr, &val, 1); 981 } 982 983 static void 984 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 985 { 986 uint8_t buf[2]; 987 988 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 989 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 990 991 buf[0] = (uint8_t)val; 992 buf[1] = (uint8_t)(val >> 8); 993 urtwn_write_region_1(sc, addr, buf, 2); 994 } 995 996 static void 997 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 998 { 999 uint8_t buf[4]; 1000 1001 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1002 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1003 1004 buf[0] = (uint8_t)val; 1005 buf[1] = (uint8_t)(val >> 8); 1006 buf[2] = (uint8_t)(val >> 16); 1007 buf[3] = (uint8_t)(val >> 24); 1008 urtwn_write_region_1(sc, addr, buf, 4); 1009 } 1010 1011 static int 1012 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1013 { 1014 1015 URTWNHIST_FUNC(); 1016 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1017 1018 return urtwn_write_region_1(sc, addr, buf, len); 1019 } 1020 1021 static int 1022 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1023 int len) 1024 { 1025 usb_device_request_t req; 1026 usbd_status error; 1027 1028 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1029 1030 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1031 req.bRequest = R92C_REQ_REGS; 1032 USETW(req.wValue, addr); 1033 USETW(req.wIndex, 0); 1034 USETW(req.wLength, len); 1035 error = usbd_do_request(sc->sc_udev, &req, buf); 1036 if (error != USBD_NORMAL_COMPLETION) { 1037 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1038 error, addr, len, 0); 1039 } 1040 return error; 1041 } 1042 1043 static uint8_t 1044 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1045 { 1046 uint8_t val; 1047 1048 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1049 1050 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1051 return 0xff; 1052 1053 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1054 return val; 1055 } 1056 1057 static uint16_t 1058 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1059 { 1060 uint8_t buf[2]; 1061 uint16_t val; 1062 1063 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1064 1065 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1066 return 0xffff; 1067 1068 val = LE_READ_2(&buf[0]); 1069 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1070 return val; 1071 } 1072 1073 static uint32_t 1074 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1075 { 1076 uint8_t buf[4]; 1077 uint32_t val; 1078 1079 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1080 1081 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1082 return 0xffffffff; 1083 1084 val = LE_READ_4(&buf[0]); 1085 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1086 return val; 1087 } 1088 1089 static int 1090 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1091 { 1092 struct r92c_fw_cmd cmd; 1093 uint8_t *cp; 1094 int fwcur; 1095 int ntries; 1096 1097 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1098 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1099 1100 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1101 1102 mutex_enter(&sc->sc_fwcmd_mtx); 1103 fwcur = sc->fwcur; 1104 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1105 mutex_exit(&sc->sc_fwcmd_mtx); 1106 1107 /* Wait for current FW box to be empty. */ 1108 for (ntries = 0; ntries < 100; ntries++) { 1109 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1110 break; 1111 DELAY(2000); 1112 } 1113 if (ntries == 100) { 1114 aprint_error_dev(sc->sc_dev, 1115 "could not send firmware command %d\n", id); 1116 return ETIMEDOUT; 1117 } 1118 1119 memset(&cmd, 0, sizeof(cmd)); 1120 KASSERT(len <= sizeof(cmd.msg)); 1121 memcpy(cmd.msg, buf, len); 1122 1123 /* Write the first word last since that will trigger the FW. */ 1124 cp = (uint8_t *)&cmd; 1125 cmd.id = id; 1126 if (len >= 4) { 1127 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1128 cmd.id |= R92C_CMD_FLAG_EXT; 1129 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1130 &cp[1], 2); 1131 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1132 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1133 ((uint32_t)cp[5] << 24)); 1134 } else { 1135 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1136 &cp[4], 2); 1137 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1138 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1139 ((uint32_t)cp[3] << 24)); 1140 } 1141 } else { 1142 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1143 } 1144 1145 return 0; 1146 } 1147 1148 static __inline void 1149 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1150 { 1151 1152 sc->sc_rf_write(sc, chain, addr, val); 1153 } 1154 1155 static void 1156 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1157 uint32_t val) 1158 { 1159 1160 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1161 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1162 } 1163 1164 static void 1165 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1166 uint32_t val) 1167 { 1168 1169 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1170 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1171 } 1172 1173 static void 1174 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1175 uint32_t val) 1176 { 1177 1178 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1179 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1180 } 1181 1182 static uint32_t 1183 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1184 { 1185 uint32_t reg[R92C_MAX_CHAINS], val; 1186 1187 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1188 if (chain != 0) { 1189 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1190 } 1191 1192 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1193 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1194 DELAY(1000); 1195 1196 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1197 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1198 R92C_HSSI_PARAM2_READ_EDGE); 1199 DELAY(1000); 1200 1201 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1202 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1203 DELAY(1000); 1204 1205 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1206 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1207 } else { 1208 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1209 } 1210 return MS(val, R92C_LSSI_READBACK_DATA); 1211 } 1212 1213 static int 1214 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1215 { 1216 int ntries; 1217 1218 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1219 1220 urtwn_write_4(sc, R92C_LLT_INIT, 1221 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1222 SM(R92C_LLT_INIT_ADDR, addr) | 1223 SM(R92C_LLT_INIT_DATA, data)); 1224 /* Wait for write operation to complete. */ 1225 for (ntries = 0; ntries < 20; ntries++) { 1226 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1227 R92C_LLT_INIT_OP_NO_ACTIVE) { 1228 /* Done */ 1229 return 0; 1230 } 1231 DELAY(5); 1232 } 1233 return ETIMEDOUT; 1234 } 1235 1236 static uint8_t 1237 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1238 { 1239 uint32_t reg; 1240 int ntries; 1241 1242 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1243 1244 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1245 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1246 reg &= ~R92C_EFUSE_CTRL_VALID; 1247 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1248 1249 /* Wait for read operation to complete. */ 1250 for (ntries = 0; ntries < 100; ntries++) { 1251 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1252 if (reg & R92C_EFUSE_CTRL_VALID) { 1253 /* Done */ 1254 return MS(reg, R92C_EFUSE_CTRL_DATA); 1255 } 1256 DELAY(5); 1257 } 1258 aprint_error_dev(sc->sc_dev, 1259 "could not read efuse byte at address 0x%04x\n", addr); 1260 return 0xff; 1261 } 1262 1263 static void 1264 urtwn_efuse_read(struct urtwn_softc *sc) 1265 { 1266 uint8_t *rom = (uint8_t *)&sc->rom; 1267 uint32_t reg; 1268 uint16_t addr = 0; 1269 uint8_t off, msk; 1270 size_t i; 1271 1272 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1273 1274 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1275 1276 urtwn_efuse_switch_power(sc); 1277 1278 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1279 while (addr < 512) { 1280 reg = urtwn_efuse_read_1(sc, addr); 1281 if (reg == 0xff) 1282 break; 1283 addr++; 1284 off = reg >> 4; 1285 msk = reg & 0xf; 1286 for (i = 0; i < 4; i++) { 1287 if (msk & (1U << i)) 1288 continue; 1289 1290 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1291 addr++; 1292 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1293 addr++; 1294 } 1295 } 1296 #ifdef URTWN_DEBUG 1297 /* Dump ROM content. */ 1298 for (i = 0; i < (int)sizeof(sc->rom); i++) 1299 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1300 #endif 1301 } 1302 1303 static void 1304 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1305 { 1306 uint32_t reg; 1307 1308 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1309 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1310 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1311 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1312 } 1313 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1314 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1315 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1316 reg | R92C_SYS_FUNC_EN_ELDR); 1317 } 1318 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1319 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1320 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1321 urtwn_write_2(sc, R92C_SYS_CLKR, 1322 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1323 } 1324 } 1325 1326 static int 1327 urtwn_read_chipid(struct urtwn_softc *sc) 1328 { 1329 uint32_t reg; 1330 1331 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1332 1333 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1334 ISSET(sc->chip, URTWN_CHIP_92EU)) 1335 return 0; 1336 1337 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1338 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1339 /* test chip, not supported */ 1340 return EIO; 1341 } 1342 if (reg & R92C_SYS_CFG_TYPE_92C) { 1343 sc->chip |= URTWN_CHIP_92C; 1344 /* Check if it is a castrated 8192C. */ 1345 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1346 R92C_HPON_FSM_CHIP_BONDING_ID) == 1347 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1348 sc->chip |= URTWN_CHIP_92C_1T2R; 1349 } 1350 } 1351 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1352 sc->chip |= URTWN_CHIP_UMC; 1353 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1354 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1355 } 1356 } 1357 return 0; 1358 } 1359 1360 #ifdef URTWN_DEBUG 1361 static void 1362 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1363 { 1364 1365 aprint_normal_dev(sc->sc_dev, 1366 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1367 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1368 1369 aprint_normal_dev(sc->sc_dev, 1370 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1371 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1372 1373 aprint_normal_dev(sc->sc_dev, 1374 "macaddr %s\n", 1375 ether_sprintf(rp->macaddr)); 1376 1377 aprint_normal_dev(sc->sc_dev, 1378 "string %s, subcustomer_id %#x\n", 1379 rp->string, rp->subcustomer_id); 1380 1381 aprint_normal_dev(sc->sc_dev, 1382 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1383 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1384 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1385 1386 aprint_normal_dev(sc->sc_dev, 1387 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1388 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1389 rp->ht40_1s_tx_pwr[0][2], 1390 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1391 rp->ht40_1s_tx_pwr[1][2]); 1392 1393 aprint_normal_dev(sc->sc_dev, 1394 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1395 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1396 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1397 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1398 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1399 1400 aprint_normal_dev(sc->sc_dev, 1401 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1402 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1403 rp->ht20_tx_pwr_diff[2] & 0xf, 1404 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1405 rp->ht20_tx_pwr_diff[2] >> 4); 1406 1407 aprint_normal_dev(sc->sc_dev, 1408 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1409 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1410 rp->ofdm_tx_pwr_diff[2] & 0xf, 1411 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1412 rp->ofdm_tx_pwr_diff[2] >> 4); 1413 1414 aprint_normal_dev(sc->sc_dev, 1415 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1416 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1417 rp->ht40_max_pwr[2] & 0xf, 1418 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1419 rp->ht40_max_pwr[2] >> 4); 1420 1421 aprint_normal_dev(sc->sc_dev, 1422 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1423 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1424 rp->ht20_max_pwr[2] & 0xf, 1425 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1426 rp->ht20_max_pwr[2] >> 4); 1427 1428 aprint_normal_dev(sc->sc_dev, 1429 "xtal_calib %d, tssi %d %d, thermal %d\n", 1430 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1431 1432 aprint_normal_dev(sc->sc_dev, 1433 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1434 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1435 1436 aprint_normal_dev(sc->sc_dev, 1437 "channnel_plan %d, version %d customer_id %#x\n", 1438 rp->channel_plan, rp->version, rp->curstomer_id); 1439 } 1440 #endif 1441 1442 static void 1443 urtwn_read_rom(struct urtwn_softc *sc) 1444 { 1445 struct ieee80211com *ic = &sc->sc_ic; 1446 struct r92c_rom *rom = &sc->rom; 1447 1448 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1449 1450 mutex_enter(&sc->sc_write_mtx); 1451 1452 /* Read full ROM image. */ 1453 urtwn_efuse_read(sc); 1454 #ifdef URTWN_DEBUG 1455 if (urtwn_debug & DBG_REG) 1456 urtwn_dump_rom(sc, rom); 1457 #endif 1458 1459 /* XXX Weird but this is what the vendor driver does. */ 1460 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1461 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1462 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1463 1464 DPRINTFN(DBG_INIT, 1465 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1466 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1467 1468 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1469 1470 sc->sc_rf_write = urtwn_r92c_rf_write; 1471 sc->sc_power_on = urtwn_r92c_power_on; 1472 sc->sc_dma_init = urtwn_r92c_dma_init; 1473 1474 mutex_exit(&sc->sc_write_mtx); 1475 } 1476 1477 static void 1478 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1479 { 1480 struct ieee80211com *ic = &sc->sc_ic; 1481 uint8_t *rom = sc->r88e_rom; 1482 uint32_t reg; 1483 uint16_t addr = 0; 1484 uint8_t off, msk, tmp; 1485 int i; 1486 1487 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1488 1489 mutex_enter(&sc->sc_write_mtx); 1490 1491 off = 0; 1492 urtwn_efuse_switch_power(sc); 1493 1494 /* Read full ROM image. */ 1495 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1496 while (addr < 4096) { 1497 reg = urtwn_efuse_read_1(sc, addr); 1498 if (reg == 0xff) 1499 break; 1500 addr++; 1501 if ((reg & 0x1f) == 0x0f) { 1502 tmp = (reg & 0xe0) >> 5; 1503 reg = urtwn_efuse_read_1(sc, addr); 1504 if ((reg & 0x0f) != 0x0f) 1505 off = ((reg & 0xf0) >> 1) | tmp; 1506 addr++; 1507 } else 1508 off = reg >> 4; 1509 msk = reg & 0xf; 1510 for (i = 0; i < 4; i++) { 1511 if (msk & (1 << i)) 1512 continue; 1513 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1514 addr++; 1515 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1516 addr++; 1517 } 1518 } 1519 #ifdef URTWN_DEBUG 1520 if (urtwn_debug & DBG_REG) { 1521 } 1522 #endif 1523 1524 addr = 0x10; 1525 for (i = 0; i < 6; i++) 1526 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1527 for (i = 0; i < 5; i++) 1528 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1529 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1530 if (sc->bw20_tx_pwr_diff & 0x08) 1531 sc->bw20_tx_pwr_diff |= 0xf0; 1532 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1533 if (sc->ofdm_tx_pwr_diff & 0x08) 1534 sc->ofdm_tx_pwr_diff |= 0xf0; 1535 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1536 1537 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1538 1539 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1540 sc->sc_power_on = urtwn_r92e_power_on; 1541 sc->sc_rf_write = urtwn_r92e_rf_write; 1542 } else { 1543 sc->sc_power_on = urtwn_r88e_power_on; 1544 sc->sc_rf_write = urtwn_r88e_rf_write; 1545 } 1546 sc->sc_dma_init = urtwn_r88e_dma_init; 1547 1548 mutex_exit(&sc->sc_write_mtx); 1549 } 1550 1551 static int 1552 urtwn_media_change(struct ifnet *ifp) 1553 { 1554 int error; 1555 1556 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1557 1558 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1559 return error; 1560 1561 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1562 (IFF_UP | IFF_RUNNING)) { 1563 urtwn_init(ifp); 1564 } 1565 return 0; 1566 } 1567 1568 /* 1569 * Initialize rate adaptation in firmware. 1570 */ 1571 static int __noinline 1572 urtwn_ra_init(struct urtwn_softc *sc) 1573 { 1574 static const uint8_t map[] = { 1575 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1576 }; 1577 struct ieee80211com *ic = &sc->sc_ic; 1578 struct ieee80211_node *ni = ic->ic_bss; 1579 struct ieee80211_rateset *rs = &ni->ni_rates; 1580 struct r92c_fw_cmd_macid_cfg cmd; 1581 uint32_t rates, basicrates; 1582 uint32_t rrsr_mask, rrsr_rate; 1583 uint8_t mode; 1584 size_t maxrate, maxbasicrate, i, j; 1585 int error; 1586 1587 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1588 1589 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1590 1591 /* Get normal and basic rates mask. */ 1592 rates = basicrates = 1; 1593 maxrate = maxbasicrate = 0; 1594 for (i = 0; i < rs->rs_nrates; i++) { 1595 /* Convert 802.11 rate to HW rate index. */ 1596 for (j = 0; j < __arraycount(map); j++) { 1597 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1598 break; 1599 } 1600 } 1601 if (j == __arraycount(map)) { 1602 /* Unknown rate, skip. */ 1603 continue; 1604 } 1605 1606 rates |= 1U << j; 1607 if (j > maxrate) { 1608 maxrate = j; 1609 } 1610 1611 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1612 basicrates |= 1U << j; 1613 if (j > maxbasicrate) { 1614 maxbasicrate = j; 1615 } 1616 } 1617 } 1618 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1619 mode = R92C_RAID_11B; 1620 } else { 1621 mode = R92C_RAID_11BG; 1622 } 1623 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1624 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1625 "maxrate=%jx, maxbasicrate=%jx", 1626 rates, basicrates, maxrate, maxbasicrate); 1627 1628 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1629 maxbasicrate |= R92C_RATE_SHORTGI; 1630 maxrate |= R92C_RATE_SHORTGI; 1631 } 1632 1633 /* Set rates mask for group addressed frames. */ 1634 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1635 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1636 cmd.macid |= RTWN_MACID_SHORTGI; 1637 cmd.mask = htole32((mode << 28) | basicrates); 1638 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1639 if (error != 0) { 1640 aprint_error_dev(sc->sc_dev, 1641 "could not add broadcast station\n"); 1642 return error; 1643 } 1644 /* Set initial MRR rate. */ 1645 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1646 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1647 1648 /* Set rates mask for unicast frames. */ 1649 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1650 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1651 cmd.macid |= RTWN_MACID_SHORTGI; 1652 cmd.mask = htole32((mode << 28) | rates); 1653 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1654 if (error != 0) { 1655 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1656 return error; 1657 } 1658 /* Set initial MRR rate. */ 1659 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1660 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1661 1662 rrsr_rate = ic->ic_fixed_rate; 1663 if (rrsr_rate == -1) 1664 rrsr_rate = 11; 1665 1666 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1667 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1668 1669 /* Indicate highest supported rate. */ 1670 ni->ni_txrate = rs->rs_nrates - 1; 1671 1672 return 0; 1673 } 1674 1675 static int 1676 urtwn_get_nettype(struct urtwn_softc *sc) 1677 { 1678 struct ieee80211com *ic = &sc->sc_ic; 1679 int type; 1680 1681 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1682 1683 switch (ic->ic_opmode) { 1684 case IEEE80211_M_STA: 1685 type = R92C_CR_NETTYPE_INFRA; 1686 break; 1687 1688 case IEEE80211_M_IBSS: 1689 type = R92C_CR_NETTYPE_ADHOC; 1690 break; 1691 1692 default: 1693 type = R92C_CR_NETTYPE_NOLINK; 1694 break; 1695 } 1696 1697 return type; 1698 } 1699 1700 static void 1701 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1702 { 1703 uint8_t reg; 1704 1705 URTWNHIST_FUNC(); 1706 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1707 1708 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1709 1710 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1711 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1712 } 1713 1714 static void 1715 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1716 { 1717 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1718 uint64_t tsf; 1719 1720 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1721 1722 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1723 1724 /* Enable TSF synchronization. */ 1725 urtwn_write_1(sc, R92C_BCN_CTRL, 1726 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1727 1728 /* Correct TSF */ 1729 urtwn_write_1(sc, R92C_BCN_CTRL, 1730 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1731 1732 /* Set initial TSF. */ 1733 tsf = ni->ni_tstamp.tsf; 1734 tsf = le64toh(tsf); 1735 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1736 tsf -= IEEE80211_DUR_TU; 1737 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1738 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1739 1740 urtwn_write_1(sc, R92C_BCN_CTRL, 1741 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1742 } 1743 1744 static void 1745 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1746 { 1747 uint8_t reg; 1748 1749 URTWNHIST_FUNC(); 1750 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1751 1752 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1753 1754 if (led == URTWN_LED_LINK) { 1755 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1756 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1757 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1758 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1759 (R92C_LEDCFG0_DIS << 1)); 1760 if (on) { 1761 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1762 R92E_LEDSON; 1763 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1764 } 1765 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1766 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1767 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1768 if (!on) { 1769 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1770 urtwn_write_1(sc, R92C_LEDCFG2, 1771 reg | R92C_LEDCFG0_DIS); 1772 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1773 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1774 reg & 0xfe); 1775 } 1776 } else { 1777 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1778 if (!on) { 1779 reg |= R92C_LEDCFG0_DIS; 1780 } 1781 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1782 } 1783 sc->ledlink = on; /* Save LED state. */ 1784 } 1785 } 1786 1787 static void 1788 urtwn_calib_to(void *arg) 1789 { 1790 struct urtwn_softc *sc = arg; 1791 1792 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1793 1794 if (sc->sc_dying) 1795 return; 1796 1797 /* Do it in a process context. */ 1798 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1799 } 1800 1801 /* ARGSUSED */ 1802 static void 1803 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1804 { 1805 struct r92c_fw_cmd_rssi cmd; 1806 struct r92e_fw_cmd_rssi cmde; 1807 1808 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1809 1810 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1811 goto restart_timer; 1812 1813 mutex_enter(&sc->sc_write_mtx); 1814 if (sc->avg_pwdb != -1) { 1815 /* Indicate Rx signal strength to FW for rate adaptation. */ 1816 memset(&cmd, 0, sizeof(cmd)); 1817 memset(&cmde, 0, sizeof(cmde)); 1818 cmd.macid = 0; /* BSS. */ 1819 cmde.macid = 0; /* BSS. */ 1820 cmd.pwdb = sc->avg_pwdb; 1821 cmde.pwdb = sc->avg_pwdb; 1822 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1823 sc->avg_pwdb, 0, 0, 0); 1824 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1825 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1826 sizeof(cmd)); 1827 } else { 1828 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1829 sizeof(cmde)); 1830 } 1831 } 1832 1833 /* Do temperature compensation. */ 1834 urtwn_temp_calib(sc); 1835 mutex_exit(&sc->sc_write_mtx); 1836 1837 restart_timer: 1838 if (!sc->sc_dying) { 1839 /* Restart calibration timer. */ 1840 callout_schedule(&sc->sc_calib_to, hz); 1841 } 1842 } 1843 1844 static void 1845 urtwn_next_scan(void *arg) 1846 { 1847 struct urtwn_softc *sc = arg; 1848 int s; 1849 1850 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1851 1852 if (sc->sc_dying) 1853 return; 1854 1855 s = splnet(); 1856 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1857 ieee80211_next_scan(&sc->sc_ic); 1858 splx(s); 1859 } 1860 1861 static void 1862 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1863 { 1864 URTWNHIST_FUNC(); 1865 URTWNHIST_CALLARGS("new node %06jx%06jx", 1866 ni->ni_macaddr[0] << 2 | 1867 ni->ni_macaddr[1] << 1 | 1868 ni->ni_macaddr[2], 1869 ni->ni_macaddr[3] << 2 | 1870 ni->ni_macaddr[4] << 1 | 1871 ni->ni_macaddr[5], 1872 0, 0); 1873 /* start with lowest Tx rate */ 1874 ni->ni_txrate = 0; 1875 } 1876 1877 static int 1878 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1879 { 1880 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1881 struct urtwn_cmd_newstate cmd; 1882 1883 URTWNHIST_FUNC(); 1884 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1885 1886 callout_stop(&sc->sc_scan_to); 1887 callout_stop(&sc->sc_calib_to); 1888 1889 /* Do it in a process context. */ 1890 cmd.state = nstate; 1891 cmd.arg = arg; 1892 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1893 return 0; 1894 } 1895 1896 static void 1897 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1898 { 1899 struct urtwn_cmd_newstate *cmd = arg; 1900 struct ieee80211com *ic = &sc->sc_ic; 1901 struct ieee80211_node *ni; 1902 enum ieee80211_state ostate = ic->ic_state; 1903 enum ieee80211_state nstate = cmd->state; 1904 uint32_t reg; 1905 uint8_t sifs_time, msr; 1906 int s; 1907 1908 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1909 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1910 1911 s = splnet(); 1912 mutex_enter(&sc->sc_write_mtx); 1913 1914 callout_stop(&sc->sc_scan_to); 1915 callout_stop(&sc->sc_calib_to); 1916 1917 switch (ostate) { 1918 case IEEE80211_S_INIT: 1919 break; 1920 1921 case IEEE80211_S_SCAN: 1922 if (nstate != IEEE80211_S_SCAN) { 1923 /* 1924 * End of scanning 1925 */ 1926 /* flush 4-AC Queue after site_survey */ 1927 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1928 1929 /* Allow Rx from our BSSID only. */ 1930 urtwn_write_4(sc, R92C_RCR, 1931 urtwn_read_4(sc, R92C_RCR) | 1932 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1933 } 1934 break; 1935 1936 case IEEE80211_S_AUTH: 1937 case IEEE80211_S_ASSOC: 1938 break; 1939 1940 case IEEE80211_S_RUN: 1941 /* Turn link LED off. */ 1942 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1943 1944 /* Set media status to 'No Link'. */ 1945 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1946 1947 /* Stop Rx of data frames. */ 1948 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1949 1950 /* Reset TSF. */ 1951 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1952 1953 /* Disable TSF synchronization. */ 1954 urtwn_write_1(sc, R92C_BCN_CTRL, 1955 urtwn_read_1(sc, R92C_BCN_CTRL) | 1956 R92C_BCN_CTRL_DIS_TSF_UDT0); 1957 1958 /* Back to 20MHz mode */ 1959 urtwn_set_chan(sc, ic->ic_curchan, 1960 IEEE80211_HTINFO_2NDCHAN_NONE); 1961 1962 if (ic->ic_opmode == IEEE80211_M_IBSS || 1963 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1964 /* Stop BCN */ 1965 urtwn_write_1(sc, R92C_BCN_CTRL, 1966 urtwn_read_1(sc, R92C_BCN_CTRL) & 1967 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1968 } 1969 1970 /* Reset EDCA parameters. */ 1971 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1972 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1973 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1974 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1975 1976 /* flush all cam entries */ 1977 urtwn_cam_init(sc); 1978 break; 1979 } 1980 1981 switch (nstate) { 1982 case IEEE80211_S_INIT: 1983 /* Turn link LED off. */ 1984 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1985 break; 1986 1987 case IEEE80211_S_SCAN: 1988 if (ostate != IEEE80211_S_SCAN) { 1989 /* 1990 * Begin of scanning 1991 */ 1992 1993 /* Set gain for scanning. */ 1994 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1995 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1996 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1997 1998 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1999 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2000 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2001 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2002 } 2003 2004 /* Set media status to 'No Link'. */ 2005 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2006 2007 /* Allow Rx from any BSSID. */ 2008 urtwn_write_4(sc, R92C_RCR, 2009 urtwn_read_4(sc, R92C_RCR) & 2010 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2011 2012 /* Stop Rx of data frames. */ 2013 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2014 2015 /* Disable update TSF */ 2016 urtwn_write_1(sc, R92C_BCN_CTRL, 2017 urtwn_read_1(sc, R92C_BCN_CTRL) | 2018 R92C_BCN_CTRL_DIS_TSF_UDT0); 2019 } 2020 2021 /* Make link LED blink during scan. */ 2022 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2023 2024 /* Pause AC Tx queues. */ 2025 urtwn_write_1(sc, R92C_TXPAUSE, 2026 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2027 2028 urtwn_set_chan(sc, ic->ic_curchan, 2029 IEEE80211_HTINFO_2NDCHAN_NONE); 2030 2031 /* Start periodic scan. */ 2032 if (!sc->sc_dying) 2033 callout_schedule(&sc->sc_scan_to, hz / 5); 2034 break; 2035 2036 case IEEE80211_S_AUTH: 2037 /* Set initial gain under link. */ 2038 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2039 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2040 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2041 2042 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2043 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2044 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2045 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2046 } 2047 2048 /* Set media status to 'No Link'. */ 2049 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2050 2051 /* Allow Rx from any BSSID. */ 2052 urtwn_write_4(sc, R92C_RCR, 2053 urtwn_read_4(sc, R92C_RCR) & 2054 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2055 2056 urtwn_set_chan(sc, ic->ic_curchan, 2057 IEEE80211_HTINFO_2NDCHAN_NONE); 2058 break; 2059 2060 case IEEE80211_S_ASSOC: 2061 break; 2062 2063 case IEEE80211_S_RUN: 2064 ni = ic->ic_bss; 2065 2066 /* XXX: Set 20MHz mode */ 2067 urtwn_set_chan(sc, ic->ic_curchan, 2068 IEEE80211_HTINFO_2NDCHAN_NONE); 2069 2070 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2071 /* Back to 20MHz mode */ 2072 urtwn_set_chan(sc, ic->ic_curchan, 2073 IEEE80211_HTINFO_2NDCHAN_NONE); 2074 2075 /* Set media status to 'No Link'. */ 2076 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2077 2078 /* Enable Rx of data frames. */ 2079 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2080 2081 /* Allow Rx from any BSSID. */ 2082 urtwn_write_4(sc, R92C_RCR, 2083 urtwn_read_4(sc, R92C_RCR) & 2084 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2085 2086 /* Accept Rx data/control/management frames */ 2087 urtwn_write_4(sc, R92C_RCR, 2088 urtwn_read_4(sc, R92C_RCR) | 2089 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2090 2091 /* Turn link LED on. */ 2092 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2093 break; 2094 } 2095 2096 /* Set media status to 'Associated'. */ 2097 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2098 2099 /* Set BSSID. */ 2100 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2101 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2102 2103 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2104 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2105 } else { 2106 /* 802.11b/g */ 2107 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2108 } 2109 2110 /* Enable Rx of data frames. */ 2111 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2112 2113 /* Set beacon interval. */ 2114 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2115 2116 msr = urtwn_read_1(sc, R92C_MSR); 2117 msr &= R92C_MSR_MASK; 2118 switch (ic->ic_opmode) { 2119 case IEEE80211_M_STA: 2120 /* Allow Rx from our BSSID only. */ 2121 urtwn_write_4(sc, R92C_RCR, 2122 urtwn_read_4(sc, R92C_RCR) | 2123 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2124 2125 /* Enable TSF synchronization. */ 2126 urtwn_tsf_sync_enable(sc); 2127 2128 msr |= R92C_MSR_INFRA; 2129 break; 2130 case IEEE80211_M_HOSTAP: 2131 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2132 2133 /* Allow Rx from any BSSID. */ 2134 urtwn_write_4(sc, R92C_RCR, 2135 urtwn_read_4(sc, R92C_RCR) & 2136 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2137 2138 /* Reset TSF timer to zero. */ 2139 reg = urtwn_read_4(sc, R92C_TCR); 2140 reg &= ~0x01; 2141 urtwn_write_4(sc, R92C_TCR, reg); 2142 reg |= 0x01; 2143 urtwn_write_4(sc, R92C_TCR, reg); 2144 2145 msr |= R92C_MSR_AP; 2146 break; 2147 default: 2148 msr |= R92C_MSR_ADHOC; 2149 break; 2150 } 2151 urtwn_write_1(sc, R92C_MSR, msr); 2152 2153 sifs_time = 10; 2154 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2155 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2156 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2157 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2158 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2159 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2160 2161 /* Initialize rate adaptation. */ 2162 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2163 ISSET(sc->chip, URTWN_CHIP_92EU)) 2164 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2165 else 2166 urtwn_ra_init(sc); 2167 2168 /* Turn link LED on. */ 2169 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2170 2171 /* Reset average RSSI. */ 2172 sc->avg_pwdb = -1; 2173 2174 /* Reset temperature calibration state machine. */ 2175 sc->thcal_state = 0; 2176 sc->thcal_lctemp = 0; 2177 2178 /* Start periodic calibration. */ 2179 if (!sc->sc_dying) 2180 callout_schedule(&sc->sc_calib_to, hz); 2181 break; 2182 } 2183 2184 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2185 2186 mutex_exit(&sc->sc_write_mtx); 2187 splx(s); 2188 } 2189 2190 static int 2191 urtwn_wme_update(struct ieee80211com *ic) 2192 { 2193 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2194 2195 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2196 2197 /* don't override default WME values if WME is not actually enabled */ 2198 if (!(ic->ic_flags & IEEE80211_F_WME)) 2199 return 0; 2200 2201 /* Do it in a process context. */ 2202 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2203 return 0; 2204 } 2205 2206 static void 2207 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2208 { 2209 static const uint16_t ac2reg[WME_NUM_AC] = { 2210 R92C_EDCA_BE_PARAM, 2211 R92C_EDCA_BK_PARAM, 2212 R92C_EDCA_VI_PARAM, 2213 R92C_EDCA_VO_PARAM 2214 }; 2215 struct ieee80211com *ic = &sc->sc_ic; 2216 const struct wmeParams *wmep; 2217 int ac, aifs, slottime; 2218 int s; 2219 2220 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2221 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2222 2223 s = splnet(); 2224 mutex_enter(&sc->sc_write_mtx); 2225 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2226 for (ac = 0; ac < WME_NUM_AC; ac++) { 2227 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2228 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2229 aifs = wmep->wmep_aifsn * slottime + 10; 2230 urtwn_write_4(sc, ac2reg[ac], 2231 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2232 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2233 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2234 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2235 } 2236 mutex_exit(&sc->sc_write_mtx); 2237 splx(s); 2238 } 2239 2240 static void 2241 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2242 { 2243 int pwdb; 2244 2245 URTWNHIST_FUNC(); 2246 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2247 2248 /* Convert antenna signal to percentage. */ 2249 if (rssi <= -100 || rssi >= 20) 2250 pwdb = 0; 2251 else if (rssi >= 0) 2252 pwdb = 100; 2253 else 2254 pwdb = 100 + rssi; 2255 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2256 if (rate <= 3) { 2257 /* CCK gain is smaller than OFDM/MCS gain. */ 2258 pwdb += 6; 2259 if (pwdb > 100) 2260 pwdb = 100; 2261 if (pwdb <= 14) 2262 pwdb -= 4; 2263 else if (pwdb <= 26) 2264 pwdb -= 8; 2265 else if (pwdb <= 34) 2266 pwdb -= 6; 2267 else if (pwdb <= 42) 2268 pwdb -= 2; 2269 } 2270 } 2271 if (sc->avg_pwdb == -1) /* Init. */ 2272 sc->avg_pwdb = pwdb; 2273 else if (sc->avg_pwdb < pwdb) 2274 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2275 else 2276 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2277 2278 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2279 rate, rssi, pwdb, sc->avg_pwdb); 2280 } 2281 2282 static int8_t 2283 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2284 { 2285 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2286 struct r92c_rx_phystat *phy; 2287 struct r92c_rx_cck *cck; 2288 uint8_t rpt; 2289 int8_t rssi; 2290 2291 URTWNHIST_FUNC(); 2292 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2293 2294 if (rate <= 3) { 2295 cck = (struct r92c_rx_cck *)physt; 2296 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2297 rpt = (cck->agc_rpt >> 5) & 0x3; 2298 rssi = (cck->agc_rpt & 0x1f) << 1; 2299 } else { 2300 rpt = (cck->agc_rpt >> 6) & 0x3; 2301 rssi = cck->agc_rpt & 0x3e; 2302 } 2303 rssi = cckoff[rpt] - rssi; 2304 } else { /* OFDM/HT. */ 2305 phy = (struct r92c_rx_phystat *)physt; 2306 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2307 } 2308 return rssi; 2309 } 2310 2311 static int8_t 2312 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2313 { 2314 struct r92c_rx_phystat *phy; 2315 struct r88e_rx_cck *cck; 2316 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2317 int8_t rssi; 2318 2319 URTWNHIST_FUNC(); 2320 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2321 2322 rssi = 0; 2323 if (rate <= 3) { 2324 cck = (struct r88e_rx_cck *)physt; 2325 cck_agc_rpt = cck->agc_rpt; 2326 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2327 vga_idx = cck_agc_rpt & 0x1f; 2328 switch (lna_idx) { 2329 case 7: 2330 if (vga_idx <= 27) 2331 rssi = -100 + 2* (27 - vga_idx); 2332 else 2333 rssi = -100; 2334 break; 2335 case 6: 2336 rssi = -48 + 2 * (2 - vga_idx); 2337 break; 2338 case 5: 2339 rssi = -42 + 2 * (7 - vga_idx); 2340 break; 2341 case 4: 2342 rssi = -36 + 2 * (7 - vga_idx); 2343 break; 2344 case 3: 2345 rssi = -24 + 2 * (7 - vga_idx); 2346 break; 2347 case 2: 2348 rssi = -12 + 2 * (5 - vga_idx); 2349 break; 2350 case 1: 2351 rssi = 8 - (2 * vga_idx); 2352 break; 2353 case 0: 2354 rssi = 14 - (2 * vga_idx); 2355 break; 2356 } 2357 rssi += 6; 2358 } else { /* OFDM/HT. */ 2359 phy = (struct r92c_rx_phystat *)physt; 2360 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2361 } 2362 return rssi; 2363 } 2364 2365 static void 2366 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2367 { 2368 struct ieee80211com *ic = &sc->sc_ic; 2369 struct ifnet *ifp = ic->ic_ifp; 2370 struct ieee80211_frame *wh; 2371 struct ieee80211_node *ni; 2372 struct r92c_rx_desc_usb *stat; 2373 uint32_t rxdw0, rxdw3; 2374 struct mbuf *m; 2375 uint8_t rate; 2376 int8_t rssi = 0; 2377 int s, infosz; 2378 2379 URTWNHIST_FUNC(); 2380 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2381 2382 stat = (struct r92c_rx_desc_usb *)buf; 2383 rxdw0 = le32toh(stat->rxdw0); 2384 rxdw3 = le32toh(stat->rxdw3); 2385 2386 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2387 /* 2388 * This should not happen since we setup our Rx filter 2389 * to not receive these frames. 2390 */ 2391 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2392 if_statinc(ifp, if_ierrors); 2393 return; 2394 } 2395 /* 2396 * XXX: This will drop most control packets. Do we really 2397 * want this in IEEE80211_M_MONITOR mode? 2398 */ 2399 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2400 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2401 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2402 ic->ic_stats.is_rx_tooshort++; 2403 if_statinc(ifp, if_ierrors); 2404 return; 2405 } 2406 if (__predict_false(pktlen > MCLBYTES)) { 2407 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2408 if_statinc(ifp, if_ierrors); 2409 return; 2410 } 2411 2412 rate = MS(rxdw3, R92C_RXDW3_RATE); 2413 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2414 2415 /* Get RSSI from PHY status descriptor if present. */ 2416 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2417 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2418 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2419 else 2420 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2421 /* Update our average RSSI. */ 2422 urtwn_update_avgrssi(sc, rate, rssi); 2423 } 2424 2425 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2426 pktlen, rate, infosz, rssi); 2427 2428 MGETHDR(m, M_DONTWAIT, MT_DATA); 2429 if (__predict_false(m == NULL)) { 2430 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2431 ic->ic_stats.is_rx_nobuf++; 2432 if_statinc(ifp, if_ierrors); 2433 return; 2434 } 2435 if (pktlen > (int)MHLEN) { 2436 MCLGET(m, M_DONTWAIT); 2437 if (__predict_false(!(m->m_flags & M_EXT))) { 2438 aprint_error_dev(sc->sc_dev, 2439 "couldn't allocate rx mbuf cluster\n"); 2440 m_freem(m); 2441 ic->ic_stats.is_rx_nobuf++; 2442 if_statinc(ifp, if_ierrors); 2443 return; 2444 } 2445 } 2446 2447 /* Finalize mbuf. */ 2448 m_set_rcvif(m, ifp); 2449 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2450 memcpy(mtod(m, uint8_t *), wh, pktlen); 2451 m->m_pkthdr.len = m->m_len = pktlen; 2452 2453 s = splnet(); 2454 if (__predict_false(sc->sc_drvbpf != NULL)) { 2455 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2456 2457 tap->wr_flags = 0; 2458 if (!(rxdw3 & R92C_RXDW3_HT)) { 2459 switch (rate) { 2460 /* CCK. */ 2461 case 0: tap->wr_rate = 2; break; 2462 case 1: tap->wr_rate = 4; break; 2463 case 2: tap->wr_rate = 11; break; 2464 case 3: tap->wr_rate = 22; break; 2465 /* OFDM. */ 2466 case 4: tap->wr_rate = 12; break; 2467 case 5: tap->wr_rate = 18; break; 2468 case 6: tap->wr_rate = 24; break; 2469 case 7: tap->wr_rate = 36; break; 2470 case 8: tap->wr_rate = 48; break; 2471 case 9: tap->wr_rate = 72; break; 2472 case 10: tap->wr_rate = 96; break; 2473 case 11: tap->wr_rate = 108; break; 2474 } 2475 } else if (rate >= 12) { /* MCS0~15. */ 2476 /* Bit 7 set means HT MCS instead of rate. */ 2477 tap->wr_rate = 0x80 | (rate - 12); 2478 } 2479 tap->wr_dbm_antsignal = rssi; 2480 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2481 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2482 2483 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2484 } 2485 2486 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2487 2488 /* push the frame up to the 802.11 stack */ 2489 ieee80211_input(ic, m, ni, rssi, 0); 2490 2491 /* Node is no longer needed. */ 2492 ieee80211_free_node(ni); 2493 2494 splx(s); 2495 } 2496 2497 static void 2498 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2499 { 2500 struct urtwn_rx_data *data = priv; 2501 struct urtwn_softc *sc = data->sc; 2502 struct r92c_rx_desc_usb *stat; 2503 size_t pidx = data->pidx; 2504 uint32_t rxdw0; 2505 uint8_t *buf; 2506 int len, totlen, pktlen, infosz, npkts; 2507 2508 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2509 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2510 2511 mutex_enter(&sc->sc_rx_mtx); 2512 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2513 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2514 /* Put this Rx buffer back to our free list. */ 2515 mutex_exit(&sc->sc_rx_mtx); 2516 2517 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2518 if (status == USBD_STALLED) 2519 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2520 else if (status != USBD_CANCELLED) 2521 goto resubmit; 2522 return; 2523 } 2524 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2525 2526 if (__predict_false(len < (int)sizeof(*stat))) { 2527 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2528 goto resubmit; 2529 } 2530 buf = data->buf; 2531 2532 /* Get the number of encapsulated frames. */ 2533 stat = (struct r92c_rx_desc_usb *)buf; 2534 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2535 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2536 else 2537 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2538 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2539 2540 if (npkts != 0) 2541 rnd_add_uint32(&sc->rnd_source, npkts); 2542 2543 /* Process all of them. */ 2544 while (npkts-- > 0) { 2545 if (__predict_false(len < (int)sizeof(*stat))) { 2546 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2547 len, 0, 0, 0); 2548 break; 2549 } 2550 stat = (struct r92c_rx_desc_usb *)buf; 2551 rxdw0 = le32toh(stat->rxdw0); 2552 2553 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2554 if (__predict_false(pktlen == 0)) { 2555 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2556 break; 2557 } 2558 2559 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2560 2561 /* Make sure everything fits in xfer. */ 2562 totlen = sizeof(*stat) + infosz + pktlen; 2563 if (__predict_false(totlen > len)) { 2564 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2565 (int)sizeof(*stat), infosz, pktlen, len); 2566 break; 2567 } 2568 2569 /* Process 802.11 frame. */ 2570 urtwn_rx_frame(sc, buf, pktlen); 2571 2572 /* Next chunk is 128-byte aligned. */ 2573 totlen = roundup2(totlen, 128); 2574 buf += totlen; 2575 len -= totlen; 2576 } 2577 2578 resubmit: 2579 /* Setup a new transfer. */ 2580 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2581 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2582 (void)usbd_transfer(xfer); 2583 } 2584 2585 static void 2586 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2587 { 2588 struct urtwn_tx_data *data = priv; 2589 struct urtwn_softc *sc = data->sc; 2590 struct ifnet *ifp = &sc->sc_if; 2591 size_t pidx = data->pidx; 2592 int s; 2593 2594 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2595 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2596 2597 mutex_enter(&sc->sc_tx_mtx); 2598 /* Put this Tx buffer back to our free list. */ 2599 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2600 mutex_exit(&sc->sc_tx_mtx); 2601 2602 s = splnet(); 2603 sc->tx_timer = 0; 2604 ifp->if_flags &= ~IFF_OACTIVE; 2605 2606 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2607 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2608 if (status == USBD_STALLED) { 2609 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2610 usbd_clear_endpoint_stall_async(pipe); 2611 } 2612 printf("ERROR1\n"); 2613 if_statinc(ifp, if_oerrors); 2614 } 2615 splx(s); 2616 return; 2617 } 2618 2619 if_statinc(ifp, if_opackets); 2620 urtwn_start(ifp); 2621 splx(s); 2622 2623 } 2624 2625 static int 2626 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2627 struct urtwn_tx_data *data) 2628 { 2629 struct ieee80211com *ic = &sc->sc_ic; 2630 struct ieee80211_frame *wh; 2631 struct ieee80211_key *k = NULL; 2632 struct r92c_tx_desc_usb *txd; 2633 size_t i, padsize, xferlen, txd_len; 2634 uint16_t seq, sum; 2635 uint8_t raid, type, tid; 2636 int s, hasqos, error; 2637 2638 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2639 2640 wh = mtod(m, struct ieee80211_frame *); 2641 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2642 txd_len = sizeof(*txd); 2643 2644 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2645 txd_len = 32; 2646 2647 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2648 k = ieee80211_crypto_encap(ic, ni, m); 2649 if (k == NULL) 2650 return ENOBUFS; 2651 2652 /* packet header may have moved, reset our local pointer */ 2653 wh = mtod(m, struct ieee80211_frame *); 2654 } 2655 2656 if (__predict_false(sc->sc_drvbpf != NULL)) { 2657 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2658 2659 tap->wt_flags = 0; 2660 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2661 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2662 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2663 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2664 2665 /* XXX: set tap->wt_rate? */ 2666 2667 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2668 } 2669 2670 /* non-qos data frames */ 2671 tid = R92C_TXDW1_QSEL_BE; 2672 if ((hasqos = ieee80211_has_qos(wh))) { 2673 /* data frames in 11n mode */ 2674 struct ieee80211_qosframe *qwh = (void *)wh; 2675 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2676 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2677 tid = R92C_TXDW1_QSEL_MGNT; 2678 } 2679 2680 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2681 padsize = 8; 2682 else 2683 padsize = 0; 2684 2685 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2686 padsize = 0; 2687 2688 /* Fill Tx descriptor. */ 2689 txd = (struct r92c_tx_desc_usb *)data->buf; 2690 memset(txd, 0, txd_len + padsize); 2691 2692 txd->txdw0 |= htole32( 2693 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2694 SM(R92C_TXDW0_OFFSET, txd_len)); 2695 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2696 txd->txdw0 |= htole32( 2697 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2698 } 2699 2700 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2701 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2702 2703 /* fix pad field */ 2704 if (padsize > 0) { 2705 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2706 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2707 } 2708 2709 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2710 type == IEEE80211_FC0_TYPE_DATA) { 2711 if (ic->ic_curmode == IEEE80211_MODE_11B) 2712 raid = R92C_RAID_11B; 2713 else 2714 raid = R92C_RAID_11BG; 2715 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2716 tid, raid, 0, 0); 2717 2718 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2719 txd->txdw1 |= htole32( 2720 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2721 SM(R92C_TXDW1_QSEL, tid) | 2722 SM(R92C_TXDW1_RAID, raid) | 2723 R92C_TXDW1_AGGBK); 2724 } else 2725 txd->txdw1 |= htole32( 2726 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2727 SM(R92C_TXDW1_QSEL, tid) | 2728 SM(R92C_TXDW1_RAID, raid) | 2729 R92C_TXDW1_AGGBK); 2730 2731 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2732 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2733 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2734 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2735 2736 if (hasqos) { 2737 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2738 } 2739 2740 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2741 /* for 11g */ 2742 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2743 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2744 R92C_TXDW4_HWRTSEN); 2745 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2746 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2747 R92C_TXDW4_HWRTSEN); 2748 } 2749 } 2750 /* Send RTS at OFDM24. */ 2751 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2752 txd->txdw5 |= htole32(0x0001ff00); 2753 /* Send data at OFDM54. */ 2754 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2755 txd->txdw5 |= htole32(0x13 & 0x3f); 2756 else 2757 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2758 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2759 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2760 txd->txdw1 |= htole32( 2761 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2762 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2763 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2764 2765 /* Force CCK1. */ 2766 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2767 /* Use 1Mbps */ 2768 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2769 } else { 2770 /* broadcast or multicast packets */ 2771 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2772 txd->txdw1 |= htole32( 2773 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2774 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2775 2776 /* Force CCK1. */ 2777 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2778 /* Use 1Mbps */ 2779 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2780 } 2781 /* Set sequence number */ 2782 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2783 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2784 txd->txdseq |= htole16(seq); 2785 2786 if (!hasqos) { 2787 /* Use HW sequence numbering for non-QoS frames. */ 2788 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2789 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2790 } 2791 } else { 2792 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2793 R92E_HWSEQ_SHIFT); 2794 if (!hasqos) { 2795 /* Use HW sequence numbering for non-QoS frames. */ 2796 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2797 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2798 } 2799 } 2800 2801 /* Compute Tx descriptor checksum. */ 2802 sum = 0; 2803 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2804 sum ^= ((uint16_t *)txd)[i]; 2805 txd->txdsum = sum; /* NB: already little endian. */ 2806 2807 xferlen = txd_len + m->m_pkthdr.len + padsize; 2808 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2809 2810 s = splnet(); 2811 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2812 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2813 urtwn_txeof); 2814 error = usbd_transfer(data->xfer); 2815 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2816 error != USBD_IN_PROGRESS)) { 2817 splx(s); 2818 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2819 return error; 2820 } 2821 splx(s); 2822 return 0; 2823 } 2824 2825 struct urtwn_tx_data * 2826 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2827 { 2828 struct urtwn_tx_data *data = NULL; 2829 2830 mutex_enter(&sc->sc_tx_mtx); 2831 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2832 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2833 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2834 } 2835 mutex_exit(&sc->sc_tx_mtx); 2836 2837 return data; 2838 } 2839 2840 static void 2841 urtwn_start(struct ifnet *ifp) 2842 { 2843 struct urtwn_softc *sc = ifp->if_softc; 2844 struct ieee80211com *ic = &sc->sc_ic; 2845 struct urtwn_tx_data *data; 2846 struct ether_header *eh; 2847 struct ieee80211_node *ni; 2848 struct mbuf *m; 2849 2850 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2851 2852 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2853 return; 2854 2855 data = NULL; 2856 for (;;) { 2857 /* Send pending management frames first. */ 2858 IF_POLL(&ic->ic_mgtq, m); 2859 if (m != NULL) { 2860 /* Use AC_VO for management frames. */ 2861 2862 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2863 2864 if (data == NULL) { 2865 ifp->if_flags |= IFF_OACTIVE; 2866 DPRINTFN(DBG_TX, "empty tx_free_list", 2867 0, 0, 0, 0); 2868 return; 2869 } 2870 IF_DEQUEUE(&ic->ic_mgtq, m); 2871 ni = M_GETCTX(m, struct ieee80211_node *); 2872 M_CLEARCTX(m); 2873 goto sendit; 2874 } 2875 if (ic->ic_state != IEEE80211_S_RUN) 2876 break; 2877 2878 /* Encapsulate and send data frames. */ 2879 IFQ_POLL(&ifp->if_snd, m); 2880 if (m == NULL) 2881 break; 2882 2883 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2884 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2885 uint8_t qid = WME_AC_BE; 2886 if (ieee80211_has_qos(wh)) { 2887 /* data frames in 11n mode */ 2888 struct ieee80211_qosframe *qwh = (void *)wh; 2889 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2890 qid = TID_TO_WME_AC(tid); 2891 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2892 qid = WME_AC_VO; 2893 } 2894 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2895 2896 if (data == NULL) { 2897 ifp->if_flags |= IFF_OACTIVE; 2898 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2899 return; 2900 } 2901 IFQ_DEQUEUE(&ifp->if_snd, m); 2902 2903 if (m->m_len < (int)sizeof(*eh) && 2904 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2905 printf("ERROR6\n"); 2906 if_statinc(ifp, if_oerrors); 2907 continue; 2908 } 2909 eh = mtod(m, struct ether_header *); 2910 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2911 if (ni == NULL) { 2912 m_freem(m); 2913 printf("ERROR5\n"); 2914 if_statinc(ifp, if_oerrors); 2915 continue; 2916 } 2917 2918 bpf_mtap(ifp, m, BPF_D_OUT); 2919 2920 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2921 ieee80211_free_node(ni); 2922 printf("ERROR4\n"); 2923 if_statinc(ifp, if_oerrors); 2924 continue; 2925 } 2926 sendit: 2927 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2928 2929 if (urtwn_tx(sc, m, ni, data) != 0) { 2930 m_freem(m); 2931 ieee80211_free_node(ni); 2932 printf("ERROR3\n"); 2933 if_statinc(ifp, if_oerrors); 2934 continue; 2935 } 2936 m_freem(m); 2937 ieee80211_free_node(ni); 2938 sc->tx_timer = 5; 2939 ifp->if_timer = 1; 2940 } 2941 } 2942 2943 static void 2944 urtwn_watchdog(struct ifnet *ifp) 2945 { 2946 struct urtwn_softc *sc = ifp->if_softc; 2947 2948 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2949 2950 ifp->if_timer = 0; 2951 2952 if (sc->tx_timer > 0) { 2953 if (--sc->tx_timer == 0) { 2954 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2955 /* urtwn_init(ifp); XXX needs a process context! */ 2956 printf("ERROR2\n"); 2957 if_statinc(ifp, if_oerrors); 2958 return; 2959 } 2960 ifp->if_timer = 1; 2961 } 2962 ieee80211_watchdog(&sc->sc_ic); 2963 } 2964 2965 static int 2966 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2967 { 2968 struct urtwn_softc *sc = ifp->if_softc; 2969 struct ieee80211com *ic = &sc->sc_ic; 2970 int s, error = 0; 2971 2972 URTWNHIST_FUNC(); 2973 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2974 0, 0); 2975 2976 s = splnet(); 2977 2978 switch (cmd) { 2979 case SIOCSIFFLAGS: 2980 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2981 break; 2982 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2983 case IFF_UP | IFF_RUNNING: 2984 break; 2985 case IFF_UP: 2986 urtwn_init(ifp); 2987 break; 2988 case IFF_RUNNING: 2989 urtwn_stop(ifp, 1); 2990 break; 2991 case 0: 2992 break; 2993 } 2994 break; 2995 2996 case SIOCADDMULTI: 2997 case SIOCDELMULTI: 2998 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2999 /* setup multicast filter, etc */ 3000 error = 0; 3001 } 3002 break; 3003 3004 case SIOCS80211CHANNEL: 3005 /* 3006 * This allows for fast channel switching in monitor mode 3007 * (used by kismet). In IBSS mode, we must explicitly reset 3008 * the interface to generate a new beacon frame. 3009 */ 3010 error = ieee80211_ioctl(ic, cmd, data); 3011 if (error == ENETRESET && 3012 ic->ic_opmode == IEEE80211_M_MONITOR) { 3013 urtwn_set_chan(sc, ic->ic_curchan, 3014 IEEE80211_HTINFO_2NDCHAN_NONE); 3015 error = 0; 3016 } 3017 break; 3018 3019 default: 3020 error = ieee80211_ioctl(ic, cmd, data); 3021 break; 3022 } 3023 if (error == ENETRESET) { 3024 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3025 (IFF_UP | IFF_RUNNING) && 3026 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3027 urtwn_init(ifp); 3028 } 3029 error = 0; 3030 } 3031 3032 splx(s); 3033 3034 return error; 3035 } 3036 3037 static __inline int 3038 urtwn_power_on(struct urtwn_softc *sc) 3039 { 3040 3041 return sc->sc_power_on(sc); 3042 } 3043 3044 static int 3045 urtwn_r92c_power_on(struct urtwn_softc *sc) 3046 { 3047 uint32_t reg; 3048 int ntries; 3049 3050 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3051 3052 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3053 3054 /* Wait for autoload done bit. */ 3055 for (ntries = 0; ntries < 1000; ntries++) { 3056 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3057 break; 3058 DELAY(5); 3059 } 3060 if (ntries == 1000) { 3061 aprint_error_dev(sc->sc_dev, 3062 "timeout waiting for chip autoload\n"); 3063 return ETIMEDOUT; 3064 } 3065 3066 /* Unlock ISO/CLK/Power control register. */ 3067 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3068 /* Move SPS into PWM mode. */ 3069 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3070 DELAY(5); 3071 3072 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3073 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3074 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3075 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3076 DELAY(100); 3077 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3078 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3079 ~R92C_SYS_ISO_CTRL_MD2PP); 3080 } 3081 3082 /* Auto enable WLAN. */ 3083 urtwn_write_2(sc, R92C_APS_FSMCO, 3084 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3085 for (ntries = 0; ntries < 1000; ntries++) { 3086 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3087 R92C_APS_FSMCO_APFM_ONMAC)) 3088 break; 3089 DELAY(100); 3090 } 3091 if (ntries == 1000) { 3092 aprint_error_dev(sc->sc_dev, 3093 "timeout waiting for MAC auto ON\n"); 3094 return ETIMEDOUT; 3095 } 3096 3097 /* Enable radio, GPIO and LED functions. */ 3098 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3099 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3100 urtwn_write_2(sc, R92C_APS_FSMCO, 3101 R92C_APS_FSMCO_AFSM_HSUS | 3102 R92C_APS_FSMCO_PDN_EN | 3103 R92C_APS_FSMCO_PFM_ALDN); 3104 3105 /* Release RF digital isolation. */ 3106 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3107 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3108 3109 /* Initialize MAC. */ 3110 urtwn_write_1(sc, R92C_APSD_CTRL, 3111 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3112 for (ntries = 0; ntries < 200; ntries++) { 3113 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3114 R92C_APSD_CTRL_OFF_STATUS)) 3115 break; 3116 DELAY(5); 3117 } 3118 if (ntries == 200) { 3119 aprint_error_dev(sc->sc_dev, 3120 "timeout waiting for MAC initialization\n"); 3121 return ETIMEDOUT; 3122 } 3123 3124 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3125 reg = urtwn_read_2(sc, R92C_CR); 3126 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3127 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3128 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3129 R92C_CR_ENSEC; 3130 urtwn_write_2(sc, R92C_CR, reg); 3131 3132 urtwn_write_1(sc, 0xfe10, 0x19); 3133 return 0; 3134 } 3135 3136 static int 3137 urtwn_r92e_power_on(struct urtwn_softc *sc) 3138 { 3139 uint32_t reg; 3140 uint32_t val; 3141 int ntries; 3142 3143 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3144 3145 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3146 3147 /* Enable radio, GPIO and LED functions. */ 3148 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3149 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3150 urtwn_write_2(sc, R92C_APS_FSMCO, 3151 R92C_APS_FSMCO_AFSM_HSUS | 3152 R92C_APS_FSMCO_PDN_EN | 3153 R92C_APS_FSMCO_PFM_ALDN); 3154 3155 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3156 /* LDO. */ 3157 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3158 } 3159 else { 3160 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3161 R92C_SYS_SWR_CTRL2) & 0xffff); 3162 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3163 } 3164 3165 for (ntries = 0; ntries < 2; ntries++) { 3166 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3167 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3168 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3169 R92C_AFE_CTRL4)); 3170 } 3171 3172 /* Reset BB. */ 3173 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3174 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3175 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3176 3177 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3178 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3179 3180 /* Disable HWPDN. */ 3181 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3182 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3183 3184 /* Disable WL suspend. */ 3185 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3186 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3187 R92C_APS_FSMCO_AFSM_HSUS)); 3188 3189 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3190 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3191 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3192 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3193 for (ntries = 0; ntries < 10000; ntries++) { 3194 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3195 R92C_APS_FSMCO_APFM_ONMAC; 3196 if (val == 0x0) 3197 break; 3198 DELAY(10); 3199 } 3200 if (ntries == 10000) { 3201 aprint_error_dev(sc->sc_dev, 3202 "timeout waiting for chip power up\n"); 3203 return ETIMEDOUT; 3204 } 3205 3206 urtwn_write_2(sc, R92C_CR, 0x00); 3207 reg = urtwn_read_2(sc, R92C_CR); 3208 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3209 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3210 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3211 urtwn_write_2(sc, R92C_CR, reg); 3212 3213 return 0; 3214 } 3215 3216 static int 3217 urtwn_r88e_power_on(struct urtwn_softc *sc) 3218 { 3219 uint32_t reg; 3220 uint8_t val; 3221 int ntries; 3222 3223 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3224 3225 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3226 3227 /* Wait for power ready bit. */ 3228 for (ntries = 0; ntries < 5000; ntries++) { 3229 val = urtwn_read_1(sc, 0x6) & 0x2; 3230 if (val == 0x2) 3231 break; 3232 DELAY(10); 3233 } 3234 if (ntries == 5000) { 3235 aprint_error_dev(sc->sc_dev, 3236 "timeout waiting for chip power up\n"); 3237 return ETIMEDOUT; 3238 } 3239 3240 /* Reset BB. */ 3241 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3242 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3243 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3244 3245 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3246 3247 /* Disable HWPDN. */ 3248 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3249 3250 /* Disable WL suspend. */ 3251 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3252 3253 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3254 for (ntries = 0; ntries < 5000; ntries++) { 3255 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3256 break; 3257 DELAY(10); 3258 } 3259 if (ntries == 5000) 3260 return ETIMEDOUT; 3261 3262 /* Enable LDO normal mode. */ 3263 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3264 3265 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3266 urtwn_write_2(sc, R92C_CR, 0); 3267 reg = urtwn_read_2(sc, R92C_CR); 3268 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3269 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3270 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3271 urtwn_write_2(sc, R92C_CR, reg); 3272 3273 return 0; 3274 } 3275 3276 static int __noinline 3277 urtwn_llt_init(struct urtwn_softc *sc) 3278 { 3279 size_t i, page_count, pktbuf_count; 3280 uint32_t val; 3281 int error; 3282 3283 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3284 3285 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3286 3287 if (sc->chip & URTWN_CHIP_88E) 3288 page_count = R88E_TX_PAGE_COUNT; 3289 else if (sc->chip & URTWN_CHIP_92EU) 3290 page_count = R92E_TX_PAGE_COUNT; 3291 else 3292 page_count = R92C_TX_PAGE_COUNT; 3293 if (sc->chip & URTWN_CHIP_88E) 3294 pktbuf_count = R88E_TXPKTBUF_COUNT; 3295 else if (sc->chip & URTWN_CHIP_92EU) 3296 pktbuf_count = R88E_TXPKTBUF_COUNT; 3297 else 3298 pktbuf_count = R92C_TXPKTBUF_COUNT; 3299 3300 if (sc->chip & URTWN_CHIP_92EU) { 3301 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3302 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3303 DELAY(100); 3304 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3305 if (val & R92E_AUTO_LLT_EN) 3306 return EIO; 3307 return 0; 3308 } 3309 3310 /* Reserve pages [0; page_count]. */ 3311 for (i = 0; i < page_count; i++) { 3312 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3313 return error; 3314 } 3315 /* NB: 0xff indicates end-of-list. */ 3316 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3317 return error; 3318 /* 3319 * Use pages [page_count + 1; pktbuf_count - 1] 3320 * as ring buffer. 3321 */ 3322 for (++i; i < pktbuf_count - 1; i++) { 3323 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3324 return error; 3325 } 3326 /* Make the last page point to the beginning of the ring buffer. */ 3327 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3328 return error; 3329 } 3330 3331 static void 3332 urtwn_fw_reset(struct urtwn_softc *sc) 3333 { 3334 uint16_t reg; 3335 int ntries; 3336 3337 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3338 3339 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3340 3341 /* Tell 8051 to reset itself. */ 3342 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3343 3344 /* Wait until 8051 resets by itself. */ 3345 for (ntries = 0; ntries < 100; ntries++) { 3346 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3347 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3348 return; 3349 DELAY(50); 3350 } 3351 /* Force 8051 reset. */ 3352 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3353 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3354 } 3355 3356 static void 3357 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3358 { 3359 uint16_t reg; 3360 3361 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3362 3363 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3364 3365 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3366 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3367 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3368 } 3369 DELAY(50); 3370 3371 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3372 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3373 DELAY(50); 3374 3375 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3376 DELAY(50); 3377 3378 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3379 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3380 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3381 } 3382 DELAY(50); 3383 3384 } 3385 3386 static int 3387 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3388 { 3389 uint32_t reg; 3390 int off, mlen, error = 0; 3391 3392 URTWNHIST_FUNC(); 3393 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3394 page, (uintptr_t)buf, len, 0); 3395 3396 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3397 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3398 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3399 3400 off = R92C_FW_START_ADDR; 3401 while (len > 0) { 3402 if (len > 196) 3403 mlen = 196; 3404 else if (len > 4) 3405 mlen = 4; 3406 else 3407 mlen = 1; 3408 error = urtwn_write_region(sc, off, buf, mlen); 3409 if (error != 0) 3410 break; 3411 off += mlen; 3412 buf += mlen; 3413 len -= mlen; 3414 } 3415 return error; 3416 } 3417 3418 static int __noinline 3419 urtwn_load_firmware(struct urtwn_softc *sc) 3420 { 3421 firmware_handle_t fwh; 3422 const struct r92c_fw_hdr *hdr; 3423 const char *name; 3424 u_char *fw, *ptr; 3425 size_t len; 3426 uint32_t reg; 3427 int mlen, ntries, page, error; 3428 3429 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3430 3431 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3432 3433 /* Read firmware image from the filesystem. */ 3434 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3435 name = "rtl8188eufw.bin"; 3436 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3437 name = "rtl8192eefw.bin"; 3438 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3439 URTWN_CHIP_UMC_A_CUT) 3440 name = "rtl8192cfwU.bin"; 3441 else 3442 name = "rtl8192cfw.bin"; 3443 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3444 aprint_error_dev(sc->sc_dev, 3445 "failed load firmware of file %s (error %d)\n", name, 3446 error); 3447 return error; 3448 } 3449 const size_t fwlen = len = firmware_get_size(fwh); 3450 fw = firmware_malloc(len); 3451 if (fw == NULL) { 3452 aprint_error_dev(sc->sc_dev, 3453 "failed to allocate firmware memory\n"); 3454 firmware_close(fwh); 3455 return ENOMEM; 3456 } 3457 error = firmware_read(fwh, 0, fw, len); 3458 firmware_close(fwh); 3459 if (error != 0) { 3460 aprint_error_dev(sc->sc_dev, 3461 "failed to read firmware (error %d)\n", error); 3462 firmware_free(fw, fwlen); 3463 return error; 3464 } 3465 3466 len = fwlen; 3467 ptr = fw; 3468 hdr = (const struct r92c_fw_hdr *)ptr; 3469 /* Check if there is a valid FW header and skip it. */ 3470 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3471 (le16toh(hdr->signature) >> 4) == 0x88e || 3472 (le16toh(hdr->signature) >> 4) == 0x92e || 3473 (le16toh(hdr->signature) >> 4) == 0x92c) { 3474 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3475 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3476 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3477 hdr->month, hdr->date, hdr->hour, hdr->minute); 3478 ptr += sizeof(*hdr); 3479 len -= sizeof(*hdr); 3480 } 3481 3482 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3483 /* Reset MCU ready status */ 3484 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3485 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3486 ISSET(sc->chip, URTWN_CHIP_92EU)) 3487 urtwn_r88e_fw_reset(sc); 3488 else 3489 urtwn_fw_reset(sc); 3490 } 3491 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3492 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3493 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3494 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3495 R92C_SYS_FUNC_EN_CPUEN); 3496 } 3497 3498 /* download enabled */ 3499 urtwn_write_1(sc, R92C_MCUFWDL, 3500 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3501 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3502 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3503 3504 /* Reset the FWDL checksum. */ 3505 urtwn_write_1(sc, R92C_MCUFWDL, 3506 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3507 3508 DELAY(50); 3509 /* download firmware */ 3510 for (page = 0; len > 0; page++) { 3511 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3512 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3513 if (error != 0) { 3514 aprint_error_dev(sc->sc_dev, 3515 "could not load firmware page %d\n", page); 3516 goto fail; 3517 } 3518 ptr += mlen; 3519 len -= mlen; 3520 } 3521 3522 /* download disable */ 3523 urtwn_write_1(sc, R92C_MCUFWDL, 3524 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3525 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3526 3527 /* Wait for checksum report. */ 3528 for (ntries = 0; ntries < 1000; ntries++) { 3529 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3530 break; 3531 DELAY(5); 3532 } 3533 if (ntries == 1000) { 3534 aprint_error_dev(sc->sc_dev, 3535 "timeout waiting for checksum report\n"); 3536 error = ETIMEDOUT; 3537 goto fail; 3538 } 3539 3540 /* Wait for firmware readiness. */ 3541 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3542 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3543 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3544 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3545 ISSET(sc->chip, URTWN_CHIP_92EU)) 3546 urtwn_r88e_fw_reset(sc); 3547 for (ntries = 0; ntries < 6000; ntries++) { 3548 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3549 break; 3550 DELAY(5); 3551 } 3552 if (ntries == 6000) { 3553 aprint_error_dev(sc->sc_dev, 3554 "timeout waiting for firmware readiness\n"); 3555 error = ETIMEDOUT; 3556 goto fail; 3557 } 3558 fail: 3559 firmware_free(fw, fwlen); 3560 return error; 3561 } 3562 3563 static __inline int 3564 urtwn_dma_init(struct urtwn_softc *sc) 3565 { 3566 3567 return sc->sc_dma_init(sc); 3568 } 3569 3570 static int 3571 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3572 { 3573 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3574 uint32_t reg; 3575 int error; 3576 3577 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3578 3579 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3580 3581 /* Initialize LLT table. */ 3582 error = urtwn_llt_init(sc); 3583 if (error != 0) 3584 return error; 3585 3586 /* Get Tx queues to USB endpoints mapping. */ 3587 hashq = hasnq = haslq = 0; 3588 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3589 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3590 if (MS(reg, R92C_USB_EP_HQ) != 0) 3591 hashq = 1; 3592 if (MS(reg, R92C_USB_EP_NQ) != 0) 3593 hasnq = 1; 3594 if (MS(reg, R92C_USB_EP_LQ) != 0) 3595 haslq = 1; 3596 nqueues = hashq + hasnq + haslq; 3597 if (nqueues == 0) 3598 return EIO; 3599 /* Get the number of pages for each queue. */ 3600 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3601 /* The remaining pages are assigned to the high priority queue. */ 3602 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3603 3604 /* Set number of pages for normal priority queue. */ 3605 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3606 urtwn_write_4(sc, R92C_RQPN, 3607 /* Set number of pages for public queue. */ 3608 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3609 /* Set number of pages for high priority queue. */ 3610 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3611 /* Set number of pages for low priority queue. */ 3612 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3613 /* Load values. */ 3614 R92C_RQPN_LD); 3615 3616 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3617 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3618 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3619 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3620 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3621 3622 /* Set queue to USB pipe mapping. */ 3623 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3624 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3625 if (nqueues == 1) { 3626 if (hashq) { 3627 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3628 } else if (hasnq) { 3629 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3630 } else { 3631 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3632 } 3633 } else if (nqueues == 2) { 3634 /* All 2-endpoints configs have a high priority queue. */ 3635 if (!hashq) { 3636 return EIO; 3637 } 3638 if (hasnq) { 3639 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3640 } else { 3641 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3642 } 3643 } else { 3644 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3645 } 3646 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3647 3648 /* Set Tx/Rx transfer page boundary. */ 3649 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3650 3651 /* Set Tx/Rx transfer page size. */ 3652 urtwn_write_1(sc, R92C_PBP, 3653 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3654 return 0; 3655 } 3656 3657 static int 3658 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3659 { 3660 usb_interface_descriptor_t *id; 3661 uint32_t reg; 3662 int nqueues; 3663 int error; 3664 3665 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3666 3667 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3668 3669 /* Initialize LLT table. */ 3670 error = urtwn_llt_init(sc); 3671 if (error != 0) 3672 return error; 3673 3674 /* Get Tx queues to USB endpoints mapping. */ 3675 id = usbd_get_interface_descriptor(sc->sc_iface); 3676 nqueues = id->bNumEndpoints - 1; 3677 if (nqueues == 0) 3678 return EIO; 3679 3680 /* Set number of pages for normal priority queue. */ 3681 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3682 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3683 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3684 3685 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3686 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3687 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3688 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3689 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3690 3691 /* Set queue to USB pipe mapping. */ 3692 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3693 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3694 if (nqueues == 1) 3695 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3696 else if (nqueues == 2) 3697 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3698 else 3699 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3700 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3701 3702 /* Set Tx/Rx transfer page boundary. */ 3703 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3704 3705 /* Set Tx/Rx transfer page size. */ 3706 urtwn_write_1(sc, R92C_PBP, 3707 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3708 3709 return 0; 3710 } 3711 3712 static void __noinline 3713 urtwn_mac_init(struct urtwn_softc *sc) 3714 { 3715 size_t i; 3716 3717 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3718 3719 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3720 3721 /* Write MAC initialization values. */ 3722 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3723 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3724 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3725 rtl8188eu_mac[i].val); 3726 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3727 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3728 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3729 rtl8192eu_mac[i].val); 3730 } else { 3731 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3732 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3733 rtl8192cu_mac[i].val); 3734 } 3735 } 3736 3737 static void __noinline 3738 urtwn_bb_init(struct urtwn_softc *sc) 3739 { 3740 const struct rtwn_bb_prog *prog; 3741 uint32_t reg; 3742 uint8_t crystalcap; 3743 size_t i; 3744 3745 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3746 3747 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3748 3749 /* Enable BB and RF. */ 3750 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3751 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3752 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3753 R92C_SYS_FUNC_EN_DIO_RF); 3754 3755 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3756 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3757 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3758 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3759 } 3760 3761 urtwn_write_1(sc, R92C_RF_CTRL, 3762 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3763 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3764 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3765 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3766 3767 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3768 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3769 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3770 urtwn_write_1(sc, 0x15, 0xe9); 3771 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3772 } 3773 3774 /* Select BB programming based on board type. */ 3775 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3776 prog = &rtl8188eu_bb_prog; 3777 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3778 prog = &rtl8192eu_bb_prog; 3779 else if (!(sc->chip & URTWN_CHIP_92C)) { 3780 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3781 prog = &rtl8188ce_bb_prog; 3782 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3783 prog = &rtl8188ru_bb_prog; 3784 } else { 3785 prog = &rtl8188cu_bb_prog; 3786 } 3787 } else { 3788 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3789 prog = &rtl8192ce_bb_prog; 3790 } else { 3791 prog = &rtl8192cu_bb_prog; 3792 } 3793 } 3794 /* Write BB initialization values. */ 3795 for (i = 0; i < prog->count; i++) { 3796 /* additional delay depend on registers */ 3797 switch (prog->regs[i]) { 3798 case 0xfe: 3799 urtwn_delay_ms(sc, 50); 3800 break; 3801 case 0xfd: 3802 urtwn_delay_ms(sc, 5); 3803 break; 3804 case 0xfc: 3805 urtwn_delay_ms(sc, 1); 3806 break; 3807 case 0xfb: 3808 DELAY(50); 3809 break; 3810 case 0xfa: 3811 DELAY(5); 3812 break; 3813 case 0xf9: 3814 DELAY(1); 3815 break; 3816 } 3817 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3818 DELAY(1); 3819 } 3820 3821 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3822 /* 8192C 1T only configuration. */ 3823 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3824 reg = (reg & ~0x00000003) | 0x2; 3825 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3826 3827 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3828 reg = (reg & ~0x00300033) | 0x00200022; 3829 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3830 3831 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3832 reg = (reg & ~0xff000000) | (0x45 << 24); 3833 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3834 3835 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3836 reg = (reg & ~0x000000ff) | 0x23; 3837 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3838 3839 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3840 reg = (reg & ~0x00000030) | (1 << 4); 3841 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3842 3843 reg = urtwn_bb_read(sc, 0xe74); 3844 reg = (reg & ~0x0c000000) | (2 << 26); 3845 urtwn_bb_write(sc, 0xe74, reg); 3846 reg = urtwn_bb_read(sc, 0xe78); 3847 reg = (reg & ~0x0c000000) | (2 << 26); 3848 urtwn_bb_write(sc, 0xe78, reg); 3849 reg = urtwn_bb_read(sc, 0xe7c); 3850 reg = (reg & ~0x0c000000) | (2 << 26); 3851 urtwn_bb_write(sc, 0xe7c, reg); 3852 reg = urtwn_bb_read(sc, 0xe80); 3853 reg = (reg & ~0x0c000000) | (2 << 26); 3854 urtwn_bb_write(sc, 0xe80, reg); 3855 reg = urtwn_bb_read(sc, 0xe88); 3856 reg = (reg & ~0x0c000000) | (2 << 26); 3857 urtwn_bb_write(sc, 0xe88, reg); 3858 } 3859 3860 /* Write AGC values. */ 3861 for (i = 0; i < prog->agccount; i++) { 3862 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3863 DELAY(1); 3864 } 3865 3866 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3867 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3868 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3869 DELAY(1); 3870 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3871 DELAY(1); 3872 } 3873 3874 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3875 crystalcap = sc->r88e_rom[0xb9]; 3876 if (crystalcap == 0x00) 3877 crystalcap = 0x20; 3878 crystalcap &= 0x3f; 3879 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3880 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3881 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3882 crystalcap | crystalcap << 6)); 3883 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3884 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3885 crystalcap = sc->r88e_rom[0xb9]; 3886 if (crystalcap == 0xff) 3887 crystalcap = 0x20; 3888 crystalcap &= 0x3f; 3889 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3890 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3891 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3892 crystalcap | crystalcap << 6)); 3893 } else { 3894 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3895 R92C_HSSI_PARAM2_CCK_HIPWR) { 3896 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3897 } 3898 } 3899 } 3900 3901 static void __noinline 3902 urtwn_rf_init(struct urtwn_softc *sc) 3903 { 3904 const struct rtwn_rf_prog *prog; 3905 uint32_t reg, mask, saved; 3906 size_t i, j, idx; 3907 3908 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3909 3910 /* Select RF programming based on board type. */ 3911 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3912 prog = rtl8188eu_rf_prog; 3913 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3914 prog = rtl8192eu_rf_prog; 3915 else if (!(sc->chip & URTWN_CHIP_92C)) { 3916 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3917 prog = rtl8188ce_rf_prog; 3918 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3919 prog = rtl8188ru_rf_prog; 3920 } else { 3921 prog = rtl8188cu_rf_prog; 3922 } 3923 } else { 3924 prog = rtl8192ce_rf_prog; 3925 } 3926 3927 for (i = 0; i < sc->nrxchains; i++) { 3928 /* Save RF_ENV control type. */ 3929 idx = i / 2; 3930 mask = 0xffffU << ((i % 2) * 16); 3931 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3932 3933 /* Set RF_ENV enable. */ 3934 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3935 reg |= 0x100000; 3936 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3937 DELAY(50); 3938 3939 /* Set RF_ENV output high. */ 3940 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3941 reg |= 0x10; 3942 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3943 DELAY(50); 3944 3945 /* Set address and data lengths of RF registers. */ 3946 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3947 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3948 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3949 DELAY(50); 3950 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3951 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3952 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3953 DELAY(50); 3954 3955 /* Write RF initialization values for this chain. */ 3956 for (j = 0; j < prog[i].count; j++) { 3957 if (prog[i].regs[j] >= 0xf9 && 3958 prog[i].regs[j] <= 0xfe) { 3959 /* 3960 * These are fake RF registers offsets that 3961 * indicate a delay is required. 3962 */ 3963 urtwn_delay_ms(sc, 50); 3964 continue; 3965 } 3966 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3967 DELAY(5); 3968 } 3969 3970 /* Restore RF_ENV control type. */ 3971 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3972 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3973 } 3974 3975 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3976 URTWN_CHIP_UMC_A_CUT) { 3977 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3978 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3979 } 3980 3981 /* Cache RF register CHNLBW. */ 3982 for (i = 0; i < 2; i++) { 3983 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3984 } 3985 } 3986 3987 static void __noinline 3988 urtwn_cam_init(struct urtwn_softc *sc) 3989 { 3990 uint32_t content, command; 3991 uint8_t idx; 3992 size_t i; 3993 3994 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3995 3996 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3997 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3998 return; 3999 4000 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4001 content = (idx & 3) 4002 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4003 | R92C_CAM_VALID; 4004 4005 command = R92C_CAMCMD_POLLING 4006 | R92C_CAMCMD_WRITE 4007 | R92C_CAM_CTL0(idx); 4008 4009 urtwn_write_4(sc, R92C_CAMWRITE, content); 4010 urtwn_write_4(sc, R92C_CAMCMD, command); 4011 } 4012 4013 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4014 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4015 if (i == 0) { 4016 content = (idx & 3) 4017 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4018 | R92C_CAM_VALID; 4019 } else { 4020 content = 0; 4021 } 4022 4023 command = R92C_CAMCMD_POLLING 4024 | R92C_CAMCMD_WRITE 4025 | R92C_CAM_CTL0(idx) 4026 | i; 4027 4028 urtwn_write_4(sc, R92C_CAMWRITE, content); 4029 urtwn_write_4(sc, R92C_CAMCMD, command); 4030 } 4031 } 4032 4033 /* Invalidate all CAM entries. */ 4034 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4035 } 4036 4037 static void __noinline 4038 urtwn_pa_bias_init(struct urtwn_softc *sc) 4039 { 4040 uint8_t reg; 4041 size_t i; 4042 4043 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4044 4045 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4046 4047 for (i = 0; i < sc->nrxchains; i++) { 4048 if (sc->pa_setting & (1U << i)) 4049 continue; 4050 4051 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4052 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4053 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4054 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4055 } 4056 if (!(sc->pa_setting & 0x10)) { 4057 reg = urtwn_read_1(sc, 0x16); 4058 reg = (reg & ~0xf0) | 0x90; 4059 urtwn_write_1(sc, 0x16, reg); 4060 } 4061 } 4062 4063 static void __noinline 4064 urtwn_rxfilter_init(struct urtwn_softc *sc) 4065 { 4066 4067 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4068 4069 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4070 4071 /* Initialize Rx filter. */ 4072 /* TODO: use better filter for monitor mode. */ 4073 urtwn_write_4(sc, R92C_RCR, 4074 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4075 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4076 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4077 /* Accept all multicast frames. */ 4078 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4079 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4080 /* Accept all management frames. */ 4081 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4082 /* Reject all control frames. */ 4083 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4084 /* Accept all data frames. */ 4085 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4086 } 4087 4088 static void __noinline 4089 urtwn_edca_init(struct urtwn_softc *sc) 4090 { 4091 4092 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4093 4094 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4095 4096 /* set spec SIFS (used in NAV) */ 4097 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4098 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4099 4100 /* set SIFS CCK/OFDM */ 4101 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4102 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4103 4104 /* TXOP */ 4105 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4106 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4107 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4108 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4109 } 4110 4111 static void 4112 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4113 uint16_t power[URTWN_RIDX_COUNT]) 4114 { 4115 uint32_t reg; 4116 4117 URTWNHIST_FUNC(); 4118 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4119 4120 /* Write per-CCK rate Tx power. */ 4121 if (chain == 0) { 4122 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4123 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4124 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4125 4126 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4127 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4128 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4129 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4130 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4131 } else { 4132 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4133 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4134 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4135 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4136 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4137 4138 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4139 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4140 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4141 } 4142 /* Write per-OFDM rate Tx power. */ 4143 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4144 SM(R92C_TXAGC_RATE06, power[ 4]) | 4145 SM(R92C_TXAGC_RATE09, power[ 5]) | 4146 SM(R92C_TXAGC_RATE12, power[ 6]) | 4147 SM(R92C_TXAGC_RATE18, power[ 7])); 4148 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4149 SM(R92C_TXAGC_RATE24, power[ 8]) | 4150 SM(R92C_TXAGC_RATE36, power[ 9]) | 4151 SM(R92C_TXAGC_RATE48, power[10]) | 4152 SM(R92C_TXAGC_RATE54, power[11])); 4153 /* Write per-MCS Tx power. */ 4154 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4155 SM(R92C_TXAGC_MCS00, power[12]) | 4156 SM(R92C_TXAGC_MCS01, power[13]) | 4157 SM(R92C_TXAGC_MCS02, power[14]) | 4158 SM(R92C_TXAGC_MCS03, power[15])); 4159 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4160 SM(R92C_TXAGC_MCS04, power[16]) | 4161 SM(R92C_TXAGC_MCS05, power[17]) | 4162 SM(R92C_TXAGC_MCS06, power[18]) | 4163 SM(R92C_TXAGC_MCS07, power[19])); 4164 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4165 SM(R92C_TXAGC_MCS08, power[20]) | 4166 SM(R92C_TXAGC_MCS09, power[21]) | 4167 SM(R92C_TXAGC_MCS10, power[22]) | 4168 SM(R92C_TXAGC_MCS11, power[23])); 4169 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4170 SM(R92C_TXAGC_MCS12, power[24]) | 4171 SM(R92C_TXAGC_MCS13, power[25]) | 4172 SM(R92C_TXAGC_MCS14, power[26]) | 4173 SM(R92C_TXAGC_MCS15, power[27])); 4174 } 4175 4176 static void 4177 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4178 uint16_t power[URTWN_RIDX_COUNT]) 4179 { 4180 struct r92c_rom *rom = &sc->rom; 4181 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4182 const struct rtwn_txpwr *base; 4183 int ridx, group; 4184 4185 URTWNHIST_FUNC(); 4186 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4187 4188 /* Determine channel group. */ 4189 if (chan <= 3) { 4190 group = 0; 4191 } else if (chan <= 9) { 4192 group = 1; 4193 } else { 4194 group = 2; 4195 } 4196 4197 /* Get original Tx power based on board type and RF chain. */ 4198 if (!(sc->chip & URTWN_CHIP_92C)) { 4199 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4200 base = &rtl8188ru_txagc[chain]; 4201 } else { 4202 base = &rtl8192cu_txagc[chain]; 4203 } 4204 } else { 4205 base = &rtl8192cu_txagc[chain]; 4206 } 4207 4208 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4209 if (sc->regulatory == 0) { 4210 for (ridx = 0; ridx <= 3; ridx++) { 4211 power[ridx] = base->pwr[0][ridx]; 4212 } 4213 } 4214 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4215 if (sc->regulatory == 3) { 4216 power[ridx] = base->pwr[0][ridx]; 4217 /* Apply vendor limits. */ 4218 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4219 maxpow = rom->ht40_max_pwr[group]; 4220 } else { 4221 maxpow = rom->ht20_max_pwr[group]; 4222 } 4223 maxpow = (maxpow >> (chain * 4)) & 0xf; 4224 if (power[ridx] > maxpow) { 4225 power[ridx] = maxpow; 4226 } 4227 } else if (sc->regulatory == 1) { 4228 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4229 power[ridx] = base->pwr[group][ridx]; 4230 } 4231 } else if (sc->regulatory != 2) { 4232 power[ridx] = base->pwr[0][ridx]; 4233 } 4234 } 4235 4236 /* Compute per-CCK rate Tx power. */ 4237 cckpow = rom->cck_tx_pwr[chain][group]; 4238 for (ridx = 0; ridx <= 3; ridx++) { 4239 power[ridx] += cckpow; 4240 if (power[ridx] > R92C_MAX_TX_PWR) { 4241 power[ridx] = R92C_MAX_TX_PWR; 4242 } 4243 } 4244 4245 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4246 if (sc->ntxchains > 1) { 4247 /* Apply reduction for 2 spatial streams. */ 4248 diff = rom->ht40_2s_tx_pwr_diff[group]; 4249 diff = (diff >> (chain * 4)) & 0xf; 4250 htpow = (htpow > diff) ? htpow - diff : 0; 4251 } 4252 4253 /* Compute per-OFDM rate Tx power. */ 4254 diff = rom->ofdm_tx_pwr_diff[group]; 4255 diff = (diff >> (chain * 4)) & 0xf; 4256 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4257 for (ridx = 4; ridx <= 11; ridx++) { 4258 power[ridx] += ofdmpow; 4259 if (power[ridx] > R92C_MAX_TX_PWR) { 4260 power[ridx] = R92C_MAX_TX_PWR; 4261 } 4262 } 4263 4264 /* Compute per-MCS Tx power. */ 4265 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4266 diff = rom->ht20_tx_pwr_diff[group]; 4267 diff = (diff >> (chain * 4)) & 0xf; 4268 htpow += diff; /* HT40->HT20 correction. */ 4269 } 4270 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4271 power[ridx] += htpow; 4272 if (power[ridx] > R92C_MAX_TX_PWR) { 4273 power[ridx] = R92C_MAX_TX_PWR; 4274 } 4275 } 4276 #ifdef URTWN_DEBUG 4277 if (urtwn_debug & DBG_RF) { 4278 /* Dump per-rate Tx power values. */ 4279 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4280 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4281 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4282 } 4283 #endif 4284 } 4285 4286 void 4287 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4288 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4289 { 4290 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4291 const struct rtwn_r88e_txpwr *base; 4292 int ridx, group; 4293 4294 URTWNHIST_FUNC(); 4295 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4296 4297 /* Determine channel group. */ 4298 if (chan <= 2) 4299 group = 0; 4300 else if (chan <= 5) 4301 group = 1; 4302 else if (chan <= 8) 4303 group = 2; 4304 else if (chan <= 11) 4305 group = 3; 4306 else if (chan <= 13) 4307 group = 4; 4308 else 4309 group = 5; 4310 4311 /* Get original Tx power based on board type and RF chain. */ 4312 base = &rtl8188eu_txagc[chain]; 4313 4314 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4315 if (sc->regulatory == 0) { 4316 for (ridx = 0; ridx <= 3; ridx++) 4317 power[ridx] = base->pwr[0][ridx]; 4318 } 4319 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4320 if (sc->regulatory == 3) 4321 power[ridx] = base->pwr[0][ridx]; 4322 else if (sc->regulatory == 1) { 4323 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4324 power[ridx] = base->pwr[group][ridx]; 4325 } else if (sc->regulatory != 2) 4326 power[ridx] = base->pwr[0][ridx]; 4327 } 4328 4329 /* Compute per-CCK rate Tx power. */ 4330 cckpow = sc->cck_tx_pwr[group]; 4331 for (ridx = 0; ridx <= 3; ridx++) { 4332 power[ridx] += cckpow; 4333 if (power[ridx] > R92C_MAX_TX_PWR) 4334 power[ridx] = R92C_MAX_TX_PWR; 4335 } 4336 4337 htpow = sc->ht40_tx_pwr[group]; 4338 4339 /* Compute per-OFDM rate Tx power. */ 4340 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4341 for (ridx = 4; ridx <= 11; ridx++) { 4342 power[ridx] += ofdmpow; 4343 if (power[ridx] > R92C_MAX_TX_PWR) 4344 power[ridx] = R92C_MAX_TX_PWR; 4345 } 4346 4347 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4348 for (ridx = 12; ridx <= 27; ridx++) { 4349 power[ridx] += bw20pow; 4350 if (power[ridx] > R92C_MAX_TX_PWR) 4351 power[ridx] = R92C_MAX_TX_PWR; 4352 } 4353 } 4354 4355 static void 4356 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4357 { 4358 uint16_t power[URTWN_RIDX_COUNT]; 4359 size_t i; 4360 4361 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4362 4363 for (i = 0; i < sc->ntxchains; i++) { 4364 /* Compute per-rate Tx power values. */ 4365 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4366 ISSET(sc->chip, URTWN_CHIP_92EU)) 4367 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4368 else 4369 urtwn_get_txpower(sc, i, chan, ht40m, power); 4370 /* Write per-rate Tx power values to hardware. */ 4371 urtwn_write_txpower(sc, i, power); 4372 } 4373 } 4374 4375 static void __noinline 4376 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4377 { 4378 struct ieee80211com *ic = &sc->sc_ic; 4379 u_int chan; 4380 size_t i; 4381 4382 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4383 4384 URTWNHIST_FUNC(); 4385 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4386 4387 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4388 4389 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4390 chan += 2; 4391 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4392 chan -= 2; 4393 } 4394 4395 /* Set Tx power for this new channel. */ 4396 urtwn_set_txpower(sc, chan, ht40m); 4397 4398 for (i = 0; i < sc->nrxchains; i++) { 4399 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4400 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4401 } 4402 4403 if (ht40m) { 4404 /* Is secondary channel below or above primary? */ 4405 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4406 uint32_t reg; 4407 4408 urtwn_write_1(sc, R92C_BWOPMODE, 4409 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4410 4411 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4412 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4413 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4414 4415 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4416 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4417 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4418 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4419 4420 /* Set CCK side band. */ 4421 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4422 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4423 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4424 4425 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4426 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4427 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4428 4429 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4430 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4431 ~R92C_FPGA0_ANAPARAM2_CBW20); 4432 4433 reg = urtwn_bb_read(sc, 0x818); 4434 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4435 urtwn_bb_write(sc, 0x818, reg); 4436 4437 /* Select 40MHz bandwidth. */ 4438 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4439 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4440 } else { 4441 urtwn_write_1(sc, R92C_BWOPMODE, 4442 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4443 4444 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4445 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4446 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4447 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4448 4449 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4450 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4451 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4452 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4453 R92C_FPGA0_ANAPARAM2_CBW20); 4454 } 4455 4456 /* Select 20MHz bandwidth. */ 4457 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4458 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4459 (ISSET(sc->chip, URTWN_CHIP_88E) || 4460 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4461 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4462 } 4463 } 4464 4465 static void __noinline 4466 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4467 { 4468 4469 URTWNHIST_FUNC(); 4470 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4471 4472 uint32_t addaBackup[16], iqkBackup[4], piMode; 4473 4474 #ifdef notyet 4475 uint32_t odfm0_agccore_regs[3]; 4476 uint32_t ant_regs[3]; 4477 uint32_t rf_regs[8]; 4478 #endif 4479 uint32_t reg0, reg1, reg2; 4480 int i, attempt; 4481 4482 #ifdef notyet 4483 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4484 R92E_STBC_SETTING + 2)); 4485 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4486 /* Save AGCCORE regs. */ 4487 for (i = 0; i < sc->nrxchains; i++) { 4488 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4489 R92C_OFDM0_AGCCORE1(i)); 4490 } 4491 #endif 4492 /* Save BB regs. */ 4493 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4494 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4495 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4496 4497 /* Save adda regs to be restored when finished. */ 4498 for (i = 0; i < __arraycount(addaReg); i++) 4499 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4500 /* Save mac regs. */ 4501 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4502 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4503 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4504 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4505 4506 #ifdef notyet 4507 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4508 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4509 4510 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4511 for (i = 0; i < sc->nrxchains; i++) 4512 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4513 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4514 #endif 4515 4516 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4517 R92C_HSSI_PARAM1_PI); 4518 if (piMode == 0) { 4519 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4520 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4521 R92C_HSSI_PARAM1_PI); 4522 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4523 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4524 R92C_HSSI_PARAM1_PI); 4525 } 4526 4527 attempt = 1; 4528 4529 next_attempt: 4530 4531 /* Set mac regs for calibration. */ 4532 for (i = 0; i < __arraycount(addaReg); i++) { 4533 urtwn_bb_write(sc, addaReg[i], 4534 addaReg[__arraycount(addaReg) - 1]); 4535 } 4536 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4537 R92C_CCK0_AFESETTING)); 4538 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4539 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4540 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4541 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4542 4543 if (sc->ntxchains > 1) 4544 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4545 4546 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4547 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4548 ~R92C_BCN_CTRL_EN_BCN)); 4549 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4550 ~R92C_BCN_CTRL_EN_BCN)); 4551 4552 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4553 ~R92C_GPIO_MUXCFG_ENBT)); 4554 4555 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4556 4557 if (sc->ntxchains > 1) 4558 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4559 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4560 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4561 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4562 4563 /* Restore BB regs. */ 4564 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4565 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4566 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4567 4568 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4569 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4570 if (sc->nrxchains > 1) 4571 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4572 4573 if (attempt-- > 0) 4574 goto next_attempt; 4575 4576 /* Restore mode. */ 4577 if (piMode == 0) { 4578 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4579 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4580 ~R92C_HSSI_PARAM1_PI); 4581 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4582 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4583 ~R92C_HSSI_PARAM1_PI); 4584 } 4585 4586 #ifdef notyet 4587 for (i = 0; i < sc->nrxchains; i++) { 4588 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4589 odfm0_agccore_regs[i]); 4590 } 4591 #endif 4592 4593 /* Restore adda regs. */ 4594 for (i = 0; i < __arraycount(addaReg); i++) 4595 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4596 /* Restore mac regs. */ 4597 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4598 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4599 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4600 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4601 4602 #ifdef notyet 4603 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4604 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4605 4606 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4607 for (i = 0; i < sc->nrxchains; i++) 4608 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4609 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4610 #endif 4611 } 4612 4613 static void 4614 urtwn_lc_calib(struct urtwn_softc *sc) 4615 { 4616 uint32_t rf_ac[2]; 4617 uint8_t txmode; 4618 size_t i; 4619 4620 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4621 4622 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4623 4624 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4625 if ((txmode & 0x70) != 0) { 4626 /* Disable all continuous Tx. */ 4627 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4628 4629 /* Set RF mode to standby mode. */ 4630 for (i = 0; i < sc->nrxchains; i++) { 4631 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4632 urtwn_rf_write(sc, i, R92C_RF_AC, 4633 RW(rf_ac[i], R92C_RF_AC_MODE, 4634 R92C_RF_AC_MODE_STANDBY)); 4635 } 4636 } else { 4637 /* Block all Tx queues. */ 4638 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4639 } 4640 /* Start calibration. */ 4641 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4642 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4643 4644 /* Give calibration the time to complete. */ 4645 urtwn_delay_ms(sc, 100); 4646 4647 /* Restore configuration. */ 4648 if ((txmode & 0x70) != 0) { 4649 /* Restore Tx mode. */ 4650 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4651 /* Restore RF mode. */ 4652 for (i = 0; i < sc->nrxchains; i++) { 4653 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4654 } 4655 } else { 4656 /* Unblock all Tx queues. */ 4657 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4658 } 4659 } 4660 4661 static void 4662 urtwn_temp_calib(struct urtwn_softc *sc) 4663 { 4664 int temp, t_meter_reg; 4665 4666 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4667 4668 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4669 4670 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4671 t_meter_reg = R92C_RF_T_METER; 4672 else 4673 t_meter_reg = R92E_RF_T_METER; 4674 4675 if (sc->thcal_state == 0) { 4676 /* Start measuring temperature. */ 4677 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4678 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4679 sc->thcal_state = 1; 4680 return; 4681 } 4682 sc->thcal_state = 0; 4683 4684 /* Read measured temperature. */ 4685 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4686 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4687 if (temp == 0) /* Read failed, skip. */ 4688 return; 4689 4690 /* 4691 * Redo LC calibration if temperature changed significantly since 4692 * last calibration. 4693 */ 4694 if (sc->thcal_lctemp == 0) { 4695 /* First LC calibration is performed in urtwn_init(). */ 4696 sc->thcal_lctemp = temp; 4697 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4698 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4699 sc->thcal_lctemp, temp, 0, 0); 4700 urtwn_lc_calib(sc); 4701 /* Record temperature of last LC calibration. */ 4702 sc->thcal_lctemp = temp; 4703 } 4704 } 4705 4706 static int 4707 urtwn_init(struct ifnet *ifp) 4708 { 4709 struct urtwn_softc *sc = ifp->if_softc; 4710 struct ieee80211com *ic = &sc->sc_ic; 4711 struct urtwn_rx_data *data; 4712 uint32_t reg; 4713 size_t i; 4714 int error; 4715 4716 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4717 4718 urtwn_stop(ifp, 0); 4719 4720 mutex_enter(&sc->sc_write_mtx); 4721 4722 mutex_enter(&sc->sc_task_mtx); 4723 /* Init host async commands ring. */ 4724 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4725 mutex_exit(&sc->sc_task_mtx); 4726 4727 mutex_enter(&sc->sc_fwcmd_mtx); 4728 /* Init firmware commands ring. */ 4729 sc->fwcur = 0; 4730 mutex_exit(&sc->sc_fwcmd_mtx); 4731 4732 /* Allocate Tx/Rx buffers. */ 4733 error = urtwn_alloc_rx_list(sc); 4734 if (error != 0) { 4735 aprint_error_dev(sc->sc_dev, 4736 "could not allocate Rx buffers\n"); 4737 goto fail; 4738 } 4739 error = urtwn_alloc_tx_list(sc); 4740 if (error != 0) { 4741 aprint_error_dev(sc->sc_dev, 4742 "could not allocate Tx buffers\n"); 4743 goto fail; 4744 } 4745 4746 /* Power on adapter. */ 4747 error = urtwn_power_on(sc); 4748 if (error != 0) 4749 goto fail; 4750 4751 /* Initialize DMA. */ 4752 error = urtwn_dma_init(sc); 4753 if (error != 0) 4754 goto fail; 4755 4756 /* Set info size in Rx descriptors (in 64-bit words). */ 4757 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4758 4759 /* Init interrupts. */ 4760 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4761 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4762 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4763 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4764 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4765 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4766 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4767 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4768 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4769 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4770 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4771 } 4772 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4773 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4774 } else { 4775 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4776 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4777 } 4778 4779 /* Set MAC address. */ 4780 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4781 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4782 4783 /* Set initial network type. */ 4784 reg = urtwn_read_4(sc, R92C_CR); 4785 switch (ic->ic_opmode) { 4786 case IEEE80211_M_STA: 4787 default: 4788 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4789 break; 4790 4791 case IEEE80211_M_IBSS: 4792 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4793 break; 4794 } 4795 urtwn_write_4(sc, R92C_CR, reg); 4796 4797 /* Set response rate */ 4798 reg = urtwn_read_4(sc, R92C_RRSR); 4799 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4800 urtwn_write_4(sc, R92C_RRSR, reg); 4801 4802 /* SIFS (used in NAV) */ 4803 urtwn_write_2(sc, R92C_SPEC_SIFS, 4804 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4805 4806 /* Set short/long retry limits. */ 4807 urtwn_write_2(sc, R92C_RL, 4808 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4809 4810 /* Initialize EDCA parameters. */ 4811 urtwn_edca_init(sc); 4812 4813 /* Setup rate fallback. */ 4814 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4815 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4816 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4817 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4818 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4819 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4820 } 4821 4822 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4823 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4824 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4825 /* Set ACK timeout. */ 4826 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4827 4828 /* Setup USB aggregation. */ 4829 /* Tx */ 4830 reg = urtwn_read_4(sc, R92C_TDECTRL); 4831 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4832 urtwn_write_4(sc, R92C_TDECTRL, reg); 4833 /* Rx */ 4834 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4835 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4836 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4837 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4838 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4839 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4840 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4841 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4842 ISSET(sc->chip, URTWN_CHIP_92EU)) 4843 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4844 else 4845 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4846 4847 /* Initialize beacon parameters. */ 4848 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4849 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4850 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4851 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4852 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4853 4854 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4855 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4856 /* Setup AMPDU aggregation. */ 4857 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4858 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4859 urtwn_write_2(sc, 0x4ca, 0x0708); 4860 4861 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4862 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4863 } 4864 4865 /* Load 8051 microcode. */ 4866 error = urtwn_load_firmware(sc); 4867 if (error != 0) 4868 goto fail; 4869 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4870 4871 /* Initialize MAC/BB/RF blocks. */ 4872 /* 4873 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4874 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4875 * XXX: This setting should be removed from rtl8192cu_mac[]. 4876 */ 4877 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4878 urtwn_rxfilter_init(sc); // reset R92C_RCR 4879 urtwn_bb_init(sc); 4880 urtwn_rf_init(sc); 4881 4882 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4883 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4884 urtwn_write_2(sc, R92C_CR, 4885 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4886 R92C_CR_MACRXEN); 4887 } 4888 4889 /* Turn CCK and OFDM blocks on. */ 4890 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4891 reg |= R92C_RFMOD_CCK_EN; 4892 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4893 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4894 reg |= R92C_RFMOD_OFDM_EN; 4895 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4896 4897 /* Clear per-station keys table. */ 4898 urtwn_cam_init(sc); 4899 4900 /* Enable hardware sequence numbering. */ 4901 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4902 4903 /* Perform LO and IQ calibrations. */ 4904 urtwn_iq_calib(sc, sc->iqk_inited); 4905 sc->iqk_inited = true; 4906 4907 /* Perform LC calibration. */ 4908 urtwn_lc_calib(sc); 4909 4910 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4911 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4912 /* Fix USB interference issue. */ 4913 urtwn_write_1(sc, 0xfe40, 0xe0); 4914 urtwn_write_1(sc, 0xfe41, 0x8d); 4915 urtwn_write_1(sc, 0xfe42, 0x80); 4916 urtwn_write_4(sc, 0x20c, 0xfd0320); 4917 4918 urtwn_pa_bias_init(sc); 4919 } 4920 4921 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4922 !(sc->chip & URTWN_CHIP_92EU)) { 4923 /* 1T1R */ 4924 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4925 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4926 } 4927 4928 /* Initialize GPIO setting. */ 4929 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4930 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4931 4932 /* Fix for lower temperature. */ 4933 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4934 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4935 urtwn_write_1(sc, 0x15, 0xe9); 4936 4937 /* Set default channel. */ 4938 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4939 4940 /* Queue Rx xfers. */ 4941 for (size_t j = 0; j < sc->rx_npipe; j++) { 4942 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4943 data = &sc->rx_data[j][i]; 4944 usbd_setup_xfer(data->xfer, data, data->buf, 4945 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4946 urtwn_rxeof); 4947 error = usbd_transfer(data->xfer); 4948 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4949 error != USBD_IN_PROGRESS)) 4950 goto fail; 4951 } 4952 } 4953 4954 /* We're ready to go. */ 4955 ifp->if_flags &= ~IFF_OACTIVE; 4956 ifp->if_flags |= IFF_RUNNING; 4957 sc->sc_running = true; 4958 4959 mutex_exit(&sc->sc_write_mtx); 4960 4961 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4962 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4963 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4964 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4965 urtwn_wait_async(sc); 4966 4967 return 0; 4968 4969 fail: 4970 mutex_exit(&sc->sc_write_mtx); 4971 4972 urtwn_stop(ifp, 1); 4973 return error; 4974 } 4975 4976 static void __noinline 4977 urtwn_stop(struct ifnet *ifp, int disable) 4978 { 4979 struct urtwn_softc *sc = ifp->if_softc; 4980 struct ieee80211com *ic = &sc->sc_ic; 4981 size_t i; 4982 int s; 4983 4984 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4985 4986 s = splusb(); 4987 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4988 urtwn_wait_async(sc); 4989 splx(s); 4990 4991 sc->tx_timer = 0; 4992 ifp->if_timer = 0; 4993 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4994 4995 callout_stop(&sc->sc_scan_to); 4996 callout_stop(&sc->sc_calib_to); 4997 4998 /* Abort Tx. */ 4999 for (i = 0; i < sc->tx_npipe; i++) { 5000 if (sc->tx_pipe[i] != NULL) 5001 usbd_abort_pipe(sc->tx_pipe[i]); 5002 } 5003 5004 /* Stop Rx pipe. */ 5005 for (i = 0; i < sc->rx_npipe; i++) { 5006 if (sc->rx_pipe[i] != NULL) 5007 usbd_abort_pipe(sc->rx_pipe[i]); 5008 } 5009 5010 /* Free Tx/Rx buffers. */ 5011 urtwn_free_tx_list(sc); 5012 urtwn_free_rx_list(sc); 5013 5014 sc->sc_running = false; 5015 if (disable) 5016 urtwn_chip_stop(sc); 5017 } 5018 5019 static int 5020 urtwn_reset(struct ifnet *ifp) 5021 { 5022 struct urtwn_softc *sc = ifp->if_softc; 5023 struct ieee80211com *ic = &sc->sc_ic; 5024 5025 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5026 return ENETRESET; 5027 5028 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5029 5030 return 0; 5031 } 5032 5033 static void 5034 urtwn_chip_stop(struct urtwn_softc *sc) 5035 { 5036 uint32_t reg; 5037 bool disabled = true; 5038 5039 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5040 5041 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5042 ISSET(sc->chip, URTWN_CHIP_92EU)) 5043 return; 5044 5045 mutex_enter(&sc->sc_write_mtx); 5046 5047 /* 5048 * RF Off Sequence 5049 */ 5050 /* Pause MAC TX queue */ 5051 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5052 5053 /* Disable RF */ 5054 urtwn_rf_write(sc, 0, 0, 0); 5055 5056 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5057 5058 /* Reset BB state machine */ 5059 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5060 R92C_SYS_FUNC_EN_USBD | 5061 R92C_SYS_FUNC_EN_USBA | 5062 R92C_SYS_FUNC_EN_BB_GLB_RST); 5063 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5064 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5065 5066 /* 5067 * Reset digital sequence 5068 */ 5069 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5070 /* Reset MCU ready status */ 5071 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5072 /* If firmware in ram code, do reset */ 5073 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5074 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5075 ISSET(sc->chip, URTWN_CHIP_92EU)) 5076 urtwn_r88e_fw_reset(sc); 5077 else 5078 urtwn_fw_reset(sc); 5079 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5080 } 5081 } 5082 5083 /* Reset MAC and Enable 8051 */ 5084 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5085 5086 /* Reset MCU ready status */ 5087 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5088 5089 if (disabled) { 5090 /* Disable MAC clock */ 5091 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5092 /* Disable AFE PLL */ 5093 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5094 /* Gated AFE DIG_CLOCK */ 5095 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5096 /* Isolated digital to PON */ 5097 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5098 } 5099 5100 /* 5101 * Pull GPIO PIN to balance level and LED control 5102 */ 5103 /* 1. Disable GPIO[7:0] */ 5104 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5105 5106 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5107 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5108 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5109 5110 /* Disable GPIO[10:8] */ 5111 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5112 5113 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5114 reg |= (((reg & 0x000f) << 4) | 0x0780); 5115 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5116 5117 /* Disable LED0 & 1 */ 5118 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5119 5120 /* 5121 * Reset digital sequence 5122 */ 5123 if (disabled) { 5124 /* Disable ELDR clock */ 5125 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5126 /* Isolated ELDR to PON */ 5127 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5128 } 5129 5130 /* 5131 * Disable analog sequence 5132 */ 5133 if (disabled) { 5134 /* Disable A15 power */ 5135 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5136 /* Disable digital core power */ 5137 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5138 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5139 ~R92C_LDOV12D_CTRL_LDV12_EN); 5140 } 5141 5142 /* Enter PFM mode */ 5143 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5144 5145 /* Set USB suspend */ 5146 urtwn_write_2(sc, R92C_APS_FSMCO, 5147 R92C_APS_FSMCO_APDM_HOST | 5148 R92C_APS_FSMCO_AFSM_HSUS | 5149 R92C_APS_FSMCO_PFM_ALDN); 5150 5151 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5152 5153 mutex_exit(&sc->sc_write_mtx); 5154 } 5155 5156 static void 5157 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5158 { 5159 if (sc->sc_running == false) 5160 DELAY(ms * 1000); 5161 else 5162 usbd_delay_ms(sc->sc_udev, ms); 5163 } 5164 5165 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5166 5167 #ifdef _MODULE 5168 #include "ioconf.c" 5169 #endif 5170 5171 static int 5172 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5173 { 5174 int error = 0; 5175 5176 switch (cmd) { 5177 case MODULE_CMD_INIT: 5178 #ifdef _MODULE 5179 error = config_init_component(cfdriver_ioconf_urtwn, 5180 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5181 #endif 5182 return error; 5183 case MODULE_CMD_FINI: 5184 #ifdef _MODULE 5185 error = config_fini_component(cfdriver_ioconf_urtwn, 5186 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5187 #endif 5188 return error; 5189 default: 5190 return ENOTTY; 5191 } 5192 } 5193
Indexes created Tue Sep 30 17:09:57 GMT 2025