if_urtwn.c revision 1.98
1 /* $NetBSD: if_urtwn.c,v 1.98 2021/09/17 12:58:31 nat Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.98 2021/09/17 12:58:31 nat Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 u_int urtwn_debug = 0; 99 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 100 if (urtwn_debug & (n)) { \ 101 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 102 } \ 103 } while (/*CONSTCOND*/0) 104 #define URTWNHIST_FUNC() USBHIST_FUNC() 105 #define URTWNHIST_CALLED() do { \ 106 if (urtwn_debug & DBG_FN) { \ 107 KERNHIST_CALLED(usbhist); \ 108 } \ 109 } while(/*CONSTCOND*/0) 110 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 111 if (urtwn_debug & DBG_FN) { \ 112 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 #else 116 #define DPRINTFN(n, fmt, a, b, c, d) 117 #define URTWNHIST_FUNC() 118 #define URTWNHIST_CALLED() 119 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 120 #endif 121 122 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 123 #define URTWN_RTL8188E_DEV(v,p) \ 124 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 125 #define URTWN_RTL8192EU_DEV(v,p) \ 126 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 127 static const struct urtwn_dev { 128 struct usb_devno dev; 129 uint32_t flags; 130 #define FLAG_RTL8188E __BIT(0) 131 #define FLAG_RTL8192E __BIT(1) 132 } urtwn_devs[] = { 133 URTWN_DEV(ABOCOM, RTL8188CU_1), 134 URTWN_DEV(ABOCOM, RTL8188CU_2), 135 URTWN_DEV(ABOCOM, RTL8192CU), 136 URTWN_DEV(ASUSTEK, RTL8192CU), 137 URTWN_DEV(ASUSTEK, RTL8192CU_3), 138 URTWN_DEV(ASUSTEK, USBN10NANO), 139 URTWN_DEV(ASUSTEK, RTL8192CU_3), 140 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 141 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 142 URTWN_DEV(AZUREWAVE, RTL8188CU), 143 URTWN_DEV(BELKIN, F7D2102), 144 URTWN_DEV(BELKIN, RTL8188CU), 145 URTWN_DEV(BELKIN, RTL8188CUS), 146 URTWN_DEV(BELKIN, RTL8192CU), 147 URTWN_DEV(BELKIN, RTL8192CU_1), 148 URTWN_DEV(BELKIN, RTL8192CU_2), 149 URTWN_DEV(CHICONY, RTL8188CUS_1), 150 URTWN_DEV(CHICONY, RTL8188CUS_2), 151 URTWN_DEV(CHICONY, RTL8188CUS_3), 152 URTWN_DEV(CHICONY, RTL8188CUS_4), 153 URTWN_DEV(CHICONY, RTL8188CUS_5), 154 URTWN_DEV(CHICONY, RTL8188CUS_6), 155 URTWN_DEV(COMPARE, RTL8192CU), 156 URTWN_DEV(COREGA, RTL8192CU), 157 URTWN_DEV(DLINK, DWA131B), 158 URTWN_DEV(DLINK, RTL8188CU), 159 URTWN_DEV(DLINK, RTL8192CU_1), 160 URTWN_DEV(DLINK, RTL8192CU_2), 161 URTWN_DEV(DLINK, RTL8192CU_3), 162 URTWN_DEV(DLINK, RTL8192CU_4), 163 URTWN_DEV(EDIMAX, RTL8188CU), 164 URTWN_DEV(EDIMAX, RTL8192CU), 165 URTWN_DEV(FEIXUN, RTL8188CU), 166 URTWN_DEV(FEIXUN, RTL8192CU), 167 URTWN_DEV(GUILLEMOT, HWNUP150), 168 URTWN_DEV(GUILLEMOT, RTL8192CU), 169 URTWN_DEV(HAWKING, RTL8192CU), 170 URTWN_DEV(HAWKING, RTL8192CU_2), 171 URTWN_DEV(HP3, RTL8188CU), 172 URTWN_DEV(IODATA, WNG150UM), 173 URTWN_DEV(IODATA, RTL8192CU), 174 URTWN_DEV(NETGEAR, WNA1000M), 175 URTWN_DEV(NETGEAR, RTL8192CU), 176 URTWN_DEV(NETGEAR4, RTL8188CU), 177 URTWN_DEV(NOVATECH, RTL8188CU), 178 URTWN_DEV(PLANEX2, RTL8188CU_1), 179 URTWN_DEV(PLANEX2, RTL8188CU_2), 180 URTWN_DEV(PLANEX2, RTL8192CU), 181 URTWN_DEV(PLANEX2, RTL8188CU_3), 182 URTWN_DEV(PLANEX2, RTL8188CU_4), 183 URTWN_DEV(PLANEX2, RTL8188CUS), 184 URTWN_DEV(REALTEK, RTL8188CE_0), 185 URTWN_DEV(REALTEK, RTL8188CE_1), 186 URTWN_DEV(REALTEK, RTL8188CTV), 187 URTWN_DEV(REALTEK, RTL8188CU_0), 188 URTWN_DEV(REALTEK, RTL8188CU_1), 189 URTWN_DEV(REALTEK, RTL8188CU_2), 190 URTWN_DEV(REALTEK, RTL8188CU_3), 191 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 192 URTWN_DEV(REALTEK, RTL8188CUS), 193 URTWN_DEV(REALTEK, RTL8188RU), 194 URTWN_DEV(REALTEK, RTL8188RU_2), 195 URTWN_DEV(REALTEK, RTL8188RU_3), 196 URTWN_DEV(REALTEK, RTL8191CU), 197 URTWN_DEV(REALTEK, RTL8192CE), 198 URTWN_DEV(REALTEK, RTL8192CU), 199 URTWN_DEV(SITECOMEU, RTL8188CU), 200 URTWN_DEV(SITECOMEU, RTL8188CU_2), 201 URTWN_DEV(SITECOMEU, RTL8192CU), 202 URTWN_DEV(SITECOMEU, RTL8192CUR2), 203 URTWN_DEV(TPLINK, RTL8192CU), 204 URTWN_DEV(TRENDNET, RTL8188CU), 205 URTWN_DEV(TRENDNET, RTL8192CU), 206 URTWN_DEV(ZYXEL, RTL8192CU), 207 208 /* URTWN_RTL8188E */ 209 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 210 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 211 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 212 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 213 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 214 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 215 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 216 217 /* URTWN_RTL8192EU */ 218 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 219 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 220 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 221 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 222 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 223 }; 224 #undef URTWN_DEV 225 #undef URTWN_RTL8188E_DEV 226 #undef URTWN_RTL8192EU_DEV 227 228 static int urtwn_match(device_t, cfdata_t, void *); 229 static void urtwn_attach(device_t, device_t, void *); 230 static int urtwn_detach(device_t, int); 231 static int urtwn_activate(device_t, enum devact); 232 233 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 234 urtwn_attach, urtwn_detach, urtwn_activate); 235 236 static int urtwn_open_pipes(struct urtwn_softc *); 237 static void urtwn_close_pipes(struct urtwn_softc *); 238 static int urtwn_alloc_rx_list(struct urtwn_softc *); 239 static void urtwn_free_rx_list(struct urtwn_softc *); 240 static int urtwn_alloc_tx_list(struct urtwn_softc *); 241 static void urtwn_free_tx_list(struct urtwn_softc *); 242 static void urtwn_task(void *); 243 static void urtwn_do_async(struct urtwn_softc *, 244 void (*)(struct urtwn_softc *, void *), void *, int); 245 static void urtwn_wait_async(struct urtwn_softc *); 246 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 247 int); 248 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 249 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 250 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 251 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 252 int); 253 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 254 int); 255 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 256 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 257 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 258 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 259 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 260 uint32_t); 261 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 262 uint32_t); 263 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 264 uint32_t); 265 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 266 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 267 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 268 static void urtwn_efuse_read(struct urtwn_softc *); 269 static void urtwn_efuse_switch_power(struct urtwn_softc *); 270 static int urtwn_read_chipid(struct urtwn_softc *); 271 #ifdef URTWN_DEBUG 272 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 273 #endif 274 static void urtwn_read_rom(struct urtwn_softc *); 275 static void urtwn_r88e_read_rom(struct urtwn_softc *); 276 static int urtwn_media_change(struct ifnet *); 277 static int urtwn_ra_init(struct urtwn_softc *); 278 static int urtwn_get_nettype(struct urtwn_softc *); 279 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 280 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 281 static void urtwn_set_led(struct urtwn_softc *, int, int); 282 static void urtwn_calib_to(void *); 283 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 284 static void urtwn_next_scan(void *); 285 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 286 int); 287 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 288 static int urtwn_wme_update(struct ieee80211com *); 289 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 290 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 291 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 292 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 293 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 294 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 295 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 296 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 297 struct ieee80211_node *, struct urtwn_tx_data *); 298 static struct urtwn_tx_data * 299 urtwn_get_tx_data(struct urtwn_softc *, size_t); 300 static void urtwn_start(struct ifnet *); 301 static void urtwn_watchdog(struct ifnet *); 302 static int urtwn_ioctl(struct ifnet *, u_long, void *); 303 static int urtwn_r92c_power_on(struct urtwn_softc *); 304 static int urtwn_r92e_power_on(struct urtwn_softc *); 305 static int urtwn_r88e_power_on(struct urtwn_softc *); 306 static int urtwn_llt_init(struct urtwn_softc *); 307 static void urtwn_fw_reset(struct urtwn_softc *); 308 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 309 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 310 static int urtwn_load_firmware(struct urtwn_softc *); 311 static int urtwn_r92c_dma_init(struct urtwn_softc *); 312 static int urtwn_r88e_dma_init(struct urtwn_softc *); 313 static void urtwn_mac_init(struct urtwn_softc *); 314 static void urtwn_bb_init(struct urtwn_softc *); 315 static void urtwn_rf_init(struct urtwn_softc *); 316 static void urtwn_cam_init(struct urtwn_softc *); 317 static void urtwn_pa_bias_init(struct urtwn_softc *); 318 static void urtwn_rxfilter_init(struct urtwn_softc *); 319 static void urtwn_edca_init(struct urtwn_softc *); 320 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 321 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 322 uint16_t[]); 323 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 324 u_int, uint16_t[]); 325 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 326 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 327 u_int); 328 static void urtwn_iq_calib(struct urtwn_softc *, bool); 329 static void urtwn_lc_calib(struct urtwn_softc *); 330 static void urtwn_temp_calib(struct urtwn_softc *); 331 static int urtwn_init(struct ifnet *); 332 static void urtwn_stop(struct ifnet *, int); 333 static int urtwn_reset(struct ifnet *); 334 static void urtwn_chip_stop(struct urtwn_softc *); 335 static void urtwn_newassoc(struct ieee80211_node *, int); 336 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 337 338 /* Aliases. */ 339 #define urtwn_bb_write urtwn_write_4 340 #define urtwn_bb_read urtwn_read_4 341 342 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 343 344 static const uint16_t addaReg[] = { 345 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 346 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 347 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 348 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 349 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 350 }; 351 352 static int 353 urtwn_match(device_t parent, cfdata_t match, void *aux) 354 { 355 struct usb_attach_arg *uaa = aux; 356 357 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 358 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 359 } 360 361 static void 362 urtwn_attach(device_t parent, device_t self, void *aux) 363 { 364 struct urtwn_softc *sc = device_private(self); 365 struct ieee80211com *ic = &sc->sc_ic; 366 struct ifnet *ifp = &sc->sc_if; 367 struct usb_attach_arg *uaa = aux; 368 char *devinfop; 369 const struct urtwn_dev *dev; 370 usb_device_request_t req; 371 size_t i; 372 int error; 373 374 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 375 376 sc->sc_dev = self; 377 sc->sc_udev = uaa->uaa_device; 378 379 sc->chip = 0; 380 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 381 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 382 SET(sc->chip, URTWN_CHIP_88E); 383 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 384 SET(sc->chip, URTWN_CHIP_92EU); 385 386 aprint_naive("\n"); 387 aprint_normal("\n"); 388 389 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 390 aprint_normal_dev(self, "%s\n", devinfop); 391 usbd_devinfo_free(devinfop); 392 393 req.bmRequestType = UT_WRITE_DEVICE; 394 req.bRequest = UR_SET_FEATURE; 395 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 396 USETW(req.wIndex, UHF_PORT_SUSPEND); 397 USETW(req.wLength, 0); 398 399 (void) usbd_do_request(sc->sc_udev, &req, 0); 400 401 cv_init(&sc->sc_task_cv, "urtwntsk"); 402 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 403 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 404 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 405 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 406 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 407 408 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 409 410 callout_init(&sc->sc_scan_to, 0); 411 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 412 callout_init(&sc->sc_calib_to, 0); 413 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 414 415 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 416 RND_TYPE_NET, RND_FLAG_DEFAULT); 417 418 error = usbd_set_config_no(sc->sc_udev, 1, 0); 419 if (error != 0) { 420 aprint_error_dev(self, "failed to set configuration" 421 ", err=%s\n", usbd_errstr(error)); 422 goto fail; 423 } 424 425 /* Get the first interface handle. */ 426 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 427 if (error != 0) { 428 aprint_error_dev(self, "could not get interface handle\n"); 429 goto fail; 430 } 431 432 error = urtwn_read_chipid(sc); 433 if (error != 0) { 434 aprint_error_dev(self, "unsupported test chip\n"); 435 goto fail; 436 } 437 438 /* Determine number of Tx/Rx chains. */ 439 if (sc->chip & URTWN_CHIP_92C) { 440 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 441 sc->nrxchains = 2; 442 } else if (sc->chip & URTWN_CHIP_92EU) { 443 sc->ntxchains = 2; 444 sc->nrxchains = 2; 445 } else { 446 sc->ntxchains = 1; 447 sc->nrxchains = 1; 448 } 449 450 if (ISSET(sc->chip, URTWN_CHIP_88E) || 451 ISSET(sc->chip, URTWN_CHIP_92EU)) 452 urtwn_r88e_read_rom(sc); 453 else 454 urtwn_read_rom(sc); 455 456 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 457 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 458 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 459 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 460 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 461 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 462 "8188CUS", sc->ntxchains, sc->nrxchains, 463 ether_sprintf(ic->ic_myaddr)); 464 465 error = urtwn_open_pipes(sc); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 468 goto fail; 469 } 470 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 471 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 472 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 473 474 /* 475 * Setup the 802.11 device. 476 */ 477 ic->ic_ifp = ifp; 478 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 479 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 480 ic->ic_state = IEEE80211_S_INIT; 481 482 /* Set device capabilities. */ 483 ic->ic_caps = 484 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 485 IEEE80211_C_IBSS | /* IBSS mode supported */ 486 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 487 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 488 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 489 IEEE80211_C_WME | /* 802.11e */ 490 IEEE80211_C_WPA; /* 802.11i */ 491 492 /* Set supported .11b and .11g rates. */ 493 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 494 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 495 496 /* Set supported .11b and .11g channels (1 through 14). */ 497 for (i = 1; i <= 14; i++) { 498 ic->ic_channels[i].ic_freq = 499 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 500 ic->ic_channels[i].ic_flags = 501 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 502 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 503 } 504 505 ifp->if_softc = sc; 506 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 507 ifp->if_init = urtwn_init; 508 ifp->if_ioctl = urtwn_ioctl; 509 ifp->if_start = urtwn_start; 510 ifp->if_watchdog = urtwn_watchdog; 511 IFQ_SET_READY(&ifp->if_snd); 512 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 513 514 if_initialize(ifp); 515 ieee80211_ifattach(ic); 516 517 /* override default methods */ 518 ic->ic_newassoc = urtwn_newassoc; 519 ic->ic_reset = urtwn_reset; 520 ic->ic_wme.wme_update = urtwn_wme_update; 521 522 /* Override state transition machine. */ 523 sc->sc_newstate = ic->ic_newstate; 524 ic->ic_newstate = urtwn_newstate; 525 526 /* XXX media locking needs revisiting */ 527 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 528 ieee80211_media_init_with_lock(ic, 529 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 530 531 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 532 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 533 &sc->sc_drvbpf); 534 535 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 536 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 537 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 538 539 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 540 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 541 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 542 543 ifp->if_percpuq = if_percpuq_create(ifp); 544 if_register(ifp); 545 546 ieee80211_announce(ic); 547 548 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 549 550 if (!pmf_device_register(self, NULL, NULL)) 551 aprint_error_dev(self, "couldn't establish power handler\n"); 552 553 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 554 return; 555 556 fail: 557 sc->sc_dying = 1; 558 aprint_error_dev(self, "attach failed\n"); 559 } 560 561 static int 562 urtwn_detach(device_t self, int flags) 563 { 564 struct urtwn_softc *sc = device_private(self); 565 struct ifnet *ifp = &sc->sc_if; 566 int s; 567 568 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 569 570 pmf_device_deregister(self); 571 572 s = splusb(); 573 574 sc->sc_dying = 1; 575 576 callout_halt(&sc->sc_scan_to, NULL); 577 callout_halt(&sc->sc_calib_to, NULL); 578 579 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 580 urtwn_stop(ifp, 0); 581 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 582 NULL); 583 584 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 585 bpf_detach(ifp); 586 ieee80211_ifdetach(&sc->sc_ic); 587 if_detach(ifp); 588 589 mutex_destroy(&sc->sc_media_mtx); 590 591 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 592 urtwn_close_pipes(sc); 593 } 594 595 splx(s); 596 597 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 598 599 rnd_detach_source(&sc->rnd_source); 600 601 callout_destroy(&sc->sc_scan_to); 602 callout_destroy(&sc->sc_calib_to); 603 604 cv_destroy(&sc->sc_task_cv); 605 mutex_destroy(&sc->sc_write_mtx); 606 mutex_destroy(&sc->sc_fwcmd_mtx); 607 mutex_destroy(&sc->sc_tx_mtx); 608 mutex_destroy(&sc->sc_rx_mtx); 609 mutex_destroy(&sc->sc_task_mtx); 610 611 return 0; 612 } 613 614 static int 615 urtwn_activate(device_t self, enum devact act) 616 { 617 struct urtwn_softc *sc = device_private(self); 618 619 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 620 621 switch (act) { 622 case DVACT_DEACTIVATE: 623 if_deactivate(sc->sc_ic.ic_ifp); 624 return 0; 625 default: 626 return EOPNOTSUPP; 627 } 628 } 629 630 static int 631 urtwn_open_pipes(struct urtwn_softc *sc) 632 { 633 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 634 static uint8_t epaddr[R92C_MAX_EPOUT]; 635 static uint8_t rxepaddr[R92C_MAX_EPIN]; 636 usb_interface_descriptor_t *id; 637 usb_endpoint_descriptor_t *ed; 638 size_t i, ntx = 0, nrx = 0; 639 int error; 640 641 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 642 643 /* Determine the number of bulk-out pipes. */ 644 id = usbd_get_interface_descriptor(sc->sc_iface); 645 for (i = 0; i < id->bNumEndpoints; i++) { 646 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 647 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 648 continue; 649 } 650 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 651 if (ntx < sizeof(epaddr)) 652 epaddr[ntx] = ed->bEndpointAddress; 653 ntx++; 654 } 655 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 656 if (nrx < sizeof(rxepaddr)) 657 rxepaddr[nrx] = ed->bEndpointAddress; 658 nrx++; 659 } 660 } 661 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 662 aprint_error_dev(sc->sc_dev, 663 "%zd: invalid number of Rx bulk pipes\n", nrx); 664 return EIO; 665 } 666 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 667 aprint_error_dev(sc->sc_dev, 668 "%zd: invalid number of Tx bulk pipes\n", ntx); 669 return EIO; 670 } 671 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 672 nrx, ntx, 0, 0); 673 sc->rx_npipe = nrx; 674 sc->tx_npipe = ntx; 675 676 /* Open bulk-in pipe at address 0x81. */ 677 for (i = 0; i < nrx; i++) { 678 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 679 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 680 if (error != 0) { 681 aprint_error_dev(sc->sc_dev, 682 "could not open Rx bulk pipe 0x%02x: %d\n", 683 rxepaddr[i], error); 684 goto fail; 685 } 686 } 687 688 /* Open bulk-out pipes (up to 3). */ 689 for (i = 0; i < ntx; i++) { 690 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 691 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 692 if (error != 0) { 693 aprint_error_dev(sc->sc_dev, 694 "could not open Tx bulk pipe 0x%02x: %d\n", 695 epaddr[i], error); 696 goto fail; 697 } 698 } 699 700 /* Map 802.11 access categories to USB pipes. */ 701 sc->ac2idx[WME_AC_BK] = 702 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 703 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 704 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 705 706 fail: 707 if (error != 0) 708 urtwn_close_pipes(sc); 709 return error; 710 } 711 712 static void 713 urtwn_close_pipes(struct urtwn_softc *sc) 714 { 715 struct usbd_pipe *pipe; 716 size_t i; 717 718 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 719 720 /* Close Rx pipes. */ 721 CTASSERT(sizeof(pipe) == sizeof(void *)); 722 for (i = 0; i < sc->rx_npipe; i++) { 723 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 724 if (pipe != NULL) { 725 usbd_close_pipe(pipe); 726 } 727 } 728 729 /* Close Tx pipes. */ 730 for (i = 0; i < sc->tx_npipe; i++) { 731 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 732 if (pipe != NULL) { 733 usbd_close_pipe(pipe); 734 } 735 } 736 } 737 738 static int __noinline 739 urtwn_alloc_rx_list(struct urtwn_softc *sc) 740 { 741 struct urtwn_rx_data *data; 742 size_t i; 743 int error = 0; 744 745 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 746 747 for (size_t j = 0; j < sc->rx_npipe; j++) { 748 TAILQ_INIT(&sc->rx_free_list[j]); 749 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 750 data = &sc->rx_data[j][i]; 751 752 data->sc = sc; /* Backpointer for callbacks. */ 753 754 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 755 0, 0, &data->xfer); 756 if (error) { 757 aprint_error_dev(sc->sc_dev, 758 "could not allocate xfer\n"); 759 break; 760 } 761 762 data->buf = usbd_get_buffer(data->xfer); 763 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 764 } 765 } 766 if (error != 0) 767 urtwn_free_rx_list(sc); 768 return error; 769 } 770 771 static void 772 urtwn_free_rx_list(struct urtwn_softc *sc) 773 { 774 struct usbd_xfer *xfer; 775 size_t i; 776 777 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 778 779 /* NB: Caller must abort pipe first. */ 780 for (size_t j = 0; j < sc->rx_npipe; j++) { 781 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 782 CTASSERT(sizeof(xfer) == sizeof(void *)); 783 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 784 if (xfer != NULL) 785 usbd_destroy_xfer(xfer); 786 } 787 } 788 } 789 790 static int __noinline 791 urtwn_alloc_tx_list(struct urtwn_softc *sc) 792 { 793 struct urtwn_tx_data *data; 794 size_t i; 795 int error = 0; 796 797 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 798 799 mutex_enter(&sc->sc_tx_mtx); 800 for (size_t j = 0; j < sc->tx_npipe; j++) { 801 TAILQ_INIT(&sc->tx_free_list[j]); 802 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 803 data = &sc->tx_data[j][i]; 804 805 data->sc = sc; /* Backpointer for callbacks. */ 806 data->pidx = j; 807 808 error = usbd_create_xfer(sc->tx_pipe[j], 809 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 810 &data->xfer); 811 if (error) { 812 aprint_error_dev(sc->sc_dev, 813 "could not allocate xfer\n"); 814 goto fail; 815 } 816 817 data->buf = usbd_get_buffer(data->xfer); 818 819 /* Append this Tx buffer to our free list. */ 820 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 821 } 822 } 823 mutex_exit(&sc->sc_tx_mtx); 824 return 0; 825 826 fail: 827 urtwn_free_tx_list(sc); 828 mutex_exit(&sc->sc_tx_mtx); 829 return error; 830 } 831 832 static void 833 urtwn_free_tx_list(struct urtwn_softc *sc) 834 { 835 struct usbd_xfer *xfer; 836 size_t i; 837 838 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 839 840 /* NB: Caller must abort pipe first. */ 841 for (size_t j = 0; j < sc->tx_npipe; j++) { 842 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 843 CTASSERT(sizeof(xfer) == sizeof(void *)); 844 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 845 if (xfer != NULL) 846 usbd_destroy_xfer(xfer); 847 } 848 } 849 } 850 851 static int 852 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 853 struct ieee80211_node *ni) 854 { 855 struct urtwn_tx_data *data = 856 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 857 858 if (data == NULL) 859 return ENOBUFS; 860 861 return urtwn_tx(sc, m, ni, data); 862 } 863 864 static void 865 urtwn_task(void *arg) 866 { 867 struct urtwn_softc *sc = arg; 868 struct ieee80211com *ic = &sc->sc_ic; 869 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 870 struct urtwn_host_cmd *cmd; 871 int s; 872 873 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 874 if (ic->ic_state == IEEE80211_S_RUN && 875 (ic->ic_opmode == IEEE80211_M_HOSTAP || 876 ic->ic_opmode == IEEE80211_M_IBSS)) { 877 878 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 879 &sc->sc_bo); 880 if (m == NULL) { 881 aprint_error_dev(sc->sc_dev, 882 "could not allocate beacon"); 883 } 884 885 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 886 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 887 } 888 889 /* beacon is no longer needed */ 890 m_freem(m); 891 } 892 893 /* Process host commands. */ 894 s = splusb(); 895 mutex_spin_enter(&sc->sc_task_mtx); 896 while (ring->next != ring->cur) { 897 cmd = &ring->cmd[ring->next]; 898 mutex_spin_exit(&sc->sc_task_mtx); 899 splx(s); 900 /* Invoke callback with kernel lock held. */ 901 cmd->cb(sc, cmd->data); 902 s = splusb(); 903 mutex_spin_enter(&sc->sc_task_mtx); 904 ring->queued--; 905 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 906 } 907 cv_broadcast(&sc->sc_task_cv); 908 mutex_spin_exit(&sc->sc_task_mtx); 909 splx(s); 910 } 911 912 static void 913 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 914 void *arg, int len) 915 { 916 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 917 struct urtwn_host_cmd *cmd; 918 int s; 919 920 URTWNHIST_FUNC(); 921 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 922 (uintptr_t)cb, (uintptr_t)arg, len, 0); 923 924 s = splusb(); 925 mutex_spin_enter(&sc->sc_task_mtx); 926 cmd = &ring->cmd[ring->cur]; 927 cmd->cb = cb; 928 KASSERT(len <= sizeof(cmd->data)); 929 memcpy(cmd->data, arg, len); 930 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 931 932 /* If there is no pending command already, schedule a task. */ 933 if (!sc->sc_dying && ++ring->queued == 1) { 934 mutex_spin_exit(&sc->sc_task_mtx); 935 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 936 } else 937 mutex_spin_exit(&sc->sc_task_mtx); 938 splx(s); 939 } 940 941 static void 942 urtwn_wait_async(struct urtwn_softc *sc) 943 { 944 945 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 946 947 /* Wait for all queued asynchronous commands to complete. */ 948 mutex_spin_enter(&sc->sc_task_mtx); 949 while (sc->cmdq.queued > 0) 950 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 951 mutex_spin_exit(&sc->sc_task_mtx); 952 } 953 954 static int 955 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 956 int len) 957 { 958 usb_device_request_t req; 959 usbd_status error; 960 961 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 962 KASSERT(mutex_owned(&sc->sc_write_mtx)); 963 964 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 965 req.bRequest = R92C_REQ_REGS; 966 USETW(req.wValue, addr); 967 USETW(req.wIndex, 0); 968 USETW(req.wLength, len); 969 error = usbd_do_request(sc->sc_udev, &req, buf); 970 if (error != USBD_NORMAL_COMPLETION) { 971 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 972 error, addr, len, 0); 973 } 974 return error; 975 } 976 977 static void 978 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 979 { 980 981 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 982 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 983 984 urtwn_write_region_1(sc, addr, &val, 1); 985 } 986 987 static void 988 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 989 { 990 uint8_t buf[2]; 991 992 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 993 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 994 995 buf[0] = (uint8_t)val; 996 buf[1] = (uint8_t)(val >> 8); 997 urtwn_write_region_1(sc, addr, buf, 2); 998 } 999 1000 static void 1001 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1002 { 1003 uint8_t buf[4]; 1004 1005 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1006 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1007 1008 buf[0] = (uint8_t)val; 1009 buf[1] = (uint8_t)(val >> 8); 1010 buf[2] = (uint8_t)(val >> 16); 1011 buf[3] = (uint8_t)(val >> 24); 1012 urtwn_write_region_1(sc, addr, buf, 4); 1013 } 1014 1015 static int 1016 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1017 { 1018 1019 URTWNHIST_FUNC(); 1020 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1021 1022 return urtwn_write_region_1(sc, addr, buf, len); 1023 } 1024 1025 static int 1026 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1027 int len) 1028 { 1029 usb_device_request_t req; 1030 usbd_status error; 1031 1032 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1033 1034 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1035 req.bRequest = R92C_REQ_REGS; 1036 USETW(req.wValue, addr); 1037 USETW(req.wIndex, 0); 1038 USETW(req.wLength, len); 1039 error = usbd_do_request(sc->sc_udev, &req, buf); 1040 if (error != USBD_NORMAL_COMPLETION) { 1041 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1042 error, addr, len, 0); 1043 } 1044 return error; 1045 } 1046 1047 static uint8_t 1048 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1049 { 1050 uint8_t val; 1051 1052 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1053 1054 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1055 return 0xff; 1056 1057 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1058 return val; 1059 } 1060 1061 static uint16_t 1062 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1063 { 1064 uint8_t buf[2]; 1065 uint16_t val; 1066 1067 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1068 1069 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1070 return 0xffff; 1071 1072 val = LE_READ_2(&buf[0]); 1073 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1074 return val; 1075 } 1076 1077 static uint32_t 1078 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1079 { 1080 uint8_t buf[4]; 1081 uint32_t val; 1082 1083 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1084 1085 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1086 return 0xffffffff; 1087 1088 val = LE_READ_4(&buf[0]); 1089 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1090 return val; 1091 } 1092 1093 static int 1094 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1095 { 1096 struct r92c_fw_cmd cmd; 1097 uint8_t *cp; 1098 int fwcur; 1099 int ntries; 1100 1101 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1102 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1103 1104 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1105 1106 mutex_enter(&sc->sc_fwcmd_mtx); 1107 fwcur = sc->fwcur; 1108 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1109 1110 /* Wait for current FW box to be empty. */ 1111 for (ntries = 0; ntries < 100; ntries++) { 1112 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1113 break; 1114 urtwn_delay_ms(sc, 2); 1115 } 1116 if (ntries == 100) { 1117 aprint_error_dev(sc->sc_dev, 1118 "could not send firmware command %d\n", id); 1119 mutex_exit(&sc->sc_fwcmd_mtx); 1120 return ETIMEDOUT; 1121 } 1122 1123 memset(&cmd, 0, sizeof(cmd)); 1124 KASSERT(len <= sizeof(cmd.msg)); 1125 memcpy(cmd.msg, buf, len); 1126 1127 /* Write the first word last since that will trigger the FW. */ 1128 cp = (uint8_t *)&cmd; 1129 cmd.id = id; 1130 if (len >= 4) { 1131 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1132 cmd.id |= R92C_CMD_FLAG_EXT; 1133 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1134 &cp[1], 2); 1135 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1136 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1137 ((uint32_t)cp[5] << 24)); 1138 } else { 1139 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1140 &cp[4], 2); 1141 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1142 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1143 ((uint32_t)cp[3] << 24)); 1144 } 1145 } else { 1146 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1147 } 1148 mutex_exit(&sc->sc_fwcmd_mtx); 1149 1150 return 0; 1151 } 1152 1153 static __inline void 1154 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1155 { 1156 1157 sc->sc_rf_write(sc, chain, addr, val); 1158 } 1159 1160 static void 1161 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1162 uint32_t val) 1163 { 1164 1165 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1166 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1167 } 1168 1169 static void 1170 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1171 uint32_t val) 1172 { 1173 1174 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1175 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1176 } 1177 1178 static void 1179 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1180 uint32_t val) 1181 { 1182 1183 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1184 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1185 } 1186 1187 static uint32_t 1188 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1189 { 1190 uint32_t reg[R92C_MAX_CHAINS], val; 1191 1192 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1193 if (chain != 0) { 1194 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1195 } 1196 1197 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1198 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1199 urtwn_delay_ms(sc, 1); 1200 1201 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1202 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1203 R92C_HSSI_PARAM2_READ_EDGE); 1204 urtwn_delay_ms(sc, 1); 1205 1206 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1207 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1208 urtwn_delay_ms(sc, 1); 1209 1210 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1211 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1212 } else { 1213 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1214 } 1215 return MS(val, R92C_LSSI_READBACK_DATA); 1216 } 1217 1218 static int 1219 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1220 { 1221 int ntries; 1222 1223 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1224 1225 urtwn_write_4(sc, R92C_LLT_INIT, 1226 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1227 SM(R92C_LLT_INIT_ADDR, addr) | 1228 SM(R92C_LLT_INIT_DATA, data)); 1229 /* Wait for write operation to complete. */ 1230 for (ntries = 0; ntries < 20; ntries++) { 1231 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1232 R92C_LLT_INIT_OP_NO_ACTIVE) { 1233 /* Done */ 1234 return 0; 1235 } 1236 DELAY(5); 1237 } 1238 return ETIMEDOUT; 1239 } 1240 1241 static uint8_t 1242 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1243 { 1244 uint32_t reg; 1245 int ntries; 1246 1247 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1248 1249 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1250 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1251 reg &= ~R92C_EFUSE_CTRL_VALID; 1252 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1253 1254 /* Wait for read operation to complete. */ 1255 for (ntries = 0; ntries < 100; ntries++) { 1256 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1257 if (reg & R92C_EFUSE_CTRL_VALID) { 1258 /* Done */ 1259 return MS(reg, R92C_EFUSE_CTRL_DATA); 1260 } 1261 DELAY(5); 1262 } 1263 aprint_error_dev(sc->sc_dev, 1264 "could not read efuse byte at address 0x%04x\n", addr); 1265 return 0xff; 1266 } 1267 1268 static void 1269 urtwn_efuse_read(struct urtwn_softc *sc) 1270 { 1271 uint8_t *rom = (uint8_t *)&sc->rom; 1272 uint32_t reg; 1273 uint16_t addr = 0; 1274 uint8_t off, msk; 1275 size_t i; 1276 1277 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1278 1279 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1280 1281 urtwn_efuse_switch_power(sc); 1282 1283 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1284 while (addr < 512) { 1285 reg = urtwn_efuse_read_1(sc, addr); 1286 if (reg == 0xff) 1287 break; 1288 addr++; 1289 off = reg >> 4; 1290 msk = reg & 0xf; 1291 for (i = 0; i < 4; i++) { 1292 if (msk & (1U << i)) 1293 continue; 1294 1295 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1296 addr++; 1297 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1298 addr++; 1299 } 1300 } 1301 #ifdef URTWN_DEBUG 1302 /* Dump ROM content. */ 1303 for (i = 0; i < (int)sizeof(sc->rom); i++) 1304 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1305 #endif 1306 } 1307 1308 static void 1309 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1310 { 1311 uint32_t reg; 1312 1313 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1314 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1315 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1316 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1317 } 1318 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1319 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1320 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1321 reg | R92C_SYS_FUNC_EN_ELDR); 1322 } 1323 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1324 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1325 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1326 urtwn_write_2(sc, R92C_SYS_CLKR, 1327 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1328 } 1329 } 1330 1331 static int 1332 urtwn_read_chipid(struct urtwn_softc *sc) 1333 { 1334 uint32_t reg; 1335 1336 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1337 1338 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1339 ISSET(sc->chip, URTWN_CHIP_92EU)) 1340 return 0; 1341 1342 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1343 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1344 /* test chip, not supported */ 1345 return EIO; 1346 } 1347 if (reg & R92C_SYS_CFG_TYPE_92C) { 1348 sc->chip |= URTWN_CHIP_92C; 1349 /* Check if it is a castrated 8192C. */ 1350 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1351 R92C_HPON_FSM_CHIP_BONDING_ID) == 1352 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1353 sc->chip |= URTWN_CHIP_92C_1T2R; 1354 } 1355 } 1356 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1357 sc->chip |= URTWN_CHIP_UMC; 1358 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1359 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1360 } 1361 } 1362 return 0; 1363 } 1364 1365 #ifdef URTWN_DEBUG 1366 static void 1367 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1368 { 1369 1370 aprint_normal_dev(sc->sc_dev, 1371 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1372 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1373 1374 aprint_normal_dev(sc->sc_dev, 1375 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1376 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1377 1378 aprint_normal_dev(sc->sc_dev, 1379 "macaddr %s\n", 1380 ether_sprintf(rp->macaddr)); 1381 1382 aprint_normal_dev(sc->sc_dev, 1383 "string %s, subcustomer_id %#x\n", 1384 rp->string, rp->subcustomer_id); 1385 1386 aprint_normal_dev(sc->sc_dev, 1387 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1388 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1389 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1390 1391 aprint_normal_dev(sc->sc_dev, 1392 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1393 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1394 rp->ht40_1s_tx_pwr[0][2], 1395 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1396 rp->ht40_1s_tx_pwr[1][2]); 1397 1398 aprint_normal_dev(sc->sc_dev, 1399 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1400 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1401 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1402 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1403 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1404 1405 aprint_normal_dev(sc->sc_dev, 1406 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1407 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1408 rp->ht20_tx_pwr_diff[2] & 0xf, 1409 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1410 rp->ht20_tx_pwr_diff[2] >> 4); 1411 1412 aprint_normal_dev(sc->sc_dev, 1413 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1414 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1415 rp->ofdm_tx_pwr_diff[2] & 0xf, 1416 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1417 rp->ofdm_tx_pwr_diff[2] >> 4); 1418 1419 aprint_normal_dev(sc->sc_dev, 1420 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1421 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1422 rp->ht40_max_pwr[2] & 0xf, 1423 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1424 rp->ht40_max_pwr[2] >> 4); 1425 1426 aprint_normal_dev(sc->sc_dev, 1427 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1428 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1429 rp->ht20_max_pwr[2] & 0xf, 1430 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1431 rp->ht20_max_pwr[2] >> 4); 1432 1433 aprint_normal_dev(sc->sc_dev, 1434 "xtal_calib %d, tssi %d %d, thermal %d\n", 1435 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1436 1437 aprint_normal_dev(sc->sc_dev, 1438 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1439 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1440 1441 aprint_normal_dev(sc->sc_dev, 1442 "channnel_plan %d, version %d customer_id %#x\n", 1443 rp->channel_plan, rp->version, rp->curstomer_id); 1444 } 1445 #endif 1446 1447 static void 1448 urtwn_read_rom(struct urtwn_softc *sc) 1449 { 1450 struct ieee80211com *ic = &sc->sc_ic; 1451 struct r92c_rom *rom = &sc->rom; 1452 1453 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1454 1455 mutex_enter(&sc->sc_write_mtx); 1456 1457 /* Read full ROM image. */ 1458 urtwn_efuse_read(sc); 1459 #ifdef URTWN_DEBUG 1460 if (urtwn_debug & DBG_REG) 1461 urtwn_dump_rom(sc, rom); 1462 #endif 1463 1464 /* XXX Weird but this is what the vendor driver does. */ 1465 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1466 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1467 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1468 1469 DPRINTFN(DBG_INIT, 1470 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1471 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1472 1473 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1474 1475 sc->sc_rf_write = urtwn_r92c_rf_write; 1476 sc->sc_power_on = urtwn_r92c_power_on; 1477 sc->sc_dma_init = urtwn_r92c_dma_init; 1478 1479 mutex_exit(&sc->sc_write_mtx); 1480 } 1481 1482 static void 1483 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1484 { 1485 struct ieee80211com *ic = &sc->sc_ic; 1486 uint8_t *rom = sc->r88e_rom; 1487 uint32_t reg; 1488 uint16_t addr = 0; 1489 uint8_t off, msk, tmp; 1490 int i; 1491 1492 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1493 1494 mutex_enter(&sc->sc_write_mtx); 1495 1496 off = 0; 1497 urtwn_efuse_switch_power(sc); 1498 1499 /* Read full ROM image. */ 1500 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1501 while (addr < 4096) { 1502 reg = urtwn_efuse_read_1(sc, addr); 1503 if (reg == 0xff) 1504 break; 1505 addr++; 1506 if ((reg & 0x1f) == 0x0f) { 1507 tmp = (reg & 0xe0) >> 5; 1508 reg = urtwn_efuse_read_1(sc, addr); 1509 if ((reg & 0x0f) != 0x0f) 1510 off = ((reg & 0xf0) >> 1) | tmp; 1511 addr++; 1512 } else 1513 off = reg >> 4; 1514 msk = reg & 0xf; 1515 for (i = 0; i < 4; i++) { 1516 if (msk & (1 << i)) 1517 continue; 1518 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1519 addr++; 1520 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1521 addr++; 1522 } 1523 } 1524 #ifdef URTWN_DEBUG 1525 if (urtwn_debug & DBG_REG) { 1526 } 1527 #endif 1528 1529 addr = 0x10; 1530 for (i = 0; i < 6; i++) 1531 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1532 for (i = 0; i < 5; i++) 1533 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1534 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1535 if (sc->bw20_tx_pwr_diff & 0x08) 1536 sc->bw20_tx_pwr_diff |= 0xf0; 1537 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1538 if (sc->ofdm_tx_pwr_diff & 0x08) 1539 sc->ofdm_tx_pwr_diff |= 0xf0; 1540 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1541 1542 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1543 1544 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1545 sc->sc_power_on = urtwn_r92e_power_on; 1546 sc->sc_rf_write = urtwn_r92e_rf_write; 1547 } else { 1548 sc->sc_power_on = urtwn_r88e_power_on; 1549 sc->sc_rf_write = urtwn_r88e_rf_write; 1550 } 1551 sc->sc_dma_init = urtwn_r88e_dma_init; 1552 1553 mutex_exit(&sc->sc_write_mtx); 1554 } 1555 1556 static int 1557 urtwn_media_change(struct ifnet *ifp) 1558 { 1559 int error; 1560 1561 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1562 1563 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1564 return error; 1565 1566 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1567 (IFF_UP | IFF_RUNNING)) { 1568 urtwn_init(ifp); 1569 } 1570 return 0; 1571 } 1572 1573 /* 1574 * Initialize rate adaptation in firmware. 1575 */ 1576 static int __noinline 1577 urtwn_ra_init(struct urtwn_softc *sc) 1578 { 1579 static const uint8_t map[] = { 1580 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1581 }; 1582 struct ieee80211com *ic = &sc->sc_ic; 1583 struct ieee80211_node *ni = ic->ic_bss; 1584 struct ieee80211_rateset *rs = &ni->ni_rates; 1585 struct r92c_fw_cmd_macid_cfg cmd; 1586 uint32_t rates, basicrates; 1587 uint32_t rrsr_mask, rrsr_rate; 1588 uint8_t mode; 1589 size_t maxrate, maxbasicrate, i, j; 1590 int error; 1591 1592 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1593 1594 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1595 1596 /* Get normal and basic rates mask. */ 1597 rates = basicrates = 1; 1598 maxrate = maxbasicrate = 0; 1599 for (i = 0; i < rs->rs_nrates; i++) { 1600 /* Convert 802.11 rate to HW rate index. */ 1601 for (j = 0; j < __arraycount(map); j++) { 1602 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1603 break; 1604 } 1605 } 1606 if (j == __arraycount(map)) { 1607 /* Unknown rate, skip. */ 1608 continue; 1609 } 1610 1611 rates |= 1U << j; 1612 if (j > maxrate) { 1613 maxrate = j; 1614 } 1615 1616 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1617 basicrates |= 1U << j; 1618 if (j > maxbasicrate) { 1619 maxbasicrate = j; 1620 } 1621 } 1622 } 1623 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1624 mode = R92C_RAID_11B; 1625 } else { 1626 mode = R92C_RAID_11BG; 1627 } 1628 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1629 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1630 "maxrate=%jx, maxbasicrate=%jx", 1631 rates, basicrates, maxrate, maxbasicrate); 1632 1633 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1634 maxbasicrate |= R92C_RATE_SHORTGI; 1635 maxrate |= R92C_RATE_SHORTGI; 1636 } 1637 1638 /* Set rates mask for group addressed frames. */ 1639 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1640 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1641 cmd.macid |= RTWN_MACID_SHORTGI; 1642 cmd.mask = htole32((mode << 28) | basicrates); 1643 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1644 if (error != 0) { 1645 aprint_error_dev(sc->sc_dev, 1646 "could not add broadcast station\n"); 1647 return error; 1648 } 1649 /* Set initial MRR rate. */ 1650 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1651 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1652 1653 /* Set rates mask for unicast frames. */ 1654 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1655 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1656 cmd.macid |= RTWN_MACID_SHORTGI; 1657 cmd.mask = htole32((mode << 28) | rates); 1658 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1659 if (error != 0) { 1660 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1661 return error; 1662 } 1663 /* Set initial MRR rate. */ 1664 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1665 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1666 1667 rrsr_rate = ic->ic_fixed_rate; 1668 if (rrsr_rate == -1) 1669 rrsr_rate = 11; 1670 1671 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1672 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1673 1674 /* Indicate highest supported rate. */ 1675 ni->ni_txrate = rs->rs_nrates - 1; 1676 1677 return 0; 1678 } 1679 1680 static int 1681 urtwn_get_nettype(struct urtwn_softc *sc) 1682 { 1683 struct ieee80211com *ic = &sc->sc_ic; 1684 int type; 1685 1686 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1687 1688 switch (ic->ic_opmode) { 1689 case IEEE80211_M_STA: 1690 type = R92C_CR_NETTYPE_INFRA; 1691 break; 1692 1693 case IEEE80211_M_IBSS: 1694 type = R92C_CR_NETTYPE_ADHOC; 1695 break; 1696 1697 default: 1698 type = R92C_CR_NETTYPE_NOLINK; 1699 break; 1700 } 1701 1702 return type; 1703 } 1704 1705 static void 1706 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1707 { 1708 uint8_t reg; 1709 1710 URTWNHIST_FUNC(); 1711 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1712 1713 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1714 1715 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1716 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1717 } 1718 1719 static void 1720 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1721 { 1722 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1723 uint64_t tsf; 1724 1725 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1726 1727 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1728 1729 /* Enable TSF synchronization. */ 1730 urtwn_write_1(sc, R92C_BCN_CTRL, 1731 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1732 1733 /* Correct TSF */ 1734 urtwn_write_1(sc, R92C_BCN_CTRL, 1735 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1736 1737 /* Set initial TSF. */ 1738 tsf = ni->ni_tstamp.tsf; 1739 tsf = le64toh(tsf); 1740 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1741 tsf -= IEEE80211_DUR_TU; 1742 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1743 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1744 1745 urtwn_write_1(sc, R92C_BCN_CTRL, 1746 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1747 } 1748 1749 static void 1750 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1751 { 1752 uint8_t reg; 1753 1754 URTWNHIST_FUNC(); 1755 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1756 1757 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1758 1759 if (led == URTWN_LED_LINK) { 1760 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1761 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1762 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1763 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1764 (R92C_LEDCFG0_DIS << 1)); 1765 if (on) { 1766 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1767 R92E_LEDSON; 1768 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1769 } 1770 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1771 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1772 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1773 if (!on) { 1774 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1775 urtwn_write_1(sc, R92C_LEDCFG2, 1776 reg | R92C_LEDCFG0_DIS); 1777 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1778 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1779 reg & 0xfe); 1780 } 1781 } else { 1782 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1783 if (!on) { 1784 reg |= R92C_LEDCFG0_DIS; 1785 } 1786 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1787 } 1788 sc->ledlink = on; /* Save LED state. */ 1789 } 1790 } 1791 1792 static void 1793 urtwn_calib_to(void *arg) 1794 { 1795 struct urtwn_softc *sc = arg; 1796 1797 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1798 1799 if (sc->sc_dying) 1800 return; 1801 1802 /* Do it in a process context. */ 1803 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1804 } 1805 1806 /* ARGSUSED */ 1807 static void 1808 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1809 { 1810 struct r92c_fw_cmd_rssi cmd; 1811 struct r92e_fw_cmd_rssi cmde; 1812 1813 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1814 1815 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1816 goto restart_timer; 1817 1818 mutex_enter(&sc->sc_write_mtx); 1819 if (sc->avg_pwdb != -1) { 1820 /* Indicate Rx signal strength to FW for rate adaptation. */ 1821 memset(&cmd, 0, sizeof(cmd)); 1822 memset(&cmde, 0, sizeof(cmde)); 1823 cmd.macid = 0; /* BSS. */ 1824 cmde.macid = 0; /* BSS. */ 1825 cmd.pwdb = sc->avg_pwdb; 1826 cmde.pwdb = sc->avg_pwdb; 1827 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1828 sc->avg_pwdb, 0, 0, 0); 1829 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1830 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1831 sizeof(cmd)); 1832 } else { 1833 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1834 sizeof(cmde)); 1835 } 1836 } 1837 1838 /* Do temperature compensation. */ 1839 urtwn_temp_calib(sc); 1840 mutex_exit(&sc->sc_write_mtx); 1841 1842 restart_timer: 1843 if (!sc->sc_dying) { 1844 /* Restart calibration timer. */ 1845 callout_schedule(&sc->sc_calib_to, hz); 1846 } 1847 } 1848 1849 static void 1850 urtwn_next_scan(void *arg) 1851 { 1852 struct urtwn_softc *sc = arg; 1853 int s; 1854 1855 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1856 1857 if (sc->sc_dying) 1858 return; 1859 1860 s = splnet(); 1861 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1862 ieee80211_next_scan(&sc->sc_ic); 1863 splx(s); 1864 } 1865 1866 static void 1867 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1868 { 1869 URTWNHIST_FUNC(); 1870 URTWNHIST_CALLARGS("new node %06jx%06jx", 1871 ni->ni_macaddr[0] << 2 | 1872 ni->ni_macaddr[1] << 1 | 1873 ni->ni_macaddr[2], 1874 ni->ni_macaddr[3] << 2 | 1875 ni->ni_macaddr[4] << 1 | 1876 ni->ni_macaddr[5], 1877 0, 0); 1878 /* start with lowest Tx rate */ 1879 ni->ni_txrate = 0; 1880 } 1881 1882 static int 1883 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1884 { 1885 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1886 struct urtwn_cmd_newstate cmd; 1887 1888 URTWNHIST_FUNC(); 1889 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1890 1891 callout_stop(&sc->sc_scan_to); 1892 callout_stop(&sc->sc_calib_to); 1893 1894 /* Do it in a process context. */ 1895 cmd.state = nstate; 1896 cmd.arg = arg; 1897 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1898 return 0; 1899 } 1900 1901 static void 1902 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1903 { 1904 struct urtwn_cmd_newstate *cmd = arg; 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 struct ieee80211_node *ni; 1907 enum ieee80211_state ostate = ic->ic_state; 1908 enum ieee80211_state nstate = cmd->state; 1909 uint32_t reg; 1910 uint8_t sifs_time, msr; 1911 int s; 1912 1913 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1914 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1915 1916 s = splnet(); 1917 mutex_enter(&sc->sc_write_mtx); 1918 1919 callout_stop(&sc->sc_scan_to); 1920 callout_stop(&sc->sc_calib_to); 1921 1922 switch (ostate) { 1923 case IEEE80211_S_INIT: 1924 break; 1925 1926 case IEEE80211_S_SCAN: 1927 if (nstate != IEEE80211_S_SCAN) { 1928 /* 1929 * End of scanning 1930 */ 1931 /* flush 4-AC Queue after site_survey */ 1932 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1933 1934 /* Allow Rx from our BSSID only. */ 1935 urtwn_write_4(sc, R92C_RCR, 1936 urtwn_read_4(sc, R92C_RCR) | 1937 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1938 } 1939 break; 1940 1941 case IEEE80211_S_AUTH: 1942 case IEEE80211_S_ASSOC: 1943 break; 1944 1945 case IEEE80211_S_RUN: 1946 /* Turn link LED off. */ 1947 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1948 1949 /* Set media status to 'No Link'. */ 1950 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1951 1952 /* Stop Rx of data frames. */ 1953 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1954 1955 /* Reset TSF. */ 1956 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1957 1958 /* Disable TSF synchronization. */ 1959 urtwn_write_1(sc, R92C_BCN_CTRL, 1960 urtwn_read_1(sc, R92C_BCN_CTRL) | 1961 R92C_BCN_CTRL_DIS_TSF_UDT0); 1962 1963 /* Back to 20MHz mode */ 1964 urtwn_set_chan(sc, ic->ic_curchan, 1965 IEEE80211_HTINFO_2NDCHAN_NONE); 1966 1967 if (ic->ic_opmode == IEEE80211_M_IBSS || 1968 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1969 /* Stop BCN */ 1970 urtwn_write_1(sc, R92C_BCN_CTRL, 1971 urtwn_read_1(sc, R92C_BCN_CTRL) & 1972 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1973 } 1974 1975 /* Reset EDCA parameters. */ 1976 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1977 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1978 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1979 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1980 1981 /* flush all cam entries */ 1982 urtwn_cam_init(sc); 1983 break; 1984 } 1985 1986 switch (nstate) { 1987 case IEEE80211_S_INIT: 1988 /* Turn link LED off. */ 1989 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1990 break; 1991 1992 case IEEE80211_S_SCAN: 1993 if (ostate != IEEE80211_S_SCAN) { 1994 /* 1995 * Begin of scanning 1996 */ 1997 1998 /* Set gain for scanning. */ 1999 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2000 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2001 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2002 2003 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2004 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2005 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2006 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2007 } 2008 2009 /* Set media status to 'No Link'. */ 2010 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2011 2012 /* Allow Rx from any BSSID. */ 2013 urtwn_write_4(sc, R92C_RCR, 2014 urtwn_read_4(sc, R92C_RCR) & 2015 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2016 2017 /* Stop Rx of data frames. */ 2018 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2019 2020 /* Disable update TSF */ 2021 urtwn_write_1(sc, R92C_BCN_CTRL, 2022 urtwn_read_1(sc, R92C_BCN_CTRL) | 2023 R92C_BCN_CTRL_DIS_TSF_UDT0); 2024 } 2025 2026 /* Make link LED blink during scan. */ 2027 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2028 2029 /* Pause AC Tx queues. */ 2030 urtwn_write_1(sc, R92C_TXPAUSE, 2031 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2032 2033 urtwn_set_chan(sc, ic->ic_curchan, 2034 IEEE80211_HTINFO_2NDCHAN_NONE); 2035 2036 /* Start periodic scan. */ 2037 if (!sc->sc_dying) 2038 callout_schedule(&sc->sc_scan_to, hz / 5); 2039 break; 2040 2041 case IEEE80211_S_AUTH: 2042 /* Set initial gain under link. */ 2043 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2044 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2045 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2046 2047 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2048 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2049 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2050 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2051 } 2052 2053 /* Set media status to 'No Link'. */ 2054 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2055 2056 /* Allow Rx from any BSSID. */ 2057 urtwn_write_4(sc, R92C_RCR, 2058 urtwn_read_4(sc, R92C_RCR) & 2059 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2060 2061 urtwn_set_chan(sc, ic->ic_curchan, 2062 IEEE80211_HTINFO_2NDCHAN_NONE); 2063 break; 2064 2065 case IEEE80211_S_ASSOC: 2066 break; 2067 2068 case IEEE80211_S_RUN: 2069 ni = ic->ic_bss; 2070 2071 /* XXX: Set 20MHz mode */ 2072 urtwn_set_chan(sc, ic->ic_curchan, 2073 IEEE80211_HTINFO_2NDCHAN_NONE); 2074 2075 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2076 /* Back to 20MHz mode */ 2077 urtwn_set_chan(sc, ic->ic_curchan, 2078 IEEE80211_HTINFO_2NDCHAN_NONE); 2079 2080 /* Set media status to 'No Link'. */ 2081 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2082 2083 /* Enable Rx of data frames. */ 2084 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2085 2086 /* Allow Rx from any BSSID. */ 2087 urtwn_write_4(sc, R92C_RCR, 2088 urtwn_read_4(sc, R92C_RCR) & 2089 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2090 2091 /* Accept Rx data/control/management frames */ 2092 urtwn_write_4(sc, R92C_RCR, 2093 urtwn_read_4(sc, R92C_RCR) | 2094 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2095 2096 /* Turn link LED on. */ 2097 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2098 break; 2099 } 2100 2101 /* Set media status to 'Associated'. */ 2102 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2103 2104 /* Set BSSID. */ 2105 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2106 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2107 2108 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2109 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2110 } else { 2111 /* 802.11b/g */ 2112 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2113 } 2114 2115 /* Enable Rx of data frames. */ 2116 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2117 2118 /* Set beacon interval. */ 2119 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2120 2121 msr = urtwn_read_1(sc, R92C_MSR); 2122 msr &= R92C_MSR_MASK; 2123 switch (ic->ic_opmode) { 2124 case IEEE80211_M_STA: 2125 /* Allow Rx from our BSSID only. */ 2126 urtwn_write_4(sc, R92C_RCR, 2127 urtwn_read_4(sc, R92C_RCR) | 2128 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2129 2130 /* Enable TSF synchronization. */ 2131 urtwn_tsf_sync_enable(sc); 2132 2133 msr |= R92C_MSR_INFRA; 2134 break; 2135 case IEEE80211_M_HOSTAP: 2136 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2137 2138 /* Allow Rx from any BSSID. */ 2139 urtwn_write_4(sc, R92C_RCR, 2140 urtwn_read_4(sc, R92C_RCR) & 2141 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2142 2143 /* Reset TSF timer to zero. */ 2144 reg = urtwn_read_4(sc, R92C_TCR); 2145 reg &= ~0x01; 2146 urtwn_write_4(sc, R92C_TCR, reg); 2147 reg |= 0x01; 2148 urtwn_write_4(sc, R92C_TCR, reg); 2149 2150 msr |= R92C_MSR_AP; 2151 break; 2152 default: 2153 msr |= R92C_MSR_ADHOC; 2154 break; 2155 } 2156 urtwn_write_1(sc, R92C_MSR, msr); 2157 2158 sifs_time = 10; 2159 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2160 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2161 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2162 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2163 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2164 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2165 2166 /* Initialize rate adaptation. */ 2167 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2168 ISSET(sc->chip, URTWN_CHIP_92EU)) 2169 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2170 else 2171 urtwn_ra_init(sc); 2172 2173 /* Turn link LED on. */ 2174 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2175 2176 /* Reset average RSSI. */ 2177 sc->avg_pwdb = -1; 2178 2179 /* Reset temperature calibration state machine. */ 2180 sc->thcal_state = 0; 2181 sc->thcal_lctemp = 0; 2182 2183 /* Start periodic calibration. */ 2184 if (!sc->sc_dying) 2185 callout_schedule(&sc->sc_calib_to, hz); 2186 break; 2187 } 2188 2189 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2190 2191 mutex_exit(&sc->sc_write_mtx); 2192 splx(s); 2193 } 2194 2195 static int 2196 urtwn_wme_update(struct ieee80211com *ic) 2197 { 2198 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2199 2200 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2201 2202 /* don't override default WME values if WME is not actually enabled */ 2203 if (!(ic->ic_flags & IEEE80211_F_WME)) 2204 return 0; 2205 2206 /* Do it in a process context. */ 2207 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2208 return 0; 2209 } 2210 2211 static void 2212 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2213 { 2214 static const uint16_t ac2reg[WME_NUM_AC] = { 2215 R92C_EDCA_BE_PARAM, 2216 R92C_EDCA_BK_PARAM, 2217 R92C_EDCA_VI_PARAM, 2218 R92C_EDCA_VO_PARAM 2219 }; 2220 struct ieee80211com *ic = &sc->sc_ic; 2221 const struct wmeParams *wmep; 2222 int ac, aifs, slottime; 2223 int s; 2224 2225 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2226 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2227 2228 s = splnet(); 2229 mutex_enter(&sc->sc_write_mtx); 2230 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2231 for (ac = 0; ac < WME_NUM_AC; ac++) { 2232 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2233 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2234 aifs = wmep->wmep_aifsn * slottime + 10; 2235 urtwn_write_4(sc, ac2reg[ac], 2236 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2237 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2238 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2239 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2240 } 2241 mutex_exit(&sc->sc_write_mtx); 2242 splx(s); 2243 } 2244 2245 static void 2246 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2247 { 2248 int pwdb; 2249 2250 URTWNHIST_FUNC(); 2251 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2252 2253 /* Convert antenna signal to percentage. */ 2254 if (rssi <= -100 || rssi >= 20) 2255 pwdb = 0; 2256 else if (rssi >= 0) 2257 pwdb = 100; 2258 else 2259 pwdb = 100 + rssi; 2260 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2261 if (rate <= 3) { 2262 /* CCK gain is smaller than OFDM/MCS gain. */ 2263 pwdb += 6; 2264 if (pwdb > 100) 2265 pwdb = 100; 2266 if (pwdb <= 14) 2267 pwdb -= 4; 2268 else if (pwdb <= 26) 2269 pwdb -= 8; 2270 else if (pwdb <= 34) 2271 pwdb -= 6; 2272 else if (pwdb <= 42) 2273 pwdb -= 2; 2274 } 2275 } 2276 if (sc->avg_pwdb == -1) /* Init. */ 2277 sc->avg_pwdb = pwdb; 2278 else if (sc->avg_pwdb < pwdb) 2279 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2280 else 2281 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2282 2283 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2284 rate, rssi, pwdb, sc->avg_pwdb); 2285 } 2286 2287 static int8_t 2288 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2289 { 2290 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2291 struct r92c_rx_phystat *phy; 2292 struct r92c_rx_cck *cck; 2293 uint8_t rpt; 2294 int8_t rssi; 2295 2296 URTWNHIST_FUNC(); 2297 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2298 2299 if (rate <= 3) { 2300 cck = (struct r92c_rx_cck *)physt; 2301 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2302 rpt = (cck->agc_rpt >> 5) & 0x3; 2303 rssi = (cck->agc_rpt & 0x1f) << 1; 2304 } else { 2305 rpt = (cck->agc_rpt >> 6) & 0x3; 2306 rssi = cck->agc_rpt & 0x3e; 2307 } 2308 rssi = cckoff[rpt] - rssi; 2309 } else { /* OFDM/HT. */ 2310 phy = (struct r92c_rx_phystat *)physt; 2311 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2312 } 2313 return rssi; 2314 } 2315 2316 static int8_t 2317 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2318 { 2319 struct r92c_rx_phystat *phy; 2320 struct r88e_rx_cck *cck; 2321 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2322 int8_t rssi; 2323 2324 URTWNHIST_FUNC(); 2325 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2326 2327 rssi = 0; 2328 if (rate <= 3) { 2329 cck = (struct r88e_rx_cck *)physt; 2330 cck_agc_rpt = cck->agc_rpt; 2331 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2332 vga_idx = cck_agc_rpt & 0x1f; 2333 switch (lna_idx) { 2334 case 7: 2335 if (vga_idx <= 27) 2336 rssi = -100 + 2* (27 - vga_idx); 2337 else 2338 rssi = -100; 2339 break; 2340 case 6: 2341 rssi = -48 + 2 * (2 - vga_idx); 2342 break; 2343 case 5: 2344 rssi = -42 + 2 * (7 - vga_idx); 2345 break; 2346 case 4: 2347 rssi = -36 + 2 * (7 - vga_idx); 2348 break; 2349 case 3: 2350 rssi = -24 + 2 * (7 - vga_idx); 2351 break; 2352 case 2: 2353 rssi = -12 + 2 * (5 - vga_idx); 2354 break; 2355 case 1: 2356 rssi = 8 - (2 * vga_idx); 2357 break; 2358 case 0: 2359 rssi = 14 - (2 * vga_idx); 2360 break; 2361 } 2362 rssi += 6; 2363 } else { /* OFDM/HT. */ 2364 phy = (struct r92c_rx_phystat *)physt; 2365 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2366 } 2367 return rssi; 2368 } 2369 2370 static void 2371 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2372 { 2373 struct ieee80211com *ic = &sc->sc_ic; 2374 struct ifnet *ifp = ic->ic_ifp; 2375 struct ieee80211_frame *wh; 2376 struct ieee80211_node *ni; 2377 struct r92c_rx_desc_usb *stat; 2378 uint32_t rxdw0, rxdw3; 2379 struct mbuf *m; 2380 uint8_t rate; 2381 int8_t rssi = 0; 2382 int s, infosz; 2383 2384 URTWNHIST_FUNC(); 2385 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2386 2387 stat = (struct r92c_rx_desc_usb *)buf; 2388 rxdw0 = le32toh(stat->rxdw0); 2389 rxdw3 = le32toh(stat->rxdw3); 2390 2391 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2392 /* 2393 * This should not happen since we setup our Rx filter 2394 * to not receive these frames. 2395 */ 2396 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2397 if_statinc(ifp, if_ierrors); 2398 return; 2399 } 2400 /* 2401 * XXX: This will drop most control packets. Do we really 2402 * want this in IEEE80211_M_MONITOR mode? 2403 */ 2404 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2405 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2406 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2407 ic->ic_stats.is_rx_tooshort++; 2408 if_statinc(ifp, if_ierrors); 2409 return; 2410 } 2411 if (__predict_false(pktlen > MCLBYTES)) { 2412 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2413 if_statinc(ifp, if_ierrors); 2414 return; 2415 } 2416 2417 rate = MS(rxdw3, R92C_RXDW3_RATE); 2418 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2419 2420 /* Get RSSI from PHY status descriptor if present. */ 2421 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2422 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2423 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2424 else 2425 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2426 /* Update our average RSSI. */ 2427 urtwn_update_avgrssi(sc, rate, rssi); 2428 } 2429 2430 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2431 pktlen, rate, infosz, rssi); 2432 2433 MGETHDR(m, M_DONTWAIT, MT_DATA); 2434 if (__predict_false(m == NULL)) { 2435 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2436 ic->ic_stats.is_rx_nobuf++; 2437 if_statinc(ifp, if_ierrors); 2438 return; 2439 } 2440 if (pktlen > (int)MHLEN) { 2441 MCLGET(m, M_DONTWAIT); 2442 if (__predict_false(!(m->m_flags & M_EXT))) { 2443 aprint_error_dev(sc->sc_dev, 2444 "couldn't allocate rx mbuf cluster\n"); 2445 m_freem(m); 2446 ic->ic_stats.is_rx_nobuf++; 2447 if_statinc(ifp, if_ierrors); 2448 return; 2449 } 2450 } 2451 2452 /* Finalize mbuf. */ 2453 m_set_rcvif(m, ifp); 2454 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2455 memcpy(mtod(m, uint8_t *), wh, pktlen); 2456 m->m_pkthdr.len = m->m_len = pktlen; 2457 2458 s = splnet(); 2459 if (__predict_false(sc->sc_drvbpf != NULL)) { 2460 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2461 2462 tap->wr_flags = 0; 2463 if (!(rxdw3 & R92C_RXDW3_HT)) { 2464 switch (rate) { 2465 /* CCK. */ 2466 case 0: tap->wr_rate = 2; break; 2467 case 1: tap->wr_rate = 4; break; 2468 case 2: tap->wr_rate = 11; break; 2469 case 3: tap->wr_rate = 22; break; 2470 /* OFDM. */ 2471 case 4: tap->wr_rate = 12; break; 2472 case 5: tap->wr_rate = 18; break; 2473 case 6: tap->wr_rate = 24; break; 2474 case 7: tap->wr_rate = 36; break; 2475 case 8: tap->wr_rate = 48; break; 2476 case 9: tap->wr_rate = 72; break; 2477 case 10: tap->wr_rate = 96; break; 2478 case 11: tap->wr_rate = 108; break; 2479 } 2480 } else if (rate >= 12) { /* MCS0~15. */ 2481 /* Bit 7 set means HT MCS instead of rate. */ 2482 tap->wr_rate = 0x80 | (rate - 12); 2483 } 2484 tap->wr_dbm_antsignal = rssi; 2485 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2486 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2487 2488 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2489 } 2490 2491 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2492 2493 /* push the frame up to the 802.11 stack */ 2494 ieee80211_input(ic, m, ni, rssi, 0); 2495 2496 /* Node is no longer needed. */ 2497 ieee80211_free_node(ni); 2498 2499 splx(s); 2500 } 2501 2502 static void 2503 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2504 { 2505 struct urtwn_rx_data *data = priv; 2506 struct urtwn_softc *sc = data->sc; 2507 struct r92c_rx_desc_usb *stat; 2508 size_t pidx = data->pidx; 2509 uint32_t rxdw0; 2510 uint8_t *buf; 2511 int len, totlen, pktlen, infosz, npkts; 2512 2513 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2514 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2515 2516 mutex_enter(&sc->sc_rx_mtx); 2517 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2518 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2519 /* Put this Rx buffer back to our free list. */ 2520 mutex_exit(&sc->sc_rx_mtx); 2521 2522 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2523 if (status == USBD_STALLED) 2524 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2525 else if (status != USBD_CANCELLED) 2526 goto resubmit; 2527 return; 2528 } 2529 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2530 2531 if (__predict_false(len < (int)sizeof(*stat))) { 2532 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2533 goto resubmit; 2534 } 2535 buf = data->buf; 2536 2537 /* Get the number of encapsulated frames. */ 2538 stat = (struct r92c_rx_desc_usb *)buf; 2539 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2540 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2541 else 2542 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2543 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2544 2545 if (npkts != 0) 2546 rnd_add_uint32(&sc->rnd_source, npkts); 2547 2548 /* Process all of them. */ 2549 while (npkts-- > 0) { 2550 if (__predict_false(len < (int)sizeof(*stat))) { 2551 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2552 len, 0, 0, 0); 2553 break; 2554 } 2555 stat = (struct r92c_rx_desc_usb *)buf; 2556 rxdw0 = le32toh(stat->rxdw0); 2557 2558 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2559 if (__predict_false(pktlen == 0)) { 2560 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2561 break; 2562 } 2563 2564 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2565 2566 /* Make sure everything fits in xfer. */ 2567 totlen = sizeof(*stat) + infosz + pktlen; 2568 if (__predict_false(totlen > len)) { 2569 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2570 (int)sizeof(*stat), infosz, pktlen, len); 2571 break; 2572 } 2573 2574 /* Process 802.11 frame. */ 2575 urtwn_rx_frame(sc, buf, pktlen); 2576 2577 /* Next chunk is 128-byte aligned. */ 2578 totlen = roundup2(totlen, 128); 2579 buf += totlen; 2580 len -= totlen; 2581 } 2582 2583 resubmit: 2584 /* Setup a new transfer. */ 2585 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2586 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2587 (void)usbd_transfer(xfer); 2588 } 2589 2590 static void 2591 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2592 { 2593 size_t pidx = data->pidx; 2594 2595 mutex_enter(&sc->sc_tx_mtx); 2596 /* Put this Tx buffer back to our free list. */ 2597 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2598 mutex_exit(&sc->sc_tx_mtx); 2599 } 2600 2601 static void 2602 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2603 { 2604 struct urtwn_tx_data *data = priv; 2605 struct urtwn_softc *sc = data->sc; 2606 struct ifnet *ifp = &sc->sc_if; 2607 size_t pidx = data->pidx; 2608 int s; 2609 2610 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2611 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2612 2613 urtwn_put_tx_data(sc, data); 2614 2615 s = splnet(); 2616 sc->tx_timer = 0; 2617 ifp->if_flags &= ~IFF_OACTIVE; 2618 2619 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2620 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2621 if (status == USBD_STALLED) { 2622 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2623 usbd_clear_endpoint_stall_async(pipe); 2624 } 2625 device_printf(sc->sc_dev, "device timeout\n"); 2626 if_statinc(ifp, if_oerrors); 2627 } 2628 splx(s); 2629 return; 2630 } 2631 2632 if_statinc(ifp, if_opackets); 2633 urtwn_start(ifp); 2634 splx(s); 2635 2636 } 2637 2638 static int 2639 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2640 struct urtwn_tx_data *data) 2641 { 2642 struct ieee80211com *ic = &sc->sc_ic; 2643 struct ieee80211_frame *wh; 2644 struct ieee80211_key *k = NULL; 2645 struct r92c_tx_desc_usb *txd; 2646 size_t i, padsize, xferlen, txd_len; 2647 uint16_t seq, sum; 2648 uint8_t raid, type, tid; 2649 int s, hasqos, error; 2650 2651 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2652 2653 wh = mtod(m, struct ieee80211_frame *); 2654 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2655 txd_len = sizeof(*txd); 2656 2657 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2658 txd_len = 32; 2659 2660 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2661 k = ieee80211_crypto_encap(ic, ni, m); 2662 if (k == NULL) { 2663 urtwn_put_tx_data(sc, data); 2664 m_free(m); 2665 return ENOBUFS; 2666 } 2667 2668 /* packet header may have moved, reset our local pointer */ 2669 wh = mtod(m, struct ieee80211_frame *); 2670 } 2671 2672 if (__predict_false(sc->sc_drvbpf != NULL)) { 2673 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2674 2675 tap->wt_flags = 0; 2676 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2677 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2678 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2679 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2680 2681 /* XXX: set tap->wt_rate? */ 2682 2683 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2684 } 2685 2686 /* non-qos data frames */ 2687 tid = R92C_TXDW1_QSEL_BE; 2688 if ((hasqos = ieee80211_has_qos(wh))) { 2689 /* data frames in 11n mode */ 2690 struct ieee80211_qosframe *qwh = (void *)wh; 2691 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2692 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2693 tid = R92C_TXDW1_QSEL_MGNT; 2694 } 2695 2696 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2697 padsize = 8; 2698 else 2699 padsize = 0; 2700 2701 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2702 padsize = 0; 2703 2704 /* Fill Tx descriptor. */ 2705 txd = (struct r92c_tx_desc_usb *)data->buf; 2706 memset(txd, 0, txd_len + padsize); 2707 2708 txd->txdw0 |= htole32( 2709 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2710 SM(R92C_TXDW0_OFFSET, txd_len)); 2711 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2712 txd->txdw0 |= htole32( 2713 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2714 } 2715 2716 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2717 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2718 2719 /* fix pad field */ 2720 if (padsize > 0) { 2721 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2722 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2723 } 2724 2725 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2726 type == IEEE80211_FC0_TYPE_DATA) { 2727 if (ic->ic_curmode == IEEE80211_MODE_11B) 2728 raid = R92C_RAID_11B; 2729 else 2730 raid = R92C_RAID_11BG; 2731 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2732 tid, raid, 0, 0); 2733 2734 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2735 txd->txdw1 |= htole32( 2736 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2737 SM(R92C_TXDW1_QSEL, tid) | 2738 SM(R92C_TXDW1_RAID, raid) | 2739 R92C_TXDW1_AGGBK); 2740 } else 2741 txd->txdw1 |= htole32( 2742 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2743 SM(R92C_TXDW1_QSEL, tid) | 2744 SM(R92C_TXDW1_RAID, raid) | 2745 R92C_TXDW1_AGGBK); 2746 2747 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2748 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2749 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2750 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2751 2752 if (hasqos) { 2753 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2754 } 2755 2756 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2757 /* for 11g */ 2758 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2759 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2760 R92C_TXDW4_HWRTSEN); 2761 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2762 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2763 R92C_TXDW4_HWRTSEN); 2764 } 2765 } 2766 /* Send RTS at OFDM24. */ 2767 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2768 txd->txdw5 |= htole32(0x0001ff00); 2769 /* Send data at OFDM54. */ 2770 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2771 txd->txdw5 |= htole32(0x13 & 0x3f); 2772 else 2773 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2774 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2775 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2776 txd->txdw1 |= htole32( 2777 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2778 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2779 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2780 2781 /* Force CCK1. */ 2782 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2783 /* Use 1Mbps */ 2784 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2785 } else { 2786 /* broadcast or multicast packets */ 2787 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2788 txd->txdw1 |= htole32( 2789 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2790 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2791 2792 /* Force CCK1. */ 2793 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2794 /* Use 1Mbps */ 2795 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2796 } 2797 /* Set sequence number */ 2798 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2799 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2800 txd->txdseq |= htole16(seq); 2801 2802 if (!hasqos) { 2803 /* Use HW sequence numbering for non-QoS frames. */ 2804 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2805 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2806 } 2807 } else { 2808 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2809 R92E_HWSEQ_SHIFT); 2810 if (!hasqos) { 2811 /* Use HW sequence numbering for non-QoS frames. */ 2812 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2813 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2814 } 2815 } 2816 2817 /* Compute Tx descriptor checksum. */ 2818 sum = 0; 2819 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2820 sum ^= ((uint16_t *)txd)[i]; 2821 txd->txdsum = sum; /* NB: already little endian. */ 2822 2823 xferlen = txd_len + m->m_pkthdr.len + padsize; 2824 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2825 2826 s = splnet(); 2827 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2828 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2829 urtwn_txeof); 2830 error = usbd_transfer(data->xfer); 2831 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2832 error != USBD_IN_PROGRESS)) { 2833 splx(s); 2834 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2835 return error; 2836 } 2837 splx(s); 2838 return 0; 2839 } 2840 2841 struct urtwn_tx_data * 2842 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2843 { 2844 struct urtwn_tx_data *data = NULL; 2845 2846 mutex_enter(&sc->sc_tx_mtx); 2847 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2848 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2849 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2850 } 2851 mutex_exit(&sc->sc_tx_mtx); 2852 2853 return data; 2854 } 2855 2856 static void 2857 urtwn_start(struct ifnet *ifp) 2858 { 2859 struct urtwn_softc *sc = ifp->if_softc; 2860 struct ieee80211com *ic = &sc->sc_ic; 2861 struct urtwn_tx_data *data; 2862 struct ether_header *eh; 2863 struct ieee80211_node *ni; 2864 struct mbuf *m; 2865 2866 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2867 2868 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2869 return; 2870 2871 data = NULL; 2872 for (;;) { 2873 /* Send pending management frames first. */ 2874 IF_POLL(&ic->ic_mgtq, m); 2875 if (m != NULL) { 2876 /* Use AC_VO for management frames. */ 2877 2878 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2879 2880 if (data == NULL) { 2881 ifp->if_flags |= IFF_OACTIVE; 2882 DPRINTFN(DBG_TX, "empty tx_free_list", 2883 0, 0, 0, 0); 2884 return; 2885 } 2886 IF_DEQUEUE(&ic->ic_mgtq, m); 2887 ni = M_GETCTX(m, struct ieee80211_node *); 2888 M_CLEARCTX(m); 2889 goto sendit; 2890 } 2891 if (ic->ic_state != IEEE80211_S_RUN) 2892 break; 2893 2894 /* Encapsulate and send data frames. */ 2895 IFQ_POLL(&ifp->if_snd, m); 2896 if (m == NULL) 2897 break; 2898 2899 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2900 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2901 uint8_t qid = WME_AC_BE; 2902 if (ieee80211_has_qos(wh)) { 2903 /* data frames in 11n mode */ 2904 struct ieee80211_qosframe *qwh = (void *)wh; 2905 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2906 qid = TID_TO_WME_AC(tid); 2907 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2908 qid = WME_AC_VO; 2909 } 2910 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2911 2912 if (data == NULL) { 2913 ifp->if_flags |= IFF_OACTIVE; 2914 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2915 return; 2916 } 2917 IFQ_DEQUEUE(&ifp->if_snd, m); 2918 2919 if (m->m_len < (int)sizeof(*eh) && 2920 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2921 device_printf(sc->sc_dev, "m_pullup failed\n"); 2922 if_statinc(ifp, if_oerrors); 2923 urtwn_put_tx_data(sc, data); 2924 m_freem(m); 2925 continue; 2926 } 2927 eh = mtod(m, struct ether_header *); 2928 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2929 if (ni == NULL) { 2930 device_printf(sc->sc_dev, 2931 "unable to find transmit node\n"); 2932 if_statinc(ifp, if_oerrors); 2933 urtwn_put_tx_data(sc, data); 2934 m_freem(m); 2935 continue; 2936 } 2937 2938 bpf_mtap(ifp, m, BPF_D_OUT); 2939 2940 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2941 ieee80211_free_node(ni); 2942 device_printf(sc->sc_dev, 2943 "unable to encapsulate packet\n"); 2944 if_statinc(ifp, if_oerrors); 2945 urtwn_put_tx_data(sc, data); 2946 m_freem(m); 2947 continue; 2948 } 2949 sendit: 2950 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2951 2952 if (urtwn_tx(sc, m, ni, data) != 0) { 2953 m_freem(m); 2954 ieee80211_free_node(ni); 2955 device_printf(sc->sc_dev, 2956 "unable to transmit packet\n"); 2957 if_statinc(ifp, if_oerrors); 2958 continue; 2959 } 2960 m_freem(m); 2961 ieee80211_free_node(ni); 2962 sc->tx_timer = 5; 2963 ifp->if_timer = 1; 2964 } 2965 } 2966 2967 static void 2968 urtwn_watchdog(struct ifnet *ifp) 2969 { 2970 struct urtwn_softc *sc = ifp->if_softc; 2971 2972 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2973 2974 ifp->if_timer = 0; 2975 2976 if (sc->tx_timer > 0) { 2977 if (--sc->tx_timer == 0) { 2978 device_printf(sc->sc_dev, "device timeout\n"); 2979 /* urtwn_init(ifp); XXX needs a process context! */ 2980 if_statinc(ifp, if_oerrors); 2981 return; 2982 } 2983 ifp->if_timer = 1; 2984 } 2985 ieee80211_watchdog(&sc->sc_ic); 2986 } 2987 2988 static int 2989 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2990 { 2991 struct urtwn_softc *sc = ifp->if_softc; 2992 struct ieee80211com *ic = &sc->sc_ic; 2993 int s, error = 0; 2994 2995 URTWNHIST_FUNC(); 2996 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 2997 0, 0); 2998 2999 s = splnet(); 3000 3001 switch (cmd) { 3002 case SIOCSIFFLAGS: 3003 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3004 break; 3005 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3006 case IFF_UP | IFF_RUNNING: 3007 break; 3008 case IFF_UP: 3009 urtwn_init(ifp); 3010 break; 3011 case IFF_RUNNING: 3012 urtwn_stop(ifp, 1); 3013 break; 3014 case 0: 3015 break; 3016 } 3017 break; 3018 3019 case SIOCADDMULTI: 3020 case SIOCDELMULTI: 3021 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3022 /* setup multicast filter, etc */ 3023 error = 0; 3024 } 3025 break; 3026 3027 case SIOCS80211CHANNEL: 3028 /* 3029 * This allows for fast channel switching in monitor mode 3030 * (used by kismet). In IBSS mode, we must explicitly reset 3031 * the interface to generate a new beacon frame. 3032 */ 3033 error = ieee80211_ioctl(ic, cmd, data); 3034 if (error == ENETRESET && 3035 ic->ic_opmode == IEEE80211_M_MONITOR) { 3036 urtwn_set_chan(sc, ic->ic_curchan, 3037 IEEE80211_HTINFO_2NDCHAN_NONE); 3038 error = 0; 3039 } 3040 break; 3041 3042 default: 3043 error = ieee80211_ioctl(ic, cmd, data); 3044 break; 3045 } 3046 if (error == ENETRESET) { 3047 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3048 (IFF_UP | IFF_RUNNING) && 3049 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3050 urtwn_init(ifp); 3051 } 3052 error = 0; 3053 } 3054 3055 splx(s); 3056 3057 return error; 3058 } 3059 3060 static __inline int 3061 urtwn_power_on(struct urtwn_softc *sc) 3062 { 3063 3064 return sc->sc_power_on(sc); 3065 } 3066 3067 static int 3068 urtwn_r92c_power_on(struct urtwn_softc *sc) 3069 { 3070 uint32_t reg; 3071 int ntries; 3072 3073 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3074 3075 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3076 3077 /* Wait for autoload done bit. */ 3078 for (ntries = 0; ntries < 1000; ntries++) { 3079 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3080 break; 3081 DELAY(5); 3082 } 3083 if (ntries == 1000) { 3084 aprint_error_dev(sc->sc_dev, 3085 "timeout waiting for chip autoload\n"); 3086 return ETIMEDOUT; 3087 } 3088 3089 /* Unlock ISO/CLK/Power control register. */ 3090 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3091 /* Move SPS into PWM mode. */ 3092 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3093 DELAY(5); 3094 3095 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3096 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3097 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3098 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3099 DELAY(100); 3100 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3101 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3102 ~R92C_SYS_ISO_CTRL_MD2PP); 3103 } 3104 3105 /* Auto enable WLAN. */ 3106 urtwn_write_2(sc, R92C_APS_FSMCO, 3107 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3108 for (ntries = 0; ntries < 1000; ntries++) { 3109 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3110 R92C_APS_FSMCO_APFM_ONMAC)) 3111 break; 3112 DELAY(100); 3113 } 3114 if (ntries == 1000) { 3115 aprint_error_dev(sc->sc_dev, 3116 "timeout waiting for MAC auto ON\n"); 3117 return ETIMEDOUT; 3118 } 3119 3120 /* Enable radio, GPIO and LED functions. */ 3121 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3122 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3123 urtwn_write_2(sc, R92C_APS_FSMCO, 3124 R92C_APS_FSMCO_AFSM_HSUS | 3125 R92C_APS_FSMCO_PDN_EN | 3126 R92C_APS_FSMCO_PFM_ALDN); 3127 3128 /* Release RF digital isolation. */ 3129 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3130 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3131 3132 /* Initialize MAC. */ 3133 urtwn_write_1(sc, R92C_APSD_CTRL, 3134 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3135 for (ntries = 0; ntries < 200; ntries++) { 3136 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3137 R92C_APSD_CTRL_OFF_STATUS)) 3138 break; 3139 DELAY(5); 3140 } 3141 if (ntries == 200) { 3142 aprint_error_dev(sc->sc_dev, 3143 "timeout waiting for MAC initialization\n"); 3144 return ETIMEDOUT; 3145 } 3146 3147 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3148 reg = urtwn_read_2(sc, R92C_CR); 3149 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3150 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3151 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3152 R92C_CR_ENSEC; 3153 urtwn_write_2(sc, R92C_CR, reg); 3154 3155 urtwn_write_1(sc, 0xfe10, 0x19); 3156 return 0; 3157 } 3158 3159 static int 3160 urtwn_r92e_power_on(struct urtwn_softc *sc) 3161 { 3162 uint32_t reg; 3163 uint32_t val; 3164 int ntries; 3165 3166 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3167 3168 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3169 3170 /* Enable radio, GPIO and LED functions. */ 3171 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3172 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3173 urtwn_write_2(sc, R92C_APS_FSMCO, 3174 R92C_APS_FSMCO_AFSM_HSUS | 3175 R92C_APS_FSMCO_PDN_EN | 3176 R92C_APS_FSMCO_PFM_ALDN); 3177 3178 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3179 /* LDO. */ 3180 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3181 } 3182 else { 3183 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3184 R92C_SYS_SWR_CTRL2) & 0xffff); 3185 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3186 } 3187 3188 for (ntries = 0; ntries < 2; ntries++) { 3189 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3190 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3191 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3192 R92C_AFE_CTRL4)); 3193 } 3194 3195 /* Reset BB. */ 3196 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3197 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3198 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3199 3200 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3201 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3202 3203 /* Disable HWPDN. */ 3204 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3205 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3206 3207 /* Disable WL suspend. */ 3208 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3209 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3210 R92C_APS_FSMCO_AFSM_HSUS)); 3211 3212 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3213 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3214 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3215 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3216 for (ntries = 0; ntries < 10000; ntries++) { 3217 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3218 R92C_APS_FSMCO_APFM_ONMAC; 3219 if (val == 0x0) 3220 break; 3221 DELAY(10); 3222 } 3223 if (ntries == 10000) { 3224 aprint_error_dev(sc->sc_dev, 3225 "timeout waiting for chip power up\n"); 3226 return ETIMEDOUT; 3227 } 3228 3229 urtwn_write_2(sc, R92C_CR, 0x00); 3230 reg = urtwn_read_2(sc, R92C_CR); 3231 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3232 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3233 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3234 urtwn_write_2(sc, R92C_CR, reg); 3235 3236 return 0; 3237 } 3238 3239 static int 3240 urtwn_r88e_power_on(struct urtwn_softc *sc) 3241 { 3242 uint32_t reg; 3243 uint8_t val; 3244 int ntries; 3245 3246 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3247 3248 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3249 3250 /* Wait for power ready bit. */ 3251 for (ntries = 0; ntries < 5000; ntries++) { 3252 val = urtwn_read_1(sc, 0x6) & 0x2; 3253 if (val == 0x2) 3254 break; 3255 DELAY(10); 3256 } 3257 if (ntries == 5000) { 3258 aprint_error_dev(sc->sc_dev, 3259 "timeout waiting for chip power up\n"); 3260 return ETIMEDOUT; 3261 } 3262 3263 /* Reset BB. */ 3264 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3265 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3266 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3267 3268 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3269 3270 /* Disable HWPDN. */ 3271 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3272 3273 /* Disable WL suspend. */ 3274 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3275 3276 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3277 for (ntries = 0; ntries < 5000; ntries++) { 3278 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3279 break; 3280 DELAY(10); 3281 } 3282 if (ntries == 5000) 3283 return ETIMEDOUT; 3284 3285 /* Enable LDO normal mode. */ 3286 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3287 3288 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3289 urtwn_write_2(sc, R92C_CR, 0); 3290 reg = urtwn_read_2(sc, R92C_CR); 3291 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3292 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3293 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3294 urtwn_write_2(sc, R92C_CR, reg); 3295 3296 return 0; 3297 } 3298 3299 static int __noinline 3300 urtwn_llt_init(struct urtwn_softc *sc) 3301 { 3302 size_t i, page_count, pktbuf_count; 3303 uint32_t val; 3304 int error; 3305 3306 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3307 3308 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3309 3310 if (sc->chip & URTWN_CHIP_88E) 3311 page_count = R88E_TX_PAGE_COUNT; 3312 else if (sc->chip & URTWN_CHIP_92EU) 3313 page_count = R92E_TX_PAGE_COUNT; 3314 else 3315 page_count = R92C_TX_PAGE_COUNT; 3316 if (sc->chip & URTWN_CHIP_88E) 3317 pktbuf_count = R88E_TXPKTBUF_COUNT; 3318 else if (sc->chip & URTWN_CHIP_92EU) 3319 pktbuf_count = R88E_TXPKTBUF_COUNT; 3320 else 3321 pktbuf_count = R92C_TXPKTBUF_COUNT; 3322 3323 if (sc->chip & URTWN_CHIP_92EU) { 3324 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3325 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3326 DELAY(100); 3327 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3328 if (val & R92E_AUTO_LLT_EN) 3329 return EIO; 3330 return 0; 3331 } 3332 3333 /* Reserve pages [0; page_count]. */ 3334 for (i = 0; i < page_count; i++) { 3335 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3336 return error; 3337 } 3338 /* NB: 0xff indicates end-of-list. */ 3339 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3340 return error; 3341 /* 3342 * Use pages [page_count + 1; pktbuf_count - 1] 3343 * as ring buffer. 3344 */ 3345 for (++i; i < pktbuf_count - 1; i++) { 3346 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3347 return error; 3348 } 3349 /* Make the last page point to the beginning of the ring buffer. */ 3350 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3351 return error; 3352 } 3353 3354 static void 3355 urtwn_fw_reset(struct urtwn_softc *sc) 3356 { 3357 uint16_t reg; 3358 int ntries; 3359 3360 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3361 3362 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3363 3364 /* Tell 8051 to reset itself. */ 3365 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3366 3367 /* Wait until 8051 resets by itself. */ 3368 for (ntries = 0; ntries < 100; ntries++) { 3369 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3370 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3371 return; 3372 DELAY(50); 3373 } 3374 /* Force 8051 reset. */ 3375 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3376 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3377 } 3378 3379 static void 3380 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3381 { 3382 uint16_t reg; 3383 3384 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3385 3386 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3387 3388 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3389 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3390 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3391 } 3392 DELAY(50); 3393 3394 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3395 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3396 DELAY(50); 3397 3398 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3399 DELAY(50); 3400 3401 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3402 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3403 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3404 } 3405 DELAY(50); 3406 3407 } 3408 3409 static int 3410 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3411 { 3412 uint32_t reg; 3413 int off, mlen, error = 0; 3414 3415 URTWNHIST_FUNC(); 3416 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3417 page, (uintptr_t)buf, len, 0); 3418 3419 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3420 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3421 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3422 3423 off = R92C_FW_START_ADDR; 3424 while (len > 0) { 3425 if (len > 196) 3426 mlen = 196; 3427 else if (len > 4) 3428 mlen = 4; 3429 else 3430 mlen = 1; 3431 error = urtwn_write_region(sc, off, buf, mlen); 3432 if (error != 0) 3433 break; 3434 off += mlen; 3435 buf += mlen; 3436 len -= mlen; 3437 } 3438 return error; 3439 } 3440 3441 static int __noinline 3442 urtwn_load_firmware(struct urtwn_softc *sc) 3443 { 3444 firmware_handle_t fwh; 3445 const struct r92c_fw_hdr *hdr; 3446 const char *name; 3447 u_char *fw, *ptr; 3448 size_t len; 3449 uint32_t reg; 3450 int mlen, ntries, page, error; 3451 3452 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3453 3454 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3455 3456 /* Read firmware image from the filesystem. */ 3457 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3458 name = "rtl8188eufw.bin"; 3459 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3460 name = "rtl8192eefw.bin"; 3461 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3462 URTWN_CHIP_UMC_A_CUT) 3463 name = "rtl8192cfwU.bin"; 3464 else 3465 name = "rtl8192cfw.bin"; 3466 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3467 aprint_error_dev(sc->sc_dev, 3468 "failed load firmware of file %s (error %d)\n", name, 3469 error); 3470 return error; 3471 } 3472 const size_t fwlen = len = firmware_get_size(fwh); 3473 fw = firmware_malloc(len); 3474 if (fw == NULL) { 3475 aprint_error_dev(sc->sc_dev, 3476 "failed to allocate firmware memory\n"); 3477 firmware_close(fwh); 3478 return ENOMEM; 3479 } 3480 error = firmware_read(fwh, 0, fw, len); 3481 firmware_close(fwh); 3482 if (error != 0) { 3483 aprint_error_dev(sc->sc_dev, 3484 "failed to read firmware (error %d)\n", error); 3485 firmware_free(fw, fwlen); 3486 return error; 3487 } 3488 3489 len = fwlen; 3490 ptr = fw; 3491 hdr = (const struct r92c_fw_hdr *)ptr; 3492 /* Check if there is a valid FW header and skip it. */ 3493 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3494 (le16toh(hdr->signature) >> 4) == 0x88e || 3495 (le16toh(hdr->signature) >> 4) == 0x92e || 3496 (le16toh(hdr->signature) >> 4) == 0x92c) { 3497 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3498 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3499 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3500 hdr->month, hdr->date, hdr->hour, hdr->minute); 3501 ptr += sizeof(*hdr); 3502 len -= sizeof(*hdr); 3503 } 3504 3505 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3506 /* Reset MCU ready status */ 3507 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3508 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3509 ISSET(sc->chip, URTWN_CHIP_92EU)) 3510 urtwn_r88e_fw_reset(sc); 3511 else 3512 urtwn_fw_reset(sc); 3513 } 3514 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3515 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3516 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3517 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3518 R92C_SYS_FUNC_EN_CPUEN); 3519 } 3520 3521 /* download enabled */ 3522 urtwn_write_1(sc, R92C_MCUFWDL, 3523 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3524 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3525 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3526 3527 /* Reset the FWDL checksum. */ 3528 urtwn_write_1(sc, R92C_MCUFWDL, 3529 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3530 3531 DELAY(50); 3532 /* download firmware */ 3533 for (page = 0; len > 0; page++) { 3534 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3535 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3536 if (error != 0) { 3537 aprint_error_dev(sc->sc_dev, 3538 "could not load firmware page %d\n", page); 3539 goto fail; 3540 } 3541 ptr += mlen; 3542 len -= mlen; 3543 } 3544 3545 /* download disable */ 3546 urtwn_write_1(sc, R92C_MCUFWDL, 3547 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3548 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3549 3550 /* Wait for checksum report. */ 3551 for (ntries = 0; ntries < 1000; ntries++) { 3552 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3553 break; 3554 DELAY(5); 3555 } 3556 if (ntries == 1000) { 3557 aprint_error_dev(sc->sc_dev, 3558 "timeout waiting for checksum report\n"); 3559 error = ETIMEDOUT; 3560 goto fail; 3561 } 3562 3563 /* Wait for firmware readiness. */ 3564 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3565 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3566 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3567 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3568 ISSET(sc->chip, URTWN_CHIP_92EU)) 3569 urtwn_r88e_fw_reset(sc); 3570 for (ntries = 0; ntries < 6000; ntries++) { 3571 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3572 break; 3573 DELAY(5); 3574 } 3575 if (ntries == 6000) { 3576 aprint_error_dev(sc->sc_dev, 3577 "timeout waiting for firmware readiness\n"); 3578 error = ETIMEDOUT; 3579 goto fail; 3580 } 3581 fail: 3582 firmware_free(fw, fwlen); 3583 return error; 3584 } 3585 3586 static __inline int 3587 urtwn_dma_init(struct urtwn_softc *sc) 3588 { 3589 3590 return sc->sc_dma_init(sc); 3591 } 3592 3593 static int 3594 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3595 { 3596 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3597 uint32_t reg; 3598 int error; 3599 3600 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3601 3602 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3603 3604 /* Initialize LLT table. */ 3605 error = urtwn_llt_init(sc); 3606 if (error != 0) 3607 return error; 3608 3609 /* Get Tx queues to USB endpoints mapping. */ 3610 hashq = hasnq = haslq = 0; 3611 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3612 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3613 if (MS(reg, R92C_USB_EP_HQ) != 0) 3614 hashq = 1; 3615 if (MS(reg, R92C_USB_EP_NQ) != 0) 3616 hasnq = 1; 3617 if (MS(reg, R92C_USB_EP_LQ) != 0) 3618 haslq = 1; 3619 nqueues = hashq + hasnq + haslq; 3620 if (nqueues == 0) 3621 return EIO; 3622 /* Get the number of pages for each queue. */ 3623 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3624 /* The remaining pages are assigned to the high priority queue. */ 3625 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3626 3627 /* Set number of pages for normal priority queue. */ 3628 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3629 urtwn_write_4(sc, R92C_RQPN, 3630 /* Set number of pages for public queue. */ 3631 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3632 /* Set number of pages for high priority queue. */ 3633 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3634 /* Set number of pages for low priority queue. */ 3635 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3636 /* Load values. */ 3637 R92C_RQPN_LD); 3638 3639 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3640 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3641 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3642 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3643 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3644 3645 /* Set queue to USB pipe mapping. */ 3646 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3647 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3648 if (nqueues == 1) { 3649 if (hashq) { 3650 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3651 } else if (hasnq) { 3652 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3653 } else { 3654 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3655 } 3656 } else if (nqueues == 2) { 3657 /* All 2-endpoints configs have a high priority queue. */ 3658 if (!hashq) { 3659 return EIO; 3660 } 3661 if (hasnq) { 3662 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3663 } else { 3664 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3665 } 3666 } else { 3667 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3668 } 3669 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3670 3671 /* Set Tx/Rx transfer page boundary. */ 3672 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3673 3674 /* Set Tx/Rx transfer page size. */ 3675 urtwn_write_1(sc, R92C_PBP, 3676 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3677 return 0; 3678 } 3679 3680 static int 3681 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3682 { 3683 usb_interface_descriptor_t *id; 3684 uint32_t reg; 3685 int nqueues; 3686 int error; 3687 3688 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3689 3690 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3691 3692 /* Initialize LLT table. */ 3693 error = urtwn_llt_init(sc); 3694 if (error != 0) 3695 return error; 3696 3697 /* Get Tx queues to USB endpoints mapping. */ 3698 id = usbd_get_interface_descriptor(sc->sc_iface); 3699 nqueues = id->bNumEndpoints - 1; 3700 if (nqueues == 0) 3701 return EIO; 3702 3703 /* Set number of pages for normal priority queue. */ 3704 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3705 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3706 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3707 3708 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3709 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3710 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3711 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3712 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3713 3714 /* Set queue to USB pipe mapping. */ 3715 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3716 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3717 if (nqueues == 1) 3718 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3719 else if (nqueues == 2) 3720 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3721 else 3722 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3723 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3724 3725 /* Set Tx/Rx transfer page boundary. */ 3726 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3727 3728 /* Set Tx/Rx transfer page size. */ 3729 urtwn_write_1(sc, R92C_PBP, 3730 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3731 3732 return 0; 3733 } 3734 3735 static void __noinline 3736 urtwn_mac_init(struct urtwn_softc *sc) 3737 { 3738 size_t i; 3739 3740 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3741 3742 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3743 3744 /* Write MAC initialization values. */ 3745 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3746 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3747 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3748 rtl8188eu_mac[i].val); 3749 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3750 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3751 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3752 rtl8192eu_mac[i].val); 3753 } else { 3754 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3755 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3756 rtl8192cu_mac[i].val); 3757 } 3758 } 3759 3760 static void __noinline 3761 urtwn_bb_init(struct urtwn_softc *sc) 3762 { 3763 const struct rtwn_bb_prog *prog; 3764 uint32_t reg; 3765 uint8_t crystalcap; 3766 size_t i; 3767 3768 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3769 3770 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3771 3772 /* Enable BB and RF. */ 3773 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3774 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3775 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3776 R92C_SYS_FUNC_EN_DIO_RF); 3777 3778 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3779 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3780 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3781 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3782 } 3783 3784 urtwn_write_1(sc, R92C_RF_CTRL, 3785 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3786 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3787 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3788 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3789 3790 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3791 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3792 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3793 urtwn_write_1(sc, 0x15, 0xe9); 3794 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3795 } 3796 3797 /* Select BB programming based on board type. */ 3798 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3799 prog = &rtl8188eu_bb_prog; 3800 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3801 prog = &rtl8192eu_bb_prog; 3802 else if (!(sc->chip & URTWN_CHIP_92C)) { 3803 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3804 prog = &rtl8188ce_bb_prog; 3805 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3806 prog = &rtl8188ru_bb_prog; 3807 } else { 3808 prog = &rtl8188cu_bb_prog; 3809 } 3810 } else { 3811 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3812 prog = &rtl8192ce_bb_prog; 3813 } else { 3814 prog = &rtl8192cu_bb_prog; 3815 } 3816 } 3817 /* Write BB initialization values. */ 3818 for (i = 0; i < prog->count; i++) { 3819 /* additional delay depend on registers */ 3820 switch (prog->regs[i]) { 3821 case 0xfe: 3822 urtwn_delay_ms(sc, 50); 3823 break; 3824 case 0xfd: 3825 urtwn_delay_ms(sc, 5); 3826 break; 3827 case 0xfc: 3828 urtwn_delay_ms(sc, 1); 3829 break; 3830 case 0xfb: 3831 DELAY(50); 3832 break; 3833 case 0xfa: 3834 DELAY(5); 3835 break; 3836 case 0xf9: 3837 DELAY(1); 3838 break; 3839 } 3840 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3841 DELAY(1); 3842 } 3843 3844 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3845 /* 8192C 1T only configuration. */ 3846 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3847 reg = (reg & ~0x00000003) | 0x2; 3848 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3849 3850 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3851 reg = (reg & ~0x00300033) | 0x00200022; 3852 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3853 3854 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3855 reg = (reg & ~0xff000000) | (0x45 << 24); 3856 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3857 3858 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3859 reg = (reg & ~0x000000ff) | 0x23; 3860 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3861 3862 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3863 reg = (reg & ~0x00000030) | (1 << 4); 3864 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3865 3866 reg = urtwn_bb_read(sc, 0xe74); 3867 reg = (reg & ~0x0c000000) | (2 << 26); 3868 urtwn_bb_write(sc, 0xe74, reg); 3869 reg = urtwn_bb_read(sc, 0xe78); 3870 reg = (reg & ~0x0c000000) | (2 << 26); 3871 urtwn_bb_write(sc, 0xe78, reg); 3872 reg = urtwn_bb_read(sc, 0xe7c); 3873 reg = (reg & ~0x0c000000) | (2 << 26); 3874 urtwn_bb_write(sc, 0xe7c, reg); 3875 reg = urtwn_bb_read(sc, 0xe80); 3876 reg = (reg & ~0x0c000000) | (2 << 26); 3877 urtwn_bb_write(sc, 0xe80, reg); 3878 reg = urtwn_bb_read(sc, 0xe88); 3879 reg = (reg & ~0x0c000000) | (2 << 26); 3880 urtwn_bb_write(sc, 0xe88, reg); 3881 } 3882 3883 /* Write AGC values. */ 3884 for (i = 0; i < prog->agccount; i++) { 3885 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3886 DELAY(1); 3887 } 3888 3889 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3890 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3891 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3892 DELAY(1); 3893 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3894 DELAY(1); 3895 } 3896 3897 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3898 crystalcap = sc->r88e_rom[0xb9]; 3899 if (crystalcap == 0x00) 3900 crystalcap = 0x20; 3901 crystalcap &= 0x3f; 3902 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3903 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3904 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3905 crystalcap | crystalcap << 6)); 3906 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3907 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3908 crystalcap = sc->r88e_rom[0xb9]; 3909 if (crystalcap == 0xff) 3910 crystalcap = 0x20; 3911 crystalcap &= 0x3f; 3912 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3913 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3914 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3915 crystalcap | crystalcap << 6)); 3916 } else { 3917 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3918 R92C_HSSI_PARAM2_CCK_HIPWR) { 3919 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3920 } 3921 } 3922 } 3923 3924 static void __noinline 3925 urtwn_rf_init(struct urtwn_softc *sc) 3926 { 3927 const struct rtwn_rf_prog *prog; 3928 uint32_t reg, mask, saved; 3929 size_t i, j, idx; 3930 3931 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3932 3933 /* Select RF programming based on board type. */ 3934 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3935 prog = rtl8188eu_rf_prog; 3936 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3937 prog = rtl8192eu_rf_prog; 3938 else if (!(sc->chip & URTWN_CHIP_92C)) { 3939 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3940 prog = rtl8188ce_rf_prog; 3941 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3942 prog = rtl8188ru_rf_prog; 3943 } else { 3944 prog = rtl8188cu_rf_prog; 3945 } 3946 } else { 3947 prog = rtl8192ce_rf_prog; 3948 } 3949 3950 for (i = 0; i < sc->nrxchains; i++) { 3951 /* Save RF_ENV control type. */ 3952 idx = i / 2; 3953 mask = 0xffffU << ((i % 2) * 16); 3954 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3955 3956 /* Set RF_ENV enable. */ 3957 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3958 reg |= 0x100000; 3959 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3960 DELAY(50); 3961 3962 /* Set RF_ENV output high. */ 3963 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3964 reg |= 0x10; 3965 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3966 DELAY(50); 3967 3968 /* Set address and data lengths of RF registers. */ 3969 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3970 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3971 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3972 DELAY(50); 3973 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3974 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3975 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3976 DELAY(50); 3977 3978 /* Write RF initialization values for this chain. */ 3979 for (j = 0; j < prog[i].count; j++) { 3980 if (prog[i].regs[j] >= 0xf9 && 3981 prog[i].regs[j] <= 0xfe) { 3982 /* 3983 * These are fake RF registers offsets that 3984 * indicate a delay is required. 3985 */ 3986 urtwn_delay_ms(sc, 50); 3987 continue; 3988 } 3989 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3990 DELAY(5); 3991 } 3992 3993 /* Restore RF_ENV control type. */ 3994 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3995 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3996 } 3997 3998 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3999 URTWN_CHIP_UMC_A_CUT) { 4000 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4001 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4002 } 4003 4004 /* Cache RF register CHNLBW. */ 4005 for (i = 0; i < 2; i++) { 4006 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4007 } 4008 } 4009 4010 static void __noinline 4011 urtwn_cam_init(struct urtwn_softc *sc) 4012 { 4013 uint32_t content, command; 4014 uint8_t idx; 4015 size_t i; 4016 4017 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4018 4019 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4020 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4021 return; 4022 4023 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4024 content = (idx & 3) 4025 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4026 | R92C_CAM_VALID; 4027 4028 command = R92C_CAMCMD_POLLING 4029 | R92C_CAMCMD_WRITE 4030 | R92C_CAM_CTL0(idx); 4031 4032 urtwn_write_4(sc, R92C_CAMWRITE, content); 4033 urtwn_write_4(sc, R92C_CAMCMD, command); 4034 } 4035 4036 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4037 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4038 if (i == 0) { 4039 content = (idx & 3) 4040 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4041 | R92C_CAM_VALID; 4042 } else { 4043 content = 0; 4044 } 4045 4046 command = R92C_CAMCMD_POLLING 4047 | R92C_CAMCMD_WRITE 4048 | R92C_CAM_CTL0(idx) 4049 | i; 4050 4051 urtwn_write_4(sc, R92C_CAMWRITE, content); 4052 urtwn_write_4(sc, R92C_CAMCMD, command); 4053 } 4054 } 4055 4056 /* Invalidate all CAM entries. */ 4057 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4058 } 4059 4060 static void __noinline 4061 urtwn_pa_bias_init(struct urtwn_softc *sc) 4062 { 4063 uint8_t reg; 4064 size_t i; 4065 4066 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4067 4068 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4069 4070 for (i = 0; i < sc->nrxchains; i++) { 4071 if (sc->pa_setting & (1U << i)) 4072 continue; 4073 4074 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4075 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4076 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4077 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4078 } 4079 if (!(sc->pa_setting & 0x10)) { 4080 reg = urtwn_read_1(sc, 0x16); 4081 reg = (reg & ~0xf0) | 0x90; 4082 urtwn_write_1(sc, 0x16, reg); 4083 } 4084 } 4085 4086 static void __noinline 4087 urtwn_rxfilter_init(struct urtwn_softc *sc) 4088 { 4089 4090 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4091 4092 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4093 4094 /* Initialize Rx filter. */ 4095 /* TODO: use better filter for monitor mode. */ 4096 urtwn_write_4(sc, R92C_RCR, 4097 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4098 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4099 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4100 /* Accept all multicast frames. */ 4101 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4102 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4103 /* Accept all management frames. */ 4104 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4105 /* Reject all control frames. */ 4106 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4107 /* Accept all data frames. */ 4108 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4109 } 4110 4111 static void __noinline 4112 urtwn_edca_init(struct urtwn_softc *sc) 4113 { 4114 4115 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4116 4117 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4118 4119 /* set spec SIFS (used in NAV) */ 4120 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4121 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4122 4123 /* set SIFS CCK/OFDM */ 4124 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4125 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4126 4127 /* TXOP */ 4128 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4129 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4130 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4131 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4132 } 4133 4134 static void 4135 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4136 uint16_t power[URTWN_RIDX_COUNT]) 4137 { 4138 uint32_t reg; 4139 4140 URTWNHIST_FUNC(); 4141 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4142 4143 /* Write per-CCK rate Tx power. */ 4144 if (chain == 0) { 4145 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4146 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4147 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4148 4149 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4150 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4151 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4152 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4153 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4154 } else { 4155 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4156 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4157 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4158 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4159 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4160 4161 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4162 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4163 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4164 } 4165 /* Write per-OFDM rate Tx power. */ 4166 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4167 SM(R92C_TXAGC_RATE06, power[ 4]) | 4168 SM(R92C_TXAGC_RATE09, power[ 5]) | 4169 SM(R92C_TXAGC_RATE12, power[ 6]) | 4170 SM(R92C_TXAGC_RATE18, power[ 7])); 4171 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4172 SM(R92C_TXAGC_RATE24, power[ 8]) | 4173 SM(R92C_TXAGC_RATE36, power[ 9]) | 4174 SM(R92C_TXAGC_RATE48, power[10]) | 4175 SM(R92C_TXAGC_RATE54, power[11])); 4176 /* Write per-MCS Tx power. */ 4177 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4178 SM(R92C_TXAGC_MCS00, power[12]) | 4179 SM(R92C_TXAGC_MCS01, power[13]) | 4180 SM(R92C_TXAGC_MCS02, power[14]) | 4181 SM(R92C_TXAGC_MCS03, power[15])); 4182 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4183 SM(R92C_TXAGC_MCS04, power[16]) | 4184 SM(R92C_TXAGC_MCS05, power[17]) | 4185 SM(R92C_TXAGC_MCS06, power[18]) | 4186 SM(R92C_TXAGC_MCS07, power[19])); 4187 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4188 SM(R92C_TXAGC_MCS08, power[20]) | 4189 SM(R92C_TXAGC_MCS09, power[21]) | 4190 SM(R92C_TXAGC_MCS10, power[22]) | 4191 SM(R92C_TXAGC_MCS11, power[23])); 4192 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4193 SM(R92C_TXAGC_MCS12, power[24]) | 4194 SM(R92C_TXAGC_MCS13, power[25]) | 4195 SM(R92C_TXAGC_MCS14, power[26]) | 4196 SM(R92C_TXAGC_MCS15, power[27])); 4197 } 4198 4199 static void 4200 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4201 uint16_t power[URTWN_RIDX_COUNT]) 4202 { 4203 struct r92c_rom *rom = &sc->rom; 4204 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4205 const struct rtwn_txpwr *base; 4206 int ridx, group; 4207 4208 URTWNHIST_FUNC(); 4209 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4210 4211 /* Determine channel group. */ 4212 if (chan <= 3) { 4213 group = 0; 4214 } else if (chan <= 9) { 4215 group = 1; 4216 } else { 4217 group = 2; 4218 } 4219 4220 /* Get original Tx power based on board type and RF chain. */ 4221 if (!(sc->chip & URTWN_CHIP_92C)) { 4222 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4223 base = &rtl8188ru_txagc[chain]; 4224 } else { 4225 base = &rtl8192cu_txagc[chain]; 4226 } 4227 } else { 4228 base = &rtl8192cu_txagc[chain]; 4229 } 4230 4231 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4232 if (sc->regulatory == 0) { 4233 for (ridx = 0; ridx <= 3; ridx++) { 4234 power[ridx] = base->pwr[0][ridx]; 4235 } 4236 } 4237 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4238 if (sc->regulatory == 3) { 4239 power[ridx] = base->pwr[0][ridx]; 4240 /* Apply vendor limits. */ 4241 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4242 maxpow = rom->ht40_max_pwr[group]; 4243 } else { 4244 maxpow = rom->ht20_max_pwr[group]; 4245 } 4246 maxpow = (maxpow >> (chain * 4)) & 0xf; 4247 if (power[ridx] > maxpow) { 4248 power[ridx] = maxpow; 4249 } 4250 } else if (sc->regulatory == 1) { 4251 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4252 power[ridx] = base->pwr[group][ridx]; 4253 } 4254 } else if (sc->regulatory != 2) { 4255 power[ridx] = base->pwr[0][ridx]; 4256 } 4257 } 4258 4259 /* Compute per-CCK rate Tx power. */ 4260 cckpow = rom->cck_tx_pwr[chain][group]; 4261 for (ridx = 0; ridx <= 3; ridx++) { 4262 power[ridx] += cckpow; 4263 if (power[ridx] > R92C_MAX_TX_PWR) { 4264 power[ridx] = R92C_MAX_TX_PWR; 4265 } 4266 } 4267 4268 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4269 if (sc->ntxchains > 1) { 4270 /* Apply reduction for 2 spatial streams. */ 4271 diff = rom->ht40_2s_tx_pwr_diff[group]; 4272 diff = (diff >> (chain * 4)) & 0xf; 4273 htpow = (htpow > diff) ? htpow - diff : 0; 4274 } 4275 4276 /* Compute per-OFDM rate Tx power. */ 4277 diff = rom->ofdm_tx_pwr_diff[group]; 4278 diff = (diff >> (chain * 4)) & 0xf; 4279 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4280 for (ridx = 4; ridx <= 11; ridx++) { 4281 power[ridx] += ofdmpow; 4282 if (power[ridx] > R92C_MAX_TX_PWR) { 4283 power[ridx] = R92C_MAX_TX_PWR; 4284 } 4285 } 4286 4287 /* Compute per-MCS Tx power. */ 4288 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4289 diff = rom->ht20_tx_pwr_diff[group]; 4290 diff = (diff >> (chain * 4)) & 0xf; 4291 htpow += diff; /* HT40->HT20 correction. */ 4292 } 4293 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4294 power[ridx] += htpow; 4295 if (power[ridx] > R92C_MAX_TX_PWR) { 4296 power[ridx] = R92C_MAX_TX_PWR; 4297 } 4298 } 4299 #ifdef URTWN_DEBUG 4300 if (urtwn_debug & DBG_RF) { 4301 /* Dump per-rate Tx power values. */ 4302 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4303 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4304 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4305 } 4306 #endif 4307 } 4308 4309 void 4310 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4311 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4312 { 4313 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4314 const struct rtwn_r88e_txpwr *base; 4315 int ridx, group; 4316 4317 URTWNHIST_FUNC(); 4318 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4319 4320 /* Determine channel group. */ 4321 if (chan <= 2) 4322 group = 0; 4323 else if (chan <= 5) 4324 group = 1; 4325 else if (chan <= 8) 4326 group = 2; 4327 else if (chan <= 11) 4328 group = 3; 4329 else if (chan <= 13) 4330 group = 4; 4331 else 4332 group = 5; 4333 4334 /* Get original Tx power based on board type and RF chain. */ 4335 base = &rtl8188eu_txagc[chain]; 4336 4337 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4338 if (sc->regulatory == 0) { 4339 for (ridx = 0; ridx <= 3; ridx++) 4340 power[ridx] = base->pwr[0][ridx]; 4341 } 4342 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4343 if (sc->regulatory == 3) 4344 power[ridx] = base->pwr[0][ridx]; 4345 else if (sc->regulatory == 1) { 4346 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4347 power[ridx] = base->pwr[group][ridx]; 4348 } else if (sc->regulatory != 2) 4349 power[ridx] = base->pwr[0][ridx]; 4350 } 4351 4352 /* Compute per-CCK rate Tx power. */ 4353 cckpow = sc->cck_tx_pwr[group]; 4354 for (ridx = 0; ridx <= 3; ridx++) { 4355 power[ridx] += cckpow; 4356 if (power[ridx] > R92C_MAX_TX_PWR) 4357 power[ridx] = R92C_MAX_TX_PWR; 4358 } 4359 4360 htpow = sc->ht40_tx_pwr[group]; 4361 4362 /* Compute per-OFDM rate Tx power. */ 4363 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4364 for (ridx = 4; ridx <= 11; ridx++) { 4365 power[ridx] += ofdmpow; 4366 if (power[ridx] > R92C_MAX_TX_PWR) 4367 power[ridx] = R92C_MAX_TX_PWR; 4368 } 4369 4370 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4371 for (ridx = 12; ridx <= 27; ridx++) { 4372 power[ridx] += bw20pow; 4373 if (power[ridx] > R92C_MAX_TX_PWR) 4374 power[ridx] = R92C_MAX_TX_PWR; 4375 } 4376 } 4377 4378 static void 4379 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4380 { 4381 uint16_t power[URTWN_RIDX_COUNT]; 4382 size_t i; 4383 4384 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4385 4386 for (i = 0; i < sc->ntxchains; i++) { 4387 /* Compute per-rate Tx power values. */ 4388 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4389 ISSET(sc->chip, URTWN_CHIP_92EU)) 4390 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4391 else 4392 urtwn_get_txpower(sc, i, chan, ht40m, power); 4393 /* Write per-rate Tx power values to hardware. */ 4394 urtwn_write_txpower(sc, i, power); 4395 } 4396 } 4397 4398 static void __noinline 4399 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4400 { 4401 struct ieee80211com *ic = &sc->sc_ic; 4402 u_int chan; 4403 size_t i; 4404 4405 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4406 4407 URTWNHIST_FUNC(); 4408 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4409 4410 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4411 4412 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4413 chan += 2; 4414 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4415 chan -= 2; 4416 } 4417 4418 /* Set Tx power for this new channel. */ 4419 urtwn_set_txpower(sc, chan, ht40m); 4420 4421 for (i = 0; i < sc->nrxchains; i++) { 4422 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4423 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4424 } 4425 4426 if (ht40m) { 4427 /* Is secondary channel below or above primary? */ 4428 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4429 uint32_t reg; 4430 4431 urtwn_write_1(sc, R92C_BWOPMODE, 4432 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4433 4434 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4435 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4436 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4437 4438 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4439 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4440 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4441 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4442 4443 /* Set CCK side band. */ 4444 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4445 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4446 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4447 4448 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4449 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4450 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4451 4452 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4453 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4454 ~R92C_FPGA0_ANAPARAM2_CBW20); 4455 4456 reg = urtwn_bb_read(sc, 0x818); 4457 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4458 urtwn_bb_write(sc, 0x818, reg); 4459 4460 /* Select 40MHz bandwidth. */ 4461 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4462 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4463 } else { 4464 urtwn_write_1(sc, R92C_BWOPMODE, 4465 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4466 4467 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4468 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4469 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4470 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4471 4472 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4473 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4474 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4475 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4476 R92C_FPGA0_ANAPARAM2_CBW20); 4477 } 4478 4479 /* Select 20MHz bandwidth. */ 4480 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4481 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4482 (ISSET(sc->chip, URTWN_CHIP_88E) || 4483 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4484 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4485 } 4486 } 4487 4488 static void __noinline 4489 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4490 { 4491 4492 URTWNHIST_FUNC(); 4493 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4494 4495 uint32_t addaBackup[16], iqkBackup[4], piMode; 4496 4497 #ifdef notyet 4498 uint32_t odfm0_agccore_regs[3]; 4499 uint32_t ant_regs[3]; 4500 uint32_t rf_regs[8]; 4501 #endif 4502 uint32_t reg0, reg1, reg2; 4503 int i, attempt; 4504 4505 #ifdef notyet 4506 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4507 R92E_STBC_SETTING + 2)); 4508 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4509 /* Save AGCCORE regs. */ 4510 for (i = 0; i < sc->nrxchains; i++) { 4511 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4512 R92C_OFDM0_AGCCORE1(i)); 4513 } 4514 #endif 4515 /* Save BB regs. */ 4516 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4517 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4518 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4519 4520 /* Save adda regs to be restored when finished. */ 4521 for (i = 0; i < __arraycount(addaReg); i++) 4522 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4523 /* Save mac regs. */ 4524 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4525 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4526 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4527 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4528 4529 #ifdef notyet 4530 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4531 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4532 4533 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4534 for (i = 0; i < sc->nrxchains; i++) 4535 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4536 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4537 #endif 4538 4539 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4540 R92C_HSSI_PARAM1_PI); 4541 if (piMode == 0) { 4542 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4543 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4544 R92C_HSSI_PARAM1_PI); 4545 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4546 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4547 R92C_HSSI_PARAM1_PI); 4548 } 4549 4550 attempt = 1; 4551 4552 next_attempt: 4553 4554 /* Set mac regs for calibration. */ 4555 for (i = 0; i < __arraycount(addaReg); i++) { 4556 urtwn_bb_write(sc, addaReg[i], 4557 addaReg[__arraycount(addaReg) - 1]); 4558 } 4559 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4560 R92C_CCK0_AFESETTING)); 4561 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4562 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4563 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4564 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4565 4566 if (sc->ntxchains > 1) 4567 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4568 4569 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4570 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4571 ~R92C_BCN_CTRL_EN_BCN)); 4572 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4573 ~R92C_BCN_CTRL_EN_BCN)); 4574 4575 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4576 ~R92C_GPIO_MUXCFG_ENBT)); 4577 4578 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4579 4580 if (sc->ntxchains > 1) 4581 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4582 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4583 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4584 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4585 4586 /* Restore BB regs. */ 4587 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4588 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4589 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4590 4591 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4592 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4593 if (sc->nrxchains > 1) 4594 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4595 4596 if (attempt-- > 0) 4597 goto next_attempt; 4598 4599 /* Restore mode. */ 4600 if (piMode == 0) { 4601 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4602 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4603 ~R92C_HSSI_PARAM1_PI); 4604 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4605 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4606 ~R92C_HSSI_PARAM1_PI); 4607 } 4608 4609 #ifdef notyet 4610 for (i = 0; i < sc->nrxchains; i++) { 4611 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4612 odfm0_agccore_regs[i]); 4613 } 4614 #endif 4615 4616 /* Restore adda regs. */ 4617 for (i = 0; i < __arraycount(addaReg); i++) 4618 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4619 /* Restore mac regs. */ 4620 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4621 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4622 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4623 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4624 4625 #ifdef notyet 4626 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4627 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4628 4629 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4630 for (i = 0; i < sc->nrxchains; i++) 4631 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4632 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4633 #endif 4634 } 4635 4636 static void 4637 urtwn_lc_calib(struct urtwn_softc *sc) 4638 { 4639 uint32_t rf_ac[2]; 4640 uint8_t txmode; 4641 size_t i; 4642 4643 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4644 4645 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4646 4647 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4648 if ((txmode & 0x70) != 0) { 4649 /* Disable all continuous Tx. */ 4650 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4651 4652 /* Set RF mode to standby mode. */ 4653 for (i = 0; i < sc->nrxchains; i++) { 4654 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4655 urtwn_rf_write(sc, i, R92C_RF_AC, 4656 RW(rf_ac[i], R92C_RF_AC_MODE, 4657 R92C_RF_AC_MODE_STANDBY)); 4658 } 4659 } else { 4660 /* Block all Tx queues. */ 4661 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4662 } 4663 /* Start calibration. */ 4664 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4665 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4666 4667 /* Give calibration the time to complete. */ 4668 urtwn_delay_ms(sc, 100); 4669 4670 /* Restore configuration. */ 4671 if ((txmode & 0x70) != 0) { 4672 /* Restore Tx mode. */ 4673 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4674 /* Restore RF mode. */ 4675 for (i = 0; i < sc->nrxchains; i++) { 4676 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4677 } 4678 } else { 4679 /* Unblock all Tx queues. */ 4680 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4681 } 4682 } 4683 4684 static void 4685 urtwn_temp_calib(struct urtwn_softc *sc) 4686 { 4687 int temp, t_meter_reg; 4688 4689 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4690 4691 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4692 4693 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4694 t_meter_reg = R92C_RF_T_METER; 4695 else 4696 t_meter_reg = R92E_RF_T_METER; 4697 4698 if (sc->thcal_state == 0) { 4699 /* Start measuring temperature. */ 4700 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4701 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4702 sc->thcal_state = 1; 4703 return; 4704 } 4705 sc->thcal_state = 0; 4706 4707 /* Read measured temperature. */ 4708 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4709 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4710 if (temp == 0) /* Read failed, skip. */ 4711 return; 4712 4713 /* 4714 * Redo LC calibration if temperature changed significantly since 4715 * last calibration. 4716 */ 4717 if (sc->thcal_lctemp == 0) { 4718 /* First LC calibration is performed in urtwn_init(). */ 4719 sc->thcal_lctemp = temp; 4720 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4721 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4722 sc->thcal_lctemp, temp, 0, 0); 4723 urtwn_lc_calib(sc); 4724 /* Record temperature of last LC calibration. */ 4725 sc->thcal_lctemp = temp; 4726 } 4727 } 4728 4729 static int 4730 urtwn_init(struct ifnet *ifp) 4731 { 4732 struct urtwn_softc *sc = ifp->if_softc; 4733 struct ieee80211com *ic = &sc->sc_ic; 4734 struct urtwn_rx_data *data; 4735 uint32_t reg; 4736 size_t i; 4737 int error; 4738 4739 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4740 4741 urtwn_stop(ifp, 0); 4742 4743 mutex_enter(&sc->sc_write_mtx); 4744 4745 mutex_enter(&sc->sc_task_mtx); 4746 /* Init host async commands ring. */ 4747 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4748 mutex_exit(&sc->sc_task_mtx); 4749 4750 mutex_enter(&sc->sc_fwcmd_mtx); 4751 /* Init firmware commands ring. */ 4752 sc->fwcur = 0; 4753 mutex_exit(&sc->sc_fwcmd_mtx); 4754 4755 /* Allocate Tx/Rx buffers. */ 4756 error = urtwn_alloc_rx_list(sc); 4757 if (error != 0) { 4758 aprint_error_dev(sc->sc_dev, 4759 "could not allocate Rx buffers\n"); 4760 goto fail; 4761 } 4762 error = urtwn_alloc_tx_list(sc); 4763 if (error != 0) { 4764 aprint_error_dev(sc->sc_dev, 4765 "could not allocate Tx buffers\n"); 4766 goto fail; 4767 } 4768 4769 /* Power on adapter. */ 4770 error = urtwn_power_on(sc); 4771 if (error != 0) 4772 goto fail; 4773 4774 /* Initialize DMA. */ 4775 error = urtwn_dma_init(sc); 4776 if (error != 0) 4777 goto fail; 4778 4779 /* Set info size in Rx descriptors (in 64-bit words). */ 4780 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4781 4782 /* Init interrupts. */ 4783 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4784 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4785 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4786 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4787 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4788 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4789 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4790 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4791 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4792 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4793 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4794 } 4795 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4796 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4797 } else { 4798 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4799 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4800 } 4801 4802 /* Set MAC address. */ 4803 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4804 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4805 4806 /* Set initial network type. */ 4807 reg = urtwn_read_4(sc, R92C_CR); 4808 switch (ic->ic_opmode) { 4809 case IEEE80211_M_STA: 4810 default: 4811 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4812 break; 4813 4814 case IEEE80211_M_IBSS: 4815 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4816 break; 4817 } 4818 urtwn_write_4(sc, R92C_CR, reg); 4819 4820 /* Set response rate */ 4821 reg = urtwn_read_4(sc, R92C_RRSR); 4822 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4823 urtwn_write_4(sc, R92C_RRSR, reg); 4824 4825 /* SIFS (used in NAV) */ 4826 urtwn_write_2(sc, R92C_SPEC_SIFS, 4827 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4828 4829 /* Set short/long retry limits. */ 4830 urtwn_write_2(sc, R92C_RL, 4831 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4832 4833 /* Initialize EDCA parameters. */ 4834 urtwn_edca_init(sc); 4835 4836 /* Setup rate fallback. */ 4837 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4838 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4839 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4840 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4841 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4842 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4843 } 4844 4845 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4846 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4847 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4848 /* Set ACK timeout. */ 4849 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4850 4851 /* Setup USB aggregation. */ 4852 /* Tx */ 4853 reg = urtwn_read_4(sc, R92C_TDECTRL); 4854 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4855 urtwn_write_4(sc, R92C_TDECTRL, reg); 4856 /* Rx */ 4857 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4858 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4859 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4860 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4861 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4862 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4863 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4864 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4865 ISSET(sc->chip, URTWN_CHIP_92EU)) 4866 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4867 else 4868 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4869 4870 /* Initialize beacon parameters. */ 4871 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4872 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4873 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4874 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4875 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4876 4877 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4878 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4879 /* Setup AMPDU aggregation. */ 4880 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4881 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4882 urtwn_write_2(sc, 0x4ca, 0x0708); 4883 4884 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4885 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4886 } 4887 4888 /* Load 8051 microcode. */ 4889 error = urtwn_load_firmware(sc); 4890 if (error != 0) 4891 goto fail; 4892 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4893 4894 /* Initialize MAC/BB/RF blocks. */ 4895 /* 4896 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4897 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4898 * XXX: This setting should be removed from rtl8192cu_mac[]. 4899 */ 4900 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4901 urtwn_rxfilter_init(sc); // reset R92C_RCR 4902 urtwn_bb_init(sc); 4903 urtwn_rf_init(sc); 4904 4905 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4906 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4907 urtwn_write_2(sc, R92C_CR, 4908 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4909 R92C_CR_MACRXEN); 4910 } 4911 4912 /* Turn CCK and OFDM blocks on. */ 4913 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4914 reg |= R92C_RFMOD_CCK_EN; 4915 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4916 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4917 reg |= R92C_RFMOD_OFDM_EN; 4918 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4919 4920 /* Clear per-station keys table. */ 4921 urtwn_cam_init(sc); 4922 4923 /* Enable hardware sequence numbering. */ 4924 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4925 4926 /* Perform LO and IQ calibrations. */ 4927 urtwn_iq_calib(sc, sc->iqk_inited); 4928 sc->iqk_inited = true; 4929 4930 /* Perform LC calibration. */ 4931 urtwn_lc_calib(sc); 4932 4933 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4934 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4935 /* Fix USB interference issue. */ 4936 urtwn_write_1(sc, 0xfe40, 0xe0); 4937 urtwn_write_1(sc, 0xfe41, 0x8d); 4938 urtwn_write_1(sc, 0xfe42, 0x80); 4939 urtwn_write_4(sc, 0x20c, 0xfd0320); 4940 4941 urtwn_pa_bias_init(sc); 4942 } 4943 4944 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4945 !(sc->chip & URTWN_CHIP_92EU)) { 4946 /* 1T1R */ 4947 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4948 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4949 } 4950 4951 /* Initialize GPIO setting. */ 4952 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4953 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4954 4955 /* Fix for lower temperature. */ 4956 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4957 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4958 urtwn_write_1(sc, 0x15, 0xe9); 4959 4960 /* Set default channel. */ 4961 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4962 4963 /* Queue Rx xfers. */ 4964 for (size_t j = 0; j < sc->rx_npipe; j++) { 4965 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4966 data = &sc->rx_data[j][i]; 4967 usbd_setup_xfer(data->xfer, data, data->buf, 4968 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4969 urtwn_rxeof); 4970 error = usbd_transfer(data->xfer); 4971 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4972 error != USBD_IN_PROGRESS)) 4973 goto fail; 4974 } 4975 } 4976 4977 /* We're ready to go. */ 4978 ifp->if_flags &= ~IFF_OACTIVE; 4979 ifp->if_flags |= IFF_RUNNING; 4980 sc->sc_running = true; 4981 4982 mutex_exit(&sc->sc_write_mtx); 4983 4984 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4985 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4986 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4987 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4988 urtwn_wait_async(sc); 4989 4990 return 0; 4991 4992 fail: 4993 mutex_exit(&sc->sc_write_mtx); 4994 4995 urtwn_stop(ifp, 1); 4996 return error; 4997 } 4998 4999 static void __noinline 5000 urtwn_stop(struct ifnet *ifp, int disable) 5001 { 5002 struct urtwn_softc *sc = ifp->if_softc; 5003 struct ieee80211com *ic = &sc->sc_ic; 5004 size_t i; 5005 int s; 5006 5007 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5008 5009 s = splusb(); 5010 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5011 urtwn_wait_async(sc); 5012 splx(s); 5013 5014 sc->tx_timer = 0; 5015 ifp->if_timer = 0; 5016 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5017 5018 callout_stop(&sc->sc_scan_to); 5019 callout_stop(&sc->sc_calib_to); 5020 5021 /* Abort Tx. */ 5022 for (i = 0; i < sc->tx_npipe; i++) { 5023 if (sc->tx_pipe[i] != NULL) 5024 usbd_abort_pipe(sc->tx_pipe[i]); 5025 } 5026 5027 /* Stop Rx pipe. */ 5028 for (i = 0; i < sc->rx_npipe; i++) { 5029 if (sc->rx_pipe[i] != NULL) 5030 usbd_abort_pipe(sc->rx_pipe[i]); 5031 } 5032 5033 /* Free Tx/Rx buffers. */ 5034 urtwn_free_tx_list(sc); 5035 urtwn_free_rx_list(sc); 5036 5037 sc->sc_running = false; 5038 if (disable) 5039 urtwn_chip_stop(sc); 5040 } 5041 5042 static int 5043 urtwn_reset(struct ifnet *ifp) 5044 { 5045 struct urtwn_softc *sc = ifp->if_softc; 5046 struct ieee80211com *ic = &sc->sc_ic; 5047 5048 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5049 return ENETRESET; 5050 5051 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5052 5053 return 0; 5054 } 5055 5056 static void 5057 urtwn_chip_stop(struct urtwn_softc *sc) 5058 { 5059 uint32_t reg; 5060 bool disabled = true; 5061 5062 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5063 5064 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5065 ISSET(sc->chip, URTWN_CHIP_92EU)) 5066 return; 5067 5068 mutex_enter(&sc->sc_write_mtx); 5069 5070 /* 5071 * RF Off Sequence 5072 */ 5073 /* Pause MAC TX queue */ 5074 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5075 5076 /* Disable RF */ 5077 urtwn_rf_write(sc, 0, 0, 0); 5078 5079 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5080 5081 /* Reset BB state machine */ 5082 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5083 R92C_SYS_FUNC_EN_USBD | 5084 R92C_SYS_FUNC_EN_USBA | 5085 R92C_SYS_FUNC_EN_BB_GLB_RST); 5086 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5087 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5088 5089 /* 5090 * Reset digital sequence 5091 */ 5092 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5093 /* Reset MCU ready status */ 5094 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5095 /* If firmware in ram code, do reset */ 5096 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5097 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5098 ISSET(sc->chip, URTWN_CHIP_92EU)) 5099 urtwn_r88e_fw_reset(sc); 5100 else 5101 urtwn_fw_reset(sc); 5102 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5103 } 5104 } 5105 5106 /* Reset MAC and Enable 8051 */ 5107 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5108 5109 /* Reset MCU ready status */ 5110 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5111 5112 if (disabled) { 5113 /* Disable MAC clock */ 5114 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5115 /* Disable AFE PLL */ 5116 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5117 /* Gated AFE DIG_CLOCK */ 5118 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5119 /* Isolated digital to PON */ 5120 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5121 } 5122 5123 /* 5124 * Pull GPIO PIN to balance level and LED control 5125 */ 5126 /* 1. Disable GPIO[7:0] */ 5127 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5128 5129 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5130 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5131 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5132 5133 /* Disable GPIO[10:8] */ 5134 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5135 5136 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5137 reg |= (((reg & 0x000f) << 4) | 0x0780); 5138 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5139 5140 /* Disable LED0 & 1 */ 5141 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5142 5143 /* 5144 * Reset digital sequence 5145 */ 5146 if (disabled) { 5147 /* Disable ELDR clock */ 5148 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5149 /* Isolated ELDR to PON */ 5150 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5151 } 5152 5153 /* 5154 * Disable analog sequence 5155 */ 5156 if (disabled) { 5157 /* Disable A15 power */ 5158 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5159 /* Disable digital core power */ 5160 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5161 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5162 ~R92C_LDOV12D_CTRL_LDV12_EN); 5163 } 5164 5165 /* Enter PFM mode */ 5166 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5167 5168 /* Set USB suspend */ 5169 urtwn_write_2(sc, R92C_APS_FSMCO, 5170 R92C_APS_FSMCO_APDM_HOST | 5171 R92C_APS_FSMCO_AFSM_HSUS | 5172 R92C_APS_FSMCO_PFM_ALDN); 5173 5174 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5175 5176 mutex_exit(&sc->sc_write_mtx); 5177 } 5178 5179 static void 5180 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5181 { 5182 if (sc->sc_running == false) 5183 DELAY(ms * 1000); 5184 else 5185 usbd_delay_ms(sc->sc_udev, ms); 5186 } 5187 5188 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5189 5190 #ifdef _MODULE 5191 #include "ioconf.c" 5192 #endif 5193 5194 static int 5195 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5196 { 5197 int error = 0; 5198 5199 switch (cmd) { 5200 case MODULE_CMD_INIT: 5201 #ifdef _MODULE 5202 error = config_init_component(cfdriver_ioconf_urtwn, 5203 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5204 #endif 5205 return error; 5206 case MODULE_CMD_FINI: 5207 #ifdef _MODULE 5208 error = config_fini_component(cfdriver_ioconf_urtwn, 5209 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5210 #endif 5211 return error; 5212 default: 5213 return ENOTTY; 5214 } 5215 } 5216
Indexes created Tue Sep 30 06:09:59 GMT 2025