if_urtwnreg.h revision 1.1.8.1
1 /* $NetBSD: if_urtwnreg.h,v 1.1.8.1 2013/02/25 00:29:36 tls Exp $ */ 2 /* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define R92C_MAX_CHAINS 2 21 22 /* Maximum number of output pipes is 3. */ 23 #define R92C_MAX_EPOUT 3 24 25 #define R92C_MAX_TX_PWR 0x3f 26 27 #define R92C_PUBQ_NPAGES 231 28 #define R92C_TXPKTBUF_COUNT 256 29 #define R92C_TX_PAGE_COUNT 248 30 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 31 32 #define R92C_H2C_NBOX 4 33 34 /* USB Requests. */ 35 #define R92C_REQ_REGS 0x05 36 37 /* 38 * MAC registers. 39 */ 40 /* System Configuration. */ 41 #define R92C_SYS_ISO_CTRL 0x000 42 #define R92C_SYS_FUNC_EN 0x002 43 #define R92C_APS_FSMCO 0x004 44 #define R92C_SYS_CLKR 0x008 45 #define R92C_AFE_MISC 0x010 46 #define R92C_SPS0_CTRL 0x011 47 #define R92C_SPS_OCP_CFG 0x018 48 #define R92C_RSV_CTRL 0x01c 49 #define R92C_RF_CTRL 0x01f 50 #define R92C_LDOA15_CTRL 0x020 51 #define R92C_LDOV12D_CTRL 0x021 52 #define R92C_LDOHCI12_CTRL 0x022 53 #define R92C_LPLDO_CTRL 0x023 54 #define R92C_AFE_XTAL_CTRL 0x024 55 #define R92C_AFE_PLL_CTRL 0x028 56 #define R92C_EFUSE_CTRL 0x030 57 #define R92C_EFUSE_TEST 0x034 58 #define R92C_PWR_DATA 0x038 59 #define R92C_CAL_TIMER 0x03c 60 #define R92C_ACLK_MON 0x03e 61 #define R92C_GPIO_MUXCFG 0x040 62 #define R92C_GPIO_IO_SEL 0x042 63 #define R92C_MAC_PINMUX_CFG 0x043 64 #define R92C_GPIO_PIN_CTRL 0x044 65 #define R92C_GPIO_INTM 0x048 66 #define R92C_LEDCFG0 0x04c 67 #define R92C_LEDCFG1 0x04d 68 #define R92C_LEDCFG2 0x04e 69 #define R92C_LEDCFG3 0x04f 70 #define R92C_FSIMR 0x050 71 #define R92C_FSISR 0x054 72 #define R92C_HSIMR 0x058 73 #define R92C_HSISR 0x05c 74 #define R92C_MCUFWDL 0x080 75 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 76 #define R92C_BIST_SCAN 0x0d0 77 #define R92C_BIST_RPT 0x0d4 78 #define R92C_BIST_ROM_RPT 0x0d8 79 #define R92C_USB_SIE_INTF 0x0e0 80 #define R92C_PCIE_MIO_INTF 0x0e4 81 #define R92C_PCIE_MIO_INTD 0x0e8 82 #define R92C_HPON_FSM 0x0ec 83 #define R92C_SYS_CFG 0x0f0 84 /* MAC General Configuration. */ 85 #define R92C_CR 0x100 86 #define R92C_PBP 0x104 87 #define R92C_TRXDMA_CTRL 0x10c 88 #define R92C_TRXFF_BNDY 0x114 89 #define R92C_TRXFF_STATUS 0x118 90 #define R92C_RXFF_PTR 0x11c 91 #define R92C_HIMR 0x120 92 #define R92C_HISR 0x124 93 #define R92C_HIMRE 0x128 94 #define R92C_HISRE 0x12c 95 #define R92C_CPWM 0x12f 96 #define R92C_FWIMR 0x130 97 #define R92C_FWISR 0x134 98 #define R92C_PKTBUF_DBG_CTRL 0x140 99 #define R92C_PKTBUF_DBG_DATA_L 0x144 100 #define R92C_PKTBUF_DBG_DATA_H 0x148 101 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 102 #define R92C_TCUNIT_BASE 0x164 103 #define R92C_MBIST_START 0x174 104 #define R92C_MBIST_DONE 0x178 105 #define R92C_MBIST_FAIL 0x17c 106 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 107 #define R92C_C2HEVT_MSG_TEST 0x1b8 108 #define R92C_C2HEVT_CLEAR 0x1bf 109 #define R92C_MCUTST_1 0x1c0 110 #define R92C_FMETHR 0x1c8 111 #define R92C_HMETFR 0x1cc 112 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 113 #define R92C_LLT_INIT 0x1e0 114 #define R92C_BB_ACCESS_CTRL 0x1e8 115 #define R92C_BB_ACCESS_DATA 0x1ec 116 /* Tx DMA Configuration. */ 117 #define R92C_RQPN 0x200 118 #define R92C_FIFOPAGE 0x204 119 #define R92C_TDECTRL 0x208 120 #define R92C_TXDMA_OFFSET_CHK 0x20c 121 #define R92C_TXDMA_STATUS 0x210 122 #define R92C_RQPN_NPQ 0x214 123 /* Rx DMA Configuration. */ 124 #define R92C_RXDMA_AGG_PG_TH 0x280 125 #define R92C_RXPKT_NUM 0x284 126 #define R92C_RXDMA_STATUS 0x288 127 /* Protocol Configuration. */ 128 #define R92C_FWHW_TXQ_CTRL 0x420 129 #define R92C_HWSEQ_CTRL 0x423 130 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 131 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 132 #define R92C_SPEC_SIFS 0x428 133 #define R92C_RL 0x42a 134 #define R92C_DARFRC 0x430 135 #define R92C_RARFRC 0x438 136 #define R92C_RRSR 0x440 137 #define R92C_ARFR(i) (0x444 + (i) * 4) 138 #define R92C_AGGLEN_LMT 0x458 139 #define R92C_AMPDU_MIN_SPACE 0x45c 140 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 141 #define R92C_FAST_EDCA_CTRL 0x460 142 #define R92C_RD_RESP_PKT_TH 0x463 143 #define R92C_INIRTS_RATE_SEL 0x480 144 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 145 #define R92C_PROT_MODE_CTRL 0x4c8 146 #define R92C_BAR_MODE_CTRL 0x4cc 147 /* EDCA Configuration. */ 148 #define R92C_EDCA_VO_PARAM 0x500 149 #define R92C_EDCA_VI_PARAM 0x504 150 #define R92C_EDCA_BE_PARAM 0x508 151 #define R92C_EDCA_BK_PARAM 0x50c 152 #define R92C_BCNTCFG 0x510 153 #define R92C_PIFS 0x512 154 #define R92C_RDG_PIFS 0x513 155 #define R92C_SIFS_CCK 0x514 156 #define R92C_SIFS_OFDM 0x516 157 #define R92C_AGGR_BREAK_TIME 0x51a 158 #define R92C_SLOT 0x51b 159 #define R92C_TX_PTCL_CTRL 0x520 160 #define R92C_TXPAUSE 0x522 161 #define R92C_DIS_TXREQ_CLR 0x523 162 #define R92C_RD_CTRL 0x524 163 #define R92C_TBTT_PROHIBIT 0x540 164 #define R92C_RD_NAV_NXT 0x544 165 #define R92C_NAV_PROT_LEN 0x546 166 #define R92C_BCN_CTRL 0x550 167 #define R92C_USTIME_TSF 0x551 168 #define R92C_MBID_NUM 0x552 169 #define R92C_DUAL_TSF_RST 0x553 170 #define R92C_BCN_INTERVAL 0x554 171 #define R92C_DRVERLYINT 0x558 172 #define R92C_BCNDMATIM 0x559 173 #define R92C_ATIMWND 0x55a 174 #define R92C_BCN_MAX_ERR 0x55d 175 #define R92C_RXTSF_OFFSET_CCK 0x55e 176 #define R92C_RXTSF_OFFSET_OFDM 0x55f 177 #define R92C_TSFTR 0x560 178 #define R92C_INIT_TSFTR 0x564 179 #define R92C_PSTIMER 0x580 180 #define R92C_TIMER0 0x584 181 #define R92C_TIMER1 0x588 182 #define R92C_ACMHWCTRL 0x5c0 183 #define R92C_ACMRSTCTRL 0x5c1 184 #define R92C_ACMAVG 0x5c2 185 #define R92C_VO_ADMTIME 0x5c4 186 #define R92C_VI_ADMTIME 0x5c6 187 #define R92C_BE_ADMTIME 0x5c8 188 #define R92C_EDCA_RANDOM_GEN 0x5cc 189 #define R92C_SCH_TXCMD 0x5d0 190 /* WMAC Configuration. */ 191 #define R92C_APSD_CTRL 0x600 192 #define R92C_BWOPMODE 0x603 193 #define R92C_TCR 0x604 194 #define R92C_RCR 0x608 195 #define R92C_RX_PKT_LIMIT 0x60c 196 #define R92C_RX_DLK_TIME 0x60d 197 #define R92C_RX_DRVINFO_SZ 0x60f 198 #define R92C_MACID 0x610 199 #define R92C_BSSID 0x618 200 #define R92C_MAR 0x620 201 #define R92C_MBIDCAMCFG 0x628 202 #define R92C_USTIME_EDCA 0x638 203 #define R92C_MAC_SPEC_SIFS 0x63a 204 #define R92C_R2T_SIFS 0x63c 205 #define R92C_T2T_SIFS 0x63e 206 #define R92C_ACKTO 0x640 207 #define R92C_CTS2TO 0x641 208 #define R92C_EIFS 0x642 209 #define R92C_NAV_CTRL 0x650 210 #define R92C_BACAMCMD 0x654 211 #define R92C_BACAMCONTENT 0x658 212 #define R92C_LBDLY 0x660 213 #define R92C_FWDLY 0x661 214 #define R92C_RXERR_RPT 0x664 215 #define R92C_WMAC_TRXPTCL_CTL 0x668 216 #define R92C_CAMCMD 0x670 217 #define R92C_CAMWRITE 0x674 218 #define R92C_CAMREAD 0x678 219 #define R92C_CAMDBG 0x67c 220 #define R92C_SECCFG 0x680 221 #define R92C_WOW_CTRL 0x690 222 #define R92C_PSSTATUS 0x691 223 #define R92C_PS_RX_INFO 0x692 224 #define R92C_LPNAV_CTRL 0x694 225 #define R92C_WKFMCAM_CMD 0x698 226 #define R92C_WKFMCAM_RWD 0x69c 227 #define R92C_RXFLTMAP0 0x6a0 228 #define R92C_RXFLTMAP1 0x6a2 229 #define R92C_RXFLTMAP2 0x6a4 230 #define R92C_BCN_PSR_RPT 0x6a8 231 #define R92C_CALB32K_CTRL 0x6ac 232 #define R92C_PKT_MON_CTRL 0x6b4 233 #define R92C_BT_COEX_TABLE 0x6c0 234 #define R92C_WMAC_RESP_TXINFO 0x6d8 235 236 /* Bits for R92C_SYS_ISO_CTRL. */ 237 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 238 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 239 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 240 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 241 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 242 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 243 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 244 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 245 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 246 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 247 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 248 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 249 250 /* Bits for R92C_SYS_FUNC_EN. */ 251 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 252 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 253 #define R92C_SYS_FUNC_EN_USBA 0x0004 254 #define R92C_SYS_FUNC_EN_UPLL 0x0008 255 #define R92C_SYS_FUNC_EN_USBD 0x0010 256 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 257 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 258 #define R92C_SYS_FUNC_EN_PPLL 0x0080 259 #define R92C_SYS_FUNC_EN_PCIED 0x0100 260 #define R92C_SYS_FUNC_EN_DIOE 0x0200 261 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 262 #define R92C_SYS_FUNC_EN_DCORE 0x0800 263 #define R92C_SYS_FUNC_EN_ELDR 0x1000 264 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 265 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 266 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 267 268 /* Bits for R92C_APS_FSMCO. */ 269 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 270 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 271 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 272 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 273 #define R92C_APS_FSMCO_PDN_EN 0x00000010 274 #define R92C_APS_FSMCO_PDN_PL 0x00000020 275 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 276 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 277 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 278 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 279 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 280 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 281 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 282 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 283 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 284 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 285 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 286 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 287 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 288 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 289 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 290 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 291 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 292 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 293 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 294 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 295 296 /* Bits for R92C_SYS_CLKR. */ 297 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 298 #define R92C_SYS_CLKR_ANA8M 0x00000002 299 #define R92C_SYS_CLKR_MACSLP 0x00000010 300 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 301 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 302 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 303 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 304 #define R92C_SYS_CLKR_SEC_EN 0x00000400 305 #define R92C_SYS_CLKR_MAC_EN 0x00000800 306 #define R92C_SYS_CLKR_SYS_EN 0x00001000 307 #define R92C_SYS_CLKR_RING_EN 0x00002000 308 309 /* Bits for R92C_RF_CTRL. */ 310 #define R92C_RF_CTRL_EN 0x01 311 #define R92C_RF_CTRL_RSTB 0x02 312 #define R92C_RF_CTRL_SDMRSTB 0x04 313 314 /* Bits for R92C_LDOV12D_CTRL. */ 315 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 316 317 /* Bits for R92C_EFUSE_CTRL. */ 318 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 319 #define R92C_EFUSE_CTRL_DATA_S 0 320 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 321 #define R92C_EFUSE_CTRL_ADDR_S 8 322 #define R92C_EFUSE_CTRL_VALID 0x80000000 323 324 /* Bits for R92C_GPIO_MUXCFG. */ 325 #define R92C_GPIO_MUXCFG_ENBT 0x0020 326 327 /* Bits for R92C_LEDCFG0. */ 328 #define R92C_LEDCFG0_DIS 0x08 329 330 /* Bits for R92C_MCUFWDL. */ 331 #define R92C_MCUFWDL_EN 0x00000001 332 #define R92C_MCUFWDL_RDY 0x00000002 333 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 334 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 335 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 336 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 337 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 338 #define R92C_MCUFWDL_PAGE_M 0x00070000 339 #define R92C_MCUFWDL_PAGE_S 16 340 #define R92C_MCUFWDL_CPRST 0x00800000 341 342 /* Bits for R92C_HPON_FSM. */ 343 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 344 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 345 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 346 347 /* Bits for R92C_SYS_CFG. */ 348 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 349 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 350 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 351 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 352 #define R92C_SYS_CFG_PCIRSTB 0x00000010 353 #define R92C_SYS_CFG_V15_VLD 0x00000020 354 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 355 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 356 #define R92C_SYS_CFG_BD_MAC2 0x00000200 357 #define R92C_SYS_CFG_BD_MAC1 0x00000400 358 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 359 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 360 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 361 #define R92C_SYS_CFG_BT_FUNC 0x00010000 362 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 363 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 364 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 365 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 366 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 367 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 368 #define R92C_SYS_CFG_TYPE_92C 0x08000000 369 370 /* Bits for R92C_CR. */ 371 #define R92C_CR_HCI_TXDMA_EN 0x00000001 372 #define R92C_CR_HCI_RXDMA_EN 0x00000002 373 #define R92C_CR_TXDMA_EN 0x00000004 374 #define R92C_CR_RXDMA_EN 0x00000008 375 #define R92C_CR_PROTOCOL_EN 0x00000010 376 #define R92C_CR_SCHEDULE_EN 0x00000020 377 #define R92C_CR_MACTXEN 0x00000040 378 #define R92C_CR_MACRXEN 0x00000080 379 #define R92C_CR_ENSEC 0x00000200 380 #define R92C_CR_NETTYPE_S 16 381 #define R92C_CR_NETTYPE_M 0x00030000 382 #define R92C_CR_NETTYPE_NOLINK 0 383 #define R92C_CR_NETTYPE_ADHOC 1 384 #define R92C_CR_NETTYPE_INFRA 2 385 #define R92C_CR_NETTYPE_AP 3 386 387 /* Bits for R92C_PBP. */ 388 #define R92C_PBP_PSRX_M 0x0f 389 #define R92C_PBP_PSRX_S 0 390 #define R92C_PBP_PSTX_M 0xf0 391 #define R92C_PBP_PSTX_S 4 392 #define R92C_PBP_64 0 393 #define R92C_PBP_128 1 394 #define R92C_PBP_256 2 395 #define R92C_PBP_512 3 396 #define R92C_PBP_1024 4 397 398 /* Bits for R92C_TRXDMA_CTRL. */ 399 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 400 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 401 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 402 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 403 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 404 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 405 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 406 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 407 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 408 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 409 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 410 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 411 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 412 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 413 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 414 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 415 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 416 /* Shortcuts. */ 417 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 418 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 419 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 420 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 421 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 422 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 423 424 /* Bits for R92C_LLT_INIT. */ 425 #define R92C_LLT_INIT_DATA_M 0x000000ff 426 #define R92C_LLT_INIT_DATA_S 0 427 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 428 #define R92C_LLT_INIT_ADDR_S 8 429 #define R92C_LLT_INIT_OP_M 0xc0000000 430 #define R92C_LLT_INIT_OP_S 30 431 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 432 #define R92C_LLT_INIT_OP_WRITE 1 433 434 /* Bits for R92C_RQPN. */ 435 #define R92C_RQPN_HPQ_M 0x000000ff 436 #define R92C_RQPN_HPQ_S 0 437 #define R92C_RQPN_LPQ_M 0x0000ff00 438 #define R92C_RQPN_LPQ_S 8 439 #define R92C_RQPN_PUBQ_M 0x00ff0000 440 #define R92C_RQPN_PUBQ_S 16 441 #define R92C_RQPN_LD 0x80000000 442 443 /* Bits for R92C_TDECTRL. */ 444 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 445 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 446 447 /* Bits for R92C_FWHW_TXQ_CTRL. */ 448 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 449 450 /* Bits for R92C_SPEC_SIFS. */ 451 #define R92C_SPEC_SIFS_CCK_M 0x00ff 452 #define R92C_SPEC_SIFS_CCK_S 0 453 #define R92C_SPEC_SIFS_OFDM_M 0xff00 454 #define R92C_SPEC_SIFS_OFDM_S 8 455 456 /* Bits for R92C_RL. */ 457 #define R92C_RL_LRL_M 0x003f 458 #define R92C_RL_LRL_S 0 459 #define R92C_RL_SRL_M 0x3f00 460 #define R92C_RL_SRL_S 8 461 462 /* Bits for R92C_RRSR. */ 463 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 464 #define R92C_RRSR_RATE_BITMAP_S 0 465 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 466 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 467 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 468 #define R92C_RRSR_SHORT 0x00800000 469 470 /* Bits for R92C_EDCA_XX_PARAM. */ 471 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 472 #define R92C_EDCA_PARAM_AIFS_S 0 473 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 474 #define R92C_EDCA_PARAM_ECWMIN_S 8 475 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 476 #define R92C_EDCA_PARAM_ECWMAX_S 12 477 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 478 #define R92C_EDCA_PARAM_TXOP_S 16 479 480 /* Bits for R92C_BCN_CTRL. */ 481 #define R92C_BCN_CTRL_EN_MBSSID 0x02 482 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 483 #define R92C_BCN_CTRL_EN_BCN 0x08 484 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 485 486 /* Bits for R92C_APSD_CTRL. */ 487 #define R92C_APSD_CTRL_OFF 0x40 488 #define R92C_APSD_CTRL_OFF_STATUS 0x80 489 490 /* Bits for R92C_BWOPMODE. */ 491 #define R92C_BWOPMODE_11J 0x01 492 #define R92C_BWOPMODE_5G 0x02 493 #define R92C_BWOPMODE_20MHZ 0x04 494 495 /* Bits for R92C_RCR. */ 496 #define R92C_RCR_AAP 0x00000001 // Accept all unicast packet 497 #define R92C_RCR_APM 0x00000002 // Accept physical match packet 498 #define R92C_RCR_AM 0x00000004 // Accept multicast packet 499 #define R92C_RCR_AB 0x00000008 // Accept broadcast packet 500 #define R92C_RCR_ADD3 0x00000010 // Accept address 3 match packet 501 #define R92C_RCR_APWRMGT 0x00000020 // Accept power management packet 502 #define R92C_RCR_CBSSID_DATA 0x00000040 // Accept BSSID match packet (Data) 503 #define R92C_RCR_CBSSID_BCN 0x00000080 // Accept BSSID match packet (Rx beacon, probe rsp) 504 #define R92C_RCR_ACRC32 0x00000100 // Accept CRC32 error packet 505 #define R92C_RCR_AICV 0x00000200 // Accept ICV error packet 506 #define R92C_RCR_ADF 0x00000800 // Accept data type frame 507 #define R92C_RCR_ACF 0x00001000 // Accept control type frame 508 #define R92C_RCR_AMF 0x00002000 // Accept management type frame 509 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 // MFC<--HTC=1 MFC-->HTC=0 510 #define R92C_RCR_MFBEN 0x00400000 511 #define R92C_RCR_LSIGEN 0x00800000 512 #define R92C_RCR_ENMBID 0x01000000 // Enable Multiple BssId. 513 #define R92C_RCR_APP_BA_SSN 0x08000000 // Accept BA SSN 514 #define R92C_RCR_APP_PHYSTS 0x10000000 515 #define R92C_RCR_APP_ICV 0x20000000 516 #define R92C_RCR_APP_MIC 0x40000000 517 #define R92C_RCR_APPFCS 0x80000000 // WMAC append FCS after payload 518 519 /* Bits for R92C_CAMCMD. */ 520 #define R92C_CAMCMD_ADDR_M 0x0000ffff 521 #define R92C_CAMCMD_ADDR_S 0 522 #define R92C_CAMCMD_WRITE 0x00010000 523 #define R92C_CAMCMD_CLR 0x40000000 524 #define R92C_CAMCMD_POLLING 0x80000000 525 526 527 /* 528 * Baseband registers. 529 */ 530 #define R92C_FPGA0_RFMOD 0x800 531 #define R92C_FPGA0_TXINFO 0x804 532 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 533 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 534 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 535 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 536 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 537 #define R92C_FPGA0_XA_HSSIPARAM1 0x820 538 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 539 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 540 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 541 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 542 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 543 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 544 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 545 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 546 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 547 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 548 #define R92C_FPGA0_ANAPARAM2 0x884 549 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 550 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 551 #define R92C_FPGA1_RFMOD 0x900 552 #define R92C_FPGA1_TXINFO 0x90c 553 #define R92C_CCK0_SYSTEM 0xa00 554 #define R92C_CCK0_AFESETTING 0xa04 555 #define R92C_OFDM0_TRXPATHENA 0xc04 556 #define R92C_OFDM0_TRMUXPAR 0xc08 557 #define R92C_OFDM0_XARXIQIMBALANCE 0xc14 558 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 559 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 560 #define R92C_OFDM0_AGCPARAM1 0xc70 561 #define R92C_OFDM0_AGCRSSITABLE 0xc78 562 #define R92C_OFDM0_HTSTFAGC 0xc7c 563 #define R92C_OFDM0_XATXIQIMBALANCE 0xc80 564 #define R92C_OFDM0_XBTXIQIMBALANCE 0xc88 565 #define R92C_OFDM0_XCTXIQIMBALANCE 0xc90 566 #define R92C_OFDM0_XCTXAFE 0xc94 567 #define R92C_OFDM0_XDTXAFE 0xc9c 568 #define R92C_OFDM0_RXIQEXTANTA 0xca0 569 #define R92C_OFDM1_LSTF 0xd00 570 571 /* Bits for R92C_FPGA[01]_RFMOD. */ 572 #define R92C_RFMOD_40MHZ 0x00000001 573 #define R92C_RFMOD_JAPAN 0x00000002 574 #define R92C_RFMOD_CCK_TXSC 0x00000030 575 #define R92C_RFMOD_CCK_EN 0x01000000 576 #define R92C_RFMOD_OFDM_EN 0x02000000 577 578 /* Bits for R92C_HSSI_PARAM1(i). */ 579 #define R92C_HSSI_PARAM1_PI 0x00000100 580 581 /* Bits for R92C_HSSI_PARAM2(i). */ 582 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 583 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 584 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 585 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 586 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 587 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 588 589 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 590 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 591 #define R92C_TXAGC_A_CCK1_S 8 592 593 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 594 #define R92C_TXAGC_B_CCK11_M 0x000000ff 595 #define R92C_TXAGC_B_CCK11_S 0 596 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 597 #define R92C_TXAGC_A_CCK2_S 8 598 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 599 #define R92C_TXAGC_A_CCK55_S 16 600 #define R92C_TXAGC_A_CCK11_M 0xff000000 601 #define R92C_TXAGC_A_CCK11_S 24 602 603 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 604 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 605 #define R92C_TXAGC_B_CCK1_S 8 606 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 607 #define R92C_TXAGC_B_CCK2_S 16 608 #define R92C_TXAGC_B_CCK55_M 0xff000000 609 #define R92C_TXAGC_B_CCK55_S 24 610 611 /* Bits for R92C_TXAGC_RATE18_06(x). */ 612 #define R92C_TXAGC_RATE06_M 0x000000ff 613 #define R92C_TXAGC_RATE06_S 0 614 #define R92C_TXAGC_RATE09_M 0x0000ff00 615 #define R92C_TXAGC_RATE09_S 8 616 #define R92C_TXAGC_RATE12_M 0x00ff0000 617 #define R92C_TXAGC_RATE12_S 16 618 #define R92C_TXAGC_RATE18_M 0xff000000 619 #define R92C_TXAGC_RATE18_S 24 620 621 /* Bits for R92C_TXAGC_RATE54_24(x). */ 622 #define R92C_TXAGC_RATE24_M 0x000000ff 623 #define R92C_TXAGC_RATE24_S 0 624 #define R92C_TXAGC_RATE36_M 0x0000ff00 625 #define R92C_TXAGC_RATE36_S 8 626 #define R92C_TXAGC_RATE48_M 0x00ff0000 627 #define R92C_TXAGC_RATE48_S 16 628 #define R92C_TXAGC_RATE54_M 0xff000000 629 #define R92C_TXAGC_RATE54_S 24 630 631 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 632 #define R92C_TXAGC_MCS00_M 0x000000ff 633 #define R92C_TXAGC_MCS00_S 0 634 #define R92C_TXAGC_MCS01_M 0x0000ff00 635 #define R92C_TXAGC_MCS01_S 8 636 #define R92C_TXAGC_MCS02_M 0x00ff0000 637 #define R92C_TXAGC_MCS02_S 16 638 #define R92C_TXAGC_MCS03_M 0xff000000 639 #define R92C_TXAGC_MCS03_S 24 640 641 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 642 #define R92C_TXAGC_MCS04_M 0x000000ff 643 #define R92C_TXAGC_MCS04_S 0 644 #define R92C_TXAGC_MCS05_M 0x0000ff00 645 #define R92C_TXAGC_MCS05_S 8 646 #define R92C_TXAGC_MCS06_M 0x00ff0000 647 #define R92C_TXAGC_MCS06_S 16 648 #define R92C_TXAGC_MCS07_M 0xff000000 649 #define R92C_TXAGC_MCS07_S 24 650 651 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 652 #define R92C_TXAGC_MCS08_M 0x000000ff 653 #define R92C_TXAGC_MCS08_S 0 654 #define R92C_TXAGC_MCS09_M 0x0000ff00 655 #define R92C_TXAGC_MCS09_S 8 656 #define R92C_TXAGC_MCS10_M 0x00ff0000 657 #define R92C_TXAGC_MCS10_S 16 658 #define R92C_TXAGC_MCS11_M 0xff000000 659 #define R92C_TXAGC_MCS11_S 24 660 661 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 662 #define R92C_TXAGC_MCS12_M 0x000000ff 663 #define R92C_TXAGC_MCS12_S 0 664 #define R92C_TXAGC_MCS13_M 0x0000ff00 665 #define R92C_TXAGC_MCS13_S 8 666 #define R92C_TXAGC_MCS14_M 0x00ff0000 667 #define R92C_TXAGC_MCS14_S 16 668 #define R92C_TXAGC_MCS15_M 0xff000000 669 #define R92C_TXAGC_MCS15_S 24 670 671 /* Bits for R92C_LSSI_PARAM(i). */ 672 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 673 #define R92C_LSSI_PARAM_DATA_S 0 674 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 675 #define R92C_LSSI_PARAM_ADDR_S 20 676 677 /* Bits for R92C_FPGA0_ANAPARAM2. */ 678 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 679 680 /* Bits for R92C_LSSI_READBACK(i). */ 681 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 682 #define R92C_LSSI_READBACK_DATA_S 0 683 684 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 685 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 686 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 687 688 /* 689 * USB registers. 690 */ 691 #define R92C_USB_INFO 0xfe17 692 #define R92C_TEST_USB_TXQS 0xfe48 693 #define R92C_USB_SPECIAL_OPTION 0xfe55 694 #define R92C_USB_HCPWM 0xfe57 695 #define R92C_USB_HRPWM 0xfe58 696 #define R92C_USB_DMA_AGG_TO 0xfe5b 697 #define R92C_USB_AGG_TO 0xfe5c 698 #define R92C_USB_AGG_TH 0xfe5d 699 #define R92C_USB_VID 0xfe60 700 #define R92C_USB_PID 0xfe62 701 #define R92C_USB_OPTIONAL 0xfe64 702 #define R92C_USB_EP 0xfe65 703 #define R92C_USB_PHY 0xfe68 /* XXX: linux-3.7.4(rtlwifi/rtl8192ce/reg.h) has 0xfe66 */ 704 #define R92C_USB_MAC_ADDR 0xfe70 705 #define R92C_USB_STRING 0xfe80 706 707 /* Bits for R92C_USB_SPECIAL_OPTION. */ 708 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 709 710 /* Bits for R92C_USB_EP. */ 711 #define R92C_USB_EP_HQ_M 0x000f 712 #define R92C_USB_EP_HQ_S 0 713 #define R92C_USB_EP_NQ_M 0x00f0 714 #define R92C_USB_EP_NQ_S 4 715 #define R92C_USB_EP_LQ_M 0x0f00 716 #define R92C_USB_EP_LQ_S 8 717 718 /* Bits for R92C_RD_CTRL. */ 719 #define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) 720 721 /* 722 * Firmware base address. 723 */ 724 #define R92C_FW_START_ADDR 0x1000 725 #define R92C_FW_PAGE_SIZE 4096 726 727 728 /* 729 * RF (6052) registers. 730 */ 731 #define R92C_RF_AC 0x00 732 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 733 #define R92C_RF_POW_TRSW 0x05 734 #define R92C_RF_GAIN_RX 0x06 735 #define R92C_RF_GAIN_TX 0x07 736 #define R92C_RF_TXM_IDAC 0x08 737 #define R92C_RF_BS_IQGEN 0x0f 738 #define R92C_RF_MODE1 0x10 739 #define R92C_RF_MODE2 0x11 740 #define R92C_RF_RX_AGC_HP 0x12 741 #define R92C_RF_TX_AGC 0x13 742 #define R92C_RF_BIAS 0x14 743 #define R92C_RF_IPA 0x15 744 #define R92C_RF_POW_ABILITY 0x17 745 #define R92C_RF_CHNLBW 0x18 746 #define R92C_RF_RX_G1 0x1a 747 #define R92C_RF_RX_G2 0x1b 748 #define R92C_RF_RX_BB2 0x1c 749 #define R92C_RF_RX_BB1 0x1d 750 #define R92C_RF_RCK1 0x1e 751 #define R92C_RF_RCK2 0x1f 752 #define R92C_RF_TX_G(i) (0x20 + (i)) 753 #define R92C_RF_TX_BB1 0x23 754 #define R92C_RF_T_METER 0x24 755 #define R92C_RF_SYN_G(i) (0x25 + (i)) 756 #define R92C_RF_RCK_OS 0x30 757 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 758 759 /* Bits for R92C_RF_AC. */ 760 #define R92C_RF_AC_MODE_M 0x70000 761 #define R92C_RF_AC_MODE_S 16 762 #define R92C_RF_AC_MODE_STANDBY 1 763 764 /* Bits for R92C_RF_CHNLBW. */ 765 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 766 #define R92C_RF_CHNLBW_CHNL_S 0 767 #define R92C_RF_CHNLBW_BW20 0x00400 768 #define R92C_RF_CHNLBW_LCSTART 0x08000 769 770 771 /* 772 * CAM entries. 773 */ 774 #define R92C_CAM_ENTRY_COUNT 32 775 776 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 777 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 778 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 779 780 /* Bits for R92C_CAM_CTL0(i). */ 781 #define R92C_CAM_KEYID_M 0x00000003 782 #define R92C_CAM_KEYID_S 0 783 #define R92C_CAM_ALGO_M 0x0000001c 784 #define R92C_CAM_ALGO_S 2 785 #define R92C_CAM_ALGO_NONE 0 786 #define R92C_CAM_ALGO_WEP40 1 787 #define R92C_CAM_ALGO_TKIP 2 788 #define R92C_CAM_ALGO_AES 4 789 #define R92C_CAM_ALGO_WEP104 5 790 #define R92C_CAM_VALID 0x00008000 791 #define R92C_CAM_MACLO_M 0xffff0000 792 #define R92C_CAM_MACLO_S 16 793 794 /* Rate adaptation modes. */ 795 #define R92C_RAID_11GN 1 796 #define R92C_RAID_11N 3 797 #define R92C_RAID_11BG 4 798 #define R92C_RAID_11G 5 /* "pure" 11g */ 799 #define R92C_RAID_11B 6 800 801 802 /* Macros to access unaligned little-endian memory. */ 803 #define LE_READ_2(x) ((x)[0] | ((x)[1]<<8)) 804 #define LE_READ_4(x) ((x)[0] | ((x)[1]<<8) | ((x)[2]<<16) | ((x)[3]<<24)) 805 806 /* 807 * Macros to access subfields in registers. 808 */ 809 /* Mask and Shift (getter). */ 810 #define MS(val, field) \ 811 (((val) & field##_M) >> field##_S) 812 813 /* Shift and Mask (setter). */ 814 #define SM(field, val) \ 815 (((val) << field##_S) & field##_M) 816 817 /* Rewrite. */ 818 #define RW(var, field, val) \ 819 (((var) & ~field##_M) | SM(field, val)) 820 821 /* 822 * Firmware image header. 823 */ 824 struct r92c_fw_hdr { 825 /* QWORD0 */ 826 uint16_t signature; 827 uint8_t category; 828 uint8_t function; 829 uint16_t version; 830 uint16_t subversion; 831 /* QWORD1 */ 832 uint8_t month; 833 uint8_t date; 834 uint8_t hour; 835 uint8_t minute; 836 uint16_t ramcodesize; 837 uint16_t reserved2; 838 /* QWORD2 */ 839 uint32_t svnidx; 840 uint32_t reserved3; 841 /* QWORD3 */ 842 uint32_t reserved4; 843 uint32_t reserved5; 844 } __packed; 845 846 /* 847 * Host to firmware commands. 848 */ 849 struct r92c_fw_cmd { 850 uint8_t id; 851 #define R92C_CMD_AP_OFFLOAD 0 852 #define R92C_CMD_SET_PWRMODE 1 853 #define R92C_CMD_JOINBSS_RPT 2 854 #define R92C_CMD_RSVD_PAGE 3 855 #define R92C_CMD_RSSI 4 856 #define R92C_CMD_RSSI_SETTING 5 857 #define R92C_CMD_MACID_CONFIG 6 858 #define R92C_CMD_MACID_PS_MODE 7 859 #define R92C_CMD_P2P_PS_OFFLOAD 8 860 #define R92C_CMD_SELECTIVE_SUSPEND 9 861 #define R92C_CMD_FLAG_EXT 0x80 862 863 uint8_t msg[5]; 864 } __packed; 865 866 /* Structure for R92C_CMD_RSSI_SETTING. */ 867 struct r92c_fw_cmd_rssi { 868 uint8_t macid; 869 uint8_t reserved; 870 uint8_t pwdb; 871 } __packed; 872 873 /* Structure for R92C_CMD_MACID_CONFIG. */ 874 struct r92c_fw_cmd_macid_cfg { 875 uint8_t mask[4]; 876 uint8_t macid; 877 #define URTWN_MACID_BSS 0 878 #define URTWN_MACID_BC 4 /* Broadcast. */ 879 #define URTWN_MACID_VALID 0x80 880 } __packed; 881 882 /* 883 * RTL8192CU ROM image. 884 */ 885 struct r92c_rom { 886 uint16_t id; /* 0x8192 */ 887 uint8_t reserved1[5]; 888 uint8_t dbg_sel; 889 uint16_t reserved2; 890 uint16_t vid; 891 uint16_t pid; 892 uint8_t usb_opt; 893 uint8_t ep_setting; 894 uint16_t reserved3; 895 uint8_t usb_phy; 896 uint8_t reserved4[3]; 897 uint8_t macaddr[6]; 898 uint8_t string[61]; /* "Realtek" */ 899 uint8_t subcustomer_id; 900 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 901 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 902 uint8_t ht40_2s_tx_pwr_diff[3]; 903 uint8_t ht20_tx_pwr_diff[3]; 904 uint8_t ofdm_tx_pwr_diff[3]; 905 uint8_t ht40_max_pwr[3]; 906 uint8_t ht20_max_pwr[3]; 907 uint8_t xtal_calib; 908 uint8_t tssi[R92C_MAX_CHAINS]; 909 uint8_t thermal_meter; 910 uint8_t rf_opt1; 911 #define R92C_ROM_RF1_REGULATORY_M 0x07 912 #define R92C_ROM_RF1_REGULATORY_S 0 913 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 914 #define R92C_ROM_RF1_BOARD_TYPE_S 5 915 #define R92C_BOARD_TYPE_DONGLE 0 916 #define R92C_BOARD_TYPE_HIGHPA 1 917 #define R92C_BOARD_TYPE_MINICARD 2 918 #define R92C_BOARD_TYPE_SOLO 3 919 #define R92C_BOARD_TYPE_COMBO 4 920 921 uint8_t rf_opt2; 922 uint8_t rf_opt3; 923 uint8_t rf_opt4; 924 uint8_t channel_plan; 925 uint8_t version; 926 uint8_t curstomer_id; 927 } __packed; 928 929 /* Rx MAC descriptor. */ 930 struct r92c_rx_stat { 931 uint32_t rxdw0; 932 #define R92C_RXDW0_PKTLEN_M 0x00003fff 933 #define R92C_RXDW0_PKTLEN_S 0 934 #define R92C_RXDW0_CRCERR 0x00004000 935 #define R92C_RXDW0_ICVERR 0x00008000 936 #define R92C_RXDW0_INFOSZ_M 0x000f0000 937 #define R92C_RXDW0_INFOSZ_S 16 938 #define R92C_RXDW0_QOS 0x00800000 939 #define R92C_RXDW0_SHIFT_M 0x03000000 940 #define R92C_RXDW0_SHIFT_S 24 941 #define R92C_RXDW0_PHYST 0x04000000 942 #define R92C_RXDW0_DECRYPTED 0x08000000 943 944 uint32_t rxdw1; 945 uint32_t rxdw2; 946 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 947 #define R92C_RXDW2_PKTCNT_S 16 948 949 uint32_t rxdw3; 950 #define R92C_RXDW3_RATE_M 0x0000003f 951 #define R92C_RXDW3_RATE_S 0 952 #define R92C_RXDW3_HT 0x00000040 953 #define R92C_RXDW3_HTC 0x00000400 954 955 uint32_t rxdw4; 956 uint32_t rxdw5; 957 } __packed __aligned(4); 958 959 /* Rx PHY descriptor. */ 960 struct r92c_rx_phystat { 961 uint32_t phydw0; 962 uint32_t phydw1; 963 uint32_t phydw2; 964 uint32_t phydw3; 965 uint32_t phydw4; 966 uint32_t phydw5; 967 uint32_t phydw6; 968 uint32_t phydw7; 969 } __packed __aligned(4); 970 971 /* Rx PHY CCK descriptor. */ 972 struct r92c_rx_cck { 973 uint8_t adc_pwdb[4]; 974 uint8_t sq_rpt; 975 uint8_t agc_rpt; 976 } __packed; 977 978 /* Tx MAC descriptor. */ 979 struct r92c_tx_desc { 980 uint32_t txdw0; 981 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 982 #define R92C_TXDW0_PKTLEN_S 0 983 #define R92C_TXDW0_OFFSET_M 0x00ff0000 984 #define R92C_TXDW0_OFFSET_S 16 985 #define R92C_TXDW0_BMCAST 0x01000000 986 #define R92C_TXDW0_LSG 0x04000000 987 #define R92C_TXDW0_FSG 0x08000000 988 #define R92C_TXDW0_OWN 0x80000000 989 990 uint32_t txdw1; 991 #define R92C_TXDW1_MACID_M 0x0000001f 992 #define R92C_TXDW1_MACID_S 0 993 #define R92C_TXDW1_AGGEN 0x00000020 994 #define R92C_TXDW1_AGGBK 0x00000040 995 #define R92C_TXDW1_QSEL_M 0x00001f00 996 #define R92C_TXDW1_QSEL_S 8 997 #define R92C_TXDW1_QSEL_BE 0x00 998 #define R92C_TXDW1_QSEL_MGNT 0x12 999 #define R92C_TXDW1_RAID_M 0x000f0000 1000 #define R92C_TXDW1_RAID_S 16 1001 #define R92C_TXDW1_CIPHER_M 0x00c00000 1002 #define R92C_TXDW1_CIPHER_S 22 1003 #define R92C_TXDW1_CIPHER_NONE 0 1004 #define R92C_TXDW1_CIPHER_RC4 1 1005 #define R92C_TXDW1_CIPHER_AES 3 1006 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1007 #define R92C_TXDW1_PKTOFF_S 26 1008 1009 uint32_t txdw2; 1010 uint16_t txdw3; 1011 uint16_t txdseq; 1012 1013 uint32_t txdw4; 1014 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1015 #define R92C_TXDW4_RTSRATE_S 0 1016 #define R92C_TXDW4_QOS 0x00000040 1017 #define R92C_TXDW4_HWSEQ 0x00000080 1018 #define R92C_TXDW4_DRVRATE 0x00000100 1019 #define R92C_TXDW4_CTS2SELF 0x00000800 1020 #define R92C_TXDW4_RTSEN 0x00001000 1021 #define R92C_TXDW4_HWRTSEN 0x00002000 1022 #define R92C_TXDW4_SCO_M 0x003f0000 1023 #define R92C_TXDW4_SCO_S 20 1024 #define R92C_TXDW4_SCO_SCA 1 1025 #define R92C_TXDW4_SCO_SCB 2 1026 #define R92C_TXDW4_40MHZ 0x02000000 1027 1028 uint32_t txdw5; 1029 #define R92C_TXDW5_DATARATE_M 0x0000003f 1030 #define R92C_TXDW5_DATARATE_S 0 1031 #define R92C_TXDW5_SGI 0x00000040 1032 #define R92C_TXDW5_AGGNUM_M 0xff000000 1033 #define R92C_TXDW5_AGGNUM_S 24 1034 1035 uint32_t txdw6; 1036 uint16_t txdsum; 1037 uint16_t pad; 1038 } __packed __aligned(4); 1039
Indexes created Sun Oct 19 02:09:48 GMT 2025