if_urtwnreg.h revision 1.6
1 /* $NetBSD: if_urtwnreg.h,v 1.6 2014/02/16 16:13:37 christos Exp $ */ 2 /* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define R92C_MAX_CHAINS 2 21 22 /* Maximum number of output pipes is 3. */ 23 #define R92C_MAX_EPOUT 3 24 25 #define R92C_MAX_TX_PWR 0x3f 26 27 #define R92C_PUBQ_NPAGES 231 28 #define R92C_TXPKTBUF_COUNT 256 29 #define R92C_TX_PAGE_COUNT 248 30 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 31 32 #define R92C_H2C_NBOX 4 33 34 /* USB Requests. */ 35 #define R92C_REQ_REGS 0x05 36 37 /* 38 * MAC registers. 39 */ 40 /* System Configuration. */ 41 #define R92C_SYS_ISO_CTRL 0x000 42 #define R92C_SYS_FUNC_EN 0x002 43 #define R92C_APS_FSMCO 0x004 44 #define R92C_SYS_CLKR 0x008 45 #define R92C_AFE_MISC 0x010 46 #define R92C_SPS0_CTRL 0x011 47 #define R92C_SPS_OCP_CFG 0x018 48 #define R92C_RSV_CTRL 0x01c 49 #define R92C_RF_CTRL 0x01f 50 #define R92C_LDOA15_CTRL 0x020 51 #define R92C_LDOV12D_CTRL 0x021 52 #define R92C_LDOHCI12_CTRL 0x022 53 #define R92C_LPLDO_CTRL 0x023 54 #define R92C_AFE_XTAL_CTRL 0x024 55 #define R92C_AFE_PLL_CTRL 0x028 56 #define R92C_EFUSE_CTRL 0x030 57 #define R92C_EFUSE_TEST 0x034 58 #define R92C_PWR_DATA 0x038 59 #define R92C_CAL_TIMER 0x03c 60 #define R92C_ACLK_MON 0x03e 61 #define R92C_GPIO_MUXCFG 0x040 62 #define R92C_GPIO_IO_SEL 0x042 63 #define R92C_MAC_PINMUX_CFG 0x043 64 #define R92C_GPIO_PIN_CTRL 0x044 65 #define R92C_GPIO_INTM 0x048 66 #define R92C_LEDCFG0 0x04c 67 #define R92C_LEDCFG1 0x04d 68 #define R92C_LEDCFG2 0x04e 69 #define R92C_LEDCFG3 0x04f 70 #define R92C_FSIMR 0x050 71 #define R92C_FSISR 0x054 72 #define R92C_HSIMR 0x058 73 #define R92C_HSISR 0x05c 74 #define R92C_MCUFWDL 0x080 75 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 76 #define R92C_BIST_SCAN 0x0d0 77 #define R92C_BIST_RPT 0x0d4 78 #define R92C_BIST_ROM_RPT 0x0d8 79 #define R92C_USB_SIE_INTF 0x0e0 80 #define R92C_PCIE_MIO_INTF 0x0e4 81 #define R92C_PCIE_MIO_INTD 0x0e8 82 #define R92C_HPON_FSM 0x0ec 83 #define R92C_SYS_CFG 0x0f0 84 /* MAC General Configuration. */ 85 #define R92C_CR 0x100 86 #define R92C_MSR 0x102 87 #define R92C_PBP 0x104 88 #define R92C_TRXDMA_CTRL 0x10c 89 #define R92C_TRXFF_BNDY 0x114 90 #define R92C_TRXFF_STATUS 0x118 91 #define R92C_RXFF_PTR 0x11c 92 #define R92C_HIMR 0x120 93 #define R92C_HISR 0x124 94 #define R92C_HIMRE 0x128 95 #define R92C_HISRE 0x12c 96 #define R92C_CPWM 0x12f 97 #define R92C_FWIMR 0x130 98 #define R92C_FWISR 0x134 99 #define R92C_PKTBUF_DBG_CTRL 0x140 100 #define R92C_PKTBUF_DBG_DATA_L 0x144 101 #define R92C_PKTBUF_DBG_DATA_H 0x148 102 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 103 #define R92C_TCUNIT_BASE 0x164 104 #define R92C_MBIST_START 0x174 105 #define R92C_MBIST_DONE 0x178 106 #define R92C_MBIST_FAIL 0x17c 107 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 108 #define R92C_C2HEVT_MSG_TEST 0x1b8 109 #define R92C_C2HEVT_CLEAR 0x1bf 110 #define R92C_MCUTST_1 0x1c0 111 #define R92C_FMETHR 0x1c8 112 #define R92C_HMETFR 0x1cc 113 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 114 #define R92C_LLT_INIT 0x1e0 115 #define R92C_BB_ACCESS_CTRL 0x1e8 116 #define R92C_BB_ACCESS_DATA 0x1ec 117 /* Tx DMA Configuration. */ 118 #define R92C_RQPN 0x200 119 #define R92C_FIFOPAGE 0x204 120 #define R92C_TDECTRL 0x208 121 #define R92C_TXDMA_OFFSET_CHK 0x20c 122 #define R92C_TXDMA_STATUS 0x210 123 #define R92C_RQPN_NPQ 0x214 124 /* Rx DMA Configuration. */ 125 #define R92C_RXDMA_AGG_PG_TH 0x280 126 #define R92C_RXPKT_NUM 0x284 127 #define R92C_RXDMA_STATUS 0x288 128 /* Protocol Configuration. */ 129 #define R92C_FWHW_TXQ_CTRL 0x420 130 #define R92C_HWSEQ_CTRL 0x423 131 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 132 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 133 #define R92C_SPEC_SIFS 0x428 134 #define R92C_RL 0x42a 135 #define R92C_DARFRC 0x430 136 #define R92C_RARFRC 0x438 137 #define R92C_RRSR 0x440 138 #define R92C_ARFR(i) (0x444 + (i) * 4) 139 #define R92C_AGGLEN_LMT 0x458 140 #define R92C_AMPDU_MIN_SPACE 0x45c 141 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 142 #define R92C_FAST_EDCA_CTRL 0x460 143 #define R92C_RD_RESP_PKT_TH 0x463 144 #define R92C_INIRTS_RATE_SEL 0x480 145 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 146 #define R92C_PROT_MODE_CTRL 0x4c8 147 #define R92C_BAR_MODE_CTRL 0x4cc 148 /* EDCA Configuration. */ 149 #define R92C_EDCA_VO_PARAM 0x500 150 #define R92C_EDCA_VI_PARAM 0x504 151 #define R92C_EDCA_BE_PARAM 0x508 152 #define R92C_EDCA_BK_PARAM 0x50c 153 #define R92C_BCNTCFG 0x510 154 #define R92C_PIFS 0x512 155 #define R92C_RDG_PIFS 0x513 156 #define R92C_SIFS_CCK 0x514 157 #define R92C_SIFS_OFDM 0x516 158 #define R92C_AGGR_BREAK_TIME 0x51a 159 #define R92C_SLOT 0x51b 160 #define R92C_TX_PTCL_CTRL 0x520 161 #define R92C_TXPAUSE 0x522 162 #define R92C_DIS_TXREQ_CLR 0x523 163 #define R92C_RD_CTRL 0x524 164 #define R92C_TBTT_PROHIBIT 0x540 165 #define R92C_RD_NAV_NXT 0x544 166 #define R92C_NAV_PROT_LEN 0x546 167 #define R92C_BCN_CTRL 0x550 168 #define R92C_USTIME_TSF 0x551 169 #define R92C_MBID_NUM 0x552 170 #define R92C_DUAL_TSF_RST 0x553 171 #define R92C_BCN_INTERVAL 0x554 172 #define R92C_DRVERLYINT 0x558 173 #define R92C_BCNDMATIM 0x559 174 #define R92C_ATIMWND 0x55a 175 #define R92C_BCN_MAX_ERR 0x55d 176 #define R92C_RXTSF_OFFSET_CCK 0x55e 177 #define R92C_RXTSF_OFFSET_OFDM 0x55f 178 #define R92C_TSFTR 0x560 179 #define R92C_INIT_TSFTR 0x564 180 #define R92C_PSTIMER 0x580 181 #define R92C_TIMER0 0x584 182 #define R92C_TIMER1 0x588 183 #define R92C_ACMHWCTRL 0x5c0 184 #define R92C_ACMRSTCTRL 0x5c1 185 #define R92C_ACMAVG 0x5c2 186 #define R92C_VO_ADMTIME 0x5c4 187 #define R92C_VI_ADMTIME 0x5c6 188 #define R92C_BE_ADMTIME 0x5c8 189 #define R92C_EDCA_RANDOM_GEN 0x5cc 190 #define R92C_SCH_TXCMD 0x5d0 191 /* WMAC Configuration. */ 192 #define R92C_APSD_CTRL 0x600 193 #define R92C_BWOPMODE 0x603 194 #define R92C_TCR 0x604 195 #define R92C_RCR 0x608 196 #define R92C_RX_PKT_LIMIT 0x60c 197 #define R92C_RX_DLK_TIME 0x60d 198 #define R92C_RX_DRVINFO_SZ 0x60f 199 #define R92C_MACID 0x610 200 #define R92C_BSSID 0x618 201 #define R92C_MAR 0x620 202 #define R92C_MBIDCAMCFG 0x628 203 #define R92C_USTIME_EDCA 0x638 204 #define R92C_MAC_SPEC_SIFS 0x63a 205 #define R92C_R2T_SIFS 0x63c 206 #define R92C_T2T_SIFS 0x63e 207 #define R92C_ACKTO 0x640 208 #define R92C_CTS2TO 0x641 209 #define R92C_EIFS 0x642 210 #define R92C_NAV_CTRL 0x650 211 #define R92C_BACAMCMD 0x654 212 #define R92C_BACAMCONTENT 0x658 213 #define R92C_LBDLY 0x660 214 #define R92C_FWDLY 0x661 215 #define R92C_RXERR_RPT 0x664 216 #define R92C_WMAC_TRXPTCL_CTL 0x668 217 #define R92C_CAMCMD 0x670 218 #define R92C_CAMWRITE 0x674 219 #define R92C_CAMREAD 0x678 220 #define R92C_CAMDBG 0x67c 221 #define R92C_SECCFG 0x680 222 #define R92C_WOW_CTRL 0x690 223 #define R92C_PSSTATUS 0x691 224 #define R92C_PS_RX_INFO 0x692 225 #define R92C_LPNAV_CTRL 0x694 226 #define R92C_WKFMCAM_CMD 0x698 227 #define R92C_WKFMCAM_RWD 0x69c 228 #define R92C_RXFLTMAP0 0x6a0 229 #define R92C_RXFLTMAP1 0x6a2 230 #define R92C_RXFLTMAP2 0x6a4 231 #define R92C_BCN_PSR_RPT 0x6a8 232 #define R92C_CALB32K_CTRL 0x6ac 233 #define R92C_PKT_MON_CTRL 0x6b4 234 #define R92C_BT_COEX_TABLE 0x6c0 235 #define R92C_WMAC_RESP_TXINFO 0x6d8 236 237 /* Bits for R92C_SYS_ISO_CTRL. */ 238 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 239 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 240 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 241 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 242 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 243 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 244 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 245 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 246 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 247 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 248 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 249 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 250 251 /* Bits for R92C_SYS_FUNC_EN. */ 252 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 253 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 254 #define R92C_SYS_FUNC_EN_USBA 0x0004 255 #define R92C_SYS_FUNC_EN_UPLL 0x0008 256 #define R92C_SYS_FUNC_EN_USBD 0x0010 257 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 258 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 259 #define R92C_SYS_FUNC_EN_PPLL 0x0080 260 #define R92C_SYS_FUNC_EN_PCIED 0x0100 261 #define R92C_SYS_FUNC_EN_DIOE 0x0200 262 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 263 #define R92C_SYS_FUNC_EN_DCORE 0x0800 264 #define R92C_SYS_FUNC_EN_ELDR 0x1000 265 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 266 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 267 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 268 269 /* Bits for R92C_APS_FSMCO. */ 270 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 271 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 272 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 273 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 274 #define R92C_APS_FSMCO_PDN_EN 0x00000010 275 #define R92C_APS_FSMCO_PDN_PL 0x00000020 276 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 277 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 278 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 279 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 280 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 281 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 282 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 283 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 284 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 285 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 286 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 287 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 288 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 289 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 290 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 291 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 292 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 293 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 294 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 295 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 296 297 /* Bits for R92C_SYS_CLKR. */ 298 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 299 #define R92C_SYS_CLKR_ANA8M 0x00000002 300 #define R92C_SYS_CLKR_MACSLP 0x00000010 301 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 302 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 303 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 304 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 305 #define R92C_SYS_CLKR_SEC_EN 0x00000400 306 #define R92C_SYS_CLKR_MAC_EN 0x00000800 307 #define R92C_SYS_CLKR_SYS_EN 0x00001000 308 #define R92C_SYS_CLKR_RING_EN 0x00002000 309 310 /* Bits for R92C_RF_CTRL. */ 311 #define R92C_RF_CTRL_EN 0x01 312 #define R92C_RF_CTRL_RSTB 0x02 313 #define R92C_RF_CTRL_SDMRSTB 0x04 314 315 /* Bits for R92C_LDOV12D_CTRL. */ 316 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 317 318 /* Bits for R92C_EFUSE_CTRL. */ 319 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 320 #define R92C_EFUSE_CTRL_DATA_S 0 321 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 322 #define R92C_EFUSE_CTRL_ADDR_S 8 323 #define R92C_EFUSE_CTRL_VALID 0x80000000 324 325 /* Bits for R92C_GPIO_MUXCFG. */ 326 #define R92C_GPIO_MUXCFG_ENBT 0x0020 327 328 /* Bits for R92C_LEDCFG0. */ 329 #define R92C_LEDCFG0_DIS 0x08 330 331 /* Bits for R92C_MCUFWDL. */ 332 #define R92C_MCUFWDL_EN 0x00000001 333 #define R92C_MCUFWDL_RDY 0x00000002 334 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 335 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 336 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 337 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 338 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 339 #define R92C_MCUFWDL_PAGE_M 0x00070000 340 #define R92C_MCUFWDL_PAGE_S 16 341 #define R92C_MCUFWDL_CPRST 0x00800000 342 343 /* Bits for R92C_HPON_FSM. */ 344 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 345 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 346 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 347 348 /* Bits for R92C_SYS_CFG. */ 349 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 350 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 351 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 352 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 353 #define R92C_SYS_CFG_PCIRSTB 0x00000010 354 #define R92C_SYS_CFG_V15_VLD 0x00000020 355 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 356 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 357 #define R92C_SYS_CFG_BD_MAC2 0x00000200 358 #define R92C_SYS_CFG_BD_MAC1 0x00000400 359 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 360 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 361 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 362 #define R92C_SYS_CFG_BT_FUNC 0x00010000 363 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 364 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 365 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 366 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 367 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 368 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 369 #define R92C_SYS_CFG_TYPE_92C 0x08000000 370 371 /* Bits for R92C_CR. */ 372 #define R92C_CR_HCI_TXDMA_EN 0x00000001 373 #define R92C_CR_HCI_RXDMA_EN 0x00000002 374 #define R92C_CR_TXDMA_EN 0x00000004 375 #define R92C_CR_RXDMA_EN 0x00000008 376 #define R92C_CR_PROTOCOL_EN 0x00000010 377 #define R92C_CR_SCHEDULE_EN 0x00000020 378 #define R92C_CR_MACTXEN 0x00000040 379 #define R92C_CR_MACRXEN 0x00000080 380 #define R92C_CR_ENSEC 0x00000200 381 #define R92C_CR_NETTYPE_S 16 382 #define R92C_CR_NETTYPE_M 0x00030000 383 #define R92C_CR_NETTYPE_NOLINK 0 384 #define R92C_CR_NETTYPE_ADHOC 1 385 #define R92C_CR_NETTYPE_INFRA 2 386 #define R92C_CR_NETTYPE_AP 3 387 388 /* Bits for R92C_MSR. */ 389 #define R92C_MSR_NOLINK 0x00 390 #define R92C_MSR_ADHOC 0x01 391 #define R92C_MSR_INFRA 0x02 392 #define R92C_MSR_AP 0x03 393 #define R92C_MSR_MASK (~R92C_MSR_AP) 394 395 /* Bits for R92C_PBP. */ 396 #define R92C_PBP_PSRX_M 0x0f 397 #define R92C_PBP_PSRX_S 0 398 #define R92C_PBP_PSTX_M 0xf0 399 #define R92C_PBP_PSTX_S 4 400 #define R92C_PBP_64 0 401 #define R92C_PBP_128 1 402 #define R92C_PBP_256 2 403 #define R92C_PBP_512 3 404 #define R92C_PBP_1024 4 405 406 /* Bits for R92C_TRXDMA_CTRL. */ 407 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 408 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 409 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 410 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 411 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 412 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 413 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 414 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 415 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 416 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 417 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 418 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 419 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 420 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 421 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 422 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 423 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 424 /* Shortcuts. */ 425 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 426 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 427 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 428 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 429 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 430 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 431 432 /* Bits for R92C_LLT_INIT. */ 433 #define R92C_LLT_INIT_DATA_M 0x000000ff 434 #define R92C_LLT_INIT_DATA_S 0 435 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 436 #define R92C_LLT_INIT_ADDR_S 8 437 #define R92C_LLT_INIT_OP_M 0xc0000000 438 #define R92C_LLT_INIT_OP_S 30 439 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 440 #define R92C_LLT_INIT_OP_WRITE 1 441 442 /* Bits for R92C_RQPN. */ 443 #define R92C_RQPN_HPQ_M 0x000000ff 444 #define R92C_RQPN_HPQ_S 0 445 #define R92C_RQPN_LPQ_M 0x0000ff00 446 #define R92C_RQPN_LPQ_S 8 447 #define R92C_RQPN_PUBQ_M 0x00ff0000 448 #define R92C_RQPN_PUBQ_S 16 449 #define R92C_RQPN_LD 0x80000000 450 451 /* Bits for R92C_TDECTRL. */ 452 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 453 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 454 455 /* Bits for R92C_FWHW_TXQ_CTRL. */ 456 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 457 458 /* Bits for R92C_SPEC_SIFS. */ 459 #define R92C_SPEC_SIFS_CCK_M 0x00ff 460 #define R92C_SPEC_SIFS_CCK_S 0 461 #define R92C_SPEC_SIFS_OFDM_M 0xff00 462 #define R92C_SPEC_SIFS_OFDM_S 8 463 464 /* Bits for R92C_RL. */ 465 #define R92C_RL_LRL_M 0x003f 466 #define R92C_RL_LRL_S 0 467 #define R92C_RL_SRL_M 0x3f00 468 #define R92C_RL_SRL_S 8 469 470 /* Bits for R92C_RRSR. */ 471 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 472 #define R92C_RRSR_RATE_BITMAP_S 0 473 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 474 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 475 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 476 #define R92C_RRSR_SHORT 0x00800000 477 478 /* Bits for R92C_EDCA_XX_PARAM. */ 479 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 480 #define R92C_EDCA_PARAM_AIFS_S 0 481 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 482 #define R92C_EDCA_PARAM_ECWMIN_S 8 483 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 484 #define R92C_EDCA_PARAM_ECWMAX_S 12 485 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 486 #define R92C_EDCA_PARAM_TXOP_S 16 487 488 /* Bits for R92C_BCN_CTRL. */ 489 #define R92C_BCN_CTRL_EN_MBSSID 0x02 490 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 491 #define R92C_BCN_CTRL_EN_BCN 0x08 492 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 493 494 /* Bits for R92C_DRVERLYINT */ 495 #define R92C_DRIVER_EARLY_INT_TIME 0x05 496 497 /* Bits for R92C_BCNDMATIM */ 498 #define R92C_DMA_ATIME_INT_TIME 0x02 499 500 /* Bits for R92C_APSD_CTRL. */ 501 #define R92C_APSD_CTRL_OFF 0x40 502 #define R92C_APSD_CTRL_OFF_STATUS 0x80 503 504 /* Bits for R92C_BWOPMODE. */ 505 #define R92C_BWOPMODE_11J 0x01 506 #define R92C_BWOPMODE_5G 0x02 507 #define R92C_BWOPMODE_20MHZ 0x04 508 509 /* Bits for R92C_RCR. */ 510 #define R92C_RCR_AAP 0x00000001 // Accept all unicast packet 511 #define R92C_RCR_APM 0x00000002 // Accept physical match packet 512 #define R92C_RCR_AM 0x00000004 // Accept multicast packet 513 #define R92C_RCR_AB 0x00000008 // Accept broadcast packet 514 #define R92C_RCR_ADD3 0x00000010 // Accept address 3 match packet 515 #define R92C_RCR_APWRMGT 0x00000020 // Accept power management packet 516 #define R92C_RCR_CBSSID_DATA 0x00000040 // Accept BSSID match packet (Data) 517 #define R92C_RCR_CBSSID_BCN 0x00000080 // Accept BSSID match packet (Rx beacon, probe rsp) 518 #define R92C_RCR_ACRC32 0x00000100 // Accept CRC32 error packet 519 #define R92C_RCR_AICV 0x00000200 // Accept ICV error packet 520 #define R92C_RCR_ADF 0x00000800 // Accept data type frame 521 #define R92C_RCR_ACF 0x00001000 // Accept control type frame 522 #define R92C_RCR_AMF 0x00002000 // Accept management type frame 523 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 // MFC<--HTC=1 MFC-->HTC=0 524 #define R92C_RCR_MFBEN 0x00400000 525 #define R92C_RCR_LSIGEN 0x00800000 526 #define R92C_RCR_ENMBID 0x01000000 // Enable Multiple BssId. 527 #define R92C_RCR_APP_BA_SSN 0x08000000 // Accept BA SSN 528 #define R92C_RCR_APP_PHYSTS 0x10000000 529 #define R92C_RCR_APP_ICV 0x20000000 530 #define R92C_RCR_APP_MIC 0x40000000 531 #define R92C_RCR_APPFCS 0x80000000 // WMAC append FCS after payload 532 533 /* Bits for R92C_CAMCMD. */ 534 #define R92C_CAMCMD_ADDR_M 0x0000ffff 535 #define R92C_CAMCMD_ADDR_S 0 536 #define R92C_CAMCMD_WRITE 0x00010000 537 #define R92C_CAMCMD_CLR 0x40000000 538 #define R92C_CAMCMD_POLLING 0x80000000 539 540 541 /* 542 * Baseband registers. 543 */ 544 #define R92C_FPGA0_RFMOD 0x800 545 #define R92C_FPGA0_TXINFO 0x804 546 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 547 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 548 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 549 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 550 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 551 #define R92C_FPGA0_XA_HSSIPARAM1 0x820 552 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 553 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 554 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 555 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 556 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 557 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 558 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 559 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 560 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 561 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 562 #define R92C_FPGA0_ANAPARAM2 0x884 563 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 564 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 565 #define R92C_FPGA1_RFMOD 0x900 566 #define R92C_FPGA1_TXINFO 0x90c 567 #define R92C_CCK0_SYSTEM 0xa00 568 #define R92C_CCK0_AFESETTING 0xa04 569 #define R92C_OFDM0_TRXPATHENA 0xc04 570 #define R92C_OFDM0_TRMUXPAR 0xc08 571 #define R92C_OFDM0_XARXIQIMBALANCE 0xc14 572 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 573 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 574 #define R92C_OFDM0_AGCPARAM1 0xc70 575 #define R92C_OFDM0_AGCRSSITABLE 0xc78 576 #define R92C_OFDM0_HTSTFAGC 0xc7c 577 #define R92C_OFDM0_XATXIQIMBALANCE 0xc80 578 #define R92C_OFDM0_XBTXIQIMBALANCE 0xc88 579 #define R92C_OFDM0_XCTXIQIMBALANCE 0xc90 580 #define R92C_OFDM0_XCTXAFE 0xc94 581 #define R92C_OFDM0_XDTXAFE 0xc9c 582 #define R92C_OFDM0_RXIQEXTANTA 0xca0 583 #define R92C_OFDM1_LSTF 0xd00 584 585 /* Bits for R92C_FPGA[01]_RFMOD. */ 586 #define R92C_RFMOD_40MHZ 0x00000001 587 #define R92C_RFMOD_JAPAN 0x00000002 588 #define R92C_RFMOD_CCK_TXSC 0x00000030 589 #define R92C_RFMOD_CCK_EN 0x01000000 590 #define R92C_RFMOD_OFDM_EN 0x02000000 591 592 /* Bits for R92C_HSSI_PARAM1(i). */ 593 #define R92C_HSSI_PARAM1_PI 0x00000100 594 595 /* Bits for R92C_HSSI_PARAM2(i). */ 596 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 597 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 598 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 599 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 600 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 601 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 602 603 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 604 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 605 #define R92C_TXAGC_A_CCK1_S 8 606 607 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 608 #define R92C_TXAGC_B_CCK11_M 0x000000ff 609 #define R92C_TXAGC_B_CCK11_S 0 610 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 611 #define R92C_TXAGC_A_CCK2_S 8 612 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 613 #define R92C_TXAGC_A_CCK55_S 16 614 #define R92C_TXAGC_A_CCK11_M 0xff000000 615 #define R92C_TXAGC_A_CCK11_S 24 616 617 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 618 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 619 #define R92C_TXAGC_B_CCK1_S 8 620 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 621 #define R92C_TXAGC_B_CCK2_S 16 622 #define R92C_TXAGC_B_CCK55_M 0xff000000 623 #define R92C_TXAGC_B_CCK55_S 24 624 625 /* Bits for R92C_TXAGC_RATE18_06(x). */ 626 #define R92C_TXAGC_RATE06_M 0x000000ff 627 #define R92C_TXAGC_RATE06_S 0 628 #define R92C_TXAGC_RATE09_M 0x0000ff00 629 #define R92C_TXAGC_RATE09_S 8 630 #define R92C_TXAGC_RATE12_M 0x00ff0000 631 #define R92C_TXAGC_RATE12_S 16 632 #define R92C_TXAGC_RATE18_M 0xff000000 633 #define R92C_TXAGC_RATE18_S 24 634 635 /* Bits for R92C_TXAGC_RATE54_24(x). */ 636 #define R92C_TXAGC_RATE24_M 0x000000ff 637 #define R92C_TXAGC_RATE24_S 0 638 #define R92C_TXAGC_RATE36_M 0x0000ff00 639 #define R92C_TXAGC_RATE36_S 8 640 #define R92C_TXAGC_RATE48_M 0x00ff0000 641 #define R92C_TXAGC_RATE48_S 16 642 #define R92C_TXAGC_RATE54_M 0xff000000 643 #define R92C_TXAGC_RATE54_S 24 644 645 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 646 #define R92C_TXAGC_MCS00_M 0x000000ff 647 #define R92C_TXAGC_MCS00_S 0 648 #define R92C_TXAGC_MCS01_M 0x0000ff00 649 #define R92C_TXAGC_MCS01_S 8 650 #define R92C_TXAGC_MCS02_M 0x00ff0000 651 #define R92C_TXAGC_MCS02_S 16 652 #define R92C_TXAGC_MCS03_M 0xff000000 653 #define R92C_TXAGC_MCS03_S 24 654 655 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 656 #define R92C_TXAGC_MCS04_M 0x000000ff 657 #define R92C_TXAGC_MCS04_S 0 658 #define R92C_TXAGC_MCS05_M 0x0000ff00 659 #define R92C_TXAGC_MCS05_S 8 660 #define R92C_TXAGC_MCS06_M 0x00ff0000 661 #define R92C_TXAGC_MCS06_S 16 662 #define R92C_TXAGC_MCS07_M 0xff000000 663 #define R92C_TXAGC_MCS07_S 24 664 665 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 666 #define R92C_TXAGC_MCS08_M 0x000000ff 667 #define R92C_TXAGC_MCS08_S 0 668 #define R92C_TXAGC_MCS09_M 0x0000ff00 669 #define R92C_TXAGC_MCS09_S 8 670 #define R92C_TXAGC_MCS10_M 0x00ff0000 671 #define R92C_TXAGC_MCS10_S 16 672 #define R92C_TXAGC_MCS11_M 0xff000000 673 #define R92C_TXAGC_MCS11_S 24 674 675 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 676 #define R92C_TXAGC_MCS12_M 0x000000ff 677 #define R92C_TXAGC_MCS12_S 0 678 #define R92C_TXAGC_MCS13_M 0x0000ff00 679 #define R92C_TXAGC_MCS13_S 8 680 #define R92C_TXAGC_MCS14_M 0x00ff0000 681 #define R92C_TXAGC_MCS14_S 16 682 #define R92C_TXAGC_MCS15_M 0xff000000 683 #define R92C_TXAGC_MCS15_S 24 684 685 /* Bits for R92C_LSSI_PARAM(i). */ 686 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 687 #define R92C_LSSI_PARAM_DATA_S 0 688 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 689 #define R92C_LSSI_PARAM_ADDR_S 20 690 691 /* Bits for R92C_FPGA0_ANAPARAM2. */ 692 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 693 694 /* Bits for R92C_LSSI_READBACK(i). */ 695 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 696 #define R92C_LSSI_READBACK_DATA_S 0 697 698 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 699 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 700 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 701 702 /* 703 * USB registers. 704 */ 705 #define R92C_USB_INFO 0xfe17 706 #define R92C_TEST_USB_TXQS 0xfe48 707 #define R92C_USB_SPECIAL_OPTION 0xfe55 708 #define R92C_USB_HCPWM 0xfe57 709 #define R92C_USB_HRPWM 0xfe58 710 #define R92C_USB_DMA_AGG_TO 0xfe5b 711 #define R92C_USB_AGG_TO 0xfe5c 712 #define R92C_USB_AGG_TH 0xfe5d 713 #define R92C_USB_VID 0xfe60 714 #define R92C_USB_PID 0xfe62 715 #define R92C_USB_OPTIONAL 0xfe64 716 #define R92C_USB_EP 0xfe65 717 #define R92C_USB_PHY 0xfe68 /* XXX: linux-3.7.4(rtlwifi/rtl8192ce/reg.h) has 0xfe66 */ 718 #define R92C_USB_MAC_ADDR 0xfe70 719 #define R92C_USB_STRING 0xfe80 720 721 /* Bits for R92C_USB_SPECIAL_OPTION. */ 722 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 723 724 /* Bits for R92C_USB_EP. */ 725 #define R92C_USB_EP_HQ_M 0x000f 726 #define R92C_USB_EP_HQ_S 0 727 #define R92C_USB_EP_NQ_M 0x00f0 728 #define R92C_USB_EP_NQ_S 4 729 #define R92C_USB_EP_LQ_M 0x0f00 730 #define R92C_USB_EP_LQ_S 8 731 732 /* Bits for R92C_RD_CTRL. */ 733 #define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) 734 735 /* 736 * Firmware base address. 737 */ 738 #define R92C_FW_START_ADDR 0x1000 739 #define R92C_FW_PAGE_SIZE 4096 740 741 742 /* 743 * RF (6052) registers. 744 */ 745 #define R92C_RF_AC 0x00 746 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 747 #define R92C_RF_POW_TRSW 0x05 748 #define R92C_RF_GAIN_RX 0x06 749 #define R92C_RF_GAIN_TX 0x07 750 #define R92C_RF_TXM_IDAC 0x08 751 #define R92C_RF_BS_IQGEN 0x0f 752 #define R92C_RF_MODE1 0x10 753 #define R92C_RF_MODE2 0x11 754 #define R92C_RF_RX_AGC_HP 0x12 755 #define R92C_RF_TX_AGC 0x13 756 #define R92C_RF_BIAS 0x14 757 #define R92C_RF_IPA 0x15 758 #define R92C_RF_POW_ABILITY 0x17 759 #define R92C_RF_CHNLBW 0x18 760 #define R92C_RF_RX_G1 0x1a 761 #define R92C_RF_RX_G2 0x1b 762 #define R92C_RF_RX_BB2 0x1c 763 #define R92C_RF_RX_BB1 0x1d 764 #define R92C_RF_RCK1 0x1e 765 #define R92C_RF_RCK2 0x1f 766 #define R92C_RF_TX_G(i) (0x20 + (i)) 767 #define R92C_RF_TX_BB1 0x23 768 #define R92C_RF_T_METER 0x24 769 #define R92C_RF_SYN_G(i) (0x25 + (i)) 770 #define R92C_RF_RCK_OS 0x30 771 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 772 773 /* Bits for R92C_RF_AC. */ 774 #define R92C_RF_AC_MODE_M 0x70000 775 #define R92C_RF_AC_MODE_S 16 776 #define R92C_RF_AC_MODE_STANDBY 1 777 778 /* Bits for R92C_RF_CHNLBW. */ 779 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 780 #define R92C_RF_CHNLBW_CHNL_S 0 781 #define R92C_RF_CHNLBW_BW20 0x00400 782 #define R92C_RF_CHNLBW_LCSTART 0x08000 783 784 785 /* 786 * CAM entries. 787 */ 788 #define R92C_CAM_ENTRY_COUNT 32 789 790 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 791 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 792 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 793 794 /* Bits for R92C_CAM_CTL0(i). */ 795 #define R92C_CAM_KEYID_M 0x00000003 796 #define R92C_CAM_KEYID_S 0 797 #define R92C_CAM_ALGO_M 0x0000001c 798 #define R92C_CAM_ALGO_S 2 799 #define R92C_CAM_ALGO_NONE 0 800 #define R92C_CAM_ALGO_WEP40 1 801 #define R92C_CAM_ALGO_TKIP 2 802 #define R92C_CAM_ALGO_AES 4 803 #define R92C_CAM_ALGO_WEP104 5 804 #define R92C_CAM_VALID 0x00008000 805 #define R92C_CAM_MACLO_M 0xffff0000 806 #define R92C_CAM_MACLO_S 16 807 808 /* Rate adaptation modes. */ 809 #define R92C_RAID_11GN 1 810 #define R92C_RAID_11N 3 811 #define R92C_RAID_11BG 4 812 #define R92C_RAID_11G 5 /* "pure" 11g */ 813 #define R92C_RAID_11B 6 814 815 816 /* Macros to access unaligned little-endian memory. */ 817 #define LE_READ_2(x) ((x)[0] | ((x)[1]<<8)) 818 #define LE_READ_4(x) ((x)[0] | ((x)[1]<<8) | ((x)[2]<<16) | ((x)[3]<<24)) 819 820 /* 821 * Macros to access subfields in registers. 822 */ 823 /* Mask and Shift (getter). */ 824 #define MS(val, field) \ 825 (((val) & field##_M) >> field##_S) 826 827 /* Shift and Mask (setter). */ 828 #define SM(field, val) \ 829 (((val) << field##_S) & field##_M) 830 831 /* Rewrite. */ 832 #define RW(var, field, val) \ 833 (((var) & ~field##_M) | SM(field, val)) 834 835 /* 836 * Firmware image header. 837 */ 838 struct r92c_fw_hdr { 839 /* QWORD0 */ 840 uint16_t signature; 841 uint8_t category; 842 uint8_t function; 843 uint16_t version; 844 uint16_t subversion; 845 /* QWORD1 */ 846 uint8_t month; 847 uint8_t date; 848 uint8_t hour; 849 uint8_t minute; 850 uint16_t ramcodesize; 851 uint16_t reserved2; 852 /* QWORD2 */ 853 uint32_t svnidx; 854 uint32_t reserved3; 855 /* QWORD3 */ 856 uint32_t reserved4; 857 uint32_t reserved5; 858 } __packed; 859 860 /* 861 * Host to firmware commands. 862 */ 863 struct r92c_fw_cmd { 864 uint8_t id; 865 #define R92C_CMD_AP_OFFLOAD 0 866 #define R92C_CMD_SET_PWRMODE 1 867 #define R92C_CMD_JOINBSS_RPT 2 868 #define R92C_CMD_RSVD_PAGE 3 869 #define R92C_CMD_RSSI 4 870 #define R92C_CMD_RSSI_SETTING 5 871 #define R92C_CMD_MACID_CONFIG 6 872 #define R92C_CMD_MACID_PS_MODE 7 873 #define R92C_CMD_P2P_PS_OFFLOAD 8 874 #define R92C_CMD_SELECTIVE_SUSPEND 9 875 #define R92C_CMD_FLAG_EXT 0x80 876 877 uint8_t msg[5]; 878 } __packed; 879 880 /* Structure for R92C_CMD_RSSI_SETTING. */ 881 struct r92c_fw_cmd_rssi { 882 uint8_t macid; 883 uint8_t reserved; 884 uint8_t pwdb; 885 } __packed; 886 887 /* Structure for R92C_CMD_MACID_CONFIG. */ 888 struct r92c_fw_cmd_macid_cfg { 889 uint8_t mask[4]; 890 uint8_t macid; 891 #define URTWN_MACID_BSS 0 892 #define URTWN_MACID_BC 4 /* Broadcast. */ 893 #define URTWN_MACID_VALID 0x80 894 } __packed; 895 896 /* 897 * RTL8192CU ROM image. 898 */ 899 struct r92c_rom { 900 uint16_t id; /* 0x8192 */ 901 uint8_t reserved1[5]; 902 uint8_t dbg_sel; 903 uint16_t reserved2; 904 uint16_t vid; 905 uint16_t pid; 906 uint8_t usb_opt; 907 uint8_t ep_setting; 908 uint16_t reserved3; 909 uint8_t usb_phy; 910 uint8_t reserved4[3]; 911 uint8_t macaddr[6]; 912 uint8_t string[61]; /* "Realtek" */ 913 uint8_t subcustomer_id; 914 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 915 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 916 uint8_t ht40_2s_tx_pwr_diff[3]; 917 uint8_t ht20_tx_pwr_diff[3]; 918 uint8_t ofdm_tx_pwr_diff[3]; 919 uint8_t ht40_max_pwr[3]; 920 uint8_t ht20_max_pwr[3]; 921 uint8_t xtal_calib; 922 uint8_t tssi[R92C_MAX_CHAINS]; 923 uint8_t thermal_meter; 924 uint8_t rf_opt1; 925 #define R92C_ROM_RF1_REGULATORY_M 0x07 926 #define R92C_ROM_RF1_REGULATORY_S 0 927 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 928 #define R92C_ROM_RF1_BOARD_TYPE_S 5 929 #define R92C_BOARD_TYPE_DONGLE 0 930 #define R92C_BOARD_TYPE_HIGHPA 1 931 #define R92C_BOARD_TYPE_MINICARD 2 932 #define R92C_BOARD_TYPE_SOLO 3 933 #define R92C_BOARD_TYPE_COMBO 4 934 935 uint8_t rf_opt2; 936 uint8_t rf_opt3; 937 uint8_t rf_opt4; 938 uint8_t channel_plan; 939 uint8_t version; 940 uint8_t curstomer_id; 941 } __packed; 942 943 /* Rx MAC descriptor. */ 944 struct r92c_rx_stat { 945 uint32_t rxdw0; 946 #define R92C_RXDW0_PKTLEN_M 0x00003fff 947 #define R92C_RXDW0_PKTLEN_S 0 948 #define R92C_RXDW0_CRCERR 0x00004000 949 #define R92C_RXDW0_ICVERR 0x00008000 950 #define R92C_RXDW0_INFOSZ_M 0x000f0000 951 #define R92C_RXDW0_INFOSZ_S 16 952 #define R92C_RXDW0_QOS 0x00800000 953 #define R92C_RXDW0_SHIFT_M 0x03000000 954 #define R92C_RXDW0_SHIFT_S 24 955 #define R92C_RXDW0_PHYST 0x04000000 956 #define R92C_RXDW0_DECRYPTED 0x08000000 957 958 uint32_t rxdw1; 959 uint32_t rxdw2; 960 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 961 #define R92C_RXDW2_PKTCNT_S 16 962 963 uint32_t rxdw3; 964 #define R92C_RXDW3_RATE_M 0x0000003f 965 #define R92C_RXDW3_RATE_S 0 966 #define R92C_RXDW3_HT 0x00000040 967 #define R92C_RXDW3_HTC 0x00000400 968 969 uint32_t rxdw4; 970 uint32_t rxdw5; 971 } __packed __aligned(4); 972 973 /* Rx PHY descriptor. */ 974 struct r92c_rx_phystat { 975 uint32_t phydw0; 976 uint32_t phydw1; 977 uint32_t phydw2; 978 uint32_t phydw3; 979 uint32_t phydw4; 980 uint32_t phydw5; 981 uint32_t phydw6; 982 uint32_t phydw7; 983 } __packed __aligned(4); 984 985 /* Rx PHY CCK descriptor. */ 986 struct r92c_rx_cck { 987 uint8_t adc_pwdb[4]; 988 uint8_t sq_rpt; 989 uint8_t agc_rpt; 990 } __packed; 991 992 /* Tx MAC descriptor. */ 993 struct r92c_tx_desc { 994 uint32_t txdw0; 995 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 996 #define R92C_TXDW0_PKTLEN_S 0 997 #define R92C_TXDW0_OFFSET_M 0x00ff0000 998 #define R92C_TXDW0_OFFSET_S 16 999 #define R92C_TXDW0_BMCAST 0x01000000 1000 #define R92C_TXDW0_LSG 0x04000000 1001 #define R92C_TXDW0_FSG 0x08000000 1002 #define R92C_TXDW0_OWN 0x80000000 1003 1004 uint32_t txdw1; 1005 #define R92C_TXDW1_MACID_M 0x0000001f 1006 #define R92C_TXDW1_MACID_S 0 1007 #define R92C_TXDW1_AGGEN 0x00000020 1008 #define R92C_TXDW1_AGGBK 0x00000040 1009 #define R92C_TXDW1_QSEL_M 0x00001f00 1010 #define R92C_TXDW1_QSEL_S 8 1011 #define R92C_TXDW1_QSEL_BE 0x00 1012 #define R92C_TXDW1_QSEL_MGNT 0x12 1013 #define R92C_TXDW1_RAID_M 0x000f0000 1014 #define R92C_TXDW1_RAID_S 16 1015 #define R92C_TXDW1_CIPHER_M 0x00c00000 1016 #define R92C_TXDW1_CIPHER_S 22 1017 #define R92C_TXDW1_CIPHER_NONE 0 1018 #define R92C_TXDW1_CIPHER_RC4 1 1019 #define R92C_TXDW1_CIPHER_AES 3 1020 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1021 #define R92C_TXDW1_PKTOFF_S 26 1022 1023 uint32_t txdw2; 1024 uint16_t txdw3; 1025 uint16_t txdseq; 1026 1027 uint32_t txdw4; 1028 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1029 #define R92C_TXDW4_RTSRATE_S 0 1030 #define R92C_TXDW4_QOS 0x00000040 1031 #define R92C_TXDW4_HWSEQ 0x00000080 1032 #define R92C_TXDW4_DRVRATE 0x00000100 1033 #define R92C_TXDW4_CTS2SELF 0x00000800 1034 #define R92C_TXDW4_RTSEN 0x00001000 1035 #define R92C_TXDW4_HWRTSEN 0x00002000 1036 #define R92C_TXDW4_SCO_M 0x003f0000 1037 #define R92C_TXDW4_SCO_S 20 1038 #define R92C_TXDW4_SCO_SCA 1 1039 #define R92C_TXDW4_SCO_SCB 2 1040 #define R92C_TXDW4_40MHZ 0x02000000 1041 1042 uint32_t txdw5; 1043 #define R92C_TXDW5_DATARATE_M 0x0000003f 1044 #define R92C_TXDW5_DATARATE_S 0 1045 #define R92C_TXDW5_SGI 0x00000040 1046 #define R92C_TXDW5_AGGNUM_M 0xff000000 1047 #define R92C_TXDW5_AGGNUM_S 24 1048 1049 uint32_t txdw6; 1050 uint16_t txdsum; 1051 uint16_t pad; 1052 } __packed __aligned(4); 1053
Indexes created Wed Oct 01 07:09:59 GMT 2025