motg.c revision 1.10
1 /* $NetBSD: motg.c,v 1.10 2014/09/13 17:42:48 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include "opt_motg.h" 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.10 2014/09/13 17:42:48 jmcneill Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #ifdef MOTG_ALLWINNER 68 #include <arch/arm/allwinner/awin_otgreg.h> 69 #else 70 #include <dev/usb/motgreg.h> 71 #endif 72 73 #include <dev/usb/motgvar.h> 74 #include <dev/usb/usbroothub_subr.h> 75 76 #define MOTG_DEBUG 77 #ifdef MOTG_DEBUG 78 #define DPRINTF(x) if (motgdebug) printf x 79 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 80 #define MD_ROOT 0x0002 81 #define MD_CTRL 0x0004 82 #define MD_BULK 0x0008 83 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 84 int motgdebug = 0; 85 #else 86 #define DPRINTF(x) 87 #define DPRINTFN(n,x) 88 #endif 89 90 /* various timeouts, for various speeds */ 91 /* control NAK timeouts */ 92 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 93 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 94 95 /* intr/iso polling intervals */ 96 #define POLL_TO 100 /* 100 frames, about 0.1s */ 97 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 98 99 /* bulk NAK timeouts */ 100 #define NAK_TO_BULK 0 /* disabled */ 101 #define NAK_TO_BULK_HIGH 0 102 103 static void motg_hub_change(struct motg_softc *); 104 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 105 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 106 static void motg_root_ctrl_abort(usbd_xfer_handle); 107 static void motg_root_ctrl_close(usbd_pipe_handle); 108 static void motg_root_ctrl_done(usbd_xfer_handle); 109 110 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 111 static usbd_status motg_root_intr_start(usbd_xfer_handle); 112 static void motg_root_intr_abort(usbd_xfer_handle); 113 static void motg_root_intr_close(usbd_pipe_handle); 114 static void motg_root_intr_done(usbd_xfer_handle); 115 116 static usbd_status motg_open(usbd_pipe_handle); 117 static void motg_poll(struct usbd_bus *); 118 static void motg_softintr(void *); 119 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 120 static void motg_freem(struct usbd_bus *, usb_dma_t *); 121 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 122 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 123 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 124 static void motg_noop(usbd_pipe_handle pipe); 125 static usbd_status motg_portreset(struct motg_softc*); 126 127 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 128 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 129 static void motg_device_ctrl_abort(usbd_xfer_handle); 130 static void motg_device_ctrl_close(usbd_pipe_handle); 131 static void motg_device_ctrl_done(usbd_xfer_handle); 132 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 133 static void motg_device_ctrl_read(usbd_xfer_handle); 134 static void motg_device_ctrl_intr_rx(struct motg_softc *); 135 static void motg_device_ctrl_intr_tx(struct motg_softc *); 136 137 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 138 static usbd_status motg_device_data_start(usbd_xfer_handle); 139 static usbd_status motg_device_data_start1(struct motg_softc *, 140 struct motg_hw_ep *); 141 static void motg_device_data_abort(usbd_xfer_handle); 142 static void motg_device_data_close(usbd_pipe_handle); 143 static void motg_device_data_done(usbd_xfer_handle); 144 static void motg_device_intr_rx(struct motg_softc *, int); 145 static void motg_device_intr_tx(struct motg_softc *, int); 146 static void motg_device_data_read(usbd_xfer_handle); 147 static void motg_device_data_write(usbd_xfer_handle); 148 149 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 150 static void motg_device_clear_toggle(usbd_pipe_handle); 151 static void motg_device_xfer_abort(usbd_xfer_handle); 152 153 #define MOTG_INTR_ENDPT 1 154 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 155 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 156 #define UWRITE1(sc, r, x) \ 157 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 158 } while (/*CONSTCOND*/0) 159 #define UWRITE2(sc, r, x) \ 160 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 161 } while (/*CONSTCOND*/0) 162 #define UWRITE4(sc, r, x) \ 163 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 164 } while (/*CONSTCOND*/0) 165 166 static __inline uint32_t 167 UREAD1(struct motg_softc *sc, bus_size_t r) 168 { 169 170 UBARR(sc); 171 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 172 } 173 static __inline uint32_t 174 UREAD2(struct motg_softc *sc, bus_size_t r) 175 { 176 177 UBARR(sc); 178 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 179 } 180 181 #if 0 182 static __inline uint32_t 183 UREAD4(struct motg_softc *sc, bus_size_t r) 184 { 185 186 UBARR(sc); 187 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 188 } 189 #endif 190 191 static void 192 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 193 { 194 uint8_t val; 195 196 val = UREAD1(sc, MUSB2_REG_POWER); 197 if (on) 198 val |= MUSB2_MASK_SOFTC; 199 else 200 val &= ~MUSB2_MASK_SOFTC; 201 202 UWRITE1(sc, MUSB2_REG_POWER, val); 203 } 204 205 const struct usbd_bus_methods motg_bus_methods = { 206 .open_pipe = motg_open, 207 .soft_intr = motg_softintr, 208 .do_poll = motg_poll, 209 .allocm = motg_allocm, 210 .freem = motg_freem, 211 .allocx = motg_allocx, 212 .freex = motg_freex, 213 .get_lock = motg_get_lock, 214 .new_device = NULL, 215 }; 216 217 const struct usbd_pipe_methods motg_root_ctrl_methods = { 218 .transfer = motg_root_ctrl_transfer, 219 .start = motg_root_ctrl_start, 220 .abort = motg_root_ctrl_abort, 221 .close = motg_root_ctrl_close, 222 .cleartoggle = motg_noop, 223 .done = motg_root_ctrl_done, 224 }; 225 226 const struct usbd_pipe_methods motg_root_intr_methods = { 227 .transfer = motg_root_intr_transfer, 228 .start = motg_root_intr_start, 229 .abort = motg_root_intr_abort, 230 .close = motg_root_intr_close, 231 .cleartoggle = motg_noop, 232 .done = motg_root_intr_done, 233 }; 234 235 const struct usbd_pipe_methods motg_device_ctrl_methods = { 236 .transfer = motg_device_ctrl_transfer, 237 .start = motg_device_ctrl_start, 238 .abort = motg_device_ctrl_abort, 239 .close = motg_device_ctrl_close, 240 .cleartoggle = motg_noop, 241 .done = motg_device_ctrl_done, 242 }; 243 244 const struct usbd_pipe_methods motg_device_data_methods = { 245 .transfer = motg_device_data_transfer, 246 .start = motg_device_data_start, 247 .abort = motg_device_data_abort, 248 .close = motg_device_data_close, 249 .cleartoggle = motg_device_clear_toggle, 250 .done = motg_device_data_done, 251 }; 252 253 usbd_status 254 motg_init(struct motg_softc *sc) 255 { 256 uint32_t nrx, ntx, val; 257 int dynfifo; 258 int offset, i; 259 260 if (sc->sc_mode == MOTG_MODE_DEVICE) 261 return USBD_NORMAL_COMPLETION; /* not supported */ 262 263 /* disable all interrupts */ 264 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 265 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 266 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 267 /* disable pullup */ 268 269 musbotg_pull_common(sc, 0); 270 271 #ifdef MUSB2_REG_RXDBDIS 272 /* disable double packet buffering XXX what's this ? */ 273 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 274 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 275 #endif 276 277 /* enable HighSpeed and ISO Update flags */ 278 279 UWRITE1(sc, MUSB2_REG_POWER, 280 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 281 282 if (sc->sc_mode == MOTG_MODE_DEVICE) { 283 /* clear Session bit, if set */ 284 val = UREAD1(sc, MUSB2_REG_DEVCTL); 285 val &= ~MUSB2_MASK_SESS; 286 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 287 } else { 288 /* Enter session for Host mode */ 289 val = UREAD1(sc, MUSB2_REG_DEVCTL); 290 val |= MUSB2_MASK_SESS; 291 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 292 } 293 delay(1000); 294 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 295 296 /* disable testmode */ 297 298 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 299 300 #ifdef MUSB2_REG_MISC 301 /* set default value */ 302 303 UWRITE1(sc, MUSB2_REG_MISC, 0); 304 #endif 305 306 /* select endpoint index 0 */ 307 308 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 309 310 if (sc->sc_ep_max == 0) { 311 /* read out number of endpoints */ 312 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 313 314 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 315 316 /* these numbers exclude the control endpoint */ 317 318 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 319 320 sc->sc_ep_max = MAX(nrx, ntx); 321 } else { 322 nrx = ntx = sc->sc_ep_max; 323 } 324 if (sc->sc_ep_max == 0) { 325 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 326 return USBD_INVAL; 327 } 328 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 329 /* read out configuration data */ 330 val = UREAD1(sc, MUSB2_REG_CONFDATA); 331 332 DPRINTF(("Config Data: 0x%02x\n", val)); 333 334 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 335 336 if (dynfifo) { 337 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 338 "assuming 16Kbytes of FIFO RAM\n"); 339 } 340 341 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 342 343 /* initialise endpoint profiles */ 344 sc->sc_in_ep[0].ep_fifo_size = 64; 345 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 346 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 347 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 348 offset = 64; 349 350 for (i = 1; i <= sc->sc_ep_max; i++) { 351 int fiforx_size, fifotx_size, fifo_size; 352 353 /* select endpoint */ 354 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 355 356 val = UREAD1(sc, MUSB2_REG_FSIZE); 357 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 358 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 359 360 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 361 i, fifotx_size, fiforx_size, dynfifo)); 362 363 if (dynfifo) { 364 if (i < 3) { 365 fifo_size = 12; /* 4K */ 366 } else if (i < 10) { 367 fifo_size = 10; /* 1K */ 368 } else { 369 fifo_size = 7; /* 128 bytes */ 370 } 371 if (fiforx_size && (i <= nrx)) { 372 fiforx_size = fifo_size; 373 if (fifo_size > 7) { 374 #if 0 375 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 376 MUSB2_VAL_FIFOSZ(fifo_size) | 377 MUSB2_MASK_FIFODB); 378 #else 379 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 380 MUSB2_VAL_FIFOSZ(fifo_size)); 381 #endif 382 } else { 383 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 384 MUSB2_VAL_FIFOSZ(fifo_size)); 385 } 386 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 387 offset >> 3); 388 offset += (1 << fiforx_size); 389 } 390 if (fifotx_size && (i <= ntx)) { 391 fifotx_size = fifo_size; 392 if (fifo_size > 7) { 393 #if 0 394 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 395 MUSB2_VAL_FIFOSZ(fifo_size) | 396 MUSB2_MASK_FIFODB); 397 #else 398 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 399 MUSB2_VAL_FIFOSZ(fifo_size)); 400 #endif 401 } else { 402 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size)); 404 } 405 406 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 407 offset >> 3); 408 409 offset += (1 << fifotx_size); 410 } 411 } 412 if (fiforx_size && (i <= nrx)) { 413 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 414 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 415 } 416 if (fifotx_size && (i <= ntx)) { 417 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 418 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 419 } 420 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 421 } 422 423 424 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 425 426 /* turn on default interrupts */ 427 428 if (sc->sc_mode == MOTG_MODE_HOST) { 429 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 430 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 431 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 432 } else 433 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 434 435 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 436 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 437 438 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 439 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 440 441 /* Set up the bus struct. */ 442 sc->sc_bus.methods = &motg_bus_methods; 443 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 444 sc->sc_bus.usbrev = USBREV_2_0; 445 sc->sc_bus.hci_private = sc; 446 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 447 "Mentor Graphics"); 448 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 449 return USBD_NORMAL_COMPLETION; 450 } 451 452 static int 453 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 454 { 455 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 456 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 457 struct motg_hw_ep *ep; 458 int i, size; 459 460 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 461 sc->sc_in_ep : sc->sc_out_ep; 462 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 463 464 for (i = sc->sc_ep_max; i >= 1; i--) { 465 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 466 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 467 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 468 if (ep[i].ep_fifo_size >= size) { 469 /* found a suitable endpoint */ 470 otgpipe->hw_ep = &ep[i]; 471 mutex_enter(&sc->sc_lock); 472 if (otgpipe->hw_ep->refcount > 0) { 473 /* no luck, try next */ 474 mutex_exit(&sc->sc_lock); 475 otgpipe->hw_ep = NULL; 476 } else { 477 otgpipe->hw_ep->refcount++; 478 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 479 otgpipe, ep_pipe_list); 480 mutex_exit(&sc->sc_lock); 481 return 0; 482 } 483 } 484 } 485 return -1; 486 } 487 488 /* Open a new pipe. */ 489 usbd_status 490 motg_open(usbd_pipe_handle pipe) 491 { 492 struct motg_softc *sc = pipe->device->bus->hci_private; 493 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 494 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 495 496 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 497 pipe, pipe->device->address, 498 ed->bEndpointAddress, sc->sc_root_addr)); 499 500 if (sc->sc_dying) 501 return USBD_IOERROR; 502 503 /* toggle state needed for bulk endpoints */ 504 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 505 506 if (pipe->device->address == sc->sc_root_addr) { 507 switch (ed->bEndpointAddress) { 508 case USB_CONTROL_ENDPOINT: 509 pipe->methods = &motg_root_ctrl_methods; 510 break; 511 case UE_DIR_IN | MOTG_INTR_ENDPT: 512 pipe->methods = &motg_root_intr_methods; 513 break; 514 default: 515 return (USBD_INVAL); 516 } 517 } else { 518 switch (ed->bmAttributes & UE_XFERTYPE) { 519 case UE_CONTROL: 520 pipe->methods = &motg_device_ctrl_methods; 521 /* always use sc_in_ep[0] for in and out */ 522 otgpipe->hw_ep = &sc->sc_in_ep[0]; 523 mutex_enter(&sc->sc_lock); 524 otgpipe->hw_ep->refcount++; 525 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 526 otgpipe, ep_pipe_list); 527 mutex_exit(&sc->sc_lock); 528 break; 529 case UE_BULK: 530 case UE_INTERRUPT: 531 DPRINTFN(MD_BULK, 532 ("new %s %s pipe wMaxPacketSize %d\n", 533 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 534 "bulk" : "interrupt", 535 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 536 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 537 if (motg_select_ep(sc, pipe) != 0) 538 goto bad; 539 KASSERT(otgpipe->hw_ep != NULL); 540 pipe->methods = &motg_device_data_methods; 541 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 542 break; 543 default: 544 goto bad; 545 #ifdef notyet 546 case UE_ISOCHRONOUS: 547 ... 548 break; 549 #endif /* notyet */ 550 } 551 } 552 return (USBD_NORMAL_COMPLETION); 553 554 bad: 555 return (USBD_NOMEM); 556 } 557 558 void 559 motg_softintr(void *v) 560 { 561 struct usbd_bus *bus = v; 562 struct motg_softc *sc = bus->hci_private; 563 uint16_t rx_status, tx_status; 564 uint8_t ctrl_status; 565 uint32_t val; 566 int i; 567 568 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 569 570 DPRINTFN(MD_ROOT | MD_CTRL, 571 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 572 573 mutex_spin_enter(&sc->sc_intr_lock); 574 rx_status = sc->sc_intr_rx_ep; 575 sc->sc_intr_rx_ep = 0; 576 tx_status = sc->sc_intr_tx_ep; 577 sc->sc_intr_tx_ep = 0; 578 ctrl_status = sc->sc_intr_ctrl; 579 sc->sc_intr_ctrl = 0; 580 mutex_spin_exit(&sc->sc_intr_lock); 581 582 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 583 584 if (ctrl_status & (MUSB2_MASK_IRESET | 585 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 586 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 587 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 588 ctrl_status)); 589 590 if (ctrl_status & MUSB2_MASK_IRESET) { 591 sc->sc_isreset = 1; 592 sc->sc_port_suspended = 0; 593 sc->sc_port_suspended_change = 1; 594 sc->sc_connected_changed = 1; 595 sc->sc_port_enabled = 1; 596 597 val = UREAD1(sc, MUSB2_REG_POWER); 598 if (val & MUSB2_MASK_HSMODE) 599 sc->sc_high_speed = 1; 600 else 601 sc->sc_high_speed = 0; 602 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 603 sc->sc_high_speed)); 604 605 /* turn off interrupts */ 606 val = MUSB2_MASK_IRESET; 607 val &= ~MUSB2_MASK_IRESUME; 608 val |= MUSB2_MASK_ISUSP; 609 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 610 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 611 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 612 } 613 if (ctrl_status & MUSB2_MASK_IRESUME) { 614 if (sc->sc_port_suspended) { 615 sc->sc_port_suspended = 0; 616 sc->sc_port_suspended_change = 1; 617 val = UREAD1(sc, MUSB2_REG_INTUSBE); 618 /* disable resume interrupt */ 619 val &= ~MUSB2_MASK_IRESUME; 620 /* enable suspend interrupt */ 621 val |= MUSB2_MASK_ISUSP; 622 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 623 } 624 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 625 if (!sc->sc_port_suspended) { 626 sc->sc_port_suspended = 1; 627 sc->sc_port_suspended_change = 1; 628 629 val = UREAD1(sc, MUSB2_REG_INTUSBE); 630 /* disable suspend interrupt */ 631 val &= ~MUSB2_MASK_ISUSP; 632 /* enable resume interrupt */ 633 val |= MUSB2_MASK_IRESUME; 634 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 635 } 636 } 637 if (ctrl_status & MUSB2_MASK_ICONN) { 638 sc->sc_connected = 1; 639 sc->sc_connected_changed = 1; 640 sc->sc_isreset = 1; 641 sc->sc_port_enabled = 1; 642 } else if (ctrl_status & MUSB2_MASK_IDISC) { 643 sc->sc_connected = 0; 644 sc->sc_connected_changed = 1; 645 sc->sc_isreset = 0; 646 sc->sc_port_enabled = 0; 647 } 648 649 /* complete root HUB interrupt endpoint */ 650 651 motg_hub_change(sc); 652 } 653 /* 654 * read in interrupt status and mix with the status we 655 * got from the wrapper 656 */ 657 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 658 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 659 660 if (rx_status & 0x01) 661 panic("ctrl_rx %08x", rx_status); 662 if (tx_status & 0x01) 663 motg_device_ctrl_intr_tx(sc); 664 for (i = 1; i <= sc->sc_ep_max; i++) { 665 if (rx_status & (0x01 << i)) 666 motg_device_intr_rx(sc, i); 667 if (tx_status & (0x01 << i)) 668 motg_device_intr_tx(sc, i); 669 } 670 return; 671 } 672 673 void 674 motg_poll(struct usbd_bus *bus) 675 { 676 struct motg_softc *sc = bus->hci_private; 677 678 sc->sc_intr_poll(sc->sc_intr_poll_arg); 679 mutex_enter(&sc->sc_lock); 680 motg_softintr(bus); 681 mutex_exit(&sc->sc_lock); 682 } 683 684 int 685 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 686 uint8_t ctrl) 687 { 688 KASSERT(mutex_owned(&sc->sc_intr_lock)); 689 sc->sc_intr_tx_ep = tx_ep; 690 sc->sc_intr_rx_ep = rx_ep; 691 sc->sc_intr_ctrl = ctrl; 692 693 if (!sc->sc_bus.use_polling) { 694 sc->sc_bus.no_intrs++; 695 usb_schedsoftintr(&sc->sc_bus); 696 } 697 return 1; 698 } 699 700 int 701 motg_intr_vbus(struct motg_softc *sc, int vbus) 702 { 703 uint8_t val; 704 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 705 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 706 /* try to re-enter session for Host mode */ 707 val = UREAD1(sc, MUSB2_REG_DEVCTL); 708 val |= MUSB2_MASK_SESS; 709 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 710 } 711 return 1; 712 } 713 714 usbd_status 715 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 716 { 717 struct motg_softc *sc = bus->hci_private; 718 usbd_status status; 719 720 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 721 if (status == USBD_NOMEM) 722 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 723 return status; 724 } 725 726 void 727 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 728 { 729 if (dma->block->flags & USB_DMA_RESERVE) { 730 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 731 dma); 732 return; 733 } 734 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 735 } 736 737 usbd_xfer_handle 738 motg_allocx(struct usbd_bus *bus) 739 { 740 struct motg_softc *sc = bus->hci_private; 741 usbd_xfer_handle xfer; 742 743 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 744 if (xfer != NULL) { 745 memset(xfer, 0, sizeof(struct motg_xfer)); 746 UXFER(xfer)->sc = sc; 747 #ifdef DIAGNOSTIC 748 // XXX UXFER(xfer)->iinfo.isdone = 1; 749 xfer->busy_free = XFER_BUSY; 750 #endif 751 } 752 return (xfer); 753 } 754 755 void 756 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 757 { 758 struct motg_softc *sc = bus->hci_private; 759 760 #ifdef DIAGNOSTIC 761 if (xfer->busy_free != XFER_BUSY) { 762 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 763 xfer->busy_free); 764 } 765 xfer->busy_free = XFER_FREE; 766 #endif 767 pool_cache_put(sc->sc_xferpool, xfer); 768 } 769 770 static void 771 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 772 { 773 struct motg_softc *sc = bus->hci_private; 774 775 *lock = &sc->sc_lock; 776 } 777 778 /* 779 * Data structures and routines to emulate the root hub. 780 */ 781 usb_device_descriptor_t motg_devd = { 782 USB_DEVICE_DESCRIPTOR_SIZE, 783 UDESC_DEVICE, /* type */ 784 {0x00, 0x01}, /* USB version */ 785 UDCLASS_HUB, /* class */ 786 UDSUBCLASS_HUB, /* subclass */ 787 UDPROTO_FSHUB, /* protocol */ 788 64, /* max packet */ 789 {0},{0},{0x00,0x01}, /* device id */ 790 1,2,0, /* string indicies */ 791 1 /* # of configurations */ 792 }; 793 794 const usb_config_descriptor_t motg_confd = { 795 USB_CONFIG_DESCRIPTOR_SIZE, 796 UDESC_CONFIG, 797 {USB_CONFIG_DESCRIPTOR_SIZE + 798 USB_INTERFACE_DESCRIPTOR_SIZE + 799 USB_ENDPOINT_DESCRIPTOR_SIZE}, 800 1, 801 1, 802 0, 803 UC_ATTR_MBO | UC_SELF_POWERED, 804 0 /* max power */ 805 }; 806 807 const usb_interface_descriptor_t motg_ifcd = { 808 USB_INTERFACE_DESCRIPTOR_SIZE, 809 UDESC_INTERFACE, 810 0, 811 0, 812 1, 813 UICLASS_HUB, 814 UISUBCLASS_HUB, 815 UIPROTO_FSHUB, 816 0 817 }; 818 819 const usb_endpoint_descriptor_t motg_endpd = { 820 USB_ENDPOINT_DESCRIPTOR_SIZE, 821 UDESC_ENDPOINT, 822 UE_DIR_IN | MOTG_INTR_ENDPT, 823 UE_INTERRUPT, 824 {8}, 825 255 826 }; 827 828 const usb_hub_descriptor_t motg_hubd = { 829 USB_HUB_DESCRIPTOR_SIZE, 830 UDESC_HUB, 831 1, 832 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 833 50, /* power on to power good */ 834 0, 835 { 0x00 }, /* port is removable */ 836 { 0 }, 837 }; 838 839 /* 840 * Simulate a hardware hub by handling all the necessary requests. 841 */ 842 usbd_status 843 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 844 { 845 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 846 usbd_status err; 847 848 /* Insert last in queue. */ 849 mutex_enter(&sc->sc_lock); 850 err = usb_insert_transfer(xfer); 851 mutex_exit(&sc->sc_lock); 852 if (err) 853 return (err); 854 855 /* 856 * Pipe isn't running (otherwise err would be USBD_INPROG), 857 * so start it first. 858 */ 859 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 860 } 861 862 usbd_status 863 motg_root_ctrl_start(usbd_xfer_handle xfer) 864 { 865 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 866 usb_device_request_t *req; 867 void *buf = NULL; 868 int len, value, index, status, change, l, totlen = 0; 869 usb_port_status_t ps; 870 usbd_status err; 871 uint32_t val; 872 873 if (sc->sc_dying) 874 return (USBD_IOERROR); 875 876 #ifdef DIAGNOSTIC 877 if (!(xfer->rqflags & URQ_REQUEST)) 878 panic("motg_root_ctrl_start: not a request"); 879 #endif 880 req = &xfer->request; 881 882 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 883 req->bmRequestType, req->bRequest)); 884 885 len = UGETW(req->wLength); 886 value = UGETW(req->wValue); 887 index = UGETW(req->wIndex); 888 889 if (len != 0) 890 buf = KERNADDR(&xfer->dmabuf, 0); 891 892 #define C(x,y) ((x) | ((y) << 8)) 893 switch(C(req->bRequest, req->bmRequestType)) { 894 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 895 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 896 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 897 /* 898 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 899 * for the integrated root hub. 900 */ 901 break; 902 case C(UR_GET_CONFIG, UT_READ_DEVICE): 903 if (len > 0) { 904 *(u_int8_t *)buf = sc->sc_root_conf; 905 totlen = 1; 906 } 907 break; 908 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 909 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 910 if (len == 0) 911 break; 912 switch(value >> 8) { 913 case UDESC_DEVICE: 914 if ((value & 0xff) != 0) { 915 err = USBD_IOERROR; 916 goto ret; 917 } 918 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 919 USETW(motg_devd.idVendor, sc->sc_id_vendor); 920 memcpy(buf, &motg_devd, l); 921 break; 922 case UDESC_CONFIG: 923 if ((value & 0xff) != 0) { 924 err = USBD_IOERROR; 925 goto ret; 926 } 927 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 928 memcpy(buf, &motg_confd, l); 929 buf = (char *)buf + l; 930 len -= l; 931 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 932 totlen += l; 933 memcpy(buf, &motg_ifcd, l); 934 buf = (char *)buf + l; 935 len -= l; 936 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 937 totlen += l; 938 memcpy(buf, &motg_endpd, l); 939 break; 940 case UDESC_STRING: 941 #define sd ((usb_string_descriptor_t *)buf) 942 switch (value & 0xff) { 943 case 0: /* Language table */ 944 totlen = usb_makelangtbl(sd, len); 945 break; 946 case 1: /* Vendor */ 947 totlen = usb_makestrdesc(sd, len, 948 sc->sc_vendor); 949 break; 950 case 2: /* Product */ 951 totlen = usb_makestrdesc(sd, len, 952 "MOTG root hub"); 953 break; 954 } 955 #undef sd 956 break; 957 default: 958 err = USBD_IOERROR; 959 goto ret; 960 } 961 break; 962 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 963 if (len > 0) { 964 *(u_int8_t *)buf = 0; 965 totlen = 1; 966 } 967 break; 968 case C(UR_GET_STATUS, UT_READ_DEVICE): 969 if (len > 1) { 970 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 971 totlen = 2; 972 } 973 break; 974 case C(UR_GET_STATUS, UT_READ_INTERFACE): 975 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 976 if (len > 1) { 977 USETW(((usb_status_t *)buf)->wStatus, 0); 978 totlen = 2; 979 } 980 break; 981 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 982 if (value >= USB_MAX_DEVICES) { 983 err = USBD_IOERROR; 984 goto ret; 985 } 986 sc->sc_root_addr = value; 987 break; 988 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 989 if (value != 0 && value != 1) { 990 err = USBD_IOERROR; 991 goto ret; 992 } 993 sc->sc_root_conf = value; 994 break; 995 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 996 break; 997 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 998 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 999 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1000 err = USBD_IOERROR; 1001 goto ret; 1002 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1003 break; 1004 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1005 break; 1006 /* Hub requests */ 1007 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1008 break; 1009 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1010 DPRINTFN(MD_ROOT, 1011 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1012 "port=%d feature=%d\n", 1013 index, value)); 1014 if (index != 1) { 1015 err = USBD_IOERROR; 1016 goto ret; 1017 } 1018 switch(value) { 1019 case UHF_PORT_ENABLE: 1020 sc->sc_port_enabled = 0; 1021 break; 1022 case UHF_PORT_SUSPEND: 1023 if (sc->sc_port_suspended != 0) { 1024 val = UREAD1(sc, MUSB2_REG_POWER); 1025 val &= ~MUSB2_MASK_SUSPMODE; 1026 val |= MUSB2_MASK_RESUME; 1027 UWRITE1(sc, MUSB2_REG_POWER, val); 1028 /* wait 20 milliseconds */ 1029 usb_delay_ms(&sc->sc_bus, 20); 1030 val = UREAD1(sc, MUSB2_REG_POWER); 1031 val &= ~MUSB2_MASK_RESUME; 1032 UWRITE1(sc, MUSB2_REG_POWER, val); 1033 sc->sc_port_suspended = 0; 1034 sc->sc_port_suspended_change = 1; 1035 } 1036 break; 1037 case UHF_PORT_RESET: 1038 break; 1039 case UHF_C_PORT_CONNECTION: 1040 break; 1041 case UHF_C_PORT_ENABLE: 1042 break; 1043 case UHF_C_PORT_OVER_CURRENT: 1044 break; 1045 case UHF_C_PORT_RESET: 1046 sc->sc_isreset = 0; 1047 err = USBD_NORMAL_COMPLETION; 1048 goto ret; 1049 case UHF_PORT_POWER: 1050 /* XXX todo */ 1051 break; 1052 case UHF_PORT_CONNECTION: 1053 case UHF_PORT_OVER_CURRENT: 1054 case UHF_PORT_LOW_SPEED: 1055 case UHF_C_PORT_SUSPEND: 1056 default: 1057 err = USBD_IOERROR; 1058 goto ret; 1059 } 1060 break; 1061 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1062 err = USBD_IOERROR; 1063 goto ret; 1064 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1065 if (len == 0) 1066 break; 1067 if ((value & 0xff) != 0) { 1068 err = USBD_IOERROR; 1069 goto ret; 1070 } 1071 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1072 totlen = l; 1073 memcpy(buf, &motg_hubd, l); 1074 break; 1075 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1076 if (len != 4) { 1077 err = USBD_IOERROR; 1078 goto ret; 1079 } 1080 memset(buf, 0, len); 1081 totlen = len; 1082 break; 1083 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1084 if (index != 1) { 1085 err = USBD_IOERROR; 1086 goto ret; 1087 } 1088 if (len != 4) { 1089 err = USBD_IOERROR; 1090 goto ret; 1091 } 1092 status = change = 0; 1093 if (sc->sc_connected) 1094 status |= UPS_CURRENT_CONNECT_STATUS; 1095 if (sc->sc_connected_changed) { 1096 change |= UPS_C_CONNECT_STATUS; 1097 sc->sc_connected_changed = 0; 1098 } 1099 if (sc->sc_port_enabled) 1100 status |= UPS_PORT_ENABLED; 1101 if (sc->sc_port_enabled_changed) { 1102 change |= UPS_C_PORT_ENABLED; 1103 sc->sc_port_enabled_changed = 0; 1104 } 1105 if (sc->sc_port_suspended) 1106 status |= UPS_SUSPEND; 1107 if (sc->sc_high_speed) 1108 status |= UPS_HIGH_SPEED; 1109 status |= UPS_PORT_POWER; /* XXX */ 1110 if (sc->sc_isreset) 1111 change |= UPS_C_PORT_RESET; 1112 USETW(ps.wPortStatus, status); 1113 USETW(ps.wPortChange, change); 1114 l = min(len, sizeof ps); 1115 memcpy(buf, &ps, l); 1116 totlen = l; 1117 break; 1118 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1119 err = USBD_IOERROR; 1120 goto ret; 1121 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1122 break; 1123 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1124 if (index != 1) { 1125 err = USBD_IOERROR; 1126 goto ret; 1127 } 1128 switch(value) { 1129 case UHF_PORT_ENABLE: 1130 sc->sc_port_enabled = 1; 1131 break; 1132 case UHF_PORT_SUSPEND: 1133 if (sc->sc_port_suspended == 0) { 1134 val = UREAD1(sc, MUSB2_REG_POWER); 1135 val |= MUSB2_MASK_SUSPMODE; 1136 UWRITE1(sc, MUSB2_REG_POWER, val); 1137 /* wait 20 milliseconds */ 1138 usb_delay_ms(&sc->sc_bus, 20); 1139 sc->sc_port_suspended = 1; 1140 sc->sc_port_suspended_change = 1; 1141 } 1142 break; 1143 case UHF_PORT_RESET: 1144 err = motg_portreset(sc); 1145 goto ret; 1146 case UHF_PORT_POWER: 1147 /* XXX todo */ 1148 err = USBD_NORMAL_COMPLETION; 1149 goto ret; 1150 case UHF_C_PORT_CONNECTION: 1151 case UHF_C_PORT_ENABLE: 1152 case UHF_C_PORT_OVER_CURRENT: 1153 case UHF_PORT_CONNECTION: 1154 case UHF_PORT_OVER_CURRENT: 1155 case UHF_PORT_LOW_SPEED: 1156 case UHF_C_PORT_SUSPEND: 1157 case UHF_C_PORT_RESET: 1158 default: 1159 err = USBD_IOERROR; 1160 goto ret; 1161 } 1162 break; 1163 default: 1164 err = USBD_IOERROR; 1165 goto ret; 1166 } 1167 xfer->actlen = totlen; 1168 err = USBD_NORMAL_COMPLETION; 1169 ret: 1170 xfer->status = err; 1171 mutex_enter(&sc->sc_lock); 1172 usb_transfer_complete(xfer); 1173 mutex_exit(&sc->sc_lock); 1174 return (USBD_IN_PROGRESS); 1175 } 1176 1177 /* Abort a root control request. */ 1178 void 1179 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1180 { 1181 /* Nothing to do, all transfers are synchronous. */ 1182 } 1183 1184 /* Close the root pipe. */ 1185 void 1186 motg_root_ctrl_close(usbd_pipe_handle pipe) 1187 { 1188 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1189 } 1190 1191 void 1192 motg_root_ctrl_done(usbd_xfer_handle xfer) 1193 { 1194 } 1195 1196 /* Abort a root interrupt request. */ 1197 void 1198 motg_root_intr_abort(usbd_xfer_handle xfer) 1199 { 1200 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1201 1202 KASSERT(mutex_owned(&sc->sc_lock)); 1203 KASSERT(xfer->pipe->intrxfer == xfer); 1204 1205 sc->sc_intr_xfer = NULL; 1206 1207 #ifdef DIAGNOSTIC 1208 // XXX UXFER(xfer)->iinfo.isdone = 1; 1209 #endif 1210 xfer->status = USBD_CANCELLED; 1211 usb_transfer_complete(xfer); 1212 } 1213 1214 usbd_status 1215 motg_root_intr_transfer(usbd_xfer_handle xfer) 1216 { 1217 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1218 usbd_status err; 1219 1220 /* Insert last in queue. */ 1221 mutex_enter(&sc->sc_lock); 1222 err = usb_insert_transfer(xfer); 1223 mutex_exit(&sc->sc_lock); 1224 if (err) 1225 return (err); 1226 1227 /* 1228 * Pipe isn't running (otherwise err would be USBD_INPROG), 1229 * start first 1230 */ 1231 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1232 } 1233 1234 /* Start a transfer on the root interrupt pipe */ 1235 usbd_status 1236 motg_root_intr_start(usbd_xfer_handle xfer) 1237 { 1238 usbd_pipe_handle pipe = xfer->pipe; 1239 struct motg_softc *sc = pipe->device->bus->hci_private; 1240 1241 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1242 xfer, xfer->length, xfer->flags)); 1243 1244 if (sc->sc_dying) 1245 return (USBD_IOERROR); 1246 1247 sc->sc_intr_xfer = xfer; 1248 return (USBD_IN_PROGRESS); 1249 } 1250 1251 /* Close the root interrupt pipe. */ 1252 void 1253 motg_root_intr_close(usbd_pipe_handle pipe) 1254 { 1255 struct motg_softc *sc = pipe->device->bus->hci_private; 1256 1257 KASSERT(mutex_owned(&sc->sc_lock)); 1258 1259 sc->sc_intr_xfer = NULL; 1260 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1261 } 1262 1263 void 1264 motg_root_intr_done(usbd_xfer_handle xfer) 1265 { 1266 } 1267 1268 void 1269 motg_noop(usbd_pipe_handle pipe) 1270 { 1271 } 1272 1273 static usbd_status 1274 motg_portreset(struct motg_softc *sc) 1275 { 1276 uint32_t val; 1277 1278 val = UREAD1(sc, MUSB2_REG_POWER); 1279 val |= MUSB2_MASK_RESET; 1280 UWRITE1(sc, MUSB2_REG_POWER, val); 1281 /* Wait for 20 msec */ 1282 usb_delay_ms(&sc->sc_bus, 20); 1283 1284 val = UREAD1(sc, MUSB2_REG_POWER); 1285 val &= ~MUSB2_MASK_RESET; 1286 UWRITE1(sc, MUSB2_REG_POWER, val); 1287 1288 /* determine line speed */ 1289 val = UREAD1(sc, MUSB2_REG_POWER); 1290 if (val & MUSB2_MASK_HSMODE) 1291 sc->sc_high_speed = 1; 1292 else 1293 sc->sc_high_speed = 0; 1294 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1295 sc->sc_high_speed)); 1296 1297 sc->sc_isreset = 1; 1298 sc->sc_port_enabled = 1; 1299 return (USBD_NORMAL_COMPLETION); 1300 } 1301 1302 /* 1303 * This routine is executed when an interrupt on the root hub is detected 1304 */ 1305 static void 1306 motg_hub_change(struct motg_softc *sc) 1307 { 1308 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1309 usbd_pipe_handle pipe; 1310 u_char *p; 1311 1312 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1313 1314 if (xfer == NULL) 1315 return; /* the interrupt pipe is not open */ 1316 1317 pipe = xfer->pipe; 1318 if (pipe->device == NULL || pipe->device->bus == NULL) 1319 return; /* device has detached */ 1320 1321 p = KERNADDR(&xfer->dmabuf, 0); 1322 p[0] = 1<<1; 1323 xfer->actlen = 1; 1324 xfer->status = USBD_NORMAL_COMPLETION; 1325 usb_transfer_complete(xfer); 1326 } 1327 1328 static uint8_t 1329 motg_speed(u_int8_t speed) 1330 { 1331 switch(speed) { 1332 case USB_SPEED_LOW: 1333 return MUSB2_MASK_TI_SPEED_LO; 1334 case USB_SPEED_FULL: 1335 return MUSB2_MASK_TI_SPEED_FS; 1336 case USB_SPEED_HIGH: 1337 return MUSB2_MASK_TI_SPEED_HS; 1338 default: 1339 panic("motg: unknown speed %d", speed); 1340 /* NOTREACHED */ 1341 } 1342 } 1343 1344 static uint8_t 1345 motg_type(u_int8_t type) 1346 { 1347 switch(type) { 1348 case UE_CONTROL: 1349 return MUSB2_MASK_TI_PROTO_CTRL; 1350 case UE_ISOCHRONOUS: 1351 return MUSB2_MASK_TI_PROTO_ISOC; 1352 case UE_BULK: 1353 return MUSB2_MASK_TI_PROTO_BULK; 1354 case UE_INTERRUPT: 1355 return MUSB2_MASK_TI_PROTO_INTR; 1356 default: 1357 panic("motg: unknown type %d", type); 1358 /* NOTREACHED */ 1359 } 1360 } 1361 1362 static void 1363 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1364 { 1365 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1366 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1367 usbd_device_handle dev = otgpipe->pipe.device; 1368 int epnumber = otgpipe->hw_ep->ep_number; 1369 1370 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1371 if (dev->myhsport) { 1372 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1373 dev->myhsport->parent->address); 1374 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1375 dev->myhsport->portno); 1376 } else { 1377 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1378 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1379 } 1380 UWRITE1(sc, MUSB2_REG_TXTI, 1381 motg_speed(dev->speed) | 1382 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1383 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1384 ); 1385 if (epnumber == 0) { 1386 if (sc->sc_high_speed) { 1387 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1388 NAK_TO_CTRL_HIGH); 1389 } else { 1390 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1391 } 1392 } else { 1393 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1394 == UE_BULK) { 1395 if (sc->sc_high_speed) { 1396 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1397 NAK_TO_BULK_HIGH); 1398 } else { 1399 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1400 } 1401 } else { 1402 if (sc->sc_high_speed) { 1403 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1404 } else { 1405 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1406 } 1407 } 1408 } 1409 } 1410 1411 static void 1412 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1413 { 1414 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1415 usbd_device_handle dev = xfer->pipe->device; 1416 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1417 int epnumber = otgpipe->hw_ep->ep_number; 1418 1419 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1420 if (dev->myhsport) { 1421 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1422 dev->myhsport->parent->address); 1423 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1424 dev->myhsport->portno); 1425 } else { 1426 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1427 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1428 } 1429 UWRITE1(sc, MUSB2_REG_RXTI, 1430 motg_speed(dev->speed) | 1431 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1432 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1433 ); 1434 if (epnumber == 0) { 1435 if (sc->sc_high_speed) { 1436 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1437 NAK_TO_CTRL_HIGH); 1438 } else { 1439 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1440 } 1441 } else { 1442 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1443 == UE_BULK) { 1444 if (sc->sc_high_speed) { 1445 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1446 NAK_TO_BULK_HIGH); 1447 } else { 1448 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1449 } 1450 } else { 1451 if (sc->sc_high_speed) { 1452 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1453 } else { 1454 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1455 } 1456 } 1457 } 1458 } 1459 1460 static usbd_status 1461 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1462 { 1463 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1464 usbd_status err; 1465 1466 /* Insert last in queue. */ 1467 mutex_enter(&sc->sc_lock); 1468 err = usb_insert_transfer(xfer); 1469 xfer->status = USBD_NOT_STARTED; 1470 mutex_exit(&sc->sc_lock); 1471 if (err) 1472 return (err); 1473 1474 /* 1475 * Pipe isn't running (otherwise err would be USBD_INPROG), 1476 * so start it first. 1477 */ 1478 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1479 } 1480 1481 static usbd_status 1482 motg_device_ctrl_start(usbd_xfer_handle xfer) 1483 { 1484 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1485 usbd_status err; 1486 mutex_enter(&sc->sc_lock); 1487 err = motg_device_ctrl_start1(sc); 1488 mutex_exit(&sc->sc_lock); 1489 if (err != USBD_IN_PROGRESS) 1490 return err; 1491 if (sc->sc_bus.use_polling) 1492 motg_waitintr(sc, xfer); 1493 return USBD_IN_PROGRESS; 1494 } 1495 1496 static usbd_status 1497 motg_device_ctrl_start1(struct motg_softc *sc) 1498 { 1499 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1500 usbd_xfer_handle xfer = NULL; 1501 struct motg_pipe *otgpipe; 1502 usbd_status err = 0; 1503 1504 KASSERT(mutex_owned(&sc->sc_lock)); 1505 if (sc->sc_dying) 1506 return (USBD_IOERROR); 1507 1508 if (!sc->sc_connected) 1509 return (USBD_IOERROR); 1510 1511 if (ep->xfer != NULL) { 1512 err = USBD_IN_PROGRESS; 1513 goto end; 1514 } 1515 /* locate the first pipe with work to do */ 1516 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1517 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1518 DPRINTFN(MD_CTRL, 1519 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1520 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1521 1522 if (xfer != NULL) { 1523 /* move this pipe to the end of the list */ 1524 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1525 motg_pipe, ep_pipe_list); 1526 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1527 otgpipe, ep_pipe_list); 1528 break; 1529 } 1530 } 1531 if (xfer == NULL) { 1532 err = USBD_NOT_STARTED; 1533 goto end; 1534 } 1535 xfer->status = USBD_IN_PROGRESS; 1536 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1537 KASSERT(otgpipe->hw_ep == ep); 1538 #ifdef DIAGNOSTIC 1539 if (!(xfer->rqflags & URQ_REQUEST)) 1540 panic("motg_device_ctrl_transfer: not a request"); 1541 #endif 1542 // KASSERT(xfer->actlen == 0); 1543 xfer->actlen = 0; 1544 1545 ep->xfer = xfer; 1546 ep->datalen = xfer->length; 1547 if (ep->datalen > 0) 1548 ep->data = KERNADDR(&xfer->dmabuf, 0); 1549 else 1550 ep->data = NULL; 1551 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1552 (ep->datalen % 64) == 0) 1553 ep->need_short_xfer = 1; 1554 else 1555 ep->need_short_xfer = 0; 1556 /* now we need send this request */ 1557 DPRINTFN(MD_CTRL, 1558 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1559 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1560 xfer->pipe->device->address)); 1561 KASSERT(ep->phase == IDLE); 1562 ep->phase = SETUP; 1563 /* select endpoint 0 */ 1564 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1565 /* fifo should be empty at this point */ 1566 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1567 /* send data */ 1568 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1569 KASSERT(sizeof(xfer->request) == 8); 1570 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1571 (void *)&xfer->request, sizeof(xfer->request)); 1572 1573 motg_setup_endpoint_tx(xfer); 1574 /* start transaction */ 1575 UWRITE1(sc, MUSB2_REG_TXCSRL, 1576 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1577 1578 end: 1579 if (err) 1580 return (err); 1581 1582 return (USBD_IN_PROGRESS); 1583 } 1584 1585 static void 1586 motg_device_ctrl_read(usbd_xfer_handle xfer) 1587 { 1588 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1589 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1590 /* assume endpoint already selected */ 1591 motg_setup_endpoint_rx(xfer); 1592 /* start transaction */ 1593 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1594 otgpipe->hw_ep->phase = DATA_IN; 1595 } 1596 1597 static void 1598 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1599 { 1600 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1601 usbd_xfer_handle xfer = ep->xfer; 1602 uint8_t csr; 1603 int datalen, max_datalen; 1604 char *data; 1605 bool got_short; 1606 usbd_status new_status = USBD_IN_PROGRESS; 1607 1608 KASSERT(mutex_owned(&sc->sc_lock)); 1609 1610 #ifdef DIAGNOSTIC 1611 if (ep->phase != DATA_IN && 1612 ep->phase != STATUS_IN) 1613 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1614 #endif 1615 /* select endpoint 0 */ 1616 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1617 1618 /* read out FIFO status */ 1619 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1620 DPRINTFN(MD_CTRL, 1621 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1622 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1623 1624 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1625 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1626 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1627 1628 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1629 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1630 new_status = USBD_TIMEOUT; /* XXX */ 1631 goto complete; 1632 } 1633 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1634 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1635 new_status = USBD_STALLED; 1636 else 1637 new_status = USBD_IOERROR; 1638 /* clear status */ 1639 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1640 goto complete; 1641 } 1642 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1643 return; /* no data yet */ 1644 1645 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1646 goto complete; 1647 1648 if (ep->phase == STATUS_IN) { 1649 new_status = USBD_NORMAL_COMPLETION; 1650 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1651 goto complete; 1652 } 1653 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1654 DPRINTFN(MD_CTRL, 1655 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1656 ep->phase, datalen)); 1657 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1658 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1659 ep->datalen); 1660 if (datalen > max_datalen) { 1661 new_status = USBD_IOERROR; 1662 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1663 goto complete; 1664 } 1665 got_short = (datalen < max_datalen); 1666 if (datalen > 0) { 1667 KASSERT(ep->phase == DATA_IN); 1668 data = ep->data; 1669 ep->data += datalen; 1670 ep->datalen -= datalen; 1671 xfer->actlen += datalen; 1672 if (((vaddr_t)data & 0x3) == 0 && 1673 (datalen >> 2) > 0) { 1674 DPRINTFN(MD_CTRL, 1675 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1676 data, datalen)); 1677 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1678 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1679 data += (datalen & ~0x3); 1680 datalen -= (datalen & ~0x3); 1681 } 1682 DPRINTFN(MD_CTRL, 1683 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1684 data, datalen)); 1685 if (datalen) { 1686 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1687 MUSB2_REG_EPFIFO(0), data, datalen); 1688 } 1689 } 1690 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1691 KASSERT(ep->phase == DATA_IN); 1692 if (got_short || (ep->datalen == 0)) { 1693 if (ep->need_short_xfer == 0) { 1694 ep->phase = STATUS_OUT; 1695 UWRITE1(sc, MUSB2_REG_TXCSRH, 1696 UREAD1(sc, MUSB2_REG_TXCSRH) | 1697 MUSB2_MASK_CSR0H_PING_DIS); 1698 motg_setup_endpoint_tx(xfer); 1699 UWRITE1(sc, MUSB2_REG_TXCSRL, 1700 MUSB2_MASK_CSR0L_STATUSPKT | 1701 MUSB2_MASK_CSR0L_TXPKTRDY); 1702 return; 1703 } 1704 ep->need_short_xfer = 0; 1705 } 1706 motg_device_ctrl_read(xfer); 1707 return; 1708 complete: 1709 ep->phase = IDLE; 1710 ep->xfer = NULL; 1711 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1712 KASSERT(new_status != USBD_IN_PROGRESS); 1713 xfer->status = new_status; 1714 usb_transfer_complete(xfer); 1715 } 1716 motg_device_ctrl_start1(sc); 1717 } 1718 1719 static void 1720 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1721 { 1722 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1723 usbd_xfer_handle xfer = ep->xfer; 1724 uint8_t csr; 1725 int datalen; 1726 char *data; 1727 usbd_status new_status = USBD_IN_PROGRESS; 1728 1729 KASSERT(mutex_owned(&sc->sc_lock)); 1730 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1731 motg_device_ctrl_intr_rx(sc); 1732 return; 1733 } 1734 1735 #ifdef DIAGNOSTIC 1736 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1737 ep->phase != STATUS_OUT) 1738 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1739 #endif 1740 /* select endpoint 0 */ 1741 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1742 1743 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1744 DPRINTFN(MD_CTRL, 1745 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1746 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1747 1748 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1749 /* command not accepted */ 1750 new_status = USBD_STALLED; 1751 /* clear status */ 1752 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1753 goto complete; 1754 } 1755 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1756 new_status = USBD_TIMEOUT; /* XXX */ 1757 /* flush fifo */ 1758 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1759 UWRITE1(sc, MUSB2_REG_TXCSRH, 1760 UREAD1(sc, MUSB2_REG_TXCSRH) | 1761 MUSB2_MASK_CSR0H_FFLUSH); 1762 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1763 } 1764 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1765 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1766 goto complete; 1767 } 1768 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1769 new_status = USBD_IOERROR; 1770 /* clear status */ 1771 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1772 goto complete; 1773 } 1774 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1775 /* data still not sent */ 1776 return; 1777 } 1778 if (xfer == NULL) 1779 goto complete; 1780 if (ep->phase == STATUS_OUT) { 1781 /* 1782 * we have sent status and got no error; 1783 * declare transfer complete 1784 */ 1785 DPRINTFN(MD_CTRL, 1786 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1787 xfer, xfer->status)); 1788 new_status = USBD_NORMAL_COMPLETION; 1789 goto complete; 1790 } 1791 if (ep->datalen == 0) { 1792 if (ep->need_short_xfer) { 1793 ep->need_short_xfer = 0; 1794 /* one more data phase */ 1795 if (xfer->request.bmRequestType & UT_READ) { 1796 DPRINTFN(MD_CTRL, 1797 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1798 motg_device_ctrl_read(xfer); 1799 return; 1800 } /* else fall back to DATA_OUT */ 1801 } else { 1802 DPRINTFN(MD_CTRL, 1803 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1804 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1805 ep->phase = STATUS_IN; 1806 UWRITE1(sc, MUSB2_REG_RXCSRH, 1807 UREAD1(sc, MUSB2_REG_RXCSRH) | 1808 MUSB2_MASK_CSR0H_PING_DIS); 1809 motg_setup_endpoint_rx(xfer); 1810 UWRITE1(sc, MUSB2_REG_TXCSRL, 1811 MUSB2_MASK_CSR0L_STATUSPKT | 1812 MUSB2_MASK_CSR0L_REQPKT); 1813 return; 1814 } 1815 } 1816 if (xfer->request.bmRequestType & UT_READ) { 1817 motg_device_ctrl_read(xfer); 1818 return; 1819 } 1820 /* setup a dataout phase */ 1821 datalen = min(ep->datalen, 1822 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1823 ep->phase = DATA_OUT; 1824 DPRINTFN(MD_CTRL, 1825 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1826 UREAD1(sc, MUSB2_REG_TXCSRH))); 1827 if (datalen) { 1828 data = ep->data; 1829 ep->data += datalen; 1830 ep->datalen -= datalen; 1831 xfer->actlen += datalen; 1832 if (((vaddr_t)data & 0x3) == 0 && 1833 (datalen >> 2) > 0) { 1834 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1835 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1836 data += (datalen & ~0x3); 1837 datalen -= (datalen & ~0x3); 1838 } 1839 if (datalen) { 1840 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1841 MUSB2_REG_EPFIFO(0), data, datalen); 1842 } 1843 } 1844 /* send data */ 1845 motg_setup_endpoint_tx(xfer); 1846 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1847 return; 1848 1849 complete: 1850 ep->phase = IDLE; 1851 ep->xfer = NULL; 1852 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1853 KASSERT(new_status != USBD_IN_PROGRESS); 1854 xfer->status = new_status; 1855 usb_transfer_complete(xfer); 1856 } 1857 motg_device_ctrl_start1(sc); 1858 } 1859 1860 /* Abort a device control request. */ 1861 void 1862 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1863 { 1864 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1865 motg_device_xfer_abort(xfer); 1866 } 1867 1868 /* Close a device control pipe */ 1869 void 1870 motg_device_ctrl_close(usbd_pipe_handle pipe) 1871 { 1872 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 1873 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1874 struct motg_pipe *otgpipeiter; 1875 1876 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1877 KASSERT(mutex_owned(&sc->sc_lock)); 1878 KASSERT(otgpipe->hw_ep->xfer == NULL || 1879 otgpipe->hw_ep->xfer->pipe != pipe); 1880 1881 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1882 if (otgpipeiter == otgpipe) { 1883 /* remove from list */ 1884 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1885 motg_pipe, ep_pipe_list); 1886 otgpipe->hw_ep->refcount--; 1887 /* we're done */ 1888 return; 1889 } 1890 } 1891 panic("motg_device_ctrl_close: not found"); 1892 } 1893 1894 void 1895 motg_device_ctrl_done(usbd_xfer_handle xfer) 1896 { 1897 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 1898 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1899 KASSERT(otgpipe->hw_ep->xfer != xfer); 1900 } 1901 1902 static usbd_status 1903 motg_device_data_transfer(usbd_xfer_handle xfer) 1904 { 1905 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1906 usbd_status err; 1907 1908 /* Insert last in queue. */ 1909 mutex_enter(&sc->sc_lock); 1910 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1911 xfer, xfer->status)); 1912 err = usb_insert_transfer(xfer); 1913 xfer->status = USBD_NOT_STARTED; 1914 mutex_exit(&sc->sc_lock); 1915 if (err) 1916 return (err); 1917 1918 /* 1919 * Pipe isn't running (otherwise err would be USBD_INPROG), 1920 * so start it first. 1921 */ 1922 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1923 } 1924 1925 static usbd_status 1926 motg_device_data_start(usbd_xfer_handle xfer) 1927 { 1928 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1929 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1930 usbd_status err; 1931 mutex_enter(&sc->sc_lock); 1932 DPRINTF(("motg_device_data_start(%p) status %d\n", 1933 xfer, xfer->status)); 1934 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1935 mutex_exit(&sc->sc_lock); 1936 if (err != USBD_IN_PROGRESS) 1937 return err; 1938 if (sc->sc_bus.use_polling) 1939 motg_waitintr(sc, xfer); 1940 return USBD_IN_PROGRESS; 1941 } 1942 1943 static usbd_status 1944 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1945 { 1946 usbd_xfer_handle xfer = NULL; 1947 struct motg_pipe *otgpipe; 1948 usbd_status err = 0; 1949 uint32_t val __diagused; 1950 1951 KASSERT(mutex_owned(&sc->sc_lock)); 1952 if (sc->sc_dying) 1953 return (USBD_IOERROR); 1954 1955 if (!sc->sc_connected) 1956 return (USBD_IOERROR); 1957 1958 if (ep->xfer != NULL) { 1959 err = USBD_IN_PROGRESS; 1960 goto end; 1961 } 1962 /* locate the first pipe with work to do */ 1963 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1964 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1965 DPRINTFN(MD_BULK, 1966 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1967 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1968 if (xfer != NULL) { 1969 /* move this pipe to the end of the list */ 1970 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1971 motg_pipe, ep_pipe_list); 1972 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1973 otgpipe, ep_pipe_list); 1974 break; 1975 } 1976 } 1977 if (xfer == NULL) { 1978 err = USBD_NOT_STARTED; 1979 goto end; 1980 } 1981 xfer->status = USBD_IN_PROGRESS; 1982 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1983 KASSERT(otgpipe->hw_ep == ep); 1984 #ifdef DIAGNOSTIC 1985 if (xfer->rqflags & URQ_REQUEST) 1986 panic("motg_device_data_transfer: a request"); 1987 #endif 1988 // KASSERT(xfer->actlen == 0); 1989 xfer->actlen = 0; 1990 1991 ep->xfer = xfer; 1992 ep->datalen = xfer->length; 1993 KASSERT(ep->datalen > 0); 1994 ep->data = KERNADDR(&xfer->dmabuf, 0); 1995 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1996 (ep->datalen % 64) == 0) 1997 ep->need_short_xfer = 1; 1998 else 1999 ep->need_short_xfer = 0; 2000 /* now we need send this request */ 2001 DPRINTFN(MD_BULK, 2002 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 2003 xfer, 2004 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 2005 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 2006 xfer->pipe->device->address)); 2007 KASSERT(ep->phase == IDLE); 2008 /* select endpoint */ 2009 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 2010 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 2011 == UE_DIR_IN) { 2012 val = UREAD1(sc, MUSB2_REG_RXCSRL); 2013 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 2014 motg_device_data_read(xfer); 2015 } else { 2016 ep->phase = DATA_OUT; 2017 val = UREAD1(sc, MUSB2_REG_TXCSRL); 2018 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 2019 motg_device_data_write(xfer); 2020 } 2021 end: 2022 if (err) 2023 return (err); 2024 2025 return (USBD_IN_PROGRESS); 2026 } 2027 2028 static void 2029 motg_device_data_read(usbd_xfer_handle xfer) 2030 { 2031 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2032 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2033 uint32_t val; 2034 2035 KASSERT(mutex_owned(&sc->sc_lock)); 2036 /* assume endpoint already selected */ 2037 motg_setup_endpoint_rx(xfer); 2038 /* Max packet size */ 2039 UWRITE2(sc, MUSB2_REG_RXMAXP, 2040 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2041 /* Data Toggle */ 2042 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2043 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2044 if (otgpipe->nexttoggle) 2045 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2046 else 2047 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2048 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2049 2050 DPRINTFN(MD_BULK, 2051 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2052 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2053 /* start transaction */ 2054 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2055 otgpipe->hw_ep->phase = DATA_IN; 2056 } 2057 2058 static void 2059 motg_device_data_write(usbd_xfer_handle xfer) 2060 { 2061 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2062 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2063 struct motg_hw_ep *ep = otgpipe->hw_ep; 2064 int datalen; 2065 char *data; 2066 uint32_t val; 2067 2068 KASSERT(xfer!=NULL); 2069 KASSERT(mutex_owned(&sc->sc_lock)); 2070 2071 datalen = min(ep->datalen, 2072 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2073 ep->phase = DATA_OUT; 2074 DPRINTFN(MD_BULK, 2075 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2076 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2077 2078 /* assume endpoint already selected */ 2079 /* write data to fifo */ 2080 data = ep->data; 2081 ep->data += datalen; 2082 ep->datalen -= datalen; 2083 xfer->actlen += datalen; 2084 if (((vaddr_t)data & 0x3) == 0 && 2085 (datalen >> 2) > 0) { 2086 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2087 MUSB2_REG_EPFIFO(ep->ep_number), 2088 (void *)data, datalen >> 2); 2089 data += (datalen & ~0x3); 2090 datalen -= (datalen & ~0x3); 2091 } 2092 if (datalen) { 2093 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2094 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2095 } 2096 2097 motg_setup_endpoint_tx(xfer); 2098 /* Max packet size */ 2099 UWRITE2(sc, MUSB2_REG_TXMAXP, 2100 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2101 /* Data Toggle */ 2102 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2103 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2104 if (otgpipe->nexttoggle) 2105 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2106 else 2107 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2108 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2109 2110 /* start transaction */ 2111 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2112 } 2113 2114 static void 2115 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2116 { 2117 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2118 usbd_xfer_handle xfer = ep->xfer; 2119 uint8_t csr; 2120 int datalen, max_datalen; 2121 char *data; 2122 bool got_short; 2123 usbd_status new_status = USBD_IN_PROGRESS; 2124 2125 KASSERT(mutex_owned(&sc->sc_lock)); 2126 KASSERT(ep->ep_number == epnumber); 2127 2128 DPRINTFN(MD_BULK, 2129 ("motg_device_intr_rx on ep %d\n", epnumber)); 2130 /* select endpoint */ 2131 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2132 2133 /* read out FIFO status */ 2134 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2135 DPRINTFN(MD_BULK, 2136 ("motg_device_intr_rx phase %d csr 0x%x\n", 2137 ep->phase, csr)); 2138 2139 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2140 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2141 return; 2142 2143 #ifdef DIAGNOSTIC 2144 if (ep->phase != DATA_IN) 2145 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2146 #endif 2147 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2148 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2149 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2150 2151 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2152 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2153 new_status = USBD_TIMEOUT; /* XXX */ 2154 goto complete; 2155 } 2156 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2157 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2158 new_status = USBD_STALLED; 2159 else 2160 new_status = USBD_IOERROR; 2161 /* clear status */ 2162 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2163 goto complete; 2164 } 2165 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2166 2167 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2168 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2169 goto complete; 2170 } 2171 2172 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2173 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2174 2175 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2176 DPRINTFN(MD_BULK, 2177 ("motg_device_intr_rx phase %d datalen %d\n", 2178 ep->phase, datalen)); 2179 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2180 max_datalen = min( 2181 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2182 ep->datalen); 2183 if (datalen > max_datalen) { 2184 new_status = USBD_IOERROR; 2185 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2186 goto complete; 2187 } 2188 got_short = (datalen < max_datalen); 2189 if (datalen > 0) { 2190 KASSERT(ep->phase == DATA_IN); 2191 data = ep->data; 2192 ep->data += datalen; 2193 ep->datalen -= datalen; 2194 xfer->actlen += datalen; 2195 if (((vaddr_t)data & 0x3) == 0 && 2196 (datalen >> 2) > 0) { 2197 DPRINTFN(MD_BULK, 2198 ("motg_device_intr_rx r4 data %p len %d\n", 2199 data, datalen)); 2200 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2201 MUSB2_REG_EPFIFO(ep->ep_number), 2202 (void *)data, datalen >> 2); 2203 data += (datalen & ~0x3); 2204 datalen -= (datalen & ~0x3); 2205 } 2206 DPRINTFN(MD_BULK, 2207 ("motg_device_intr_rx r1 data %p len %d\n", 2208 data, datalen)); 2209 if (datalen) { 2210 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2211 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2212 } 2213 } 2214 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2215 KASSERT(ep->phase == DATA_IN); 2216 if (got_short || (ep->datalen == 0)) { 2217 if (ep->need_short_xfer == 0) { 2218 new_status = USBD_NORMAL_COMPLETION; 2219 goto complete; 2220 } 2221 ep->need_short_xfer = 0; 2222 } 2223 motg_device_data_read(xfer); 2224 return; 2225 complete: 2226 DPRINTFN(MD_BULK, 2227 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2228 (xfer != NULL) ? xfer->status : 0)); 2229 ep->phase = IDLE; 2230 ep->xfer = NULL; 2231 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2232 KASSERT(new_status != USBD_IN_PROGRESS); 2233 xfer->status = new_status; 2234 usb_transfer_complete(xfer); 2235 } 2236 motg_device_data_start1(sc, ep); 2237 } 2238 2239 static void 2240 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2241 { 2242 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2243 usbd_xfer_handle xfer = ep->xfer; 2244 uint8_t csr; 2245 struct motg_pipe *otgpipe; 2246 usbd_status new_status = USBD_IN_PROGRESS; 2247 2248 KASSERT(mutex_owned(&sc->sc_lock)); 2249 KASSERT(ep->ep_number == epnumber); 2250 2251 DPRINTFN(MD_BULK, 2252 ("motg_device_intr_tx on ep %d\n", epnumber)); 2253 /* select endpoint */ 2254 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2255 2256 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2257 DPRINTFN(MD_BULK, 2258 ("motg_device_intr_tx phase %d csr 0x%x\n", 2259 ep->phase, csr)); 2260 2261 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2262 /* command not accepted */ 2263 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2264 new_status = USBD_STALLED; 2265 else 2266 new_status = USBD_IOERROR; 2267 /* clear status */ 2268 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2269 goto complete; 2270 } 2271 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2272 new_status = USBD_TIMEOUT; /* XXX */ 2273 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2274 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2275 /* flush fifo */ 2276 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2277 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2278 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2279 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2280 delay(1000); 2281 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2282 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2283 epnumber, csr)); 2284 } 2285 goto complete; 2286 } 2287 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2288 /* data still not sent */ 2289 return; 2290 } 2291 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2292 goto complete; 2293 #ifdef DIAGNOSTIC 2294 if (ep->phase != DATA_OUT) 2295 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2296 #endif 2297 2298 otgpipe = (struct motg_pipe *)xfer->pipe; 2299 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2300 2301 if (ep->datalen == 0) { 2302 if (ep->need_short_xfer) { 2303 ep->need_short_xfer = 0; 2304 /* one more data phase */ 2305 } else { 2306 new_status = USBD_NORMAL_COMPLETION; 2307 goto complete; 2308 } 2309 } 2310 motg_device_data_write(xfer); 2311 return; 2312 2313 complete: 2314 DPRINTFN(MD_BULK, 2315 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2316 (xfer != NULL) ? xfer->status : 0)); 2317 #ifdef DIAGNOSTIC 2318 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2319 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2320 #endif 2321 ep->phase = IDLE; 2322 ep->xfer = NULL; 2323 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2324 KASSERT(new_status != USBD_IN_PROGRESS); 2325 xfer->status = new_status; 2326 usb_transfer_complete(xfer); 2327 } 2328 motg_device_data_start1(sc, ep); 2329 } 2330 2331 /* Abort a device control request. */ 2332 void 2333 motg_device_data_abort(usbd_xfer_handle xfer) 2334 { 2335 #ifdef DIAGNOSTIC 2336 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2337 #endif 2338 KASSERT(mutex_owned(&sc->sc_lock)); 2339 2340 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2341 motg_device_xfer_abort(xfer); 2342 } 2343 2344 /* Close a device control pipe */ 2345 void 2346 motg_device_data_close(usbd_pipe_handle pipe) 2347 { 2348 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 2349 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2350 struct motg_pipe *otgpipeiter; 2351 2352 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2353 KASSERT(mutex_owned(&sc->sc_lock)); 2354 KASSERT(otgpipe->hw_ep->xfer == NULL || 2355 otgpipe->hw_ep->xfer->pipe != pipe); 2356 2357 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2358 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2359 if (otgpipeiter == otgpipe) { 2360 /* remove from list */ 2361 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2362 motg_pipe, ep_pipe_list); 2363 otgpipe->hw_ep->refcount--; 2364 /* we're done */ 2365 return; 2366 } 2367 } 2368 panic("motg_device_data_close: not found"); 2369 } 2370 2371 void 2372 motg_device_data_done(usbd_xfer_handle xfer) 2373 { 2374 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 2375 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2376 KASSERT(otgpipe->hw_ep->xfer != xfer); 2377 } 2378 2379 /* 2380 * Wait here until controller claims to have an interrupt. 2381 * Then call motg_intr and return. Use timeout to avoid waiting 2382 * too long. 2383 * Only used during boot when interrupts are not enabled yet. 2384 */ 2385 void 2386 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2387 { 2388 int timo = xfer->timeout; 2389 2390 mutex_enter(&sc->sc_lock); 2391 2392 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2393 2394 for (; timo >= 0; timo--) { 2395 mutex_exit(&sc->sc_lock); 2396 usb_delay_ms(&sc->sc_bus, 1); 2397 mutex_spin_enter(&sc->sc_intr_lock); 2398 motg_poll(&sc->sc_bus); 2399 mutex_spin_exit(&sc->sc_intr_lock); 2400 mutex_enter(&sc->sc_lock); 2401 if (xfer->status != USBD_IN_PROGRESS) 2402 goto done; 2403 } 2404 2405 /* Timeout */ 2406 DPRINTF(("motg_waitintr: timeout\n")); 2407 panic("motg_waitintr: timeout"); 2408 /* XXX handle timeout ! */ 2409 2410 done: 2411 mutex_exit(&sc->sc_lock); 2412 } 2413 2414 void 2415 motg_device_clear_toggle(usbd_pipe_handle pipe) 2416 { 2417 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2418 otgpipe->nexttoggle = 0; 2419 } 2420 2421 /* Abort a device control request. */ 2422 static void 2423 motg_device_xfer_abort(usbd_xfer_handle xfer) 2424 { 2425 int wake; 2426 uint8_t csr; 2427 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2428 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2429 KASSERT(mutex_owned(&sc->sc_lock)); 2430 2431 DPRINTF(("motg_device_xfer_abort:\n")); 2432 if (xfer->hcflags & UXFER_ABORTING) { 2433 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2434 xfer->hcflags |= UXFER_ABORTWAIT; 2435 while (xfer->hcflags & UXFER_ABORTING) 2436 cv_wait(&xfer->hccv, &sc->sc_lock); 2437 return; 2438 } 2439 xfer->hcflags |= UXFER_ABORTING; 2440 if (otgpipe->hw_ep->xfer == xfer) { 2441 KASSERT(xfer->status == USBD_IN_PROGRESS); 2442 otgpipe->hw_ep->xfer = NULL; 2443 if (otgpipe->hw_ep->ep_number > 0) { 2444 /* select endpoint */ 2445 UWRITE1(sc, MUSB2_REG_EPINDEX, 2446 otgpipe->hw_ep->ep_number); 2447 if (otgpipe->hw_ep->phase == DATA_OUT) { 2448 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2449 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2450 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2451 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2452 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2453 } 2454 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2455 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2456 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2457 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2458 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2459 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2460 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2461 } 2462 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2463 } 2464 otgpipe->hw_ep->phase = IDLE; 2465 } 2466 } 2467 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2468 wake = xfer->hcflags & UXFER_ABORTWAIT; 2469 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2470 usb_transfer_complete(xfer); 2471 if (wake) 2472 cv_broadcast(&xfer->hccv); 2473 } 2474
Indexes created Wed Sep 24 05:09:52 GMT 2025