motg.c revision 1.12.2.1
1 /* $NetBSD: motg.c,v 1.12.2.1 2014/11/30 12:18:58 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include "opt_motg.h" 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.12.2.1 2014/11/30 12:18:58 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #ifdef MOTG_ALLWINNER 68 #include <arch/arm/allwinner/awin_otgreg.h> 69 #else 70 #include <dev/usb/motgreg.h> 71 #endif 72 73 #include <dev/usb/motgvar.h> 74 #include <dev/usb/usbroothub_subr.h> 75 76 #define MOTG_DEBUG 77 #ifdef MOTG_DEBUG 78 #define DPRINTF(x) if (motgdebug) printf x 79 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 80 #define MD_ROOT 0x0002 81 #define MD_CTRL 0x0004 82 #define MD_BULK 0x0008 83 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 84 int motgdebug = 0; 85 #else 86 #define DPRINTF(x) 87 #define DPRINTFN(n,x) 88 #endif 89 90 /* various timeouts, for various speeds */ 91 /* control NAK timeouts */ 92 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 93 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 94 95 /* intr/iso polling intervals */ 96 #define POLL_TO 100 /* 100 frames, about 0.1s */ 97 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 98 99 /* bulk NAK timeouts */ 100 #define NAK_TO_BULK 0 /* disabled */ 101 #define NAK_TO_BULK_HIGH 0 102 103 static void motg_hub_change(struct motg_softc *); 104 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 105 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 106 static void motg_root_ctrl_abort(usbd_xfer_handle); 107 static void motg_root_ctrl_close(usbd_pipe_handle); 108 static void motg_root_ctrl_done(usbd_xfer_handle); 109 110 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 111 static usbd_status motg_root_intr_start(usbd_xfer_handle); 112 static void motg_root_intr_abort(usbd_xfer_handle); 113 static void motg_root_intr_close(usbd_pipe_handle); 114 static void motg_root_intr_done(usbd_xfer_handle); 115 116 static usbd_status motg_open(usbd_pipe_handle); 117 static void motg_poll(struct usbd_bus *); 118 static void motg_softintr(void *); 119 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 120 static void motg_freem(struct usbd_bus *, usb_dma_t *); 121 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 122 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 123 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 124 static void motg_noop(usbd_pipe_handle pipe); 125 static usbd_status motg_portreset(struct motg_softc*); 126 127 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 128 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 129 static void motg_device_ctrl_abort(usbd_xfer_handle); 130 static void motg_device_ctrl_close(usbd_pipe_handle); 131 static void motg_device_ctrl_done(usbd_xfer_handle); 132 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 133 static void motg_device_ctrl_read(usbd_xfer_handle); 134 static void motg_device_ctrl_intr_rx(struct motg_softc *); 135 static void motg_device_ctrl_intr_tx(struct motg_softc *); 136 137 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 138 static usbd_status motg_device_data_start(usbd_xfer_handle); 139 static usbd_status motg_device_data_start1(struct motg_softc *, 140 struct motg_hw_ep *); 141 static void motg_device_data_abort(usbd_xfer_handle); 142 static void motg_device_data_close(usbd_pipe_handle); 143 static void motg_device_data_done(usbd_xfer_handle); 144 static void motg_device_intr_rx(struct motg_softc *, int); 145 static void motg_device_intr_tx(struct motg_softc *, int); 146 static void motg_device_data_read(usbd_xfer_handle); 147 static void motg_device_data_write(usbd_xfer_handle); 148 149 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 150 static void motg_device_clear_toggle(usbd_pipe_handle); 151 static void motg_device_xfer_abort(usbd_xfer_handle); 152 153 #define MOTG_INTR_ENDPT 1 154 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 155 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 156 #define UWRITE1(sc, r, x) \ 157 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 158 } while (/*CONSTCOND*/0) 159 #define UWRITE2(sc, r, x) \ 160 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 161 } while (/*CONSTCOND*/0) 162 #define UWRITE4(sc, r, x) \ 163 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 164 } while (/*CONSTCOND*/0) 165 166 static __inline uint32_t 167 UREAD1(struct motg_softc *sc, bus_size_t r) 168 { 169 170 UBARR(sc); 171 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 172 } 173 static __inline uint32_t 174 UREAD2(struct motg_softc *sc, bus_size_t r) 175 { 176 177 UBARR(sc); 178 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 179 } 180 181 #if 0 182 static __inline uint32_t 183 UREAD4(struct motg_softc *sc, bus_size_t r) 184 { 185 186 UBARR(sc); 187 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 188 } 189 #endif 190 191 static void 192 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 193 { 194 uint8_t val; 195 196 val = UREAD1(sc, MUSB2_REG_POWER); 197 if (on) 198 val |= MUSB2_MASK_SOFTC; 199 else 200 val &= ~MUSB2_MASK_SOFTC; 201 202 UWRITE1(sc, MUSB2_REG_POWER, val); 203 } 204 205 const struct usbd_bus_methods motg_bus_methods = { 206 .open_pipe = motg_open, 207 .soft_intr = motg_softintr, 208 .do_poll = motg_poll, 209 .allocm = motg_allocm, 210 .freem = motg_freem, 211 .allocx = motg_allocx, 212 .freex = motg_freex, 213 .get_lock = motg_get_lock, 214 .new_device = NULL, 215 }; 216 217 const struct usbd_pipe_methods motg_root_ctrl_methods = { 218 .transfer = motg_root_ctrl_transfer, 219 .start = motg_root_ctrl_start, 220 .abort = motg_root_ctrl_abort, 221 .close = motg_root_ctrl_close, 222 .cleartoggle = motg_noop, 223 .done = motg_root_ctrl_done, 224 }; 225 226 const struct usbd_pipe_methods motg_root_intr_methods = { 227 .transfer = motg_root_intr_transfer, 228 .start = motg_root_intr_start, 229 .abort = motg_root_intr_abort, 230 .close = motg_root_intr_close, 231 .cleartoggle = motg_noop, 232 .done = motg_root_intr_done, 233 }; 234 235 const struct usbd_pipe_methods motg_device_ctrl_methods = { 236 .transfer = motg_device_ctrl_transfer, 237 .start = motg_device_ctrl_start, 238 .abort = motg_device_ctrl_abort, 239 .close = motg_device_ctrl_close, 240 .cleartoggle = motg_noop, 241 .done = motg_device_ctrl_done, 242 }; 243 244 const struct usbd_pipe_methods motg_device_data_methods = { 245 .transfer = motg_device_data_transfer, 246 .start = motg_device_data_start, 247 .abort = motg_device_data_abort, 248 .close = motg_device_data_close, 249 .cleartoggle = motg_device_clear_toggle, 250 .done = motg_device_data_done, 251 }; 252 253 usbd_status 254 motg_init(struct motg_softc *sc) 255 { 256 uint32_t nrx, ntx, val; 257 int dynfifo; 258 int offset, i; 259 260 if (sc->sc_mode == MOTG_MODE_DEVICE) 261 return USBD_NORMAL_COMPLETION; /* not supported */ 262 263 /* disable all interrupts */ 264 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 265 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 266 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 267 /* disable pullup */ 268 269 musbotg_pull_common(sc, 0); 270 271 #ifdef MUSB2_REG_RXDBDIS 272 /* disable double packet buffering XXX what's this ? */ 273 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 274 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 275 #endif 276 277 /* enable HighSpeed and ISO Update flags */ 278 279 UWRITE1(sc, MUSB2_REG_POWER, 280 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 281 282 if (sc->sc_mode == MOTG_MODE_DEVICE) { 283 /* clear Session bit, if set */ 284 val = UREAD1(sc, MUSB2_REG_DEVCTL); 285 val &= ~MUSB2_MASK_SESS; 286 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 287 } else { 288 /* Enter session for Host mode */ 289 val = UREAD1(sc, MUSB2_REG_DEVCTL); 290 val |= MUSB2_MASK_SESS; 291 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 292 } 293 delay(1000); 294 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 295 296 /* disable testmode */ 297 298 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 299 300 #ifdef MUSB2_REG_MISC 301 /* set default value */ 302 303 UWRITE1(sc, MUSB2_REG_MISC, 0); 304 #endif 305 306 /* select endpoint index 0 */ 307 308 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 309 310 if (sc->sc_ep_max == 0) { 311 /* read out number of endpoints */ 312 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 313 314 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 315 316 /* these numbers exclude the control endpoint */ 317 318 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 319 320 sc->sc_ep_max = MAX(nrx, ntx); 321 } else { 322 nrx = ntx = sc->sc_ep_max; 323 } 324 if (sc->sc_ep_max == 0) { 325 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 326 return USBD_INVAL; 327 } 328 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 329 /* read out configuration data */ 330 val = UREAD1(sc, MUSB2_REG_CONFDATA); 331 332 DPRINTF(("Config Data: 0x%02x\n", val)); 333 334 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 335 336 if (dynfifo) { 337 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 338 "assuming 16Kbytes of FIFO RAM\n"); 339 } 340 341 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 342 343 /* initialise endpoint profiles */ 344 sc->sc_in_ep[0].ep_fifo_size = 64; 345 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 346 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 347 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 348 offset = 64; 349 350 for (i = 1; i <= sc->sc_ep_max; i++) { 351 int fiforx_size, fifotx_size, fifo_size; 352 353 /* select endpoint */ 354 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 355 356 if (sc->sc_ep_fifosize) { 357 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 358 } else { 359 val = UREAD1(sc, MUSB2_REG_FSIZE); 360 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 361 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 362 } 363 364 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 365 i, fifotx_size, fiforx_size, dynfifo)); 366 367 if (dynfifo) { 368 if (sc->sc_ep_fifosize) { 369 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 370 } else { 371 if (i < 3) { 372 fifo_size = 12; /* 4K */ 373 } else if (i < 10) { 374 fifo_size = 10; /* 1K */ 375 } else { 376 fifo_size = 7; /* 128 bytes */ 377 } 378 } 379 if (fiforx_size && (i <= nrx)) { 380 fiforx_size = fifo_size; 381 if (fifo_size > 7) { 382 #if 0 383 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 384 MUSB2_VAL_FIFOSZ(fifo_size) | 385 MUSB2_MASK_FIFODB); 386 #else 387 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 388 MUSB2_VAL_FIFOSZ(fifo_size)); 389 #endif 390 } else { 391 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 392 MUSB2_VAL_FIFOSZ(fifo_size)); 393 } 394 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 395 offset >> 3); 396 offset += (1 << fiforx_size); 397 } 398 if (fifotx_size && (i <= ntx)) { 399 fifotx_size = fifo_size; 400 if (fifo_size > 7) { 401 #if 0 402 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size) | 404 MUSB2_MASK_FIFODB); 405 #else 406 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size)); 408 #endif 409 } else { 410 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 411 MUSB2_VAL_FIFOSZ(fifo_size)); 412 } 413 414 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 415 offset >> 3); 416 417 offset += (1 << fifotx_size); 418 } 419 } 420 if (fiforx_size && (i <= nrx)) { 421 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 422 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 423 } 424 if (fifotx_size && (i <= ntx)) { 425 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 426 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 427 } 428 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 429 } 430 431 432 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 433 434 /* turn on default interrupts */ 435 436 if (sc->sc_mode == MOTG_MODE_HOST) { 437 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 438 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 439 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 440 } else 441 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 442 443 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 444 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 445 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 447 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 448 449 /* Set up the bus struct. */ 450 sc->sc_bus.methods = &motg_bus_methods; 451 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 452 sc->sc_bus.usbrev = USBREV_2_0; 453 sc->sc_bus.hci_private = sc; 454 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 455 "Mentor Graphics"); 456 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 457 return USBD_NORMAL_COMPLETION; 458 } 459 460 static int 461 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 462 { 463 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 464 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 465 struct motg_hw_ep *ep; 466 int i, size; 467 468 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 469 sc->sc_in_ep : sc->sc_out_ep; 470 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 471 472 for (i = sc->sc_ep_max; i >= 1; i--) { 473 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 474 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 475 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 476 if (ep[i].ep_fifo_size >= size) { 477 /* found a suitable endpoint */ 478 otgpipe->hw_ep = &ep[i]; 479 mutex_enter(&sc->sc_lock); 480 if (otgpipe->hw_ep->refcount > 0) { 481 /* no luck, try next */ 482 mutex_exit(&sc->sc_lock); 483 otgpipe->hw_ep = NULL; 484 } else { 485 otgpipe->hw_ep->refcount++; 486 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 487 otgpipe, ep_pipe_list); 488 mutex_exit(&sc->sc_lock); 489 return 0; 490 } 491 } 492 } 493 return -1; 494 } 495 496 /* Open a new pipe. */ 497 usbd_status 498 motg_open(usbd_pipe_handle pipe) 499 { 500 struct motg_softc *sc = pipe->device->bus->hci_private; 501 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 502 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 503 504 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 505 pipe, pipe->device->address, 506 ed->bEndpointAddress, sc->sc_root_addr)); 507 508 if (sc->sc_dying) 509 return USBD_IOERROR; 510 511 /* toggle state needed for bulk endpoints */ 512 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 513 514 if (pipe->device->address == sc->sc_root_addr) { 515 switch (ed->bEndpointAddress) { 516 case USB_CONTROL_ENDPOINT: 517 pipe->methods = &motg_root_ctrl_methods; 518 break; 519 case UE_DIR_IN | MOTG_INTR_ENDPT: 520 pipe->methods = &motg_root_intr_methods; 521 break; 522 default: 523 return (USBD_INVAL); 524 } 525 } else { 526 switch (ed->bmAttributes & UE_XFERTYPE) { 527 case UE_CONTROL: 528 pipe->methods = &motg_device_ctrl_methods; 529 /* always use sc_in_ep[0] for in and out */ 530 otgpipe->hw_ep = &sc->sc_in_ep[0]; 531 mutex_enter(&sc->sc_lock); 532 otgpipe->hw_ep->refcount++; 533 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 534 otgpipe, ep_pipe_list); 535 mutex_exit(&sc->sc_lock); 536 break; 537 case UE_BULK: 538 case UE_INTERRUPT: 539 DPRINTFN(MD_BULK, 540 ("new %s %s pipe wMaxPacketSize %d\n", 541 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 542 "bulk" : "interrupt", 543 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 544 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 545 if (motg_select_ep(sc, pipe) != 0) 546 goto bad; 547 KASSERT(otgpipe->hw_ep != NULL); 548 pipe->methods = &motg_device_data_methods; 549 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 550 break; 551 default: 552 goto bad; 553 #ifdef notyet 554 case UE_ISOCHRONOUS: 555 ... 556 break; 557 #endif /* notyet */ 558 } 559 } 560 return (USBD_NORMAL_COMPLETION); 561 562 bad: 563 return (USBD_NOMEM); 564 } 565 566 void 567 motg_softintr(void *v) 568 { 569 struct usbd_bus *bus = v; 570 struct motg_softc *sc = bus->hci_private; 571 uint16_t rx_status, tx_status; 572 uint8_t ctrl_status; 573 uint32_t val; 574 int i; 575 576 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 577 578 DPRINTFN(MD_ROOT | MD_CTRL, 579 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 580 581 mutex_spin_enter(&sc->sc_intr_lock); 582 rx_status = sc->sc_intr_rx_ep; 583 sc->sc_intr_rx_ep = 0; 584 tx_status = sc->sc_intr_tx_ep; 585 sc->sc_intr_tx_ep = 0; 586 ctrl_status = sc->sc_intr_ctrl; 587 sc->sc_intr_ctrl = 0; 588 mutex_spin_exit(&sc->sc_intr_lock); 589 590 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 591 592 if (ctrl_status & (MUSB2_MASK_IRESET | 593 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 594 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 595 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 596 ctrl_status)); 597 598 if (ctrl_status & MUSB2_MASK_IRESET) { 599 sc->sc_isreset = 1; 600 sc->sc_port_suspended = 0; 601 sc->sc_port_suspended_change = 1; 602 sc->sc_connected_changed = 1; 603 sc->sc_port_enabled = 1; 604 605 val = UREAD1(sc, MUSB2_REG_POWER); 606 if (val & MUSB2_MASK_HSMODE) 607 sc->sc_high_speed = 1; 608 else 609 sc->sc_high_speed = 0; 610 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 611 sc->sc_high_speed)); 612 613 /* turn off interrupts */ 614 val = MUSB2_MASK_IRESET; 615 val &= ~MUSB2_MASK_IRESUME; 616 val |= MUSB2_MASK_ISUSP; 617 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 618 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 619 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 620 } 621 if (ctrl_status & MUSB2_MASK_IRESUME) { 622 if (sc->sc_port_suspended) { 623 sc->sc_port_suspended = 0; 624 sc->sc_port_suspended_change = 1; 625 val = UREAD1(sc, MUSB2_REG_INTUSBE); 626 /* disable resume interrupt */ 627 val &= ~MUSB2_MASK_IRESUME; 628 /* enable suspend interrupt */ 629 val |= MUSB2_MASK_ISUSP; 630 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 631 } 632 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 633 if (!sc->sc_port_suspended) { 634 sc->sc_port_suspended = 1; 635 sc->sc_port_suspended_change = 1; 636 637 val = UREAD1(sc, MUSB2_REG_INTUSBE); 638 /* disable suspend interrupt */ 639 val &= ~MUSB2_MASK_ISUSP; 640 /* enable resume interrupt */ 641 val |= MUSB2_MASK_IRESUME; 642 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 643 } 644 } 645 if (ctrl_status & MUSB2_MASK_ICONN) { 646 sc->sc_connected = 1; 647 sc->sc_connected_changed = 1; 648 sc->sc_isreset = 1; 649 sc->sc_port_enabled = 1; 650 } else if (ctrl_status & MUSB2_MASK_IDISC) { 651 sc->sc_connected = 0; 652 sc->sc_connected_changed = 1; 653 sc->sc_isreset = 0; 654 sc->sc_port_enabled = 0; 655 } 656 657 /* complete root HUB interrupt endpoint */ 658 659 motg_hub_change(sc); 660 } 661 /* 662 * read in interrupt status and mix with the status we 663 * got from the wrapper 664 */ 665 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 666 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 667 668 if (rx_status & 0x01) 669 panic("ctrl_rx %08x", rx_status); 670 if (tx_status & 0x01) 671 motg_device_ctrl_intr_tx(sc); 672 for (i = 1; i <= sc->sc_ep_max; i++) { 673 if (rx_status & (0x01 << i)) 674 motg_device_intr_rx(sc, i); 675 if (tx_status & (0x01 << i)) 676 motg_device_intr_tx(sc, i); 677 } 678 return; 679 } 680 681 void 682 motg_poll(struct usbd_bus *bus) 683 { 684 struct motg_softc *sc = bus->hci_private; 685 686 sc->sc_intr_poll(sc->sc_intr_poll_arg); 687 mutex_enter(&sc->sc_lock); 688 motg_softintr(bus); 689 mutex_exit(&sc->sc_lock); 690 } 691 692 int 693 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 694 uint8_t ctrl) 695 { 696 KASSERT(mutex_owned(&sc->sc_intr_lock)); 697 sc->sc_intr_tx_ep = tx_ep; 698 sc->sc_intr_rx_ep = rx_ep; 699 sc->sc_intr_ctrl = ctrl; 700 701 if (!sc->sc_bus.use_polling) { 702 sc->sc_bus.no_intrs++; 703 usb_schedsoftintr(&sc->sc_bus); 704 } 705 return 1; 706 } 707 708 int 709 motg_intr_vbus(struct motg_softc *sc, int vbus) 710 { 711 uint8_t val; 712 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 713 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 714 /* try to re-enter session for Host mode */ 715 val = UREAD1(sc, MUSB2_REG_DEVCTL); 716 val |= MUSB2_MASK_SESS; 717 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 718 } 719 return 1; 720 } 721 722 usbd_status 723 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 724 { 725 struct motg_softc *sc = bus->hci_private; 726 usbd_status status; 727 728 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 729 if (status == USBD_NOMEM) 730 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 731 return status; 732 } 733 734 void 735 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 736 { 737 if (dma->block->flags & USB_DMA_RESERVE) { 738 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 739 dma); 740 return; 741 } 742 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 743 } 744 745 usbd_xfer_handle 746 motg_allocx(struct usbd_bus *bus) 747 { 748 struct motg_softc *sc = bus->hci_private; 749 usbd_xfer_handle xfer; 750 751 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 752 if (xfer != NULL) { 753 memset(xfer, 0, sizeof(struct motg_xfer)); 754 UXFER(xfer)->sc = sc; 755 #ifdef DIAGNOSTIC 756 // XXX UXFER(xfer)->iinfo.isdone = 1; 757 xfer->busy_free = XFER_BUSY; 758 #endif 759 } 760 return (xfer); 761 } 762 763 void 764 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 765 { 766 struct motg_softc *sc = bus->hci_private; 767 768 #ifdef DIAGNOSTIC 769 if (xfer->busy_free != XFER_BUSY) { 770 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 771 xfer->busy_free); 772 } 773 xfer->busy_free = XFER_FREE; 774 #endif 775 pool_cache_put(sc->sc_xferpool, xfer); 776 } 777 778 static void 779 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 780 { 781 struct motg_softc *sc = bus->hci_private; 782 783 *lock = &sc->sc_lock; 784 } 785 786 /* 787 * Data structures and routines to emulate the root hub. 788 */ 789 usb_device_descriptor_t motg_devd = { 790 USB_DEVICE_DESCRIPTOR_SIZE, 791 UDESC_DEVICE, /* type */ 792 {0x00, 0x01}, /* USB version */ 793 UDCLASS_HUB, /* class */ 794 UDSUBCLASS_HUB, /* subclass */ 795 UDPROTO_FSHUB, /* protocol */ 796 64, /* max packet */ 797 {0},{0},{0x00,0x01}, /* device id */ 798 1,2,0, /* string indicies */ 799 1 /* # of configurations */ 800 }; 801 802 const usb_config_descriptor_t motg_confd = { 803 USB_CONFIG_DESCRIPTOR_SIZE, 804 UDESC_CONFIG, 805 {USB_CONFIG_DESCRIPTOR_SIZE + 806 USB_INTERFACE_DESCRIPTOR_SIZE + 807 USB_ENDPOINT_DESCRIPTOR_SIZE}, 808 1, 809 1, 810 0, 811 UC_ATTR_MBO | UC_SELF_POWERED, 812 0 /* max power */ 813 }; 814 815 const usb_interface_descriptor_t motg_ifcd = { 816 USB_INTERFACE_DESCRIPTOR_SIZE, 817 UDESC_INTERFACE, 818 0, 819 0, 820 1, 821 UICLASS_HUB, 822 UISUBCLASS_HUB, 823 UIPROTO_FSHUB, 824 0 825 }; 826 827 const usb_endpoint_descriptor_t motg_endpd = { 828 USB_ENDPOINT_DESCRIPTOR_SIZE, 829 UDESC_ENDPOINT, 830 UE_DIR_IN | MOTG_INTR_ENDPT, 831 UE_INTERRUPT, 832 {8}, 833 255 834 }; 835 836 const usb_hub_descriptor_t motg_hubd = { 837 USB_HUB_DESCRIPTOR_SIZE, 838 UDESC_HUB, 839 1, 840 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 841 50, /* power on to power good */ 842 0, 843 { 0x00 }, /* port is removable */ 844 { 0 }, 845 }; 846 847 /* 848 * Simulate a hardware hub by handling all the necessary requests. 849 */ 850 usbd_status 851 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 852 { 853 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 854 usbd_status err; 855 856 /* Insert last in queue. */ 857 mutex_enter(&sc->sc_lock); 858 err = usb_insert_transfer(xfer); 859 mutex_exit(&sc->sc_lock); 860 if (err) 861 return (err); 862 863 /* 864 * Pipe isn't running (otherwise err would be USBD_INPROG), 865 * so start it first. 866 */ 867 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 868 } 869 870 usbd_status 871 motg_root_ctrl_start(usbd_xfer_handle xfer) 872 { 873 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 874 usb_device_request_t *req; 875 void *buf = NULL; 876 int len, value, index, status, change, l, totlen = 0; 877 usb_port_status_t ps; 878 usbd_status err; 879 uint32_t val; 880 881 if (sc->sc_dying) 882 return (USBD_IOERROR); 883 884 #ifdef DIAGNOSTIC 885 if (!(xfer->rqflags & URQ_REQUEST)) 886 panic("motg_root_ctrl_start: not a request"); 887 #endif 888 req = &xfer->request; 889 890 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 891 req->bmRequestType, req->bRequest)); 892 893 len = UGETW(req->wLength); 894 value = UGETW(req->wValue); 895 index = UGETW(req->wIndex); 896 897 if (len != 0) 898 buf = KERNADDR(&xfer->dmabuf, 0); 899 900 #define C(x,y) ((x) | ((y) << 8)) 901 switch(C(req->bRequest, req->bmRequestType)) { 902 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 903 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 904 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 905 /* 906 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 907 * for the integrated root hub. 908 */ 909 break; 910 case C(UR_GET_CONFIG, UT_READ_DEVICE): 911 if (len > 0) { 912 *(uint8_t *)buf = sc->sc_root_conf; 913 totlen = 1; 914 } 915 break; 916 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 917 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 918 if (len == 0) 919 break; 920 switch(value >> 8) { 921 case UDESC_DEVICE: 922 if ((value & 0xff) != 0) { 923 err = USBD_IOERROR; 924 goto ret; 925 } 926 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 927 USETW(motg_devd.idVendor, sc->sc_id_vendor); 928 memcpy(buf, &motg_devd, l); 929 break; 930 case UDESC_CONFIG: 931 if ((value & 0xff) != 0) { 932 err = USBD_IOERROR; 933 goto ret; 934 } 935 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 936 memcpy(buf, &motg_confd, l); 937 buf = (char *)buf + l; 938 len -= l; 939 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 940 totlen += l; 941 memcpy(buf, &motg_ifcd, l); 942 buf = (char *)buf + l; 943 len -= l; 944 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 945 totlen += l; 946 memcpy(buf, &motg_endpd, l); 947 break; 948 case UDESC_STRING: 949 #define sd ((usb_string_descriptor_t *)buf) 950 switch (value & 0xff) { 951 case 0: /* Language table */ 952 totlen = usb_makelangtbl(sd, len); 953 break; 954 case 1: /* Vendor */ 955 totlen = usb_makestrdesc(sd, len, 956 sc->sc_vendor); 957 break; 958 case 2: /* Product */ 959 totlen = usb_makestrdesc(sd, len, 960 "MOTG root hub"); 961 break; 962 } 963 #undef sd 964 break; 965 default: 966 err = USBD_IOERROR; 967 goto ret; 968 } 969 break; 970 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 971 if (len > 0) { 972 *(uint8_t *)buf = 0; 973 totlen = 1; 974 } 975 break; 976 case C(UR_GET_STATUS, UT_READ_DEVICE): 977 if (len > 1) { 978 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 979 totlen = 2; 980 } 981 break; 982 case C(UR_GET_STATUS, UT_READ_INTERFACE): 983 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 984 if (len > 1) { 985 USETW(((usb_status_t *)buf)->wStatus, 0); 986 totlen = 2; 987 } 988 break; 989 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 990 if (value >= USB_MAX_DEVICES) { 991 err = USBD_IOERROR; 992 goto ret; 993 } 994 sc->sc_root_addr = value; 995 break; 996 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 997 if (value != 0 && value != 1) { 998 err = USBD_IOERROR; 999 goto ret; 1000 } 1001 sc->sc_root_conf = value; 1002 break; 1003 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1004 break; 1005 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1006 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1007 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1008 err = USBD_IOERROR; 1009 goto ret; 1010 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1011 break; 1012 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1013 break; 1014 /* Hub requests */ 1015 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1016 break; 1017 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1018 DPRINTFN(MD_ROOT, 1019 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1020 "port=%d feature=%d\n", 1021 index, value)); 1022 if (index != 1) { 1023 err = USBD_IOERROR; 1024 goto ret; 1025 } 1026 switch(value) { 1027 case UHF_PORT_ENABLE: 1028 sc->sc_port_enabled = 0; 1029 break; 1030 case UHF_PORT_SUSPEND: 1031 if (sc->sc_port_suspended != 0) { 1032 val = UREAD1(sc, MUSB2_REG_POWER); 1033 val &= ~MUSB2_MASK_SUSPMODE; 1034 val |= MUSB2_MASK_RESUME; 1035 UWRITE1(sc, MUSB2_REG_POWER, val); 1036 /* wait 20 milliseconds */ 1037 usb_delay_ms(&sc->sc_bus, 20); 1038 val = UREAD1(sc, MUSB2_REG_POWER); 1039 val &= ~MUSB2_MASK_RESUME; 1040 UWRITE1(sc, MUSB2_REG_POWER, val); 1041 sc->sc_port_suspended = 0; 1042 sc->sc_port_suspended_change = 1; 1043 } 1044 break; 1045 case UHF_PORT_RESET: 1046 break; 1047 case UHF_C_PORT_CONNECTION: 1048 break; 1049 case UHF_C_PORT_ENABLE: 1050 break; 1051 case UHF_C_PORT_OVER_CURRENT: 1052 break; 1053 case UHF_C_PORT_RESET: 1054 sc->sc_isreset = 0; 1055 err = USBD_NORMAL_COMPLETION; 1056 goto ret; 1057 case UHF_PORT_POWER: 1058 /* XXX todo */ 1059 break; 1060 case UHF_PORT_CONNECTION: 1061 case UHF_PORT_OVER_CURRENT: 1062 case UHF_PORT_LOW_SPEED: 1063 case UHF_C_PORT_SUSPEND: 1064 default: 1065 err = USBD_IOERROR; 1066 goto ret; 1067 } 1068 break; 1069 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1070 err = USBD_IOERROR; 1071 goto ret; 1072 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1073 if (len == 0) 1074 break; 1075 if ((value & 0xff) != 0) { 1076 err = USBD_IOERROR; 1077 goto ret; 1078 } 1079 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1080 totlen = l; 1081 memcpy(buf, &motg_hubd, l); 1082 break; 1083 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1084 if (len != 4) { 1085 err = USBD_IOERROR; 1086 goto ret; 1087 } 1088 memset(buf, 0, len); 1089 totlen = len; 1090 break; 1091 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1092 if (index != 1) { 1093 err = USBD_IOERROR; 1094 goto ret; 1095 } 1096 if (len != 4) { 1097 err = USBD_IOERROR; 1098 goto ret; 1099 } 1100 status = change = 0; 1101 if (sc->sc_connected) 1102 status |= UPS_CURRENT_CONNECT_STATUS; 1103 if (sc->sc_connected_changed) { 1104 change |= UPS_C_CONNECT_STATUS; 1105 sc->sc_connected_changed = 0; 1106 } 1107 if (sc->sc_port_enabled) 1108 status |= UPS_PORT_ENABLED; 1109 if (sc->sc_port_enabled_changed) { 1110 change |= UPS_C_PORT_ENABLED; 1111 sc->sc_port_enabled_changed = 0; 1112 } 1113 if (sc->sc_port_suspended) 1114 status |= UPS_SUSPEND; 1115 if (sc->sc_high_speed) 1116 status |= UPS_HIGH_SPEED; 1117 status |= UPS_PORT_POWER; /* XXX */ 1118 if (sc->sc_isreset) 1119 change |= UPS_C_PORT_RESET; 1120 USETW(ps.wPortStatus, status); 1121 USETW(ps.wPortChange, change); 1122 l = min(len, sizeof ps); 1123 memcpy(buf, &ps, l); 1124 totlen = l; 1125 break; 1126 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1127 err = USBD_IOERROR; 1128 goto ret; 1129 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1130 break; 1131 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1132 if (index != 1) { 1133 err = USBD_IOERROR; 1134 goto ret; 1135 } 1136 switch(value) { 1137 case UHF_PORT_ENABLE: 1138 sc->sc_port_enabled = 1; 1139 break; 1140 case UHF_PORT_SUSPEND: 1141 if (sc->sc_port_suspended == 0) { 1142 val = UREAD1(sc, MUSB2_REG_POWER); 1143 val |= MUSB2_MASK_SUSPMODE; 1144 UWRITE1(sc, MUSB2_REG_POWER, val); 1145 /* wait 20 milliseconds */ 1146 usb_delay_ms(&sc->sc_bus, 20); 1147 sc->sc_port_suspended = 1; 1148 sc->sc_port_suspended_change = 1; 1149 } 1150 break; 1151 case UHF_PORT_RESET: 1152 err = motg_portreset(sc); 1153 goto ret; 1154 case UHF_PORT_POWER: 1155 /* XXX todo */ 1156 err = USBD_NORMAL_COMPLETION; 1157 goto ret; 1158 case UHF_C_PORT_CONNECTION: 1159 case UHF_C_PORT_ENABLE: 1160 case UHF_C_PORT_OVER_CURRENT: 1161 case UHF_PORT_CONNECTION: 1162 case UHF_PORT_OVER_CURRENT: 1163 case UHF_PORT_LOW_SPEED: 1164 case UHF_C_PORT_SUSPEND: 1165 case UHF_C_PORT_RESET: 1166 default: 1167 err = USBD_IOERROR; 1168 goto ret; 1169 } 1170 break; 1171 default: 1172 err = USBD_IOERROR; 1173 goto ret; 1174 } 1175 xfer->actlen = totlen; 1176 err = USBD_NORMAL_COMPLETION; 1177 ret: 1178 xfer->status = err; 1179 mutex_enter(&sc->sc_lock); 1180 usb_transfer_complete(xfer); 1181 mutex_exit(&sc->sc_lock); 1182 return (USBD_IN_PROGRESS); 1183 } 1184 1185 /* Abort a root control request. */ 1186 void 1187 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1188 { 1189 /* Nothing to do, all transfers are synchronous. */ 1190 } 1191 1192 /* Close the root pipe. */ 1193 void 1194 motg_root_ctrl_close(usbd_pipe_handle pipe) 1195 { 1196 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1197 } 1198 1199 void 1200 motg_root_ctrl_done(usbd_xfer_handle xfer) 1201 { 1202 } 1203 1204 /* Abort a root interrupt request. */ 1205 void 1206 motg_root_intr_abort(usbd_xfer_handle xfer) 1207 { 1208 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1209 1210 KASSERT(mutex_owned(&sc->sc_lock)); 1211 KASSERT(xfer->pipe->intrxfer == xfer); 1212 1213 sc->sc_intr_xfer = NULL; 1214 1215 #ifdef DIAGNOSTIC 1216 // XXX UXFER(xfer)->iinfo.isdone = 1; 1217 #endif 1218 xfer->status = USBD_CANCELLED; 1219 usb_transfer_complete(xfer); 1220 } 1221 1222 usbd_status 1223 motg_root_intr_transfer(usbd_xfer_handle xfer) 1224 { 1225 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1226 usbd_status err; 1227 1228 /* Insert last in queue. */ 1229 mutex_enter(&sc->sc_lock); 1230 err = usb_insert_transfer(xfer); 1231 mutex_exit(&sc->sc_lock); 1232 if (err) 1233 return (err); 1234 1235 /* 1236 * Pipe isn't running (otherwise err would be USBD_INPROG), 1237 * start first 1238 */ 1239 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1240 } 1241 1242 /* Start a transfer on the root interrupt pipe */ 1243 usbd_status 1244 motg_root_intr_start(usbd_xfer_handle xfer) 1245 { 1246 usbd_pipe_handle pipe = xfer->pipe; 1247 struct motg_softc *sc = pipe->device->bus->hci_private; 1248 1249 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1250 xfer, xfer->length, xfer->flags)); 1251 1252 if (sc->sc_dying) 1253 return (USBD_IOERROR); 1254 1255 sc->sc_intr_xfer = xfer; 1256 return (USBD_IN_PROGRESS); 1257 } 1258 1259 /* Close the root interrupt pipe. */ 1260 void 1261 motg_root_intr_close(usbd_pipe_handle pipe) 1262 { 1263 struct motg_softc *sc = pipe->device->bus->hci_private; 1264 1265 KASSERT(mutex_owned(&sc->sc_lock)); 1266 1267 sc->sc_intr_xfer = NULL; 1268 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1269 } 1270 1271 void 1272 motg_root_intr_done(usbd_xfer_handle xfer) 1273 { 1274 } 1275 1276 void 1277 motg_noop(usbd_pipe_handle pipe) 1278 { 1279 } 1280 1281 static usbd_status 1282 motg_portreset(struct motg_softc *sc) 1283 { 1284 uint32_t val; 1285 1286 val = UREAD1(sc, MUSB2_REG_POWER); 1287 val |= MUSB2_MASK_RESET; 1288 UWRITE1(sc, MUSB2_REG_POWER, val); 1289 /* Wait for 20 msec */ 1290 usb_delay_ms(&sc->sc_bus, 20); 1291 1292 val = UREAD1(sc, MUSB2_REG_POWER); 1293 val &= ~MUSB2_MASK_RESET; 1294 UWRITE1(sc, MUSB2_REG_POWER, val); 1295 1296 /* determine line speed */ 1297 val = UREAD1(sc, MUSB2_REG_POWER); 1298 if (val & MUSB2_MASK_HSMODE) 1299 sc->sc_high_speed = 1; 1300 else 1301 sc->sc_high_speed = 0; 1302 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1303 sc->sc_high_speed)); 1304 1305 sc->sc_isreset = 1; 1306 sc->sc_port_enabled = 1; 1307 return (USBD_NORMAL_COMPLETION); 1308 } 1309 1310 /* 1311 * This routine is executed when an interrupt on the root hub is detected 1312 */ 1313 static void 1314 motg_hub_change(struct motg_softc *sc) 1315 { 1316 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1317 usbd_pipe_handle pipe; 1318 u_char *p; 1319 1320 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1321 1322 if (xfer == NULL) 1323 return; /* the interrupt pipe is not open */ 1324 1325 pipe = xfer->pipe; 1326 if (pipe->device == NULL || pipe->device->bus == NULL) 1327 return; /* device has detached */ 1328 1329 p = KERNADDR(&xfer->dmabuf, 0); 1330 p[0] = 1<<1; 1331 xfer->actlen = 1; 1332 xfer->status = USBD_NORMAL_COMPLETION; 1333 usb_transfer_complete(xfer); 1334 } 1335 1336 static uint8_t 1337 motg_speed(uint8_t speed) 1338 { 1339 switch(speed) { 1340 case USB_SPEED_LOW: 1341 return MUSB2_MASK_TI_SPEED_LO; 1342 case USB_SPEED_FULL: 1343 return MUSB2_MASK_TI_SPEED_FS; 1344 case USB_SPEED_HIGH: 1345 return MUSB2_MASK_TI_SPEED_HS; 1346 default: 1347 panic("motg: unknown speed %d", speed); 1348 /* NOTREACHED */ 1349 } 1350 } 1351 1352 static uint8_t 1353 motg_type(uint8_t type) 1354 { 1355 switch(type) { 1356 case UE_CONTROL: 1357 return MUSB2_MASK_TI_PROTO_CTRL; 1358 case UE_ISOCHRONOUS: 1359 return MUSB2_MASK_TI_PROTO_ISOC; 1360 case UE_BULK: 1361 return MUSB2_MASK_TI_PROTO_BULK; 1362 case UE_INTERRUPT: 1363 return MUSB2_MASK_TI_PROTO_INTR; 1364 default: 1365 panic("motg: unknown type %d", type); 1366 /* NOTREACHED */ 1367 } 1368 } 1369 1370 static void 1371 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1372 { 1373 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1374 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1375 usbd_device_handle dev = otgpipe->pipe.device; 1376 int epnumber = otgpipe->hw_ep->ep_number; 1377 1378 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1379 if (dev->myhsport) { 1380 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1381 dev->myhsport->parent->address); 1382 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1383 dev->myhsport->portno); 1384 } else { 1385 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1386 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1387 } 1388 UWRITE1(sc, MUSB2_REG_TXTI, 1389 motg_speed(dev->speed) | 1390 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1391 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1392 ); 1393 if (epnumber == 0) { 1394 if (sc->sc_high_speed) { 1395 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1396 NAK_TO_CTRL_HIGH); 1397 } else { 1398 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1399 } 1400 } else { 1401 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1402 == UE_BULK) { 1403 if (sc->sc_high_speed) { 1404 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1405 NAK_TO_BULK_HIGH); 1406 } else { 1407 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1408 } 1409 } else { 1410 if (sc->sc_high_speed) { 1411 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1412 } else { 1413 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1414 } 1415 } 1416 } 1417 } 1418 1419 static void 1420 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1421 { 1422 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1423 usbd_device_handle dev = xfer->pipe->device; 1424 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1425 int epnumber = otgpipe->hw_ep->ep_number; 1426 1427 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1428 if (dev->myhsport) { 1429 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1430 dev->myhsport->parent->address); 1431 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1432 dev->myhsport->portno); 1433 } else { 1434 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1435 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1436 } 1437 UWRITE1(sc, MUSB2_REG_RXTI, 1438 motg_speed(dev->speed) | 1439 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1440 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1441 ); 1442 if (epnumber == 0) { 1443 if (sc->sc_high_speed) { 1444 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1445 NAK_TO_CTRL_HIGH); 1446 } else { 1447 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1448 } 1449 } else { 1450 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1451 == UE_BULK) { 1452 if (sc->sc_high_speed) { 1453 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1454 NAK_TO_BULK_HIGH); 1455 } else { 1456 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1457 } 1458 } else { 1459 if (sc->sc_high_speed) { 1460 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1461 } else { 1462 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1463 } 1464 } 1465 } 1466 } 1467 1468 static usbd_status 1469 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1470 { 1471 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1472 usbd_status err; 1473 1474 /* Insert last in queue. */ 1475 mutex_enter(&sc->sc_lock); 1476 err = usb_insert_transfer(xfer); 1477 xfer->status = USBD_NOT_STARTED; 1478 mutex_exit(&sc->sc_lock); 1479 if (err) 1480 return (err); 1481 1482 /* 1483 * Pipe isn't running (otherwise err would be USBD_INPROG), 1484 * so start it first. 1485 */ 1486 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1487 } 1488 1489 static usbd_status 1490 motg_device_ctrl_start(usbd_xfer_handle xfer) 1491 { 1492 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1493 usbd_status err; 1494 mutex_enter(&sc->sc_lock); 1495 err = motg_device_ctrl_start1(sc); 1496 mutex_exit(&sc->sc_lock); 1497 if (err != USBD_IN_PROGRESS) 1498 return err; 1499 if (sc->sc_bus.use_polling) 1500 motg_waitintr(sc, xfer); 1501 return USBD_IN_PROGRESS; 1502 } 1503 1504 static usbd_status 1505 motg_device_ctrl_start1(struct motg_softc *sc) 1506 { 1507 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1508 usbd_xfer_handle xfer = NULL; 1509 struct motg_pipe *otgpipe; 1510 usbd_status err = 0; 1511 1512 KASSERT(mutex_owned(&sc->sc_lock)); 1513 if (sc->sc_dying) 1514 return (USBD_IOERROR); 1515 1516 if (!sc->sc_connected) 1517 return (USBD_IOERROR); 1518 1519 if (ep->xfer != NULL) { 1520 err = USBD_IN_PROGRESS; 1521 goto end; 1522 } 1523 /* locate the first pipe with work to do */ 1524 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1525 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1526 DPRINTFN(MD_CTRL, 1527 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1528 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1529 1530 if (xfer != NULL) { 1531 /* move this pipe to the end of the list */ 1532 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1533 motg_pipe, ep_pipe_list); 1534 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1535 otgpipe, ep_pipe_list); 1536 break; 1537 } 1538 } 1539 if (xfer == NULL) { 1540 err = USBD_NOT_STARTED; 1541 goto end; 1542 } 1543 xfer->status = USBD_IN_PROGRESS; 1544 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1545 KASSERT(otgpipe->hw_ep == ep); 1546 #ifdef DIAGNOSTIC 1547 if (!(xfer->rqflags & URQ_REQUEST)) 1548 panic("motg_device_ctrl_transfer: not a request"); 1549 #endif 1550 // KASSERT(xfer->actlen == 0); 1551 xfer->actlen = 0; 1552 1553 ep->xfer = xfer; 1554 ep->datalen = xfer->length; 1555 if (ep->datalen > 0) 1556 ep->data = KERNADDR(&xfer->dmabuf, 0); 1557 else 1558 ep->data = NULL; 1559 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1560 (ep->datalen % 64) == 0) 1561 ep->need_short_xfer = 1; 1562 else 1563 ep->need_short_xfer = 0; 1564 /* now we need send this request */ 1565 DPRINTFN(MD_CTRL, 1566 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1567 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1568 xfer->pipe->device->address)); 1569 KASSERT(ep->phase == IDLE); 1570 ep->phase = SETUP; 1571 /* select endpoint 0 */ 1572 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1573 /* fifo should be empty at this point */ 1574 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1575 /* send data */ 1576 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1577 KASSERT(sizeof(xfer->request) == 8); 1578 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1579 (void *)&xfer->request, sizeof(xfer->request)); 1580 1581 motg_setup_endpoint_tx(xfer); 1582 /* start transaction */ 1583 UWRITE1(sc, MUSB2_REG_TXCSRL, 1584 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1585 1586 end: 1587 if (err) 1588 return (err); 1589 1590 return (USBD_IN_PROGRESS); 1591 } 1592 1593 static void 1594 motg_device_ctrl_read(usbd_xfer_handle xfer) 1595 { 1596 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1597 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1598 /* assume endpoint already selected */ 1599 motg_setup_endpoint_rx(xfer); 1600 /* start transaction */ 1601 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1602 otgpipe->hw_ep->phase = DATA_IN; 1603 } 1604 1605 static void 1606 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1607 { 1608 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1609 usbd_xfer_handle xfer = ep->xfer; 1610 uint8_t csr; 1611 int datalen, max_datalen; 1612 char *data; 1613 bool got_short; 1614 usbd_status new_status = USBD_IN_PROGRESS; 1615 1616 KASSERT(mutex_owned(&sc->sc_lock)); 1617 1618 #ifdef DIAGNOSTIC 1619 if (ep->phase != DATA_IN && 1620 ep->phase != STATUS_IN) 1621 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1622 #endif 1623 /* select endpoint 0 */ 1624 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1625 1626 /* read out FIFO status */ 1627 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1628 DPRINTFN(MD_CTRL, 1629 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1630 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1631 1632 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1633 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1634 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1635 1636 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1637 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1638 new_status = USBD_TIMEOUT; /* XXX */ 1639 goto complete; 1640 } 1641 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1642 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1643 new_status = USBD_STALLED; 1644 else 1645 new_status = USBD_IOERROR; 1646 /* clear status */ 1647 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1648 goto complete; 1649 } 1650 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1651 return; /* no data yet */ 1652 1653 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1654 goto complete; 1655 1656 if (ep->phase == STATUS_IN) { 1657 new_status = USBD_NORMAL_COMPLETION; 1658 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1659 goto complete; 1660 } 1661 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1662 DPRINTFN(MD_CTRL, 1663 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1664 ep->phase, datalen)); 1665 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1666 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1667 ep->datalen); 1668 if (datalen > max_datalen) { 1669 new_status = USBD_IOERROR; 1670 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1671 goto complete; 1672 } 1673 got_short = (datalen < max_datalen); 1674 if (datalen > 0) { 1675 KASSERT(ep->phase == DATA_IN); 1676 data = ep->data; 1677 ep->data += datalen; 1678 ep->datalen -= datalen; 1679 xfer->actlen += datalen; 1680 if (((vaddr_t)data & 0x3) == 0 && 1681 (datalen >> 2) > 0) { 1682 DPRINTFN(MD_CTRL, 1683 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1684 data, datalen)); 1685 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1686 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1687 data += (datalen & ~0x3); 1688 datalen -= (datalen & ~0x3); 1689 } 1690 DPRINTFN(MD_CTRL, 1691 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1692 data, datalen)); 1693 if (datalen) { 1694 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1695 MUSB2_REG_EPFIFO(0), data, datalen); 1696 } 1697 } 1698 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1699 KASSERT(ep->phase == DATA_IN); 1700 if (got_short || (ep->datalen == 0)) { 1701 if (ep->need_short_xfer == 0) { 1702 ep->phase = STATUS_OUT; 1703 UWRITE1(sc, MUSB2_REG_TXCSRH, 1704 UREAD1(sc, MUSB2_REG_TXCSRH) | 1705 MUSB2_MASK_CSR0H_PING_DIS); 1706 motg_setup_endpoint_tx(xfer); 1707 UWRITE1(sc, MUSB2_REG_TXCSRL, 1708 MUSB2_MASK_CSR0L_STATUSPKT | 1709 MUSB2_MASK_CSR0L_TXPKTRDY); 1710 return; 1711 } 1712 ep->need_short_xfer = 0; 1713 } 1714 motg_device_ctrl_read(xfer); 1715 return; 1716 complete: 1717 ep->phase = IDLE; 1718 ep->xfer = NULL; 1719 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1720 KASSERT(new_status != USBD_IN_PROGRESS); 1721 xfer->status = new_status; 1722 usb_transfer_complete(xfer); 1723 } 1724 motg_device_ctrl_start1(sc); 1725 } 1726 1727 static void 1728 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1729 { 1730 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1731 usbd_xfer_handle xfer = ep->xfer; 1732 uint8_t csr; 1733 int datalen; 1734 char *data; 1735 usbd_status new_status = USBD_IN_PROGRESS; 1736 1737 KASSERT(mutex_owned(&sc->sc_lock)); 1738 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1739 motg_device_ctrl_intr_rx(sc); 1740 return; 1741 } 1742 1743 #ifdef DIAGNOSTIC 1744 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1745 ep->phase != STATUS_OUT) 1746 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1747 #endif 1748 /* select endpoint 0 */ 1749 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1750 1751 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1752 DPRINTFN(MD_CTRL, 1753 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1754 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1755 1756 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1757 /* command not accepted */ 1758 new_status = USBD_STALLED; 1759 /* clear status */ 1760 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1761 goto complete; 1762 } 1763 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1764 new_status = USBD_TIMEOUT; /* XXX */ 1765 /* flush fifo */ 1766 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1767 UWRITE1(sc, MUSB2_REG_TXCSRH, 1768 UREAD1(sc, MUSB2_REG_TXCSRH) | 1769 MUSB2_MASK_CSR0H_FFLUSH); 1770 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1771 } 1772 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1773 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1774 goto complete; 1775 } 1776 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1777 new_status = USBD_IOERROR; 1778 /* clear status */ 1779 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1780 goto complete; 1781 } 1782 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1783 /* data still not sent */ 1784 return; 1785 } 1786 if (xfer == NULL) 1787 goto complete; 1788 if (ep->phase == STATUS_OUT) { 1789 /* 1790 * we have sent status and got no error; 1791 * declare transfer complete 1792 */ 1793 DPRINTFN(MD_CTRL, 1794 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1795 xfer, xfer->status)); 1796 new_status = USBD_NORMAL_COMPLETION; 1797 goto complete; 1798 } 1799 if (ep->datalen == 0) { 1800 if (ep->need_short_xfer) { 1801 ep->need_short_xfer = 0; 1802 /* one more data phase */ 1803 if (xfer->request.bmRequestType & UT_READ) { 1804 DPRINTFN(MD_CTRL, 1805 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1806 motg_device_ctrl_read(xfer); 1807 return; 1808 } /* else fall back to DATA_OUT */ 1809 } else { 1810 DPRINTFN(MD_CTRL, 1811 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1812 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1813 ep->phase = STATUS_IN; 1814 UWRITE1(sc, MUSB2_REG_RXCSRH, 1815 UREAD1(sc, MUSB2_REG_RXCSRH) | 1816 MUSB2_MASK_CSR0H_PING_DIS); 1817 motg_setup_endpoint_rx(xfer); 1818 UWRITE1(sc, MUSB2_REG_TXCSRL, 1819 MUSB2_MASK_CSR0L_STATUSPKT | 1820 MUSB2_MASK_CSR0L_REQPKT); 1821 return; 1822 } 1823 } 1824 if (xfer->request.bmRequestType & UT_READ) { 1825 motg_device_ctrl_read(xfer); 1826 return; 1827 } 1828 /* setup a dataout phase */ 1829 datalen = min(ep->datalen, 1830 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1831 ep->phase = DATA_OUT; 1832 DPRINTFN(MD_CTRL, 1833 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1834 UREAD1(sc, MUSB2_REG_TXCSRH))); 1835 if (datalen) { 1836 data = ep->data; 1837 ep->data += datalen; 1838 ep->datalen -= datalen; 1839 xfer->actlen += datalen; 1840 if (((vaddr_t)data & 0x3) == 0 && 1841 (datalen >> 2) > 0) { 1842 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1843 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1844 data += (datalen & ~0x3); 1845 datalen -= (datalen & ~0x3); 1846 } 1847 if (datalen) { 1848 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1849 MUSB2_REG_EPFIFO(0), data, datalen); 1850 } 1851 } 1852 /* send data */ 1853 motg_setup_endpoint_tx(xfer); 1854 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1855 return; 1856 1857 complete: 1858 ep->phase = IDLE; 1859 ep->xfer = NULL; 1860 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1861 KASSERT(new_status != USBD_IN_PROGRESS); 1862 xfer->status = new_status; 1863 usb_transfer_complete(xfer); 1864 } 1865 motg_device_ctrl_start1(sc); 1866 } 1867 1868 /* Abort a device control request. */ 1869 void 1870 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1871 { 1872 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1873 motg_device_xfer_abort(xfer); 1874 } 1875 1876 /* Close a device control pipe */ 1877 void 1878 motg_device_ctrl_close(usbd_pipe_handle pipe) 1879 { 1880 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 1881 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1882 struct motg_pipe *otgpipeiter; 1883 1884 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1885 KASSERT(mutex_owned(&sc->sc_lock)); 1886 KASSERT(otgpipe->hw_ep->xfer == NULL || 1887 otgpipe->hw_ep->xfer->pipe != pipe); 1888 1889 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1890 if (otgpipeiter == otgpipe) { 1891 /* remove from list */ 1892 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1893 motg_pipe, ep_pipe_list); 1894 otgpipe->hw_ep->refcount--; 1895 /* we're done */ 1896 return; 1897 } 1898 } 1899 panic("motg_device_ctrl_close: not found"); 1900 } 1901 1902 void 1903 motg_device_ctrl_done(usbd_xfer_handle xfer) 1904 { 1905 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 1906 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1907 KASSERT(otgpipe->hw_ep->xfer != xfer); 1908 } 1909 1910 static usbd_status 1911 motg_device_data_transfer(usbd_xfer_handle xfer) 1912 { 1913 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1914 usbd_status err; 1915 1916 /* Insert last in queue. */ 1917 mutex_enter(&sc->sc_lock); 1918 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1919 xfer, xfer->status)); 1920 err = usb_insert_transfer(xfer); 1921 xfer->status = USBD_NOT_STARTED; 1922 mutex_exit(&sc->sc_lock); 1923 if (err) 1924 return (err); 1925 1926 /* 1927 * Pipe isn't running (otherwise err would be USBD_INPROG), 1928 * so start it first. 1929 */ 1930 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1931 } 1932 1933 static usbd_status 1934 motg_device_data_start(usbd_xfer_handle xfer) 1935 { 1936 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1937 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1938 usbd_status err; 1939 mutex_enter(&sc->sc_lock); 1940 DPRINTF(("motg_device_data_start(%p) status %d\n", 1941 xfer, xfer->status)); 1942 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1943 mutex_exit(&sc->sc_lock); 1944 if (err != USBD_IN_PROGRESS) 1945 return err; 1946 if (sc->sc_bus.use_polling) 1947 motg_waitintr(sc, xfer); 1948 return USBD_IN_PROGRESS; 1949 } 1950 1951 static usbd_status 1952 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1953 { 1954 usbd_xfer_handle xfer = NULL; 1955 struct motg_pipe *otgpipe; 1956 usbd_status err = 0; 1957 uint32_t val __diagused; 1958 1959 KASSERT(mutex_owned(&sc->sc_lock)); 1960 if (sc->sc_dying) 1961 return (USBD_IOERROR); 1962 1963 if (!sc->sc_connected) 1964 return (USBD_IOERROR); 1965 1966 if (ep->xfer != NULL) { 1967 err = USBD_IN_PROGRESS; 1968 goto end; 1969 } 1970 /* locate the first pipe with work to do */ 1971 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1972 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1973 DPRINTFN(MD_BULK, 1974 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1975 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1976 if (xfer != NULL) { 1977 /* move this pipe to the end of the list */ 1978 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1979 motg_pipe, ep_pipe_list); 1980 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1981 otgpipe, ep_pipe_list); 1982 break; 1983 } 1984 } 1985 if (xfer == NULL) { 1986 err = USBD_NOT_STARTED; 1987 goto end; 1988 } 1989 xfer->status = USBD_IN_PROGRESS; 1990 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1991 KASSERT(otgpipe->hw_ep == ep); 1992 #ifdef DIAGNOSTIC 1993 if (xfer->rqflags & URQ_REQUEST) 1994 panic("motg_device_data_transfer: a request"); 1995 #endif 1996 // KASSERT(xfer->actlen == 0); 1997 xfer->actlen = 0; 1998 1999 ep->xfer = xfer; 2000 ep->datalen = xfer->length; 2001 KASSERT(ep->datalen > 0); 2002 ep->data = KERNADDR(&xfer->dmabuf, 0); 2003 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 2004 (ep->datalen % 64) == 0) 2005 ep->need_short_xfer = 1; 2006 else 2007 ep->need_short_xfer = 0; 2008 /* now we need send this request */ 2009 DPRINTFN(MD_BULK, 2010 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 2011 xfer, 2012 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 2013 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 2014 xfer->pipe->device->address)); 2015 KASSERT(ep->phase == IDLE); 2016 /* select endpoint */ 2017 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 2018 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 2019 == UE_DIR_IN) { 2020 val = UREAD1(sc, MUSB2_REG_RXCSRL); 2021 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 2022 motg_device_data_read(xfer); 2023 } else { 2024 ep->phase = DATA_OUT; 2025 val = UREAD1(sc, MUSB2_REG_TXCSRL); 2026 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 2027 motg_device_data_write(xfer); 2028 } 2029 end: 2030 if (err) 2031 return (err); 2032 2033 return (USBD_IN_PROGRESS); 2034 } 2035 2036 static void 2037 motg_device_data_read(usbd_xfer_handle xfer) 2038 { 2039 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2040 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2041 uint32_t val; 2042 2043 KASSERT(mutex_owned(&sc->sc_lock)); 2044 /* assume endpoint already selected */ 2045 motg_setup_endpoint_rx(xfer); 2046 /* Max packet size */ 2047 UWRITE2(sc, MUSB2_REG_RXMAXP, 2048 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2049 /* Data Toggle */ 2050 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2051 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2052 if (otgpipe->nexttoggle) 2053 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2054 else 2055 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2056 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2057 2058 DPRINTFN(MD_BULK, 2059 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2060 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2061 /* start transaction */ 2062 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2063 otgpipe->hw_ep->phase = DATA_IN; 2064 } 2065 2066 static void 2067 motg_device_data_write(usbd_xfer_handle xfer) 2068 { 2069 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2070 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2071 struct motg_hw_ep *ep = otgpipe->hw_ep; 2072 int datalen; 2073 char *data; 2074 uint32_t val; 2075 2076 KASSERT(xfer!=NULL); 2077 KASSERT(mutex_owned(&sc->sc_lock)); 2078 2079 datalen = min(ep->datalen, 2080 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2081 ep->phase = DATA_OUT; 2082 DPRINTFN(MD_BULK, 2083 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2084 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2085 2086 /* assume endpoint already selected */ 2087 /* write data to fifo */ 2088 data = ep->data; 2089 ep->data += datalen; 2090 ep->datalen -= datalen; 2091 xfer->actlen += datalen; 2092 if (((vaddr_t)data & 0x3) == 0 && 2093 (datalen >> 2) > 0) { 2094 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2095 MUSB2_REG_EPFIFO(ep->ep_number), 2096 (void *)data, datalen >> 2); 2097 data += (datalen & ~0x3); 2098 datalen -= (datalen & ~0x3); 2099 } 2100 if (datalen) { 2101 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2102 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2103 } 2104 2105 motg_setup_endpoint_tx(xfer); 2106 /* Max packet size */ 2107 UWRITE2(sc, MUSB2_REG_TXMAXP, 2108 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2109 /* Data Toggle */ 2110 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2111 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2112 if (otgpipe->nexttoggle) 2113 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2114 else 2115 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2116 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2117 2118 /* start transaction */ 2119 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2120 } 2121 2122 static void 2123 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2124 { 2125 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2126 usbd_xfer_handle xfer = ep->xfer; 2127 uint8_t csr; 2128 int datalen, max_datalen; 2129 char *data; 2130 bool got_short; 2131 usbd_status new_status = USBD_IN_PROGRESS; 2132 2133 KASSERT(mutex_owned(&sc->sc_lock)); 2134 KASSERT(ep->ep_number == epnumber); 2135 2136 DPRINTFN(MD_BULK, 2137 ("motg_device_intr_rx on ep %d\n", epnumber)); 2138 /* select endpoint */ 2139 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2140 2141 /* read out FIFO status */ 2142 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2143 DPRINTFN(MD_BULK, 2144 ("motg_device_intr_rx phase %d csr 0x%x\n", 2145 ep->phase, csr)); 2146 2147 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2148 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2149 return; 2150 2151 #ifdef DIAGNOSTIC 2152 if (ep->phase != DATA_IN) 2153 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2154 #endif 2155 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2156 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2157 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2158 2159 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2160 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2161 new_status = USBD_TIMEOUT; /* XXX */ 2162 goto complete; 2163 } 2164 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2165 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2166 new_status = USBD_STALLED; 2167 else 2168 new_status = USBD_IOERROR; 2169 /* clear status */ 2170 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2171 goto complete; 2172 } 2173 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2174 2175 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2176 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2177 goto complete; 2178 } 2179 2180 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2181 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2182 2183 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2184 DPRINTFN(MD_BULK, 2185 ("motg_device_intr_rx phase %d datalen %d\n", 2186 ep->phase, datalen)); 2187 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2188 max_datalen = min( 2189 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2190 ep->datalen); 2191 if (datalen > max_datalen) { 2192 new_status = USBD_IOERROR; 2193 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2194 goto complete; 2195 } 2196 got_short = (datalen < max_datalen); 2197 if (datalen > 0) { 2198 KASSERT(ep->phase == DATA_IN); 2199 data = ep->data; 2200 ep->data += datalen; 2201 ep->datalen -= datalen; 2202 xfer->actlen += datalen; 2203 if (((vaddr_t)data & 0x3) == 0 && 2204 (datalen >> 2) > 0) { 2205 DPRINTFN(MD_BULK, 2206 ("motg_device_intr_rx r4 data %p len %d\n", 2207 data, datalen)); 2208 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2209 MUSB2_REG_EPFIFO(ep->ep_number), 2210 (void *)data, datalen >> 2); 2211 data += (datalen & ~0x3); 2212 datalen -= (datalen & ~0x3); 2213 } 2214 DPRINTFN(MD_BULK, 2215 ("motg_device_intr_rx r1 data %p len %d\n", 2216 data, datalen)); 2217 if (datalen) { 2218 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2219 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2220 } 2221 } 2222 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2223 KASSERT(ep->phase == DATA_IN); 2224 if (got_short || (ep->datalen == 0)) { 2225 if (ep->need_short_xfer == 0) { 2226 new_status = USBD_NORMAL_COMPLETION; 2227 goto complete; 2228 } 2229 ep->need_short_xfer = 0; 2230 } 2231 motg_device_data_read(xfer); 2232 return; 2233 complete: 2234 DPRINTFN(MD_BULK, 2235 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2236 (xfer != NULL) ? xfer->status : 0)); 2237 ep->phase = IDLE; 2238 ep->xfer = NULL; 2239 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2240 KASSERT(new_status != USBD_IN_PROGRESS); 2241 xfer->status = new_status; 2242 usb_transfer_complete(xfer); 2243 } 2244 motg_device_data_start1(sc, ep); 2245 } 2246 2247 static void 2248 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2249 { 2250 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2251 usbd_xfer_handle xfer = ep->xfer; 2252 uint8_t csr; 2253 struct motg_pipe *otgpipe; 2254 usbd_status new_status = USBD_IN_PROGRESS; 2255 2256 KASSERT(mutex_owned(&sc->sc_lock)); 2257 KASSERT(ep->ep_number == epnumber); 2258 2259 DPRINTFN(MD_BULK, 2260 ("motg_device_intr_tx on ep %d\n", epnumber)); 2261 /* select endpoint */ 2262 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2263 2264 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2265 DPRINTFN(MD_BULK, 2266 ("motg_device_intr_tx phase %d csr 0x%x\n", 2267 ep->phase, csr)); 2268 2269 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2270 /* command not accepted */ 2271 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2272 new_status = USBD_STALLED; 2273 else 2274 new_status = USBD_IOERROR; 2275 /* clear status */ 2276 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2277 goto complete; 2278 } 2279 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2280 new_status = USBD_TIMEOUT; /* XXX */ 2281 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2282 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2283 /* flush fifo */ 2284 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2285 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2286 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2287 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2288 delay(1000); 2289 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2290 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2291 epnumber, csr)); 2292 } 2293 goto complete; 2294 } 2295 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2296 /* data still not sent */ 2297 return; 2298 } 2299 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2300 goto complete; 2301 #ifdef DIAGNOSTIC 2302 if (ep->phase != DATA_OUT) 2303 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2304 #endif 2305 2306 otgpipe = (struct motg_pipe *)xfer->pipe; 2307 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2308 2309 if (ep->datalen == 0) { 2310 if (ep->need_short_xfer) { 2311 ep->need_short_xfer = 0; 2312 /* one more data phase */ 2313 } else { 2314 new_status = USBD_NORMAL_COMPLETION; 2315 goto complete; 2316 } 2317 } 2318 motg_device_data_write(xfer); 2319 return; 2320 2321 complete: 2322 DPRINTFN(MD_BULK, 2323 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2324 (xfer != NULL) ? xfer->status : 0)); 2325 #ifdef DIAGNOSTIC 2326 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2327 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2328 #endif 2329 ep->phase = IDLE; 2330 ep->xfer = NULL; 2331 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2332 KASSERT(new_status != USBD_IN_PROGRESS); 2333 xfer->status = new_status; 2334 usb_transfer_complete(xfer); 2335 } 2336 motg_device_data_start1(sc, ep); 2337 } 2338 2339 /* Abort a device control request. */ 2340 void 2341 motg_device_data_abort(usbd_xfer_handle xfer) 2342 { 2343 #ifdef DIAGNOSTIC 2344 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2345 #endif 2346 KASSERT(mutex_owned(&sc->sc_lock)); 2347 2348 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2349 motg_device_xfer_abort(xfer); 2350 } 2351 2352 /* Close a device control pipe */ 2353 void 2354 motg_device_data_close(usbd_pipe_handle pipe) 2355 { 2356 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 2357 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2358 struct motg_pipe *otgpipeiter; 2359 2360 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2361 KASSERT(mutex_owned(&sc->sc_lock)); 2362 KASSERT(otgpipe->hw_ep->xfer == NULL || 2363 otgpipe->hw_ep->xfer->pipe != pipe); 2364 2365 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2366 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2367 if (otgpipeiter == otgpipe) { 2368 /* remove from list */ 2369 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2370 motg_pipe, ep_pipe_list); 2371 otgpipe->hw_ep->refcount--; 2372 /* we're done */ 2373 return; 2374 } 2375 } 2376 panic("motg_device_data_close: not found"); 2377 } 2378 2379 void 2380 motg_device_data_done(usbd_xfer_handle xfer) 2381 { 2382 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 2383 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2384 KASSERT(otgpipe->hw_ep->xfer != xfer); 2385 } 2386 2387 /* 2388 * Wait here until controller claims to have an interrupt. 2389 * Then call motg_intr and return. Use timeout to avoid waiting 2390 * too long. 2391 * Only used during boot when interrupts are not enabled yet. 2392 */ 2393 void 2394 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2395 { 2396 int timo = xfer->timeout; 2397 2398 mutex_enter(&sc->sc_lock); 2399 2400 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2401 2402 for (; timo >= 0; timo--) { 2403 mutex_exit(&sc->sc_lock); 2404 usb_delay_ms(&sc->sc_bus, 1); 2405 mutex_spin_enter(&sc->sc_intr_lock); 2406 motg_poll(&sc->sc_bus); 2407 mutex_spin_exit(&sc->sc_intr_lock); 2408 mutex_enter(&sc->sc_lock); 2409 if (xfer->status != USBD_IN_PROGRESS) 2410 goto done; 2411 } 2412 2413 /* Timeout */ 2414 DPRINTF(("motg_waitintr: timeout\n")); 2415 panic("motg_waitintr: timeout"); 2416 /* XXX handle timeout ! */ 2417 2418 done: 2419 mutex_exit(&sc->sc_lock); 2420 } 2421 2422 void 2423 motg_device_clear_toggle(usbd_pipe_handle pipe) 2424 { 2425 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2426 otgpipe->nexttoggle = 0; 2427 } 2428 2429 /* Abort a device control request. */ 2430 static void 2431 motg_device_xfer_abort(usbd_xfer_handle xfer) 2432 { 2433 int wake; 2434 uint8_t csr; 2435 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2436 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 2439 DPRINTF(("motg_device_xfer_abort:\n")); 2440 if (xfer->hcflags & UXFER_ABORTING) { 2441 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2442 xfer->hcflags |= UXFER_ABORTWAIT; 2443 while (xfer->hcflags & UXFER_ABORTING) 2444 cv_wait(&xfer->hccv, &sc->sc_lock); 2445 return; 2446 } 2447 xfer->hcflags |= UXFER_ABORTING; 2448 if (otgpipe->hw_ep->xfer == xfer) { 2449 KASSERT(xfer->status == USBD_IN_PROGRESS); 2450 otgpipe->hw_ep->xfer = NULL; 2451 if (otgpipe->hw_ep->ep_number > 0) { 2452 /* select endpoint */ 2453 UWRITE1(sc, MUSB2_REG_EPINDEX, 2454 otgpipe->hw_ep->ep_number); 2455 if (otgpipe->hw_ep->phase == DATA_OUT) { 2456 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2457 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2458 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2459 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2460 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2461 } 2462 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2463 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2464 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2465 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2466 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2467 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2468 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2469 } 2470 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2471 } 2472 otgpipe->hw_ep->phase = IDLE; 2473 } 2474 } 2475 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2476 wake = xfer->hcflags & UXFER_ABORTWAIT; 2477 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2478 usb_transfer_complete(xfer); 2479 if (wake) 2480 cv_broadcast(&xfer->hccv); 2481 } 2482
Indexes created Mon Oct 13 16:09:52 GMT 2025