motg.c revision 1.12.2.17
1 /* $NetBSD: motg.c,v 1.12.2.17 2015/03/19 17:26:43 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include "opt_motg.h" 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.12.2.17 2015/03/19 17:26:43 skrll Exp $"); 46 47 #include <sys/param.h> 48 49 #include <sys/bus.h> 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usbhist.h> 67 68 #ifdef MOTG_ALLWINNER 69 #include <arch/arm/allwinner/awin_otgreg.h> 70 #else 71 #include <dev/usb/motgreg.h> 72 #endif 73 74 #include <dev/usb/motgvar.h> 75 #include <dev/usb/usbroothub.h> 76 77 #ifdef USB_DEBUG 78 #ifndef MOTG_DEBUG 79 #define motgdebug 0 80 #else 81 int motgdebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 91 SYSCTL_DESCR("motg global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* MOTG_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #define MD_ROOT 0x0002 114 #define MD_CTRL 0x0004 115 #define MD_BULK 0x0008 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 119 #define MOTGHIST_FUNC() USBHIST_FUNC() 120 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 121 122 123 /* various timeouts, for various speeds */ 124 /* control NAK timeouts */ 125 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 126 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 127 128 /* intr/iso polling intervals */ 129 #define POLL_TO 100 /* 100 frames, about 0.1s */ 130 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 131 132 /* bulk NAK timeouts */ 133 #define NAK_TO_BULK 0 /* disabled */ 134 #define NAK_TO_BULK_HIGH 0 135 136 static void motg_hub_change(struct motg_softc *); 137 138 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 139 static usbd_status motg_root_intr_start(struct usbd_xfer *); 140 static void motg_root_intr_abort(struct usbd_xfer *); 141 static void motg_root_intr_close(struct usbd_pipe *); 142 static void motg_root_intr_done(struct usbd_xfer *); 143 144 static usbd_status motg_open(struct usbd_pipe *); 145 static void motg_poll(struct usbd_bus *); 146 static void motg_softintr(void *); 147 static struct usbd_xfer * motg_allocx(struct usbd_bus *); 148 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 149 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 150 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 151 void *, int); 152 153 static void motg_noop(struct usbd_pipe *pipe); 154 static usbd_status motg_portreset(struct motg_softc*); 155 156 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 157 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 158 static void motg_device_ctrl_abort(struct usbd_xfer *); 159 static void motg_device_ctrl_close(struct usbd_pipe *); 160 static void motg_device_ctrl_done(struct usbd_xfer *); 161 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 162 static void motg_device_ctrl_read(struct usbd_xfer *); 163 static void motg_device_ctrl_intr_rx(struct motg_softc *); 164 static void motg_device_ctrl_intr_tx(struct motg_softc *); 165 166 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 167 static usbd_status motg_device_data_start(struct usbd_xfer *); 168 static usbd_status motg_device_data_start1(struct motg_softc *, 169 struct motg_hw_ep *); 170 static void motg_device_data_abort(struct usbd_xfer *); 171 static void motg_device_data_close(struct usbd_pipe *); 172 static void motg_device_data_done(struct usbd_xfer *); 173 static void motg_device_intr_rx(struct motg_softc *, int); 174 static void motg_device_intr_tx(struct motg_softc *, int); 175 static void motg_device_data_read(struct usbd_xfer *); 176 static void motg_device_data_write(struct usbd_xfer *); 177 178 static void motg_waitintr(struct motg_softc *, struct usbd_xfer *); 179 static void motg_device_clear_toggle(struct usbd_pipe *); 180 static void motg_device_xfer_abort(struct usbd_xfer *); 181 182 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 183 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 184 #define UWRITE1(sc, r, x) \ 185 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 186 } while (/*CONSTCOND*/0) 187 #define UWRITE2(sc, r, x) \ 188 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 189 } while (/*CONSTCOND*/0) 190 #define UWRITE4(sc, r, x) \ 191 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 192 } while (/*CONSTCOND*/0) 193 194 static __inline uint32_t 195 UREAD1(struct motg_softc *sc, bus_size_t r) 196 { 197 198 UBARR(sc); 199 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 200 } 201 static __inline uint32_t 202 UREAD2(struct motg_softc *sc, bus_size_t r) 203 { 204 205 UBARR(sc); 206 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 207 } 208 209 #if 0 210 static __inline uint32_t 211 UREAD4(struct motg_softc *sc, bus_size_t r) 212 { 213 214 UBARR(sc); 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 216 } 217 #endif 218 219 static void 220 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 221 { 222 uint8_t val; 223 224 val = UREAD1(sc, MUSB2_REG_POWER); 225 if (on) 226 val |= MUSB2_MASK_SOFTC; 227 else 228 val &= ~MUSB2_MASK_SOFTC; 229 230 UWRITE1(sc, MUSB2_REG_POWER, val); 231 } 232 233 const struct usbd_bus_methods motg_bus_methods = { 234 .ubm_open = motg_open, 235 .ubm_softint = motg_softintr, 236 .ubm_dopoll = motg_poll, 237 .ubm_allocx = motg_allocx, 238 .ubm_freex = motg_freex, 239 .ubm_getlock = motg_get_lock, 240 .ubm_rhctrl = motg_roothub_ctrl, 241 }; 242 243 const struct usbd_pipe_methods motg_root_intr_methods = { 244 .upm_transfer = motg_root_intr_transfer, 245 .upm_start = motg_root_intr_start, 246 .upm_abort = motg_root_intr_abort, 247 .upm_close = motg_root_intr_close, 248 .upm_cleartoggle = motg_noop, 249 .upm_done = motg_root_intr_done, 250 }; 251 252 const struct usbd_pipe_methods motg_device_ctrl_methods = { 253 .upm_transfer = motg_device_ctrl_transfer, 254 .upm_start = motg_device_ctrl_start, 255 .upm_abort = motg_device_ctrl_abort, 256 .upm_close = motg_device_ctrl_close, 257 .upm_cleartoggle = motg_noop, 258 .upm_done = motg_device_ctrl_done, 259 }; 260 261 const struct usbd_pipe_methods motg_device_data_methods = { 262 .upm_transfer = motg_device_data_transfer, 263 .upm_start = motg_device_data_start, 264 .upm_abort = motg_device_data_abort, 265 .upm_close = motg_device_data_close, 266 .upm_cleartoggle = motg_device_clear_toggle, 267 .upm_done = motg_device_data_done, 268 }; 269 270 int 271 motg_init(struct motg_softc *sc) 272 { 273 uint32_t nrx, ntx, val; 274 int dynfifo; 275 int offset, i; 276 277 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 278 279 if (sc->sc_mode == MOTG_MODE_DEVICE) 280 return ENOTSUP; /* not supported */ 281 282 /* disable all interrupts */ 283 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 284 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 285 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 286 /* disable pullup */ 287 288 musbotg_pull_common(sc, 0); 289 290 #ifdef MUSB2_REG_RXDBDIS 291 /* disable double packet buffering XXX what's this ? */ 292 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 293 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 294 #endif 295 296 /* enable HighSpeed and ISO Update flags */ 297 298 UWRITE1(sc, MUSB2_REG_POWER, 299 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 300 301 if (sc->sc_mode == MOTG_MODE_DEVICE) { 302 /* clear Session bit, if set */ 303 val = UREAD1(sc, MUSB2_REG_DEVCTL); 304 val &= ~MUSB2_MASK_SESS; 305 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 306 } else { 307 /* Enter session for Host mode */ 308 val = UREAD1(sc, MUSB2_REG_DEVCTL); 309 val |= MUSB2_MASK_SESS; 310 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 311 } 312 delay(1000); 313 DPRINTF("DEVCTL 0x%x", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 314 315 /* disable testmode */ 316 317 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 318 319 #ifdef MUSB2_REG_MISC 320 /* set default value */ 321 322 UWRITE1(sc, MUSB2_REG_MISC, 0); 323 #endif 324 325 /* select endpoint index 0 */ 326 327 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 328 329 if (sc->sc_ep_max == 0) { 330 /* read out number of endpoints */ 331 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 332 333 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 334 335 /* these numbers exclude the control endpoint */ 336 337 DPRINTFN(1,"RX/TX endpoints: %u/%u", nrx, ntx, 0, 0); 338 339 sc->sc_ep_max = MAX(nrx, ntx); 340 } else { 341 nrx = ntx = sc->sc_ep_max; 342 } 343 if (sc->sc_ep_max == 0) { 344 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 345 return -1; 346 } 347 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 348 /* read out configuration data */ 349 val = UREAD1(sc, MUSB2_REG_CONFDATA); 350 351 DPRINTF("Config Data: 0x%02x", val, 0, 0, 0); 352 353 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 354 355 if (dynfifo) { 356 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 357 "assuming 16Kbytes of FIFO RAM\n"); 358 } 359 360 DPRINTF("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 361 362 /* initialise endpoint profiles */ 363 sc->sc_in_ep[0].ep_fifo_size = 64; 364 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 365 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 366 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 367 offset = 64; 368 369 for (i = 1; i <= sc->sc_ep_max; i++) { 370 int fiforx_size, fifotx_size, fifo_size; 371 372 /* select endpoint */ 373 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 374 375 if (sc->sc_ep_fifosize) { 376 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 377 } else { 378 val = UREAD1(sc, MUSB2_REG_FSIZE); 379 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 380 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 381 } 382 383 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d", 384 i, fifotx_size, fiforx_size, dynfifo); 385 386 if (dynfifo) { 387 if (sc->sc_ep_fifosize) { 388 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 389 } else { 390 if (i < 3) { 391 fifo_size = 12; /* 4K */ 392 } else if (i < 10) { 393 fifo_size = 10; /* 1K */ 394 } else { 395 fifo_size = 7; /* 128 bytes */ 396 } 397 } 398 if (fiforx_size && (i <= nrx)) { 399 fiforx_size = fifo_size; 400 if (fifo_size > 7) { 401 #if 0 402 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size) | 404 MUSB2_MASK_FIFODB); 405 #else 406 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size)); 408 #endif 409 } else { 410 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 411 MUSB2_VAL_FIFOSZ(fifo_size)); 412 } 413 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 414 offset >> 3); 415 offset += (1 << fiforx_size); 416 } 417 if (fifotx_size && (i <= ntx)) { 418 fifotx_size = fifo_size; 419 if (fifo_size > 7) { 420 #if 0 421 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 422 MUSB2_VAL_FIFOSZ(fifo_size) | 423 MUSB2_MASK_FIFODB); 424 #else 425 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 426 MUSB2_VAL_FIFOSZ(fifo_size)); 427 #endif 428 } else { 429 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 430 MUSB2_VAL_FIFOSZ(fifo_size)); 431 } 432 433 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 434 offset >> 3); 435 436 offset += (1 << fifotx_size); 437 } 438 } 439 if (fiforx_size && (i <= nrx)) { 440 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 441 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 442 } 443 if (fifotx_size && (i <= ntx)) { 444 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 445 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 446 } 447 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 448 } 449 450 451 DPRINTF("Dynamic FIFO size = %d bytes", offset, 0, 0, 0); 452 453 /* turn on default interrupts */ 454 455 if (sc->sc_mode == MOTG_MODE_HOST) { 456 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 457 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 458 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 459 } else 460 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 461 462 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 463 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 464 465 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 466 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.ub_methods = &motg_bus_methods; 470 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 471 sc->sc_bus.ub_revision = USBREV_2_0; 472 sc->sc_bus.ub_usedma = false; 473 sc->sc_bus.ub_hcpriv = sc; 474 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 475 "Mentor Graphics"); 476 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 477 return 0; 478 } 479 480 static int 481 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 482 { 483 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 484 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 485 struct motg_hw_ep *ep; 486 int i, size; 487 488 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 489 490 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 491 sc->sc_in_ep : sc->sc_out_ep; 492 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 493 494 for (i = sc->sc_ep_max; i >= 1; i--) { 495 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 496 "in_ep[%d].ep_fifo_size %d size %d ref %d" : 497 "out_ep[%d].ep_fifo_size %d size %d ref %d", i, 498 ep[i].ep_fifo_size, size, ep[i].refcount); 499 if (ep[i].ep_fifo_size >= size) { 500 /* found a suitable endpoint */ 501 otgpipe->hw_ep = &ep[i]; 502 mutex_enter(&sc->sc_lock); 503 if (otgpipe->hw_ep->refcount > 0) { 504 /* no luck, try next */ 505 mutex_exit(&sc->sc_lock); 506 otgpipe->hw_ep = NULL; 507 } else { 508 otgpipe->hw_ep->refcount++; 509 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 510 otgpipe, ep_pipe_list); 511 mutex_exit(&sc->sc_lock); 512 return 0; 513 } 514 } 515 } 516 return -1; 517 } 518 519 /* Open a new pipe. */ 520 usbd_status 521 motg_open(struct usbd_pipe *pipe) 522 { 523 struct motg_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv; 524 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 525 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 526 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 527 528 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 529 530 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, 531 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 532 533 if (sc->sc_dying) 534 return USBD_IOERROR; 535 536 /* toggle state needed for bulk endpoints */ 537 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 538 539 if (pipe->up_dev->ud_addr == rhaddr) { 540 switch (ed->bEndpointAddress) { 541 case USB_CONTROL_ENDPOINT: 542 pipe->up_methods = &roothub_ctrl_methods; 543 break; 544 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 545 pipe->up_methods = &motg_root_intr_methods; 546 break; 547 default: 548 return USBD_INVAL; 549 } 550 } else { 551 switch (ed->bmAttributes & UE_XFERTYPE) { 552 case UE_CONTROL: 553 pipe->up_methods = &motg_device_ctrl_methods; 554 /* always use sc_in_ep[0] for in and out */ 555 otgpipe->hw_ep = &sc->sc_in_ep[0]; 556 mutex_enter(&sc->sc_lock); 557 otgpipe->hw_ep->refcount++; 558 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 559 otgpipe, ep_pipe_list); 560 mutex_exit(&sc->sc_lock); 561 break; 562 case UE_BULK: 563 case UE_INTERRUPT: 564 DPRINTFN(MD_BULK, 565 "type %d dir %d pipe wMaxPacketSize %d", 566 UE_GET_XFERTYPE(ed->bmAttributes), 567 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 568 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 569 if (motg_select_ep(sc, pipe) != 0) 570 goto bad; 571 KASSERT(otgpipe->hw_ep != NULL); 572 pipe->up_methods = &motg_device_data_methods; 573 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 574 break; 575 default: 576 goto bad; 577 #ifdef notyet 578 case UE_ISOCHRONOUS: 579 ... 580 break; 581 #endif /* notyet */ 582 } 583 } 584 return USBD_NORMAL_COMPLETION; 585 586 bad: 587 return USBD_NOMEM; 588 } 589 590 void 591 motg_softintr(void *v) 592 { 593 struct usbd_bus *bus = v; 594 struct motg_softc *sc = bus->ub_hcpriv; 595 uint16_t rx_status, tx_status; 596 uint8_t ctrl_status; 597 uint32_t val; 598 int i; 599 600 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 601 602 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 603 604 DPRINTFN(MD_ROOT | MD_CTRL, "sc %p", sc, 0 ,0 ,0); 605 606 mutex_spin_enter(&sc->sc_intr_lock); 607 rx_status = sc->sc_intr_rx_ep; 608 sc->sc_intr_rx_ep = 0; 609 tx_status = sc->sc_intr_tx_ep; 610 sc->sc_intr_tx_ep = 0; 611 ctrl_status = sc->sc_intr_ctrl; 612 sc->sc_intr_ctrl = 0; 613 mutex_spin_exit(&sc->sc_intr_lock); 614 615 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 616 617 if (ctrl_status & (MUSB2_MASK_IRESET | 618 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 619 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 620 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%x", ctrl_status, 0, 0, 0); 621 622 if (ctrl_status & MUSB2_MASK_IRESET) { 623 sc->sc_isreset = 1; 624 sc->sc_port_suspended = 0; 625 sc->sc_port_suspended_change = 1; 626 sc->sc_connected_changed = 1; 627 sc->sc_port_enabled = 1; 628 629 val = UREAD1(sc, MUSB2_REG_POWER); 630 if (val & MUSB2_MASK_HSMODE) 631 sc->sc_high_speed = 1; 632 else 633 sc->sc_high_speed = 0; 634 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 635 0, 0, 0); 636 637 /* turn off interrupts */ 638 val = MUSB2_MASK_IRESET; 639 val &= ~MUSB2_MASK_IRESUME; 640 val |= MUSB2_MASK_ISUSP; 641 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 642 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 643 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 644 } 645 if (ctrl_status & MUSB2_MASK_IRESUME) { 646 if (sc->sc_port_suspended) { 647 sc->sc_port_suspended = 0; 648 sc->sc_port_suspended_change = 1; 649 val = UREAD1(sc, MUSB2_REG_INTUSBE); 650 /* disable resume interrupt */ 651 val &= ~MUSB2_MASK_IRESUME; 652 /* enable suspend interrupt */ 653 val |= MUSB2_MASK_ISUSP; 654 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 655 } 656 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 657 if (!sc->sc_port_suspended) { 658 sc->sc_port_suspended = 1; 659 sc->sc_port_suspended_change = 1; 660 661 val = UREAD1(sc, MUSB2_REG_INTUSBE); 662 /* disable suspend interrupt */ 663 val &= ~MUSB2_MASK_ISUSP; 664 /* enable resume interrupt */ 665 val |= MUSB2_MASK_IRESUME; 666 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 667 } 668 } 669 if (ctrl_status & MUSB2_MASK_ICONN) { 670 sc->sc_connected = 1; 671 sc->sc_connected_changed = 1; 672 sc->sc_isreset = 1; 673 sc->sc_port_enabled = 1; 674 } else if (ctrl_status & MUSB2_MASK_IDISC) { 675 sc->sc_connected = 0; 676 sc->sc_connected_changed = 1; 677 sc->sc_isreset = 0; 678 sc->sc_port_enabled = 0; 679 } 680 681 /* complete root HUB interrupt endpoint */ 682 683 motg_hub_change(sc); 684 } 685 /* 686 * read in interrupt status and mix with the status we 687 * got from the wrapper 688 */ 689 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 690 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 691 692 if (rx_status & 0x01) 693 panic("ctrl_rx %08x", rx_status); 694 if (tx_status & 0x01) 695 motg_device_ctrl_intr_tx(sc); 696 for (i = 1; i <= sc->sc_ep_max; i++) { 697 if (rx_status & (0x01 << i)) 698 motg_device_intr_rx(sc, i); 699 if (tx_status & (0x01 << i)) 700 motg_device_intr_tx(sc, i); 701 } 702 return; 703 } 704 705 void 706 motg_poll(struct usbd_bus *bus) 707 { 708 struct motg_softc *sc = bus->ub_hcpriv; 709 710 sc->sc_intr_poll(sc->sc_intr_poll_arg); 711 mutex_enter(&sc->sc_lock); 712 motg_softintr(bus); 713 mutex_exit(&sc->sc_lock); 714 } 715 716 int 717 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 718 uint8_t ctrl) 719 { 720 KASSERT(mutex_owned(&sc->sc_intr_lock)); 721 sc->sc_intr_tx_ep = tx_ep; 722 sc->sc_intr_rx_ep = rx_ep; 723 sc->sc_intr_ctrl = ctrl; 724 725 if (!sc->sc_bus.ub_usepolling) { 726 usb_schedsoftintr(&sc->sc_bus); 727 } 728 return 1; 729 } 730 731 int 732 motg_intr_vbus(struct motg_softc *sc, int vbus) 733 { 734 uint8_t val; 735 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 736 737 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 738 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 739 /* try to re-enter session for Host mode */ 740 val = UREAD1(sc, MUSB2_REG_DEVCTL); 741 val |= MUSB2_MASK_SESS; 742 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 743 } 744 return 1; 745 } 746 747 struct usbd_xfer * 748 motg_allocx(struct usbd_bus *bus) 749 { 750 struct motg_softc *sc = bus->ub_hcpriv; 751 struct usbd_xfer *xfer; 752 753 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 754 if (xfer != NULL) { 755 memset(xfer, 0, sizeof(struct motg_xfer)); 756 UXFER(xfer)->sc = sc; 757 #ifdef DIAGNOSTIC 758 // XXX UXFER(xfer)->iinfo.isdone = 1; 759 xfer->ux_state = XFER_BUSY; 760 #endif 761 } 762 return xfer; 763 } 764 765 void 766 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 767 { 768 struct motg_softc *sc = bus->ub_hcpriv; 769 770 #ifdef DIAGNOSTIC 771 if (xfer->ux_state != XFER_BUSY) { 772 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 773 xfer->ux_state); 774 } 775 xfer->ux_state = XFER_FREE; 776 #endif 777 pool_cache_put(sc->sc_xferpool, xfer); 778 } 779 780 static void 781 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 782 { 783 struct motg_softc *sc = bus->ub_hcpriv; 784 785 *lock = &sc->sc_lock; 786 } 787 788 /* 789 * Routines to emulate the root hub. 790 */ 791 Static int 792 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 793 void *buf, int buflen) 794 { 795 struct motg_softc *sc = bus->ub_hcpriv; 796 int status, change, totlen = 0; 797 uint16_t len, value, index; 798 usb_port_status_t ps; 799 usbd_status err; 800 uint32_t val; 801 802 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 803 804 if (sc->sc_dying) 805 return -1; 806 807 DPRINTFN(MD_ROOT, "type=0x%02x request=%02x", req->bmRequestType, 808 req->bRequest, 0, 0); 809 810 len = UGETW(req->wLength); 811 value = UGETW(req->wValue); 812 index = UGETW(req->wIndex); 813 814 #define C(x,y) ((x) | ((y) << 8)) 815 switch (C(req->bRequest, req->bmRequestType)) { 816 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 817 DPRINTFN(MD_ROOT, "wValue=0x%04x", value, 0, 0, 0); 818 switch (value) { 819 case C(0, UDESC_DEVICE): { 820 usb_device_descriptor_t devd; 821 822 totlen = min(buflen, sizeof(devd)); 823 memcpy(&devd, buf, totlen); 824 USETW(devd.idVendor, sc->sc_id_vendor); 825 memcpy(buf, &devd, totlen); 826 break; 827 } 828 case C(1, UDESC_STRING): 829 #define sd ((usb_string_descriptor_t *)buf) 830 /* Vendor */ 831 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 832 break; 833 case C(2, UDESC_STRING): 834 /* Product */ 835 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 836 break; 837 #undef sd 838 default: 839 /* default from usbroothub */ 840 return buflen; 841 } 842 break; 843 /* Hub requests */ 844 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 845 break; 846 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 847 DPRINTFN(MD_ROOT, 848 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 849 0, 0); 850 if (index != 1) { 851 return -1; 852 } 853 switch (value) { 854 case UHF_PORT_ENABLE: 855 sc->sc_port_enabled = 0; 856 break; 857 case UHF_PORT_SUSPEND: 858 if (sc->sc_port_suspended != 0) { 859 val = UREAD1(sc, MUSB2_REG_POWER); 860 val &= ~MUSB2_MASK_SUSPMODE; 861 val |= MUSB2_MASK_RESUME; 862 UWRITE1(sc, MUSB2_REG_POWER, val); 863 /* wait 20 milliseconds */ 864 usb_delay_ms(&sc->sc_bus, 20); 865 val = UREAD1(sc, MUSB2_REG_POWER); 866 val &= ~MUSB2_MASK_RESUME; 867 UWRITE1(sc, MUSB2_REG_POWER, val); 868 sc->sc_port_suspended = 0; 869 sc->sc_port_suspended_change = 1; 870 } 871 break; 872 case UHF_PORT_RESET: 873 break; 874 case UHF_C_PORT_CONNECTION: 875 break; 876 case UHF_C_PORT_ENABLE: 877 break; 878 case UHF_C_PORT_OVER_CURRENT: 879 break; 880 case UHF_C_PORT_RESET: 881 sc->sc_isreset = 0; 882 break; 883 case UHF_PORT_POWER: 884 /* XXX todo */ 885 break; 886 case UHF_PORT_CONNECTION: 887 case UHF_PORT_OVER_CURRENT: 888 case UHF_PORT_LOW_SPEED: 889 case UHF_C_PORT_SUSPEND: 890 default: 891 return -1; 892 } 893 break; 894 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 895 return -1; 896 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 897 if (len == 0) 898 break; 899 if ((value & 0xff) != 0) { 900 return -1; 901 } 902 totlen = buflen; 903 break; 904 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 905 if (len != 4) { 906 return -1; 907 } 908 memset(buf, 0, len); 909 totlen = len; 910 break; 911 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 912 if (index != 1) { 913 return -1; 914 } 915 if (len != 4) { 916 return -1; 917 } 918 status = change = 0; 919 if (sc->sc_connected) 920 status |= UPS_CURRENT_CONNECT_STATUS; 921 if (sc->sc_connected_changed) { 922 change |= UPS_C_CONNECT_STATUS; 923 sc->sc_connected_changed = 0; 924 } 925 if (sc->sc_port_enabled) 926 status |= UPS_PORT_ENABLED; 927 if (sc->sc_port_enabled_changed) { 928 change |= UPS_C_PORT_ENABLED; 929 sc->sc_port_enabled_changed = 0; 930 } 931 if (sc->sc_port_suspended) 932 status |= UPS_SUSPEND; 933 if (sc->sc_high_speed) 934 status |= UPS_HIGH_SPEED; 935 status |= UPS_PORT_POWER; /* XXX */ 936 if (sc->sc_isreset) 937 change |= UPS_C_PORT_RESET; 938 USETW(ps.wPortStatus, status); 939 USETW(ps.wPortChange, change); 940 totlen = min(len, sizeof(ps)); 941 memcpy(buf, &ps, totlen); 942 break; 943 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 944 return -1; 945 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 946 break; 947 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 948 if (index != 1) { 949 return -1; 950 } 951 switch(value) { 952 case UHF_PORT_ENABLE: 953 sc->sc_port_enabled = 1; 954 break; 955 case UHF_PORT_SUSPEND: 956 if (sc->sc_port_suspended == 0) { 957 val = UREAD1(sc, MUSB2_REG_POWER); 958 val |= MUSB2_MASK_SUSPMODE; 959 UWRITE1(sc, MUSB2_REG_POWER, val); 960 /* wait 20 milliseconds */ 961 usb_delay_ms(&sc->sc_bus, 20); 962 sc->sc_port_suspended = 1; 963 sc->sc_port_suspended_change = 1; 964 } 965 break; 966 case UHF_PORT_RESET: 967 err = motg_portreset(sc); 968 if (err != USBD_NORMAL_COMPLETION) 969 return -1; 970 return 0; 971 case UHF_PORT_POWER: 972 /* XXX todo */ 973 return 0; 974 case UHF_C_PORT_CONNECTION: 975 case UHF_C_PORT_ENABLE: 976 case UHF_C_PORT_OVER_CURRENT: 977 case UHF_PORT_CONNECTION: 978 case UHF_PORT_OVER_CURRENT: 979 case UHF_PORT_LOW_SPEED: 980 case UHF_C_PORT_SUSPEND: 981 case UHF_C_PORT_RESET: 982 default: 983 return -1; 984 } 985 break; 986 default: 987 /* default from usbroothub */ 988 return buflen; 989 } 990 991 return totlen; 992 } 993 994 /* Abort a root interrupt request. */ 995 void 996 motg_root_intr_abort(struct usbd_xfer *xfer) 997 { 998 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 999 1000 KASSERT(mutex_owned(&sc->sc_lock)); 1001 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 1002 1003 sc->sc_intr_xfer = NULL; 1004 1005 #ifdef DIAGNOSTIC 1006 // XXX UXFER(xfer)->iinfo.isdone = 1; 1007 #endif 1008 xfer->ux_status = USBD_CANCELLED; 1009 usb_transfer_complete(xfer); 1010 } 1011 1012 usbd_status 1013 motg_root_intr_transfer(struct usbd_xfer *xfer) 1014 { 1015 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1016 usbd_status err; 1017 1018 /* Insert last in queue. */ 1019 mutex_enter(&sc->sc_lock); 1020 err = usb_insert_transfer(xfer); 1021 mutex_exit(&sc->sc_lock); 1022 if (err) 1023 return err; 1024 1025 /* 1026 * Pipe isn't running (otherwise err would be USBD_INPROG), 1027 * start first 1028 */ 1029 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1030 } 1031 1032 /* Start a transfer on the root interrupt pipe */ 1033 usbd_status 1034 motg_root_intr_start(struct usbd_xfer *xfer) 1035 { 1036 struct usbd_pipe *pipe = xfer->ux_pipe; 1037 struct motg_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv; 1038 1039 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1040 1041 DPRINTFN(MD_ROOT, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 1042 xfer->ux_flags, 0); 1043 1044 if (sc->sc_dying) 1045 return USBD_IOERROR; 1046 1047 sc->sc_intr_xfer = xfer; 1048 return USBD_IN_PROGRESS; 1049 } 1050 1051 /* Close the root interrupt pipe. */ 1052 void 1053 motg_root_intr_close(struct usbd_pipe *pipe) 1054 { 1055 struct motg_softc *sc = pipe->up_dev->ud_bus->ub_hcpriv; 1056 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1057 1058 KASSERT(mutex_owned(&sc->sc_lock)); 1059 1060 sc->sc_intr_xfer = NULL; 1061 } 1062 1063 void 1064 motg_root_intr_done(struct usbd_xfer *xfer) 1065 { 1066 } 1067 1068 void 1069 motg_noop(struct usbd_pipe *pipe) 1070 { 1071 } 1072 1073 static usbd_status 1074 motg_portreset(struct motg_softc *sc) 1075 { 1076 uint32_t val; 1077 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1078 1079 val = UREAD1(sc, MUSB2_REG_POWER); 1080 val |= MUSB2_MASK_RESET; 1081 UWRITE1(sc, MUSB2_REG_POWER, val); 1082 /* Wait for 20 msec */ 1083 usb_delay_ms(&sc->sc_bus, 20); 1084 1085 val = UREAD1(sc, MUSB2_REG_POWER); 1086 val &= ~MUSB2_MASK_RESET; 1087 UWRITE1(sc, MUSB2_REG_POWER, val); 1088 1089 /* determine line speed */ 1090 val = UREAD1(sc, MUSB2_REG_POWER); 1091 if (val & MUSB2_MASK_HSMODE) 1092 sc->sc_high_speed = 1; 1093 else 1094 sc->sc_high_speed = 0; 1095 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 0, 0, 0); 1096 1097 sc->sc_isreset = 1; 1098 sc->sc_port_enabled = 1; 1099 return USBD_NORMAL_COMPLETION; 1100 } 1101 1102 /* 1103 * This routine is executed when an interrupt on the root hub is detected 1104 */ 1105 static void 1106 motg_hub_change(struct motg_softc *sc) 1107 { 1108 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1109 struct usbd_pipe *pipe; 1110 u_char *p; 1111 1112 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1113 1114 if (xfer == NULL) 1115 return; /* the interrupt pipe is not open */ 1116 1117 pipe = xfer->ux_pipe; 1118 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1119 return; /* device has detached */ 1120 1121 p = xfer->ux_buf; 1122 p[0] = 1<<1; 1123 xfer->ux_actlen = 1; 1124 xfer->ux_status = USBD_NORMAL_COMPLETION; 1125 usb_transfer_complete(xfer); 1126 } 1127 1128 static uint8_t 1129 motg_speed(uint8_t speed) 1130 { 1131 switch(speed) { 1132 case USB_SPEED_LOW: 1133 return MUSB2_MASK_TI_SPEED_LO; 1134 case USB_SPEED_FULL: 1135 return MUSB2_MASK_TI_SPEED_FS; 1136 case USB_SPEED_HIGH: 1137 return MUSB2_MASK_TI_SPEED_HS; 1138 default: 1139 panic("motg: unknown speed %d", speed); 1140 /* NOTREACHED */ 1141 } 1142 } 1143 1144 static uint8_t 1145 motg_type(uint8_t type) 1146 { 1147 switch(type) { 1148 case UE_CONTROL: 1149 return MUSB2_MASK_TI_PROTO_CTRL; 1150 case UE_ISOCHRONOUS: 1151 return MUSB2_MASK_TI_PROTO_ISOC; 1152 case UE_BULK: 1153 return MUSB2_MASK_TI_PROTO_BULK; 1154 case UE_INTERRUPT: 1155 return MUSB2_MASK_TI_PROTO_INTR; 1156 default: 1157 panic("motg: unknown type %d", type); 1158 /* NOTREACHED */ 1159 } 1160 } 1161 1162 static void 1163 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1164 { 1165 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1166 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1167 struct usbd_device *dev = otgpipe->pipe.up_dev; 1168 int epnumber = otgpipe->hw_ep->ep_number; 1169 1170 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1171 if (dev->ud_myhsport) { 1172 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1173 dev->ud_myhsport->up_parent->ud_addr); 1174 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1175 dev->ud_myhsport->up_portno); 1176 } else { 1177 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1178 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1179 } 1180 UWRITE1(sc, MUSB2_REG_TXTI, 1181 motg_speed(dev->ud_speed) | 1182 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1183 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1184 ); 1185 if (epnumber == 0) { 1186 if (sc->sc_high_speed) { 1187 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1188 NAK_TO_CTRL_HIGH); 1189 } else { 1190 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1191 } 1192 } else { 1193 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1194 == UE_BULK) { 1195 if (sc->sc_high_speed) { 1196 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1197 NAK_TO_BULK_HIGH); 1198 } else { 1199 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1200 } 1201 } else { 1202 if (sc->sc_high_speed) { 1203 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1204 } else { 1205 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1206 } 1207 } 1208 } 1209 } 1210 1211 static void 1212 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1213 { 1214 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1215 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1216 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1217 int epnumber = otgpipe->hw_ep->ep_number; 1218 1219 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1220 if (dev->ud_myhsport) { 1221 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1222 dev->ud_myhsport->up_parent->ud_addr); 1223 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1224 dev->ud_myhsport->up_portno); 1225 } else { 1226 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1227 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1228 } 1229 UWRITE1(sc, MUSB2_REG_RXTI, 1230 motg_speed(dev->ud_speed) | 1231 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1232 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1233 ); 1234 if (epnumber == 0) { 1235 if (sc->sc_high_speed) { 1236 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1237 NAK_TO_CTRL_HIGH); 1238 } else { 1239 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1240 } 1241 } else { 1242 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1243 == UE_BULK) { 1244 if (sc->sc_high_speed) { 1245 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1246 NAK_TO_BULK_HIGH); 1247 } else { 1248 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1249 } 1250 } else { 1251 if (sc->sc_high_speed) { 1252 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1253 } else { 1254 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1255 } 1256 } 1257 } 1258 } 1259 1260 static usbd_status 1261 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1262 { 1263 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1264 usbd_status err; 1265 1266 /* Insert last in queue. */ 1267 mutex_enter(&sc->sc_lock); 1268 err = usb_insert_transfer(xfer); 1269 xfer->ux_status = USBD_NOT_STARTED; 1270 mutex_exit(&sc->sc_lock); 1271 if (err) 1272 return err; 1273 1274 /* 1275 * Pipe isn't running (otherwise err would be USBD_INPROG), 1276 * so start it first. 1277 */ 1278 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1279 } 1280 1281 static usbd_status 1282 motg_device_ctrl_start(struct usbd_xfer *xfer) 1283 { 1284 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1285 usbd_status err; 1286 mutex_enter(&sc->sc_lock); 1287 err = motg_device_ctrl_start1(sc); 1288 mutex_exit(&sc->sc_lock); 1289 if (err != USBD_IN_PROGRESS) 1290 return err; 1291 if (sc->sc_bus.ub_usepolling) 1292 motg_waitintr(sc, xfer); 1293 return USBD_IN_PROGRESS; 1294 } 1295 1296 static usbd_status 1297 motg_device_ctrl_start1(struct motg_softc *sc) 1298 { 1299 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1300 struct usbd_xfer *xfer = NULL; 1301 struct motg_pipe *otgpipe; 1302 usbd_status err = 0; 1303 1304 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1305 1306 KASSERT(mutex_owned(&sc->sc_lock)); 1307 if (sc->sc_dying) 1308 return USBD_IOERROR; 1309 1310 if (!sc->sc_connected) 1311 return USBD_IOERROR; 1312 1313 if (ep->xfer != NULL) { 1314 err = USBD_IN_PROGRESS; 1315 goto end; 1316 } 1317 /* locate the first pipe with work to do */ 1318 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1319 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1320 DPRINTFN(MD_CTRL, "pipe %p xfer %p status %d", 1321 otgpipe, xfer, (xfer != NULL) ? xfer->ux_status : 0, 0); 1322 1323 if (xfer != NULL) { 1324 /* move this pipe to the end of the list */ 1325 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1326 motg_pipe, ep_pipe_list); 1327 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1328 otgpipe, ep_pipe_list); 1329 break; 1330 } 1331 } 1332 if (xfer == NULL) { 1333 err = USBD_NOT_STARTED; 1334 goto end; 1335 } 1336 xfer->ux_status = USBD_IN_PROGRESS; 1337 KASSERT(otgpipe == (struct motg_pipe *)xfer->ux_pipe); 1338 KASSERT(otgpipe->hw_ep == ep); 1339 #ifdef DIAGNOSTIC 1340 if (!(xfer->ux_rqflags & URQ_REQUEST)) 1341 panic("motg_device_ctrl_transfer: not a request"); 1342 #endif 1343 // KASSERT(xfer->ux_actlen == 0); 1344 xfer->ux_actlen = 0; 1345 1346 ep->xfer = xfer; 1347 ep->datalen = xfer->ux_length; 1348 if (ep->datalen > 0) 1349 ep->data = xfer->ux_buf; 1350 else 1351 ep->data = NULL; 1352 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1353 (ep->datalen % 64) == 0) 1354 ep->need_short_xfer = 1; 1355 else 1356 ep->need_short_xfer = 0; 1357 /* now we need send this request */ 1358 DPRINTFN(MD_CTRL, 1359 "xfer %p send data %p len %d short %d", 1360 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1361 DPRINTFN(MD_CTRL, 1362 "xfer %p ... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1363 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1364 KASSERT(ep->phase == IDLE); 1365 ep->phase = SETUP; 1366 /* select endpoint 0 */ 1367 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1368 /* fifo should be empty at this point */ 1369 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1370 /* send data */ 1371 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1372 KASSERT(sizeof(xfer->ux_request) == 8); 1373 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1374 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1375 1376 motg_setup_endpoint_tx(xfer); 1377 /* start transaction */ 1378 UWRITE1(sc, MUSB2_REG_TXCSRL, 1379 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1380 1381 end: 1382 if (err) 1383 return err; 1384 1385 return USBD_IN_PROGRESS; 1386 } 1387 1388 static void 1389 motg_device_ctrl_read(struct usbd_xfer *xfer) 1390 { 1391 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1392 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1393 /* assume endpoint already selected */ 1394 motg_setup_endpoint_rx(xfer); 1395 /* start transaction */ 1396 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1397 otgpipe->hw_ep->phase = DATA_IN; 1398 } 1399 1400 static void 1401 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1402 { 1403 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1404 struct usbd_xfer *xfer = ep->xfer; 1405 uint8_t csr; 1406 int datalen, max_datalen; 1407 char *data; 1408 bool got_short; 1409 usbd_status new_status = USBD_IN_PROGRESS; 1410 1411 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1412 1413 KASSERT(mutex_owned(&sc->sc_lock)); 1414 1415 #ifdef DIAGNOSTIC 1416 if (ep->phase != DATA_IN && 1417 ep->phase != STATUS_IN) 1418 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1419 #endif 1420 /* select endpoint 0 */ 1421 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1422 1423 /* read out FIFO status */ 1424 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1425 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1426 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1427 1428 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1429 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1430 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1431 1432 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1433 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1434 new_status = USBD_TIMEOUT; /* XXX */ 1435 goto complete; 1436 } 1437 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1438 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1439 new_status = USBD_STALLED; 1440 else 1441 new_status = USBD_IOERROR; 1442 /* clear status */ 1443 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1444 goto complete; 1445 } 1446 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1447 return; /* no data yet */ 1448 1449 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1450 goto complete; 1451 1452 if (ep->phase == STATUS_IN) { 1453 new_status = USBD_NORMAL_COMPLETION; 1454 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1455 goto complete; 1456 } 1457 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1458 DPRINTFN(MD_CTRL, "phase %d datalen %d", ep->phase, datalen, 0, 0); 1459 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1460 max_datalen = min(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1461 ep->datalen); 1462 if (datalen > max_datalen) { 1463 new_status = USBD_IOERROR; 1464 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1465 goto complete; 1466 } 1467 got_short = (datalen < max_datalen); 1468 if (datalen > 0) { 1469 KASSERT(ep->phase == DATA_IN); 1470 data = ep->data; 1471 ep->data += datalen; 1472 ep->datalen -= datalen; 1473 xfer->ux_actlen += datalen; 1474 if (((vaddr_t)data & 0x3) == 0 && 1475 (datalen >> 2) > 0) { 1476 DPRINTFN(MD_CTRL, "r4 data %p len %d", data, datalen, 1477 0, 0); 1478 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1479 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1480 data += (datalen & ~0x3); 1481 datalen -= (datalen & ~0x3); 1482 } 1483 DPRINTFN(MD_CTRL, "r1 data %p len %d", data, datalen, 0, 0); 1484 if (datalen) { 1485 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1486 MUSB2_REG_EPFIFO(0), data, datalen); 1487 } 1488 } 1489 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1490 KASSERT(ep->phase == DATA_IN); 1491 if (got_short || (ep->datalen == 0)) { 1492 if (ep->need_short_xfer == 0) { 1493 ep->phase = STATUS_OUT; 1494 UWRITE1(sc, MUSB2_REG_TXCSRH, 1495 UREAD1(sc, MUSB2_REG_TXCSRH) | 1496 MUSB2_MASK_CSR0H_PING_DIS); 1497 motg_setup_endpoint_tx(xfer); 1498 UWRITE1(sc, MUSB2_REG_TXCSRL, 1499 MUSB2_MASK_CSR0L_STATUSPKT | 1500 MUSB2_MASK_CSR0L_TXPKTRDY); 1501 return; 1502 } 1503 ep->need_short_xfer = 0; 1504 } 1505 motg_device_ctrl_read(xfer); 1506 return; 1507 complete: 1508 ep->phase = IDLE; 1509 ep->xfer = NULL; 1510 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1511 KASSERT(new_status != USBD_IN_PROGRESS); 1512 xfer->ux_status = new_status; 1513 usb_transfer_complete(xfer); 1514 } 1515 motg_device_ctrl_start1(sc); 1516 } 1517 1518 static void 1519 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1520 { 1521 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1522 struct usbd_xfer *xfer = ep->xfer; 1523 uint8_t csr; 1524 int datalen; 1525 char *data; 1526 usbd_status new_status = USBD_IN_PROGRESS; 1527 1528 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1529 1530 KASSERT(mutex_owned(&sc->sc_lock)); 1531 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1532 motg_device_ctrl_intr_rx(sc); 1533 return; 1534 } 1535 1536 #ifdef DIAGNOSTIC 1537 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1538 ep->phase != STATUS_OUT) 1539 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1540 #endif 1541 /* select endpoint 0 */ 1542 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1543 1544 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1545 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1546 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1547 1548 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1549 /* command not accepted */ 1550 new_status = USBD_STALLED; 1551 /* clear status */ 1552 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1553 goto complete; 1554 } 1555 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1556 new_status = USBD_TIMEOUT; /* XXX */ 1557 /* flush fifo */ 1558 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1559 UWRITE1(sc, MUSB2_REG_TXCSRH, 1560 UREAD1(sc, MUSB2_REG_TXCSRH) | 1561 MUSB2_MASK_CSR0H_FFLUSH); 1562 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1563 } 1564 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1565 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1566 goto complete; 1567 } 1568 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1569 new_status = USBD_IOERROR; 1570 /* clear status */ 1571 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1572 goto complete; 1573 } 1574 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1575 /* data still not sent */ 1576 return; 1577 } 1578 if (xfer == NULL) 1579 goto complete; 1580 if (ep->phase == STATUS_OUT) { 1581 /* 1582 * we have sent status and got no error; 1583 * declare transfer complete 1584 */ 1585 DPRINTFN(MD_CTRL, "xfer %p status %d complete", xfer, 1586 xfer->ux_status, 0, 0); 1587 new_status = USBD_NORMAL_COMPLETION; 1588 goto complete; 1589 } 1590 if (ep->datalen == 0) { 1591 if (ep->need_short_xfer) { 1592 ep->need_short_xfer = 0; 1593 /* one more data phase */ 1594 if (xfer->ux_request.bmRequestType & UT_READ) { 1595 DPRINTFN(MD_CTRL, "xfer %p to DATA_IN", xfer, 1596 0, 0, 0); 1597 motg_device_ctrl_read(xfer); 1598 return; 1599 } /* else fall back to DATA_OUT */ 1600 } else { 1601 DPRINTFN(MD_CTRL, "xfer %p to STATUS_IN, csrh 0x%x", 1602 xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1603 ep->phase = STATUS_IN; 1604 UWRITE1(sc, MUSB2_REG_RXCSRH, 1605 UREAD1(sc, MUSB2_REG_RXCSRH) | 1606 MUSB2_MASK_CSR0H_PING_DIS); 1607 motg_setup_endpoint_rx(xfer); 1608 UWRITE1(sc, MUSB2_REG_TXCSRL, 1609 MUSB2_MASK_CSR0L_STATUSPKT | 1610 MUSB2_MASK_CSR0L_REQPKT); 1611 return; 1612 } 1613 } 1614 if (xfer->ux_request.bmRequestType & UT_READ) { 1615 motg_device_ctrl_read(xfer); 1616 return; 1617 } 1618 /* setup a dataout phase */ 1619 datalen = min(ep->datalen, 1620 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1621 ep->phase = DATA_OUT; 1622 DPRINTFN(MD_CTRL, "xfer %p to DATA_OUT, csrh 0x%x", xfer, 1623 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1624 if (datalen) { 1625 data = ep->data; 1626 ep->data += datalen; 1627 ep->datalen -= datalen; 1628 xfer->ux_actlen += datalen; 1629 if (((vaddr_t)data & 0x3) == 0 && 1630 (datalen >> 2) > 0) { 1631 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1632 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1633 data += (datalen & ~0x3); 1634 datalen -= (datalen & ~0x3); 1635 } 1636 if (datalen) { 1637 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1638 MUSB2_REG_EPFIFO(0), data, datalen); 1639 } 1640 } 1641 /* send data */ 1642 motg_setup_endpoint_tx(xfer); 1643 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1644 return; 1645 1646 complete: 1647 ep->phase = IDLE; 1648 ep->xfer = NULL; 1649 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1650 KASSERT(new_status != USBD_IN_PROGRESS); 1651 xfer->ux_status = new_status; 1652 usb_transfer_complete(xfer); 1653 } 1654 motg_device_ctrl_start1(sc); 1655 } 1656 1657 /* Abort a device control request. */ 1658 void 1659 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1660 { 1661 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1662 1663 motg_device_xfer_abort(xfer); 1664 } 1665 1666 /* Close a device control pipe */ 1667 void 1668 motg_device_ctrl_close(struct usbd_pipe *pipe) 1669 { 1670 struct motg_softc *sc __diagused = pipe->up_dev->ud_bus->ub_hcpriv; 1671 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1672 struct motg_pipe *otgpipeiter; 1673 1674 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1675 1676 KASSERT(mutex_owned(&sc->sc_lock)); 1677 KASSERT(otgpipe->hw_ep->xfer == NULL || 1678 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1679 1680 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1681 if (otgpipeiter == otgpipe) { 1682 /* remove from list */ 1683 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1684 motg_pipe, ep_pipe_list); 1685 otgpipe->hw_ep->refcount--; 1686 /* we're done */ 1687 return; 1688 } 1689 } 1690 panic("motg_device_ctrl_close: not found"); 1691 } 1692 1693 void 1694 motg_device_ctrl_done(struct usbd_xfer *xfer) 1695 { 1696 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->ux_pipe; 1697 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1698 1699 KASSERT(otgpipe->hw_ep->xfer != xfer); 1700 } 1701 1702 static usbd_status 1703 motg_device_data_transfer(struct usbd_xfer *xfer) 1704 { 1705 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1706 usbd_status err; 1707 1708 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1709 1710 /* Insert last in queue. */ 1711 mutex_enter(&sc->sc_lock); 1712 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1713 err = usb_insert_transfer(xfer); 1714 xfer->ux_status = USBD_NOT_STARTED; 1715 mutex_exit(&sc->sc_lock); 1716 if (err) 1717 return err; 1718 1719 /* 1720 * Pipe isn't running (otherwise err would be USBD_INPROG), 1721 * so start it first. 1722 */ 1723 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1724 } 1725 1726 static usbd_status 1727 motg_device_data_start(struct usbd_xfer *xfer) 1728 { 1729 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1730 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1731 usbd_status err; 1732 1733 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1734 1735 mutex_enter(&sc->sc_lock); 1736 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1737 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1738 mutex_exit(&sc->sc_lock); 1739 if (err != USBD_IN_PROGRESS) 1740 return err; 1741 if (sc->sc_bus.ub_usepolling) 1742 motg_waitintr(sc, xfer); 1743 return USBD_IN_PROGRESS; 1744 } 1745 1746 static usbd_status 1747 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1748 { 1749 struct usbd_xfer *xfer = NULL; 1750 struct motg_pipe *otgpipe; 1751 usbd_status err = 0; 1752 uint32_t val __diagused; 1753 1754 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1755 1756 KASSERT(mutex_owned(&sc->sc_lock)); 1757 if (sc->sc_dying) 1758 return USBD_IOERROR; 1759 1760 if (!sc->sc_connected) 1761 return USBD_IOERROR; 1762 1763 if (ep->xfer != NULL) { 1764 err = USBD_IN_PROGRESS; 1765 goto end; 1766 } 1767 /* locate the first pipe with work to do */ 1768 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1769 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1770 DPRINTFN(MD_BULK, "pipe %p xfer %p status %d", otgpipe, xfer, 1771 (xfer != NULL) ? xfer->ux_status : 0, 0); 1772 if (xfer != NULL) { 1773 /* move this pipe to the end of the list */ 1774 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1775 motg_pipe, ep_pipe_list); 1776 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1777 otgpipe, ep_pipe_list); 1778 break; 1779 } 1780 } 1781 if (xfer == NULL) { 1782 err = USBD_NOT_STARTED; 1783 goto end; 1784 } 1785 xfer->ux_status = USBD_IN_PROGRESS; 1786 KASSERT(otgpipe == (struct motg_pipe *)xfer->ux_pipe); 1787 KASSERT(otgpipe->hw_ep == ep); 1788 #ifdef DIAGNOSTIC 1789 if (xfer->ux_rqflags & URQ_REQUEST) 1790 panic("motg_device_data_transfer: a request"); 1791 #endif 1792 // KASSERT(xfer->ux_actlen == 0); 1793 xfer->ux_actlen = 0; 1794 1795 ep->xfer = xfer; 1796 ep->datalen = xfer->ux_length; 1797 KASSERT(ep->datalen > 0); 1798 ep->data = xfer->ux_buf; 1799 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1800 (ep->datalen % 64) == 0) 1801 ep->need_short_xfer = 1; 1802 else 1803 ep->need_short_xfer = 0; 1804 /* now we need send this request */ 1805 DPRINTFN(MD_BULK, 1806 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1807 "xfer %p in data %p len %d short %d" : 1808 "xfer %p out data %p len %d short %d", 1809 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1810 DPRINTFN(MD_BULK, "... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1811 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1812 KASSERT(ep->phase == IDLE); 1813 /* select endpoint */ 1814 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1815 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1816 == UE_DIR_IN) { 1817 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1818 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1819 motg_device_data_read(xfer); 1820 } else { 1821 ep->phase = DATA_OUT; 1822 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1823 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1824 motg_device_data_write(xfer); 1825 } 1826 end: 1827 if (err) 1828 return err; 1829 1830 return USBD_IN_PROGRESS; 1831 } 1832 1833 static void 1834 motg_device_data_read(struct usbd_xfer *xfer) 1835 { 1836 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1837 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1838 uint32_t val; 1839 1840 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1841 1842 KASSERT(mutex_owned(&sc->sc_lock)); 1843 /* assume endpoint already selected */ 1844 motg_setup_endpoint_rx(xfer); 1845 /* Max packet size */ 1846 UWRITE2(sc, MUSB2_REG_RXMAXP, 1847 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1848 /* Data Toggle */ 1849 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1850 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1851 if (otgpipe->nexttoggle) 1852 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1853 else 1854 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1855 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1856 1857 DPRINTFN(MD_BULK, "%p to DATA_IN on ep %d, csrh 0x%x", 1858 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1859 /* start transaction */ 1860 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1861 otgpipe->hw_ep->phase = DATA_IN; 1862 } 1863 1864 static void 1865 motg_device_data_write(struct usbd_xfer *xfer) 1866 { 1867 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1868 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1869 struct motg_hw_ep *ep = otgpipe->hw_ep; 1870 int datalen; 1871 char *data; 1872 uint32_t val; 1873 1874 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1875 1876 KASSERT(xfer!=NULL); 1877 KASSERT(mutex_owned(&sc->sc_lock)); 1878 1879 datalen = min(ep->datalen, 1880 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1881 ep->phase = DATA_OUT; 1882 DPRINTFN(MD_BULK, "%p to DATA_OUT on ep %d, len %d csrh 0x%x", 1883 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH)); 1884 1885 /* assume endpoint already selected */ 1886 /* write data to fifo */ 1887 data = ep->data; 1888 ep->data += datalen; 1889 ep->datalen -= datalen; 1890 xfer->ux_actlen += datalen; 1891 if (((vaddr_t)data & 0x3) == 0 && 1892 (datalen >> 2) > 0) { 1893 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1894 MUSB2_REG_EPFIFO(ep->ep_number), 1895 (void *)data, datalen >> 2); 1896 data += (datalen & ~0x3); 1897 datalen -= (datalen & ~0x3); 1898 } 1899 if (datalen) { 1900 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1901 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1902 } 1903 1904 motg_setup_endpoint_tx(xfer); 1905 /* Max packet size */ 1906 UWRITE2(sc, MUSB2_REG_TXMAXP, 1907 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1908 /* Data Toggle */ 1909 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1910 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1911 if (otgpipe->nexttoggle) 1912 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1913 else 1914 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1915 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1916 1917 /* start transaction */ 1918 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1919 } 1920 1921 static void 1922 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1923 { 1924 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1925 struct usbd_xfer *xfer = ep->xfer; 1926 uint8_t csr; 1927 int datalen, max_datalen; 1928 char *data; 1929 bool got_short; 1930 usbd_status new_status = USBD_IN_PROGRESS; 1931 1932 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1933 1934 KASSERT(mutex_owned(&sc->sc_lock)); 1935 KASSERT(ep->ep_number == epnumber); 1936 1937 DPRINTFN(MD_BULK, "on ep %d", epnumber, 0, 0, 0); 1938 /* select endpoint */ 1939 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1940 1941 /* read out FIFO status */ 1942 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1943 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr ,0 ,0); 1944 1945 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1946 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1947 return; 1948 1949 #ifdef DIAGNOSTIC 1950 if (ep->phase != DATA_IN) 1951 panic("motg_device_intr_rx: bad phase %d", ep->phase); 1952 #endif 1953 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1954 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1955 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1956 1957 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1958 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1959 new_status = USBD_TIMEOUT; /* XXX */ 1960 goto complete; 1961 } 1962 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1963 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1964 new_status = USBD_STALLED; 1965 else 1966 new_status = USBD_IOERROR; 1967 /* clear status */ 1968 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1969 goto complete; 1970 } 1971 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1972 1973 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1974 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1975 goto complete; 1976 } 1977 1978 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1979 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1980 1981 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1982 DPRINTFN(MD_BULK, "phase %d datalen %d", ep->phase, datalen ,0 ,0); 1983 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1984 max_datalen = min( 1985 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1986 ep->datalen); 1987 if (datalen > max_datalen) { 1988 new_status = USBD_IOERROR; 1989 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1990 goto complete; 1991 } 1992 got_short = (datalen < max_datalen); 1993 if (datalen > 0) { 1994 KASSERT(ep->phase == DATA_IN); 1995 data = ep->data; 1996 ep->data += datalen; 1997 ep->datalen -= datalen; 1998 xfer->ux_actlen += datalen; 1999 if (((vaddr_t)data & 0x3) == 0 && 2000 (datalen >> 2) > 0) { 2001 DPRINTFN(MD_BULK, "r4 data %p len %d", data, datalen, 2002 0, 0); 2003 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2004 MUSB2_REG_EPFIFO(ep->ep_number), 2005 (void *)data, datalen >> 2); 2006 data += (datalen & ~0x3); 2007 datalen -= (datalen & ~0x3); 2008 } 2009 DPRINTFN(MD_BULK, "r1 data %p len %d", data, datalen ,0 ,0); 2010 if (datalen) { 2011 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2012 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2013 } 2014 } 2015 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2016 KASSERT(ep->phase == DATA_IN); 2017 if (got_short || (ep->datalen == 0)) { 2018 if (ep->need_short_xfer == 0) { 2019 new_status = USBD_NORMAL_COMPLETION; 2020 goto complete; 2021 } 2022 ep->need_short_xfer = 0; 2023 } 2024 motg_device_data_read(xfer); 2025 return; 2026 complete: 2027 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2028 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2029 ep->phase = IDLE; 2030 ep->xfer = NULL; 2031 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2032 KASSERT(new_status != USBD_IN_PROGRESS); 2033 xfer->ux_status = new_status; 2034 usb_transfer_complete(xfer); 2035 } 2036 motg_device_data_start1(sc, ep); 2037 } 2038 2039 static void 2040 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2041 { 2042 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2043 struct usbd_xfer *xfer = ep->xfer; 2044 uint8_t csr; 2045 struct motg_pipe *otgpipe; 2046 usbd_status new_status = USBD_IN_PROGRESS; 2047 2048 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2049 2050 KASSERT(mutex_owned(&sc->sc_lock)); 2051 KASSERT(ep->ep_number == epnumber); 2052 2053 DPRINTFN(MD_BULK, " on ep %d", epnumber, 0, 0, 0); 2054 /* select endpoint */ 2055 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2056 2057 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2058 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr, 0, 0); 2059 2060 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2061 /* command not accepted */ 2062 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2063 new_status = USBD_STALLED; 2064 else 2065 new_status = USBD_IOERROR; 2066 /* clear status */ 2067 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2068 goto complete; 2069 } 2070 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2071 new_status = USBD_TIMEOUT; /* XXX */ 2072 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2073 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2074 /* flush fifo */ 2075 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2076 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2077 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2078 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2079 delay(1000); 2080 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2081 DPRINTFN(MD_BULK, "TX fifo flush ep %d CSR 0x%x", 2082 epnumber, csr, 0, 0); 2083 } 2084 goto complete; 2085 } 2086 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2087 /* data still not sent */ 2088 return; 2089 } 2090 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2091 goto complete; 2092 #ifdef DIAGNOSTIC 2093 if (ep->phase != DATA_OUT) 2094 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2095 #endif 2096 2097 otgpipe = (struct motg_pipe *)xfer->ux_pipe; 2098 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2099 2100 if (ep->datalen == 0) { 2101 if (ep->need_short_xfer) { 2102 ep->need_short_xfer = 0; 2103 /* one more data phase */ 2104 } else { 2105 new_status = USBD_NORMAL_COMPLETION; 2106 goto complete; 2107 } 2108 } 2109 motg_device_data_write(xfer); 2110 return; 2111 2112 complete: 2113 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2114 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2115 #ifdef DIAGNOSTIC 2116 if (xfer && xfer->ux_status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2117 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2118 #endif 2119 ep->phase = IDLE; 2120 ep->xfer = NULL; 2121 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2122 KASSERT(new_status != USBD_IN_PROGRESS); 2123 xfer->ux_status = new_status; 2124 usb_transfer_complete(xfer); 2125 } 2126 motg_device_data_start1(sc, ep); 2127 } 2128 2129 /* Abort a device control request. */ 2130 void 2131 motg_device_data_abort(struct usbd_xfer *xfer) 2132 { 2133 #ifdef DIAGNOSTIC 2134 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2135 #endif 2136 KASSERT(mutex_owned(&sc->sc_lock)); 2137 2138 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2139 2140 motg_device_xfer_abort(xfer); 2141 } 2142 2143 /* Close a device control pipe */ 2144 void 2145 motg_device_data_close(struct usbd_pipe *pipe) 2146 { 2147 struct motg_softc *sc __diagused = pipe->up_dev->ud_bus->ub_hcpriv; 2148 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2149 struct motg_pipe *otgpipeiter; 2150 2151 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2152 2153 KASSERT(mutex_owned(&sc->sc_lock)); 2154 KASSERT(otgpipe->hw_ep->xfer == NULL || 2155 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2156 2157 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2158 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2159 if (otgpipeiter == otgpipe) { 2160 /* remove from list */ 2161 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2162 motg_pipe, ep_pipe_list); 2163 otgpipe->hw_ep->refcount--; 2164 /* we're done */ 2165 return; 2166 } 2167 } 2168 panic("motg_device_data_close: not found"); 2169 } 2170 2171 void 2172 motg_device_data_done(struct usbd_xfer *xfer) 2173 { 2174 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->ux_pipe; 2175 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2176 2177 KASSERT(otgpipe->hw_ep->xfer != xfer); 2178 } 2179 2180 /* 2181 * Wait here until controller claims to have an interrupt. 2182 * Then call motg_intr and return. Use timeout to avoid waiting 2183 * too long. 2184 * Only used during boot when interrupts are not enabled yet. 2185 */ 2186 void 2187 motg_waitintr(struct motg_softc *sc, struct usbd_xfer *xfer) 2188 { 2189 int timo = xfer->ux_timeout; 2190 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2191 2192 mutex_enter(&sc->sc_lock); 2193 2194 DPRINTF("timeout = %dms", timo, 0, 0, 0); 2195 2196 for (; timo >= 0; timo--) { 2197 mutex_exit(&sc->sc_lock); 2198 usb_delay_ms(&sc->sc_bus, 1); 2199 mutex_spin_enter(&sc->sc_intr_lock); 2200 motg_poll(&sc->sc_bus); 2201 mutex_spin_exit(&sc->sc_intr_lock); 2202 mutex_enter(&sc->sc_lock); 2203 if (xfer->ux_status != USBD_IN_PROGRESS) 2204 goto done; 2205 } 2206 2207 /* Timeout */ 2208 DPRINTF("timeout", 0, 0, 0, 0); 2209 panic("motg_waitintr: timeout"); 2210 /* XXX handle timeout ! */ 2211 2212 done: 2213 mutex_exit(&sc->sc_lock); 2214 } 2215 2216 void 2217 motg_device_clear_toggle(struct usbd_pipe *pipe) 2218 { 2219 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2220 otgpipe->nexttoggle = 0; 2221 } 2222 2223 /* Abort a device control request. */ 2224 static void 2225 motg_device_xfer_abort(struct usbd_xfer *xfer) 2226 { 2227 int wake; 2228 uint8_t csr; 2229 struct motg_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2230 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 2231 KASSERT(mutex_owned(&sc->sc_lock)); 2232 2233 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2234 2235 if (xfer->ux_hcflags & UXFER_ABORTING) { 2236 DPRINTF("already aborting", 0, 0, 0, 0); 2237 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2238 while (xfer->ux_hcflags & UXFER_ABORTING) 2239 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2240 return; 2241 } 2242 xfer->ux_hcflags |= UXFER_ABORTING; 2243 if (otgpipe->hw_ep->xfer == xfer) { 2244 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2245 otgpipe->hw_ep->xfer = NULL; 2246 if (otgpipe->hw_ep->ep_number > 0) { 2247 /* select endpoint */ 2248 UWRITE1(sc, MUSB2_REG_EPINDEX, 2249 otgpipe->hw_ep->ep_number); 2250 if (otgpipe->hw_ep->phase == DATA_OUT) { 2251 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2252 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2253 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2254 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2255 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2256 } 2257 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2258 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2259 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2260 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2261 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2262 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2263 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2264 } 2265 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2266 } 2267 otgpipe->hw_ep->phase = IDLE; 2268 } 2269 } 2270 xfer->ux_status = USBD_CANCELLED; /* make software ignore it */ 2271 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2272 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2273 usb_transfer_complete(xfer); 2274 if (wake) 2275 cv_broadcast(&xfer->ux_hccv); 2276 } 2277
Indexes created Mon Oct 13 08:09:50 GMT 2025