motg.c revision 1.12.2.21
1 /* $NetBSD: motg.c,v 1.12.2.21 2015/10/20 15:31:21 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include "opt_motg.h" 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.12.2.21 2015/10/20 15:31:21 skrll Exp $"); 46 47 #include <sys/param.h> 48 49 #include <sys/bus.h> 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usbhist.h> 67 68 #ifdef MOTG_ALLWINNER 69 #include <arch/arm/allwinner/awin_otgreg.h> 70 #else 71 #include <dev/usb/motgreg.h> 72 #endif 73 74 #include <dev/usb/motgvar.h> 75 #include <dev/usb/usbroothub.h> 76 77 #ifdef USB_DEBUG 78 #ifndef MOTG_DEBUG 79 #define motgdebug 0 80 #else 81 int motgdebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 91 SYSCTL_DESCR("motg global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* MOTG_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #define MD_ROOT 0x0002 114 #define MD_CTRL 0x0004 115 #define MD_BULK 0x0008 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 119 #define MOTGHIST_FUNC() USBHIST_FUNC() 120 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 121 122 123 /* various timeouts, for various speeds */ 124 /* control NAK timeouts */ 125 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 126 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 127 128 /* intr/iso polling intervals */ 129 #define POLL_TO 100 /* 100 frames, about 0.1s */ 130 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 131 132 /* bulk NAK timeouts */ 133 #define NAK_TO_BULK 0 /* disabled */ 134 #define NAK_TO_BULK_HIGH 0 135 136 static void motg_hub_change(struct motg_softc *); 137 138 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 139 static usbd_status motg_root_intr_start(struct usbd_xfer *); 140 static void motg_root_intr_abort(struct usbd_xfer *); 141 static void motg_root_intr_close(struct usbd_pipe *); 142 static void motg_root_intr_done(struct usbd_xfer *); 143 144 static usbd_status motg_open(struct usbd_pipe *); 145 static void motg_poll(struct usbd_bus *); 146 static void motg_softintr(void *); 147 static struct usbd_xfer * 148 motg_allocx(struct usbd_bus *, unsigned int); 149 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 150 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 151 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 152 void *, int); 153 154 static void motg_noop(struct usbd_pipe *pipe); 155 static usbd_status motg_portreset(struct motg_softc*); 156 157 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 158 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 159 static void motg_device_ctrl_abort(struct usbd_xfer *); 160 static void motg_device_ctrl_close(struct usbd_pipe *); 161 static void motg_device_ctrl_done(struct usbd_xfer *); 162 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 163 static void motg_device_ctrl_read(struct usbd_xfer *); 164 static void motg_device_ctrl_intr_rx(struct motg_softc *); 165 static void motg_device_ctrl_intr_tx(struct motg_softc *); 166 167 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 168 static usbd_status motg_device_data_start(struct usbd_xfer *); 169 static usbd_status motg_device_data_start1(struct motg_softc *, 170 struct motg_hw_ep *); 171 static void motg_device_data_abort(struct usbd_xfer *); 172 static void motg_device_data_close(struct usbd_pipe *); 173 static void motg_device_data_done(struct usbd_xfer *); 174 static void motg_device_intr_rx(struct motg_softc *, int); 175 static void motg_device_intr_tx(struct motg_softc *, int); 176 static void motg_device_data_read(struct usbd_xfer *); 177 static void motg_device_data_write(struct usbd_xfer *); 178 179 static void motg_waitintr(struct motg_softc *, struct usbd_xfer *); 180 static void motg_device_clear_toggle(struct usbd_pipe *); 181 static void motg_device_xfer_abort(struct usbd_xfer *); 182 183 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 184 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 185 #define UWRITE1(sc, r, x) \ 186 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 187 } while (/*CONSTCOND*/0) 188 #define UWRITE2(sc, r, x) \ 189 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 190 } while (/*CONSTCOND*/0) 191 #define UWRITE4(sc, r, x) \ 192 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 193 } while (/*CONSTCOND*/0) 194 195 static __inline uint32_t 196 UREAD1(struct motg_softc *sc, bus_size_t r) 197 { 198 199 UBARR(sc); 200 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 201 } 202 static __inline uint32_t 203 UREAD2(struct motg_softc *sc, bus_size_t r) 204 { 205 206 UBARR(sc); 207 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 208 } 209 210 #if 0 211 static __inline uint32_t 212 UREAD4(struct motg_softc *sc, bus_size_t r) 213 { 214 215 UBARR(sc); 216 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 217 } 218 #endif 219 220 static void 221 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 222 { 223 uint8_t val; 224 225 val = UREAD1(sc, MUSB2_REG_POWER); 226 if (on) 227 val |= MUSB2_MASK_SOFTC; 228 else 229 val &= ~MUSB2_MASK_SOFTC; 230 231 UWRITE1(sc, MUSB2_REG_POWER, val); 232 } 233 234 const struct usbd_bus_methods motg_bus_methods = { 235 .ubm_open = motg_open, 236 .ubm_softint = motg_softintr, 237 .ubm_dopoll = motg_poll, 238 .ubm_allocx = motg_allocx, 239 .ubm_freex = motg_freex, 240 .ubm_getlock = motg_get_lock, 241 .ubm_rhctrl = motg_roothub_ctrl, 242 }; 243 244 const struct usbd_pipe_methods motg_root_intr_methods = { 245 .upm_transfer = motg_root_intr_transfer, 246 .upm_start = motg_root_intr_start, 247 .upm_abort = motg_root_intr_abort, 248 .upm_close = motg_root_intr_close, 249 .upm_cleartoggle = motg_noop, 250 .upm_done = motg_root_intr_done, 251 }; 252 253 const struct usbd_pipe_methods motg_device_ctrl_methods = { 254 .upm_transfer = motg_device_ctrl_transfer, 255 .upm_start = motg_device_ctrl_start, 256 .upm_abort = motg_device_ctrl_abort, 257 .upm_close = motg_device_ctrl_close, 258 .upm_cleartoggle = motg_noop, 259 .upm_done = motg_device_ctrl_done, 260 }; 261 262 const struct usbd_pipe_methods motg_device_data_methods = { 263 .upm_transfer = motg_device_data_transfer, 264 .upm_start = motg_device_data_start, 265 .upm_abort = motg_device_data_abort, 266 .upm_close = motg_device_data_close, 267 .upm_cleartoggle = motg_device_clear_toggle, 268 .upm_done = motg_device_data_done, 269 }; 270 271 int 272 motg_init(struct motg_softc *sc) 273 { 274 uint32_t nrx, ntx, val; 275 int dynfifo; 276 int offset, i; 277 278 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 279 280 if (sc->sc_mode == MOTG_MODE_DEVICE) 281 return ENOTSUP; /* not supported */ 282 283 /* disable all interrupts */ 284 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 285 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 286 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 287 /* disable pullup */ 288 289 musbotg_pull_common(sc, 0); 290 291 #ifdef MUSB2_REG_RXDBDIS 292 /* disable double packet buffering XXX what's this ? */ 293 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 294 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 295 #endif 296 297 /* enable HighSpeed and ISO Update flags */ 298 299 UWRITE1(sc, MUSB2_REG_POWER, 300 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 301 302 if (sc->sc_mode == MOTG_MODE_DEVICE) { 303 /* clear Session bit, if set */ 304 val = UREAD1(sc, MUSB2_REG_DEVCTL); 305 val &= ~MUSB2_MASK_SESS; 306 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 307 } else { 308 /* Enter session for Host mode */ 309 val = UREAD1(sc, MUSB2_REG_DEVCTL); 310 val |= MUSB2_MASK_SESS; 311 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 312 } 313 delay(1000); 314 DPRINTF("DEVCTL 0x%x", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 315 316 /* disable testmode */ 317 318 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 319 320 #ifdef MUSB2_REG_MISC 321 /* set default value */ 322 323 UWRITE1(sc, MUSB2_REG_MISC, 0); 324 #endif 325 326 /* select endpoint index 0 */ 327 328 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 329 330 if (sc->sc_ep_max == 0) { 331 /* read out number of endpoints */ 332 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 333 334 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 335 336 /* these numbers exclude the control endpoint */ 337 338 DPRINTFN(1,"RX/TX endpoints: %u/%u", nrx, ntx, 0, 0); 339 340 sc->sc_ep_max = MAX(nrx, ntx); 341 } else { 342 nrx = ntx = sc->sc_ep_max; 343 } 344 if (sc->sc_ep_max == 0) { 345 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 346 return -1; 347 } 348 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 349 /* read out configuration data */ 350 val = UREAD1(sc, MUSB2_REG_CONFDATA); 351 352 DPRINTF("Config Data: 0x%02x", val, 0, 0, 0); 353 354 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 355 356 if (dynfifo) { 357 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 358 "assuming 16Kbytes of FIFO RAM\n"); 359 } 360 361 DPRINTF("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 362 363 /* initialise endpoint profiles */ 364 sc->sc_in_ep[0].ep_fifo_size = 64; 365 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 366 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 367 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 368 offset = 64; 369 370 for (i = 1; i <= sc->sc_ep_max; i++) { 371 int fiforx_size, fifotx_size, fifo_size; 372 373 /* select endpoint */ 374 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 375 376 if (sc->sc_ep_fifosize) { 377 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 378 } else { 379 val = UREAD1(sc, MUSB2_REG_FSIZE); 380 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 381 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 382 } 383 384 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d", 385 i, fifotx_size, fiforx_size, dynfifo); 386 387 if (dynfifo) { 388 if (sc->sc_ep_fifosize) { 389 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 390 } else { 391 if (i < 3) { 392 fifo_size = 12; /* 4K */ 393 } else if (i < 10) { 394 fifo_size = 10; /* 1K */ 395 } else { 396 fifo_size = 7; /* 128 bytes */ 397 } 398 } 399 if (fiforx_size && (i <= nrx)) { 400 fiforx_size = fifo_size; 401 if (fifo_size > 7) { 402 #if 0 403 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 404 MUSB2_VAL_FIFOSZ(fifo_size) | 405 MUSB2_MASK_FIFODB); 406 #else 407 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 408 MUSB2_VAL_FIFOSZ(fifo_size)); 409 #endif 410 } else { 411 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 412 MUSB2_VAL_FIFOSZ(fifo_size)); 413 } 414 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 415 offset >> 3); 416 offset += (1 << fiforx_size); 417 } 418 if (fifotx_size && (i <= ntx)) { 419 fifotx_size = fifo_size; 420 if (fifo_size > 7) { 421 #if 0 422 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 423 MUSB2_VAL_FIFOSZ(fifo_size) | 424 MUSB2_MASK_FIFODB); 425 #else 426 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 427 MUSB2_VAL_FIFOSZ(fifo_size)); 428 #endif 429 } else { 430 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 431 MUSB2_VAL_FIFOSZ(fifo_size)); 432 } 433 434 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 435 offset >> 3); 436 437 offset += (1 << fifotx_size); 438 } 439 } 440 if (fiforx_size && (i <= nrx)) { 441 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 442 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 443 } 444 if (fifotx_size && (i <= ntx)) { 445 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 446 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 447 } 448 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 449 } 450 451 452 DPRINTF("Dynamic FIFO size = %d bytes", offset, 0, 0, 0); 453 454 /* turn on default interrupts */ 455 456 if (sc->sc_mode == MOTG_MODE_HOST) { 457 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 458 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 459 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 460 } else 461 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 462 463 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 464 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 465 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* Set up the bus struct. */ 470 sc->sc_bus.ub_methods = &motg_bus_methods; 471 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 472 sc->sc_bus.ub_revision = USBREV_2_0; 473 sc->sc_bus.ub_usedma = false; 474 sc->sc_bus.ub_hcpriv = sc; 475 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 476 "Mentor Graphics"); 477 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 478 return 0; 479 } 480 481 static int 482 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 483 { 484 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 485 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 486 struct motg_hw_ep *ep; 487 int i, size; 488 489 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 490 491 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 492 sc->sc_in_ep : sc->sc_out_ep; 493 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 494 495 for (i = sc->sc_ep_max; i >= 1; i--) { 496 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 497 "in_ep[%d].ep_fifo_size %d size %d ref %d" : 498 "out_ep[%d].ep_fifo_size %d size %d ref %d", i, 499 ep[i].ep_fifo_size, size, ep[i].refcount); 500 if (ep[i].ep_fifo_size >= size) { 501 /* found a suitable endpoint */ 502 otgpipe->hw_ep = &ep[i]; 503 mutex_enter(&sc->sc_lock); 504 if (otgpipe->hw_ep->refcount > 0) { 505 /* no luck, try next */ 506 mutex_exit(&sc->sc_lock); 507 otgpipe->hw_ep = NULL; 508 } else { 509 otgpipe->hw_ep->refcount++; 510 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 511 otgpipe, ep_pipe_list); 512 mutex_exit(&sc->sc_lock); 513 return 0; 514 } 515 } 516 } 517 return -1; 518 } 519 520 /* Open a new pipe. */ 521 usbd_status 522 motg_open(struct usbd_pipe *pipe) 523 { 524 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 525 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 526 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 527 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 528 529 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 530 531 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, 532 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 533 534 if (sc->sc_dying) 535 return USBD_IOERROR; 536 537 /* toggle state needed for bulk endpoints */ 538 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 539 540 if (pipe->up_dev->ud_addr == rhaddr) { 541 switch (ed->bEndpointAddress) { 542 case USB_CONTROL_ENDPOINT: 543 pipe->up_methods = &roothub_ctrl_methods; 544 break; 545 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 546 pipe->up_methods = &motg_root_intr_methods; 547 break; 548 default: 549 return USBD_INVAL; 550 } 551 } else { 552 switch (ed->bmAttributes & UE_XFERTYPE) { 553 case UE_CONTROL: 554 pipe->up_methods = &motg_device_ctrl_methods; 555 /* always use sc_in_ep[0] for in and out */ 556 otgpipe->hw_ep = &sc->sc_in_ep[0]; 557 mutex_enter(&sc->sc_lock); 558 otgpipe->hw_ep->refcount++; 559 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 560 otgpipe, ep_pipe_list); 561 mutex_exit(&sc->sc_lock); 562 break; 563 case UE_BULK: 564 case UE_INTERRUPT: 565 DPRINTFN(MD_BULK, 566 "type %d dir %d pipe wMaxPacketSize %d", 567 UE_GET_XFERTYPE(ed->bmAttributes), 568 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 569 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 570 if (motg_select_ep(sc, pipe) != 0) 571 goto bad; 572 KASSERT(otgpipe->hw_ep != NULL); 573 pipe->up_methods = &motg_device_data_methods; 574 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 575 break; 576 default: 577 goto bad; 578 #ifdef notyet 579 case UE_ISOCHRONOUS: 580 ... 581 break; 582 #endif /* notyet */ 583 } 584 } 585 return USBD_NORMAL_COMPLETION; 586 587 bad: 588 return USBD_NOMEM; 589 } 590 591 void 592 motg_softintr(void *v) 593 { 594 struct usbd_bus *bus = v; 595 struct motg_softc *sc = MOTG_BUS2SC(bus); 596 uint16_t rx_status, tx_status; 597 uint8_t ctrl_status; 598 uint32_t val; 599 int i; 600 601 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 602 603 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 604 605 DPRINTFN(MD_ROOT | MD_CTRL, "sc %p", sc, 0 ,0 ,0); 606 607 mutex_spin_enter(&sc->sc_intr_lock); 608 rx_status = sc->sc_intr_rx_ep; 609 sc->sc_intr_rx_ep = 0; 610 tx_status = sc->sc_intr_tx_ep; 611 sc->sc_intr_tx_ep = 0; 612 ctrl_status = sc->sc_intr_ctrl; 613 sc->sc_intr_ctrl = 0; 614 mutex_spin_exit(&sc->sc_intr_lock); 615 616 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 617 618 if (ctrl_status & (MUSB2_MASK_IRESET | 619 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 620 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 621 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%x", ctrl_status, 0, 0, 0); 622 623 if (ctrl_status & MUSB2_MASK_IRESET) { 624 sc->sc_isreset = 1; 625 sc->sc_port_suspended = 0; 626 sc->sc_port_suspended_change = 1; 627 sc->sc_connected_changed = 1; 628 sc->sc_port_enabled = 1; 629 630 val = UREAD1(sc, MUSB2_REG_POWER); 631 if (val & MUSB2_MASK_HSMODE) 632 sc->sc_high_speed = 1; 633 else 634 sc->sc_high_speed = 0; 635 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 636 0, 0, 0); 637 638 /* turn off interrupts */ 639 val = MUSB2_MASK_IRESET; 640 val &= ~MUSB2_MASK_IRESUME; 641 val |= MUSB2_MASK_ISUSP; 642 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 643 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 644 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 645 } 646 if (ctrl_status & MUSB2_MASK_IRESUME) { 647 if (sc->sc_port_suspended) { 648 sc->sc_port_suspended = 0; 649 sc->sc_port_suspended_change = 1; 650 val = UREAD1(sc, MUSB2_REG_INTUSBE); 651 /* disable resume interrupt */ 652 val &= ~MUSB2_MASK_IRESUME; 653 /* enable suspend interrupt */ 654 val |= MUSB2_MASK_ISUSP; 655 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 656 } 657 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 658 if (!sc->sc_port_suspended) { 659 sc->sc_port_suspended = 1; 660 sc->sc_port_suspended_change = 1; 661 662 val = UREAD1(sc, MUSB2_REG_INTUSBE); 663 /* disable suspend interrupt */ 664 val &= ~MUSB2_MASK_ISUSP; 665 /* enable resume interrupt */ 666 val |= MUSB2_MASK_IRESUME; 667 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 668 } 669 } 670 if (ctrl_status & MUSB2_MASK_ICONN) { 671 sc->sc_connected = 1; 672 sc->sc_connected_changed = 1; 673 sc->sc_isreset = 1; 674 sc->sc_port_enabled = 1; 675 } else if (ctrl_status & MUSB2_MASK_IDISC) { 676 sc->sc_connected = 0; 677 sc->sc_connected_changed = 1; 678 sc->sc_isreset = 0; 679 sc->sc_port_enabled = 0; 680 } 681 682 /* complete root HUB interrupt endpoint */ 683 684 motg_hub_change(sc); 685 } 686 /* 687 * read in interrupt status and mix with the status we 688 * got from the wrapper 689 */ 690 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 691 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 692 693 if (rx_status & 0x01) 694 panic("ctrl_rx %08x", rx_status); 695 if (tx_status & 0x01) 696 motg_device_ctrl_intr_tx(sc); 697 for (i = 1; i <= sc->sc_ep_max; i++) { 698 if (rx_status & (0x01 << i)) 699 motg_device_intr_rx(sc, i); 700 if (tx_status & (0x01 << i)) 701 motg_device_intr_tx(sc, i); 702 } 703 return; 704 } 705 706 void 707 motg_poll(struct usbd_bus *bus) 708 { 709 struct motg_softc *sc = MOTG_BUS2SC(bus); 710 711 sc->sc_intr_poll(sc->sc_intr_poll_arg); 712 mutex_enter(&sc->sc_lock); 713 motg_softintr(bus); 714 mutex_exit(&sc->sc_lock); 715 } 716 717 int 718 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 719 uint8_t ctrl) 720 { 721 KASSERT(mutex_owned(&sc->sc_intr_lock)); 722 sc->sc_intr_tx_ep = tx_ep; 723 sc->sc_intr_rx_ep = rx_ep; 724 sc->sc_intr_ctrl = ctrl; 725 726 if (!sc->sc_bus.ub_usepolling) { 727 usb_schedsoftintr(&sc->sc_bus); 728 } 729 return 1; 730 } 731 732 int 733 motg_intr_vbus(struct motg_softc *sc, int vbus) 734 { 735 uint8_t val; 736 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 737 738 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 739 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 740 /* try to re-enter session for Host mode */ 741 val = UREAD1(sc, MUSB2_REG_DEVCTL); 742 val |= MUSB2_MASK_SESS; 743 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 744 } 745 return 1; 746 } 747 748 struct usbd_xfer * 749 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 750 { 751 struct motg_softc *sc = MOTG_BUS2SC(bus); 752 struct usbd_xfer *xfer; 753 754 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 755 if (xfer != NULL) { 756 memset(xfer, 0, sizeof(struct motg_xfer)); 757 #ifdef DIAGNOSTIC 758 xfer->ux_state = XFER_BUSY; 759 #endif 760 } 761 return xfer; 762 } 763 764 void 765 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 766 { 767 struct motg_softc *sc = MOTG_BUS2SC(bus); 768 769 #ifdef DIAGNOSTIC 770 if (xfer->ux_state != XFER_BUSY) { 771 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 772 xfer->ux_state); 773 } 774 xfer->ux_state = XFER_FREE; 775 #endif 776 pool_cache_put(sc->sc_xferpool, xfer); 777 } 778 779 static void 780 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 781 { 782 struct motg_softc *sc = MOTG_BUS2SC(bus); 783 784 *lock = &sc->sc_lock; 785 } 786 787 /* 788 * Routines to emulate the root hub. 789 */ 790 Static int 791 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 792 void *buf, int buflen) 793 { 794 struct motg_softc *sc = MOTG_BUS2SC(bus); 795 int status, change, totlen = 0; 796 uint16_t len, value, index; 797 usb_port_status_t ps; 798 usbd_status err; 799 uint32_t val; 800 801 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 802 803 if (sc->sc_dying) 804 return -1; 805 806 DPRINTFN(MD_ROOT, "type=0x%02x request=%02x", req->bmRequestType, 807 req->bRequest, 0, 0); 808 809 len = UGETW(req->wLength); 810 value = UGETW(req->wValue); 811 index = UGETW(req->wIndex); 812 813 #define C(x,y) ((x) | ((y) << 8)) 814 switch (C(req->bRequest, req->bmRequestType)) { 815 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 816 DPRINTFN(MD_ROOT, "wValue=0x%04x", value, 0, 0, 0); 817 switch (value) { 818 case C(0, UDESC_DEVICE): { 819 usb_device_descriptor_t devd; 820 821 totlen = min(buflen, sizeof(devd)); 822 memcpy(&devd, buf, totlen); 823 USETW(devd.idVendor, sc->sc_id_vendor); 824 memcpy(buf, &devd, totlen); 825 break; 826 } 827 case C(1, UDESC_STRING): 828 #define sd ((usb_string_descriptor_t *)buf) 829 /* Vendor */ 830 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 831 break; 832 case C(2, UDESC_STRING): 833 /* Product */ 834 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 835 break; 836 #undef sd 837 default: 838 /* default from usbroothub */ 839 return buflen; 840 } 841 break; 842 /* Hub requests */ 843 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 844 break; 845 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 846 DPRINTFN(MD_ROOT, 847 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 848 0, 0); 849 if (index != 1) { 850 return -1; 851 } 852 switch (value) { 853 case UHF_PORT_ENABLE: 854 sc->sc_port_enabled = 0; 855 break; 856 case UHF_PORT_SUSPEND: 857 if (sc->sc_port_suspended != 0) { 858 val = UREAD1(sc, MUSB2_REG_POWER); 859 val &= ~MUSB2_MASK_SUSPMODE; 860 val |= MUSB2_MASK_RESUME; 861 UWRITE1(sc, MUSB2_REG_POWER, val); 862 /* wait 20 milliseconds */ 863 usb_delay_ms(&sc->sc_bus, 20); 864 val = UREAD1(sc, MUSB2_REG_POWER); 865 val &= ~MUSB2_MASK_RESUME; 866 UWRITE1(sc, MUSB2_REG_POWER, val); 867 sc->sc_port_suspended = 0; 868 sc->sc_port_suspended_change = 1; 869 } 870 break; 871 case UHF_PORT_RESET: 872 break; 873 case UHF_C_PORT_CONNECTION: 874 break; 875 case UHF_C_PORT_ENABLE: 876 break; 877 case UHF_C_PORT_OVER_CURRENT: 878 break; 879 case UHF_C_PORT_RESET: 880 sc->sc_isreset = 0; 881 break; 882 case UHF_PORT_POWER: 883 /* XXX todo */ 884 break; 885 case UHF_PORT_CONNECTION: 886 case UHF_PORT_OVER_CURRENT: 887 case UHF_PORT_LOW_SPEED: 888 case UHF_C_PORT_SUSPEND: 889 default: 890 return -1; 891 } 892 break; 893 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 894 return -1; 895 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 896 if (len == 0) 897 break; 898 if ((value & 0xff) != 0) { 899 return -1; 900 } 901 totlen = buflen; 902 break; 903 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 904 if (len != 4) { 905 return -1; 906 } 907 memset(buf, 0, len); 908 totlen = len; 909 break; 910 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 911 if (index != 1) { 912 return -1; 913 } 914 if (len != 4) { 915 return -1; 916 } 917 status = change = 0; 918 if (sc->sc_connected) 919 status |= UPS_CURRENT_CONNECT_STATUS; 920 if (sc->sc_connected_changed) { 921 change |= UPS_C_CONNECT_STATUS; 922 sc->sc_connected_changed = 0; 923 } 924 if (sc->sc_port_enabled) 925 status |= UPS_PORT_ENABLED; 926 if (sc->sc_port_enabled_changed) { 927 change |= UPS_C_PORT_ENABLED; 928 sc->sc_port_enabled_changed = 0; 929 } 930 if (sc->sc_port_suspended) 931 status |= UPS_SUSPEND; 932 if (sc->sc_high_speed) 933 status |= UPS_HIGH_SPEED; 934 status |= UPS_PORT_POWER; /* XXX */ 935 if (sc->sc_isreset) 936 change |= UPS_C_PORT_RESET; 937 USETW(ps.wPortStatus, status); 938 USETW(ps.wPortChange, change); 939 totlen = min(len, sizeof(ps)); 940 memcpy(buf, &ps, totlen); 941 break; 942 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 943 return -1; 944 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 945 break; 946 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 947 if (index != 1) { 948 return -1; 949 } 950 switch(value) { 951 case UHF_PORT_ENABLE: 952 sc->sc_port_enabled = 1; 953 break; 954 case UHF_PORT_SUSPEND: 955 if (sc->sc_port_suspended == 0) { 956 val = UREAD1(sc, MUSB2_REG_POWER); 957 val |= MUSB2_MASK_SUSPMODE; 958 UWRITE1(sc, MUSB2_REG_POWER, val); 959 /* wait 20 milliseconds */ 960 usb_delay_ms(&sc->sc_bus, 20); 961 sc->sc_port_suspended = 1; 962 sc->sc_port_suspended_change = 1; 963 } 964 break; 965 case UHF_PORT_RESET: 966 err = motg_portreset(sc); 967 if (err != USBD_NORMAL_COMPLETION) 968 return -1; 969 return 0; 970 case UHF_PORT_POWER: 971 /* XXX todo */ 972 return 0; 973 case UHF_C_PORT_CONNECTION: 974 case UHF_C_PORT_ENABLE: 975 case UHF_C_PORT_OVER_CURRENT: 976 case UHF_PORT_CONNECTION: 977 case UHF_PORT_OVER_CURRENT: 978 case UHF_PORT_LOW_SPEED: 979 case UHF_C_PORT_SUSPEND: 980 case UHF_C_PORT_RESET: 981 default: 982 return -1; 983 } 984 break; 985 default: 986 /* default from usbroothub */ 987 return buflen; 988 } 989 990 return totlen; 991 } 992 993 /* Abort a root interrupt request. */ 994 void 995 motg_root_intr_abort(struct usbd_xfer *xfer) 996 { 997 struct motg_softc *sc = MOTG_XFER2SC(xfer); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 1001 1002 sc->sc_intr_xfer = NULL; 1003 1004 xfer->ux_status = USBD_CANCELLED; 1005 usb_transfer_complete(xfer); 1006 } 1007 1008 usbd_status 1009 motg_root_intr_transfer(struct usbd_xfer *xfer) 1010 { 1011 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1012 usbd_status err; 1013 1014 /* Insert last in queue. */ 1015 mutex_enter(&sc->sc_lock); 1016 err = usb_insert_transfer(xfer); 1017 mutex_exit(&sc->sc_lock); 1018 if (err) 1019 return err; 1020 1021 /* 1022 * Pipe isn't running (otherwise err would be USBD_INPROG), 1023 * start first 1024 */ 1025 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1026 } 1027 1028 /* Start a transfer on the root interrupt pipe */ 1029 usbd_status 1030 motg_root_intr_start(struct usbd_xfer *xfer) 1031 { 1032 struct usbd_pipe *pipe = xfer->ux_pipe; 1033 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1034 1035 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1036 1037 DPRINTFN(MD_ROOT, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 1038 xfer->ux_flags, 0); 1039 1040 if (sc->sc_dying) 1041 return USBD_IOERROR; 1042 1043 sc->sc_intr_xfer = xfer; 1044 return USBD_IN_PROGRESS; 1045 } 1046 1047 /* Close the root interrupt pipe. */ 1048 void 1049 motg_root_intr_close(struct usbd_pipe *pipe) 1050 { 1051 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1052 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1053 1054 KASSERT(mutex_owned(&sc->sc_lock)); 1055 1056 sc->sc_intr_xfer = NULL; 1057 } 1058 1059 void 1060 motg_root_intr_done(struct usbd_xfer *xfer) 1061 { 1062 } 1063 1064 void 1065 motg_noop(struct usbd_pipe *pipe) 1066 { 1067 } 1068 1069 static usbd_status 1070 motg_portreset(struct motg_softc *sc) 1071 { 1072 uint32_t val; 1073 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1074 1075 val = UREAD1(sc, MUSB2_REG_POWER); 1076 val |= MUSB2_MASK_RESET; 1077 UWRITE1(sc, MUSB2_REG_POWER, val); 1078 /* Wait for 20 msec */ 1079 usb_delay_ms(&sc->sc_bus, 20); 1080 1081 val = UREAD1(sc, MUSB2_REG_POWER); 1082 val &= ~MUSB2_MASK_RESET; 1083 UWRITE1(sc, MUSB2_REG_POWER, val); 1084 1085 /* determine line speed */ 1086 val = UREAD1(sc, MUSB2_REG_POWER); 1087 if (val & MUSB2_MASK_HSMODE) 1088 sc->sc_high_speed = 1; 1089 else 1090 sc->sc_high_speed = 0; 1091 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 0, 0, 0); 1092 1093 sc->sc_isreset = 1; 1094 sc->sc_port_enabled = 1; 1095 return USBD_NORMAL_COMPLETION; 1096 } 1097 1098 /* 1099 * This routine is executed when an interrupt on the root hub is detected 1100 */ 1101 static void 1102 motg_hub_change(struct motg_softc *sc) 1103 { 1104 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1105 struct usbd_pipe *pipe; 1106 u_char *p; 1107 1108 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1109 1110 if (xfer == NULL) 1111 return; /* the interrupt pipe is not open */ 1112 1113 pipe = xfer->ux_pipe; 1114 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1115 return; /* device has detached */ 1116 1117 p = xfer->ux_buf; 1118 p[0] = 1<<1; 1119 xfer->ux_actlen = 1; 1120 xfer->ux_status = USBD_NORMAL_COMPLETION; 1121 usb_transfer_complete(xfer); 1122 } 1123 1124 static uint8_t 1125 motg_speed(uint8_t speed) 1126 { 1127 switch(speed) { 1128 case USB_SPEED_LOW: 1129 return MUSB2_MASK_TI_SPEED_LO; 1130 case USB_SPEED_FULL: 1131 return MUSB2_MASK_TI_SPEED_FS; 1132 case USB_SPEED_HIGH: 1133 return MUSB2_MASK_TI_SPEED_HS; 1134 default: 1135 panic("motg: unknown speed %d", speed); 1136 /* NOTREACHED */ 1137 } 1138 } 1139 1140 static uint8_t 1141 motg_type(uint8_t type) 1142 { 1143 switch(type) { 1144 case UE_CONTROL: 1145 return MUSB2_MASK_TI_PROTO_CTRL; 1146 case UE_ISOCHRONOUS: 1147 return MUSB2_MASK_TI_PROTO_ISOC; 1148 case UE_BULK: 1149 return MUSB2_MASK_TI_PROTO_BULK; 1150 case UE_INTERRUPT: 1151 return MUSB2_MASK_TI_PROTO_INTR; 1152 default: 1153 panic("motg: unknown type %d", type); 1154 /* NOTREACHED */ 1155 } 1156 } 1157 1158 static void 1159 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1160 { 1161 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1162 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1163 struct usbd_device *dev = otgpipe->pipe.up_dev; 1164 int epnumber = otgpipe->hw_ep->ep_number; 1165 1166 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1167 if (dev->ud_myhsport) { 1168 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1169 dev->ud_myhsport->up_parent->ud_addr); 1170 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1171 dev->ud_myhsport->up_portno); 1172 } else { 1173 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1174 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1175 } 1176 UWRITE1(sc, MUSB2_REG_TXTI, 1177 motg_speed(dev->ud_speed) | 1178 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1179 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1180 ); 1181 if (epnumber == 0) { 1182 if (sc->sc_high_speed) { 1183 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1184 NAK_TO_CTRL_HIGH); 1185 } else { 1186 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1187 } 1188 } else { 1189 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1190 == UE_BULK) { 1191 if (sc->sc_high_speed) { 1192 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1193 NAK_TO_BULK_HIGH); 1194 } else { 1195 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1196 } 1197 } else { 1198 if (sc->sc_high_speed) { 1199 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1200 } else { 1201 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1202 } 1203 } 1204 } 1205 } 1206 1207 static void 1208 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1209 { 1210 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1211 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1212 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1213 int epnumber = otgpipe->hw_ep->ep_number; 1214 1215 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1216 if (dev->ud_myhsport) { 1217 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1218 dev->ud_myhsport->up_parent->ud_addr); 1219 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1220 dev->ud_myhsport->up_portno); 1221 } else { 1222 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1223 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1224 } 1225 UWRITE1(sc, MUSB2_REG_RXTI, 1226 motg_speed(dev->ud_speed) | 1227 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1228 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1229 ); 1230 if (epnumber == 0) { 1231 if (sc->sc_high_speed) { 1232 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1233 NAK_TO_CTRL_HIGH); 1234 } else { 1235 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1236 } 1237 } else { 1238 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1239 == UE_BULK) { 1240 if (sc->sc_high_speed) { 1241 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1242 NAK_TO_BULK_HIGH); 1243 } else { 1244 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1245 } 1246 } else { 1247 if (sc->sc_high_speed) { 1248 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1249 } else { 1250 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1251 } 1252 } 1253 } 1254 } 1255 1256 static usbd_status 1257 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1258 { 1259 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1260 usbd_status err; 1261 1262 /* Insert last in queue. */ 1263 mutex_enter(&sc->sc_lock); 1264 err = usb_insert_transfer(xfer); 1265 xfer->ux_status = USBD_NOT_STARTED; 1266 mutex_exit(&sc->sc_lock); 1267 if (err) 1268 return err; 1269 1270 /* 1271 * Pipe isn't running (otherwise err would be USBD_INPROG), 1272 * so start it first. 1273 */ 1274 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1275 } 1276 1277 static usbd_status 1278 motg_device_ctrl_start(struct usbd_xfer *xfer) 1279 { 1280 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1281 usbd_status err; 1282 mutex_enter(&sc->sc_lock); 1283 err = motg_device_ctrl_start1(sc); 1284 mutex_exit(&sc->sc_lock); 1285 if (err != USBD_IN_PROGRESS) 1286 return err; 1287 if (sc->sc_bus.ub_usepolling) 1288 motg_waitintr(sc, xfer); 1289 return USBD_IN_PROGRESS; 1290 } 1291 1292 static usbd_status 1293 motg_device_ctrl_start1(struct motg_softc *sc) 1294 { 1295 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1296 struct usbd_xfer *xfer = NULL; 1297 struct motg_pipe *otgpipe; 1298 usbd_status err = 0; 1299 1300 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1301 1302 KASSERT(mutex_owned(&sc->sc_lock)); 1303 if (sc->sc_dying) 1304 return USBD_IOERROR; 1305 1306 if (!sc->sc_connected) 1307 return USBD_IOERROR; 1308 1309 if (ep->xfer != NULL) { 1310 err = USBD_IN_PROGRESS; 1311 goto end; 1312 } 1313 /* locate the first pipe with work to do */ 1314 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1315 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1316 DPRINTFN(MD_CTRL, "pipe %p xfer %p status %d", 1317 otgpipe, xfer, (xfer != NULL) ? xfer->ux_status : 0, 0); 1318 1319 if (xfer != NULL) { 1320 /* move this pipe to the end of the list */ 1321 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1322 motg_pipe, ep_pipe_list); 1323 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1324 otgpipe, ep_pipe_list); 1325 break; 1326 } 1327 } 1328 if (xfer == NULL) { 1329 err = USBD_NOT_STARTED; 1330 goto end; 1331 } 1332 xfer->ux_status = USBD_IN_PROGRESS; 1333 KASSERT(otgpipe == (struct motg_pipe *)xfer->ux_pipe); 1334 KASSERT(otgpipe->hw_ep == ep); 1335 #ifdef DIAGNOSTIC 1336 if (!(xfer->ux_rqflags & URQ_REQUEST)) 1337 panic("motg_device_ctrl_transfer: not a request"); 1338 #endif 1339 // KASSERT(xfer->ux_actlen == 0); 1340 xfer->ux_actlen = 0; 1341 1342 ep->xfer = xfer; 1343 ep->datalen = xfer->ux_length; 1344 if (ep->datalen > 0) 1345 ep->data = xfer->ux_buf; 1346 else 1347 ep->data = NULL; 1348 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1349 (ep->datalen % 64) == 0) 1350 ep->need_short_xfer = 1; 1351 else 1352 ep->need_short_xfer = 0; 1353 /* now we need send this request */ 1354 DPRINTFN(MD_CTRL, 1355 "xfer %p send data %p len %d short %d", 1356 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1357 DPRINTFN(MD_CTRL, 1358 "xfer %p ... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1359 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1360 KASSERT(ep->phase == IDLE); 1361 ep->phase = SETUP; 1362 /* select endpoint 0 */ 1363 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1364 /* fifo should be empty at this point */ 1365 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1366 /* send data */ 1367 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1368 KASSERT(sizeof(xfer->ux_request) == 8); 1369 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1370 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1371 1372 motg_setup_endpoint_tx(xfer); 1373 /* start transaction */ 1374 UWRITE1(sc, MUSB2_REG_TXCSRL, 1375 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1376 1377 end: 1378 if (err) 1379 return err; 1380 1381 return USBD_IN_PROGRESS; 1382 } 1383 1384 static void 1385 motg_device_ctrl_read(struct usbd_xfer *xfer) 1386 { 1387 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1388 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1389 /* assume endpoint already selected */ 1390 motg_setup_endpoint_rx(xfer); 1391 /* start transaction */ 1392 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1393 otgpipe->hw_ep->phase = DATA_IN; 1394 } 1395 1396 static void 1397 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1398 { 1399 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1400 struct usbd_xfer *xfer = ep->xfer; 1401 uint8_t csr; 1402 int datalen, max_datalen; 1403 char *data; 1404 bool got_short; 1405 usbd_status new_status = USBD_IN_PROGRESS; 1406 1407 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1408 1409 KASSERT(mutex_owned(&sc->sc_lock)); 1410 1411 #ifdef DIAGNOSTIC 1412 if (ep->phase != DATA_IN && 1413 ep->phase != STATUS_IN) 1414 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1415 #endif 1416 /* select endpoint 0 */ 1417 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1418 1419 /* read out FIFO status */ 1420 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1421 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1422 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1423 1424 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1425 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1426 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1427 1428 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1429 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1430 new_status = USBD_TIMEOUT; /* XXX */ 1431 goto complete; 1432 } 1433 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1434 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1435 new_status = USBD_STALLED; 1436 else 1437 new_status = USBD_IOERROR; 1438 /* clear status */ 1439 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1440 goto complete; 1441 } 1442 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1443 return; /* no data yet */ 1444 1445 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1446 goto complete; 1447 1448 if (ep->phase == STATUS_IN) { 1449 new_status = USBD_NORMAL_COMPLETION; 1450 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1451 goto complete; 1452 } 1453 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1454 DPRINTFN(MD_CTRL, "phase %d datalen %d", ep->phase, datalen, 0, 0); 1455 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1456 max_datalen = min(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1457 ep->datalen); 1458 if (datalen > max_datalen) { 1459 new_status = USBD_IOERROR; 1460 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1461 goto complete; 1462 } 1463 got_short = (datalen < max_datalen); 1464 if (datalen > 0) { 1465 KASSERT(ep->phase == DATA_IN); 1466 data = ep->data; 1467 ep->data += datalen; 1468 ep->datalen -= datalen; 1469 xfer->ux_actlen += datalen; 1470 if (((vaddr_t)data & 0x3) == 0 && 1471 (datalen >> 2) > 0) { 1472 DPRINTFN(MD_CTRL, "r4 data %p len %d", data, datalen, 1473 0, 0); 1474 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1475 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1476 data += (datalen & ~0x3); 1477 datalen -= (datalen & ~0x3); 1478 } 1479 DPRINTFN(MD_CTRL, "r1 data %p len %d", data, datalen, 0, 0); 1480 if (datalen) { 1481 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1482 MUSB2_REG_EPFIFO(0), data, datalen); 1483 } 1484 } 1485 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1486 KASSERT(ep->phase == DATA_IN); 1487 if (got_short || (ep->datalen == 0)) { 1488 if (ep->need_short_xfer == 0) { 1489 ep->phase = STATUS_OUT; 1490 UWRITE1(sc, MUSB2_REG_TXCSRH, 1491 UREAD1(sc, MUSB2_REG_TXCSRH) | 1492 MUSB2_MASK_CSR0H_PING_DIS); 1493 motg_setup_endpoint_tx(xfer); 1494 UWRITE1(sc, MUSB2_REG_TXCSRL, 1495 MUSB2_MASK_CSR0L_STATUSPKT | 1496 MUSB2_MASK_CSR0L_TXPKTRDY); 1497 return; 1498 } 1499 ep->need_short_xfer = 0; 1500 } 1501 motg_device_ctrl_read(xfer); 1502 return; 1503 complete: 1504 ep->phase = IDLE; 1505 ep->xfer = NULL; 1506 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1507 KASSERT(new_status != USBD_IN_PROGRESS); 1508 xfer->ux_status = new_status; 1509 usb_transfer_complete(xfer); 1510 } 1511 motg_device_ctrl_start1(sc); 1512 } 1513 1514 static void 1515 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1516 { 1517 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1518 struct usbd_xfer *xfer = ep->xfer; 1519 uint8_t csr; 1520 int datalen; 1521 char *data; 1522 usbd_status new_status = USBD_IN_PROGRESS; 1523 1524 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1525 1526 KASSERT(mutex_owned(&sc->sc_lock)); 1527 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1528 motg_device_ctrl_intr_rx(sc); 1529 return; 1530 } 1531 1532 #ifdef DIAGNOSTIC 1533 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1534 ep->phase != STATUS_OUT) 1535 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1536 #endif 1537 /* select endpoint 0 */ 1538 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1539 1540 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1541 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1542 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1543 1544 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1545 /* command not accepted */ 1546 new_status = USBD_STALLED; 1547 /* clear status */ 1548 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1549 goto complete; 1550 } 1551 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1552 new_status = USBD_TIMEOUT; /* XXX */ 1553 /* flush fifo */ 1554 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1555 UWRITE1(sc, MUSB2_REG_TXCSRH, 1556 UREAD1(sc, MUSB2_REG_TXCSRH) | 1557 MUSB2_MASK_CSR0H_FFLUSH); 1558 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1559 } 1560 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1561 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1562 goto complete; 1563 } 1564 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1565 new_status = USBD_IOERROR; 1566 /* clear status */ 1567 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1568 goto complete; 1569 } 1570 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1571 /* data still not sent */ 1572 return; 1573 } 1574 if (xfer == NULL) 1575 goto complete; 1576 if (ep->phase == STATUS_OUT) { 1577 /* 1578 * we have sent status and got no error; 1579 * declare transfer complete 1580 */ 1581 DPRINTFN(MD_CTRL, "xfer %p status %d complete", xfer, 1582 xfer->ux_status, 0, 0); 1583 new_status = USBD_NORMAL_COMPLETION; 1584 goto complete; 1585 } 1586 if (ep->datalen == 0) { 1587 if (ep->need_short_xfer) { 1588 ep->need_short_xfer = 0; 1589 /* one more data phase */ 1590 if (xfer->ux_request.bmRequestType & UT_READ) { 1591 DPRINTFN(MD_CTRL, "xfer %p to DATA_IN", xfer, 1592 0, 0, 0); 1593 motg_device_ctrl_read(xfer); 1594 return; 1595 } /* else fall back to DATA_OUT */ 1596 } else { 1597 DPRINTFN(MD_CTRL, "xfer %p to STATUS_IN, csrh 0x%x", 1598 xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1599 ep->phase = STATUS_IN; 1600 UWRITE1(sc, MUSB2_REG_RXCSRH, 1601 UREAD1(sc, MUSB2_REG_RXCSRH) | 1602 MUSB2_MASK_CSR0H_PING_DIS); 1603 motg_setup_endpoint_rx(xfer); 1604 UWRITE1(sc, MUSB2_REG_TXCSRL, 1605 MUSB2_MASK_CSR0L_STATUSPKT | 1606 MUSB2_MASK_CSR0L_REQPKT); 1607 return; 1608 } 1609 } 1610 if (xfer->ux_request.bmRequestType & UT_READ) { 1611 motg_device_ctrl_read(xfer); 1612 return; 1613 } 1614 /* setup a dataout phase */ 1615 datalen = min(ep->datalen, 1616 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1617 ep->phase = DATA_OUT; 1618 DPRINTFN(MD_CTRL, "xfer %p to DATA_OUT, csrh 0x%x", xfer, 1619 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1620 if (datalen) { 1621 data = ep->data; 1622 ep->data += datalen; 1623 ep->datalen -= datalen; 1624 xfer->ux_actlen += datalen; 1625 if (((vaddr_t)data & 0x3) == 0 && 1626 (datalen >> 2) > 0) { 1627 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1628 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1629 data += (datalen & ~0x3); 1630 datalen -= (datalen & ~0x3); 1631 } 1632 if (datalen) { 1633 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1634 MUSB2_REG_EPFIFO(0), data, datalen); 1635 } 1636 } 1637 /* send data */ 1638 motg_setup_endpoint_tx(xfer); 1639 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1640 return; 1641 1642 complete: 1643 ep->phase = IDLE; 1644 ep->xfer = NULL; 1645 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1646 KASSERT(new_status != USBD_IN_PROGRESS); 1647 xfer->ux_status = new_status; 1648 usb_transfer_complete(xfer); 1649 } 1650 motg_device_ctrl_start1(sc); 1651 } 1652 1653 /* Abort a device control request. */ 1654 void 1655 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1656 { 1657 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1658 1659 motg_device_xfer_abort(xfer); 1660 } 1661 1662 /* Close a device control pipe */ 1663 void 1664 motg_device_ctrl_close(struct usbd_pipe *pipe) 1665 { 1666 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1667 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1668 struct motg_pipe *otgpipeiter; 1669 1670 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1671 1672 KASSERT(mutex_owned(&sc->sc_lock)); 1673 KASSERT(otgpipe->hw_ep->xfer == NULL || 1674 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1675 1676 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1677 if (otgpipeiter == otgpipe) { 1678 /* remove from list */ 1679 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1680 motg_pipe, ep_pipe_list); 1681 otgpipe->hw_ep->refcount--; 1682 /* we're done */ 1683 return; 1684 } 1685 } 1686 panic("motg_device_ctrl_close: not found"); 1687 } 1688 1689 void 1690 motg_device_ctrl_done(struct usbd_xfer *xfer) 1691 { 1692 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->ux_pipe; 1693 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1694 1695 KASSERT(otgpipe->hw_ep->xfer != xfer); 1696 } 1697 1698 static usbd_status 1699 motg_device_data_transfer(struct usbd_xfer *xfer) 1700 { 1701 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1702 usbd_status err; 1703 1704 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1705 1706 /* Insert last in queue. */ 1707 mutex_enter(&sc->sc_lock); 1708 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1709 err = usb_insert_transfer(xfer); 1710 xfer->ux_status = USBD_NOT_STARTED; 1711 mutex_exit(&sc->sc_lock); 1712 if (err) 1713 return err; 1714 1715 /* 1716 * Pipe isn't running (otherwise err would be USBD_INPROG), 1717 * so start it first. 1718 */ 1719 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1720 } 1721 1722 static usbd_status 1723 motg_device_data_start(struct usbd_xfer *xfer) 1724 { 1725 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1726 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1727 usbd_status err; 1728 1729 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1730 1731 mutex_enter(&sc->sc_lock); 1732 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1733 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1734 mutex_exit(&sc->sc_lock); 1735 if (err != USBD_IN_PROGRESS) 1736 return err; 1737 if (sc->sc_bus.ub_usepolling) 1738 motg_waitintr(sc, xfer); 1739 return USBD_IN_PROGRESS; 1740 } 1741 1742 static usbd_status 1743 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1744 { 1745 struct usbd_xfer *xfer = NULL; 1746 struct motg_pipe *otgpipe; 1747 usbd_status err = 0; 1748 uint32_t val __diagused; 1749 1750 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1751 1752 KASSERT(mutex_owned(&sc->sc_lock)); 1753 if (sc->sc_dying) 1754 return USBD_IOERROR; 1755 1756 if (!sc->sc_connected) 1757 return USBD_IOERROR; 1758 1759 if (ep->xfer != NULL) { 1760 err = USBD_IN_PROGRESS; 1761 goto end; 1762 } 1763 /* locate the first pipe with work to do */ 1764 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1765 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1766 DPRINTFN(MD_BULK, "pipe %p xfer %p status %d", otgpipe, xfer, 1767 (xfer != NULL) ? xfer->ux_status : 0, 0); 1768 if (xfer != NULL) { 1769 /* move this pipe to the end of the list */ 1770 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1771 motg_pipe, ep_pipe_list); 1772 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1773 otgpipe, ep_pipe_list); 1774 break; 1775 } 1776 } 1777 if (xfer == NULL) { 1778 err = USBD_NOT_STARTED; 1779 goto end; 1780 } 1781 xfer->ux_status = USBD_IN_PROGRESS; 1782 KASSERT(otgpipe == (struct motg_pipe *)xfer->ux_pipe); 1783 KASSERT(otgpipe->hw_ep == ep); 1784 #ifdef DIAGNOSTIC 1785 if (xfer->ux_rqflags & URQ_REQUEST) 1786 panic("motg_device_data_transfer: a request"); 1787 #endif 1788 // KASSERT(xfer->ux_actlen == 0); 1789 xfer->ux_actlen = 0; 1790 1791 ep->xfer = xfer; 1792 ep->datalen = xfer->ux_length; 1793 KASSERT(ep->datalen > 0); 1794 ep->data = xfer->ux_buf; 1795 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1796 (ep->datalen % 64) == 0) 1797 ep->need_short_xfer = 1; 1798 else 1799 ep->need_short_xfer = 0; 1800 /* now we need send this request */ 1801 DPRINTFN(MD_BULK, 1802 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1803 "xfer %p in data %p len %d short %d" : 1804 "xfer %p out data %p len %d short %d", 1805 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1806 DPRINTFN(MD_BULK, "... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1807 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1808 KASSERT(ep->phase == IDLE); 1809 /* select endpoint */ 1810 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1811 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1812 == UE_DIR_IN) { 1813 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1814 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1815 motg_device_data_read(xfer); 1816 } else { 1817 ep->phase = DATA_OUT; 1818 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1819 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1820 motg_device_data_write(xfer); 1821 } 1822 end: 1823 if (err) 1824 return err; 1825 1826 return USBD_IN_PROGRESS; 1827 } 1828 1829 static void 1830 motg_device_data_read(struct usbd_xfer *xfer) 1831 { 1832 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1833 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1834 uint32_t val; 1835 1836 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1837 1838 KASSERT(mutex_owned(&sc->sc_lock)); 1839 /* assume endpoint already selected */ 1840 motg_setup_endpoint_rx(xfer); 1841 /* Max packet size */ 1842 UWRITE2(sc, MUSB2_REG_RXMAXP, 1843 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1844 /* Data Toggle */ 1845 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1846 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1847 if (otgpipe->nexttoggle) 1848 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1849 else 1850 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1851 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1852 1853 DPRINTFN(MD_BULK, "%p to DATA_IN on ep %d, csrh 0x%x", 1854 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1855 /* start transaction */ 1856 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1857 otgpipe->hw_ep->phase = DATA_IN; 1858 } 1859 1860 static void 1861 motg_device_data_write(struct usbd_xfer *xfer) 1862 { 1863 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1864 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1865 struct motg_hw_ep *ep = otgpipe->hw_ep; 1866 int datalen; 1867 char *data; 1868 uint32_t val; 1869 1870 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1871 1872 KASSERT(xfer!=NULL); 1873 KASSERT(mutex_owned(&sc->sc_lock)); 1874 1875 datalen = min(ep->datalen, 1876 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1877 ep->phase = DATA_OUT; 1878 DPRINTFN(MD_BULK, "%p to DATA_OUT on ep %d, len %d csrh 0x%x", 1879 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH)); 1880 1881 /* assume endpoint already selected */ 1882 /* write data to fifo */ 1883 data = ep->data; 1884 ep->data += datalen; 1885 ep->datalen -= datalen; 1886 xfer->ux_actlen += datalen; 1887 if (((vaddr_t)data & 0x3) == 0 && 1888 (datalen >> 2) > 0) { 1889 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1890 MUSB2_REG_EPFIFO(ep->ep_number), 1891 (void *)data, datalen >> 2); 1892 data += (datalen & ~0x3); 1893 datalen -= (datalen & ~0x3); 1894 } 1895 if (datalen) { 1896 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1897 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1898 } 1899 1900 motg_setup_endpoint_tx(xfer); 1901 /* Max packet size */ 1902 UWRITE2(sc, MUSB2_REG_TXMAXP, 1903 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1904 /* Data Toggle */ 1905 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1906 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1907 if (otgpipe->nexttoggle) 1908 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1909 else 1910 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1911 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1912 1913 /* start transaction */ 1914 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1915 } 1916 1917 static void 1918 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1919 { 1920 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1921 struct usbd_xfer *xfer = ep->xfer; 1922 uint8_t csr; 1923 int datalen, max_datalen; 1924 char *data; 1925 bool got_short; 1926 usbd_status new_status = USBD_IN_PROGRESS; 1927 1928 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1929 1930 KASSERT(mutex_owned(&sc->sc_lock)); 1931 KASSERT(ep->ep_number == epnumber); 1932 1933 DPRINTFN(MD_BULK, "on ep %d", epnumber, 0, 0, 0); 1934 /* select endpoint */ 1935 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1936 1937 /* read out FIFO status */ 1938 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1939 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr ,0 ,0); 1940 1941 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1942 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1943 return; 1944 1945 #ifdef DIAGNOSTIC 1946 if (ep->phase != DATA_IN) 1947 panic("motg_device_intr_rx: bad phase %d", ep->phase); 1948 #endif 1949 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1950 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1951 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1952 1953 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1954 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1955 new_status = USBD_TIMEOUT; /* XXX */ 1956 goto complete; 1957 } 1958 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1959 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1960 new_status = USBD_STALLED; 1961 else 1962 new_status = USBD_IOERROR; 1963 /* clear status */ 1964 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1965 goto complete; 1966 } 1967 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1968 1969 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1970 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1971 goto complete; 1972 } 1973 1974 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 1975 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1976 1977 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1978 DPRINTFN(MD_BULK, "phase %d datalen %d", ep->phase, datalen ,0 ,0); 1979 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1980 max_datalen = min( 1981 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1982 ep->datalen); 1983 if (datalen > max_datalen) { 1984 new_status = USBD_IOERROR; 1985 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1986 goto complete; 1987 } 1988 got_short = (datalen < max_datalen); 1989 if (datalen > 0) { 1990 KASSERT(ep->phase == DATA_IN); 1991 data = ep->data; 1992 ep->data += datalen; 1993 ep->datalen -= datalen; 1994 xfer->ux_actlen += datalen; 1995 if (((vaddr_t)data & 0x3) == 0 && 1996 (datalen >> 2) > 0) { 1997 DPRINTFN(MD_BULK, "r4 data %p len %d", data, datalen, 1998 0, 0); 1999 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2000 MUSB2_REG_EPFIFO(ep->ep_number), 2001 (void *)data, datalen >> 2); 2002 data += (datalen & ~0x3); 2003 datalen -= (datalen & ~0x3); 2004 } 2005 DPRINTFN(MD_BULK, "r1 data %p len %d", data, datalen ,0 ,0); 2006 if (datalen) { 2007 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2008 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2009 } 2010 } 2011 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2012 KASSERT(ep->phase == DATA_IN); 2013 if (got_short || (ep->datalen == 0)) { 2014 if (ep->need_short_xfer == 0) { 2015 new_status = USBD_NORMAL_COMPLETION; 2016 goto complete; 2017 } 2018 ep->need_short_xfer = 0; 2019 } 2020 motg_device_data_read(xfer); 2021 return; 2022 complete: 2023 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2024 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2025 ep->phase = IDLE; 2026 ep->xfer = NULL; 2027 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2028 KASSERT(new_status != USBD_IN_PROGRESS); 2029 xfer->ux_status = new_status; 2030 usb_transfer_complete(xfer); 2031 } 2032 motg_device_data_start1(sc, ep); 2033 } 2034 2035 static void 2036 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2037 { 2038 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2039 struct usbd_xfer *xfer = ep->xfer; 2040 uint8_t csr; 2041 struct motg_pipe *otgpipe; 2042 usbd_status new_status = USBD_IN_PROGRESS; 2043 2044 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2045 2046 KASSERT(mutex_owned(&sc->sc_lock)); 2047 KASSERT(ep->ep_number == epnumber); 2048 2049 DPRINTFN(MD_BULK, " on ep %d", epnumber, 0, 0, 0); 2050 /* select endpoint */ 2051 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2052 2053 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2054 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr, 0, 0); 2055 2056 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2057 /* command not accepted */ 2058 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2059 new_status = USBD_STALLED; 2060 else 2061 new_status = USBD_IOERROR; 2062 /* clear status */ 2063 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2064 goto complete; 2065 } 2066 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2067 new_status = USBD_TIMEOUT; /* XXX */ 2068 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2069 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2070 /* flush fifo */ 2071 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2072 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2073 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2074 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2075 delay(1000); 2076 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2077 DPRINTFN(MD_BULK, "TX fifo flush ep %d CSR 0x%x", 2078 epnumber, csr, 0, 0); 2079 } 2080 goto complete; 2081 } 2082 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2083 /* data still not sent */ 2084 return; 2085 } 2086 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2087 goto complete; 2088 #ifdef DIAGNOSTIC 2089 if (ep->phase != DATA_OUT) 2090 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2091 #endif 2092 2093 otgpipe = (struct motg_pipe *)xfer->ux_pipe; 2094 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2095 2096 if (ep->datalen == 0) { 2097 if (ep->need_short_xfer) { 2098 ep->need_short_xfer = 0; 2099 /* one more data phase */ 2100 } else { 2101 new_status = USBD_NORMAL_COMPLETION; 2102 goto complete; 2103 } 2104 } 2105 motg_device_data_write(xfer); 2106 return; 2107 2108 complete: 2109 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2110 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2111 #ifdef DIAGNOSTIC 2112 if (xfer && xfer->ux_status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2113 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2114 #endif 2115 ep->phase = IDLE; 2116 ep->xfer = NULL; 2117 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2118 KASSERT(new_status != USBD_IN_PROGRESS); 2119 xfer->ux_status = new_status; 2120 usb_transfer_complete(xfer); 2121 } 2122 motg_device_data_start1(sc, ep); 2123 } 2124 2125 /* Abort a device control request. */ 2126 void 2127 motg_device_data_abort(struct usbd_xfer *xfer) 2128 { 2129 #ifdef DIAGNOSTIC 2130 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2131 #endif 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2135 2136 motg_device_xfer_abort(xfer); 2137 } 2138 2139 /* Close a device control pipe */ 2140 void 2141 motg_device_data_close(struct usbd_pipe *pipe) 2142 { 2143 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2144 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2145 struct motg_pipe *otgpipeiter; 2146 2147 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2148 2149 KASSERT(mutex_owned(&sc->sc_lock)); 2150 KASSERT(otgpipe->hw_ep->xfer == NULL || 2151 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2152 2153 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2154 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2155 if (otgpipeiter == otgpipe) { 2156 /* remove from list */ 2157 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2158 motg_pipe, ep_pipe_list); 2159 otgpipe->hw_ep->refcount--; 2160 /* we're done */ 2161 return; 2162 } 2163 } 2164 panic("motg_device_data_close: not found"); 2165 } 2166 2167 void 2168 motg_device_data_done(struct usbd_xfer *xfer) 2169 { 2170 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->ux_pipe; 2171 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2172 2173 KASSERT(otgpipe->hw_ep->xfer != xfer); 2174 } 2175 2176 /* 2177 * Wait here until controller claims to have an interrupt. 2178 * Then call motg_intr and return. Use timeout to avoid waiting 2179 * too long. 2180 * Only used during boot when interrupts are not enabled yet. 2181 */ 2182 void 2183 motg_waitintr(struct motg_softc *sc, struct usbd_xfer *xfer) 2184 { 2185 int timo = xfer->ux_timeout; 2186 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2187 2188 mutex_enter(&sc->sc_lock); 2189 2190 DPRINTF("timeout = %dms", timo, 0, 0, 0); 2191 2192 for (; timo >= 0; timo--) { 2193 mutex_exit(&sc->sc_lock); 2194 usb_delay_ms(&sc->sc_bus, 1); 2195 mutex_spin_enter(&sc->sc_intr_lock); 2196 motg_poll(&sc->sc_bus); 2197 mutex_spin_exit(&sc->sc_intr_lock); 2198 mutex_enter(&sc->sc_lock); 2199 if (xfer->ux_status != USBD_IN_PROGRESS) 2200 goto done; 2201 } 2202 2203 /* Timeout */ 2204 DPRINTF("timeout", 0, 0, 0, 0); 2205 panic("motg_waitintr: timeout"); 2206 /* XXX handle timeout ! */ 2207 2208 done: 2209 mutex_exit(&sc->sc_lock); 2210 } 2211 2212 void 2213 motg_device_clear_toggle(struct usbd_pipe *pipe) 2214 { 2215 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2216 otgpipe->nexttoggle = 0; 2217 } 2218 2219 /* Abort a device control request. */ 2220 static void 2221 motg_device_xfer_abort(struct usbd_xfer *xfer) 2222 { 2223 int wake; 2224 uint8_t csr; 2225 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2226 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->ux_pipe; 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 2229 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2230 2231 if (xfer->ux_hcflags & UXFER_ABORTING) { 2232 DPRINTF("already aborting", 0, 0, 0, 0); 2233 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2234 while (xfer->ux_hcflags & UXFER_ABORTING) 2235 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2236 return; 2237 } 2238 xfer->ux_hcflags |= UXFER_ABORTING; 2239 if (otgpipe->hw_ep->xfer == xfer) { 2240 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2241 otgpipe->hw_ep->xfer = NULL; 2242 if (otgpipe->hw_ep->ep_number > 0) { 2243 /* select endpoint */ 2244 UWRITE1(sc, MUSB2_REG_EPINDEX, 2245 otgpipe->hw_ep->ep_number); 2246 if (otgpipe->hw_ep->phase == DATA_OUT) { 2247 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2248 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2249 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2250 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2251 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2252 } 2253 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2254 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2255 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2256 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2257 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2258 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2259 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2260 } 2261 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2262 } 2263 otgpipe->hw_ep->phase = IDLE; 2264 } 2265 } 2266 xfer->ux_status = USBD_CANCELLED; /* make software ignore it */ 2267 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2268 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2269 usb_transfer_complete(xfer); 2270 if (wake) 2271 cv_broadcast(&xfer->ux_hccv); 2272 } 2273
Indexes created Mon Oct 13 08:09:50 GMT 2025